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Questions About Verilog Code Debugging An Design Verification

The document contains questions about a person's experience with logic IC design. It asks about tools used, typical workflows, debugging processes, verification processes, and potential benefits of automation or AI integration.

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BT21EC026 Siddharth Jha
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10 views2 pages

Questions About Verilog Code Debugging An Design Verification

The document contains questions about a person's experience with logic IC design. It asks about tools used, typical workflows, debugging processes, verification processes, and potential benefits of automation or AI integration.

Uploaded by

BT21EC026 Siddharth Jha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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PLEASE WRITE DOWN ALL ANSWERS for each question by yourself, be specific.

Note that using AI or ChatGPT to answer these questions is NOT ALLOWED and will
fail delivery.

Name:Siddharth Jha and have 2 Years of experience in logic IC design:

1. What logic IC design software/IDE do you use frequently and what is the RTL
language you use?

2. Using an example of a recently successfully completed logic ICs design project,


can you describe your typical workflow? What is the most time consuming part?

3. Please describe your RTL code debugging process. What are the specific
pain points in this process? What is the most time-consuming part?

4. In the test/verification process, What are the specific issues/pain points in


this process? What is the most time-consuming part?

5. Use an example to show how you can increase the efficiency of the
test/verification process?

6. Have you used any AI or machine learning integration with your logic IC design
tools before? If so, what was your experience (helpful or not)?

7. What features would you wish to see integrated into your logic IC design
software/IDE to make your tasks easier or more efficient?

8. Can you share an example where you felt your current logic IC design
software/IDE limited your ability to execute RTL code debugging or
test/verification process?

9. How important is collaboration in your RTL code debugging or


test/verification process, and what tools do you use to facilitate it?
10. Would you be willing to provide feedback on early versions of a language model-
augmented logic IC design software/IDE? What would be the best way to reach
you to do this?

11.Before RTL verification, do you usually (or asked to) prepare Test plan?
Are there any current tools you use to automatically generate Test Plans? If
a tool exists that can automatically generate Test Plans, would you find it
beneficial?

12.After RTL verification complete, do you usually (or asked to) prepare Test
reports? Are there any current tools you use to automatically generate Test
reports? If a tool exists that can automatically generate Test reports, would you
find it beneficial?

13.For RTL verification, are there any current tools you use to automatically
generate Test benches? If a tool exists that can automatically generate Test
benches, would you find it beneficial?

14.If a tool exists that can provide debugging suggestions, would you find it
beneficial?

15.If there is a service that is able to provide Test plan, Test bench code and
Test reported automatically while providing code debugging suggestion, would
you be willing to purchase it?

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