An Asynchronous Pipelined Time-to-Digital Converter Using

Time-Domain Subtraction
Omer Can Akgun
Section Bioelectronics, Department of Microelectronics, Delft University of Technology, the Netherlands
E-mail: [email protected]

Analog-to- Time-
Abstract—This paper presents the design of a low-power asynchronous Voltage / time Time domain Time Time-to-digital
current converter signal converter (TDC)
pipelined time-to-digital converter (AP-TDC) to be employed in a time- (ATC) processing
Digital
Digital-to-analog Voltage /
DSP converter (DAC)
domain signal processing system. The presented AP-TDC utilizes two Time-to- Time-
current
Voltage / analog Time domain Time Digital-to-time
novel concepts, namely time-domain subtraction and absolute value based current converter signal converter (DTC)
algorithmic conversion. The design and simulation of the AP-TDC is (ATC) processing

done using a standard CMOS 65 nm process. The least-significant-bit

resolution of the AP-TDC is designed to be 200 ps and the AP-TDC Figure 1. A hybrid time-domain signal processing chain.
outputs 7-bit digital words with an ENOB of 6.2 bits. The dynamic
range of the TDC is 25.4 ns and the TDC core consumes 38 µW from a as the signal processing is mostly event based [16] , e.g., the rising
supply voltage of 1 V and has a total area of 1275 µm2 . When compared edge and falling edges of a signal carrying the information to be
to a Flash TDC implementation using the same delay elements, power
consumption, total area, and conversion time are reduced by 28.3%, processed.
31.5%, and 24.6%, respectively. The AP-TDC has a figure-of-merit of The contributions and organization of this paper are as follows:
9.9-fJ/conversion step. First, a novel time-domain subtraction method is introduced in
Index Terms—asynchronous, time-to-digital converter, TDC, pipelined, Section II-A, as subtraction operation is a pre-requisite for pipelined
absolute value based conversion, time subtraction, completion detection
conversion. Second, an absolute value based, power and area effi-
cient pipelined value-to-digital conversion method suitable for asyn-
I. I NTRODUCTION chronous implementation with completion detection is presented in
With the scaling of the technology nodes, while the performance Section II-B. Combining absolute value based algorithmic conversion,
of the digital systems improve, the supply voltage, and thus, the time-domain subtraction and asynchronous operation, the design of
headroom available for analog signal processing scales down as an AP-TDC is presented in Section III. Simulation results are given
well. This imposes a strict limit on the analog signal processing in Section IV and finally conclusions are drawn in Section V.
capabilities. One solution to this problem is using time-domain
II. T IME D OMAIN S UBTRACTION AND C ONVERSION
signal processing (TDSP) techniques [1]–[4]. A hypothetical time-
domain/digital hybrid signal processing chain is shown in Figure 1. This section presents the ideas that are employed during the design
In such a system, in addition to signal processing circuitry, two main of the TDC. The first one is time-domain subtraction operation, and
blocks that are required to be able to communicate with a digital the second one is an algorithm for value-to-digital conversion using
environment are time-to-digital (TDC) and digital-to-time (DTC) the absolute value of a residue with completion detection.
converters.
A. Time Domain Subtraction Operation
A TDC resolves a time difference into a digital value. The time
difference can either be the difference between two separate signals, A pipelined TDC based on a binary-search algorithm (BS-TDC)
usually the start and the stop signals, or the time between the edges was introduced in [2]. The BS-TDC is based on employing binary
of a single signal. The result of the conversion is a digital word rep- weighted delay elements and operated by either delaying the input
resenting the time difference value, similar to the digital output word or control (clock) signal in the TDC by binary weighted amounts.
in analog-to-digital (AD) conversion. In addition to TDSP systems, Such an approach needs twice the number of binary weighted delay
TDCs find many applications in scientific experiments [5], such as elements and results in higher power consumption and a bigger chip
digital phase-locked-loop (DPLL) applications [6], and on-chip time area. Moreover, in [2] it was claimed that a time value cannot be
measurement and testing [7]. The simplest TDC implementation is subtracted from another one, hence the choice for parallel paths. In
based on a counter [1]. However, many TDCs employed today are this section it is shown that subtraction of a fixed time value from
based on simple delay lines and may be summarized as Flash TDCs an input pulse is possible and results in absolute value arithmetic.
[8], pipelined TDCs [9], [10], successive approximation TDCs [11]– The basic idea of time subtraction is that by delaying an input
[14], noise-shaping TDCs [15] and ∆ − Σ TDCs [5]. pulse by a certain amount (value to be subtracted), and XNORing
The main goal of the research work presented here is to develop the input signal with the delayed version of itself during a window
a low-power and small-area asynchronous pipelined TDC (AP-TDC) defined by the rising edge of the original signal and the falling edge
to be used in a hybrid signal processing chain as shown in Figure 1. of the delayed version, the operation
As multiple instances of a TDC may be used in such a system, a dOut = |dIn − d| (1)
pipelined architecture is chosen for both low power consumption and
small area properties while having moderate conversion speed. An is realized where dOut is the width of the resulting pulse, dIn is
asynchronous TDC implementation was chosen over a synchronous the pulse width of the input signal and d is the delay amount, i.e.,
one due to following advantages: i) lower power operation due to the value to be subtracted. Outside this time window, the pulses on
lack of a clocking signal, ii) faster average operating speed due to dOut are irrelevant. In a subtraction operation, there are three possible
the completion detection, and iii) better interface to TDSP system outcomes; a) positive, b) negative, and c) 0. The first two cases for

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 Positive outcome Negative outcome
Conversion of 6 Conversion of 9
Period of Period of 1 1
Interest Interest Stage Input, dIn
Delayed Input, dInD
Input Signal Result, dOut
2 Unit 5 Unit
t t
Delays Delayed Input Signal Delays 0 6 8 14 0 8 9 17

Result is +3 Result Result is -3 2 3 2 3 4

t t Stage Input, dIn
0 2 5 7 0 2 5 7
Delayed Input, dInD

Figure 2. Two example time subtraction operations: Positive outcome oper- Result, dOut

ation represents 5 − 2 = 3 and negative outcome time subtraction operation 6 12 8 12

t
8 13 9 14 11 13
t

represents 2 − 5 = −3.
Figure 3. 4-bit pipelined, time-domain conversion examples based on absolute
the time subtraction operation are illustrated in Figure 2, while the 0 valued residue and time subtraction. Conversion steps are numbered above
outcome case is omitted to be brief. each sub-figure.
In Figure 2 even though the pulse-width of the resulting pulses are
the same, it may be observed that the former pulse is generated by the C. Application of Time Subtraction to Time-to-Digital Conversion
AND logical operation and the second pulse is generated by a NOR In this sub-section, application of time-domain subtraction to
operation on the signals during the period of interest, representing the the absolute value based digital conversion is presented. Two 4-
positive and negative outcomes, respectively. Therefore, an XNOR bit conversions utilizing time-domain subtraction are presented in
operation, which is the union of AND and NOR operations, realizes Figure 3. The conversion steps are in order from top to bottom and
the absolute value of the result in a time subtraction operation on left to right. It should also be noted that the time axis on the figures
an input signal and a fixed delay amount. By monitoring the events is continuous for the duration of the conversion, i.e., the conversion
of AND and NOR operations during the period of interest, the sign steps overlap.
of the result is easily deduced. The sign of the result is used in the As presented in Section II-A, the residue (dOut) is generated
conversion algorithm which is explained in the next sub-section. by XNORing the input signal dIn with its delayed version, which
The third case, which is not shown, where the outcome is 0, i.e., is represented with dInD from now on, during a pre-defined time
no output pulse, occurs when the falling edge of the input signal window. In the figures, the red color represents a resolved value of
is aligned with the rising edge of the delayed signal, meaning the 0, and blue represents a resolved value of 1.
delay value matches the input pulse-width. From this observation, it During the current stage’s conversion, if the resolved bit of the
is concluded that when no signal is generated at the output of XNOR previous stage’s is 1, an event on the AND operation of dIn and
operation, and when no events are generated at the outputs of AND dInD will result in a resolved output bit of 1. An event on the
and NOR operations, the outcome of the time subtraction operation NOR operation of the same signals will result in an output bit of
is 0. 0. Likewise, if the output bit of the previous stage is 0, meaning
the residue’s sign is negative, the output bit according to the results
B. Absolute Value Based Algorithmic Conversion of AND and NOR operations is reversed, i.e., a 1 is output for an
In the proposed pipelined TDC architecture, a pulse value repre- event on NOR and a 0 is output for an event on AND. Regardless
senting the bit-weight of the stage is subtracted from the input signal of the output bit of the previous conversion, if neither NOR nor
and a new pulse signal representing the residue is generated, similar AND operations create an event, it is concluded that the final value
to a standard pipelined ADC [17], [18]. In a standard pipelined ADC, is being converted in the current step, an output bit of 1 is generated
amplification of the residue is required to keep the reference values and the overall conversion is finished, effectively realizing completion
and the input range for each stage fixed to reduce both the design detection.
overhead and verification efforts. However, no signal amplification
is required in the proposed TDC as the proposed architecture can III. P IPELINED A SYNCHRONOUS TDC
operate with changing reference and input range values without any The conversion algorithm presented in the previous section, and
overhead, as will be shown next. the implementation that is presented in this section improve the
The proposed algorithm is based on operating on the absolute value conversion algorithm and the design presented in [11]. The implemen-
and the sign bit of the residue generated. During each conversion step, tation in [11] is synchronous, and requires a clocking signal , which
for an N -bit accurate conversion, a value of 2N −k is subtracted from results in higher power consumption and chip area. The operation
the value to be converted, where k is the conversion step number, principle of the circuit depends on the matching of multiple delay
which varies from 1 to N , and the first step (k = 1) converts the most elements, causing problems in practical implementations. Another
significant bit (MSB). In this section bold-faced values represents disadvantage of the synchronous implementation is feed-forward and
the operation of the current stage and italic values belong to the feed-back signals between stages and complex timing requirements
preceding stage. During the conversion, the stage output bit is 1 if i) for correct operation. Furthermore, a custom clocked comparator is
the output bit of the previous stage is 1 and the sign of the residue required in the implementation possibly introducing metastability into
is positive, or ii) the stage output bit of the previous stage is 0 and the system. The aforementioned problems are solved by adopting
the residue of the current stage is negative, or iii) regardless of the an asynchronous compatible algorithm and by asynchronous system
result of the previous stage, if no residue is generated, i.e., result of implementation. Moreover, the employed algorithm realizes comple-
subtraction is 0, an output bit of 1 is generated. This last case, i.e., iii), tion detection during conversion, effectively increasing the conversion
is where a completion detection mechanism for the conversion can speed.
be implemented. All other conversion cases result in a stage output Based on the absolute value and time-domain subtraction based
bit of 0. conversion presented in Section II, an AP-TDC was designed using

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 0.6
Stage Delay Filter Signal
(2N-k Unit Delays) Generator
0.5
dInD

Generated pulse-width (ns)

dIn BitOut
Calculation
0.4
bitIn D Q
bitOut
D Q
Clk AND trigger 0.3
D Q
Clk
NOR trigger Conversion
Trigger completion 0.2
Generator
Completion
Detection
N Bit TDC dOut 0.1 Expected PW
(Residue)
th STG
k stage Data Out
XNOR-AND
Generator
0
-0.6 -0.4 -0.2 0 0.2 0.4 0.6
Time difference applied to the circuit (ns)
Figure 4. Block diagram of a stage of the designed asynchronous TDC.
Figure 6. Simulation results of both residue generator implementations.
a standard CMOS 65 nm process. Low-power high threshold voltage Output response is shown for varying input time differences between the
transistors were used for the delay elements and low-power standard falling edge of dIn and rising edge of dInD.
threshold voltage standard cells were used for the rest of the circuitry.
The delay elements are designed and characterized for 1V supply Table I
P ERFORMANCE COMPARISON OF RESIDUE GENERATOR
voltage operation. The architecture of the AP-TDC and implementa- IMPLEMENTATIONS .
tion details are as follows:
Implementation error @ dead zone range error @
A. Architecture lower end (ps) upper end
A block level diagram of a stage of the AP-TDC is shown in STG -8% -97,7 - 92 -7%
XNOR-AND 20% -72 - 112 -22%
Figure 4. In the figure, dIn represents the pulse to be converted, the
bitIn is the conversion result from the previous stage, bitOut is the
is basically the main limitation on the resolution of the TDC and
converted value, and dOut is the residue to the next stage. A stage
reducing the dead zone and getting an accurate residue signal pulse-
of the TDC consist of a delay element for delaying the input signal
width wise is of utmost importance for increasing the time resolution.
of the stage, a generator for the filter signal to mark the period of
To improve the performance of the residue generator, asynchronous
interest as shown in Figure 2, a trigger generator for keeping track
circuit design techniques were employed. The signal transition graph
of the events on AND and NOR operations, a residue generator for
(STG) of the implemented residue generator is shown in Figure 5(a).
creating the output for the next stage, stage output bit calculator and
The STG was synthesized and mapped to standard cell libraries using
completion detector. Except the delay element, all the circuitry is
Petrify [19]. When compared to a more straightforward XNOR-AND
the same for all the stages. Furthermore, three points that are not
implementation, STG based implementation has both better accuracy
illustrated in the figures should be noted: i) bitIn connection to the
and a more symmetric dead zone. The transistor level simulation
first stage is logic high as the value to be converted by the TDC is
results for varying input time differences is shown in Figure 6, and
positive, ii) when an input less than the LSB is applied, all the dOut
the dead zone and accuracy results at the edges of the dead zone
signals stay high in the system without switching to a low value.
are presented in Table I. It can be seen from the simulation results
Hence a completion circuit just for the case of input less than 1 LSB
that even though the STG implementation has a slightly longer dead
is also implemented and ORed with the completion signal generated
zone, the accuracy at the edges of the dead zone is much better and
by the stages, and iii) all the sub-blocks are designed to be reset on
the shape of the dead zone is more symmetric when compared to the
the falling edge of the reset signal.
XNOR-AND implementation.
B. Sub-Blocks and Implementation Details Delay elements: In the proposed TDC implementation, the LSB
Residue generator: The logical function of the residue generator is value of the TDC is limited and set by either the minimum value of
to create a residue signal employing an XNOR gate and filtering the the unit delay element or the width of the dead zone of the residue
generated residue with a filter signal so that when both inputs are low, generator, whichever is higher. Based on the simulation results of
an event is not created at the output. This filtering operation is easily the residue generator, the STG implementation has a dead zone of
realized by ANDing the output of an XNOR gate with the filter pulse. 189.7 ps. Therefore, realizing a delay element with a delay shorter
However, during the design of the residue generator, it was found that than this value is not feasible and the unit-delay element of the system
the pulse-width of the signal generated by XNORing dIn and dInD was designed to be 200 ps, as delays shorter than the dead zone
deviated from the expected value, resulting in errors in the generated width would not improve the resolution of the TDC. For ease of
residue. Furthermore, the time-period where the difference between implementation and presenting the system as a proof of concept, a
the edges of the signals dIn and dInD are small but existent, no CMOS buffer based unit delay element was designed, and binary
output pulse is generated, resulting in a dead zone. This dead zone weighted delay elements were created using the unit delay cell. Even
though the number of delay elements is similar to a standard Flash-
dIn+ TDC, if the delay elements are designed in an analog fashion, the
number of delay elements in the implementation is greatly reduced,
filter+ dInD+

dInD+ dOut+ dIn- dOut- dInD-

i.e. from 2N − 1 to N .
P1
dIn+
P2
dIn- dInD-
In addition to the absolute value of the delay elements designed, the
dIn- dOut+ dInD+ dOut- dInD-
variation of the delays of each stage with respect to process variations
filter-
is also important. As the variation of a delay element directly affects
(a) Residue generator (b) Filter
the output residue, low variation in the first stages of the pipeline
Figure 5. Signal transition graphs of the synthesized asynchronous circuits is required. For example, for an N-bit AP-TDC, the delay variation

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 0
nd
2 Harmonic
7 8 10 12 14 337.6 kHz, -25.6 dB
dIn -10

Power Spectral Density (dB)

rd
3 Harmonic
-20 506.46 kHz, -22.7 dB

7 4 6 5 6 Completion
-30
[4-7]

-40

dOut[1] -50

dOut[2]
-60
dOut[3]
-70
dOut[4] 0 1 2 3 4 5 6 7 8
dOut[5]
Frequency (MHz)

dOut[6]
Figure 8. Power spectral density of the AP-TDC.
4.85 4.90 4.95 5.00 5.05 5.10 5.15
Time (us)
in the bottom panel of the figure. From the simulation results it is
Figure 7. Transient simulation results of the AP-TDC. The panels from the calculated that, the AP-TDC completes the conversion process 24.6%
top to the bottom are: Input data to the AP-TDC, completion signals for stages faster using the proposed algorithm with completion detection, as
4 to 7, and residues generated by each stage. compared to a conventional Flash TDC.
The performance of the TDC was evaluated with respect to both
of the kth stage should be less than a certain amount such that the static metrics such as differential non-linearity (DNL) and integral
delay is N − k + 1 bit accurate and the following stage’s resolution non-linearity (INL) and dynamic metrics such as signal-to-noise ratio
is not reduced. The effects of process variation on the delay elements through transient simulations. For the static case, INL and DNL were
were simulated using 1000 point Monte Carlo simulations and it calculated using the histogram method. The pulse-width of the input
was verified that the designed delay elements satisfy the accuracy signal to the TDC was increased by 1 ps during each conversion cycle
requirements under 1-σ delay variation. and the converted value was sampled with the completion signal.
Filter signal generator: The filtering signal, which shows the AP-TDC DNL varies between 0.43 and −0.77 LSB, and INL varies
period of interest in Figure 2, is a pulse signal that marks the time between −0.05 and −2.11 LSB.
slot between the rising edge of the input signal and the falling edge The dynamic performance was evaluated using a signal with
of the delayed input signal. Such a circuit is easily implemented by varying pulse-widths based on a sampled sine wave. The sampling
the design of an STG and synthesizing the circuit using Petrify. The frequency and the sine wave frequency was set to 16.66 MHz and
STG of the designed circuit is shown in Figure 5(b). The resulting 168.82 kHz, respectively. The converted digital word was sampled
filter signal is ANDed with the generated residue to create the dOut with each completion signal. A 8192-point FFT was applied to the
signal that is fed into the subsequent stage. recorded data and power spectral density was calculated, as plotted in
Trigger Generator: This block is used for keeping track of firing Figure 8. Dynamic simulation results show an SNR of 39.2 dB, and
of either the AND or the NOR gate that provides the information an effective accuracy of 6.22 bits. Based on the layout generated,
whether dIn and dInD signals are overlapping or not. The imple- the AP-TDC has a total area of 1275 µm2 , of which half of it is
mentation is shown in Figure 4. D-type flip-flops are triggered by a the area due to delay elements. While operating from a 1 V supply
rising edge on their clock input and the D inputs of the flip-flops are voltage, the TDC consumes 38µA. For comparison, a 7-bit flash
connected to logic high, effectively storing the event that triggered. TDC implemented in the same technology using the same unit-
BitOut Calculator: The output bit of the stage is calculated and delay element has a total area of 1862 µm2 , and has a current
stored in a D-latch. The D-latch is enabled by the filter signal, hence consumption of 53 µA, both numbers excluding the thermometer to
following the generated value throughout the period of interest, and binary converter of the Flash TDC. Based on the figure-of-merit
storing the value with the falling edge of the filter signal. (FOM) defined in [6], the AP-TDC has a FOM of 9.9-fJ/conversion
Completion Detector: The completion signal is generated when step.
neither AND nor NOR events are triggered during a conversion. This
block is triggered when both edges are in the dead zone of the residue V. C ONCLUSIONS
generator, meaning the time difference between the edges is less than This paper presents the design of an asynchronous pipelined
the resolution of the TDC, hence signaling the completion of the TDC. An absolute value based conversion algorithm is modified
overall conversion process. to include completion detection and later converted to a form that
employs time-domain subtraction and is suitable for asynchronous
IV. S IMULATION R ESULTS implementation. AP-TDC design, when compared to a Flash TDC
The proposed 7-bit asynchronous pipelined TDC has been designed design using the same delay elements, reduces the total area and
in a standard 65 nm process using low-power and standard threshold power consumption by 31.5% and 28.3%, respectively. Furthermore,
voltage process options for a 1 V supply. Transistor level simulations the conversion process is 24.6% faster owing to completion detection.
were run using HSPICE and a transient simulation of the TDC Further power and area reduction may be possible by implementing
is shown in Figure 7. During the presented simulation window, 5 the delay elements in an analog fashion.
distinct values, which are shown on the top panel, are converted. It
is easily observed that completion signals are generated by different ACKNOWLEDGEMENT
stages during the conversion process. In the middle panel, the stages This project has received funding from the European Union’s
generating the completion signal are marked, 7 being the LSB stage. Horizon 2020 research and innovation programme under the Marie
Furthermore, generated residues throughout the pipeline are shown Sklodowska-Curie grant agreement No. 752819.

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