International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 13 (2017) pp.

4029-4034
© Research India Publications. http://www.ripublication.com

Low Voltage Low Power Folded Cascode OTA Design For RF Applications

Sawssen Lahiani, Houda Daoud, Samir Ben Selem and Mourad Loulou

Electronic and Communications Group, LETI-laboratory,

National School of Engineers of Sfax, Sfax University, Tunisia.

Abstract The OTA should provide sufficient transconductance gain with

acceptable linearity and power consumption. Moreover, a
This paper deals with the design of a folded cascode
proper phase margin which guarantees the stability is needed.
operational transconductance amplifier (OTA) intended to be
Also, the common mode rejection ratio (CMRR) and the
used for low power and wide band radio frequency (RF)
power supply rejection ratio (PSRR) represent two important
applications. First, a detailed description of the OTA topology
specifications of an OTA. Therefore, there are some tradeoffs
is done in order to optimize the MOS transistor sizing.
between bandwidth, phase margin, CMRR, PSRR, gain,
Second, the folded cascode OTA, which works for
linearity and power consumption when designing the OTA
frequencies that lead to a base band circuit design used for RF
design.
application, is optimized using the transistor sizing
methodology. Simulation results are performed using Operational transconductance amplifiers are very useful
Advanced Design System tool with 0.18μm CMOS process. building blocks in analog integrated circuits with an wide
The designed folded cascode OTA has a 73 dB DC gain and range of applications like continuous-time filters, data
provides a gain bandwidth product of around 2.3 GHz. The converters, variable gain amplifiers and tunable signal
input-referred in-band noise density (IRN) is 2.6nV2/Hz and generators [8, 9] etc. Very often the transconductance
the output-referred noise (ORN) of 6.2 nV2/Hz. The designed amplifiers are characterized in terms of achievable linearity
circuit consumes only 0.5 mW under a 1.8V supply voltage. over a significant input range along with low noise and
Based on the optimized circuit, we have implemented a current consumption.
second order Gm-C filter. The simulation results indicate that
Our target was to design a folded cascode OTA circuit and its
this filter achieves a Band pass of 737 MHz.
application in GM-C filter for wide band radio applications.
Keywords: Folded cascode OTA, low power, optimization,
This paper is organized as follows. The operation of the folded
Heuristic Algorithm, wide band RF application, secGm-C
cascode OTA architecture was introduced in section II where
filter.
the characterization of the OTA circuit is detailed. The
optimization strategy is presented in Section III together with
optimized characteristics for the OTAs. Simulation results are
INTRODUCTION
reported in section IV. In section V, we have implemented a
Nowadays, due to the increasing demand of system on chip Gm-C low-pass filter. Finally, the conclusion drawn from this
(SoC) productions, high performance analog integrated circuit work and possible future works are presented in Section VI.
design such as operational transconductance amplifier (OTA)
in CMOS technology becomes a big challenge. The OTA
circuit is well known for its high bandwidth in open-loop THE FOLDED CASCODE OTA ARCHITECTURE
configuration [1], which makes it proper for widespread
application such as Bluetooth, Global System for Mobile A. PMOS Input Transistor
(GSM) Communication, Wide Band Code Division Multiple Depending on system needs, OTA circuit with a wide
Access (WCDMA), Ultra Wide Band (UWB) are used in differential input range and good Gm is highly desired. For this
multimode transceiver. reason, the PMOS transistor has been chosen. For comparable
In the literature, we show that the OTA is one of the most device dimensions and bias currents, the NMOS input
important building blocks in many analog circuit applications, differential pair provides larger gain than a PMOS pair. But,
such as including multipliers [2,3], continuous-time - filters PMOS transistors input pair was used in the FC OTA in order
[4, 5], voltage-controlled oscillators (VCOs) [6] and to achieve a maximum gain and a low noise [10]. In this paper,
continuous time sigma-delta modulators [7]. This block an optimized OTA is presented to improve input dynamic
converts input voltage to output current with a linear range which operates at a low supply voltage with reduced
transformation factor. power consumption.

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B. Architecture Analysis D. Noise Analysis

Vdd
E. There are two main types of noise that transistors
contribute to the total circuit. They are the flicker, or 1/f
M13 M14
M1 M2 M11 noise and the thermal noise. Their effect must be
minimized. In the following noise analysis, the noise
contribution from the cascode transistors is neglected
when compared to cascaded transistors.
M3 M4 M12
The input referred thermal noise voltage of the FC OTA can
Vin + Vin - Vout + Vout- be expressed as,
M9 M 10
IB
M5 M6 2 2g m9,10 2g m7,8
IB CL Vin,th 2  4KT(2 2 2 ) (4)
V1
3g m9,10 3g m9,10 3g 2 m9,10

M7 M8
Where K is the Boltzmann’s constant and T is the
V2
temperature. gm7 is the transconductance of M7 transistor. The
input referred flicker noise voltage of the FC OTA can be
Vss
written as:
Figure 1: Folded cascode OTA circuit KF KF g m1,22 KF g m7,82
Vin,1/f 2 = 2 +2 +2
Cox  WL 1,2 f Cox  WL 7,8 f g 2 Cox  WL 7,8 f g 2
m9,10 m9,10 (5)
The FC OTA has a differential stage consisting of PMOS
transistors M9 and M10. M11 and M12 devices provide
Where KF is the flicker noise coefficient of NMOS and PMOS
respectively the DC bias voltages to M1, M2, M3 and M4
transistors, f is the frequency and Cox is the oxide capacitance.
transistors.
W and L are the transistors sizes. gm defines the
The open-loop voltage gain and the dominant pole are given by
transconductance of transistors differential pair.
equations (1) and (2),
(1)
g m3 1 g 1 THE FOLDED CASCODE OTA OPTIMIZATION
A v  g m9 ( . // m5 . ) In order to optimally size each component forming the OTA
g ds1 g ds3 g ds5 g ds7  g ds9
when satisfying constraints and performance functions, we
developed an algorithm that allows automating the task [11].
1 (2)
fdp  This algorithm was programmed using C++ software. It is
g m3 1 1 g m5
2π( . // . )C based on the flow chart given by figure 2. It describes an
gds1 gds3 gds5 gds7  gds9 L
optimization tool based on Heuristic algorithm. The first step
in the optimization is the expression of the different criteria by
a technology dependent model. For accurate modeling, a small
Where, gds1, gds3, gds5, gds7 and gds9 are respectively the signal analysis of the OTA is carried out to explicit the
conductances of M1, M3, M5, M7 and M9 transistors. gm3, gm5 different characteristics intended optimized. From the OTA
and gm9 are respectively the transconductances of M3, M5 and structure presented in Figure 2, we opted in this step for the
M9 devices and CL is the capacitance at the output node. TSMC CMOS 0.18μm process.

C. Gain-Bandwidth A. Optimization Algorithm

The gain bandwidth of the folded cascade OTA proposed The heuristic method allows solving an optimization problem.
given by (3): The optimization strategy is shown in Fig.2. First, we fix the
g parameters to optimize and their ranges of variations. Second,
m9 I D
GBW = (3) we generate random variables vectors and we check the
I D CL
preliminary conditions. The computation of the objective
Where gm9 is the transconductance of transistor M9. ID is the function to minimize or to maximize yields to optimal values
bias current flowing in Mosfets M4, M6, and M9. The gain of width and length of devices used, also the optimal bias
bandwidth is normally much larger than the required, for low current is attained.
bandwidth applications.

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© Research India Publications. http://www.ripublication.com

B. Folded Cascade OTA Optimization The proposed OT A cell is simulated using the Advanced
Design System (ADS) tool with TSMC 0.18µm CMOS
We used in the OTA optimization the following series of process parameters under 1.8V power supply. The NMOS and
criteria: the PMOS transistor threshold voltages are respectively 0.436
 The gain Av is maximized. V and -0.438 V. The optimized value of bias current is set to
 The dominant frequency (f-3db) is maximized. 50 μA. Current sources are implemented using cascode current
mirrors.
 The input referred noise (Vin,th) is minimized.
 The power consumption (power) is minimized.
OTA CIRCUIT SIMULATIONS
 The silicon area is minimized.
The designed folded cascode OTA has a gain of 73.57dB, a
The objective function to maximize can thus be formulated as
large unity-gain frequency of 2.3GHz (Fig.3). Fig.4 presents
follows:
the phase margin of 52degrees.
a3 a4 a5
F = a1A v + a 2f-3dB + + +
Vin,th 2 power Wi Li (6)
m3
freq=2.282GHz
Where a1-5 are the positive coefficients used for normalization. dB((Vout1-Vout2)/(Vin1-Vin2))=0.003

The first step in the optimization is the expression of the m1

freq=100.0kHz
different criteria by a technology dependent model. dB((Vout1-Vout2)/(Vin1-Vin2))=73.570
80m1

dB((Vout1-Vout2)/(Vin1-Vin2))
Initialisation of the 60
parameters’
vectors 40

20

Random choice of
m3
Verification of the 0
preliminary the vector
conditions variables
-20

-40

No -60
Calculs of the
Correction objective function 1E5 1E6 1E7 1E8 1E9 1E10

freq, Hz
Yes

« optimal » Figure 3: Gain curve of the optimized OTA

dimension

No
ADS simulation m4
freq=2.272GHz
Yes phase((Vout1-Vout2)/(Vin1-Vin2))=-128.0 deg
phase((Vout1-Vout2)/(Vin1-Vin2)), deg

0
Optimazed
structure

-50

Figure 2: Optimization Algorithm flow chart

-100
m4
After several iterations, many valid vectors test were obtained.
The transistors sizing of the OTA circuit are planned in table I. -150

Table I. Transistors Sizing -200

1E3 1E4 1E5 1E6 1E7 1E8 1E9 1E10
OTA circuit
freq, Hz
Device Name Values (µm)
M1,2,3,4, 11,12, 13 1
Figure 4: Phase curve of the optimized OTA
M5,6, 7,8 5
M9,10 20
M14 15 Fig.5 shows that the input referred noise (IRN) value of the
Simulation Conditions proposed OTA over the 1-3GHz frequency band. The OTA
IB [5, 50] µA input referred noise is around 2.6nV2/Hz. Fig.6 depicts the
V1 [-0.9, 0.9] V output referred noise (ORN) value of the proposed OTA over
V2 [-0.9, 0.9] V the 1-3GHz frequency. The OTA output referred noise is
around 6.23nV2/Hz.
CL 0.1pF

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© Research India Publications. http://www.ripublication.com

80
Supply Voltage 2 1.8 -- 1.8
70
Power consumption -- 0.45 1.2 0.5
60
(mW)
Vin1.noise, nV

50
CMOS Process (µm) 0.35 0.18 0.18 0.18
40

30 m1 FOM -- -- -- 2052
freq=2.282GHz (dB.MHz/V.mW)
20 Vin1.noise=2.611nV
10
m1
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
APPLICATION
freq, GHz
The overall performance of a wireless device greatly depends
Figure 5: Input-referred noise curve on the performance of its transceiver [16-19]. RF filters are
the essential components of all wireless transceiver front ends
as shown in fig. 7. To design band pass filter with high quality
160
factor, inductors play an important role [20]. Higher cost that
140
came from large size of silicon area to entertain on-chip
120
passive spiral inductors is one of the prime disadvantages.
Vout1.noise, nV

100
Another disadvantage of on-chip spiral inductor is its
80 deficiency of tuning ability which makes the design a little bit
60 complicated [21]. As a result the usage of on-chip spiral
m2
40 freq=2.282GHz inductors is decreasing day by day for high frequency
Vout1.noise=6.234nV
20 applications [22].
m2
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0

freq, GHz

Figure 6: Output-referred noise curve

A comparative study of the optimized OTA with other works

published is depicted in Table II.
After discussing the different performance of the designed
OTA, we can evaluate our study toward other works. It is
clearly seen that with folded cascode OTA architecture, we can
reach a low power low voltage topology with high unity gain Figure 7: RF filter at the transceiver front end
frequency.
To evaluate this work a figure of merit (FOM) can be defined Fully integrated continuous-time transconductance-C (Gm-C)
as [12]: filters have been widely used for high frequency applications
such as digital video, RF/IF filters, etc. Gm-C filters offer
Gain(GBW) (7)
FOM = many advantages in terms of low power and high frequency
(PowerSupply)(PowerConsumption)
capability.
A Gm-C filter is a kind of the continuous time filter which
needs the operational transconductance amplifier (OTA) to be
Table II: Comparison with recent works
a basic building block. Gm-C filters are popular for on-chip
Parameters [13] [14] [15] This applications due to their advantages of high frequency
work performance and low power consumption, but have linearity
DC Gain (dB) 85 -- 84.33 73.57 problems. In order to overcome the disadvantage of linearity
of Gm-C filters, many linearization techniques for
Unity-gain frequency 0.23 5 0.54 2.28
transconductors have been reported such as resistive source
(GHz)
degeneration, dynamic source Degeneration, tunable
Phase Margin (degree) 46 -- 51.34 52 feedback, combination of dynamic source degeneration and
IRN (µV2/ Hz) 1.6 28 -- 0.002 tunable feedback, transconductor with bias feedback etc.
ORN (µV2/ Hz) 35 -- -- 0.006 Besides the non-ideality of the transconductors causes
excessive phase shift and inherently limits the upper

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© Research India Publications. http://www.ripublication.com

operational frequencies, which restricts this type of filter from this large cutoff frequency, the Gm-C filter can operate in RF
being used in gigahertz frequencies. application and modern communication receivers. This filter
is able to re-configure the bandwidth, gain or linearity in order
In our case and to demonstrate the feasibility and the
to fulfill the requirements of different standards subjecting to
performance of folded cascode OTA, we simulated several
wireless standards.
applications. We have treated current mode and voltage mode
filters. Recently, analog filters design using Gm-C integrators
10
has acquired a great popularity. Tranconductance cells are

dB((Vout1-Vout2)/(Vin1-Vin2))
relatively simple circuits which allow to operate for high 0 m1
frequencies. -10
m1
freq=737.1MHz
The reason behind the selection of Gm-C concept is that the -20
dB((Vout1-Vout2)/(Vin1-Vin2))=-3.003
easy tuning capability by varying the Gm value of the
transconductors. Also the Gm-C filter has a low noise floor but -30

the ability to handle large signals is limited. In order to archive -40

the required value in terms of linearity, the Gm which depends
-50
on the width, the length and the bias current of the CMOS 1E3 1E4 1E5 1E6 1E7 1E8 1E9 1E10
transistor, has to be chosen carefully. The fully differential freq, Hz
circuit block is shown in fig. 8.

Fig. 9. Simulation result of 2nd order Gm-C low pass filter

circuit
C1 Vout+
C2

Vin+
+ +
gm1
+
gm2
+ +
gm3
+ + + CONCLUSION
gm4
Vin-
- - - - - - - - In this paper, a design of folded cascode OTA circuit has been
C1 C2 Vout- reported. The approach of optimization OTA design has been
used to improve the gain, the unity gain frequency, the input
referred noise and the power consumption. Simulation results
Figure 8: 2nd order Gm-C low pass filter circuit prove the effectiveness of this optimization approach which is
a time consuming method. The optimized topology achieves a
The basic Gm-C filter, consisting of a capacitor and a good input range with a high DC gain of 73.57dB and a large
transconductance, is shown in Fig. 8 and the transfer function bandwidth. It consumes only 0.5 mW under 1.8V supply
of is given by [13]: voltage. Based on this circuit, we have implemented a Gm-C
low-pass filter where the cutoff frequency is 737MHz.
g m2 .g m3.g m4
Vout g m4
H(S )  = REFERENCES
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