Visvesvaraya Technological University

Belagavi, Karnataka, 590018

Lab Report on
“Electronics Circuits with Verilog Lab”

Submitted in partial fulfillment of the requirements for the award of

Bachelor of Engineering
in
Computer Science and Engineering

Submitted by

Samarth Kamat
(2JR21CS079)

Subject Code: 21EC654

Jain College of Engineering & Research, Belagavi

Department of Computer Science and Engineering
Academic Year 2023 - 2024
 Jain College of Engineering & Research, Belagavi
(Approved by AICTE, New Delhi, Affiliated to VTU Belagavi & Recognized by Govt. of Karnataka)

Department of Computer Science and Engineering

CERTIFICATE

It is certified that, the Seminar Report for “Electronics Circuits With Verilog Lab” is a
bonafide work satisfactorily completed by Samarth Kamat(2JR21CS079), in partial fulfilment
for the award of Bachelor of Engineering degree in Computer Science and Engineering of the
Visvesvaraya Technological University, Belagavi during the year 2023-2024.

Lab In-charge HOD

(Dr. Pritam Dhumale) (Dr. Pritam Dhumale)
CONTENTS
1. Introduction

2. Verilog code and testbench

3.Output
 CONTENTS

TITLE DATE PAGE NUMBER

Introduction 07/05/2024

1-6
Experiment no 1 11/05/2024

Verilog code for all types of gates

Experiment no 2 25/05/2024 7-9

Verilog code for adder and subtractor

Experiment no 3 08/06/2024 10-11

Verilog code for multiplexer

Experiment no 4 22/06/2024 12
Verilog code for decoder(2:4 decoder)

Experiment no 5 29/06/2024 13
Verilog code for 4 bit ripple carry adder

Experiment no 6 13/07/2024 14-19

Verilog code for latches and flip flops 27/07/2024

i
 INTRODUCTION

Verilog is a Hardware Description Language; a textual format for describing electronic

circuits and systems. Applied to electronic design, Verilog is intended to be used for
verification through simulation, for timing analysis, for test analysis

Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). It is a language used for

describing a digital system like a network switch or a microprocessor or a memory or a
flip−flop. It means, by using a HDL we can describe any digital hardware at any level.
Designs, which are described in HDL are independent of technology, very easy for
designing and debugging, and are normally more useful than schematics, particularly for
large circuits.

Verilog supports a design at many levels of abstraction. The major three are −

 Behavioral level
 Register-transfer level
 Gate level

Verilog was developed to simplify the process and make the HDL more robust and flexible.
Today, Verilog is the most popular HDL used and practiced throughout the semiconductor
industry.

HDL was developed to enhance the design process by allowing engineers to describe the
desired hardware's functionality and let automation tools convert that behavior into
actual hardware elements like combinational gates and sequential logic.

ii
Experiment no 1

Verilog code for all types of gates

 AND Gate

Verilog Code Testbench Code

module and_gate(a,b,y); module testbench;
input a,b; reg A,B;
output y; wire Y;
and (y,a,b); and_gate UUT(A,B,Y);
endmodule initial begin
$dumpfile("dump.vcd"); $dumpvars;
$monitor($time,"A=%b,B=%b,Y=%b",A,B,Y);
A=0;B=0;
#5 A=0;B=1;
#5 A=1;B=0;
#5 A=1;B=1;
end
endmodule

Output:

1
  NAND Gate

Verilog Code Testbench Code

module nand_gate(a,b,y); module testbench;
input a,b; reg A,B;
output y; wire Y;
nand_gate UUT(A,B,Y);
nand (y,a,b);
initial begin
endmodule $dumpfile("dump.vcd"); $dumpvars;
$monitor($time,"A=%b,B=%b,Y=%b",A,B,Y);
A=0;B=0;
#5 A=0;B=1;
#5 A=1;B=0;
#5 A=1;B=1;
end
endmodule

Output:

2
  OR Gate

Verilog Code Testbench Code

module or_gate(a,b,y); module testbench;
input a,b; reg A,B;
output y; wire Y;
or_gate UUT(A,B,Y);
or (y,a,b);
initial begin
endmodule $dumpfile("dump.vcd"); $dumpvars;
$monitor($time,"A=%b,B=%b,Y=%b",A,B,Y);
A=0;B=0;
#5 A=0;B=1;
#5 A=1;B=0;
#5 A=1;B=1;
end
endmodule

Output:

3
  NOR Gate

Verilog Code Testbench Code

module nor_gate(a,b,y); module testbench;
input a,b; reg A,B;
output y; wire Y;
nor_gate UUT(A,B,Y);
nor (y,a,b);
initial begin
endmodule $dumpfile("dump.vcd"); $dumpvars;
$monitor($time,"A=%b,B=%b,Y=%b",A,B,Y);
A=0;B=0;
#5 A=0;B=1;
#5 A=1;B=0;
#5 A=1;B=1;
end
endmodule

Output:

4
  XOR Gate

Verilog Code Testbench Code

module xor_gate(a,b,y); module testbench;
input a,b; reg A,B;
output y; wire Y;
xor_gate UUT(A,B,Y);
xor (y,a,b);
initial begin
endmodule $dumpfile("dump.vcd"); $dumpvars;
$monitor($time,"A=%b,B=%b,Y=%b",A,B,Y);
A=0;B=0;
#5 A=0;B=1;
#5 A=1;B=0;
#5 A=1;B=1;
end
endmodule

Output:

5
  XNOR Gate

Verilog Code Testbench Code

module xnor_gate(a,b,y); module testbench;
input a,b; reg A,B;
output y; wire Y;
xnor_gate UUT(A,B,Y);
xnor (y,a,b);
initial begin
endmodule $dumpfile("dump.vcd"); $dumpvars;
$monitor($time,"A=%b,B=%b,Y=%b",A,B,Y);
A=0;B=0;
#5 A=0;B=1;
#5 A=1;B=0;
#5 A=1;B=1;
end
endmodule

Output:

6
Experiment no 2

Verilog code for adder and subtractor

 Half Adder

Verilog Code Testbench Code

module module testbench;
HA(a,b,sum,carry); reg A,B;
input a,b; wire S,C;
HA UUT(A,B,S,C);
output sum,carry;
initial begin
assign sum= a^b; $dumpfile("dump.vcd"); $dumpvars;
assign carry=a & b;
endmodule $monitor($time,"A=%b,B=%b,S=%b,C=%b",A,B,S,C);
A=0;B=0;
#5 A=0;B=1;
#5 A=1;B=0;
#5 A=1;B=1;
#5 $finish();
end
endmodule

Output:

7
  Full Adder

Verilog Code Testbench Code

module module testbench;
FA(a,b,c,sum,carry); reg A,B,C;
input a,b,c; wire S,Co;
FA UUT(A,B,C,S,Co);
output sum,carry;
initial begin
assign sum= a^b^c; $dumpfile("dump.vcd"); $dumpvars;
assign carry=(a&b)|(b&c)|
(a&c); $monitor($time,"A=%b,B=%b,C=%b,S=%b,Co=%b"
endmodule ,A,B,C,S,Co);
A=0;B=0;C=0;
#5 A=0;B=0;C=1;
#5 A=0;B=1;C=0;
#5 A=0;B=1;C=1;
#5 A=1;B=0;C=0;
#5 A=1;B=0;C=1;
#5 A=1;B=1;C=0;
#5 A=1;B=1;C=1;
#5 $finish();
end
endmodule

Output:

8
  Full Subtractor

Verilog Code Testbench Code

module module testbench;
FS(a,b,c,diff,borr); reg A,B,C;
input a,b,c; wire D,Bo;
FS UUT(A,B,C,D,Bo);
output diff,borr;
initial begin
assign diff= $dumpfile("dump.vcd"); $dumpvars;
a^b^c; $monitor($time,"A=%b,B=%b,C=%b,D=%b,Bo=%b"
assign borr = ~a ,A,B,C,D,Bo);
& (b^c) | b & c; A=0;B=0;C=0;
endmodule #5 A=0;B=0;C=1;
#5 A=0;B=1;C=0;
#5 A=0;B=1;C=1;
#5 A=1;B=0;C=0;
#5 A=1;B=0;C=1;
#5 A=1;B=1;C=0;
#5 A=1;B=1;C=1;
#5 $finish();
end
endmodule

Output:

9
Experiment no 3

Verilog code for multiplexer

 2:1 Multiplexer

Verilog Code Testbench Code

module mux_2_1(a,b,s,y); module mux_tb;
input a,b,s; reg a,b,s;
output y; wire y;
mux_2_1 uut(a,b,s,y);
assign y = s?b:a;
initial begin $dumpfile("dump.vcd");
endmodule $dumpvars;
s = 0; a = 1; b = 0;
#10 a = 0; b = 1;
#10 s = 1; a = 1; b = 0;
#10 a = 0; b = 1;
#10 $finish();
end
endmodule

Output:

10
  4:1 Multiplexer

Verilog Code Testbench Code

module mux_4x1_b( module mux_tb;
input I0,I1,I2,I3,S0,S1, reg I0,I1,I2,I3,S0,S1;
output Y); wire Y;
mux_4x1_b uut(I0,I1,I2,I3,S0,S1,Y);
assign Y = S0?(S1?I3:I2):(S1?I1:I0);
initial begin $dumpfile("dump.vcd");
endmodule $dumpvars;
I0 = 1; I1 = 0;I2 = 1; I3 = 0;S0 = 0;S1=0;
#10 S0 = 0;S1=1;
#10 S0 = 1;S1=0;
#10 S0 = 1;S1=1;
#10 $finish();
end
endmodule

Output:

11
Experiment no 4

Verilog code for decoder (2:4 decoder)

 2:4 Decoder

Verilog Code Testbench Code

module decoder24_assign(en,a,b,y); module tb;
input en,a,b; reg a,b,en;
output [3:0]y; wire [3:0]y;
decoder24_assign uut(en,a,b,y);
wire enb,na,nb;
initial
assign enb = ~en; begin $dumpfile("dump.vcd");
assign na = ~a; $dumpvars;
assign nb = ~b; $monitor("en=%b a=%b b=%b
assign y[0] = (enb&na&nb); y=%b",en,a,b,y);
assign y[1] = (enb&na&b); en=0;a=0;b=0;#5
assign y[2] = (enb&a&nb); en=0;a=0;b=1;#5
en=0;a=1;b=0;#5
assign y[3] = (enb&a&b);
en=0;a=1;b=1;#5
endmodule $finish;
end
endmodule

Output:

12
Experiment no 5

Verilog code for 4-bit ripple carry adder

 4-bit ripple carry adder

Verilog Code Testbench Code

module rca(a,b,cin,sum,c4); module rca_tb;
input [3:0]a,b; reg [3:0]a,b;
input cin; reg cin;
wire [3:0]sum;
output [3:0]sum,c4;
wire c4;
wire c1,c2,c3; rca uut(a,b,cin,sum,c4);
full_adder initial begin $dumpfile("dump.vcd");
fa0(a[0],b[0],cin,sum[0],c1); $dumpvars;
full_adder fa1(a[1],b[1],c1,sum[1],c2); cin = 0; a = 4'b0110; b = 4'b1100;
full_adder fa2(a[2],b[2],c2,sum[2],c3); #10 a = 4'b1110; b = 4'b1000;
full_adder fa3(a[3],b[3],c3,sum[3],c4); #10 a = 4'b0111; b = 4'b1110;
#10 a = 4'b0010; b = 4'b1001;
endmodule
#10 $finish();
end
module full_adder( endmodule
input a,b,cin,
output sum,carry);
assign sum = a ^ b ^ cin;
assign carry = (a & b)|(b & cin)|(cin &
a);
endmodule

Output:

13
Experiment no 6

Verilog code for latches and flip flops

 S-R Latch

Verilog Code Testbench Code

module S_R_latch(s,r,q,qb); module tb();
input s,r; reg s,r;
inout q,qb; wire q,qb;
S_R_latch uut(s,r,q,qb);
nor (q,s,qb);
initial begin $dumpfile("dump.vcd"); $dumpvars;
nor (qb,r,q);
endmodule $monitor($time,"s=%b,r=%b,q=%b,qb=%b",s,r,q,qb);
s=0;r=0;
#5 s=0;r=1;
#5 s=1;r=0;
#5 s=1;r=1;
#5 $finish();
end
endmodule

Output:

14
  D Latch

Verilog Code Testbench Code

module D_latch(d,q,qb); module tb();
input d; reg d;
inout q,qb; wire q,qb;
D_latch uut(d,q,qb);
wire db;
initial begin $dumpfile("dump.vcd");
not (db,d); $dumpvars;
nor (q,d,qb);
nor (qb,db,q); $monitor($time,"d=%b,q=%b,qb=%b",d,q,qb);
endmodule d=0;
#50 d=1;
#50 $finish();
end
endmodule

Output:

15
  D Flip Flop

Verilog Code Testbench Code

module dff_gate(q, module tb();
qbar, d, clk); reg d,clk;
input d,clk; wire q, qbar;
dff_gate uut(q, qbar, d, clk);
inout q, qbar;
initial begin
clk = 0;
wire nand1_out; forever #5 clk = ~clk;
wire nand2_out; end
wire db;
not (db,d); initial begin $dumpfile("dump.vcd"); $dumpvars;
nand
$monitor($time,"d=%b,clk=%b,q=%b,qbar=%b",d,clk,q,qbar);
(nand1_out,clk,d);
clk=0;
nand d=0;
(nand2_out,clk,db); #10 d=1;
nand #10 d=0;
(q,nand1_out,qbar); #10 d=1;
nand #10 d=0;
(qbar,nand2_out,q); #10 d=1;
#10 $finish();
endmodule
end
endmodule

Output:

16
  S-R Flip Flop

Verilog Code Testbench Code

module srff_gate(q, module tb();
qbar, s, r, clk); reg s,r,clk;
wire q, qbar;
srff_gate uut(q, qbar, s, r, clk);
input s,r,clk;
initial begin
output q, qbar; clk = 0;
forever #5 clk = ~clk;
wire nand1_out; end
wire nand2_out; initial begin $dumpfile("dump.vcd"); $dumpvars;

nand (nand1_out,clk,s); $monitor($time,"s=%b,r=%b,clk=%b,q=%b,qbar=%b"

,s,r,clk,q,qbar);
nand (nand2_out,clk,r);
clk=0;
nand s=0;r=0;
(q,nand1_out,qbar); #10 s=0;r=1;
nand #10 s=1;r=0;
(qbar,nand2_out,q); #10 s=1;r=1;
#10 $finish();
endmodule end
endmodule

Output:

17
  J-K Flip Flop

Verilog Code Testbench Code

module jkff_gate(q, qbar, module tb();
j, k, clk); reg j,k,clk;
wire q, qbar;
jkff_gate uut(q, qbar, j, k, clk);
input j,k,clk;
initial begin
output q, qbar; clk = 0;
forever #5 clk = ~clk;
wire nand1_out; end
wire nand2_out; initial begin $dumpfile("dump.vcd"); $dumpvars;

nand $monitor($time,"s=%b,r=%b,clk=%b,q=%b,qbar=%b"
,j,k,clk,q,qbar);
(nand1_out,clk,j,qbar);
clk=1;
nand j=0;k=0;
(nand2_out,clk,r,k,q); #10 j=0;k=1;
nand (q,nand1_out,qbar); #10 j=1;k=0;
nand (qbar,nand2_out,q); #10 j=1;k=1;
#10 $finish();
endmodule end
endmodule

Output:

18
  T Flip Flop

Verilog Code Testbench Code

module tff_gate(q, module tb();
qbar, t, clk); reg t,clk;
input t,clk; wire q, qbar;
tff_gate uut(q, qbar, t, clk);
inout q, qbar;
initial begin
clk = 0;
wire nand1_out; forever #5 clk = ~clk;
wire nand2_out; end

nand initial begin $dumpfile("dump.vcd"); $dumpvars;

(nand1_out,clk,t,qbar); $monitor($time,"t=%b,clk=%b,q=%b,qbar=%b"
,t,clk,q,qbar);
nand
clk=0;
(nand2_out,clk,q,t); t=0;
nand #10 t=1;
(q,nand1_out,qbar); #10 t=0;
nand #10 t=1;
(qbar,nand2_out,q); #10 t=0;
#10 t=1;
#10 $finish();
endmodule
end
endmodule

Output:

19