TSMC N7 SRAM Compiler Databook

Version 20151201 c190115 120b

September 2019
Copyright ➞ 2019, Taiwan Semiconductor Manufacturing Company, Ltd. All Rights Reserved. No part of this
publication may be reproduced in whole or in part by any means without prior written consent.

NOTICE
Taiwan Semiconductor Manufacturing Company Ltd. reserves the right to make changes in the contents of this
document without notice. No responsibility is assumed by Taiwan Semiconductor Manufacturing Company Ltd. for
any infringements of patents or other rights of the third parties that may result from its use. Taiwan Semiconductor
Manufacturing Company Ltd. assumes no responsibility for any error that appears in this document.
Table of Contents

Revision History of Databook 8

Databook version and Compiler version mapping table 9

About this Databook 10

1 Overview of Compiler Family 11

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.1 Product Family, Naming Convention, Classification and IP tag . . . . . . . . . . . . . . . . . . 11
1.1.2 General Features of Compiler Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1.3 Compiler Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2 Compiler Profile 16
2.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.2 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.3 Compiler Range Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1.4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1.5 Major Pin Setting Requirement During Different Operation Modes . . . . . . . . . . . . . . . . 28
2.1.6 Logic Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.1.7 Hazard Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.1.8 Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.1.9 Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.1.10 Integration Guideline of Dual Rail and Power Management . . . . . . . . . . . . . . . . . . . . 47
2.1.11 Redundancy Repair Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.1.12 DFT Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.1.13 Characterization Corners & Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.1.14 Power Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.1.15 Metal Layer Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.1.16 Scramble Diagram and Mapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.1.17 Power/Ground Connection Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.1.18 Routing Blockage Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
2.1.19 Placement Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
2.2 Reference Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.2.1 Release Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.2.2 Quick Reference Table (QRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

3 Compiler File Structure 101

3.1 Input file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
3.2 Output file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.3 Design kit and associated tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

4 Application Note 105

4.1 TSMC SRAM Verilog Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.1.2 Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.1.3 Behavioral model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.1.4 Synthesizable Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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 4.1.5 Verilog Models Used in SOC Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.1.6 Detail of Directive, Parameter and Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.2 TSMC SRAM DFT Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.2.2 Synthesis and STA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.2.3 ATPG and Synchronous Write Through (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.2.4 Using ATPG model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

5 Compiler Installation and Execution 122

5.1 Memory Compiler Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.2 Installation Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.3 License Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.3.1 Evaluation License (Front-End Kits & LEF Only) . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.3.2 Formal License (Include Front-End Kits & Back-End Kits) . . . . . . . . . . . . . . . . . . . . 123
5.4 MC2 Engine and License Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.4.1 Prepare ”install.txt” File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.4.2 Use ”mc2 install.pl” Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.4.3 Compiler and License Installation Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.5 Memory Macro Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.5.1 Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.5.2 ROM Generation with Specified ROM Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.5.3 ROM code verification and format transformation . . . . . . . . . . . . . . . . . . . . . . . . . 130

6 References 131
6.1 Abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.2 Quick Troubleshooting for MC2 License Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3 Other Related Problems and Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

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List of Figures

1.1 Macro Options of Feature Combination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1 Block diagram of 1PRF/SPMB/HSSP/SPSB (TSEL pins are described in pin description table Table 2.11) 16
2.2 Block diagram of 2PRF (TSEL pins are described in pin description table Table 2.12) . . . . . . . . . 17
2.3 Block diagram of ROM (TSEL pins are described in pin description table Table 2.12) . . . . . . . . . 18
2.4 Timing protocol of SRAM Read-only operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.5 Timing protocol of SRAM Write-only operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.6 Timing protocol of port contention Read then Write (AA=AB) . . . . . . . . . . . . . . . . . . . . . . 41
2.7 Timing protocol of port contention Write then Read (AA=AB, D=D0) . . . . . . . . . . . . . . . . . 42
2.8 Timing protocol of ROM Read-only operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.9 Timing diagram of ROM unknown Q state between clock cycles with same address . . . . . . . . . . . 43
2.10 Clock Separation with Addresses Contention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.11 Timing protocol of BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.12 Timing protocol of redundancy function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.13 Timing protocol of TSEL pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.14 Illustration of power rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.15 VDDM power gating with SD or DSLP asserted logic high . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.16 Power ramp-up sequence with SD or DSLP asserted logic high . . . . . . . . . . . . . . . . . . . . . . 50
2.17 Power ramp-down sequence (VDDM down first) with SD or DSLP asserted logic high . . . . . . . . . 50
2.18 Power ramp-down sequence (VDD down first) with SD or DSLP de-asserted . . . . . . . . . . . . . . . 51
2.19 Power ramp-down sequence (VDD down first) with SD or DSLP asserted logic high . . . . . . . . . . 51
2.20 VDD can be power-off when SD=1, VDDM=ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.21 Timing protocol of deep sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.22 Timing protocol of shut down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.23 Redundancy shift and decode direction with mux2/4 for 1PRF . . . . . . . . . . . . . . . . . . . . . . 57
2.24 Redundancy shift and decode direction with mux1 for 1PRF . . . . . . . . . . . . . . . . . . . . . . . 58
2.25 Redundancy shift and decode direction with mux2/4 for 2PRF . . . . . . . . . . . . . . . . . . . . . . 59
2.26 Redundancy shift and decode direction with mux1 for 2PRF . . . . . . . . . . . . . . . . . . . . . . . 60
2.27 Redundancy shift and decode direction with mux4/8/16 for SPSB . . . . . . . . . . . . . . . . . . . . 61
2.28 Redundancy shift and decode direction with mux2 for SPSB . . . . . . . . . . . . . . . . . . . . . . . . 62
2.29 Redundancy shift and decode direction for SPMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.30 Redundancy shift and decode direction for HSSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.31 Scan chain block diagram of 1PRF, SPSB, SPMB, HSSP compilers . . . . . . . . . . . . . . . . . . . . 66
2.32 Scan chain block diagram of 2PRF compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.33 Scan chain block diagram of ROM compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.34 Scan chain of 1PRF, 2PRF, SPSB, SPMB,HSSP, compilers . . . . . . . . . . . . . . . . . . . . . . . . 69
2.35 Scan chain of ROM compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.36 Shift/Capture mode timing protocol with DFTBYP=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.37 Debug shift and normal mode timing protocol with DFTBYP=0 . . . . . . . . . . . . . . . . . . . . . 79
2.38 Shift/Capture mode timing protocol with DFTBYP=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.39 Debug shift and normal mode timing protocol with DFTBYP=0 . . . . . . . . . . . . . . . . . . . . . 80
2.40 Shift/Capture mode timing protocol with DFTBYP=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.41 Debug shift and normal mode timing protocol with DFTBYP=0 . . . . . . . . . . . . . . . . . . . . . 81
2.42 Isolation timing protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.43 Compiler scramble diagram for 1PRF mux1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.44 Compiler scramble diagram for 1PRF mux2/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.45 Compiler scramble diagram for 2PRF mux1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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2.46 Compiler scramble diagram for 2PRF mux2/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
2.47 Compiler scramble diagram for SPSB mux2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
2.48 Compiler scramble diagram for SPSB mux4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
2.49 Compiler scramble diagram for SPSB mux8/16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
2.50 Compiler scramble diagram for SPMB with 1 bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
2.51 Compiler scramble diagram for SPMB 2 banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
2.52 Compiler scramble diagram for SPMB with 1000 rows . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.53 Compiler scramble diagram for SPMB with 520 rows . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.54 Compiler scramble diagram for HSSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2.55 Compiler scramble diagram for ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2.56 Chip level power routing guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.57 APR Chip Integration Guideline for SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
2.58 Memory space guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

3.1 File structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

3.2 Example file structure of generated kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.1 ASIC design flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4.2 FPGA design flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.3 SRAM normal mode of operation except 2PRF and ROM . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.4 SRAM shift mode of operation except 2PRF and ROM . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.5 SRAM capture mode of operation except 2PRF and ROM . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.6 Scan chain design related to SRAM macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

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List of Tables

1 Databook version and IDR Compiler mapping table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Chapter Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1 SRAM compiler product family and naming convention . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.2 Decoding of instance name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3 Featuring of each compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 Options for compiling command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5 Pins presented in combination of power rails and PM for compilers except ROM . . . . . . . . . . . . 15
1.6 Pins presented in combination of power rails and PM options . . . . . . . . . . . . . . . . . . . . . . . 15

2.1 Configuration range of 1PRF compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.2 Configuration range of 2PRF compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3 Configuration range of SPSB compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4 Configuration range of SPMB compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5 Configuration range of HSSP Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.6 Configuration range of ROM compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.7 Pin description of 1PRF/ SPSB/ SPMB/ HSSP compilers . . . . . . . . . . . . . . . . . . . . . . . . 23
2.8 Scan chain related input/output pin description of 1PRF/SPSB/SPMB/HSSP/ compilers . . . . . . . 24
2.9 Pin description of 2PRF compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.10 Pin description of ROM compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.11 Default setting of TSEL pins for 1PRF, SPSB, SPMB, HSSP, UHD2PRF . . . . . . . . . . . . . . . . 27
2.12 Default setting of TSEL pins for 2PRF, ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.13 Active pins in normal function mode for 1PRF/SPSB/SPMB/ HSSP . . . . . . . . . . . . . . . . . . . 29
2.14 Active pins in normal function mode for ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.15 Active pins in normal function mode for 2PRF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.16 Active pins in deep sleep and shut down modes for 1PRF/SPSB/SPMB/ HSSP/ . . . . . . . . . . . . 30
2.17 Active pins in deep sleep and shut down modes for 2PRF . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.18 SRAM hazard conditions for 1PRF/SPSB/SPMB/HSSP compilers . . . . . . . . . . . . . . . . . . . . 32
2.19 SRAM hazard conditions for 2PRF: write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.20 SRAM hazard conditions for 2PRF : read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.21 SRAM hazard conditions for ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.22 SRAM hazard conditions: redundancy fuse setting cycle for 1PRF/SPSB/SPMB/HSSP compilers . . 34
2.23 SRAM hazard conditions: redundancy fuse setting cycle for 2PRF compiler . . . . . . . . . . . . . . . 34
2.24 Timing specification symbols and definitions of 1PRF/SPSB/SPMB/HSSP compilers . . . . . . . . . . 36
2.25 Timing specification symbols and definitions of 2PRF compiler . . . . . . . . . . . . . . . . . . . . . . 37
2.26 Timing specification symbols and definitions of ROM compiler . . . . . . . . . . . . . . . . . . . . . . 38
2.27 Timing specification for TSEL pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.28 Condition & description of rails with on/off states vs. DSLP/SD . . . . . . . . . . . . . . . . . . . . . 52
2.29 Condition & description of rails with on/off states vs. SD . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.30 FADIO[J:0] and repair IO shift number mapping table . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.31 Scan chain configuration order of 1PRF compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.32 Scan chain configuration order of 2PRF compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.33 Scan chain configuration order of SPSB compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.34 Scan chain configuration order of SPMB compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.35 Scan chain configuration order of HSSP compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.36 Scan chain configuration order of ROM compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.37 Scan chain truth table for all compiler (except 2PRF and ROM) . . . . . . . . . . . . . . . . . . . . . 72
2.38 Scan chain truth table for 2PRF compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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2.39 Scan chain truth table for ROM compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.40 Timing specification definitions of 1PRF/SPSB/SPMB/HSSPcompiler . . . . . . . . . . . . . . . . . . 75
2.41 Timing specification definitions of 2PRF compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.42 Timing specification definitions of ROM compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.43 Signal slew table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.44 CLK slew table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.45 PVT Corner of Single Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.46 For word-depth=128, Mux = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2.47 Summary on Memory Spacing Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
2.48 Terms and description (used in QRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

3.1 Design kits generated by compilers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

4.1 Verilog model offering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4.2 SRAM ATPG operation modes for all compilers except 2PRF and ROM . . . . . . . . . . . . . . . . . 115
4.3 SRAM ATPG operation modes for 2PRF and ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

6.1 Abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

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Revision History of Databook
i

Date Document Version Description

05/24/2019 20151201 c190115 120a First created
09/23/2019 20151201 c190115 120b Removed ”Automotive” wording

8 of 132
Databook version and Compiler version mapping table

Databook 1PRF 2PRF SPSB SPMB ROM HSSP

120a 120a 120a 120a 120a 120a 120a
120b 120b 120b 120b 120b 120b 120b

Table 1: Databook version and IDR Compiler mapping table

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About this Databook
This databook describes both the overview and details of a TSMC memory compiler family. Profiles, features, op-
tions, directory structures, front-end and back-end design kits, user modes and user-specified configurable files will be
described.

Reader and User

The intention of this databook is to provide design engineers with information about TSMC memory IP products
and to help supporting engineers understand the perspective of this product family. Features, functionality, benefits,
options and usage for SOC silicon implementation are described.

How to use this Databook

This databook is organized into the following chapters. Users can refer to the chapter of interest.

Section Description
Chapter 1 Overview of Compiler Introduction of the common key features of this compiler family
Family Product
Chapter 2 Compiler Profile Specification and features Specification and features among compilers
Chapter 3 Compiler In-Output File Input and output files for the compiler execution
Structure
Chapter 4 Application Note Verilog usage, DFT application and memory placement guidelines
Chapter 5 Compiler Installation and How to run memory compiler to generate macros
Execution
Chapter 6 References Useful information of compiler installation, general guideline and
license issue debugging

Table 2: Chapter Organization

Reference Documents
In addition to this databook, a PPA (Performance, Power and Area) overview of each compiler will be provided in the
delivery package. Additionally a release note is included where tech files used for compiler development and revision
history will be described. Please see Chapter 2 for details.

Compiler Product Online Release

The latest revision of each TSMC Memory compiler portfolio can be found on TSMC-Online under Design Portal.
The databook and release note are available for review as well. TSMC-9000 Compliance Status provides reference for
the TSMC-9000 validation results and the IP alert information. Risk level will be given in the pop-up window if there
is an IP problem identified. An email notice will be sent to users who have downloaded compilers whenever there is
revised release. Users must take action to update the compiler with the latest version, or mask tape-out could be put
on hold if an old version is used.

Technical Support
For technical support, please contact Field Technical Support (FTS) at a TSMC regional office near you.

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Chapter 1

Overview of Compiler Family

1.1 Introduction
TSMC Memory Compiler family provides a total system solution of embedded memory IP for short turn-around time
of design process and a fast reliable path to market for leading SOC companies. The family is developed with 7nm Low
Leakage HKMG process and provides memory instances based on a variety of parameters, aspect ratio and support
views of corresponding EDA tools. The family includes 1PRF, 2PRF, SPSBSRAM, SPMBSRAM, HSSPSRAM, and
ROM.

1.1.1 Product Family, Naming Convention, Classification and IP tag

The Memory compilers in the family are listed in Table 1.1. The instance naming convention and bit cell size are
provided in this table as well.
IP tag is important for TSMC to identify IP name and version for wafer volume monitoring, silicon debugging and IP
quality system detection. Customer shall NOT remove the tag during tapeout.
The tag is drawn on layers OD/NW and IP(63;63).
The tag string starts with ”& ” for each of the major tags: vendor, product, version and instance tag.

Type Compiler Name Instance Name Bit- Description

cell
SPSBSRAM tsn7 spsbsram 20151201 c190115 ts1n7sb{vt}a{depth}x{width}m{mux}wbzhodcp {ver} 0.0342 Single Port Single Bank SRAM
{ver}
SPMBSRAM tsn7 spmbsram 20151201 c190115 ts1n7mb{vt}a{depth}x{width}m{mux}{seg}wbzhodcp 0.0342 Single Port Multi Bank SRAM
{ver} {ver}
HSSPSRAM tsn7 hsspsram 20151201 c190115 ts1n7hs{vt}a{depth}x{width}m{mux}wbzhodcp {ver} 0.0342 High Speed Single Port SRAM
{ver}
1PRF tsn7 1prf 20151201 c190115 {ver} ts5n7{vt}a{depth}x{width}m{mux}wbzhodcp {ver} 0.0342 One Port Register File
2PRF tsn7 2prf 20151201 c190115 {ver} ts6n7{vt}a{depth}x{width}m{mux}{seg}wbzhodcp {ver} 0.0530 Two Port Register File
ROM tsn7 rom 20151201 c190115 {ver} ts3n7{vt}a{depth}x{width}m{mux}bzod {ver} 0.0103 ROM

Table 1.1: SRAM compiler product family and naming convention

In order for users to understand what features of macro are presented with each postfix letter/term, Table 1.2 is
provided to illustrate the meaning of each letter/term.

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 Naming Decode Description
vt Periphery Vt
a or b after ”vt” Bit cell type
depth Word depth
width Word width
mux Number of mux
seg Segment type
w Bit write
b BIST
z SWT
h Deep sleep
o Shut down
d Dual rail
x Write assist
cp Column redundancy
l Half power gate
ver Version

Table 1.2: Decoding of instance name

Multiple compilers are offered in compiler family for this technology generation, major aspect of each compiler is
described in following Table 1.3

Type Featuring Remark

SPSBSRAM Single Bank one port read/write function with high current bit cell
SPMBSRAM Multi Bank one port read/write function with high current bit cell
HSSPSRAM One port read/write function with highest speed
1PRF One port read/write function with higher area utilization than HSSP
2PRF One port read and one port write function
ROM Non-volatile read only memory

Table 1.3: Featuring of each compiler

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1.1.2 General Features of Compiler Family
❼ Pins and metal layer

– 3 metal layers used

– Power pins in top layer with M3 for easy connection
– All input and output pins on one side of macro
– M1 signal pins on 57nm pitch track
❼ Compilation option :

– Bit line segment selection for performance and area optimization

– MUX selection for the desired macro aspect ratio
– Bit-write mask function
– Input MUX interface for BIST function
– Column redundancy
– Periphery majority Vt options for performance and leakage optimization. The sram macro includes mixed-
Vt devices for each selected Vt option while the majority of peripheral devices belong to the selected
Vt.
– Synchronous write through (SWT).

❼ Power management :

– Deep sleep mode powers down the most of peripheral circuit for leakage reduction and retains memory
array content with lower voltage
– Shut down mode achieves highest leakage reduction without data retention
– Dual rail design to support Dynamic Voltage Frequency Scaling (DVFS) application
– Power detector embedded in dual rail option to support VDD on followed by VDDM ramping up sequence
❼ General :

– Frequently used EDA model support, refer to Table 3.1 for supported commercial EDA tools

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1.1.3 Compiler Options
During compilation to generate macros, users can choose desired features for application with command options, all
combinations of option are described in following sections:

1.1.3.1 Compiler feature options

Table below lists all available options for each compiler, please note that not all options are applicable to every compiler.

1PRF 2PRF SPSB SPMB ROM HSSP Option Description

Y Y Y Y Y Y -h Help
Y Y Y Y Y Y -NonTsmcName To use user-defined naming
convention (default is TSMC
naming convention)
Y Y Y Y Y Y -file <configfile> To use the input file from user
as configuration file (default
is config.txt)
Y Y Y Y Y Y -DualRail To enable Dual Rail option
(default is Disable)
Y Y Y Y N Y -ULVT To enable ulvt option (default
is lvt). Mixed Vt design with
device majority of ULVT for
high speed purpose
Y Y Y Y Y Y -SVT To enable svt option (default
is lvt). Mixed Vt design with
device majority of SVT for
low power purpose
Y Y Y Y N Y -NonBWEB To disable BWEB option
Y Y Y Y Y Y -NonBIST To disable BIST option.
Y Y N N N Y -NonColRed To disable column redun-
dancy option
N N N N Y N -GenROMCode To generate the default rom
code
Y Y Y Y Y Y -PVT To choose specific PVT cor-
ners
Y Y Y Y Y Y -LISTPVT To list PVT corners
Y Y Y Y Y Y -DATASHEET To generate DATASHEET kit
only
Y Y Y Y Y Y -lefM2Metal To change the metal
naming rule in LEF,
from M0,M1,...,M4 to
METAL0,METAL1,...,METAL4
Y Y Y Y Y Y -datasheet merged To produce only merged
datasheet (* mergedpvt.ds)
Y Y Y Y Y Y -datasheet separate To produce only individual
datasheet
Y Y Y Y Y Y -DS To put the value with the spe-
<clk>X<input>X<load>cific ”clock slew index & in-
put slew index & output load-
ing index” in DATASHEET
<clk>, <input>and
<load>only support from 1
to 5
The default setting is -DS
1X1X1

Table 1.4: Options for compiling command

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1.1.3.2 Combinations of power rails and power management
Please note that not all power management options associated with power rails are independently available, combina-
tions of option are described in following tables:

PM (Power Management) :

Power Rail DSLP SD

Single Rail ON ON
Dual Rail ON ON

Table 1.5: Pins presented in combination of power rails and PM for compilers except ROM

PM (Power Management) for ROM:

Power Rail SD
Single Rail OFF
Single Rail ON
Dual Rail ON

Table 1.6: Pins presented in combination of power rails and PM options

❼ Dual Rail option is always in pair with power management.

1.1.3.3 Summary of option combinations for compiler family

All available option combinations for each compiler are summarized in table below:

Figure 1.1: Macro Options of Feature Combination

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Chapter 2

Compiler Profile

TSMC 7nm compilers operates within a voltage range from 0.675V to 0.825V and a junction temperature range from
-40C to 125C.

2.1 Specification
2.1.1 Block Diagram

Figure 2.1: Block diagram of 1PRF/SPMB/HSSP/SPSB (TSEL pins are described in pin description table Table 2.11)

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Figure 2.2: Block diagram of 2PRF (TSEL pins are described in pin description table Table 2.12)

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Figure 2.3: Block diagram of ROM (TSEL pins are described in pin description table Table 2.12)

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2.1.2 Function
The synchronized compiler is triggered by a clock rising edge, CLK. All input control pins, for example, input address
A, input data D, chip enable CEB and write enable WEB are latched by the rising edge of clock. The following
explains major operation of each compiler.

2.1.2.1 Read-only Operation

1PRF/ SPSB/ SPMB/ HSSP/ compiler :
The chip enable pin, CEB must be low and write-enable pin, WEB stays high at CLK rising edge. The read operation
accesses the memory bits specified by address A[M-1:0] and places the data outputs on bus Q[N-1:0] after the read
access time.

ROM compiler :
The chip enable pin, CEB must be low at CLK rising edge. The read operation accesses the memory bits specified by
address A[M-1:0] and places the data outputs on bus Q[N-1:0] after the read access time.

2PRF compiler :
The chip enable, REB must be low at CLKR rising edge. Data is read and then transmitted to output bus Q[N-1:0]
from memory location specified by AB[M-1:0].

2.1.2.2 Write-only Operation

1PRF/ SPSB/ SPMB / HSSP compiler :

The write-enable pin, WEB must be low and chip enable pin, CEB stays low at CLK rising edge. Data on bus
D[N-1:0] is written into memory bits specified by address A[M-1:0]. The bit-write mask feature is controlled by bus
BWEB[N-1:0]. The data bit is not written into the memory when the corresponding BWEB pin is set to high.

2PRF compiler :
The write-enable, WEB must be low at CLKW rising edge. Data D[N-1:0] is written into memory location specified
by address AA[M-1:0]. The bit-write feature is controlled by BWEB[N-1:0].

2.1.2.3 Address Contention for 2PRF

Since CLKW and CLKR are independent clocks whose edges may not be related to each other, address contentions
between ports A and B are not resolved. Address contention is defined as the same address being latched during a
write and read operation where insufficient clock separation occurs ( twrcc/trwcc ). If an address contention occurs,
indeterminate results are read from the array. Timing specification twrcc/trwcc relates the minimum time required
between CLKW and CLKR in order for same address operations to occur without indeterminate results. If the same
external signal drives CLKW and CLKR, indeterminate results will occur if the addresses match during a simultaneous
write and read operation. However, write operation for input data written into memory cell is completed.

❼ Write Operation Followed by Read Operation:

twrcc (measured from both clocks rising) is the minimum separation time required for a write to complete before
a successful read of the same address can occur. This guarantees that the data is written to the array before the
data is accessed for a read operation. If twrcc is violated during a write followed by read operation, then the
read output is indeterminate.

❼ Read Operation Followed by Write Operation:

Violation of trwcc will cause the unknown data appears in the read port output.

2.1.2.4 Deep Sleep Mode

The deep sleep mode pin, DSLP must be high to enter the mode. It reduces standby leakage by switching off the
power supply to part of periphery circuit while the bit cell power is sustained at lower VDD in single rail and lower
VDDM in Dual Rail. Thus the memory content is retained during deep sleep mode.

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2.1.2.5 Shut Down Mode
The shut down mode pin, SD must be high to enter the mode. It reduces most standby leakage by switching off the
power supply to most of periphery circuit and whole bit cell array. Thus the memory content will be corrupted after
entering this mode.

2.1.2.6 Dual Rail

Level shifters are built-in at the macro input interface to convert the input pin voltage level from VDD to VDDM, the
power voltage supplies inner memory periphery and bitcell array. This feature allows SOC to operate at a different
voltage level from SRAM macro.

2.1.2.7 Redundancy
Column redundancy is built-in for repairing defect bit cells. To start the repair function, the defective IO number
must be addressed by parallel in redundancy input pins. Once repair function is asserted, the defective IO will be
replaced by the redundant IO. Refer to subsection 2.1.11 for more details of the redundancy mechanism and repair
setting.

2.1.2.8 Design For Test (DFT) mode

DFT function increases the test coverage and improves overall testability on the SOC. It includes BIST interface
and DFT scan chain scheme. The input signals from normal function path or BIST logic path are multiplexed at
the interface by BIST control signal. The scan chain scheme supports Synchronous Write Through (SWT) bypass
function and scan in/out function to enable ATPG test. The more detailed DFT description can be referenced in
subsection 2.1.12 ”DFT Scheme”.

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2.1.3 Compiler Range Information
Memory macros can be configured by column mux option, number of words (Word Depth), and number of bits per
word (Word Width). The valid range of these parameters is specified in below tables.

1PRF:

SEG Option Mux Option Word Depth (WD) WD Increment Word Width I/O Increment
NA 1 8 4 24-288 2
NA 1 12 4 20-288 2
NA 1 16-128 4 16-288 2
NA 2 16-256 8 8-144 1
NA 4 32-512 16 8-72 1

Table 2.1: Configuration range of 1PRF compiler

2PRF:

SEG Mux Word Depth (WD) WD Word I/O

Option Option Increment Width Increment
F 1 32, 40-96, 104-160, 168-224, 4 16-288 2
232-256
F 2 64, 80-192, 208-320, 336-448, 8 8-144 1
464-512
F 4 128, 160-384, 416-640, 672-896, 16 8-72 1
928-1024
S 1 64, 72-192, 200-256 4 16-288 2
S 2 128, 144-384, 400-512 8 8-144 1
S 4 256, 288-768, 800-1024 16 8-72 1

Table 2.2: Configuration range of 2PRF compiler

SPSBSRAM:

SEG Option Mux Option Word Depth (WD) WD Increment Word Width I/O Increment
NA 2 16 8 10-288 2
NA 2 24-512 8 8-288 2
NA 4 32-1024 16 8-144 1
NA 8 64-2048 32 8-72 1
NA 16 128-4096 64 8-39 1

Table 2.3: Configuration range of SPSB compiler

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SPMBSRAM:

SEG Option Mux Option Word Depth (WD) WD Increment Word Width I/O Increment
T 4 512-2048 16 8-144 1
T 8 1024-4096 32 8-72 1
T 16 2048-8192 64 8-39 1
Q 4 512-4096 16 8-144 1
Q 8 1024-8192 32 8-72 1
Q 16 2048-16384 64 8-39 1

Table 2.4: Configuration range of SPMB compiler

HSSPSRAM:

SEG Option Mux Option Word Depth (WD) WD Increment Word Width I/O Increment
NA 2 64-512 8 8-144 1
NA 4 128-1024 16 8-72 1

Table 2.5: Configuration range of HSSP Compiler

ROM:

SEG Option Mux Option Word Depth (WD) WD Increment Word Width I/O Increment
NA 16 256-16384 256 8-72 1

Table 2.6: Configuration range of ROM compiler

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2.1.4 Pin Description
2.1.4.1 Pin list tables
Refer to tables below for detail pin description of each compiler.

Pin list of 1PRF/ SPSB / SPMB/ HSSP/ compiler :

Pin Type Description *Scanable

VDD Supply Power bus N
VDDM Supply Power bus N
VSS Supply Ground bus N
A[M-1:0] Input Address input Y
AM[M-1:0] Input Address input for BIST Y
D[N-1:0] Input Data input Y
DM[N-1:0] Input Data input for BIST Y
CLK Input Clock input N
CEB Input Chip enable, active low Y
CEBM Input Chip enable for BIST, active low Y
WEB Input Write enable, active low Y
WEBM Input Write enable for BIST, active low Y
BWEB[N-1:0] Input Bit write enable, active low Y
BWEBM[N-1:0] Input Bit write enable for BIST, active low Y
BIST Input BIST interface enable pin; active high N
DSLP Input Deep sleep mode enable; active high N
SD Input Shut down mode enable pin; active high N
REDENIO Input Column repair enable, active high N
FADIO[J:0] Input Faulty IO address input N
RTSEL[1:0] Input TSEL pins, Timing adjustment setting for debugging pur- N
pose in SVT option
WTSEL[1:0] Input TSEL pins, Timing adjustment setting for debugging pur- N
pose in SVT option
PUDELAY SD Output A propagation signal from SD (shut-down) used for sequen- N
tial wake-up control on multiple macros to reduce simulta-
neous peak current in chip level
PUDELAY DSLP Output A propagation signal from DSLP (deep-sleep) used for se- N
quential wake-up control on multiple macros to reduce si-
multaneous peak current in chip level
Q[N-1:0] Output Data output N
DSLPLV Input Diode bypass mode enable. DSLPLV=1: diode bypass N
mode; DSLPLV=0 diode retention mode
Note *Scanable :”Y” means this pin or bus can be captured and shifted through embedded scan flops.

Table 2.7: Pin description of 1PRF/ SPSB/ SPMB/ HSSP compilers

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Due to difference of layout structure and limitation of scan FF length, the required amount of scan in/out pins varies,
table(Table 2.8) below lists number of pins corresponding to types of compiler.

Pin Type Description Compilers

DFTBYP Input DFT enable pin; active high 1PRF/SPSB/SPMB/ HSSP
SE Input Scan chain enable pin; active high 1PRF/SPSB/SPMB/ HSSP
SIC Input Input of scan chain for control pins 1PRF/SPSB/SPMB/ HSSP
SOC Output Output of scan chain for control pins 1PRF/SPSB/SPMB/ HSSP
SID[1:0] Input Input of scan chain for data/bit write enable 1PRF/SPSB/SPMB /HSSP
SOD[1:0] Output Output of scan chain for data/bit write enable 1PRF/SPSB/SPMB /HSSP

Table 2.8: Scan chain related input/output pin description of 1PRF/SPSB/SPMB/HSSP/ compilers

24 of 132
Pin list of 2PRF compiler :

Pin Type Description *Scanable

VDDM Power Power bus N
Sup-
ply
VDD Power Power bus N
Sup-
ply
VSS Power Ground bus N
Sup-
ply
AA[M-1:0] Input Write address input Y
AMA[M-1:0] Input Write address input for BIST Y
D[N-1:0] Input Data input Y
DM[N-1:0] Input Data input for BIST Y
BWEB[N-1:0] Input Bit write enable pin, active low Y
BWEBM[N-1:0] Input Bit write enable pin for BIST, active low Y
WEB Input Write enable pin, active low Y
WEBM Input Write enable pin for BIST, active low Y
CLKW Input Write clock input N
AB[M-1:0] Input Read address Input Y
AMB[M-1:0] Input Read address input for BIST Y
REB Input Read enable pin, active low Y
REBM Input Read enable pin for BIST, active low Y
CLKR Input Read clock input N
DSLP Input Deep sleep mode enable; active high N
SD Input Shut down mode enable pin; active high N
BIST Input BIST interface enable pin; active high N
REDENIO Input Column repair enable pin, active high N
FADIO[J:0] Input Faulty IO address input N
RCT[1:0] Input TSEL pins, Timing adjustment setting for debugging purpose N
WCT[1:0] Input TSEL pins, Timing adjustment setting for debugging purpose N
KP[1:0] Input TSEL pins, Timing adjustment setting for debugging purpose N
DSLPLV Input Diode bypass mode enable. DSLPLV=1: diode bypass mode; N
DSLPLV=0 diode retention mode
PUDELAY SD Output A propagation signal from SD (shut-down) used for sequential N
wake-up control on multiple macros to reduce simultaneous peak
current in chip level
PUDELAY Output A propagation signal from DSLP (deep-sleep) used for sequential N
DSLP wake-up control on multiple macros to reduce simultaneous peak
current in chip level
Q[N-1:0] Output Data output N
DFTBYP Input DFT enable pin; active high N
SE Input Scan chain enable pin; active high N
SIC Input Input of scan chain for control pins N
SID[1:0] Input Input of scan chain for data/bit write enable N
SOC Output Output of scan chain for control pins N
SOD[1:0] Output Output of scan chain for data/bit write enable N
Note *Scanable :”Y” means this pin or bus can be captured and shifted through embedded scan flops.

Table 2.9: Pin description of 2PRF compiler

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Pin list of ROM compiler :

Pin Type Description *Scanable

VDD Supply Power bus N
VDDM Supply Power bus N
VSS Supply Ground bus N
A[M-1:0] Input Address inputs Y
AM[M-1:0] Input Address inputs for BIST Y
CLK Input Clock input N
CEB Input Chip enable, active low for ROM operation Y
CEBM Input Chip enable for BIST, active low for ROM operation Y
BIST Input BIST interface enable pin; active high N
SD Input Shut down mode enable pin; active high N
CKHE Input TSEL pins, Timing adjustment setting for debug purpose N
CKLE Input TSEL pins, Timing adjustment setting for debug purpose N
SKP[1:0] Input TSEL pins, Static keeper strength adjustment N
DT[1:0] Input TSEL pins, Timing adjustment setting for debug purpose N
Q[N-1] Output Data outputs N
PUDELAY Output A propagation signal from SD (shut-down) used for sequential wake- N
up control on multiple macros to reduce simultaneous peak current in
chip level
DFTBYP Input DFT enable pin; active high N
SE Input Scan chain enable pin; active high N
SIC Input Input of scan chain for control pins N
SIQ[1:0] Input Input of scan chain for data bypass N
SOC Output Output of scan chain for control pins N
SOQ[1:0] Output Output of scan chain for data bypass N
Note *Scanable :”Y” means this pin or bus can be captured and shifted through embedded scan flops.

Table 2.10: Pin description of ROM compiler

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2.1.4.2 Default values of TSEL pins
Default values of TSEL pin setting are listed in Table 2.11, Table 2.12 and ??, they are stringently required to guar-
antee correct memory function since all timing data is characterized with default setting. TSEL pin setting might be
subject to change in future revision release after silicon validation. Other setting combinations of logic state would
only be used for silicon debugging purpose only.

Compiler RTSEL WTSEL MTSEL WASSEL WASEN

1PRF 10 01 - - -
SPSB 10 01 - - -
SPMB 10 01 - - -
HSSP 10 01 - - -

Table 2.11: Default setting of TSEL pins for 1PRF, SPSB, SPMB, HSSP, UHD2PRF

Compiler RTSEL WTSEL RCT WCT KP CKHE CKLE SKP DT

2PRF - - 01 01 10 - - - -
ROM - - - - - 0 1 01 00

Table 2.12: Default setting of TSEL pins for 2PRF, ROM

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2.1.5 Major Pin Setting Requirement During Different Operation Modes
Below pin constraints are required in different modes of memory operation to ensure that logic and timing models
behave as exactly as silicon does.
The interface timing is characterized with TSEL pin default setting only in both Scan/DFT mode and normal function
mode.
In Scan/DFT mode, TSEL pins are allowed to be unknown ”X” or toggling, and output timing keeps no change even
if TSEL pin values change.
In normal function mode, TSEL pins must be default setting to assure timing is matched to timing model. TSEL pins
different from default setting may cause silicon setup/hold timing failure.

❼ During Scan/DFT Mode

– TSEL pins*: allowed to be 0, 1 or toggled, but cannot be floating.

– Redundancy REDENIO/FADIO pins: allowed to be 0, 1 or toggled, but cannot be floating.
– PM pins**: must be 0 (de-asserted).

❼ During PM Mode with either SD or DSLP asserted

– TSEL pins: allowed to be floating.

– Redundancy related pins: allowed to be floating.
– PM pins: Not allowed to be floating .
❼ During Normal Function Mode

– TSEL pins: must be default values.

– Redundancy related pins: must be set to desired static values, not allowed to be toggled during the cycle.
– PM pins: must be 0 (de-asserted).

Note * : TSEL pins include

1PRF/SPSB/SPMB/HSSP :RTSEL,WTSEL,;
2PRF :RCT, WCT, KP;
ROM : CKHE, CKLE, SKP, DT;

Note ** : PM pins include SD, DSLP, and DSLPLV

Note *** : ROM does not have DSLP and Redundancy features

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2.1.6 Logic Truth Table
States of memory array content and behavior of output data Q associated with active pins in normal function and
power management modes are described in following tables for different types of compiler.

1PRF/SPSB/SPMB/HSSP compiler:

Function CLK CEB/ WEB/ BWEB/ D/ A/ Q Memory

CEBM WEBM BWEBM DM AM contents
Standby L/H H - - - - No change No change
Deselect ❫ H - - - - No change No change
Read ❫ L H - - a mem[a][i] No change
Write bit[i] ❫ L L L d[i] a No change mem[a][i]=d[i]
Write bit[i] mask ❫ L L bweb[i]=H - a No change No change in
mem[a][i]

Table 2.13: Active pins in normal function mode for 1PRF/SPSB/SPMB/ HSSP

ROM compiler :

Function CLK CEB/ A/ AM Q Memory

CEBM contents
Standby L/H H - No change No change
Deselect ❫ H - No change No change
Read ❫ L a mem[a][i] No change

Table 2.14: Active pins in normal function mode for ROM

2PRF compiler :

Function CLKR CLKW REB WEB BWEB D AB AA Q[i] Memory

content
Standby L/H L/H H H - - - - no change no change
Deselect ❫ ❫ H H - - - - no change no change
Read ❫ - L H - - b - mem[b][i] no change
W* bit[i] - ❫ H L bweb[i]=L d[i] - a no change mem[a][i]=d[i]
W* bit[i] - ❫ H L bweb[i]=H - - a no change no change in
Mask mem[a][i]
W* bit[i] and ❫ ❫ L L bweb[i]=L d[i] b a X mem[a][i]=d[i]
Read a==b
W* bit[i] ❫ ❫ L L bweb[i]=H - b a mem[b][i] no change in
Mask and mem[a][i]
Read a==b
W* and R* ❫ ❫ L L bweb[i]=L d[i] b a mem[b][i] mem[a][i]=d[i]
a!=b
R* then W* ❫ ❫ L L bweb[i]=L d[i] b a mem[b][i] mem[a][i]=d[i]
a==b
W* then R* ❫ ❫ L L bweb[i]=L d[i] b a mem[b][i]=d[i] mem[a][i]=d[i]
a==b
Note : W* means Write, R* means Read.

Table 2.15: Active pins in normal function mode for 2PRF

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1PRF/SPSB/SPMB/HSSP/compiler:

Function SD DSLP CLK CEB/ WEB/ BWEB/ D/ A/ BIST RED. FAD. Q PUD.DSLP PUD.SD Memory
CEBM WEBM BWEBM DM AM Contents
Deep sleep L** H -/Z -/Z -/Z -/Z -/Z -/Z -/Z -/Z -/Z L H L No change
Deep sleep L** ❫ L/H - - - - - - - - X ❫ L No change
(enter)
Deep sleep L** ❴ L - - - - - - - - X ❴ L No change
(wake up)
Shut down H - -/Z -/Z -/Z -/Z -/Z -/Z -/Z -/Z -/Z L - H all X
Shut down ❫ - L/H - - - - - - - - X - ❫ all X
(enter)
Shut down ❴ L*** L/H - - - - - - - - X L ❴ all X
(wake up)

Note1 : RED. stands for REDENIO

Note2 : FAD. stands for FADIO[J:0]
Note3 : PUD.SD stands for PUDELAY SD
Note4 : PUD.DSLP stands for PUDELAY DSLP
Note5 : L** indicates SD must be ”Low” before entering to or wakeup from deep sleep mode
Note6 : L*** indicates DSLP must be ”Low” before wakeup from shut down mode

Table 2.16: Active pins in deep sleep and shut down modes for 1PRF/SPSB/SPMB/ HSSP/

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2PRF compiler :

Function SD DSLP CLKR/ REB/ WEB/ BWEB/ D/ AA/AMA BIST RED. FAD. Q PUD.DSLP PUD.SD Memory
CLKW REBM WEBM BWEBM DA AB/AMB con-
tent
Deep Sleep L** H -/Z -/Z -/Z -/Z -/Z -/Z -/Z -/Z -/Z L H L No
change
Deep Sleep L** ❫ L/H - - - - - - - - X ❫ L No
(enter) change
Deep Sleep L** ❴ L - - - - - - - - X ❴ L No
(wake up) change
Shut down H - -/Z -/Z -/Z -/Z -/Z -/Z -/Z -/Z -/Z L - H All x
Shut down ❫ - L/H - - - - - - - - X - ❫ All x
(enter)
Shut down ❴ L*** L/H - - - - - - - - X L ❴ All x
(wake up)
Note1 : RED. stands for REDENIO
Note2 : FAD. stands for FADIO[J:0]
Note3 : PUD.DSLP stands for PUDELAY DSLP
Note4 : PUD.SD stands for PUDELAY SD
Note5 : L** indicates SD must be ”Low” before entering to or wakeup from deep sleep mode
Note6 : L*** indicates DSLP must be ”Low” before wakeup from shut down mode

Table 2.17: Active pins in deep sleep and shut down modes for 2PRF

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2.1.7 Hazard Conditions
Hazard conditions happen when certain inputs of memory are unknown or floating, they could result in unknown
output data Q and/or corrupted memory content.

2.1.7.1 Hazard Conditions without redundancy pins

States of pin combinations in following tables that do not exist in function truth table may cause unknown memory
content or output data. User should be aware of or avoid these combinations.

1PRF/SPSB/ SPMB /HSSP/ compiler:

SD DSLP BIST CLK CEB WEB A BWEB D mem Output Q

CEBM WEBM AM BWEBM DM
X/Z - - - - - - - - all X X
L X/Z - - - - - - - all X X
L L X/Z - - - - - - all X X
L L L/H X/Z - - - - - all X X
L L L/H ❫ X/Z - - - - all X X
L L L/H ❫ L X/Z - - - all X X
L L L/H ❫ L H X/Z - - hold* X
L L L/H ❫ L L X/Z - - X hold
L L L/H ❫ L L valid X/Z - mem[a][i]=X hold
L L L/H ❫ L L valid valid X/Z mem[a][i]=X hold
Note *: memory content can be hold when address is ”logic unknown” in read operation, where ”logic unknown” is that address is static
at either 0 or 1 but not ”timing unknown” before enable. The ”timing unknown” means that it is caused by insufficient setup/hold
time.
Note : There are branched conditions that reflect real circuit behavior and will not flush memory content and/or output Q.

Table 2.18: SRAM hazard conditions for 1PRF/SPSB/SPMB/HSSP compilers

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2PRF compiler:

SD DSLP BIST CLKW WEB AA BWEB D Memory Con-

WEBM AMA BWEBM DM tent
X/Z - - - - - - - all X
L X/Z - - - - - - all X
L L X/Z - - - - - all X
L L L/H X/Z - - - - all X
L L L/H ❫ X/Z - - - all X
L L L/H ❫ X/Z L/H - - mem[AA/AMA]=X
L L L/H ❫ H X/Z - - hold
L L L/H ❫ L L/H X/Z - mem[AA/AMA]=X
L L L/H ❫ H L/H X/Z - hold
L L L/H ❫ L L/H H X/Z hold
L L L/H ❫ L L/H L X/Z mem[AA/AMA]=X

Table 2.19: SRAM hazard conditions for 2PRF: write cycle

SD DSLP BIST CLKR REB/ REBM AB/ Output

AMB Q
X/Z - - - - - X
L X/Z - - - - X
L L X/Z - - - X
L L L/H X/Z - - X
L L L/H ❫ X/Z - X
L L L/H ❫ L X/Z X
L L L/H ❫ H X/Z hold
Note : Any input hazard violation to read port does not cause content corrupted in memory cell.
Note : There are branched conditions that reflect real circuit behavior and will not flush memory content and/or output Q.

Table 2.20: SRAM hazard conditions for 2PRF : read cycle

ROM compiler:

SD BIST CLK CEB A Output PUDELAY

Q
X/Z - - - - X X/Z
L X/Z - - - X L
L L X/Z - - X L
L L ❫ X/Z - X L
L L ❫ H X/Z hold L
L L ❫ L X/Z X L
Note : There are branched conditions that reflect real circuit behavior and will not flush memory content and/or output Q.

Table 2.21: SRAM hazard conditions for ROM

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2.1.7.2 Hazard Conditions with redundancy pins
States of pin combinations in following tables that do not exist in repair function truth table may cause unknown
memory content or output data. User should be aware of or avoid these combinations.

1PRF/SPSB/SPMB /HSSP compiler:

SD DSLP REDENIO FADIO[J:0] BIST CLK CEB/ WEB/ Q mem

CEBM WEBM
L L X/Z - - ❫ H - all X hold
L L X/Z - - ❫ L H all X hold
L L X/Z - - ❫ L L all X all X
L L H X/Z - ❫ H - all X hold
L L H X/Z - ❫ L H all X hold
L L H X/Z - ❫ L L all X all X
L L L X/Z - L/H - - hold hold

Table 2.22: SRAM hazard conditions: redundancy fuse setting cycle for 1PRF/SPSB/SPMB/HSSP compilers

2PRF compiler:

SD DSLP REDENIO FADIO[J:0] BIST CLKR/ CLKW REB WEB Q Mem

L L X/Z - - ❫ H H all X hold
L L X/Z - - ❫ L H all X hold
L L X/Z - - ❫ H L all X all X
L L X/Z - - ❫ L L all X all X
L L H X/Z - ❫ H H all X hold
L L H X/Z - ❫ L H all X hold
L L H X/Z - ❫ H L all X all X
L L H X/Z - ❫ L L all X all X
L L L X/Z - L/H - - hold hold

Table 2.23: SRAM hazard conditions: redundancy fuse setting cycle for 2PRF compiler

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General terms used in the above truth or hazard tables
Condition:

❼ L : logic low

❼ H : logic high

❼ X : unpredictable data, it can be either ”0” or ”1” but not deterministic

❼ Z : high impedance

❼ - : L, H, X, not include Z

❼ valid : stable ( could be 0 or could be 1 ) in fixed condition

❼ ❫: signal rising edge

Output Q:

❼ hold : keep previous state

❼ X : unpredictable data, it can be either ”0” or ”1” but not deterministic

❼ L : logic low

❼ data-out : output of normal read function

Mem:

❼ mem[a] = X : memory content is unpredictable at the specific memory address

❼ mem[a][i] = X : memory content is unpredictable at the specific memory address and specific IO

❼ hold : keep the previous state

❼ all X : all memory contents are unpredictable

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2.1.8 Timing Parameter
All timing parameters are listed in following tables and described with pin of reference and measurement. All timing
is measured from a logic threshold at 50% of the power supply VDD.

1PRF/SPSB/SPMB/HSSP/ compiler:

Parameter Definition From To

tcd CLK to valid Q (data output) CLK❫ Q
thold CLK to invalid data output CLK❫ Invalid Q
tbists BIST setup before CLK❫ BIST CLK❫
tbisth BIST hold after CLK❫ CLK❫ BIST
tcs CEB setup before CLK❫ CEB CLK❫
tch CEB hold after CLK❫ CLK❫ CEB
tcms CEBM setup before CLK❫ CEBM CLK❫
tcmh CEBM hold after CLK❫ CLK❫ CEBM
tas A setup before CLK❫ A CLK❫
tah A hold after CLK❫ CLK❫ A
tams AM setup before CLK❫ AM CLK❫
tamh AM hold after CLK❫ CLK❫ AM
tws WEB setup before CLK❫ WEB CLK❫
twh WEB hold after CLK❫ CLK❫ WEB
twms WEBM setup before CLK❫ WEBM CLK❫
twmh WEBM hold after CLK❫ CLK❫ WEBM
tbws BWEB setup before CLK❫ BWEB CLK❫
tbwh BWEB hold after CLK❫ CLK❫ BWEB
tbwms BWEBM setup before CLK❫ BWEBM CLK❫
tbwmh BWEBM hold after CLK❫ CLK❫ BWEBM
tds D setup before CLK❫ D CLK❫
tdh D hold after CLK❫ CLK❫ D
tdms DM setup before CLK❫ DM CLK❫
tdmh DM hold after CLK❫ CLK❫ DM
tcyc Minimum CLK cycle time CLK❫ CLK❫
tckh Minimum CLK Pulse High CLK❫ CLK❴
tckl Minimum CLK Pulse Low CLK❴ CLK❫

Table 2.24: Timing specification symbols and definitions of 1PRF/SPSB/SPMB/HSSP compilers

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2PRF compiler:

Parameter Definition From To

tws WEB setup before CLKW❫ WEB CLKW❫
twh WEB hold after CLKW❫ CLKW❫ WEB
twms WEBM setup before CLKW❫ WEBM CLKW❫
twmh WEBM hold after CLKW❫ CLKW❫ WEBM
taas AA setup before CLKW❫ AA[M-1:0] CLKW❫
taah AA hold after CLKW❫ CLKW❫ AA[M-1:0]
tamas AMA setup before CLKW❫ AMA[M-1:0] CLKW❫
tamah AMA hold after CLKW❫ CLKW❫ AMA[M-1:0]
tds D setup before CLKW❫ D[N-1:0] CLKW❫
tdh D hold after CLKW❫ CLKW❫ D[N-1:0]
tdms DM setup before CLKW❫ DM[N-1:0] CLKW❫
tdmh DM hold after CLKW❫ CLKW❫ DM[N-1:0]
tbws BWEB setup before CLKW❫ BWEB[N-1:0] CLKW❫
tbwh BWEB hold after CLKW❫ CLKW❫ BWEB[N-1:0]
tbwms BWEBM setup before CLKW❫ BWEBM[N-1:0] CLKW❫
tbwmh BWEBM hold after CLKW❫ CLKW❫ BWEBM[N-1:0]
tbists BIST setup before CLKW❫/CLKR❫ BIST CLKW❫/CLKR❫
tbisth BIST hold after CLKW❫/CLKR❫ CLKW❫/CLKR❫ BIST
trs REB setup before CLKR❫ REB CLKR❫
trh REB hold after CLKR❫ CLKR❫ REB
trms REBM setup before CLKR❫ REBM CLKR❫
trmh REBM hold after CLKR❫ CLKR❫ REBM
tabs AB setup before CLKR❫ AB[M-1:0] CLKR❫
tabh AB hold after CLKR❫ CLKR❫ AB[M-1:0]
tambs AMB setup before CLKR❫ AMB[M-1:0] CLKR❫
tambh AMB hold after CLKR❫ CLKR❫ AMB[M-1:0]
trckh Minimum CLKR pulse high CLKR❫ CLKR❴
trckl Minimum CLKR pulse low CLKR❴ CLKR❫
twckh Minimum CLKW pulse high CLKW❫ CLKW❴
twckl Minimum CLKW pulse low CLKW❴ CLKW❫
twcyc Minimum CLKW cycle time CLKW❫ CLKW❫
trcyc Minimum CLKR cycle time CLKR❫ CLKR❫
trwcc Minimum read to write clock separation CLKR❫ CLKW❫
twrcc Minimum write to read clock separation CLKW❫ CLKR❫
tcd Clock to valid Q (data output) CLKR❫ Q
thold Clock to invalid Q (data output) CLKR❫ Q

Table 2.25: Timing specification symbols and definitions of 2PRF compiler

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ROM compiler:

Parameter Definition From To

tcd CLK to valid Q (data output) CLK❫ Q
thold CLK to invalid data output CLK❫ Invalid Q
tas Address setup before CLK❫ A[M-1:0] CLK❫
tah Address hold after CLK❫ CLK❫ A[M-1:0]
tcs CEB setup before CLK❫ CEB CLK❫
tch CEB hold after CLK❫ CLK❫ CEB
tams Address AM setup before CLK❫ AM[M-1:0] CLK❫
tamh Address AM hold after CLK❫ CLK❫ AM[M-1:0]
tcms CEBM setup before CLK❫ CEBM CLK❫
tcmh CEBM hold after CLK❫ CLK❫ CEBM
tbists BIST setup before CLK❫ BIST CLK❫
tbisth BIST hold after CLK❫ CLK❫ BIST
tckh Minimum CLK Pulse High CLK ❫ CLK ❴
tckl Minimum CLK Pulse Low CLK ❴ CLK ❫
tcyc Minimum Cycle Time CLK ❫ CLK ❫

Table 2.26: Timing specification symbols and definitions of ROM compiler

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2.1.9 Timing Waveform
All timing parameters are illustrated with input signal waveforms in following sections.

2.1.9.1 Timing waveform of read/write operation

1PRF/SPSB/SPMB/HSSP compiler:

Figure 2.4: Timing protocol of SRAM Read-only operation

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1PRF/SPSB/SPMB/HSSP compiler:

Figure 2.5: Timing protocol of SRAM Write-only operation

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2PRF compiler :

Figure 2.6: Timing protocol of port contention Read then Write (AA=AB)

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2PRF compiler :

Figure 2.7: Timing protocol of port contention Write then Read (AA=AB, D=D0)

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ROM compiler:

Figure 2.8: Timing protocol of ROM Read-only operation

Figure 2.9: Timing diagram of ROM unknown Q state between clock cycles with same address

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 Figure 2.10: Clock Separation with Addresses Contention

2.1.9.2 Timing protocol of BIST for all compilers:

Figure 2.11: Timing protocol of BIST

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2.1.9.3 Timing waveform of redundancy function
Redundancy function is not applicable to ROM compiler.

Figure 2.12: Timing protocol of redundancy function

Redundancy behavior :

❼ If REDENIO toggles, or FADIO[J:0] toggle when REDENIO=1’b1, Q will become X.

❼ If REDENIO toggles, or FADIO[J:0] toggle when REDENIO=1’b1 during write operation(WEB=L), memory
contents will become X.

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2.1.9.4 Timing waveform of TSEL pins
TSEL pin states are required to be stable with default values during normal operation, changing values during oper-
ation cycle could result in function failure.

Figure 2.13: Timing protocol of TSEL pins

Parameter Definition From To

ttests TSEL pins setup before CLK❫ TSEL pins CLK❫
ttesth TSEL pins hold after CLK❫ CLK❫ TSEL pins

Table 2.27: Timing specification for TSEL pin

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2.1.10 Integration Guideline of Dual Rail and Power Management
Definition of power domains and pins for Dual Rail option, and rail connections are described in following sections:

2.1.10.1 Definition and requirement of power domains and power management pins
❼ All compiler types provide Interface Dual Rail (IDR) for lowest VDDmin with level shifter implemented at
interface.

❼ VDD and VDDM represent power pins of two different domains as dual rail supplying voltages to memory
macro, where VDD domain is the outer rail of macro, same as the domain of input signal pins and output Q
pins, VDDM domain is the inner rail of macro for partial periphery and cell array. Internal power switches are
embedded separately for both VDD and VDDM rails to provide users with capability of power management
functions to save leakage power.
❼ All input/output pins are in VDD domain.

❼ In order to have correct function of Dual Rail option, VDD and VDDM pins must be connected to external
VDD and VDDM respectively.

❼ VDD supply voltage is not allowed to have 100mV higher than VDDM supply voltage in all kinds of operation
modes. VDD can not exceed 300mV lower than VDDM in all kinds of operation modes except SD mode.
❼ VDD power rail must always ramp up first to guarantee memory function.

❼ When VDD is ON, VDDM can be floating without extra leakage if SD or DSLP is asserted logic high. Refer to
Figure 2.15.
❼ If DSLP pin is used to control power ramp up/down sequence, SD pin is required to be tied to 0V. In this case,
PUDELAY DSLP pin is not allowed to be used to connect to SD pin of other macros.

❼ DSLP mode can be expanded with pin DSLPLV which makes supply to array with diode drop if DSLPLV=0 as
well as supply to array with direct connection to external rail if DSLPLV=1.

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Figures below illustrate different power domains of in/output pins and power ramp up/down sequence and requirement.

Figure 2.14: Illustration of power rails

Figure 2.15: VDDM power gating with SD or DSLP asserted logic high

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2.1.10.2 Voltage operation range of DualRail
❼ Summary of VDDmin and VDDMmin

❼ Voltage separation of VDD and VDDM

– IDR SVT/LVT/uLVT

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2.1.10.3 Power ramping sequence for dual rail memory
Sequence of power ramping up/down with states of PM pins and output Q state are illustrated in following waveform
diagrams.

VDD power rail must always ramp up first to guarantee memory function. During VDD is power on and VDDM is
not power on, VDDM must be at 0V voltage level to avoid leakage on VDD rail. During VDDM ramping up, SD
and/or DSLP must be asserted to avoid leakage on VDD rail.

Figure 2.16: Power ramp-up sequence with SD or DSLP asserted logic high

VDDM power rail is recommended to ramp down first with SD and/or DSPLP asserted during VDDM is ramping
down.
VDDM must be at 0V voltage level to avoid leakage on VDD rail. When VDDM is power off and VDD is still power
on.

Figure 2.17: Power ramp-down sequence (VDDM down first) with SD or DSLP asserted logic high

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VDD ramps down earlier than VDDM without SD and/or DSLP assertion is not recommended. During VDD is
ramping down, potential leakage on VDDM rail is unavoidable when SD and/or DSLP are not asserted.
After VDD ramps down, VDD must be at 0V to avoid leakage on VDDM rail.

Figure 2.18: Power ramp-down sequence (VDD down first) with SD or DSLP de-asserted

VDD ramps down earlier than VDDM with SD and/or DSLP assertion is recommended. During VDD is ramping
down, VDDM rail power switch will be clamped until VDD reaches functional Vmin, and the leakage on VDDM rail
can be minimized.
After VDD ramps down, VDD must be at 0V to avoid leakage on VDDM rail.

Figure 2.19: Power ramp-down sequence (VDD down first) with SD or DSLP asserted logic high

Allowed for SD is asserted but Q will be floating due to VDD is off.Isolation is required between memory output and
down stream logic

Figure 2.20: VDD can be power-off when SD=1, VDDM=ON

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2.1.10.4 Truth table for power domain states and power management (PM) pins
States combinations of power domains, PM pins, and result states of output pins and storage content are described in
following tables.
All compilers:
Table below is not applicable to ROM compiler since ROM does not have Deep Sleep feature.

VDD VDDM SD DSLP Q SOC/SOD Memory Scan PUD.SD PUD.DSLP Description

Content Chain
Content
1 1 1 - 0 0 all X all X 1 - Shut down mode, SD has the highest weight
with ”1” to overrule DSLP
1 1 0 1 0 0 keep all X 0 1 Deep sleep mode, and SD has to keep 0
0 1 0 - all x all x all X all X all X all X illegal condition
0 1 1 - all x all x all X all X all X all X Allowed for SD is asserted but Q will be float-
ing due to VDD is off.
Isolation is required between memory output
and down stream logic.
1 0 1 - 0 0 all X all X 1 - Allowed while SD is asserted H (logic 1), the
output Q is clamped low as an isolation to
downstream logic
Internal self SD is generated by embedded
power detector scheme
1 0 0 1 0 0 all X all X all X 1 Allowed while DSLP is asserted H (logic 1),
the output Q is clamped low as an isolation to
downstream logic
Internal self SD is generated by embedded
power detector scheme
1 0 0 0 all x all x all X all X all X 0 Internal self SD is generated by embedded
power detector scheme
Allowed only under VDDM = solid 0V (not
floating) to guarantee power detector can work

Table 2.28: Condition & description of rails with on/off states vs. DSLP/SD

ROM compiler :

VDD VDDM SD Q SOC/SOQ Scan PUDELAY Description

Chain
Content
1 1 1 0 0 all X 1 Shut down mode
0 1 0 all x all x all X all X illegal condition
0 1 1 all x all x all X all X Allowed for SD is asserted but Q will be floating due to VDD is off.
Isolation is required between memory output and down stream logic.
1 0 1 0 0 all X 1 Allowed while SD is asserted H (logic 1), the output Q is clamped low as an isolation to
downstream logic”
1 0 0 all x all x all X all X Internal self SD is generated by embedded power detector scheme
Allowed only under VDDM = solid 0V (not floating) to guarantee power detector can
work

Table 2.29: Condition & description of rails with on/off states vs. SD

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2.1.10.5 Timing waveform of power management
Deep Sleep Mode for all compilers

Waveform diagram(Figure 2.21) below is not applicable to ROM compiler since ROM does not have Deep Sleep feature.

Figure 2.21: Timing protocol of deep sleep mode

Deep Sleep Mode behavior for all compilers ( except ROM) :

❼ DSLP pin is an asynchronous control input pin.

❼ DSLP pin must be asserted high for entering deep sleep mode (1’b1 = power saving) and compliant to setup
and hold time requirement.

❼ Most of input pins can be floating or unknown (x) during deep sleep mode (DSLP = 1’b1) except SD.

❼ After DSLP goes high (1’b1), tdslpx timing shall be met before input pins become floating or unknown (x)
states, Similarly, txdslp timing shall be met before DSLP goes low (1’b0) to ensure input pins are valid (0/1).
❼ The SRAM data output (Q) is logic low after DSLP is asserted (DSLP = 1’b1) with certain waiting time, tdslpq.
While DSLP is still asserted, data output (Q) remains logic low.
❼ SRAM wake up time from deep sleep mode to normal mode (tdslpwk2clk) is required and must be sufficiently
guaranteed for instance to have healthy power supply.
❼ DSLP pin must be asserted high and meets the required timing ”tclk2dslp” for entering deep sleep mode.

❼ DSLP falling edges must be within CLK=0 duration for waking up from DSLP mode.

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 Shut Down Mode for all compilers:
Input signal DSLP and output signal PUDELAY DSLP are not applicable to ROM compiler since ROM does not
have Deep Sleep feature. Please note that PUDELAY SD is renamed as PUDELAY for ROM.

Figure 2.22: Timing protocol of shut down mode

❼ SD pin is an asynchronous control input pin.

❼ SD pin must be asserted high for entering shut down mode.

❼ All input pins except SD and DSLP can be floating or unknown (X) during shut down mode (SD=1’b1). DSLP
pin can be unknown but not floating during shut down mode.

❼ After SD goes high (1’b1) , tsdx timing shall be met before input pins become floating or unknown (x) states.
Similarly, txsd timing shall be met before SD goes low (1’b0) to ensure input pins are valid(0/1).

❼ After SD goes low (wakeup condition) the values of data output (Q) changes from logic low (shut down mode)
to unknown-X (normal stand-by mode), there is no high-Z on output Q.
❼ In order to have DSLP wake-up time of macro behavior matched tdslpwk2clk exactly, a condition of no entering
DSLP mode is required while still in process of SD waking up.
– DSLP must remain asserted low while macro waking up from shut-down mode with SD being asserted low.

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2.1.10.6 Deep Sleep Bypass Mode
For achieving lowest retention power in DSLP mode, a specific pin ”DSLPLV” to bypass retention diodes is provided.
When DSLPLV=1, a power switch is turned on to bypass retention diode in DSLP mode. DSLPLV default setting is 0,
the SRAM array retention voltage is biased by retention diodes. Both leakage number in DSLPLV=1 and DSLPLV=0
are provided in NLDM model.

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2.1.11 Redundancy Repair Setting
2.1.11.1 Column redundancy
One redundant chunk of cell array associating with an IO access is built-in additionally for column repair function. To
enable repair, the REDENIO pin must be ”high”, the defective IO address will be defined by FADIO[J:0]. Once the
repair function is activated for write mode, input data D[m] of this defective IO[m] is shifted to adjacent IO[m+1] and
D[m+1] shifted to IO[m+2] until the last D[n-1] shifted to redundant IO. Whereas the inputs of D[0] to D[m-1] still
enter their original IOs without shifting. For read operation, the data out path follows the same path as write but in
opposite direction. The IO[m+1] outputs its data to Q[m] of the defective IO and IO[m+2] outputs to Q[m+1] until
redundant IO outputs to Q[n-1]. Then same as write, the Q[0] to Q[m-1] receive the outputs of their corresponding
IOs. Due to size of word width, the address to number of IO varies, therefore, the amount of FADIO pins varies
accordingly, table below lists down number of FADIO required for each type of memory.

Compiler MUX Repair IO shift # (S) FADIO[J:0]

2 2 J=1-7
4 1 J=2-7
SPSB
8 1 J=2-6
16 1 J=2-5
4 1 J=2-7
SPMB 8 1 J=2-6
16 1 J=2-5
2 1 J=2-7
HSSP
4 1 J=2-6
1 2 J=2-7
1PRF 2 1 J=2-7
4 1 J=2-6
1 2 J=2-7
2PRF 2 1 J=2-7
4 1 J=2-6

Table 2.30: FADIO[J:0] and repair IO shift number mapping table

Note:
1.n: total IO number
2.S: number of IOs are grouped as one for the data shifting

How to calculate the total number (J) of FADIO[J:0]

1. Check on figure above, Table 2.30: FADIO[J:0] mapping table, to determine the shift (S) of per IO or per 2 IO’s
for different types of memory.

2. Follow the equation below to obtain total number J of FADIO[J:0]:

n/S
J = ceiling(log2 ) − 1

Shifting scheme of input and output data are illustrated for each type of memory in following diagrams.

1PRF compiler MUX2/4 :

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Figure 2.23: Redundancy shift and decode direction with mux2/4 for 1PRF

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1PRF compiler MUX1:

For mux1 case, the repair mechanism is similar but only differs on that two IOs are grouped as one for the data
shifting.Please refer to Figure 2.24

Figure 2.24: Redundancy shift and decode direction with mux1 for 1PRF

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2PRF compiler MUX2/4:

Figure 2.25: Redundancy shift and decode direction with mux2/4 for 2PRF

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2PRF compiler MUX1:
For mux1 case, the repair mechanism is similar but only differs on that two IOs are grouped as one for the data
shifting.
Please refer to Figure 2.26

Figure 2.26: Redundancy shift and decode direction with mux1 for 2PRF

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SPSB compiler MUX4/8/16 :

Figure 2.27: Redundancy shift and decode direction with mux4/8/16 for SPSB

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 SPSB compiler MUX 2:
For mux2 case, the repair mechanism is similar but only differs on that two IOs are grouped as one for the data shifting.

Figure 2.28: Redundancy shift and decode direction with mux2 for SPSB

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SPMB compiler :

Figure 2.29: Redundancy shift and decode direction for SPMB

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 HSSP compiler :
Two redundant chunks of cell array associating with IO access are built-in additionally in left and right banks for
column repair function respectively. To enable repair, the REDENIO pin must be ”high”, the defective IO address
will be defined by FADIO[J:0]. If the failure bit is located in left bank, once the repair function is activated for write
mode, input data D[m] of this defective IO[m] is shifted to adjacent IO[m+1] and D[m+1] shifted to IO[m+2] until
the last D[n-1] shifted to redundant IO. Whereas the inputs of D[0] to D[m-1] still enter their original IOs without
shifting. For read operation, the data out path follows the same path as write but in opposite direction. The IO[m+1]
outputs its data to Q[m] of the defective IO and IO[m+2] outputs to Q[m+1] until redundant IO outputs to Q[n-1].
Then same as write, the Q[0] to Q[m-1] receive the outputs of their corresponding IOs. If the failure bit is located in
right bank, the direction of shifting is opposite. Though 2 redundant chunks are built in, only one defect IO can be
repaired. Figure 2.30 below illustrates the direction of shifting in left and right bank.

Figure 2.30: Redundancy shift and decode direction for HSSP

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2.1.12 DFT Scheme
2.1.12.1 Introduction
To increase test coverage and improve overall testability at the SOC level the compiler is designed with DFT and
BIST functions. Input multiplexers are embedded in the memory macro to provide interface to the memory BIST.
The compiler also supports scan chain data bypass function for ATPG test.

❼ BIST interface

– All input pins to the memory core (except the clock input) can be from normal function path(D, BWEB,
A, CEB..) or BIST logic path (DM, BWEBM, AM, CEBM..).
– The interface multiplexers are controlled by BIST input signal for path selection.
❼ Scan chain with synchronous write through (bypass) function.

– The compiler supports Synchronous-Write-Through (SWT) bypass DFT function.

– The active high asynchronous DFTBYP input is used to activate the SWT bypass function.
– Multiple chains are implemented independently according to the location and numbers of IO, control signals.
Scan FFs(Flip-Flop) are chained to provide scan in, scan out and data bypass function from respected
memory input signals to Q outputs.
– The scan FFs capture their inputs on the rising edge of the macro CLK (clock) when the SE input is forced
low.
– The scan out of the memory scan chains (SOD, SOC) are valid at the negative edge of the clock.
– The output timing of data bypass is designed to be the same as normal memory access time. The output
timing is characterized in default setting of test pins for both normal and DFT modes.
– Please refer to section 4.2 ”TSMC SRAM DFT Application Notes” for detail implementation guidelines.

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2.1.12.2 Block Diagram of Scan Flip-Flop
In this section, the SWT for input signal pins are illustrated in following figures for each type of memory, detail
grouping of pins, for instance, PIN A and PIN B groups are listed in tables of section ”Scan Chain Configuration
Order”.

1PRF/SPSB/SPMB/HSSP/ compiler :

Figure 2.31: Scan chain block diagram of 1PRF, SPSB, SPMB, HSSP compilers

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2PRF compiler :
Note : The pin order of PIN A, PIN B and PIN C group are listed in Table 2.32

Figure 2.32: Scan chain block diagram of 2PRF compiler

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ROM compiler :

Figure 2.33: Scan chain block diagram of ROM compiler

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2.1.12.3 Scan Chain Configuration
Orientation of scan register chaining for input control signals and data is illustrated in following figures.

1PRF/ 2PRF/ SPSB/ SPMB/ HSSP compilers :

Figure 2.34: Scan chain of 1PRF, 2PRF, SPSB, SPMB,HSSP, compilers

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ROM compiler :

Figure 2.35: Scan chain of ROM compiler

2.1.12.4 Scan Chain Configuration Order

Chaining order and length of scan registers associated with number of IO and MUX options are described in following
tables.

1PRF compiler:

1PRF MUX Configuration Order

SIC –>SOC 1 PIN A group (A[6:0]) –> PIN B group (CEB,WEB)
SIC –>SOC 2 PIN A group (A[2:0],A[7:4],WEB) –> PIN B group (A[3],CEB)
SIC –>SOC 4 PIN A group (A[8:1]) –> PIN B group (A[0],CEB,WEB)
SID[0] –>SOD[0] 1 N=2n+2;
when n=even, IO[0] to IO[n+1]
when n=odd, IO[0] to IO[n]
SID[0] –>SOD[0] 2/4 N=n;
when n=even, IO[0] to IO[(n/2)-1]
when n=odd, IO[0] to IO[(n-1)/2]
SID[1] –>SOD[1] 1 N=2n+2;
when n=even, IO[2n+1] to IO[n+2]
when n=odd, IO[2n+1] to IO[n+1]
SID[1] –>SOD[1] 2/4 N=n;
when n=even, IO[n-1] to IO[(n/2)]
when n=odd, IO[n-1] to IO[(n+1)/2]
N : number of IO

Table 2.31: Scan chain configuration order of 1PRF compiler

2PRF compiler :

2PRF MUX Configuration Order

SIC –>SOC 4 PIN A group (AA[1:0],WEB,AA[9:6]) –> PIN B group (AA[5:2],AB[2:5]) –> PIN C group (AB[6:9],REB,AB[0:1])
SIC –>SOC 2 PIN A group (AA[0],WEB,AA[8:5]) –> PIN B group (AA[4:1],AB[1:4]) –> PIN C group (AB[5:8],REB,AB[0])
SIC –>SOC 1 PIN A group (WEB,AA[7:4]) –> PIN B group (AA[3:0],AB[0:3]) –> PIN C group (AB[4:7],REB)
SID[0] –>SOD[0] 1 N=2n+2;
when n=even, IO[0] to IO[n+1]
when n=odd, IO[0] to IO[n]
SID[0] –>SOD[0] 2/4 N=n;
when n=even, IO[0] to IO[(n/2)-1]
when n=odd, IO[0] to IO[(n-1)/2]
SID[1] –>SOD[1] 1 N=2n+2;
when n=even, IO[2n+1] to IO[n+2]
when n=odd, IO[2n+1] to IO[n+1]
SID[1] –>SOD[1] 2/4 N=n;
when n=even, IO[n-1] to IO[(n/2)]
when n=odd, IO[n-1] to IO[(n+1)/2]
N : number of IO

Table 2.32: Scan chain configuration order of 2PRF compiler

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SPSB compiler:

SPSB MUX Configuration Order

SIC –>SOC 2 PIN A group (A[6:5],A[3:2]]) –> PIN B group (CEB,WEB,A[8:7],A[4],A[1:0]])
SIC –>SOC 4 PIN A group (A[8:1]) –> PIN B group (A[0],A[9],CEB,WEB)
SIC –>SOC 8 PIN A group (A[0],A[4:3],A[10:6]) –> PIN B group (A[2:1],A[5],CEB,WEB)
SIC –>SOC 16 PIN A group (A[0],A[5:4],A[11:7]) –> PIN B group (A[3:1],A[6],CEB,WEB)
SID[0] –>SOD[0] 2 N=2n+2;
when n=even, IO[0] to IO[n+1]
when n=odd, IO[0] to IO[n]
SID[0] –>SOD[0] 4/8/16 N=n;
when n=even, IO[0] to IO[(n/2)-1]
when n=odd, IO[0] to IO[(n-1)/2]
SID[1] –>SOD[1] 2 N=2n+2;
when n=even, IO[2n+1] to IO[n+2]
when n=odd, IO[2n+1] to IO[n+1]
SID[1] –>SOD[1] 4/8/16 N=n;
when n=even, IO[n-1] to IO[(n/2)]
when n=odd, IO[n-1] to IO[(n+1)/2]
N : number of IO

Table 2.33: Scan chain configuration order of SPSB compiler

SPMB compiler:

SPMB MUX Configuration Order

SIC –>SOC 4 PIN A group (A[4:11]) –> PIN B group (A[0:3],CEB,WEB)
SIC –>SOC 8 PIN A group (A[5:12]) –> PIN B group (A[0:4],CEB,WEB)
SIC –>SOC 16 PIN A group (A[6:13]) –> PIN B group (A[0:5],CEB,WEB)
SID[0] –>SOD[0] 4/8/16 N=n;
when n=even, IO[0] to IO[(n/2)-1]
when n=odd, IO[0] to IO[(n-1)/2]
SID[1] –>SOD[1] 4/8/16 N=n;
when n=even, IO[n-1] to IO[(n/2)]
when n=odd, IO[n-1] to IO[(n+1)/2]
N : number of IO

Table 2.34: Scan chain configuration order of SPMB compiler

HSSP compiler:

HSSP MUX Configuration Order

SIC –>SOC 4 PIN A group (A[9:2]) –> PIN B group (A[10],A[1:0],CEB,WEB)
SIC –>SOC 2 PIN A group (A[8:1]) –> PIN B group (A[0],CEB,WEB)
SID[0] –>SOD[0] 2/4 N=n;
when n=even, IO[0] to IO[(n/2)-1]
when n=odd, IO[0] to IO[(n-1)/2]
SID[1] –>SOD[1] 2/4 N=n;
when n=even, IO[n-1] to IO[(n/2)]
when n=odd, IO[n-1] to IO[(n+1)/2]

Table 2.35: Scan chain configuration order of HSSP compiler

ROM compiler:

ROM MUX Configuration Order

SIC –>SOC 16 PIN A group (A[8],A[6],A[10],A[4],A[2],A[0],A[12]) –> PIN B group (A[11],A[13],A[1],A[3],A[9],A[5],A[7],CEB)
SID[0] –>SOD[0] 16 N=n;
when n=even, IO[0] to IO[(n/2)-1]
when n=odd, IO[0] to IO[(n-1)/2]
SID[1] –>SOD[1] 16 N=n;
when n=even, IO[n-1] to IO[(n/2)]
when n=odd, IO[n-1] to IO[(n+1)/2]
N : number of IO

Table 2.36: Scan chain configuration order of ROM compiler

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2.1.12.5 Scan Chain Truth Table
Behavior of functional, scan capture, scan shift and debug shift modes are described in following tables.

1PRF/SPSB/SPMB/ HSSP/ compiler:

Mode DFTBYP SE BIST CLK SOC, SOD[1:0]* Q[i]

Functional L L L/H ❫ SOC=the last Qc in scan chain, mem[a][i] @ Read,
Mode
SOD[0]=the last Qs in scan chain [0], No change @ Write
SOD[1]=the last Qs in scan chain [1]
Capture Mode H L L/H ❫ SOC=the last Qc in scan chain, D[i] XOR BWEB[i]
SOD[0]=the last Qs in scan chain [0],
SOD[1]=the last Qs in scan chain [1]
Shift Mode H H L/H ❫ SOC = the Qc before the last one in scan chain, Corresponding SI[i]
SOD[0] = the Qs before the last one in scan chain [0], from scan chain FF[i]
SOD[1] = the Qs before the last one in scan chain [1]
Debug Shift L H L/H ❫ SOC = the Qc before the last one in scan chain, Corresponding SI[i]
Mode SOD[0] = the Qs before the last one in scan chain [0], from scan chain FF[i]
SOD[1] = the Qs before the last one in scan chain [1]
Q : sram output
Qc[i] : the output for the i-th control scan FF, associated with SIC
Qs[i] : the output for the i-th data scan FF, associated with SID
D[i] : the output for the i-th data input
Note * : SOC and SOD[1:0] are related to CLK falling edge

Table 2.37: Scan chain truth table for all compiler (except 2PRF and ROM)

2PRF compiler:

Mode DFTBYP SE BIST CLKR CLKW SOC, SOD[1:0]* Q[i]

Functional L L L/H ❫ ❫ SOC=the last Qc in scan chain, mem[a][i] @ Read,
Mode
SOD[0]=the last Qs in scan chain [0], No change @ Write
SOD[1]=the last Qs in scan chain [1]
Capture Mode H L L/H - ❫ SOC=the last Qc in scan chain, Corresponding Qs[i]
SOD[0]=the last Qs in scan chain [0], from scan chain FF
SOD[1]=the last Qs in scan chain [1]
Shift Mode H H L/H - ❫ SOC = the Qc before the last one in scan chain, Corresponding SI[i]
SOD[0] = the Qs before the last one in scan chain [0], from scan chain FF[i]
SOD[1] = the Qs before the last one in scan chain [1]
Debug Shift L H L/H - ❫ SOC = the Qc before the last one in scan chain, Previous memory Q[i]
Mode SOD[0] = the Qs before the last one in scan chain [0], @ read ( no change )
SOD[1] = the Qs before the last one in scan chain [1]
Q : sram output
Qc[i] : the output for the i-th control scan FF, associated with SIC
Qs[i] : the output for the i-th data scan FF, associated with SID
Note * : SOC and SOD[1:0] are related to CLKW falling edge

Table 2.38: Scan chain truth table for 2PRF compiler

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ROM compiler:

Mode DFTBYP SE BIST CLK SOC, SOQ[1:0]* Q[i]

Functional L L L/H ❫ SOC=the last Qc in scan chain, mem[a][i] @ Read,
Mode
SOQ[0]=the last Qs in scan chain [0],
SOQ[1]=the last Qs in scan chain [1]
Capture Mode H L L/H ❫ SOC=the last Qc in scan chain, Corresponding SI[i]
SOQ[0]=the Qs before the last one in scan chain [0], from scan chain FF[i]
SOQ[1]=the Qs before the last one in scan chain [1]
Shift Mode H H L/H ❫ SOC = the Qc before the last one in scan chain, Corresponding SI[i]
SOQ[0] = the Qs before the last one in scan chain [0], from scan chain FF[i]
SOQ[1] = the Qs before the last one in scan chain [1]
Debug Shift L H L/H ❫ SOC = the Qc before the last one in scan chain, Previous memory Q[i]
Mode SOQ[0] = the Qs before the last one in scan chain [0], @ read ( no change )
SOQ[1] = the Qs before the last one in scan chain [1]
Q : sram output
Qc[i] : the output for the i-th control scan FF, associated with SIC
Qs[i] : the output for the i-th data scan FF, associated with SIQ
Note * : SOC and SOQ[1:0] are related to CLK falling edge

Table 2.39: Scan chain truth table for ROM compiler

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2.1.12.6 Timing Parameters
Timing parameters related to DFT scheme are listed in following tables for each type of memory.

1PRF/SPSB/SPMB/HSSP/ compiler:

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Parameter Definition From To
tdfts SWT enable pin setup time DFTBYP CLK❫
tdfth SWT enable pin hold time CLK❫ DFTBYP
tses Scan enable pin setup time SE CLK❫
tseh Scan enable pin hold time CLK❫ SE
tsids Data scan input setup time SID CLK❫
tsidh Data scan input hold time CLK❫ SID
tsics Control scan input setup time SIC CLK❫
tsich Control scan input hold time CLK❫ SIC
tsodq sc Delay from CLK to valid data scan output SOD in DFT capture mode CLK❴ SOD
tsodqh sc Delay from CLK to invalid data scan output SOD in DFT capture mode CLK❴ SOD
tsocq sc Delay from CLK to valid data scan output SOC in DFT capture mode CLK❴ SOC
tsocqh sc Delay from CLK to invalid data scan output SOC in DFT capture mode CLK❴ SOC
tsodq ss Delay from CLK to valid data scan output SOD in DFT shift mode CLK❴ SOD
tsodqh ss Delay from CLK to invalid data scan output SOD in DFT shift mode CLK❴ SOD
tsocq ss Delay from CLK to valid data scan output SOC in DFT shift mode CLK❴ SOC
tsocqh ss Delay from CLK to invalid data scan output SOC in DFT shift mode CLK❴ SOC
tcddft Delay from CLK to valid output Q with DFTBYP = HIGH CLK❫ Q
tholddft Delay from CLK to invalid output Q with DFTBYP = HIGH CLK❫ Q
tdslpsoc SOC(low) delay time after DSLP enable DSLP SOC
tdslpsoch SOC to invalid SOC after DSLP enable DSLP SOC
tdslpsod SOD(low) delay time after DSLP enable DSLP SOD
tdslpsodh SOD to invalid SOD after DSLP enable DSLP SOD
tsdsoc SOC(low) delay time after SD enable SD SOC
tsdsoch SOC to invalid SOC after SD enable SD SOC
tsdsod SOD(low) delay time after SD enable SD SOD
tsdsodh SOD to invalid SOD after SD enable SD SOD
tws sc WEB setup before CLK in DFT mode WEB CLK❫
twh sc WEB hold after CLK in DFT mode CLK❫ WEB
twms sc WEBM setup before CLK in DFT mode WEBM CLK❫
twmh sc WEBM hold after CLK in DFT mode CLK❫ WEBM
tds sc D setup before CLK in DFT mode D CLK❫
tdh sc D hold after CLK in DFT mode CLK❫ D
tdms sc DM setup before CLK in DFT mode DM CLK❫
tdmh sc DM hold after CLK in DFT mode CLK❫ DM
tbws sc BWEB setup before CLK in DFT mode BWEB CLK❫
tbwh sc BWEB hold after CLK in DFT mode CLK❫ BWEB
tbwms sc BWEBM setup before CLK in DFT mode BWEBM CLK❫
tbwmh sc BWEBM hold after CLK in DFT mode CLK❫ BWEBM
tas sc A setup before CLK in DFT mode A CLK❫
tah sc A hold after CLK in DFT mode CLK❫ A
tams sc AM setup before CLK in DFT mode AM CLK❫
tamh sc AM hold after CLK in DFT mode CLK❫ AM
tcs sc CEB setup before CLK in DFT mode CEB CLK❫
tch sc CEB hold after CLK in DFT mode CLK❫ CEB
tcms sc CEBM setup before CLK in DFT mode CEBM CLK❫
tcmh sc CEBM hold after CLK in DFT mode CLK❫ CEBM
tcyc ss Minimum CLK cycle time in Shift mode CLK❫ CLK❫
tckh ss Minimum CLK pulse high in Shift mode CLK❫ CLK❴
tckl ss Minimum CLK pulse low in Shift mode CLK❴ CLK❫
tcyc sc Minimum CLK cycle time in Capture mode CLK❫ CLK❫
tckh sc Minimum CLK pulse high in Capture mode CLK❫ CLK❴
tckl sc Minimum CLK pulse low in Capture mode CLK❴ CLK❫

Table 2.40: Timing specification definitions of 1PRF/SPSB/SPMB/HSSPcompiler

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2PRF compiler :

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Parameter Definition From To
tdfts SWT enable pin setup time DFTBYP CLKW❫
tdfth SWT enable pin hold time CLKW❫ DFTBYP
tses Scan enable pin setup time SE CLKW❫
tseh Scan enable pin hold time CLKW❫ SE
tsids Data scan input setup time SID CLKW❫
tsidh Data scan input hold time CLKW❫ SID
tsics Control scan input setup time SIC CLKW❫
tsich Control scan input hold time CLKW❫ SIC
tsodq sc Delay from CLK to valid data scan output SOD in DFT capture mode CLK❴ SOD
tsodqh sc Delay from CLK to invalid data scan output SOD in DFT capture mode CLK❴ SOD
tsocq sc Delay from CLK to valid data scan output SOC in DFT capture mode CLK❴ SOC
tsocqh sc Delay from CLK to invalid data scan output SOC in DFT capture mode CLK❴ SOC
tsodq ss Delay from CLK to valid data scan output SOD in DFT shift mode CLK❴ SOD
tsodqh ss Delay from CLK to invalid data scan output SOD in DFT shift mode CLK❴ SOD
tsocq ss Delay from CLK to valid data scan output SOC in DFT shift mode CLK❴ SOC
tsocqh ss Delay from CLK to invalid data scan output SOC in DFT shift mode CLK❴ SOC
tcddft Delay from CLKW to valid output Q with DFTBYP = HIGH CLKW❫ Q
tholddft Delay from CLKW to invalid output Q with DFTBYP = HIGH CLKW❫ Q
tdslpsoc SOC(low) delay time after DSLP enable DSLP SOC
tdslpsoch SOC to invalid SOC after DSLP enable DSLP SOC
tdslpsod SOD(low) delay time after DSLP enable DSLP SOD
tdslpsodh SOD to invalid SOD after DSLP enable DSLP SOD
tsdsoc SOC(low) delay time after SD enable SD SOC
tsdsoch SOC to invalid SOC after SD enable SD SOC
tsdsod SOD(low) delay time after SD enable SD SOD
tsdsodh SOD to invalid SOD after SD enable SD SOD
tws sc WEB setup before CLKW❫ in scan mode WEB CLKW
twh sc WEB hold after CLKW❫ in scan mode CLKW WEB
twms sc WEBM setup before CLKW❫ in scan mode WEBM CLKW
twmh sc WEBM hold after CLKW❫ in scan mode CLKW WEBM
tds sc D setup before CLKW❫ in scan mode D CLKW
tdh sc D hold after CLKW❫ in scan mode CLKW D
tdms sc DM setup before CLKW❫ in scan mode DM CLKW
tdmh sc DM hold after CLKW❫ in scan mode CLKW DM
tbws sc BWEB setup before CLKW❫ in scan mode BWEB CLKW
tbwh sc BWEB hold after CLKW❫ in scan mode CLKW BWEB
tbwms sc BWEBM setup before CLKW❫ in scan mode BWEBM CLKW
tbwmh sc BWEBM hold after CLKW❫ in scan mode CLKW BWEBM
taas sc AA setup before CLKW❫ in scan mode AA CLKW
taah sc AA hold after CLKW❫ in scan mode CLKW AA
tamas sc AMA setup before CLKW❫ in scan mode AMA CLKW
tamah sc AMA hold after CLKW❫ in scan mode CLKW AMA
tabs sc AB setup before CLKW❫ in scan mode AB CLKW
tabh sc AB hold after CLKW❫ in scan mode CLKW AB
tambs sc AMB setup before CLKW❫ in scan mode AMB CLKW
tambh sc AMB hold after CLKW❫ in scan mode CLKW AMB
trs sc REB setup before CLKW❫ in scan mode REB CLKW
trh sc REB hold after CLKW❫ in scan mode CLKW REB
trms sc REBM setup before CLKW❫ in scan mode REBM CLKW
trmh sc REBM hold after CLKW❫ in scan mode CLKW REBM
twcyc ss Minimum CLKW cycle time in Shift mode CLKW❫ CLKW❫
twckh ss Minimum CLKW pulse high in Shift mode CLKW❫ CLKW❴
twckl ss Minimum CLKW pulse low in Shift mode CLKW❴ CLKW❫
twcyc sc Minimum CLKW cycle time in Capture mode CLKW❫ CLKW❫
twckh sc Minimum CLKW pulse high in Capture mode CLKW❫ CLKW❴
twckl sc Minimum CLKW pulse low in Capture mode CLKW❴ CLKW❫

Table 2.41: Timing specification definitions of 2PRF compiler

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ROM compiler :

Parameter Definition From To

tdfts SWT enable pin setup time DFTBYP CLK❫
tdfth SWT enable pin hold time CLK❫ DFTBYP
tses Scan enable pin setup time SE CLK❫
tseh Scan enable pin hold time CLK❫ SE
tsiqs Data scan input setup time SIQ CLK❫
tsiqh Data scan input hold time CLK❫ SIQ
tsics Control scan input setup time SIC CLK❫
tsich Control scan input hold time CLK❫ SIC
tsoqq sc Delay from CLK to valid data scan output SOQ in DFT capture mode CLK❴ SOQ
tsoqqh sc Delay from CLK to invalid data scan output SOQ in DFT capture mode CLK❴ SOQ
tsocq sc Delay from CLK to valid data scan output SOC in DFT capture mode CLK❴ SOC
tsocqh sc Delay from CLK to invalid data scan output SOC in DFT capture mode CLK❴ SOC
tsoqq ss Delay from CLK to valid data scan output SOQ in DFT shift mode CLK❴ SOQ
tsoqqh ss Delay from CLK to invalid data scan output SOQ in DFT shift mode CLK❴ SOQ
tsocq ss Delay from CLK to valid data scan output SOC in DFT shift mode CLK❴ SOC
tsocqh ss Delay from CLK to invalid data scan output SOC in DFT shift mode CLK❴ SOC
tcddft Delay from CLK to valid output Q with DFTBYP = HIGH CLK❫ Q
tholddft Delay from CLK to invalid output Q with DFTBYP = HIGH CLK❫ Q
tsdsoc SOC(low) delay time after SD enable SD SOC
tsdsoch SOC to invalid SOC after SD enable SD SOC
tsdsoq SOQ(low) delay time after SD enable SD SOQ
tsdsoqh SOQ to invalid SOQ after SD enable SD SOQ
tas sc A setup before CLK in scan mode A CLK❫
tah sc A hold after CLK in scan mode CLK❫ A
tams sc AM setup before CLK in scan mode AM CLK❫
tamh sc AM hold after CLK in scan mode CLK❫ AM
tcs sc CEB setup before CLK in scan mode CEB CLK❫
tch sc CEB hold after CLK in scan mode CLK❫ CEB
tcms sc CEBM setup before CLK in scan mode CEBM CLK❫
tcmh sc CEBM hold after CLK in scan mode CLK❫ CEBM
tcyc ss Minimum CLK cycle time in Shift mode CLK❫ CLK❫
tckh ss Minimum CLK pulse high in Shift mode CLK❫ CLK❴
tckl ss Minimum CLK pulse low in Shift mode CLK❴ CLK❫
tcyc sc Minimum CLK cycle time in Capture mode CLK❫ CLK❫
tckh sc Minimum CLK pulse high in Capture mode CLK❫ CLK❴
tckl sc Minimum CLK pulse low in Capture mode CLK❴ CLK❫

Table 2.42: Timing specification definitions of ROM compiler

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2.1.12.7 Timing Protocol for Shift Mode, Capture Mode and Debug Shift Mode
1PRF/SPSB/SPMB/HSSP/ compiler:

Figure 2.36: Shift/Capture mode timing protocol with DFTBYP=1

Figure 2.37: Debug shift and normal mode timing protocol with DFTBYP=0

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2PRF compiler:

Figure 2.38: Shift/Capture mode timing protocol with DFTBYP=1

Figure 2.39: Debug shift and normal mode timing protocol with DFTBYP=0

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ROM compiler :

Figure 2.40: Shift/Capture mode timing protocol with DFTBYP=1

Figure 2.41: Debug shift and normal mode timing protocol with DFTBYP=0

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Notes of Shift and Capture modes :

❼ DFTBYP is an asynchronous input pin to enable function of shift and capture modes.

❼ SE is a synchronous input pin to switch between shift and capture modes, asserted high for shift mode whereas
asserted low for capture mode.

❼ Output Q is rippled in shift mode with the corresponding content of scan FF while shifting.

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 Figure 2.42: Isolation timing protocol

DFT behavior for all compilers( except ROM ) :

❼ SOC/SOD[1:0], same as output Q are isolated and clamped to low while DSLP/SD is being asserted.

❼ SIC and SID[1:0] pins are allowed to be floating in DSLP and SD mode.

❼ SOD & SID are not applicable to ROM, since there is no Data pin for ROM.

DFT behavior for ROM compiler :

❼ SOC, SOQ[1:0], same as output Q are isolated with pull down to low while SD is being asserted.

❼ SIC, SIQ[1:0] are allowed to be floating in SD mode.

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DFT behavior :

❼ Redundancy enable pin REDENIO must be static-low or static-high or toggled during shift, capture and debug
shift modes.

❼ TSEL pins can be unknown during shift, capture and debug shift modes. Names of TSEL pins for each compiler
are listed below:
– 1PRF/SPSB/ SPMB/HSSP: RTSEL,WTSEL,
– 2PRF :RCT, WCT, KP
– ROM :CKHE, CKLE, SKP, DT
❼ Delay timing of SOC, SOD and Q pins are characterized with default setting of TSEL pins.

❼ Delay timing of SOC, SOD and Q pins are independent to TSEL pin setting in capture, shift and debug shift
modes.

❼ PM(SD and DSLP) pins must be de-asserted during DFT mode.

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2.1.13 Characterization Corners & Slew Rate Definition
2.1.13.1 Slew Rate Definition and Measurement Points
All timing is measured with a logic threshold at 50% of power supply VDD. Slew time is measured from 10% to 90%
of power supply VDD.
All timing data is characterized with 5 output load 0.00128/0.01679/0.03452/0.06998/0.1409(pf) and 5 input slew
time as indexes of timing arc for those periphery voltages as shown in Table 2.43 and Table 2.44

N7 SRAM Signal input slew (ns)

Process Corner Periphery Voltage Cell Voltage Temp. 1 2 3 4 5
- >= 0.695V - - 0.0019 0.0284 0.0815 0.1877 0.4000
- >= 0.595V <0.695V - - 0.0029 0.0541 0.1566 0.3616 0.7715
- >= 0.495V <0.595V - - 0.0052 0.1264 0.3688 0.8537 1.8235
- <0.495V - - 0.0053 0.1743 0.5135 1.1918 2.5485

Table 2.43: Signal slew table

N7 SRAM CLK input slew (ns)

Process Corner Periphery Voltage Cell Voltage Temp. 1 2 3 4 5
- >= 0.695V - - 0.0019 0.0151 0.0415 0.0943 0.2000
- >= 0.595V <0.695V - - 0.0029 0.0284 0.0794 0.1815 0.3857
- >= 0.495V <0.595V - - 0.0052 0.0656 0.1865 0.4283 0.9118
- <0.495V - - 0.0053 0.0893 0.2586 0.5971 1.2742

Table 2.44: CLK slew table

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2.1.13.2 Characterization PVT Corners
The voltage value in PVT larger than 0.825v DRM spec is characterized for timing sign-off only. TSMC does not
guarantee the SRAM reliability and yield if the user operates the SRAM above 0.825v

Single-rail PVT list :

Corner Process Voltage (V) Temperature (C)

ffgnp 0p825v m40c cbest ccbest ffgnp 0.825 -40
ffgnp 0p825v 0c cbest ccbest ffgnp 0.825 0
ffgnp 0p825v 125c cbest ccbest ffgnp 0.825 125
tt 0p750v 85c typical tt 0.750 85
tt 0p750v 25c typical tt 0.750 25
ssgnp 0p675v m40c cworst ccworst t ssgnp 0.675 -40
ssgnp 0p675v 0c cworst ccworst t ssgnp 0.675 0
ssgnp 0p675v 125c cworst ccworst t ssgnp 0.675 125
ffgnp 0p800v 125c cbest ccbest ffgnp 0.800 125
ffgnp 0p900v m40c cbest ccbest ffgnp 0.900 -40
ffgnp 0p900v 125c cbest ccbest ffgnp 0.900 125
tt 0p800v m40c typical tt 0.800 -40
tt 0p900v 125c typical tt 0.900 125
ssgnp 0p800v m40c cworst ccworst t ssgnp 0.800 -40
ssgnp 0p800v 125c cworst ccworst t ssgnp 0.800 125
ssgnpaging 0p800v m40c cworst ccworst t ssgnpaging 0.800 -40
ssgnpaging 0p800v 125c cworst ccworst t ssgnpaging 0.800 125
ssgnpaging 0p675v m40c cworst ccworst t ssgnpaging 0.675 -40
ssgnpaging 0p675v 125c cworst ccworst t ssgnpaging 0.675 125

Table 2.45: PVT Corner of Single Rail

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2.1.14 Power Definition
DC and AC power number can be found in macro datasheet after compiling, definitions as following:
❼ Read current: Clock read current which excludes leakage and pin power.

❼ Write current: Clock write current which excludes leakage and pin power.

❼ Deselect current: memory is disabled by CEB pin, and clock is toggling; all signals are in steady state.

❼ Static standby (leakage) current: memory is disabled by CEB pin, and clock is not toggling; all signals are in
steady state.

❼ Dynamic standby current: memory is disabled by CEB pin, and clock is toggling in 50% clock activity; address
and data pins maintain 50% activity.
❼ Pin power: specific power for pin/bus contribution information, please refer to ”Dynamic Power break down per
pin” table in datasheet of memory macros.

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2.1.15 Metal Layer Usage
❼ Metal scheme is 1P3M 1X1Xa.

❼ Power pins are brought up to top level as M3 pins for easy access

❼ M3 layer is mainly for power routing

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2.1.16 Scramble Diagram and Mapping Example
In order to efficiently for users to test on silicon, users may need to understand of how memory bit lines and word
lines are organized, following figures illustrate the scramble diagram for each type of memory.

1PRF compiler MUX1:

Figure 2.43: Compiler scramble diagram for 1PRF mux1

1PRF compiler MUX2/4:

Figure 2.44: Compiler scramble diagram for 1PRF mux2/4

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2PRF compiler MUX1:

Figure 2.45: Compiler scramble diagram for 2PRF mux1

2PRF compiler MUX2/4:

Figure 2.46: Compiler scramble diagram for 2PRF mux2/4

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SPSB compiler MUX2:

Figure 2.47: Compiler scramble diagram for SPSB mux2

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SPSB MUX4 :

Figure 2.48: Compiler scramble diagram for SPSB mux4

SPSB compiler MUX8/16 :

Figure 2.49: Compiler scramble diagram for SPSB mux8/16

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SPMB compiler :

Figure 2.50: Compiler scramble diagram for SPMB with 1 bank

Figure 2.51: Compiler scramble diagram for SPMB 2 banks

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Figure 2.52: Compiler scramble diagram for SPMB with 1000 rows

Figure 2.53: Compiler scramble diagram for SPMB with 520 rows

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HSSP compiler :

Figure 2.54: Compiler scramble diagram for HSSP

ROM compiler :

Figure 2.55: Compiler scramble diagram for ROM

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Note
cm : the number of column-mux
m : the number of row
n : the number of word width(bits)

If n is equal to even number, all IO(bits) will be allocated evenly into left and right bank, namely each bank has the
same number of IO(bits), whereas, if n is equal to odd number, left bank always has one more IO(bit) than right bank
and 4 columns for redundancy.

Table 2.46 is an example that shows how address pins decoded for word line (WL) and Bit lines (BL, BLB).

Column Mux De- A[1:0]

code (BL&BLB)
0 00
1 01
2 10
3 11

Row Decode (WL) A[6:0]

WL[0] 000,000
WL[5] 000,101

Table 2.46: For word-depth=128, Mux = 1

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2.1.17 Power/Ground Connection Guideline
In chip design level, users shall meet the lower bound of voltage level for Vccmin specification, for example, (>=Vdd-
10%) at the memory IP boundary to avoid performance degradation due to voltage drop from system power. Guidelines
are listed below to provide better IR drop result and EM management:

❼ Connect Mn VDD/VDDM and VSS power lines through M(n+1) and VIA as many as possible.

❼ All power and ground pins MUST be connected to VDD/VDDM and VSS, respectively.

❼ Metal hookup of power supply shall be taken more care around memory IO buffer area where data input and
output pins are located.
❼ An example of power mesh implementation is shown below in Figure 2.56. M(n+1) power line width must be
larger than 0.038um and the pitch is not allowed larger than 2.5um. The fashion of power hookup illustrated in
figure below ensures the accuracy of timing and power modeling.

❼ To prevent potential VIAya DRC violation in chip level. Please make sure APR tool honor VIA spacing rule in
PG routing.
Note1 : Mn = Top metal
Note2 : VDDM = additional power domain when dual rail feature is enabled

Figure 2.56: Chip level power routing guideline

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2.1.18 Routing Blockage Guideline
❼ M1 and M2 obstruction layers allow zero space to enable maximum pin access tracks on vertical M1 signal pins.

❼ Although M0,M1,M2 and M3 obstruction layers are defined in LEF and M1/M2 allow zero space, additional
routing blockages are still required to prevent DRC violation between APR and internal drawings. The minimum
width of routing blockage from IP boundary is 0.38um around macro for M0 and M3. The M2 routing blockage
is required except signal pin side for M2 pin access, and the minimum width is 0.38um. The M1 routing blockage
is also required around macro, and the minimum width is 0.26um.
❼ The width of M3 power and ground pins are 40nm, 60nm and 180nm. The width of M3 obstruction(OBS) may
have 20nm, 22nm and 24nm. Though OBS geometry is exactly the same as internal M3 drawing, current place
and route tools may have limitation to identify M3 OBS width for minimum required space between M3 routes
and OBS. To prevent potential DRC violation between OBS and chip level routes, please follow M3 routing
guidance below.
– Create route-guide layer to cover the whole macro completely and exactly to prevent router from routing
through macro.
Example: icc shell>create route guide -coordinate [get attr ✩RAM bbox] -no signal layers M3 -name RAM
M3 RG ✩num

Figure 2.57: APR Chip Integration Guideline for SRAM

2.1.19 Placement Guideline

To enable the higher utilization in chip level placement, the white space reserved in memory is removed. With this
specification change, memory has smaller area and denser FEOL and BEOL. Below rules are space guideline for tsmc
memory and standard cell library.

❼ The minimum space required for sram macro placement is 0.912um.

❼ The minimum space between memory and Std. cell is 0.912um in horizontal direction and 0.912um in vertical
direction.
❼ Space guideline is subject to be updated due to revision for SRAM, dummy utility and Std. cell library.

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 Memory Space Guideline S/D Direction (um) ENDCAP Direction (um)
Same SRAM Macro >=0.912 >=0.912
Different SRAM macros >=0.912 >=0.912
Memory to Std. cell >=0.912 >=0.912
Note : this spacing value is base on v0.9 DRM.

Table 2.47: Summary on Memory Spacing Guideline

Figure 2.58: Memory space guideline

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2.2 Reference Document
2.2.1 Release Note
The major contents include revision history, design documents/version (DRM/DRC, LVS, RC tech file, spice model,
etc.), PVT conditions, special note and tapeout layer information.

2.2.2 Quick Reference Table (QRT)

Provides PPA (Performance, Power and Area) data for most frequently used memory configurations with all PVT
conditions. The feature options in the QRT are based on default option. Users can refer to this table to obtain memory
PPA data instantly for estimation. Please refer to Quick Reference Table (QRT) provided within delivery package for
memory performance data preview.

Terms Description
type Compiler type
word Word depth
io Word width (Bit number)
mux Column mux
seg Segment type (bit-line partition)
drawing dimension area (um2 ) Macro size in GDS layout
access time (ns) Access time (CLK to output Q)
cycle time (ns) Cycle time
adr setup (ns) Address setup time
adr hold (ns) Address hold time
data setup (ns) Data setup time
data hold (ns) Data hold time
readc (uA/MHz) Read current, excludes pin power
writec (uA/MHz) Write current, excludes pin power
leakage (uA) Static power
leakage dslp (uA) Static power in deep-sleep mode
leakage sd (uA) Static power in shut-down mode
total kbits (word * io) / 1024

Table 2.48: Terms and description (used in QRT)

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Chapter 3

Compiler File Structure

3.1 Input file

The following tar files with 1prf as an example can be downloaded from Tsmc Online. After decompressing the pack-
ages, the databook, quick reference table and release note are located under Document and the compiler database tar
file under Compiler. Refer to Figure 3.1 for file structure

tsn7 1prf 20151201 120b doc.tar.gz

tsn7 1prf 20151201 120b cec.tar.gz
tsn7 1prf 20151201 120b rln.tar.gz

Figure 3.1: File structure

The compiler tar file (example: tsn7 1prf 20151201 c190115 120b.tar.gz) contains below files after further decompress.

❼ tsn7 1prf 20151201 c190115 120b.mco

– The SRAM compiler database which is utilized to generate the macro design kits with MC2 software engine
❼ tsn7 1prf 120b.exe

– The script file to generate SRAM instance in batch mode

❼ config.txt
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 – The user-defined configuration file used for macro generation in batch mode. More than one macro config-
urations can be listed in this file with the pre-defined format
❼ UTIL/AntennaLEF

– The raw file of antenna parameters for Antenna LEF kit generation

❼ UTIL/PWL

– The raw file of PWL waveform for Voltus design kit

❼ UTIL/DATASHEET

– Post processing for Datasheet to allow users determine the timing value with specified slew rate and loading

❼ MC2 2015.12.01.g.tar.gz

– The compiler software engine that generates all the macro design kits by extracting the information from
the database *.mco file

❼ mc2 install.pl

– The script installs MC2 by decompressing MC2 2015.12.01.g.tar.gz and setting related path. It is also used
to start up compiler license

❼ install.sh

– Called by ”mc2 install.pl” script to decompress MC2 2015.12.01.g.tar.gz for MC2 installation
❼ install.txt

– The user-defined file used by ”mc2 install.pl” script to specify path for MC2 installation, license file and
*.mco file. These path are used for license startup and compiler execution

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3.2 Output file
Below is the illustration of file directory structure of design kits for SRAM macro generated from compiler. The
LOG folder contains a log file from the macro compilation. The other folders contain the design kits that are further
described in next section.

Figure 3.2: Example file structure of generated kits

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3.3 Design kit and associated tools
Design kits generated by compilers are described in Table 3.1

Kit Name Kit Description Associated Tool Tool vendor

Datasheet Macro datasheet NA NA
GDSII GDSII layout view Calibre/ Hercules Mentor/ Synopsys
SPICE Spice netlist Calibre/ Hercules Mentor/ Synopsys
LEF SOC Encounter (phantom) view Soc Encounter/ ICC Cadence/ Synopsys
NLDM Non-linear delay model Design Compiler Synopsys
CCS Composite current source model Design compiler Synopsys
VERILOG Verilog model (*.v) NV-Verilog/ VCS Cadence/ Synopsys
VERILOG Verilog model (SYN/* syn.v) NV-Verilog/ VCS Cadence/ Synopsys
DFT/ATPG ATPG model TetraMax Synopsys
DFT/ATPG ATPG model Fastscan Mentor
DFT/MBIST MASIS model SMS Synopsys
DFT/MBIST LogicV model LogicV Mentor
VOLTUS IR/EM model VOLTUS Cadence

Table 3.1: Design kits generated by compilers

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Chapter 4

Application Note

4.1 TSMC SRAM Verilog Application Notes

4.1.1 Introduction
The general purpose of TSMC SRAM Verilog models is to represent the memory functionality in digital format. In
this document, we will introduce all Verilog models in the current release. Moreover, we will provide the
recommendations for these Verilog models. User must pay attention to following instructions in order to have correct
simulation result.

1. For fast functional simulation, we recommend to use the built-in directive TSMC CM UNIT DELAY
2. In a non-fully decoded array, a write operation to a non-existed address location does not change the memory
array contents whereas the output value remains the same as previous cycle.
3. In a non-fully decoded array, a read operation to a non-existed address location does not change the memory
array contents but the output of the current cycle becomes unknown.
4. The unknown clock will corrupt the memory data when CEB or CEBM (selected by BIST) is not high and
WEB or WEBM (selected by BIST) is not high. Corruption is limited to the written location only, but if the
address is unknown, all memory is corrupted.
5. When BIST is unknown, and the non-BIST control signal is equal to BIST signal, for example CEB and
CEBM WEB and WEBM, and so on, this condition will not be treated as hazard condition.
6. Assertion in SystemVerilog format is enclosed by directive TSMC ASSERTION ADOPT, and the
corresponding code in Verilog format is also provided.
7. Though toggling TSEL pins in scan shift, scan capture, and debug shift modes is allowed, Verilogs still display
informative messages.

4.1.2 Deliverables

Model VERILOG
Behavioral model VERILOG/*.v

Table 4.1: Verilog model offering

4.1.3 Behavioral model

This model describes all functionalities, including memory access operations, power management, redundancy
scheme, and testing operations. It also handles the Hazard conditions, including illegal mode transition, and timing
violation, which can be asserted or de-asserted by directive TSMC CM UNIT DELAY. It is used for functional
simulation and SDF back-annotation, and compliant with IEEE Standard for Verilog (IEEE Std 1364-2001), and
IEEE Standard for System Verilog (IEEE Std 1800-2009 )
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Below is the summary of directives, parameters and tasks for convenience of model usage. Refer to subsection 4.1.6
for detail explanation.

4.1.3.1 Directives
1. TSMC PWR AWARE
2. TSMC NO HAZARD CHECK

3. TSMC CM UNIT DELAY

4. TSMC INITIALIZE MEM

5. TSMC MEM DISABLE EMU REDUNDANCY(synthesizable model)

6. TSMC INITIALIZE FAULT

7. TSMC INITIALIZE FORMAT BINARY

8. TSMC INITIALIZE MEM USING DEFAULT TASKS

9. TSMC MEM LOAD 0

10. TSMC MEM LOAD 1

11. TSMC MEM LOAD RANDOM

12. TSMC NO TESTPINS DEFAULT VALUE CHECK

13. TSMC NO XADDR WARNING

14. TSMC DISABLE WARNING MESSAGE
15. TSMC DISABLE INFOR MESSAGE

16. TSMC ASSERTION ADOPT

17. TSMC CM ACCESS

18. TSMC CM RETAIN

19. TSMC CM SETUP

20. TSMC CM HOLD

21. TSMC CM PERIOD

22. TSMC CM WIDTH

23. TSMC CM CONTENTION(2PRF only)

24. TSMC STUCKAT FAULT

25. TSMC NO GENERATE CONSTRUCT(synthesizable model)

26. TSMC DISABLE CONTENTION MESSAGE(2PRF only)

27. TSMC FULL CONTENTION WARNING(2PRF only)

28. TSMC PARTIAL CONTENTION WARNING(2PRF only)

29. TSMC CM UPF

30. TSMC DISABLE CONTENTION BEHAVIORAL CHECK(2PRF only)

31. TSMC TRWCC (2PRF only)

32. TSMC TWRCC (2PRF only)

33. TSMC TSDWK2CLK
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 34. TSMC TDSLPWK2CLK

35. TSMC DISABLE WAKEUP BEHAVIORAL CHECK

36. TSMC DISABLE WAKEUP MESSAGE

37. TSMC DISABLE ISO TOGGLE CHECK

4.1.3.2 Parameters
1. SRAM DELAY
2. INITIAL MEM DELAY

3. TRWCC(2PRF only)

4. TWRCC(2PRF only)
5. TSDWK2CLK
6. TDSLPWK2CLK

7. cdeFileInit

8. INITIAL FAULT DELAY

9. cdeFileFault

4.1.3.3 Tasks
1. injectSA

2. preloadData
3. writeMemory
4. readMemory
5. printMemory

6. printMemoryFromTo
7. printRMemory
8. xMemoryAll/zeroMemoryAll/oneMemoryAll/randomMemoryAll

9. xMemoryQ/zeroMemoryQ/oneMemoryQ/randomMemoryQ

4.1.4 Synthesizable Model

Synthesizable Verilog can be used at prototype stage.

4.1.5 Verilog Models Used in SOC Design Flow

The various Verilog models can be used at different stages in design flow as shown and explained below.

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 Figure 4.1: ASIC design flow

Figure 4.2: FPGA design flow

4.1.5.1 Functional simulation

When the main purpose is fast functional verification of the whole chip, you can simulate behavioral model, and
enable unit delay mode by adding ”+define+TSMC CM UNIT DELAY” in Verilog simulation option. The output
delay is controlled by the parameter SRAM DELAY, which can be overwritten by adding ”#( new delay)” in SRAM
macro instantiation, if needed. At presim stage, all timing information are assigned by default setting in Verilog,
TSMC CM ACCESS, TSMC CM RETAIN, TSMC CM SETUP, TSMC CM HOLD, TSMC CM PERIOD, TSMC
CM WIDTH, and so on.

4.1.5.2 Low-power verification

When the netlist with power/ground pins is available, you can simulate power/ground pin behavior by adding
”+define+TSMC PWR AWARE” in Verilog simulation option, to make sure they are connected appropriately and
behave correctly.

4.1.5.3 Timing analysis

When real delays related to SRAM are ready, you can simulate behavioral model, and enable SDF backannotation
by invoking ”✩sdf annotation”.

4.1.5.4 FPGA emulation

At prototype stage, you can use emulation model(synthesizable model) for FPGA synthesis. In order to meet
requirements from different emulators, there is no behavioral construct in the Verilog if TSMC NO GENERATE
CONSTRUCT is defined. To reduce the resource allocation in FPGA, redundancy behavior is not described in the
Verilog if TSMC MEM DISABLE EMU REDUNDANCY is defined.

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4.1.6 Detail of Directive, Parameter and Task
1. Directive
(a) TSMC PWR AWARE
❼ Description
i. Include power/ground pins behavior
ii. Disable (default)
– The states of power/ground pins are not taken into account
iii. Enable
– In addition to port declaration, power/ground pins would influence how sram behaves
(b) TSMC NO HAZARD CHECK
❼ Description
i. De-activate hazard condition checking
(c) TSMC CM UNIT DELAY
❼ Description
i. Speed up the simulation without timing check and delay
ii. All module path delays are replaced by variable <SRAM DELAY >, which is 1ps by default
iii. Used in fast functional simulation
iv. Disable (default)
– All timing checks and delays are included
v. Enable
– Disable all timing checks and SDF back annotation
(d) TSMC MEM DISABLE EMU REDUNDANCY
❼ Description
i. Disable all redundancy descriptions, except for port declaration
ii. Disable (default)
– Redundancy behavior is completely deployed
iii. Enable
– Redundancy ports are declared without any functionality description and resource allocation
(e) TSMC INITIALIZE MEM
❼ Description
i. Preload the memory to predefined values
ii. At time <INITIAL MEM DELAY>, 10ps by default, load <cdeFileInit> to the whole memory
iii. The format of <cdeFileInit> follows IEEE STANDARD FOR VERILOG, IEEE Std 1364
iv. The default file name of <cdeFileInit> is <module name> initial.cde
v. Disable (default)
– All memory contents are unknown initially
vi. Enable
– Preload the memory to predefined values
(f) TSMC INITIALIZE FAULT
❼ Description
i. Provide a mechanism to validate the internal redundancy logic
ii. At time <INITIAL FAULT DELAY> , 10ps by default, set the bitcell as faulty or not, based on
<cdeFileFault>
iii. When the flag is 1, the bits specified by the faulty table <cdeFileFault> in legal write operation
are flipped
iv. <cdeFileFault> follows IEEE STANDARD FOR VERILOG, IEEE Std 1364
v. The default file name of <cdeFileFault> is <module name> fault.cde
vi. Disable (default)
– No fault in memory
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 vii. Enable
– When the flag is 1, the bits specified by the faulty table <cdeFileFault> in legal write
operation are flipped
(g) TSMC INITIALIZE FORMAT BINARY
❼ Description
i. Set the radix of the initial memory file to binary
ii. Without the directive, the radix is hexadecimal by default
iii. Disable (default)
– Hexadecimal
iv. Enable
– Binary
(h) TSMC INITIALIZE MEM USING DEFAULT TASKS
❼ Description
i. Depending on whichever directive is defined (TSMC MEM LOAD (0/1/RANDOM), preset
memory to all 0/1/random
(i) TSMC MEM LOAD (0/1/RANDOM)
❼ Description
i. If TSMC INITIALIZE MEM is defined,preset memory to all 0/1/random at timing of INITIAL
MEM DELAY
ii. When entering shut-down mode, the memory contents will be reset to all 0/1/random
iii. When leaving sleep/deep-sleep/shut-down mode, outputs will be all 0/1/random
iv. Disable (default)
– The memory contents are all unknown initially
– The memory contents will be flushed as unknown when entering shut-down mode
– The outputs will be unknown when leaving sleep/deep-sleep/shut-down mode
v. Enable
– Initialize the memory contents to all 0/1/random
– When entering shut-down mode, the memory contents will be reset to all 0/1/random
– When leaving sleep/deep-sleep/shut-down mode, outputs will be all 0/1/random
(j) TSMC NO TESTPINS DEFAULT VALUE CHECK
❼ Description
i. All TSEL pins are required to connect to default values
ii. If any TSEL pin is not connected to the default value, memory contents and outputs are corrupted
iii. Disable (default)
– All TSEL pins must connect to default values in functional mode. If not, memory contents and
outputs are corrupted as unknown with warning messages, and simulation can continue to
proceed. All TSEL pins can be unknown in SWT mode.
iv. Enable
– No check on TSEL pins with default values, but toggling will be enforced. If any TSEL pins
toggles in functional read, write, scan shift, scan capture, and debug shift modes, warning
message will be displayed, and timing violations could cause memory contents corrupted.
Though TSEL pins are free to toggle anytime except for read and write modes, Verilog behaves
conservatively.
(k) TSMC ASSERTION ADOPT
❼ Description
i. Disable (default)
– use verilog to display assertion message
ii. Enable
– use systemverilog to display assertion message
(l) TSMC CM ACCESS/TSMC CM RETAIN
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 ❼ If SDF is not back-annotated and TSMC CM UNIT DELAY is not defined, they are used for all
delays from input to output
❼ By default, TSMC CM ACCESS is 20ps and TSMC CM RETAIN is the same as 20ps
(m) TSMC CM SETUP/TSMC CM HOLD
❼ If SDF is not back-annotated and TSMC CM UNIT DELAY is not defined, they are used for all
timing constraints, including synchronous related to clock, and asynchronous to SD/DSLP
❼ By default, TSMC CM SETUP is 9ps and TSMC CM HOLD is the same as 9 ps
(n) TSMC CM PERIOD/TSMC CM WIDTH
❼ If SDF is not back-annotated and TSMC CM UNIT DELAY is not defined, they are used for all
timing constraints in clock pin
❼ By default, TSMC CM PERIOD is 1.2ns and TSMC CM WIDTH is 0.5ns
(o) TSMC CM CONTENTION(2PRF only)
❼ If SDF is not back-annotated and TSMC CM UNIT DELAY is not defined, this is for contention
check in multiple-port srams
❼ By default, TSMC CM CONTENTION is 9ps
(p) TSMC NO GENERATE CONSTRUCT(synthesizable model)
❼ Replace generate statements with non-behavioral constructs.
(q) TSMC STUCKAT FAULT
❼ Description
i. Enable the capability to inject stuck-at faults to memory
ii. Disable (default)
– No error injection tasks in the model
iii. Enable
– Provide the task <injectSA> to inject stuck-at faults
(r) TSMC CM UPF
❼ Description
i. Enable to include UPF package
(s) TSMC DISABLE CONTENTION BEHAVIORAL CHECK (2PRF only)
❼ Description
i. Disable contention check in behavioral level
(t) TSMC TRWCC (2PRF only)
❼ Description
i. The contention constraint between read and write
(u) TSMC TWRCC (2PRF only)
❼ Description
– The contention constraint between write and read
(v) TSMC DISABLE WAKEUP BEHAVIORAL CHECK
❼ Description
– Disable wakeup check in behavioral level
(w) TSMC TSDWK2CLK
❼ Description
– The wakeup constraint for wakeup from shut down
(x) TSMC TDSLPWK2CLK
❼ Description
– The wakeup constraint for wakeup from deep sleep
(y) TSMC DISABLE ISO TOGGLE CHECK
❼ Description
– Disable (default)
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 ✯ Show error message that ISO is asserted; moreover, memory contents and scan flops will be
flushed.
– Enable
✯ Disable the error message that ISO is asserted; moreover, memory contents will NOT be
flushed. This could induce mismatches between circuit and Verilog.
2. Directive for Warning and Error Message
(a) TSMC NO XADDR WARNING
❼ Description
i. Disable (default)
– Pop up warning message when address is unknown in read cycle
ii. Enable
– No message when read address is unknown
(b) TSMC DISABLE WARNING MESSAGE
❼ Description
i. Suppress all runtime warning messages related to SRAM
(c) TSMC DISABLE INFO MESSAGE
❼ Description
i. Suppress all runtime information messages related to SRAM
(d) TSMC DISABLE CONTENTION MESSAGE(2PRF only)
❼ Description
i. Suppress all contention warnings/errors
(e) TSMC FULL CONTENTION WARNING(2PRF only)
❼ Description
i. Disable (default)
– Display error when all bits are written and read simultaneously
ii. Enable
– Display warning when all bits are written and read simultaneously
(f) TSMC PARTIAL CONTENTION WARNING(2PRF only)
❼ Description
i. Disable (default)
– Display error when some bits are written and read simultaneously
ii. Enable
– Display warning when some bits are written and read simultaneously
3. Parameter
(a) SRAM DELAY
❼ The delay value for simulation in TSMC CM UNIT DELAY mode
(b) TRWCC(2PRF only)
❼ The contention constraint between read and write
(c) TWRCC(2PRF only)
❼ The contention constraint between write and read
(d) TSDWK2CLK
❼ The wakeup constraint for wakeup from shut down
(e) TDSLPWK2CLK
❼ The wakeup constraint for wakeup from deep sleep
(f) cdeFileFault
❼ The input filename for TSMC INITIALIZE FAULT
❼ default is <module name> fault.cde
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 (g) INITIAL MEM DELAY
❼ The absolute simulation time to initialize memory content
❼ default is 0.01 ns
(h) INITIAL FAULT DELAY
❼ The absolute simulation time to initialize memory fault
❼ default is 0.01 ns

4. Task
(a) preloadData
❼ Preload data from text file to memory
❼ Input argument
– Filename (max 256 characters)
(b) writeMemory
❼ Directly write to memory
❼ Input arguments
– Write address
– Data to be written
– redenio to flag normal or redundant area
– fadio if redundancy is enable
(c) readMemory
❼ Directly read out memory content
❼ Input argument
– Read address
(d) printMemory
❼ Print out memory content
❼ No input argument
(e) printMemoryFromTo
❼ Print out memory content in range
❼ Input argument
– start and end address
(f) printRMemory
❼ Print out memory content of redundancy array only
❼ No input argument
(g) xMemoryAll/zeroMemoryAll/oneMemoryAll/randomMemoryAll
❼ Set memory contents to x/zero/one/random for both normal and redundancy arrays
❼ No input argument
(h) xMemoryQ/zeroMemoryQ/oneMemoryQ/randomMemoryQ
❼ Set Q to x/zero/one/random
❼ No input argument
(i) injectSA
❼ To inject a stuck-at error, please invoke the injectSA task with correct hierarchical names
❼ Input arguments
– The address location where the fault is to be injected
– Specific bit in word
– Fault polarity of stuck-at 0 or 1
❼ In order to avoid race condition, do not invoke this task at simulation time #0.

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4.2 TSMC SRAM DFT Application Notes
4.2.1 Introduction
The general purpose of TSMC SRAM DFT feature is to enable better test coverage of SoC logic. It describes the
settings on SDC files and command to connect SoC scan chains with TSMC SRAM internal scan chains for Synopsys
tools (DFT Compiler, TetraMax, and Star Memory System). In the later section, more information is provided for
TSMC SRAM ATPG model and SoC DFT implementation SMS guidelines for generating and applying test patterns.

4.2.2 Synthesis and STA

4.2.2.1 SDC Files
The DFT/BIST related signals must be forced constant in functional, MBIST or DFT SDC files to prevent false
alarms during STA.
Assume the DftByp is the SoC signal to control SRAM DFTBYP pin:
The constraint ’set case analysis 0 DftByp’ should be specified in functional and MBIST SDC files.
In DFT mode the ’set case analysis 1 DftByp’ should be specified in DFT SDC files.

4.2.2.2 Scan Insertion (DFT Compiler)

The CTL model is used for scan insertion to connect SoC scan chains to SRAM internal scan chains.
The following command can be used to read CTL model.
read test model -format ctl -design < SRAM MODULE NAME> < PATH OF CTL MODEL>

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4.2.3 ATPG and Synchronous Write Through (SWT)
4.2.3.1 General Description and Objectives
The purpose of memory ATPG model is to facilitate test pattern generation for the memory surrounding logic to
improve test coverage of a design. In general, the memory internal faults are tested by other means, such as memory
BIST. Moreover, due to the limited Verilog syntax supported by ATPG tools, only the partial functionalities are
described in the ATPG model.

TSMC SRAM ATPG model supports four modes of operations, Normal,Scan Shift,Scan Capture and Debug Shift
modes. The operation mode is controlled by the SE and DFTBYP input pins as described in Table 4.2 and Table 4.3.
Asserting the asynchronous DFTBYP (force High) puts the memory in DFT scan mode. While in DFT scan mode
the asynchronous SE signal controls the scan chain shift and capture operations. Additional shifting function is also
offered as Debug Shift mode to allow user assert SE only, however Debug Shift mode is only supported when DFTBYP
is de-asserted (force Low).

Table 4.2: SRAM ATPG operation modes for all compilers except 2PRF and ROM

Table 4.3: SRAM ATPG operation modes for 2PRF and ROM

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Normal Operating Mode When SE and DFTBYP are disabled (de-asserted), normal mode of operation, memory
read and write operations are allowed. In this mode the memory data, address and control signals are involved in the
memory operations as shown in red lines in Figure 4.3.
The ATPG model utilizes these signals to propagate faults through the memory(when sequential atpg mode is used).

Figure 4.3: SRAM normal mode of operation except 2PRF and ROM

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Capture/Shift Mode Asserting DFTBYP pin will put the memory in Shift (SE = 1) or Capture (SE = 0) mode,
and the memory core will not be involved in the test. In Shift mode, the SRAM internal scan flip-flops are used to
shift out the test result for analysis or to shift in the test patterns for testing the surrounding logic driven by the
SRAM data output (Q pins). In Capture mode, internal scan flip-flops will capture the XOR result of related inputs.
The memory outputs (Q) will also be the propagated result of corresponding XOR result except 2PRF and ROM.
The data paths of Shift and Capture modes are shown in Figure 4.4 and Figure 4.5 respectively for non 2PRF and
ROM memories.
For 2PRF and ROM DFT block diagram please refer to Figure 2.32 and Figure 2.33.

Figure 4.4: SRAM shift mode of operation except 2PRF and ROM

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Figure 4.5: SRAM capture mode of operation except 2PRF and ROM

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4.2.4 Using ATPG model
This section provides guidelines on how the SRAM ATPG model can be used to create high test coverage patterns.
It also defines the required circuit constraints in different modes of operation to maximize the test coverage.

4.2.4.1 SRAM ATPG Model

In this section, the contents and limitation of TSMC ATPG model are described. Please note that only Synopsys
TMAX model is addressed; Mentor FASTSCAN model will be addressed in a future version of the document.
In TSMC SRAM ATPG model the following operations are supported and guaranteed to have the same behavior as
TSMC Verilog simulation model.

❼ Normal mode

– The read/write/bweb operations when BIST is either enable or disabled

– The 2 port memories (2PRF, UHD2RPF) output will be unknown when contention between the read and
write address occurs

❼ Capture/Shift mode

– The Capture/Shift operations when BIST is either enable or disabled

The SRAM may have specific power-mode pins such as SD and DSLP pins. Operation of the power modes are not
supported in the ATPG model. The memory output is tied to low when power mode pins are asserted.
Except for ROM and 2PRF compilers, during Capture mode Data in D bus will be passed to Q through memory core
in one cycle.

SRAM ATPG Model Limitations

❼ Although Normal and Scan (Capture/Shift) modes are supported in ATPG model, it is not recommended to
switch between the two modes during test using DFTBYP pin. The SRAM can be controlled to operate in either
Normal or Scan (Capture/Shift) modes when generating and applying test patterns. The value depends on the
objective of the ATPG mode run

❼ ATPG model checks the values of the pins to ensure proper setting of power-mode pins and repair-related pins
to de-asserted level when generating and applying test patterns. It is recommended testing power-mode pins
using memory BIST since the outputs may be unknown during wake-up or shut-down.
Note : Different compilers could have different lists of power-mode pins

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4.2.4.2 Implementation Guidelines
Scan Chain Design/Insertion In general the inputs of TSMC SRAM can be divided into SE, DFTBYP, power-
mode pins, repair-related pins, test pins and other pins as shown in Figure 4.6. The constraints for SE, DFTBYP,
power-mode pins, repair-related pins, and test pins are listed below

❼ Please connect the SE to DFT scan enable pin of your design.

❼ Please reserve the controllability of DFTBYP pin in the DFT mode of your design. DFTBYP should not toggle
in shift or capture mode.
❼ In the DFT mode of your design, please tie the power-mode pins to de-asserted level.
❼ In the DFT mode of your design, the repair enable pin REDENIO and repair address pins FADIO[*] can be
either static-low, static-high, or toggled.
❼ TetraMax issues DRC errors if power mode pins are not in de-asserted states during shift and capture mode. The
DRC checks could be disabled by defining TSMC DISABLE ASSERTION directive when reading a TetraMax
model.
Figure 4.6 illustrates a scan chain design to achieve the above constraints. Assume DftEn and DftByp are control
signals of your design to assert DFT mode(Scan Shift, Scan Capture, and Debug Shift). You can place MUXs on the
power-mode pins, and repair enable pin, and set the result of OR gate function with two inputs DftEn and DftByp
as selection signals. With those MUXs, when either DftByp or DftEn is asserted (i.e. Scan Shift, Scan Capture, and
Debug Shift), those pins can be tied to desired values.

Note :

1. The repair interface is optional of TSMC SRAM Compiler.

Figure 4.6: Scan chain design related to SRAM macros

4.2.4.3 Recommendations on TMAX options to provide high fault coverage during fault propagation
through the memories
To achieve high fault coverage of the shadow logic it is recommended to run the ATPG tool in default mode first
followed by another ATPG run in fast sequential mode. For the second run it is recommended to set the ATPG tool
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capture phase to 4 cycles.
For example, for the Synopsys TetraMax ATPG tool the recommended steps are

1- run atpg -optimize patterns -auto compression

2- set atpg -capture cycles 4
3- run atpg -auto compression - fast sequential only

In addition the following atpg setting might be useful for the fault simulation part of TetraMax.
set drc -load nonscan cells -nodslave remodel -noreclassify invalid dslave
set simulation -shift cycles 6
Please note DON’T use ”set drc -noshadows” option in case of any coverage loss.

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Chapter 5

Compiler Installation and Execution

5.1 Memory Compiler Package

Compiler name : tsn7 1prf 20151201 c190115 <ver>
Example package name : ”tsn7 1prf 20151201 c190115 <ver>.tar.gz”
The naming convention is described in chapter 1.
The package name that user receives from TSMC for above compiler will be ”tsn7 1prf 20151201 c190115 <ver>.tar.gz”.
The ”ver” indicates the compiler version.

The available files after decompressing the above package are described in detail in Chapter 3.

5.2 Installation Environment

TSMC memory compiler supports the following Operating System

❼ 64-bit Linux [Processor : Intel/AMD 64]

– Recommended RedHat Enterprise Linux 5

❼ 64-bit SunOS 5.10 [Processor : SPARC64]

❼ 64-bit SunOS 5.10 [Processor : Intel/AMD 64]

5.3 License Key

The license is required to activate the memory compiler. One license file is only valid for a certain period of time and
for the SRAM compilers designated in the file. There are also evaluation and formal licenses which is described in
later section. The license is also limited to start up on the designated host.
User should provide your host ID information to your TSMC regional technical contact window in order to receive
the required license file. The example host ID format is: 83cdac13 (SunOS) / 00E04DA61443 (Linux)
An example of a license key is shown below:

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5.3.1 Evaluation License (Front-End Kits & LEF Only)
❼ The license feature includes MC2-CLV, MC2-Main and the corresponding memory library features.

❼ There is a six-month evaluation period. Only front-end kits and LEF can be generated.

❼ The new Cloud Compiler feature is available on Tsmc Online since 2014. While using Cloud Compiler, the user
can generate the front-end kit without compiler installation and license startup. All the user need is to ask Tsmc
FTS engineer to grant the kits and user can start using the compiler GUI for kit generation right away. Current
cloud compiler supports front-end kits only (as in June 2015) but will expand to full kits in the future.

5.3.2 Formal License (Include Front-End Kits & Back-End Kits)

❼ The license feature includes MC2-CLV, MC2-CPV, MC2-Main and corresponding library features.

❼ TSMC provides one year valid period. All design kits can be generated. MC2-CPV features the GDSII and
SPICE netlist generation.

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5.4 MC2 Engine and License Installation
5.4.1 Prepare ”install.txt” File
The following illustrates an example of ”install.txt” file.

❼ ✩Install WD/memCompiler/ =>the path where users choose to install the compiler

❼ ✩Install WD/memCompiler/license.dat =>the path where the license file is located

❼ ✩Install WD/memCompiler/compiler mco =>the path where compiler tsn10tll {sram type}.mco files are located

Note1 : ✩Install WD indicates compiler installation working directory

Note2 : ”install.sh” file must be located in the same compiler installation working directory as MC2 object code (MC2
{version}.tar.gz) and ”mc2 install.pl” script are located

5.4.2 Use ”mc2 install.pl” Script

”mc2 install.pl” script is used to install MC2 compiler and invoke license file. Two commands are shown below.

❼ To install compiler and invoke license file (first installation)

% mc2 install.pl -file install.txt -all

❼ Invoke license file only (in case the license server is down)
% mc2 install.pl -file install.txt -license

”mc2 install.pl” script options are described below.

❼ -file <installfile >: give the path for compiler installation (default is ”install.txt”)

❼ -all : to install the compiler and invoke license file

❼ -license : Invoke license file only, no compiler installation

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5.4.3 Compiler and License Installation Steps
The interactive prompt & detail of execution are demonstrated below :
% mc2 install.pl -file install.txt -all

Waiting for 5 seconds here

Choose your platform option (1 to 5) and press ”Enter”

❼ The details of license installation will be shown on the screen and recorded in ”license.log” file

❼ Check the license status by using the following command

% ../MC2 2015.12.01.g/aux/flexlm/<platform>/lmutil lmstat -c <license.dat>
❼ A message ”License check-out failed for feature MC2-CPV” is expected if evaluation license key
is adopted.

❼ A source file ”cshrc.mc2” will be generated under the path ✩Install WD/memCompiler by using install.txt file.
Users MUST source this file before running the memory compiler
❼ Use the following command to re-start up the license in case the license is down
% mc2 install.pl -file install.txt -license

❼ The command to shut down the license:

% ../MC2 2015.12.01.g/aux/flexlm/<platform>/lmutil lmdown -c <license.dat>

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5.5 Memory Macro Generation
TSMC compilers support Batch mode for sram macro generation. Users can generate more than one instance at a
time by running in Batch mode.

Before running the compilers, users must source ”cshrc.mc2” file and make sure *.mco files are put under the path
✩Install WD/memCompiler/compiler mco .

5.5.1 Batch Mode

In Batch mode, user can specify multiple instance sizes and options for compiling. An example config file(config.txt)
can be found in the received package where detail of parameters and variables are described below.

❼ Source compiler license and set environment variable ✩MC HOME to

✩Install WD/memCompiler/compiler mco
% source cshrc.mc2
❼ Execute the following command in any working directory to generate instances
% tsn7 1prf <ver>.exe

Example :
Prepare config.txt file with tsmc naming convention as default
❼ config.txt

❼ The above configuration is just an example. Please refer to chapter 2.1.3 for correct configuration setting.

❼ Default input file is config.txt, users can input user-define naming (ex: config macro.txt) then execute the fol-
lowing command.
% tsn7 1prf <ver>.exe -file config macro.txt

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 ❼ In addition to following compiling option commands for kit selection, Table 1.4 shows other option commands
for feature selection.
-DATASHEET : To generate DATASHEET kit only
-VERILOG : To generate VERILOG kit only
-NLDM : To generate NLDM kit only
-LEF : To generate LEF kit only
-SPICE : To generate SPICE kit only
-GDSII : To generate GDS kit only
-DFT : To generate DFT kit only
-CCS : To generate CCS kit only
-VOLTUS : To generate VOLTUS kit only
-SIM2IPROF : To generate SIM2IPROF kit only
-CTL : To generate CTL kit
-CTL SOURCE :To generate CTL file in DFT with auto source lc shell
-MasisWrapper : To specify the TieLevel to Wrapper for the pins with ”Tag = None” in Masis kit (default is
TestBench)
-MasisMemory : To specify the TieLevel to Memory for the pins with ”Tag = None” in Masis kit (default is
TestBench)
-datasheet merged : To produce only merged datasheet (* mergedpvt.ds)
-datasheet separate : To produce only individual datasheet

Example 1 : To use TSMC naming convention.

example% : % tsn7 1prf <ver>.exe -file config.txt
Example 2 : To use user-defined naming convention.
example% : % tsn7 1prf <ver>.exe -NonTsmcName -file config.txt
Example 3 : To use Dual Rail
example% : % tsn7 1prf <ver>.exe -DualRail
Example 4 : To generate CTL kits
example% step1: Source library compiler (Recommended tool version :J-2014.09-SP4 )
example% step2: tsn7 1prf <ver>.exe -file config.txt -CTL

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User defined configuration file example :

❼ 1st character of library name cannot be numerical (eg. not ”1abc123”)

❼ config macro.txt

5.5.2 ROM Generation with Specified ROM Code

❼ User-defined ROM code

– 2 commands are supported.

✯ -RomCodeBin: Binary format
✯ -RomCodeHex: Hexadecimal format
– Specified ROM code file in configuration file.
✯ Default is Intel HEX format

❼ ROM code format example

– Allow user to provide Address+Data or Data only ROM code

✯ For DATA only formal, the address increase from LSB to MSB with ROW.
✯ In -RomCodeBin, Address code still need to use Hexadecimal for Verilog syntax.

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❼ Usage
– tsn7 rom 120b.exe -file <config file without Rom code>-GenRomCode
✯ Example :tsn7 rom 120b.exe -file config.txt -GenROMCode
✯ config.txt file content: 16384x64m16
– tsn7 rom 120b.exe -file <config file >
✯ Example :tsn7 rom 120b.exe -file config.txt
✯ config.txt file content: 16384x64m16 16384x64m16.rcf
✯ 16384x64m16.rcf : Intel Hex format (Address+Data)
✯ Verilog example :

– tsn7 rom 120b.exe -file <config file >-RomCodeBin

✯ Example :tsn7 rom 120b.exe -file config.txt -RomCodeBin
✯ config.txt file content: 16384x64m16 16384x64m16.rcf
✯ 16384x64m16.rcf : Binary format (Address+Data or Data Only)
✯ If you want to covert RomCode file to absolute path and attach in Verilog, you can follow below setting.
➲ config.txt file content: 16384x64m16 /proj/release/A10326/memory/rcf/16384x64m16.rcf
➲ Verilog example :

– tsn7 rom 120b.exe -file <config file >-RomCodeHex

✯ Example :tsn7 rom 120b.exe -file config.txt -RomCodeHex
✯ config.txt file content: 16384x64m16 16384x64m16.rcf
✯ 16384x64m16.rcf : Hexadecimal format (Address+Data or Data Only)
✯ If you want to covert RomCode file to absolute path and attach in Verilog, you can follow below setting.
➲ config.txt file content: 16384x64m16 /proj/release/A10326/memory/rcf/16384x64m16.rcf
➲ Verilog example :

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5.5.3 ROM code verification and format transformation

❼ hex2intel.pl : Convert hex ROM code to Intel hex format

❼ ROM code verification :

1. chk rom code n7.pl -intel vlg <*.rom.v> <Intel hex rom code file>
2. chk rom code n7.pl <*.spi> <Intel hex rom code file>

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Chapter 6

References

6.1 Abbreviation

Abbreviation Description
BIST/MBIST Build In Self Test/ Memory BIST
Cu ELK Copper Extreme Low-K (dielectric)
DRM/DRC Design Rule Manual/Design Rule Check
EM Electron Migration
GUI Graphic User Interface
HKMG High-K Metal gate
IO Input Output
IP Intellectual Property
LVS Layout Versus Schematic
MC2 Memory Compiler 2 (compiler tool vendor)
MUX Multiplexor
OS Operating System
PVT Process, Voltage, Temperature
RC Resistance and Capacitance
SRAM Static Random Access Memory
ROM Read Only Memory
SOC System On Chip
SDC Synopsys Design Constraints
STA Static Timing Analysis

Table 6.1: Abbreviation

6.2 Quick Troubleshooting for MC2 License Issues

If the license fails to check out properly, please follow the troubleshooting procedure step by step:
1. csh>setenv FLEXLM DIAGNOSTICS 3
2. csh>cd ✩MC2 INSTALL DIR/aux/flexlm/<platform>
<platform>could be below:
i86 r6, i86 re3 : Linux 32 bit on AMD/Intel CPU
amd64 re3 : Linux 64 bit on AMD/Intel CPU
sun4 u5, sun4 u8 : SunOS 32 bit on SPARC CPU
sun64 u5, sun64 u8 : SunOS 64 bit on SPARC CPU
x64 sun10 : SunOS 64 bit on AMD CPU
3. csh>./lmgrd -c <LICENSE FILE PATH>/license.dat -l interrad.log
4. csh>cd <PATH WHERE COMPILER IS PRESENT>
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 5. csh>mc2-eu -c <CompilerName>.mco

6. csh>✩MC2 INSTALL DIR/aux/flexlm/<platform>/lmutil lmstat -a

7. csh>✩MC2 INSTALL DIR/aux/flexlm/<platform>/lmutil lmhostid

8. csh>uname -a
9. How to get correct hostids,

In SunOS
csh>hostid

In Linux
csh>/sbin/ifconfig eth0
and remove colons from HWaddr 00:06:5B:1C:7B:B0 ->00065B1C7BB0

Commands 6 to 9 help you find the key information which needs to match the license file and installation environment.
If license still fails to check out after these trial, send us the output on the terminal for the above commands (1 to 9),
the file ”interrad.log” and the license file so that we can understand what the issue is and solve it in a timely manner.

6.3 Other Related Problems and Solutions

A user guide provided separately will also help the following problems:

❼ Incorrect hostid and responding message from OS system

❼ The license server fails to start the compiler due to multiple installation with different software

❼ License feature unavailable or network connection problem

❼ Incompatible OS platform issue

❼ Corruption of execution code after file transfer

❼ Environment parameter setting in OS shell

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