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@vtucode - in BCS402 Model Paper 2022 Scheme

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0% found this document useful (0 votes)
2K views2 pages

@vtucode - in BCS402 Model Paper 2022 Scheme

model paper

Uploaded by

Prof Murthy SVN
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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BCS402

Model Question Paper-1/2 with effect from 2023-24


USN

Fourth Semester B.E. Degree Examination


Subject Title: Microcontrollers
TIME: 03 Hours Max. Marks: 100

Note: 01. Answer any FIVE full questions, choosing at least ONE question from each MODULE.

*Bloom’s
Module -1 Taxonomy Marks
Level
Q.01 a L2 10
Mention the difference between 1. Microctroller and Microprocessor Marks
2. RISC and CISC

b L2 10
Explain the architecture of an ARM embedded device with the help of neat Marks
diagram.
OR
Q.02 a L2 10
Explain in detail about Current Program Status Register (CPSR). Marks
b With a neat diagram, explain embedded system Hardware. L2 10
Marks
Module-2
Q. 03 a L2 10
Explain different arithmetic instructions in ARM processor with an example. Marks
b L2 10
Explain single register load store addressing mode syntax, table, index mode with Marks
an example.
OR
Q.04 a L2 10
Explain barrel shifter instructions in ARM with suitable examples. Marks
b L2 10
Explain different Logical instructions in ARM processor with an example. Marks
Module-3
Q. 05 a Explain code optimization, profiling and cycle counting. L3 10
Marks
b Write a C program that prints the square of the integers between 0 to 9 using L3 10
functions and explain how to convert this C function to an assembly function Marks
with command.
OR
Q. 06 a Discuss how registers are allocated to optimize the program. L3 10
Marks
b Develop an ALP to find the sum of first 10 integer numbers. L3 10
Marks
Module-4
Q. 07 a With a neat diagram explain ARM processor exceptions and modes. L2 10
Marks
b Explain assigning interrupts and interrupt latency. L2 10
Marks
OR
Q. 08 a Briefly explain what happens when an IRQ and FIQ exception is raised with an L2 10
ARM processor. Marks

Page 01 of 02
BCS402
b Explain firmware execution flow and explain Red Hat RedBoot. L2 10
Marks
Module-5
Q. 09 a Explain the basic architecture of cache memory. L2 10
Marks
b Explain how main memory maps to a cache memory. L2 10
Marks
OR
Q. 10 a With a neat block diagram explain associative cache. L2 10
Marks
b L2 10
Briefly explain cache line replacement policies. Marks
*Bloom’s Taxonomy Level: Indicate as L1, L2, L3, L4, etc. It is also desirable to indicate the COs and POs to be
attained by every bit of questions.

Page 02 of 02

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