 Why Need Simulations:

To validate setup info. , design related constraints like clock definitions, reset definitions,
OCC related constraints , timing related constraints(cell delays , wire delays) , JTAG
programming , PLL programming etc.
If these constraints are proper , sure simulations be passed.
In simulations we replicate tester behavior.

o What are Inputs for no-timing and timing simulations?

For No timing simulation inputs :

Library files & Pre-layout netlist. Are enough.
For Timing simulation inputs :
Library files. Post-layout netlist. ,SDF file. , SDC file.
.

o What is difference between Pre-layout netlist and post-layout netlist?

o Pre-layout netlist : Pre-layout netlist is scan inserted netlist given to ATPG.
It is applied during no timing simulation. It doesn’t having any timing info.
o Post-layout netlist : Pre-layout netlist is given to Physical design team where they do layout
and routing by considering all cell and wire delays and later STA team check timing
closures(whether setup and hold requirements met or not by considering these cell and wire
delays).
o If Simulations fails then we need to check the reason for failures.
Following is the Flow Chart to help you identify the issues and below are queries to
proceed failures.
 Information on few Important files:
 SDF(Standard delay format) : SDF contain info. of actual cell delay , net
delays.
 SDC(Synopsys design constraints) : SDC contain info. of false path ,
multicycle path.
 Timing closure session : contains timing closures of every partition.
For e.g. : STA team closed timing for one partition. Run of that partition
saved and that saved run path will be pointed to us. It will help to debug
the timing checks for failure.

 Types of Simulations
Depending on Notiming & Timing Simulations , Details were mentioned
below:
 No-timing/Zero delay/Unit delay Simulations – Here the Simulations are
performed without considering the delays of the circuit. No-timing simulation is a
simulation method used to verify patterns before the SDF and post-layout netlist are
ready. It is done to check that the pattern generated is properly working or not.
 Timing Simulations - Here the Simulations are performed including the delays of
the circuits as cell delays, net delays etc. Timing Simulation is a simulation method
used to verify patterns after the SDF and post-layout netlist are ready.

 If Simulations failed in No timing Simulation Step:

 The setup is done for unit delay GLS (no SDF) and the testcases that are planned to
be run on gate level are run with this setup to clean the testbench.
 This is done because the unit delay simulations are relatively faster (than
those with SDF) and all the testbench/testcase related issues can be resolved
here like.
 change probed logic hierarchy from rtl to gate.
 wrong flow of testcase.
 First check for Chain Simulations and then go for Capture Simulations.
 use of uninitialized variables in the testcases that can cause corruption when
read via core
  Running the unit delay GLS is recommended because one can catch most of
the testbench/testcase issues before the arrival of SDF.
 After the SDF arrives, focus should be more on finding the real
design/timing issues

 If Simulations failed in Timing Simulation Step:

 Early SDF (for initial debug)
This step involves use of a sdf in which timing is met at a lower frequency
than target and GLS can be run at that frequency. This helps in cleaning up
the flow and finding certain issues before the final SDF arrives.
 First check for Chain Simulations and then go for Capture Simulations.
 Full speed SDF
This step starts with the sdf in which timing is met at target frequency. The
entire setup is done and the planned pattern-suite is run on this setup and
failures needs to be debugged according to a priority list which should be
made before hand. All the high priority patterns need to be debugged first.
 All issues found are discussed with the design and timing team and the
required fixes are done in the netlist/SDF. This process is repeated until the
GLS regression is clean on the final SDF.

 Simulation Modes
 Serial Simulation -
 In this mode the patterns are loaded as in the tester, thus we
obtain a very realistic indication of circuit operation.
 The disadvantage is that for each pattern, you must clock the scan
chain registers at least as many times as you have the scan cells in the
longest chain.
 Parallel Simulation -
 In this mode you can directly load the simulation model with
the necessary pattern values because you have the access to internal
node in design.
 Parallel Patterns are forced parallelly (at the same time) at SI of each
flop and measured at SO. Here only two cycles are required to
simulate a pattern – one is to force all the flops and one for capture.
 The disadvantage is that even though parallel simulations passes we
are not sure that it will pass in tester.
 Advantages and disadvantages of serial and parallel simulations
 In Serial Simulations we will get very realistic indication of circuit
operation, whereas we don’t get that in parallel simulation.
 Serial simulations is time consuming as it takes more time load, as
it must load all the flop cycles, whereas in parallel we have control to internal
nodes so we can get it done in two cycles.
 Serial simulations are difficult to debug as we don’t get any failing flop
name, but parallel simulations are easier to debug as we will get the info.
 Parallel simulations are not realistic, even though it is passing we will not
be sure that it will pass in tester.
 If Parallel patterns are passing and Serial patterns are failing.
  Some ways to debug -
 We can create debug patterns which can give us the failing flop.
 We can check the failing serial logfile note down the failing edt, fail type,
cycle number and with scan chain report find the failing flop.

 If Serial patterns are passing and Parallel patterns are failing.

 One of the reasons for Parallel to fail and serial to pass is due to
shadow flops.
 A shadow flop is a non-scan flop that has the D input connected to the Q
output of a scan flop.
 There are two types of Shadow flops
 Dependently clocked
 Independently clocked
 If the shadow flop is independently clocked, use a separate procedure
called shadow_control to load it.

 Debug Patterns in case of failures not identified in Serial & Parallel:

 Debug patterns are usually used when the parallel patterns are passing but serial
patterns are failing.
 Debug patterns is a type of parallel pattern with N number of Shift cycles.
 We can generate the debug patterns by this command in parameter file.
 SIM_POST_SHIFT N
 Tools Used for Simulation
 ModelSim (by Mentor Graphics)
 VCS (by Synopsys) , Verdi for debugging (by Synopsys)
 QuestaSim (by Mentor Graphics)
 NCSim/Simvision/XCelium (by Cadence)
 Steps for Debugging
 Step 1
 Obtain Debug files
 ATPG Logfile, flattened design, and ASCII/Binary Patterns.
 Verilog Simulation logfile and waveforms
 Step 2
 Shift or Capture Problem
 Extract information from ATPG logfile, simulation logfile, or
Verilog pattern
 First in ATPG log file , see the information about Black-boxes &
DRCs and clean those to avoid any simulation issues.
 Step 3
 Trace back
 Identify failing flop or pin and failing pattern.
 Display failing cell in waveform viewer and trace back.
 Step 4
 Identify problem
 Timing, OCC, internal pins, DRC, tool settings, library, design,
setup
 Step 5
 Implement Solution

 Create wave dump. Load in debug tool and trace the signals &
waveforms to check the issues.
 Fix timing problem, fix OCC definition/constraints, set
correct drc settings, fix library, fix tool settings, get correct
design, do correct setup.
 Example1 of Timing Sim Debug:

 Description:
D2 is data signal and Q2 is output of flop2 which is failing in Timing.
D1 and Q1 is data and output signal of flop1 which we will get by tracing
back flop2.
This is an ideal case, at 1500ns the value of Q2 is 1. which is as expected.
 Example2 of Timing Sim Debug:
 Description:
Here flop2 is failing as Q2 expected value is 1 (at 1500ns) but simulated
value is 0.
When we trace back to flop1 we see flop1 is working fine.
flop2 is failing due to the added delays (buf1 and buf2).

 Fault Categories in Tessent Tool: