R19 M.TECH.

CSE/CS

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

M. Tech - CSE/CS – I Year – II Semester
Common to CSE and CS Syllabus

ADVANCED COMPUTER ARCHITECTURE (Professional Core - IV)

Prerequisites: Computer Organization

Course Objectives:
1. To impart the concepts and principles of parallel and advanced computer architectures.
2. To develop the design techniques of Scalable and multithreaded Architectures.
3. To Apply the concepts and techniques of parallel and advanced computer architectures to
design modern computer systems

Course Outcomes: Gain knowledge of

1. Computational models and Computer Architectures.
2. Concepts of parallel computer models.
3. Scalable Architectures, Pipelining, Superscalar processors, multiprocessors

UNIT - I
Theory of Parallelism, Parallel computer models, The State of Computing, Multiprocessors and
Multicomputers, Multivector and SIMD Computers, PRAM and VLSI models, Architectural development
tracks, Program and network properties, Conditions of parallelism, Program partitioning and
Scheduling, Program flow Mechanisms, System interconnect Architectures.

UNIT - II
Principals of Scalable performance, Performance metrics and measures, Parallel Processing
applications, Speed up performance laws, Scalability Analysis and Approaches, Hardware
Technologies, Processes and Memory Hierarchy, Advanced Processor Technology, Superscalar and
Vector Processors, Memory Hierarchy Technology, Virtual Memory Technology.

UNIT - III
Bus Cache and Shared memory, Backplane bus systems, Cache Memory organizations, Shared-
Memory Organizations, Sequential and weak consistency models, Pipelining and superscalar
techniques, Linear Pipeline Processors, Non-Linear Pipeline Processors, Instruction Pipeline design,
Arithmetic pipeline design, superscalar pipeline design.

UNIT - IV
Parallel and Scalable Architectures, Multiprocessors and Multicomputers, Multiprocessor system
interconnects, cache coherence and synchronization mechanism, Three Generations of
Multicomputers, Message-passing Mechanisms, Multivetor and SIMD computers, Vector Processing
Principals, Multivector Multiprocessors, Compound Vector processing, SIMD computer Organizations,
The connection machine CM-5,

UNIT - V
Scalable, Multithreaded and Dataflow Architectures, Latency-hiding techniques, Principals of
Multithreading, Fine-Grain Multicomputers, Scalable and multithreaded Architectures, Dataflow and
hybrid Architectures.

Text Book
1. Advanced Computer Architecture, Kai Hwang, 2nd Edition, Tata McGraw Hill Publishers.

Page 26 of 55
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Code No: 5658AW Rl9

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech II Semer;ter Examinations, March - 2023
.4.DVANCED C(]M PTI'I-E R ARCH ITECTTI RE
(Com purcr Scicnce and Engincering)
me: 3 Ho urs l: /f,

Note: i) Question paper consists of par1A, part B.

ii) Part A is compulsory, which carries 25 m arks. In Part A, Answer all questions
iii) In Parl B, Ansrver any one question lionr each unit. Each question carries l0 marks
and have A;b AS b q uc:;t ion s.

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"PART_A,. (25 Marks)

1a) Describe the major milestones in computer development. t5]

b) What do yorl mean by degree of parallelism? Ilorv clo you cornpute average parallelisrr?
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c) d s.l '

d) of bar 5l
e) Explain processor consistency nrodel
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FAR.'I'- B
(50 Marks)

2-a) Give the Flynn's,CIhssification c,f CO

:'i b) Describe shared-lnornory m u lti
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3.a) Make a comparison of network characteristics of dynamic connection networks.
b) Give an overview of various levels of parallelism in programs with examples. Is+5]
4.a) What are the important characteristics of parallel algorithms?
b) exp I's law.

.a) Gi an hierarch
b) Describe the typical architecture of superscalar processors Is+s]
6a) Describe direct-n-rapping cache organization.
b) Exolain seouential consistency rnodel. [5+5]
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7.a) what,ii,a linear,pipeline pro".ssor?,Describ. uryn"h.o,rous linear pipel'ine prOCeSSOrr
l,ode'I. , '- '' . 1

b) Explain internal data forwarding mechanism in pipelining with an example [5+5]

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8 a) What do you mean by caclie cotrerence problem? Explain snoopy bus protocols.
b) What is a virtual channel? Explain horv deadlocks can be avoided using virtual channe ls.

i,l [s+5]
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.a)
b) S

l0.a) Explain various context-switching policics.

b) What do you mcan by fine-grain parallelism? Explain the architecture of Message-Driven
Processor (MDP) using a schenratic block diagrarn.
[5+5]
I l.a)
b) Tera

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Code No: 5658AW

R19
.IAWAHAITLAL NEHRU TECHNO LO(;ICAL T]N IVERS ITY H YDII IIABAI)
M. Tech II Semcster Examina(it)ns, September/October -2022
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ADVANCED COMPUTI'R ARGHITECTURE ,. . ,,..
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Tim e: 3 rs '..

Ansn er an-v ii'.,s questions

All questions cal'ry equai marks

1 .a)
:
I)cscribc il1
b) C-'ornparc and

2. Drarv a ncat sketch to explain in detail about various architectllral developlnental

tracks. t I 5l

3. Describe how the superscalars and vector processors work? How their performance is
rleasured? [15]
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.ri 4 .a) of virlua
b) and lain in pnncrp of p [8+7]

5 a) Explain direct mapping of cache memor"'y'. Mention its advar,tages and disadvantages.
b) Draw a neat sketch anci expiain the cont:r:pt of non-iinear pipeiinirig. i8=7]

6.a) With ttre hclp of a neat diagrarn. explain,the concept o1'arithtnetic pipe design
b r Discuss in detail about the concept o1'trackplane bus s)'stem [8+7] ',, :,
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7.a) Describe in detail about various message passing mechanisms.

b) With a neat diagram, explain SIMD computer organization. IB+7]

8.a) Explain the multithreaded architecture with the help of a neat diagram.
b) Discuss in detail about fine grain mul ticomputer. [8+7]
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