VLSI Design

MODULE 1
Dr. Shashank M Gowda
Associate Professor,
Department of ECE, YIT, Moodbidri
 Introduction
◼ It all started in 1958
◼ First IC with 2 transistors at Texas Instruments.
◼ Flip-Flop by Jack Kilby- Nobel Prize for IC in 2000

◼ As on 2023
◼ 134 billion transistors in Apple Microprocessor
◼ 153 billion transistors in AMD’s GPU
◼ TSMC's 5 nm semiconductor manufacturing process.
1 billion is equivalent to 100 crores

◼ Reason
◼ As transistors became smaller
◼ They became faster Became Cheaper to Manufacture
◼ Dissipate less power Consumed Less Power
Introduction
◼ First was point contact transistor.
◼ Bipolar Junction Transistor
◼ Reliable, less noisy, and more power efficient
◼ Power dissipated by the base currents was more even when the
device is not switching
◼ Field Effect Transistor’s
◼ MOSFET’s found its way in 1960’s.
◼ Zero Control current in idle state.
▪ Types- nMOS and pMOS

◼ CMOS Logic
◼ Complementary MOS
◼ nMOS Logic Gates- Intel’s nMOS technology
A Brief History
Invention of the Transistor
◼ Vacuum tubes ruled in first half of 20th century
◼ Large, Expensive, Power- hungry, Unreliable.
◼ 1947: First point contact transistor (3 terminal devices)
◼ Shockley, Bardeen and Brattain at Bell Labs
A Brief History

❑ 1958: First Integrated Circuit

◼ Flip- Flop using two transistors.
◼ Built by Jack Kilby (Nobel Laureate) at Texas Instruments.
◼ Robert Noyce (Fairchild) is also considered as a co-inventor.

Kilby’s IC
A Brief History
◼ First Planer IC built in 1961

◼ 2003
◼ Intel Pentium 4 processor (55 million transistors)
◼ 512 Mbit DRAM (> 0.5 billion transistors)
◼ 53% compound annual growth rate over 45 years
◼ No other technology has grown so fast so long
◼ Driven by miniaturization of transistors
◼ Smaller is cheaper, faster, lower in power!
◼ Revolutionary effects on society
MOS Integrated Circuits
❑ 1970’s processes usually had only nMOS transistors
Inexpensive, but consume power while idle
❑ 1980s-present: CMOS processes for low idle power

Intel 1101 256-bit SRAM Intel 4004 4-bit Proc

Moore’s Law
◼ 1965: Gordon Moore plotted transistor on each chip
◼ Fit straight line on semilog scale
◼ Transistor counts have doubled every two years.
Pentium 4 Processor
• Modern transistors are few microns wide and approximately
0.1 micron or less in length
• Human hair is 80-90 microns in diameter
Evolution in Logic Complexity in IC’s
Features of Integrated Circuits
Types of Design
Full Custom or Semi Custom

→Performance Requirements.

→The Technology being used.

→The expected lifetime of the product.

→Cost of the Product.

Silicon Semiconductors
◼ Modern electronic chips are built mostly on silicon substrates
◼ Silicon is a Group IV semiconducting material
◼ crystal lattice: covalent bonds hold each atom to four neighbours

Si Si Si

Si Si Si

Si Si Si
 Dopants
◼ Silicon is a semiconductor at room temperature
◼ Pure silicon has few free carriers and conducts poorly
◼ Adding dopants increases the conductivity drastically
◼ Dopant from Group V (e.g. As, P): extra electron (n-type)
◼ Dopant from Group III (e.g. B, Al): missing electron, called
hole (p-type)

Si Si Si Si Si Si
- +
+ -
Si As Si Si B Si

Si Si Si Si Si Si
p-n Junctions
◼ First semiconductor (two terminal) devices
◼ A junction between p-type and n-type
semiconductor forms a diode.
◼ Current flows only in one direction

p-type n-type

anode cathode
Transistor Types
◼ Bipolar transistors
◼ npn or pnp silicon structure
◼ Small current into very thin base layer controls large
currents between emitter and collector
◼ Base currents limit integration density

◼ Metal Oxide Semiconductor Field Effect Transistors

◼ nMOS and pMOS MOSFETS
◼ Voltage applied to insulated gate controls current
between source and drain
◼ Low power allows very high integration
◼ First patent in the ’20s in USA and Germany
◼ Not widely used until the ’60s or ’70s
Simplified View of MOSFET
 MOS Transistors
◼ Four terminal device: gate, source, drain, body
◼ Gate – oxide – body stack looks like a capacitor
◼ Gate and body are conductors (body is also called the substrate)
◼ SiO2 (oxide) is a “good” insulator (separates the gate from the body
◼ Called metal–oxide–semiconductor (MOS) capacitor, even though
gate is mostly made of poly-crystalline silicon (polysilicon)

Source Gate Drain Source Gate Drain

Polysilicon Polysilicon
SiO 2 SiO 2

n+ n+ p+ p+
p bulk Si n bulk Si

NMOS PMOS
NMOS Operation
◼ Body is commonly tied to ground (0 V)
◼ Drain is at a higher voltage than Source
◼ When the gate is at a low voltage:
◼ P-type body is at low voltage
◼ Source-body and drain-body “diodes” are OFF
◼ No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si
NMOS Operation Cont.
◼ When the gate is at a high voltage: Positive charge
on gate of MOS capacitor
◼ Negative charge is attracted to body under the gate
◼ Inverts a channel under gate to “n-type” (N-channel, hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
◼ Now current can flow through “n-type” silicon from source
through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si
PMOS Transistor
◼ Similar, but doping and voltages reversed
◼ Body tied to high voltage (VDD)
◼ Drain is at a lower voltage than the Source
◼ Gate low: transistor ON
◼ Gate high: transistor OFF
◼ Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO 2

p+ p+
n bulk Si
Power Supply Voltage
◼ GND = 0 V

◼ In 1980’s, VDD = 5V

◼ VDD has decreased in modern processes

◼ High VDD would damage modern tiny
transistors
◼ Lower VDD saves power

◼ VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,

Transistors as Switches
◼ In Digital circuits, MOS transistors are
electrically controlled switches.

◼ Voltage at gate controls path from source to

drain. g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d
pMOS g OFF
ON
s s s
CMOS Logic
→ A static CMOS gate has
→ An nMOS pull-down network to connect the output to 0 (GND)
→ An pMOS pull-up network to connect the output to 1 (VDD)
 CMOS Logic
→ When both pull-up and pull-down are OFF, the highimpedance or floating Z
output state results.
→ This is of importance in multiplexers, memory elements, and tristate bus
drivers.
→ The crowbarred (or contention) X level exists when both pull-up and pull-
down are simultaneously turned ON.
→ Contention between the two networks results in an indeterminate output level
and dissipates static power.
→ It is usually an unwanted condition.
CMOS Logic
Connection and behavior of series and parallel transistors
CMOS Logic
Connection and behavior of series and parallel transistors
CMOS Inverter

A Y
0
1

A Y
CMOS Inverter

A Y VDD
0
1

A Y

A Y
GND
CMOS Inverter

A Y VDD
0
1

A Y

A Y
GND
CMOS Inverter

A Y VDD
0
1 0 OFF
A=1 Y=0
ON Y is pulled low by the
turned on NMOS
Device. Hence
A Y NMOS is the pull-
down device.
GND

BACK
CMOS Inverter

A Y VDD Y is pulled high by

0 1 the turned on PMOS
Device. Hence PMOS

1 0 ON is the pull-up device.

A=0 Y=1
OFF
A Y
GND
CMOS NAND Gate
A B Y
0 0
0 1
1 0
1 1
CMOS NAND Gate
A B Y
0 0 1
0 1 1 Y
1 0 1 A
1 1 0
B
CMOS NAND Gate
A B Y
0 0 1 ON ON
0 1 Y=1
1 0
A=0 OFF
1 1
B=0 OFF
CMOS NAND Gate
A B Y
0 0 1 OFF ON
0 1 1 Y=1
1 0
A=0 OFF
1 1
B=1 ON
CMOS NAND Gate
A B Y
0 0 1 ON OFF
0 1 1 Y=1
1 0 1
A=1 ON
1 1
B=0 OFF
CMOS NAND Gate
A B Y
0 0 1 OFF OFF
0 1 1 Y=0
1 0 1
A=1 ON
1 1 0
B=1 ON
CMOS NAND Gate
CMOS NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y
3-input NAND Gate
◼ Y is pulled low if ALL inputs are 1
◼ Y is pulled high if ANY input is 0
3-input NAND Gate
◼ Y is pulled low if ALL inputs are 1
◼ Y is pulled high if ANY input is 0

Y
A
B
C
3-input NOR Gate
→ If any input is high, the output is pulled low through the nMOS
transistors.
→ If all inputs are low, the output is pulled high through the pMOS
transistors.
3-input NOR Gate
→ If any input is high, the output is pulled low through the parallel nMOS
transistors.
→ If all inputs are low, the output is pulled high through the series pMOS
transistors.
 Compound Gates
→More complex logic function in a single stage of logic.
→Using a combination of series and parallel switch structures.

→Example

Y = (A · B) + (C · D)

AND-OR-INVERT-22, or AOI22
 Compound Gates
→ The AND expressions (A · B) and (C · D) may be
implemented by series connections of switches.
 Compound Gates
→ Now ORing the result requires the parallel connection of these two
structures.

→ For the pMOS pull-up network, we must compute the complementary

expression using switches that turn on with inverted polarity.

→ Transistors that appear in series in the pull-down network must appear in

parallel in the pull-up network.
 Compound Gates
→ Putting the networks together yields the full schematic conduction
complements
OR-AND-INVERT-3-1 or OAI31
Y = (A + B + C) · D
OR-AND-INVERT-3-1 or OAI31
Y = (A + B + C) · D
2:1 MUX using AOI22

2:1 MUX Y

Y= ~s.a + s.b
S
2:1 MUX using AOI22
Signal Strength
→The strength of a signal is measured by how closely it
approximates an ideal voltage source.

→The power supplies, or rails, (VDD and GND) are the

source of the strongest 1s and 0s.

→nMOS passes a strong 0, weak 1.

→pMOS passes a strong 1, weak 0.

Weak 1: HIGH voltage level is somewhat less than VDD .

Weak 0: LOW voltage level is somewhat greater than 0 .
Signal Strength

Note that both the control input and its complement are required by the
transmission gate. This is called double rail logic.
 VIDEO LINK
nmos ON → g=1
pmos ON → g=0
Transmission gate
→ When an nMOS or pMOS is used alone as an imperfect switch. Single nmos
or pmos is also called as pass transistor.
→ By combining an nMOS and a pMOS transistor in parallel we get a
transmission gate or pass gate.
Tristate Buffer
→When the enable input EN is 1, the
output Y equals the input A.

→When the enable is 0, Y is left floating.

Tristate buffer symbol

→The transmission gate in figure, has the
same truth table as a tristate buffer.

Transmission gate Symbol

Tristate Inverter
 Multiplexers
→A multiplexer chooses the output from among several
inputs based on a select signal.

→A 2-input, or 2:1 multiplexer,

→Chooses input D0 when the select is 0
→Chooses input D1 when the select is 1.

→The logic function is

Multiplexers
 Multiplexers
→Two transmission gates can be tied
together to form a compact 2-input

Logic Circuit
multiplexer.

→The select and its complement

enable exactly one of the two
transmission gates at any given
time.

Symbol
→The transmission gates produce a
nonrestoring multiplexer.

Transmission gate MUX

Multiplexers
 Multiplexers
→ Build a restoring, inverting multiplexer out of gates.

→ Using Compound gates.

 Read more..

Sequential Circuits
→ Combinational circuits, whose outputs depend only on the current
inputs.

→ Sequential circuits have memory: their outputs depend on both

current and previous inputs.

→ latches and flip-flops receive a clock, CLK, and a data input, D, and
produce an output, Q.

→ A D latch is transparent when CLK = 1, meaning that Q follows D.

→ It becomes opaque when CLK = 0, meaning Q retains its previous

value and ignores changes in D.

→ An edge-triggered flip-flop copies D to Q on the rising edge of

CLK and remembers its old value at other times.
 Latches : D Latch
→ A D latch built from a 2-input multiplexer and two
inverters.

→ The multiplexer can be built from a pair of

transmission gates.
Latches : D Latch
→The multiplexer can be built from a pair of
transmission gates.
Latches : D Latch
→When CLK = 1, the latch is transparent and D flows
through to Q.

→When CLK = 0, the latch becomes opaque, and a

feedback path around the inverter pair is established to
hold the current state of Q indefinitely.
 Latches : D Latch
→ The D latch is also known as a level-sensitive latch

→ The state of the output is dependent on the level of

the clock signal
Latches : D Latch

CLK CLK

LATCH Q D LATCH Q
D

Positive-level-sensitive latch Negative-level-sensitive latch

Flop- Flop : Edge Triggered D-FF
→Edge-triggered flip-flop.
→By combining two level-sensitive latches, one
negative-sensitive and one positive-sensitive
→The first latch stage is called the master and the
second is called the slave.

Master Slave
 Flop- Flop : Edge Triggered D-FF
→ While CLK is LOW, the master negative-level-
sensitive latch output (QM) follows the D input

→ The slave positive-level-sensitive latch holds the

previous value

=0

1=

Master Slave
 Flop- Flop : Edge Triggered D-FF
→When the CLK transitions from 0 to 1, the master
latch becomes opaque and holds the D value at the
time of the clock transition.

→The slave latch becomes transparent, passing the

stored master value (QM) to the output of the slave
latch (Q).
=1
→The D input is blocked from
affecting the output because the 0=
master is disconnected from the
D input

Master Slave
 Flop- Flop : Edge Triggered D-FF
→This flip-flop copies D to Q on the rising edge of the clock.

→Thus, this device is called a positive-edge triggered flip-flop.

→Also called a D flip-flop, D register, or master–slave flip-flop.

 MOS transistor symbols

nMOS

pMOS

→ The MOS transistor is a majority-carrier device in which the current in a

conducting channel between the source and drain is controlled by a voltage applied
to the gate.
→ nMOS → Electrons
→ pMOS → Holes
Isolated MOS Structure
→ Isolated MOS structure with a gate and body but no source or drain.

Polysilicon Gate
Silicon Dioxide Insulator

+ + + + + + + + + + +
+ + + + + + + + + + +
+ + + + + + + + + + + P-type Body

+ + + + + + + + + + +
+ + + + + + + + + + +
Accumulation Mode
→ A negative voltage is applied to the gate.

→ There is negative charge on the gate.

→ The mobile positively charged holes are attracted to the region

beneath the gate.
 Depletion Mode
→ A small positive voltage is applied to the gate.

→ This results in some positive charge on the gate.

→ The holes in the body are repelled from the region directly beneath
the gate

→ This results in a depletion region forming below the gate.

 Inversion Mode
→ A higher positive potential exceeding a critical threshold voltage Vt is
applied

→ This higher positive voltage, attracts more positive charge to the gate.
→ The holes are repelled further and some free electrons in the body are
attracted to the region beneath the gate.
→ This conductive layer of electrons in the p-type body is called the
inversion layer.
nMOS transistor
 That small amounts of leakage
currents through OFF transistors
can become significant, especially
Cutoff when multiplied by millions or
billions of transistors on a chip.

→ the gate-to-source voltage Vgs is less than the threshold voltage.

→ The source and drain have free electrons.
→ The body has free holes but no free electrons.
→ If the source is grounded, the junctions between the body and the
source or drain are reverse-biased, so little or no current flows.

→ We say the transistor is OFF, and this mode of operation is called

cutoff.
 Linear
→ The gate voltage is greater than the threshold voltage.
→ Now an inversion region of electrons (majority carriers) called the
channel connects the source and drain.
→ It creates a conductive path and turning the transistor ON.
→ The number of carriers and the conductivity increases with the
gate voltage.
 Linear
→ The potential difference between drain and source is

→ There is no electric field tending to push current from drain to source.

 Linear
→ When a small positive potential Vds is applied to the drain.
→ Current Ids flows through the channel from drain to source.
→ The current increases with increase in both the drain voltage and gate
voltage.
→ This mode is called
→ Linear
→ Resistive →Triode
→ Nonsaturated →Unsaturated
 Saturation
→ If Vds becomes sufficiently large that
Vgd < Vt

→ The channel is no longer inverted near the drain and becomes pinched off

→ However, conduction is still brought about by the drift of electrons under the
influence of the positive drain voltage.
 Saturation
→ As electrons reach the end of the channel
→ They are injected into the depletion region near the drain and
accelerated toward the drain.

→ Above this drain voltage the current Ids is controlled only by the gate
voltage and ceases to be influenced by the drain.

→ This mode is called saturation.

 Summary
→The nMOS transistor has three modes of operation.

→ If Vgs < Vt , the transistor is cutoff (OFF). CUTOFF

→ If Vgs > Vt , the transistor turns ON. LINEAR

→ If Vds is small, the transistor acts as a linear resistor in which
the current flow is proportional to Vds.

→ If Vgs > Vt and Vds is large, the transistor acts as a current source
in which the current flow becomes independent of Vds .
SATURATION
Summary
 Long- Channel I-V Characterstics
→ To derive a Model relating the current and voltage (I-V) for an nMOS
transistor in each of the three regions.

→ The model assumes that the channel length is long enough that the lateral
electric field i.e., the field between source and drain, is relatively low.

→ This model is variously known as the long-channel, ideal, first-order, or

Shockley model.

→ The long-channel model assumes that the current through an OFF

transistor is 0.

→ When a transistor turns ON (Vgs > Vt), the gate attracts carriers (electrons)
to form a channel.

→ The electrons drift from source to drain at a rate proportional to the

electric field between these regions.
 Long- Channel I-V Characterstics
→ We can compute currents if we know the amount of charge in the channel
and the rate at which it moves.

→ We know that the charge on each plate of a capacitor is Q = CV.

→ Thus, the charge in the channel Qchannel is,

Where, Cg is the capacitance of the gate to the channel

Vgc is the voltage between the gate and the channel

Vgc - Vt is the amount of voltage attracting charge to the channel

beyond the minimum required to invert from p to n.
 Long- Channel I-V Characterstics
→ If Source is at Vs. Vg

→ Drain is at Vd.
Vs Vd
→ Gate voltage is Vg.
→ Channel Voltage is Vc. n+ n+
Vc
Long- Channel I-V Characterstics
Long- Channel I-V Characterstics
 Long- Channel I-V Characterstics
→ We can model the gate as a parallel plate
capacitor with capacitance proportional to area
over thickness.

→ If the gate has length L and width W and the

oxide thickness is tox

→ Then the capacitance is given as,

→ The εox/tox term is called Cox, the capacitance per unit area of the gate oxide.
 Long- Channel I-V Characterstics
→ Each carrier in the channel is accelerated to an average velocity, v,
proportional to the lateral electric field,
→ i.e., the field between source and drain.

→ The constant of proportionality µ is called the mobility.

Long- Channel I-V Characterstics
 Long- Channel I-V Characterstics
→ The time required for carriers to cross the
channel is the channel length divided by the
carrier velocity:

▲t = L/v.

→ The current between source and drain is the total

amount of charge in the channel divided by the
time required to cross

→ The current between source and drain is the total

amount of charge in the channel divided by the
time required to cross,
Long- Channel I-V Characterstics
Long- Channel I-V Characterstics
Long- Channel I-V Characterstics
Long- Channel I-V Characterstics
Long- Channel I-V Characterstics
Long- Channel I-V Characterstics

The current in the three regions,

Long- Channel I-V Characterstics

I- V Characteristics of Ideal nMOS Transistor

Long- Channel I-V Characterstics

I- V Characteristics of Ideal pMOS Transistor

DC Transfer Characteristics
 DC Transfer Characteristics
→Digital circuits are merely analog circuits used over
a special portion of their range.

→The DC transfer characteristics of a circuit relate the

output voltage to the input voltage.
→Assuming the input changes slowly enough that
capacitances have plenty of time to charge or discharge.

→ Specific ranges of input and output voltages are

defined as valid 0 and 1 logic levels.
Static CMOS Inverter DC
Characteristics

WORKING OF THE CMOS INVERTER WHEN INPUT IS 1

WORKING OF THE CMOS INVERTER WHEN INPUT IS 0

Static CMOS Inverter DC
Characteristics
Static CMOS Inverter DC
Characteristics
→Vtn is the threshold voltage of the n-channel device (+ve Voltage)

→Vtp is the threshold voltage of the p-channel device (-ve Voltage)

→The equations are given both in terms of Vgs /Vds and Vin /Vout.

→As the source of the nMOS transistor is grounded,

→Vgsn =(Vg - Vs)n = (Vg - 0)n= (Vg)n = Vin
→Vdsn = (Vd - Vs)n = (Vd - 0)n= (Vd)n = Vout

→ As the source of the pMOS transistor is tied to VDD,

→Vgsp = (Vg - Vs)p = Vin – VDD
→Vdsp = (Vd - Vs)p = Vout – VDD.
Static CMOS Inverter DC
Characteristics
Relationships between voltages for the three regions of operation of a CMOS inverter
Static CMOS Inverter DC
Characteristics
Relationships between voltages for the three regions of operation of a CMOS inverter
Static CMOS Inverter DC
Characteristics
→ Assume

→Vtp = –Vtn

→ The pMOS transistor is 2–3 times as wide as the

nMOS transistor so βn = βp.
Static CMOS Inverter DC
Characteristics
Static CMOS Inverter DC
Characteristics
→ The supply current IDD = Idsn = |Idsp| is also plotted against Vin in
Figure showing that both transistors are momentarily ON as Vin
passes through voltages between GND and VDD
Static CMOS Inverter DC
Characteristics
Static CMOS Inverter DC
Characteristics
→The operation of the CMOS inverter can be divided
into five regions.

→ Region A
→ The nMOS transistor is OFF so the pMOS
transistor pulls the output to VDD.

→ Region B
→ The nMOS transistor starts to turn ON, pulling
the output down.
Static CMOS Inverter DC
Characteristics
→Region C
→Both transistors are in saturation.

→ Region D
→The pMOS transistor is partially ON

→ Region E
→ The pMOS transistor is completely OFF
Static CMOS Inverter DC
Characteristics
 Beta Ratio Effects
→We have seen that for βp = βn, the inverter threshold voltage
Vin=VDD/2.

→Inverters with different beta ratios r = β p / β n are called

skewed inverters.
→If r > 1, the inverter is HI-skewed.

→If r < 1, the inverter is LO-skewed.

→If r = 1, the inverter has normal skew or is unskewed.

→As the beta ratio is changed, the switching threshold moves.

Beta Ratio Effects

Transfer characteristics of skewed inverters

 Noise Margin
→It allows you to determine the allowable noise voltage on
the input of a gate so that the output will not be corrupted.

→The noise margin of an Inverter is Defined by the Noice

Margin Low (NML) and Noise Margin High (NMH)

→The LOW noise margin, NML

→The HIGH noise margin, NMH

Noise Margin