AM26LV32E

SLLS849E – APRIL 2008 – REVISED AUGUST 2023

AM26LV32E Low-Voltage High-Speed Quadruple Differential Line Receiver

With ±15-KV IEC ESD Protection

1 Features 3 Description
• Meets or exceeds standard TIA/EIA-422-B and The AM26LV32E device consists of quadruple
ITU recommendation V.11 differential line receivers with 3-state outputs. This
• Operates from a single 3.3-V power supply device is designed to meet TIA/EIA-422-B and ITU
• Switching rates up to 32 MHz recommendation V.11 drivers with reduced supply
• ESD Protection for RS422 bus pins voltage. The device is optimized for balanced bus
(See ESD Ratings) transmission at switching rates up to 32 MHz. The
• Low power dissipation: 27 mW typical 3-state outputs permit connection directly to a bus-
• Open circuit fail-safe organized system. The AM26LV32E has an internal
• ±7-V Common-mode input voltage range with fail-safe circuitry that prevents the device from putting
±200-mV sensitivity an unknown voltage signal at the receiver outputs.
• Accepts 5-V logic inputs with 3.3-V supply (enable In the open fail-safe, a high state is produced at
inputs) the respective output. This device is supported for
• Input hysteresis: 35 mV typical partial-power-down applications using Ioff. Ioff circuitry
• Pin-to-pin compatible with AM26C32, AM26LS32 disables the outputs, preventing damaging current
• Ioff Supports partial-power-down mode operation back-flow through the device when it is powered
down.
2 Applications
Package Information
• High-reliability automotive applications
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
• Configuration control and print support
• ATM and cash counters SO (16) 10.2 mm × 7.8 mm
• Smart grid SOIC (16) 9.9 mm x 6 mm
AM26LV32E
• AC and servo motor drives VQFN (16) 4 mm x 3.5 mm
TSSOP (16) 5 mm x 6.4 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.
(2) The package size (length × width) is a nominal value and
includes pins, where applicable.
G 4
12
G

1A 2
3 1Y
1B 1

2A 6
5 2Y
2B 7

3A 10
11 3Y
3B 9

4A 14
13 4Y
4B 15

Logic Diagram (Positive Logic)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.3 Feature Description.....................................................8
2 Applications..................................................................... 1 8.4 Device Functional Modes............................................9
3 Description.......................................................................1 9 Application Information Disclaimer............................. 10
4 Revision History.............................................................. 2 9.1 Application Information............................................. 10
5 Pin Configuration and Functions...................................3 9.2 Typical Application.................................................... 10
6 Specifications.................................................................. 4 10 Power Supply Recommendations..............................11
6.1 Absolute Maximum Ratings........................................ 4 11 Layout........................................................................... 12
6.2 ESD Ratings............................................................... 4 11.1 Layout Guidelines................................................... 12
6.3 Recommended Operating Conditions.........................4 11.2 Layout Example...................................................... 12
6.4 Thermal Information....................................................5 12 Device and Documentation Support..........................13
6.5 Electrical Characteristics.............................................5 12.1 Receiving Notification of Documentation Updates..13
6.6 Switching Characteristics............................................6 12.2 Support Resources................................................. 13
6.7 Typical Characteristics................................................ 6 12.3 Trademarks............................................................. 13
7 Parameter Measurement Information............................ 7 12.4 Electrostatic Discharge Caution..............................13
8 Detailed Description........................................................8 12.5 Glossary..................................................................13
8.1 Overview..................................................................... 8 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram........................................... 8 Information.................................................................... 13

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December 2020) to Revision E (August 2023) Page
• Changed the Device Information table to the Package Information table.......................................................... 1
• Changed the Thermal Information ..................................................................................................................... 5
• Changed the Typical Characteristics ................................................................................................................. 6

Changes from Revision C (July 2018) to Revision D (December 2020) Page

• Changed feature From: Open Circuit, Short Circuit, and Terminated Fail-Safe To: Open Circuit Fail-Safe ...... 1
• Deleted text from the Description: shorted fail-safe, and terminated fail-safe To: Open Circuit Fail-Safe .........1
• Deleted text from the last paragraph in Input Fail-Safe Circuitry: terminated or short .......................................8
• Deleted text from Table 8-1: shorted, or terminated .......................................................................................... 9

Changes from Revision B (July 2015) to Revision C (July 2018) Page

• Changed the pinout image appearance .............................................................................................................3
• Changed the A and B Input signals on the waveform of Figure 7-1 .................................................................. 7

Changes from Revision A (May 2008) to Revision B (July 2015) Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1

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5 Pin Configuration and Functions

VCC
1B
1B 1 16 VCC

1A 2 15 4B

16
1Y 3 14 4A
1A 2 15 4B

G 4 13 4Y
1Y 3 14 4A

2Y 5 12 G Thermal
G 4 13 4Y
Pad
2A 6 11 3Y
2Y 5 12 G

2B 7 10 3A
2A 6 11 3Y

GND 8 9 3B
2B 7 10 3A

9
Not to scale

Figure 5-1. D, NS, or PW Package, 16-Pin SOIC,

Not to scale
SO, or TSSOP

GND

3B
(Top View)
Figure 5-2. RGY Package 16-Pin VQFN
(Top View)

Table 5-1. Pin Functions

PIN
TYPE DESCRIPTION
NAME NO.
1A 2 I RS422/RS485 differential input (noninverting)
1B 1 I RS422/RS485 differential input (inverting)
1Y 3 O Logic level output
2A 6 I RS422/RS485 differential input (noninverting)
2B 7 I RS422/RS485 differential input (inverting)
2Y 5 O Logic level output
3A 10 I RS422/RS485 differential input (noninverting)
3B 9 I RS422/RS485 differential input (inverting)
3Y 11 O Logic level output
4A 14 I RS422/RS485 differential input (noninverting)
4B 15 I RS422/RS485 differential input (inverting)
4Y 13 O Logic level output
G 4 I Active-high select
G 12 I Active-low select
GND 8 — Ground
VCC 16 — Power Supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (3)
MIN MAX UNIT
VCC Supply voltage(2) -0.5 6 V
A or B inputs –14 14
VI Input voltage V
G or G inputs –0.5 6
VID Differential input voltage(4) –14 14 V
VO Output voltage –0.5 6 V
IO Output current ±20 mA
IIK Input clamp current VI < 0 -20 mA
IOK Output clamp current VO < 0 -20 mA
TJ Operating virtual junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values except differential input voltage are with respect to the network GND.
(3) This device is designed to meet TIA/EIA-422-B and ITU.
(4) Differential input voltage is measured at the non-inverting input with respect to the corresponding inverting input.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±15000
V(ESD) Electrostatic discharge IEC61000-4-2, Contact Gap Discharge ±8000 V
IEC61000-4-2, Air Gap Discharge ±15000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±15000 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0 0.8 V
VIC Common-mode input voltage –7 7 V
VID Differential input voltage –7 7 V
IOH High-level output current –5 mA
IOL Low-level output current 5 mA
TA Operating free-air temperature –40 85 °C

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6.4 Thermal Information

AM26LV32E
D (SOIC) DR (SOIC- PW PWR NS (SOP) NSR (SOP- RGY RGY
THERMAL METRIC(1) Reel) (TSSOP) (TSSOP- Reel) (VQFN) (VQFN) UNIT
Reel)
16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS
Junction-to-ambient
RθJA 73.1 84.6 109 107.5 69 88.5 92 48.4 °C/W
thermal resistance
Rθ Junction-to-case (top)
38.4 43.5 34 38.4 34 46.2 40 46.4 °C/W
JC(top) thermal resistance

Junction-to-board thermal
RθJB N/A 43.2 N/A 53.7 N/A 50.7 N/A 24.6 °C/W
resistance

Junction-to-top
ΨJT N/A 10.4 N/A 3.2 N/A 13.5 N/A 2.3 °C/W
characterization parameter
Junction-to-board
ΨJB N/A 42.8 N/A 53.1 N/A 50.3 N/A 24.5 °C/W
characterization parameter
Rθ
Junction-to-case (bottom)
JC(bottom N/A N/A N/A N/A N/A N/A N/A 8.5 °C/W
thermal resistance
)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics

over recommended ranges of common-mode input, supply voltage, and operating free-air temperature (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Positive-going input threshold voltage,
VIT+ 0.2 V
differential input
Negative-going input threshold voltage,
VIT– –0.2 V
differential input
Vhys Input hysteresis (VIT+ – VIT–) 35 mV
VIK Input clamp voltage, G and G II = –18 mA –1.5 V
VID = 200 mV, IOH = –5 mA 2.4 3.2
VOH High-level output voltage VCC – V
VID = 200 mV, IOH = –100 μA
0.1
VID = –200 mV, IOL = 5 mA 0.17 0.5
VOL Low-level output voltage V
VID = –200 mV, IOL = 100 μA 0.1
IOZ High-impedance state output current VO = VCC or GND ±50 μA
Ioff Output current with power off VCC = 0 V, VO = 0 or 5.5 V ±100 μA
VI = 10 V 1.5
II Line input current Other input at 0 V mA
VI = –10 V –2.5
II Enable input current, G and G VI = VCC or GND ±1 μA
ri Input resistance VIC = –7 V to 7 V, Other input at 0 V 4 17 kΩ
ICC Supply current (total package) G, G = VCC or GND, No load, Line inputs open 8 17 mA
Cpd Power dissipation capacitance One channel 150 pF

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6.6 Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tPLH Propagation delay time, low- to high-level output 8 16 26 ns
See Figure 7-1
tPHL Propagation delay time, high- to low-level output 8 16 26 ns
tt Transition time See Figure 7-1 5 ns
tPZH Output-enable time to high-level See Figure 7-2 17 40 ns
tPZL Output-enable time to low-level See Figure 7-2 10 40 ns
tPHZ Output-disable time from high-level See Figure 7-2 20 40 ns
tPLZ Output-disable time from low-level See Figure 7-2 16 40 ns
tsk(p) Pulse skew See Figure 7-1 Figure 7-2 4 6 ns
tsk(o) Pulse skew See Figure 7-1 Figure 7-2 4 6 ns
tsk(pp) Pulse skew (device to device) See Figure 7-1 Figure 7-2 6 9 ns
f(max) Maximum operating frequency See Figure 7-1 32 MHz

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

6.7 Typical Characteristics

Figure 6-1. Output Voltage vs Input Current

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7 Parameter Measurement Information

A
Generator Y B 2V
VO
(see Note B) B Input
CL = 15 pF A 1V
50Ÿ 50Ÿ (see Note A)
tPLH tPHL

VOH
90% 90%
VCC Output 50% 50%
10% 10% V
OL
G G tr tf
(see Note C)
A. CL includes probe and jig capacitance.

Figure 7-1. Switching Test Circuit and Voltage Waveforms

A Y
VID = 1 V VO
B
RL = 2 kΩ CL = 15 pF
(see Note A)
G
Generator G
(see Note B) 50 Ω

VCC
(see Note C)

VCC
Input 50% 50%
0V
tPZH tPHZ

VOH
VOH - 0.3 V
Output
Voff ≈ 0
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle ≤ 50%, tr = tf = 6 ns.

Figure 7-2. Enable/Disable Time Test Circuit and Output Voltage Waveforms

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8 Detailed Description
8.1 Overview
The AM26LV32E is a low-voltage, quadruple-differential line receiver that meets the necessary requirements for
NSI TIA/EIA-422-B, TIA/EIA-423-B, and ITU Recommendation V.10 and V.11. This device allows a low power or
low voltage MCU to interface with heavy machinery, subsystems and other devices through long wires of up to
1000 m, giving any design a reliable and easy to use connection. As with any RS422 interface, the AM26LV32E
works in a differential voltage range, which enables very good signal integrity.
8.2 Functional Block Diagram

EQUIVALENT OF EACH INPUT (A, B) EQUIVALENT OF EACH TYPICAL OF EACH RECEIVER OUTPUT
ENABLE INPUT (G, G)

VCC VCC VCC

2.4 kΩ

5 kΩ 7 kΩ 1.5 kΩ Enable Output

A, B G, G

200 kΩ 1.5 kΩ

VCC(A)
or
GND(B) 2.4 kΩ
GND GND
GND

8.3 Feature Description

8.3.1 ±7-V Common-Mode Range With ±200-mV Sensitivity
For a common-mode voltage varying from –7 V to 7 V, the input voltage is acceptable in low ranges greater than
200 mV as a standard.
8.3.2 Input Fail-Safe Circuitry
RS-485 specifies that the receiver output state should be logic high for differential input voltages of VAB ≥ +200
mV and logic low for VAB ≤ –200 mV. For input voltages in between these limits, a receiver’s output state is
not defined and can randomly assume high or low. Removing the uncertainty of random output states, modern
transceiver designs include internal biasing circuits that put the receiver output into a defined state (typically
high) in the absence of a valid input signal. A loss of input signal can be caused by:
• an open circuit caused by a wire break or the unintentional disconnection of a transceiver from the bus
• a short circuit due to an insulation fault, connecting both conductors of a differential pair to one another
• an idle bus when none of the bus transceivers are active.
An open circuit caused by a wire break or the unintentional disconnection of a transceiver from the bus. The
AM26LV32E has an internal circuit that ensures functionality during an open failure.
8.3.3 Active-High and Active-Low
The device can be configure using the G and G logic inputs to select receiver output. The high voltage or logic 1
on the G pin, allows the device to operate on an active-high and having a low voltage or logic 0 on the G enables
active low operation. These are simply a way to configure the logic to match that of the receiving or transmitting
controller or microprocessor.

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8.4 Device Functional Modes

8.4.1 Enable and Disable
The receivers implemented in these RS422 devices can be configured using the G and G pins to be enabled or
disabled. This allows users to ignore or filter out transmissions as desired.
Table 8-1. Function Table (Each Driver)
DIFFERENTIAL ENABLES(1)
OUTPUT
INPUT G G
H X H
VID ≥ 0.2 V
X L H
H X ?
–0.2 V < VID < 0.2 V
X L ?
H X L
VID ≤ –0.2 V
X L L
H X H
Open
X L H
X L H Z

(1) H = high-level, L = low-level, X = irrelevant,

Z = high impedance (off), ? = indeterminate

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9 Application Information Disclaimer

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

When designing a system that uses drivers, receivers, and transceivers that comply with RS-422 or RS-485,
proper cable termination is essential for highly reliable applications with reduced reflections in the transmission
line. Because RS-422 allows only one driver on the bus, if termination is used, it is placed only at the end
of the cable near the last receiver. In general, RS-485 requires termination at both ends of the cable. Factors
to consider when determining the type of termination usually are performance requirements of the application
and the ever-present factor, cost. The different types of termination techniques discussed are unterminated
lines, parallel termination, ac termination, and multipoint termination. Laboratory waveforms for each termination
technique (except multipoint termination) illustrate the usefulness and robustness of RS-422 (and, indirectly,
RS- 485). Similar results can be obtained if 485-compliant devices and termination techniques are used. For
laboratory experiments, 100 feet of 100-Ω, 24-AWG, twisted-pair cable (Bertek) was used. A single driver and
receiver, TI AM26LV31E and AM26LV32E, respectively, were tested at room temperature with a 3.3-V supply
voltage. Two plots per termination technique are shown. In each plot, the top waveform is the driver input and
the bottom waveform is the receiver output. To show voltage waveforms related to transmission-line reflections,
the first plot shows output waveforms from the driver at the start of the cable; the second plot shows input
waveforms to the receiver at the far end of the cable.
9.2 Typical Application
AM26LV31E AM26LV32E
(One Driver) (One Receiver)
RT
DIN ROUT
D D

Figure 9-1. Differential Terminated Configuration

9.2.1 Design Requirements

Resistor and capacitor (if used) termination values are shown for each laboratory experiment, but vary
from system to system. For example, the termination resistor, RT, must be within 20% of the characteristic
impedance, ROUT , of the cable and can vary from about 80 Ω to 120 Ω.
9.2.2 Detailed Design Procedure
Figure 9-1 shows a configuration with RT as termination. Although reflections are present at the receiver inputs
at a data signaling rate of 200 kbps with no termination, the RS-422-compliant receiver reads only the input
differential voltage and produces a clean signal at the output.

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9.2.3 Application Curve

5

Voltage (V)
1

±1

±2

±3 Y A/B
±4
0 0.1 0.2 0.3 0.4 0.5
Time ( s) C001

Figure 9-2. Differential 120-Ω Terminated Output Waveforms (CAT 5E Cable)

10 Power Supply Recommendations

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies.

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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it
is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
VDD

VCC
1B 1 16

1A 2 15 4B 0.1µF

Termination Resistor 1Y 3 14 4A

Reduce logic signal trace G 4 13 4Y

when possible
AM26LV32E
2Y 5 12 G

2A 6 11 3Y

2B 7 10 3A
GND
8 9 3B

Figure 11-1. Trace Layout on PCB and Recommendations

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

AM26LV32EIDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26LV32EI Samples

AM26LV32EIDRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26LV32EI Samples

AM26LV32EINSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26LV32EI Samples

AM26LV32EIPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 SB32 Samples

AM26LV32EIPWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 SB32 Samples

AM26LV32EIRGYR ACTIVE VQFN RGY 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 SB32 Samples

AM26LV32EIRGYRG4 ACTIVE VQFN RGY 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 SB32 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

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(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF AM26LV32E :

• Enhanced Product : AM26LV32E-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 28-Feb-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AM26LV32EIDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
AM26LV32EIDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
AM26LV32EINSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
AM26LV32EINSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
AM26LV32EIPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
AM26LV32EIPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
AM26LV32EIRGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 28-Feb-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
AM26LV32EIDR SOIC D 16 2500 353.0 353.0 32.0
AM26LV32EIDR SOIC D 16 2500 356.0 356.0 35.0
AM26LV32EINSR SO NS 16 2000 353.0 353.0 32.0
AM26LV32EINSR SO NS 16 2000 356.0 356.0 35.0
AM26LV32EIPWR TSSOP PW 16 2000 353.0 353.0 32.0
AM26LV32EIPWR TSSOP PW 16 2000 367.0 367.0 35.0
AM26LV32EIRGYR VQFN RGY 16 3000 360.0 360.0 36.0

Pack Materials-Page 2
 PACKAGE OUTLINE
NS0016A SCALE 1.500
SOP - 2.00 mm max height
SOP

8.2 SEATING PLANE

TYP
7.4
A PIN 1 ID 0.1 C
AREA
14X 1.27
16
1

10.4 2X
10.0 8.89
NOTE 3

8
9
0.51
16X
5.4 0.35
B 0.25 C A B 2.00 MAX
5.2
NOTE 4

0.15 TYP

SEE DETAIL A
0.25 0.3
GAGE PLANE 0.1

0 - 10
1.05
0.55 DETAIL A
TYPICAL
(1.25)

4220735/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SEE

SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP

(7)

LAND PATTERN EXAMPLE

SCALE:7X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220735/A 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP (7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220735/A 12/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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