Model Sr830: DSP Lock-In Amplifier

MODEL SR830
DSP Lock-In Amplifier
1290-D Reamwood Avenue

Sunnyvale, California 94089
Phone: (408) 744-9040 • Fax: (408) 744-9049
email: [email protected] • www.thinkSRS.com
Copyright © 1993, 2011 by SRS, Inc.

All Rights Reserved.
Revision 2.5 (10/2011)

TABLE OF CONTENTS
GENERAL INFORMATION REAR PANEL

Safety and Preparation for Use 1-3 Power Entry Module 4-27
Specifications 1-5 IEEE-488 Connector 4-27
Abridged Command List 1-7 RS232 Connector 4-27
Aux Inputs (A/D Inputs) 4-27
GETTING STARTED Aux Outputs (D/A Outputs) 4-27
X and Y Outputs 4-27
Your First Measurements 2-1
Signal Monitor Output 4-28
The Basic Lock-in 2-3
Trigger Input 4-28
X, Y, R and q 2-7
TTL Sync Output 4-28
Outputs, Offsets and Expands 2-9
Preamp Connector 4-28
Storing and Recalling Setups 2-13
Using SRS Preamps 4-29
Aux Outputs and Inputs 2-15
SR830 BASICS PROGRAMMING

GPIB Communications 5-1
What is a Lock-in Amplifier? 3-1
RS232 Communications 5-1
What Does a Lock-in Measure? 3-3
Status Indicators and Queues 5-1
The SR830 Functional Diagram 3-5
Command Syntax 5-1
Reference Channel 3-7
Interface Ready and Status 5-2
Phase Sensitive Detectors 3-9
GET (Group Execute Trigger) 5-2
Time Constants and DC Gain 3-11
DC Outputs and Scaling 3-13
Dynamic Reserve 3-15 DETAILED COMMAND LIST 5-3
Signal Input Amplifier and Filters 3-17 Reference and Phase 5-4
Input Connections 3-19 Input and Filter 5-5
Intrinsic (Random) Noise Sources 3-21 Gain and Time Constant 5-6
External Noise Sources 3-23 Display and Output 5-8
Noise Measurements 3-25 Aux Input and Output 5-9
Setup 5-10
Auto Functions 5-11
OPERATION Data Storage 5-12
Power On/Off and Power On Tests 4-1 Data Transfer 5-15
Reset 4-1 Interface 5-19
[Keys] 4-1 Status Reporting 5-20
Spin Knob 4-1
Front Panel BNC Connectors 4-2 STATUS BYTE DEFINITIONS
Key Click On/Off 4-2 Serial Poll Status Byte 5-21
Front Panel Display Test 4-2 Service Requests 5-22
Display Off Operation 4-2 Standard Event Status Byte 5-22
Keypad Test 4-3 LIA Status Byte 5-23
Standard Settings 4-4 Error Status Byte 5-23
PROGRAM EXAMPLES
FRONT PANEL Microsoft C, Nationall Instr GPIB 5-25
Signal Input and Filters 4-5
Sensitivity, Reserve, Time USING SR530 PROGRAMS 5-31
Constants 4-7
CH1 Display and Output 4-12
CH2 Display and Output 4-15 TESTING
Reference 4-18 Introduction 6-1
Auto Functions 4-21 Preset 6-1
Setup 4-23 Serial Number 6-1
Interface 4-24 Firmware Revision 6-1
Warning Messages 4-26 Test Record 6-1
If A Test Fails 6-1
Necessary Equipment 6-1
1-1
TABLE OF CONTENTS
Front Panel Display Test 6-2
Keypad Test 6-2
PERFORMANCE TESTS
Self Tests 6-3
DC Offset 6-5
Common Mode Rejection 6-7
Amplitude Accuracy and Flatness 6-9
Amplitude Linearity 6-11
Frequency Accuracy 6-13
Phase Accuracy 6-15
Sine Output Amplitude 6-17
DC Outputs and Inputs 6-19
Input Noise 6-21
Performance Test Record 6-23
CIRCUITRY
Circuit Boards 7-1
CPU and Power Supply Board 7-3
DSP Logic Board 7-5
Analog Input Board 7-7
PARTS LISTS
DSP Logic Board 7-9
Analog Input Board 7-16
CPU and Power Supply Board 7-22
Front Panel Display Boards 7-26
Miscellaneous 7-33
SCHEMATIC DIAGRAMS
CPU and Power Supply Board
Display Board
Keypad Board
DSP Logic Board
Analog Input Board
1-2
SAFETY AND PREPARATION FOR USE
WARNING
Dangerous voltages, capable of causing injury or death, are present in this instrument. Use extreme
caution whenever the instrument covers are removed. Do not remove the covers while the unit is
plugged into a live outlet.
CAUTION SERVICE
This instrument may be damaged if operated Do not attempt to service or adjust this instrument
with the LINE VOLTAGE SELECTOR set for the unless another person, capable of providing first aid
wrong AC line voltage or if the wrong fuse is or resuscitation, is present.
installed.
Do not install substitute parts or perform any
LINE VOLTAGE SELECTION unauthorized modifications to this instrument.
Contact the factory for instructions on how to return
The SR830 operates from a 100V, 120V, 220V, the instrument for authorized service and
or 240V nominal AC power source having a line adjustment.
frequency of 50 or 60 Hz. Before connecting the
power cord to a power source, verify that the FURNISHED Accessories
LINE VOLTAGE SELECTOR card, located in the
rear panel fuse holder, is set so that the correct - Power Cord
AC input voltage value is visible. - Operating Manual
Conversion to other AC input voltages requires a ENVIRONMENTAL CONDITIONS

change in the fuse holder voltage card position
and fuse value. Disconnect the power cord, open OPERATING
the fuse holder cover door and rotate the fuse- Temperature: +10 °C to + 40 °C
pull lever to remove the fuse. Remove the small (Specifications apply over + 18 °C to +28 °C)
printed circuit board and select the operating Relative Humidity: <90 % Non-condensing
voltage by orienting the printed circuit board so
that the desired voltage is visible when pushed NON-OPERATING
firmly into its slot. Rotate the fuse-pull lever back Temperature: -25 °C to 65 °C
into its normal position and insert the correct Humidity: <95 % Non-condensing
fuse into the fuse holder.
WARNING REGARDING USE WITH
LINE FUSE PHOTOMULTIPLIERS AND OTHER DETECTORS
Verify that the correct line fuse is installed before The front end amplifier of this instrument is easily
connecting the line cord. For 100V/120V, use a 1 damaged if a photomultiplier is used improperly with
Amp fuse and for 220V/240V, use a 1/2 Amp the amplifier. When left completely unterminated, a
fuse. cable connected to a PMT can charge to several
hundred volts in a relatively short time. If this cable is
LINE CORD connected to the inputs of the SR830 the stored
charge may damage the front-end op amps. To
The SR830 has a detachable, three-wire power avoid this problem, always discharge the cable and
cord for connection to the power source and to a connect the PMT output to the SR830 input before
protective ground. The exposed metal parts of turning the PMT on.
the instrument are connected to the outlet
ground to protect against electrical shock.
Always use an outlet which has a properly
connected protective ground.
1-3
Symbols you may Find on SRS Products
Symbol Description
Alternating current
Caution - risk of electric shock
Frame or chassis terminal
Caution - refer to accompanying documents
Earth (ground) terminal
Battery
Fuse
On (supply)
Off (supply)
1-4
SR830 DSP LOCK-IN AMPLIFIER
SPECIFICATIONS
SIGNAL CHANNEL
Voltage Inputs Single-ended (A) or differential (A-B).
Current Input 106 or 10 8 Volts/Amp.
Full Scale Sensitivity 2 nV to 1 V in a 1-2-5-10 sequence (expand off).
Input Impedance Voltage: 10 MΩ+25 pF, AC or DC coupled.
Current: 1 kΩ to virtual ground.
Gain Accuracy ±1% from 20°C to 30°C (notch filters off), ±0.2 % Typical.
Input Noise 6 nV/√Hz at 1 kHz (typical).
Signal Filters 60 (50) Hz and 120(100) Hz notch filters (Q=4).
CMRR 100 dB to10 kHz (DC Coupled), decreasing by 6db/octave above 10 kHz
Dynamic Reserve Greater than 100 dB (with no signal filters).
Harmonic Distortion -80 dB.
REFERENCE CHANNEL
Frequency Range 1 mHz to 102 kHz
Reference Input TTL (rising or falling edge) or Sine.
Sine input is1 MΩ, AC coupled (>1 Hz). 400 mV pk-pk minimum signal.
Phase Resolution 0.01°
Absolute Phase Error <1°
Relative Phase Error <0.01°
Orthogonality 90° ± 0.001°
Phase Noise External synthesized reference: 0.005° rms at 1 kHz, 100 ms, 12 dB/oct.
Internal reference: crystal synthesized, <0.0001° rms at 1 kHz.
Phase Drift <0.01°/°C below 10 kHz
<0.1°/°C to 100 kHz
Harmonic Detect Detect at Nxf where N<19999 and Nxf<102 kHz.
Acquisition Time (2 cycles + 5 ms) or 40 ms, whichever is greater.
DEMODULATOR
Zero Stability Digital displays have no zero drift on all dynamic reserves.
Analog outputs: <5 ppm/°C for all dynamic reserves.
Time Constants 10 µs to 30 s (reference > 200 Hz). 6, 12, 18, 24 dB/oct rolloff.
up to 30000 s (reference < 200 Hz). 6, 12, 18, 24 dB/oct rolloff.
Synchronous filtering available below 200 Hz.
Harmonic Rejection -80 dB
INTERNAL OSCILLATOR
Frequency 1 mHz to 102 kHz.
Frequency Accuracy 25 ppm + 30 µHz
Frequency Resolution 4 1/2 digits or 0.1 mHz, whichever is greater.
Distortion f<10 kHz, below -80 dBc. f>10 kHz, below -70 dBc.1 Vrms amplitude.
Output Impedance 50 Ω
Amplitude 4 mVrms to 5 Vrms (into a high impedance load) with 2 mV resolution.
(2 mVrms to 2.5 Vrms into 50Ω load).
Amplitude Accuracy 1%
Amplitude Stability 50 ppm/°C
Outputs Sine output on front panel. TTL sync output on rear panel.
When using an external reference, both outputs are phase locked to the
external reference.
1-5
SR830 DSP Lock-In Amplifier
DISPLAYS
Channel 1 4 1/2 digit LED display with 40 segment LED bar graph.
X, R, X Noise, Aux Input 1 or 2. The display can also be any of these
quantities divided by Aux Input 1 or 2.
Channel 2 4 1/2 digit LED display with 40 segment LED bar graph.
Y, θ, Y Noise, Aux Input 3 or 4. The display can also be any of these
quantities divided by Aux Input 3 or 4.
Offset X, Y and R may be offset up to ±105% of full scale.
Expand X, Y and R may be expanded by 10 or 100.
Reference 4 1/2 digit LED display.
Display and modify reference frequency or phase, sine output amplitude,
harmonic detect, offset percentage (X, Y or R), or Aux Outputs 1-4.
Data Buffer 16k points from both Channel 1 and Channel 2 display may be stored
internally. The internal data sample rate ranges from 512 Hz down to 1
point every 16 seconds. Samples can also be externally triggered. The data
buffer is accessible only over the computer interface.
INPUTS AND OUTPUTS

Channel 1 Output Output proportional to Channel 1 display, or X.
Output Voltage: ±10 V full scale. 10 mA max output current.
Channel 2 Output Output proportional to Channel 2 display, or Y.
X and Y Outputs Rear panel outputs of cosine (X) and sine (Y) components.
Aux. Outputs 4 BNC Digital to Analog outputs.
±10.5 V full scale, 1 mV resolution. 10 mA max output current.
Aux. Inputs 4 BNC Analog to Digital inputs.
Differential inputs with1 MΩ input impedance on both shield and center
conductor. ±10.5 V full scale, 1 mV resolution.
Trigger Input TTL trigger input triggers stored data samples.
Monitor Output Analog output of signal amplifiers (before the demodulator).
GENERAL
Interfaces IEEE-488 and RS232 interfaces standard.
All instrument functions can be controlled through the IEEE-488 and RS232
interfaces.
Preamp Power Power connector for SR550 and SR552 preamplifiers.
Power 40 Watts, 100/120/220/240 VAC, 50/60 Hz.
Dimensions 17"W x 5.25"H x 19.5"D
Weight 30 lbs.
Warranty One year parts and labor on materials and workmanship.
1-6
COMMAND LIST
VARIABLES i,j,k,l,m Integers
f Frequency (real)
x,y,z Real Numbers
s String
REFERENCE and PHASE page description

PHAS (?) {x} 5-4 Set (Query) the Phase Shift to x degrees.
FMOD (?) {i} 5-4 Set (Query) the Reference Source to External (0) or Internal (1).
FREQ (?) {f} 5-4 Set (Query) the Reference Frequency to f Hz.Set only in Internal reference mode.
RSLP (?) {i} 5-4 Set (Query) the External Reference Slope to Sine(0), TTL Rising (1), or TTL Falling (2).
HARM (?) {i} 5-4 Set (Query) the Detection Harmonic to 1 ≤ i ≤ 19999 and i•f ≤ 102 kHz.
SLVL (?) {x} 5-4 Set (Query) the Sine Output Amplitude to x Vrms. 0.004 ≤ x ≤5.000.
INPUT and FILTER page description

ISRC (?) {i} 5-5 Set (Query) the Input Configuration to A (0), A-B (1) , I (1 MΩ) (2) or I (100 MΩ) (3).
IGND (?) {i} 5-5 Set (Query) the Input Shield Grounding to Float (0) or Ground (1).
ICPL (?) {i} 5-5 Set (Query) the Input Coupling to AC (0) or DC (1).
ILIN (?) {i} 5-5 Set (Query) the Line Notch Filters to Out (0), Line In (1) , 2xLine In (2), or Both In (3).
GAIN and TIME CONSTANT page description

SENS (?) {i} 5-6 Set (Query) the Sensitivity to 2 nV (0) through 1 V (26) rms full scale.
RMOD (?) {i} 5-6 Set (Query) the Dynamic Reserve Mode to HighReserve (0), Normal (1), or Low Noise (2).
OFLT (?) {i} 5-6 Set (Query) the Time Constant to 10 µs (0) through 30 ks (19).
OFSL (?) {i} 5-6 Set (Query) the Low Pass Filter Slope to 6 (0), 12 (1), 18 (2) or 24 (3) dB/oct.
SYNC (?) {i} 5-7 Set (Query) the Synchronous Filter to Off (0) or On below 200 Hz (1).
DISPLAY and OUTPUT page description

DDEF (?) i {, j, k} 5-8 Set (Query) the CH1 or CH2 (i=1,2) display to XY, Rθ, XnYn, Aux 1,3 or Aux 2,4 (j=0..4)
and ratio the display to None, Aux1,3 or Aux 2,4 (k=0,1,2).
FPOP (?) i {, j} 5-8 Set (Query) the CH1 (i=1) or CH2 (i=2) Output Source to X or Y (j=1) or Display (j=0).
OEXP (?) i {, x, j} 5-8 Set (Query) the X, Y, R (i=1,2,3) Offset to x percent ( -105.00 ≤ x ≤ 105.00)
and Expand to 1, 10 or 100 (j=0,1,2).
AOFF i 5-8 Auto Offset X, Y, R (i=1,2,3).
AUX INPUT/OUTPUT page description

OAUX ? i 5-9 Query the value of Aux Input i (1,2,3,4).
AUXV (?) i {, x} 5-9 Set (Query) voltage of Aux Output i (1,2,3,4) to x Volts. -10.500 ≤ x ≤ 10.500.
SETUP page description

OUTX (?) {i} 5-10 Set (Query) the Output Interface to RS232 (0) or GPIB (1).
OVRM (?) {i} 5-10 Set (Query) the GPIB Overide Remote state to Off (0) or On (1).
KCLK (?) {i} 5-10 Set (Query) the Key Click to Off (0) or On (1).
ALRM (?) {i} 5-10 Set (Query) the Alarms to Off (0) or On (1).
SSET i 5-10 Save current setup to setting buffer i (1≤i≤9).
RSET i 5-10 Recall current setup from setting buffer i (1≤i≤9).
AUTO FUNCTIONS page description

AGAN 5-11 Auto Gain function. Same as pressing the [AUTO GAIN] key.
ARSV 5-11 Auto Reserve function. Same as pressing the [AUTO RESERVE] key.
APHS 5-11 Auto Phase function. Same as pressing the [AUTO PHASE] key.
AOFF i 5-11 Auto Offset X,Y or R (i=1,2,3).
1-7
DATA STORAGE page description

SRAT (?) {i} 5-13 Set (Query) the DataSample Rate to 62.5 mHz (0) through 512 Hz (13) or Trigger (14).
SEND (?) {i} 5-13 Set (Query) the Data Scan Mode to 1 Shot (0) or Loop (1).
TRIG 5-13 Software trigger command. Same as trigger input.
TSTR (?) {i} 5-13 Set (Query) the Trigger Starts Scan modeto No (0) or Yes (1).
STRT 5-13 Start or continue a scan.
PAUS 5-13 Pause a scan. Does not reset a paused or done scan.
REST 5-14 Reset the scan. All stored data is lost.
DATA TRANSFER page description

OUTP? i 5-15 Query the value of X (1), Y (2), R (3) or θ (4). Returns ASCII floating point value.
OUTR? i 5-15 Query the value of Display i (1,2). Returns ASCII floating point value.
SNAP?i,j{,k,l,m,n} 5-15 Query the value of 2 thru 6 paramters at once.
OAUX? i 5-16 Query the value of Aux Input i (1,2,3,4). Returns ASCII floating point value.
SPTS? 5-16 Query the number of points stored in Display buffer.
TRCA? i,j,k 5-16 Read k≥1 points starting at bin j≥0 from Display i (1,2) buffer in ASCII floating point.
TRCB? i,j,k 5-16 Read k≥1 points starting at bin j≥0 from Display i (1,2) buffer in IEEE binary floating point.
TRCL? i,j,k 5-17 Read k≥1 points starting at bin j≥0 from Display i (1,2) buffer in non-normalized binary floating
point.
FAST (?) {i} 5-17 Set (Query) Fast Data Transfer Mode On (1 or 2) or Off (0).On will transfer binary X and Y
every sample during a scan over the GPIB interface.
STRD 5-18 Start a scan after 0.5sec delay. Use with Fast Data Transfer Mode.
INTERFACE page description

❋RST 5-19 Reset the unit to its default configurations.
❋IDN? 5-19 Read the SR830 device identification string.
LOCL(?) {i} 5-19 Set (Query) the Local/Remote state to LOCAL (0), REMOTE (1), or LOCAL LOCKOUT (2).
OVRM (?) {i} 5-19 Set (Query) the GPIB Overide Remote state to Off (0) or On (1).
TRIG 5-19 Software trigger command. Same as trigger input.
STATUS page description

❋CLS 5-20 Clear all status bytes.
❋ESE (?) {i} {,j} 5-20 Set (Query) the Standard Event Status Byte Enable Register to the decimal value i (0-255).
❋ESE i,j sets bit i (0-7) to j (0 or 1). ❋ESE? queries the byte. ❋ESE?i queries only bit i.
❋ESR? {i} 5-20 Query the Standard Event Status Byte. If i is included, only bit i is queried.
❋SRE (?) {i} {,j} 5-20 Set (Query) the Serial Poll Enable Register to the decimal value i (0-255). ❋SRE i,j sets bit i (0-
7) to j (0 or 1). ❋SRE? queries the byte, ❋SRE?i queries only bit i.
❋STB? {i} 5-20 Query the Serial Poll Status Byte. If i is included, only bit i is queried.
❋PSC (?) {i} 5-20 Set (Query) the Power On Status Clear bit to Set (1) or Clear (0).
ERRE (?) {i} {,j} 5-20 Set (Query) the Error Status Enable Register to the decimal value i (0-255). ERRE i,j sets bit i
(0-7) to j (0 or 1). ERRE? queries the byte, ERRE?i queries only bit i.
ERRS? {i} 5-20 Query the Error Status Byte. If i is included, only bit i is queried.
LIAE (?) {i} {,j} 5-20 Set (Query) the LIA Status Enable Register to the decimal value i (0-255). LIAE i,j sets
bit i (0-7) to j (0 or 1). LIAE? queries the byte, LIAE?i queries only bit i.
LIAS? {i} 5-20 Query the LIA Status Byte. If i is included, only bit i is queried.
1-8
STATUS BYTE DEFINITIONS
SERIAL POLL STATUS BYTE (5-21) LIA STATUS BYTE (5-23)
bit name usage bit name usage

0 SCN No data is being acquired 0 RSRV/INPT Set when on RESERVE or INPUT overload
1 IFC No command execution in progress 1 FILTR Set when on FILTR overload
2 ERR Unmasked bit in error status byte set 2 OUTPT Set when on OUTPT overload
3 LIA Unmasked bit in LIA status byte set 3 UNLK Set when on reference unlock
4 MAV The interface output buffer is non-empty 4 RANGE Set when detection freq crosses 200 Hz
5 ESB Unmasked bit in standard status byte set 5 TC Set when time constant is changed
6 SRQ SRQ (service request) has occurred 6 TRIG Set when unit is triggered
7 Unused 7 Unused
STANDARD EVENT STATUS BYTE (5-22) ERROR STATUS BYTE (5-23)
bit name usage bit name usage

0 INP Set on input queue overflow 0 Unused
1 Unused 1 Backup Error Set when battery backup fails
2 QRY Set on output queue overflow 2 RAM Error Set when RAM Memory test finds an error
3 Unused 3 Unused
4 EXE Set when command execution error occurs 4 ROM Error Set when ROM Memory test finds an error
5 CMD Set when an illegal command is received 5 GPIB Error Set when GPIB binary data transfer aborts
6 URQ Set by any key press or knob rotation 6 DSP Error Set when DSP test finds an error
7 PON Set by power-on 7 Math Error Set when an internal math error occurs
1-9
1-10
GETTING STARTED
YOUR FIRST MEASUREMENTS
The sample measurements described in this section are designed to acquaint the first time user with the
SR830 DSP Lock-In Amplifier. Do not be concerned that your measurements do not exactly agree with these
exercises. The focus of these measurement exercises is to learn how to use the instrument.
It is highly recommended that the first time user step through some or all of these exercises before attempting
to perform an actual experiment.
The experimental procedures are detailed in two columns. The left column lists the actual steps in the experi-
ment. The right column is an explanation of each step.
[Keys] Front panel keys are referred to in brackets such as [Display] where
'Display' is the key label.
Knob The knob is used to adjust parameters which are displayed in the
Reference display.
2-1
Getting Started
2-2
The Basic Lock-in
THE BASIC LOCK-IN

This measurement is designed to use the internal oscillator to explore some of the basic lock-in functions.
You will need BNC cables.
Specifically, you will measure the amplitude of the Sine Out at various frequencies, sensitivities, time con-
stants and phase shifts.
1. Disconnect all cables from the lock-in. Turn When the power is turned on with the [Setup] key
the power on while holding down the [Setup] pressed, the lock-in returns to its standard default
key. Wait until the power-on tests are settings. See the Standard Settings list in the
completed. Operation section for a complete listing of the
settings.
The Channel 1 display shows X and Channel 2

shows Y.
2. Connect the Sine Out on the front panel to the The lock-in defaults to the internal oscillator refer-
A input using a BNC cable. ence set at 1.000 kHz. The reference mode is indi-
cated by the INTERNAL led. In this mode, the
lock-in generates a synchronous sine output at the
internal reference frequency.
The input impedance of the lock-in is 10 MΩ. The

Sine Out has an output impedance of 50Ω. Since
the Sine Output amplitude is specified into a high
impedance load, the output impedance does not
affect the amplitude.
The sine amplitude is 1.000 Vrms and the

sensitivity is 1 V(rms). Since the phase shift of the
sine output is very close to zero, Channel 1 (X)
should read close to 1.000 V and Channel 2 (Y)
should read close to 0.000 V.
3. Press [Auto Phase] Automatically adjust the reference phase shift to

eliminate any residual phase error. This should set
the value of Y to zero.
4. Press [Phase] Display the reference phase shift in the Reference

display. The phase shift should be close to zero.
5. Press the [+90°] key. This adds 90° to the reference phase shift. The
value of X drops to zero and Y becomes minus the
magnitude (-1.000 V).
2-3
The Basic Lock-in
The knob is used to adjust parameters which are

Use the knob to adjust the phase shift until Y shown in the Reference display, such as phase,
is zero and X is equal to the positive amplitude and frequency. The final phase value
amplitude. should be close to zero again.
Use the Auto Phase function to return Y to zero

Press [Auto Phase] and X to the amplitude.
Show the internal oscillator frequency in the

6. Press [Freq] Reference display.
The knob now adjusts the frequency. The meas-

Use the knob to adjust the frequency to ured signal amplitude should stay within 1% of 1 V
10 kHz. and the phase shift should stay close to zero (the
value of Y should stay close to zero).
The internal oscillator is crystal synthesized with

Use the knob to adjust the frequency back to 25 ppm of frequency error. The frequency can be
1 kHz. set with 4 1/2 digit or 0.1 mHz resolution, whichev-
er is greater.
Show the sine output amplitude in the Reference

7. Press [Ampl] display.
As the amplitude is changed, the measured value

Use the knob to adjust the amplitude to of X should equal the sine output amplitude. The
0.01 V. sine amplitude can be set from 4 mV to 5 V rms
into high impedance (half the amplitude into a 50
Ω load).
The Auto Gain function will adjust the sensitivity so

8. Press [Auto Gain] that the measured magnitude (R) is a sizable per-
centage of full scale. Watch the sensitivity indica-
tors change.
Parameters which have many options, such as

9. Press [Sensitivity Up] to select 50 mV full sensitivity and time constant, are changed with up
scale. and down keys. The sensitivity and time constant
are indicated by leds.
Change the sensitivity back to 20 mV.
The values of X and Y become noisy. This is

10. Press [Time Constant Down] to change the because the 2f component of the output (at 2 kHz)
time constant to 300 µs. is no longer attenuated completely by the low pass
filters.
Let's leave the time constant short and change the

Press [Time Constant Up] to change the time filter slope.
constant to 3 ms.
2-4
The Basic Lock-in
Parameters which have only a few values, such as

filter slope, have only a single key which cycles
11. Press the [Slope/Oct] key until 6 dB/oct is through all available options. Press the corre-
selected. sponding key until the desired option is indicated
by an led.
The X and Y outputs are somewhat noisy at this

short time constant and only 1 pole of low pass
filtering.
The outputs are less noisy with 2 poles of filtering.
Press [Slope/Oct] again to select 12 dB/oct. With 4 poles of low pass filtering, even this short
time constant attenuates the 2f component rea-
Press [Slope/Oct] twice to select 24 db/oct. sonably well and provides steady readings.
Let's leave the filtering short and the outputs noisy

for now.
Press [Slope/Oct] again to select 6 db/oct.
Show the internal reference frequency on the

Reference display.
12. Press [Freq]
At a reference frequency of 55 Hz and a 6 db/oct,
3 ms time constant, the output is totally dominated
Use the knob to adjust the frequency to by the 2f component at 100 Hz.
55.0 Hz.
This turns on synchronous filtering whenever the

detection frequency is below 200 Hz.
13. Press [Sync Filter]
Synchronous filtering effectively removes output
components at multiples of the detection frequen-
cy. At low frequencies, this filter is a very effective
way to remove 2f without using extremely long
time constants.
The outputs are now very quiet and steady, even

though the time constant is very short. The
response time of the synchronous filter is equal to
the period of the detection frequency (18 ms in this
case).
This concludes this measurement example. You

should have a feeling for the basic operation of the
front panel. Basic lock-in parameters have been
introduced and you should be able to perform
simple measurements.
2-5
The Basic Lock-in
2-6
X, Y, R and θ
X, Y, R and θ
This measurement is designed to use the internal oscillator and an external signal source to explore some of
the display types. You will need a synthesized function generator capable of providing a 100 mVrms sine
wave at 1.000 kHz (the DS335 from SRS will suffice), BNC cables and a terminator appropriate for the gener-
ator function output.
Specifically, you will display the lock-in outputs when measuring a signal close to, but not equal to, the inter-
nal reference frequency. This setup ensures changing outputs which are more illustrative than steady outputs.
The displays will be configured to show X, Y, R and θ.
the power on while holding down the [Setup] pressed, the lock-in returns to its standard set-
key. Wait until the power-on tests are tings. See the Standard Settings list in the
settings.

shows Y.
2. Turn on the function generator, set the fre- The input impedance of the lock-in is 10 MΩ. The
quency to 1.0000 kHz (exactly) and the ampli- generator may require a terminator. Many genera-
tude to 500 mVrms. tors have either a 50Ω or 600Ω output impedance.
Use the appropriate feedthrough or T termination if
Connect the function output (sine wave) from necessary. In general, not using a terminator
the synthesized function generator to the A means that the function output amplitude will not
input using a BNC cable and appropriate agree with the generator setting.
terminator.
The lock-in defaults to the internal oscillator refer-
ence set at 1.000 kHz. The reference mode is indi-
internal oscillator sets the detection frequency.
The internal oscillator is crystal synthesized so

that the actual reference frequency should be very
close to the actual generator frequency. The X and
Y displays should read values which change very
slowly. The lock-in and the generator are not
phase locked but they are at the same frequency
with some slowly changing phase.
3. Press [Freq] Show the internal oscillator frequency on the

Reference display.
Use the knob to change the frequency to By setting the lock-in reference 0.2 Hz away from
999.8 Hz. the signal frequency, the X and Y outputs are
0.2 Hz sine waves (frequency difference between
reference and signal). The X and Y output displays
2-7
X, Y, R and θ
should now oscillate at about 0.2 Hz (the accuracy

is determined by the crystals of the generator and
the lock-in).
4. Press [Channel 1 Display] to select R. The default Channel 1 display is X. Change the
display to show R. R is phase independent so it
shows a steady value (close to 0.500 V).
5. Press [Channel 2 Display] to select θ. The default Channel 2 display is Y. Change the
display to show θ. The phase between the refer-
ence and the signal changes by 360° approximate-
ly every 5 sec (0.2 Hz difference frequency).
The bar graph in this case is scaled to ±180°. The

bar graph should be a linear phase ramp at
0.2 Hz.
6. Press [Freq] Show the internal oscillator frequency.
Use the knob to adjust the frequency slowly to As the internal reference frequency gets closer to
try to stop the rotation of the phase. the signal frequency, the phase rotation gets
slower and slower. If the frequencies are
EXACTLY equal, then the phase is constant.
7. Use a BNC cable to connect the TTL SYNC By using the signal generator as the external refer-
output from the generator to the Reference ence, the lock-in will phase lock its internal oscilla-
Input of the lock-in. tor to the signal frequency and the phase will be a
constant.
Press [Source] to turn the INTERNAL led off. Select external reference mode. The lock-in will
phase lock to the signal at the Reference Input.
Press [Trig] to select POS EDGE. With a TTL reference signal, the slope needs to be
set to either rising or falling edge.
The phase is now constant. The actual phase

depends upon the phase difference between the
function output and the sync output from the
generator.
The external reference frequency (as measured by

the lock-in) is displayed on the Reference display.
The UNLOCK indicator should be OFF (success-
fully locked to the external reference).
The displays may be stored in the internal data

buffers at a programmable sampling rate. This
allows storage of 16000 points of both displays.
2-8
Outputs, Offsets and Expands
OUTPUTS, OFFSETS and EXPANDS

This measurement is designed to use the internal oscillator to explore some of the basic lock-in outputs. You
will need BNC cables and a digital voltmeter (DVM).
Specifically, you will measure the amplitude of the Sine Out and provide analog outputs proportional to the
measurement. The effect of offsets and expands on the displayed values and the analog outputs will be
explored.
settings.

shows Y.
2. Connect the Sine Out on the front panel to the The lock-in defaults to the internal oscillator refer-
A input using a BNC cable. ence set at 1.000 kHz. The reference mode is indi-
lock-in generates a synchronous sine output at the
internal reference frequency.
The input impedance of the lock-in is 10 MΩ. The

Sine Out has an output impedance of 50Ω. Since
the Sine Output amplitude is specified into a high
impedance load, the output impedance does not
affect the amplitude.
The sine amplitude is 1.000 Vrms and the

sensitivity is 1 V(rms). Since the phase shift of the
sine output is very close to zero, Channel 1 (X)
should read close to 1.000 V and Channel 2 (Y)
should read close to 0.000 V.
3. Connect the CH1 OUTPUT on the front panel The CH1 output defaults to X. The output voltage
to the DVM. Set the DVM to read DC Volts. is simply (X/Sensitivity - Offset)xExpandx10V. In
this case, X = 1.000 V, the sensitivity = 1 V, the
offset is zero percent and the expand is 1. The
output should thus be 10 V or 100% of full scale.
4. Press [Ampl] Display the sine output amplitude.
Use the knob to adjust the sine amplitude to Set the amplitude to 0.5 V. The Channel 1 display
0.5 V. should show X=0.5 V and the CH1 output voltage
should be 5 V on the DVM (1/2 of full scale).
2-9
5. Press [Channel 1 Auto Offset] X, Y and R may all be offset and expanded separ-
ately. Since Channel 1 is displaying X, the
OFFSET and [Expand] keys below the Channel 1
display set the X offset and expand. The display
determines which quantity (X or R) is offset and
expanded.
Auto Offset automatically adjusts the X offset (or Y

or R) such that X (or Y or R) becomes zero. In this
case, X is offset to zero. The offset should be
about 50%. Offsets are useful for making relative
measurements. In analog lock-ins, offsets were
generally used to remove DC output errors from
the lock-in itself. The SR830 has no DC output
errors and the offset is not required for most
measurements.
The offset affects both the displayed value of X

and any analog output proportional to X. The CH1
output voltage should be zero in this case.
The Offset indicator turns on at the bottom of the

Channel 1 display to indicate that the displayed
quantity is affected by an offset.
Press [Channel 1 Offset Modify] Show the Channel 1 (X) offset in the Reference
display.
Use the knob to adjust the X offset to 40.0% Change the offset to 40% of full scale. The output
offsets are a percentage of full scale. The percent-
age does not change with the sensitivity. The dis-
played value of X should be 0.100 V (0.5 V - 40%
of full scale). The CH1 output voltage is
(X/Sensitivity - Offset)xExpandx10V.
CH1 Out = (0.5/1.0 - 0.4)x1x10V = 1 V
Press [Channel 1 Expand] to select x10. With an expand of 10, the display has one more
digit of resolution (100.00 mV full scale).
The Expand indicator turns on at the bottom of the

Channel 1 display to indicate that the displayed
quantity is affected by a non-unity expand.
The CH1 output is

(X/Sensitivity - Offset)xExpandx10V. In this case,
the output voltage is
CH1 Out = (0.5/1.0 - 0.4)x10x10V = 10V
The expand allows the output gain to be increased

by up to 100. The output voltage is limited to
10.9 V and any output which tries to be greater will
2-10
turn on the OVLD indicator in the Channel 1

display.
With offset and expand, the output voltage gain

and offset can be programmed to provide control
of feedback signals with the proper bias and gain
for a variety of situations.
Offsets add and subtract from the displayed

values while expand increases the resolution of
the display.
6. Connect the DVM to the X output on the rear The X and Y outputs on the rear panel always pro-
panel. vide voltages proportional to X and Y (with offset
and expand). The X output voltage should be
10 V, just like the CH1 output.
7. Connect the DVM to the CH1 OUTPUT on the The front panel outputs can be configured to
front panel again. output different quantities while the rear panel out-
puts always output X and Y.
NOTE:
Outputs proportional to X and Y (rear panel, CH1
or CH2) have 100 kHz of bandwidth. The CH1 and
CH2 outputs, when configured to be proportional
to the displays (even if the display is X or Y) are
updated at 512 Hz and have a 200 Hz bandwidth.
It is important to keep this in mind if you use very
short time constants.
Press [Channel 1 Output] to select Display. CH1 OUTPUT can be proportional to X or the dis-
play. Choose Display. The display is X so the CH1
output should remain 10.0 V (but its bandwidth is
only 200 Hz instead of 100 kHz).
Press [Channel 1 Display] to select R. Let's change CH1 to output R.
The X and Y offset and expand functions are

output functions, they do NOT affect the calcula-
tion of R or θ. Thus, Channel 1 (R) should be 0.5V
and the CH1 output voltage should be 5V (1/2 of
full scale).
The Channel 1 offset and expand keys now set

the R offset and expand. The X offset and expand
are still set at 40% and x10 as reflected at the rear
panel X output.
See the DC Outputs and Scaling discussion in the

Lock-In Basics section for more detailed informa-
tion on output scaling.
2-11
2-12
Storing and Recalling Setups
STORING and RECALLING SETUPS

The SR830 can store 9 complete instrument setups in non-volatile memory.
1. Turn the lock-in on while holding down the When the power is turned on with the [Setup] key
[Setup] key. Wait until the power-on tests are pressed, the lock-in returns to its standard set-
completed. Disconnect any cables from the tings. See the Standard Settings list in the
lock-in. Operation section for a complete listing of the
settings.
Change the lock-in setup so that we have a non-

default setup to save.
2. Press [Sensitivity Down] to select 100 mV. Change the sensitivity to 100 mV.
Press [Time Constant Up] to select 1 S. Change the time constant to 1 second.
3. Press [Save] The Reference display shows the setup number

(1-9).
Use the knob to select setup number 3. The knob selects the setup number.
Press [Save] again. Press [Save] again to complete the save opera-
tion. Any other key aborts the save.
The current setup is now saved as setup number

3.
4. Turn the lock-in off and on while holding down Change the lock-in setup back to the default
the [Setup] key. Wait until the power-on tests setup. Now let's recall the lock-in setup that we
are complete. just saved.
Check that the sensitivity and time constant are 1V

and 100 ms (default values).
5. Press [Recall] The Reference display shows the setup number.
Use the knob to select setup number 3. The knob selects the setup number.
Press [Recall] again. Press [Recall] again to complete the recall opera-
tion. Any other key aborts the recall.
The sensitivity and time constant should be the

same as those in effect when the setup was
saved.
2-13
Storing and Recalling Setups
2-14
Aux Outputs and Inputs
AUX OUTPUTS and INPUTS

This measurement is designed to illustrate the use of the Aux Outputs and Inputs on the rear panel. You will
need BNC cables and a digital voltmeter (DVM).
Specifically, you will set the Aux Output voltages and measure them with the DVM. These outputs will then be
connected to the Aux Inputs to simulate external DC voltages which the lock-in can measure.
settings.
2. Connect Aux Out 1 on the rear panel to the The 4 Aux Outputs can provide programmable
DVM. Set the DVM to read DC volts. voltages between -10.5 and +10.5 volts. The out-
puts can be set from the front panel or via the
computer interface.
3. Press [Aux Out] until the Reference display Show the level of Aux Out 1 on the Reference
shows the level of Aux Out 1( as indicated by display.
the AxOut1 led below the display).
Use the knob to adjust the level to 10.00 V. Change the output to 10V. The DVM should dis-
play 10.0 V.
Use the knob to adjust the level to -5.00 V. Change the output to -5V. The DVM should dis-
play -5.0 V.
The 4 outputs are useful for controlling other

parameters in an experiment, such as pressure,
temperature, wavelength, etc.
4. Press [Channel 1 Display] to select AUX IN 1. Change the Channel 1 display to measure Aux
Input 1.
The Aux Inputs can read 4 analog voltages. These

inputs are useful for monitoring and measuring
other parameters in an experiment, such as pres-
sure, temperature, position, etc.
We'll use Aux Out 1 to provide an analog voltage

to measure.
5. Disconnect the DVM from Aux Out 1. Connect Channel 1 should now display -5 V (Aux In 1).
AuxOut 1 to Aux In 1 on the rear panel.
2-15
Aux Outputs and Inputs
6. Press [Channel 2 Display] to select AUX IN 3. Change the Channel 2 display to measure Aux
Input 3.
7. Connect Aux Out 1 to Aux In 3 on the rear Channel 2 should now display -5 V (Aux In 3).
panel.
The Channel 1 and 2 displays may be ratio'ed to
the Aux Input voltages. See the Basics section for
more about output scaling.
The displays may be stored in the internal data

buffers at a programmable sampling rate. This
allows storage of not only the lock-in outputs, X,Y,
R or θ, but also the values of the Aux Inputs. See
the Programming section for more details.
2-16
SR830 BASICS
WHAT IS A LOCK-IN AMPLIFIER?

Lock-in amplifiers are used to detect and measure experiment at the reference frequency. In the dia-
very small AC signals - all the way down to a few gram below, the reference signal is a square wave
nanovolts! Accurate measurements may be made at frequency ωr. This might be the sync output
even when the small signal is obscured by noise from a function generator. If the sine output from
sources many thousands of times larger. the function generator is used to excite the experi-
ment, the response might be the signal waveform
Lock-in amplifiers use a technique known as shown below. The signal is Vsig sin(ωrt + θsig )
phase-sensitive detection to single out the compo- where V sig is the signal amplitude.
nent of the signal at a specific reference frequency
AND phase. Noise signals at frequencies other The SR830 generates its own sine wave, shown
than the reference frequency are rejected and do as the lock-in reference below. The lock-in refer-
not affect the measurement. ence is VLsin(ωLt + θref).
Why use a lock-in? Reference

Let's consider an example. Suppose the signal is a
10 nV sine wave at 10 kHz. Clearly some amplifi-
cation is required. A good low noise amplifier will θ sig
have about 5 nV/√Hz of input noise. If the amplifier
bandwidth is 100 kHz and the gain is 1000, then Signal
we can expect our output to be 10 µV of signal
(10 nV x 1000) and 1.6 mV of broadband noise
(5 nV/√Hz x √100 kHz x 1000). We won't have
much luck measuring the output signal unless we
single out the frequency of interest.
θ ref
If we follow the amplifier with a band pass filter Lock-in Reference
with a Q=100 (a VERY good filter) centered at
10 kHz, any signal in a 100 Hz bandwidth will be The SR830 amplifies the signal and then multiplies
detected (10 kHz/Q). The noise in the filter pass it by the lock-in reference using a phase-sensitive
band will be 50 µV (5 nV/√Hz x √100 Hz x 1000) detector or multiplier. The output of the PSD is
and the signal will still be 10 µV. The output noise simply the product of two sine waves.
is much greater than the signal and an accurate
measurement can not be made. Further gain will V psd = V sig VLsin(ωrt + θsig )sin(ωLt + θref)
not help the signal to noise problem.
= 1/2 Vsig V Lcos([ω r - ωL]t + θsig - θref) -
Now try following the amplifier with a phase- 1/2 Vsig V Lcos([ω r + ωL]t + θsig + θref)
sensitive detector (PSD). The PSD can detect the
signal at 10 kHz with a bandwidth as narrow as The PSD output is two AC signals, one at the dif-
0.01 Hz! In this case, the noise in the detection ference frequency (ω r - ωL) and the other at the
bandwidth will be only 0.5 µV (5 nV/√Hz x √.01 Hz sum frequency (ω r + ωL).
x 1000) while the signal is still 10 µV. The signal to
noise ratio is now 20 and an accurate measure- If the PSD output is passed through a low pass
ment of the signal is possible. filter, the AC signals are removed. What will be
left? In the general case, nothing. However, if ω r
What is phase-sensitive detection? equals ω L, the difference frequency component
Lock-in measurements require a frequency refer- will be a DC signal. In this case, the filtered PSD
ence. Typically an experiment is excited at a fixed output will be
frequency (from an oscillator or function generator)
and the lock-in detects the response from the V psd = 1/2 Vsig V Lcos(θsig - θref)
3-1
SR830 Basics
This is a very nice signal - it is a DC signal propor- sync) which is always phase-locked to the refer-
tional to the signal amplitude. ence oscillator.
Narrow band detection Magnitude and phase

Now suppose the input is made up of signal plus Remember that the PSD output is proportional
noise. The PSD and low pass filter only detect sig- to Vsig cosθ where θ = (θsig - θref). θ is the phase
nals whose frequencies are very close to the lock- difference between the signal and the lock-in refer-
in reference frequency. Noise signals at frequen- ence oscillator. By adjusting θref we can make θ
cies far from the reference are attenuated at the equal to zero, in which case we can measure Vsig
PSD output by the low pass filter (neither ωnoise - (cosθ=1). Conversely, if θ is 90°, there will be no
ωref nor ωnoise +ωref are close to DC). Noise at fre- output at all. A lock-in with a single PSD is called a
quencies very close to the reference frequency will single-phase lock-in and its output is V sig cosθ.
result in very low frequency AC outputs from the
PSD (|ωnoise -ωref| is small). Their attenuation This phase dependency can be eliminated by
depends upon the low pass filter bandwidth and adding a second PSD. If the second PSD multi-
roll-off. A narrower bandwidth will remove noise plies the signal with the reference oscillator shifted
sources very close to the reference frequency, a by 90°, i.e. VLsin(ωLt + θref + 90°), its low pass fil-
wider bandwidth allows these signals to pass. The tered output will be
low pass filter bandwidth determines the band-
width of detection. Only the signal at the reference V psd2 = 1/2 Vsig V Lsin(θsig - θref)
frequency will result in a true DC output and be
unaffected by the low pass filter. This is the signal V psd2 ~ V sig sinθ
we want to measure.
Now we have two outputs, one proportional to
Where does the cosθ and the other proportional to sinθ. If we call
lock-in reference come from? the first output X and the second Y,
We need to make the lock-in reference the same
as the signal frequency, i.e. ωr = ωL. Not only do X = Vsig cosθ Y = Vsig sinθ
the frequencies have to be the same, the phase
between the signals can not change with time, oth- these two quantities represent the signal as a
erwise cos(θsig - θref) will change and V psd will not vector relative to the lock-in reference oscillator. X
be a DC signal. In other words, the lock-in refer- is called the 'in-phase' component and Y the
ence needs to be phase-locked to the signal 'quadrature' component. This is because when
reference. θ=0, X measures the signal while Y is zero.
Lock-in amplifiers use a phase-locked-loop (PLL) By computing the magnitude (R) of the signal
to generate the reference signal. An external refer- vector, the phase dependency is removed.
ence signal (in this case, the reference square
wave) is provided to the lock-in. The PLL in the R = (X 2 + Y2)1/2 = Vsig
lock-in locks the internal reference oscillator to this
external reference, resulting in a reference sine R measures the signal amplitude and does not
wave at ωr with a fixed phase shift of θref. Since depend upon the phase between the signal and
the PLL actively tracks the external reference, lock-in reference.
changes in the external reference frequency do
not affect the measurement. A dual-phase lock-in, such as the SR830, has two
PSD's, with reference oscillators 90° apart, and
All lock-in measurements can measure X, Y and R directly. In addition, the
require a reference signal. phase θ between the signal and lock-in reference,
In this case, the reference is provided by the exci- can be measured according to
tation source (the function generator). This is
called an external reference source. In many situa- θ = tan -1 (Y/X)
tions, the SR830's internal oscillator may be used
instead. The internal oscillator is just like a func-
tion generator (with variable sine output and a TTL
3-2
SR830 Basics
WHAT DOES A LOCK-IN MEASURE?

So what exactly does the SR830 measure? frequencies is removed by the low pass filter fol-
Fourier's theorem basically states that any input lowing the multiplier. This "bandwidth narrowing" is
signal can be represented as the sum of many, the primary advantage that a lock-in amplifier pro-
many sine waves of differing amplitudes, frequen- vides. Only inputs at frequencies at the reference
cies and phases. This is generally considered as frequency result in an output.
representing the signal in the "frequency domain".
Normal oscilloscopes display the signal in the RMS or Peak?
"time domain". Except in the case of clean sine Lock-in amplifiers as a general rule display the
waves, the time domain representation does not input signal in Volts RMS. When the SR830 dis-
convey very much information about the various plays a magnitude of 1V (rms), the component of
frequencies which make up the signal. the input signal at the reference frequency is a
sine wave with an amplitude of 1 Vrms or
What does the SR830 measure? 2.8 V pk-pk.
The SR830 multiplies the signal by a pure sine
wave at the reference frequency. All components Thus, in the previous example with a 2 V pk-pk
of the input signal are multiplied by the reference square wave input, the SR830 would detect the
simultaneously. Mathematically speaking, sine first sine component, 1.273sin(ωt). The measured
waves of differing frequencies are orthogonal, i.e. and displayed magnitude would be 0.90 V (rms)
the average of the product of two sine waves is (1/√2 x 1.273).
zero unless the frequencies are EXACTLY the
same. In the SR830, the product of this multiplica- Degrees or Radians?
tion yields a DC output signal proportional to the In this discussion, frequencies have been referred
component of the signal whose frequency is exact- to as f (Hz) and ω (2πf radians/sec). This is
ly locked to the reference frequency. The low pass because people measure frequencies in cycles
filter which follows the multiplier provides the aver- per second and math works best in radians. For
aging which removes the products of the reference purposes of measurement, frequencies as meas-
with components at all other frequencies. ured in a lock-in amplifier are in Hz. The equations
used to explain the actual calculations are some-
The SR830, because it multiplies the signal with a times written using ω to simplify the expressions.
pure sine wave, measures the single Fourier (sine)
component of the signal at the reference frequen- Phase is always reported in degrees. Once again,
cy. Let's take a look at an example. Suppose the this is more by custom than by choice. Equations
input signal is a simple square wave at frequency written as sin(ωt + θ) are written as if θ is in
f. The square wave is actually composed of many radians mostly for simplicity. Lock-in amplifiers
sine waves at multiples of f with carefully related always manipulate and measure phase in
amplitudes and phases. A 2V pk-pk square wave degrees.
can be expressed as
S(t) = 1.273sin(ωt) + 0.4244sin(3ωt) +

0.2546sin(5ωt) + ...
where ω = 2πf. The SR830, locked to f will single

out the first component. The measured signal will
be 1.273sin(ωt), not the 2V pk-pk that you'd meas-
ure on a scope.
In the general case, the input consists of signal

plus noise. Noise is represented as varying signals
at all frequencies. The ideal lock-in only responds
to noise at the reference frequency. Noise at other
3-3
SR830 Basics
3-4
SR830 Basics
THE FUNCTIONAL SR830

The functional block diagram of the SR830 DSP
Lock-In Amplifier is shown below. The functions in
the gray area are handled by the digital signal pro-
cessor (DSP). We'll discuss the DSP aspects of
the SR830 as they come up in each functional
block description.
Low Noise 50/60 Hz 100/120 Hz

Differential Notch Notch
Amp Filter Filter Gain
A
Voltage
B
Current I
DC Gain
Offset
Expand
90° Low
Phase Pass Y Out
Shift Filter
Phase
Sensitive
Detector R
R and
Ø Calc Ø
Reference In Low
Phase
Sine or TTL PLL Pass X Out
Shifter
Filter
Discriminator Phase Internal Phase DC Gain
Locked Oscillator Sensitive Offset
Loop Detector Expand
Sine Out
TTL Out
SR830 FUNCTIONAL BLOCK DIAGRAM Discriminator
3-5
SR830 Basics
3-6
SR830 Basics
REFERENCE CHANNEL
A lock-in amplifier requires a reference oscillator When an external reference is used, this internal
phase-locked to the signal frequency. In general, oscillator sine wave is phase-locked to the refer-
this is accomplished by phase-locking an internal ence. The rising zero crossing is locked to the
oscillator to an externally provided reference detected reference zero crossing or edge. In this
signal. This reference signal usually comes from mode, the SINE OUT provides a sine wave phase-
the signal source which is providing the excitation locked to the external reference. At low frequen-
to the experiment. cies (below 10 Hz), the phase locking is accom-
plished digitally by the DSP. At higher frequencies,
Reference Input a discrete phase comparator is used.
The SR830 reference input can trigger on an
analog signal (like a sine wave) or a TTL logic The internal oscillator may be used without an
signal. The first case is called External Sine. The external reference. In the Internal Reference
input is AC coupled (above 1 Hz) and the input mode, the SINE OUT provides the excitation for
impedance is 1 MΩ. A sine wave input greater the experiment. The phase-locked-loop is not used
than 200 mV pk will trigger the input discriminator. in this mode since the lock-in reference is provid-
Positive zero crossings are detected and consid- ing the excitation signal.
ered to be the zero for the reference phase shift.
The TTL OUT on the rear panel provides a TTL
TTL reference signals can be used at all frequen- sync output. The internal oscillator's rising zero
cies up to 102 kHz. For frequencies below 1 Hz, crossings are detected and translated to TTL
a TTL reference signal is required. Many func- levels. This output is a square wave.
tion generators provide a TTL SYNC output which
can be used as the reference. This is convenient Reference Oscillators and Phase
since the generator's sine output might be smaller The internal oscillator sine wave is not the refer-
than 200 mV or be varied in amplitude. The SYNC ence signal to the phase sensitive detectors. The
signal will provide a stable reference regardless of DSP computes a second sine wave, phase shifted
the sine amplitude. by θref from the internal oscillator (and thus from
an external reference), as the reference input to
When using a TTL reference, the reference input the X phase sensitive detector. This waveform is
trigger can be set to Pos Edge (detect rising sin(ωrt + θref). The reference phase shift is adjust-
edges) or Neg Edge (detect falling edges). In each able in .01° increments.
case, the internal oscillator is locked (at zero
phase) to the detected edge. The input to the Y PSD is a third sine wave, com-
puted by the DSP, shifted by 90° from the second
Internal Oscillator sine wave. This waveform is sin(ωrt + θref + 90°).
The internal oscillator in the SR830 is basically a
102 kHz function generator with sine and TTL Both reference sine waves are calculated to 20
sync outputs. The oscillator can be phase-locked bits of accuracy and a new point is calculated
to the external reference. every 4 µs (256 kHz). The phase shifts (θref and
the 90° shift) are also exact numbers and accurate
The oscillator generates a digitally synthesized to better than .001°. Neither waveform is actually
sine wave. The digital signal processor, or DSP, output in analog form since the phase sensitive
sends computed sine values to a 16 bit digital-to- detectors are actually multiply instructions inside
analog converter every 4 µs (256 kHz). An anti- the DSP.
aliasing filter converts this sampled signal into a
low distortion sine wave. The internal oscillator Phase Jitter
sine wave is output at the SINE OUT BNC on the When an external reference is used, the phase-
front panel. The amplitude of this output may be locked loop adds a little phase jitter. The internal
set from 4 mV to 5 V. oscillator is supposed to be locked with zero
phase shift relative the external reference. Phase
3-7
SR830 Basics
jitter means that the average phase shift is zero crystal oscillator and is very, very small).
but the instantaneous phase shift has a few milli-
degrees of noise. This shows up at the output as Harmonic Detection
noise in phase or quadrature measurements. It is possible to compute the two PSD reference
sine waves at a multiple of the internal oscillator
Phase noise can also cause noise to appear at the frequency. In this case, the lock-in detects signals
X and Y outputs. This is because a reference at Nxfref which are synchronous with the refer-
oscillator with a lot of phase noise is the same as ence. The SINE OUT frequency is not affected.
a reference whose frequency spectrum is spread The SR830 can detect at any harmonic up to
out. That is, the reference is not a single frequen- N=19999 as long as Nxfref does not exceed
cy, but a distribution of frequencies about the true 102 kHz.
reference frequency. These spurious frequencies
are attenuated quite a bit but still cause problems.
The spurious reference frequencies result in sig-
nals close to the reference being detected. Noise
at nearby frequencies now appears near DC and
affects the lock-in output.
Phase noise in the SR830 is very low and general-

ly causes no problems. In applications requiring no
phase jitter, the internal reference mode should be
used. Since there is no PLL, the internal oscillator
and the reference sine waves are directly linked
and there is no jitter in the measured phase.
(Actually, the phase jitter is the phase noise of a
3-8
SR830 Basics
THE PHASE SENSITIVE DETECTORS (PSD's)

The SR830 multiplies the signal with the reference present, 1000 times or 60 dB greater than the full
sine waves digitally. The amplified signal is con- scale signal, the analog PSD measures the signal
verted to digital form using a 16 bit A/D converter with an error. The error is caused by non-linearity
sampling at 256 kHz. The A/D converter is preced- in the multiplication (the error at the output
ed by a 102 kHz anti-aliasing filter to prevent depends upon the amplitude of the input). This
higher frequency inputs from aliasing below error can be quite large (10% of full scale) and
102 kHz. The signal amplifier and filters will be dis- depends upon the noise amplitude, frequency, and
cussed later. waveform. Since noise generally varies quite a bit
in these parameters, the PSD error causes quite a
This input data stream is multiplied, a point at a bit of output uncertainty.
time, with the computed reference sine waves
described previously. Every 4 µs, the input signal In the digital lock-in, the dynamic reserve is limited
is sampled and the result is multiplied by the two by the quality of the A/D conversion. Once the
reference sine waves (90° apart). input signal is digitized, no further errors are intro-
duced. Certainly the accuracy of the multiplication
Digital PSD vs Analog PSD does not depend on the size of the numbers. The
The phase sensitive detectors (PSD's) in the A/D converter used in the SR830 is extremely
SR830 act as linear multipliers, that is, they multi- linear, meaning that the presence of large noise
ply the signal with a reference sine wave. Analog signals does not impair its ability to correctly digi-
PSD's (both square wave and linear) have many tize a small signal. In fact, the dynamic reserve of
problems associated with them. The main prob- the SR830 can exceed 100 dB without any prob-
lems are harmonic rejection, output offsets, limited lems. We'll talk more about dynamic reserve a little
dynamic reserve and gain error. later.
The digital PSD multiplies the digitized signal with An analog linear PSD multiplies the signal by an
a digitally computed reference sine wave. analog reference sine wave. Any amplitude varia-
Because the reference sine waves are computed tion in the reference amplitude shows up directly
to 20 bits of accuracy, they have very low harmon- as a variation in the overall gain. Analog sine wave
ic content. In fact, the harmonics are at the generators are susceptible to amplitude drift, espe-
-120 dB level! This means that the signal is multi- cially as a function of temperature. The digital ref-
plied by a single reference sine wave (instead of a erence sine wave has a precise amplitude and
reference and its many harmonics) and only the never changes. This eliminates a major source of
signal at this single reference frequency is detect- gain error in a linear analog lock-in.
ed. The SR830 is completely insensitive to signals
at harmonics of the reference. In contrast, a The overall performance of a lock-in amplifier is
square wave multiplying lock-in will detect at all of largely determined by the performance of its
the odd harmonics of the reference (a square phase sensitive detectors. In virtually all respects,
wave contains many large odd harmonics). the digital PSD outperforms its analog
counterparts.
Output offset is a problem because the signal of
interest is a DC output from the PSD and an We've discussed how the digital signal processor
output offset contributes to error and zero drift. in the SR830 computes the internal oscillator and
The offset problems of analog PSD's are eliminat- two reference sine waves and handles both phase
ed using the digital multiplier. There are no errone- sensitive detectors. In the next section, we'll see
ous DC output offsets from the digital the same DSP perform the low pass filtering and
multiplication of the signal and reference. In fact, DC amplification required at the output of the
the actual multiplication is totally free from errors. PSD's. Here again, the digital technique eliminates
many of the problems associated with analog lock-
The dynamic reserve of an analog PSD is limited in amplifiers.
to about 60 dB. When there is a large noise signal
3-9
SR830 Basics
3-10
SR830 Basics
TIME CONSTANTS and DC GAIN

Remember, the output of the PSD contains many stages of filtering with a maximum roll off of
signals. Most of the output signals have frequen- 12 dB/oct. This limitation is usually due to space
cies which are either the sum or difference and expense. Each filter needs to have many dif-
between an input signal frequency and the refer- ferent time constant settings. The different settings
ence frequency. Only the component of the input require different components and switches to
signal whose frequency is exactly equal to the ref- select them, all of which is costly and space
erence frequency will result in a DC output. consuming.
The low pass filter at the PSD output removes all The digital signal processor in the SR830 handles
of the unwanted AC signals, both the 2F (sum of all of the low pass filtering. Each PSD can be fol-
the signal and the reference) and the noise com- lowed by up to four filter stages for up to 24 dB/oct
ponents. This filter is what makes the lock-in such of roll off. Since the filters are digital, the SR830 is
a narrow band detector. not limited to just two stages of filtering.
Time Constants Why is the increased roll off desirable? Consider

Lock-in amplifiers have traditionally set the low an example where the reference is at 1 kHz and a
pass filter bandwidth by setting the time constant. large noise signal is at 1.05 kHz. The PSD noise
The time constant is simply 1/2πf where f is the outputs are at 50 Hz (difference) and 2.05 kHz
-3 dB frequency of the filter. The low pass filters (sum). Clearly the 50 Hz component is the more
are simple 6 dB/oct roll off, RC type filters. A 1 difficult to low pass filter. If the noise signal is
second time constant referred to a filter whose 80 dB above the full scale signal and we would
-3 dB point occurred at 0.16 Hz and rolled off at like to measure the signal to 1% (-40 dB), then the
6 dB/oct beyond 0.16 Hz. Typically, there are two 50 Hz component needs to be reduced by 120 dB.
successive filters so that the overall filter can roll To do this in two stages would require a time con-
off at either 6 dB or 12 dB per octave. The time stant of at least 3 seconds. To accomplish the
constant referred to the -3 dB point of each filter same attenuation in four stages only requires
alone (not the combined filter). 100 ms of time constant. In the second case, the
output will respond 30 times faster and the experi-
The notion of time constant arises from the fact ment will take less time.
that the actual output is supposed to be a DC
signal. In fact, when there is noise at the input, Synchronous Filters
there is noise on the output. By increasing the time Another advantage of digital filtering is the ability
constant, the output becomes more steady and to do synchronous filtering. Even if the input signal
easier to measure reliably. The trade off comes has no noise, the PSD output always contains a
when real changes in the input signal take many component at 2F (sum frequency of signal and ref-
time constants to be reflected at the output. This is erence) whose amplitude equals or exceeds the
because a single RC filter requires about 5 time desired DC output depending upon the phase. At
constants to settle to its final value. The time low frequencies, the time constant required to
constant reflects how slowly the output responds, attenuate the 2F component can be quite long. For
and thus the degree of output smoothing. example, at 1 Hz, the 2F output is at 2 Hz and to
attenuate the 2 Hz by 60 dB in two stages requires
The time constant also determines the equivalent a time constant of 3 seconds.
noise bandwidth (ENBW) for noise measurements.
The ENBW is NOT the filter -3 dB pole, it is the A synchronous filter, on the other hand, operates
effective bandwidth for Gaussian noise. More totally differently. The PSD output is averaged
about this later. over a complete cycle of the reference frequency.
The result is that all components at multiples of
Digital Filters vs Analog Filters the reference (2F included) are notched out com-
The SR830 improves on analog filters in many pletely. In the case of a clean signal, almost no
ways. First, analog lock-ins provide at most, two additional filtering would be required. This is
3-11
SR830 Basics
increasingly useful the lower the reference fre- the dynamic reserve is increased to 80dB, then
quency. Imagine what the time constant would this offset needs to be 10 times smaller still. This
need to be at 0.001 Hz! is one of the reasons why analog lock-ins do not
perform well at very high dynamic reserve.
In the SR830, synchronous filters are available at
detection frequencies below 200 Hz. At higher fre- The digital lock-in does not have an analog DC
quencies, the filters are not required (2F is easily amplifier. The output gain is yet another function
removed without using long time constants). handled by the digital signal processor. We
Below 200 Hz, the synchronous filter follows either already know that the digital PSD has no DC
one or two stages of normal filters. The output of output offset. Likewise, the digital DC amplifier has
the synchronous filter is followed by two more no input offset. Amplification is simply taking input
stages of normal filters. This combination of filters numbers and multiplying by the gain. This allows
notches all multiples of the reference frequency the SR830 to operate with 100 dB of dynamic
and provides overall noise attenuation as well. reserve without any output offset or zero drift.
Long Time Constants What about resolution?

Time constants above 100 seconds are difficult to Just like the analog lock-in where the noise can
accomplish using analog filters. This is simply not exceed the input range of the PSD, in the digi-
because the capacitor required for the RC filter is tal lock-in, the noise can not exceed the input
prohibitively large (in value and in size!). Why range of the A/D converter. With a 16 bit A/D con-
would you use such a long time constant? verter, a dynamic reserve of 60 dB means that
Sometimes you have no choice. If the reference is while the noise has a range of the full 16 bits, the
well below 1 Hz and there is a lot of low frequency full scale signal only uses 6 bits. With a dynamic
noise, then the PSD output contains many very reserve of 80 dB, the full scale signal uses only
low frequency components. The synchronous filter 2.5 bits. And with 100 dB dynamic reserve, the
only notches multiples of the reference frequency, signal is below a single bit! Clearly multiplying
the noise is filtered by the normal filters. these numbers by a large gain is not going to
result in a sensible output. Where does the output
The SR830 can provide time constants as long as resolution come from?
30000 seconds at reference frequencies below
200 Hz. Obviously you don't use long time con- The answer is filtering. The low pass filters effec-
stants unless absolutely necessary, but they're tively combine many data samples together. For
available. example, at a 1 second time constant, the output
is the result of averaging data over the previous 4
DC Output Gain or 5 seconds. At a sample rate of 256 kHz, this
How big is the DC output from the PSD? It means each output point is the exponential aver-
depends on the dynamic reserve. With 60 dB of age of over a million data points. (A new output
dynamic reserve, a noise signal can be 1000 times point is computed every 4 µs and is a moving
(60 dB) greater than a full scale signal. At the exponential average). What happens when you
PSD, the noise can not exceed the PSD's input average a million points? To first order, the result-
range. In an analog lock-in, the PSD input range ing average has more resolution than the incoming
might be 5V. With 60 dB of dynamic reserve, the data points by a factor of million . This represents
signal will be only 5 mV at the PSD input. The a gain of 20 bits in resolution over the raw data. A
PSD typically has no gain so the DC output from 1 bit input data stream is converted to 20 bits of
the PSD will only be a few millivolts! Even if the output resolution.
PSD had no DC output errors, amplifying this milli-
volt signal up to 10 V is error prone. The DC The compromise here is that with high dynamic
output gain needs to be about the same as the reserve (large DC gains), some filtering is
dynamic reserve (1000 in this case) to provide a required. The shortest time constants are not
10 V output for a full scale input signal. An offset available when the dynamic reserve is very high.
as small as 1 mV will appear as 1 V at the output! This is not really a limitation since presumably
In fact, the PSD output offset plus the input offset there is noise which is requiring the high dynamic
of the DC amplifier needs to be on the order of reserve and thus substantial output filtering will
10 µV in order to not affect the measurement. If also be required.
3-12
SR830 Basics
DC OUTPUTS and SCALING

The SR830 has X and Y outputs on the rear panel defined as X, Y or R, the output scale is also 10 V
and Channel 1 and 2 (CH1 and CH2) outputs on full scale.
the front panel.
Lock-in amplifiers are designed to measure the
X and Y Rear Panel Outputs RMS value of the AC input signal. All sensitivities
The X and Y rear panel outputs are the outputs and X, Y and R outputs and displays are RMS
from the two phase sensitive detectors with low values.
pass filtering, offset and expand. These outputs
are the traditional outputs of an analog lock-in. Phase is a quantity which ranges from -180° to
The X and Y outputs have an output bandwidth of +180° regardless of the sensitivity. When CH2 out-
100 kHz. puts a voltage proportional to θ, the output scale is
18°/Volt or 180°=10V.
CH1 and CH2 Front Panel Outputs
The two front panel outputs can be configured to X, Y and R Output Offset and Expand
output voltages proportional to the CH1 and CH2 The SR830 has the ability to offset the X, Y and R
displays or X and Y. outputs. This is useful when measuring deviations
in the signal around some nominal value. The
If the outputs are set to X or Y, these outputs offset can be set so that the output is offset to
duplicate the rear panel outputs. zero. Changes in the output can then be read
directly from the display or output voltages. The
If they are set to Display, the output is updated at offset is specified as a percentage of full scale and
512 Hz. The CH1 display can be defined as X, R, the percentage does not change when the sensi-
X Noise, Aux Input 1 or 2, or any of these quanti- tivity is changed. Offsets up to ±105% can be
ties divided by Aux Input 1 or 2. The CH2 display programmed.
can be defined as Y, θ, Y Noise, Aux Input 3 or 4,
or any of these quantities divided by Aux Input 3 or The X, Y and R outputs may also be expanded.
4. If a display is defined as simply X or Y, this dis- This simply takes the output (minus its offset) and
play, when output through the CH1 or CH2 output multiplies by an expansion factor. Thus, a signal
BNC, will only update at 512 Hz. It is better in this which is only 10% of full scale can be expanded to
case to set output to X or Y directly, rather than provide 10 V of output rather than only 1 V. The
the display. normal use for expand is to expand the measure-
ment resolution around some value which is not
X, Y, R and θ Output scales zero. For example, suppose a signal has a nomi-
The sensitivity of the lock-in is the rms amplitude nal value of 0.9 mV and we want to measure small
of an input sine (at the reference frequency) which deviations, say 10 µV or so, in the signal. The sen-
results in a full scale DC output. Traditionally, full sitivity of the lock-in needs to be 1 mV to accom-
scale means 10 VDC at the X, Y or R BNC output. modate the nominal signal. If the offset is set to
The overall gain (input to output) of the amplifier is 90% of full scale, then the nominal 0.9 mV signal
then 10 V/sensitivity. This gain is distributed will result in a zero output. The 10 µV deviations in
between AC gain before the PSD and DC gain fol- the signal only provide 100 mV of DC output. If the
lowing the PSD. Changing the dynamic reserve at output is expanded by 10, these small deviations
a given sensitivity changes the gain distribution are magnified by 10 and provide outputs of 1 VDC.
while keeping the overall gain constant.
The SR830 can expand the output by 10 or 100
The SR830 considers 10 V to be full scale for any provided the expanded output does not exceed full
output proportional to simply X, Y or R. This is the scale. In the above example, the 10 µV deviations
output scale for the X and Y rear panel outputs as can be expanded by 100 times before they exceed
well as the CH1 and CH2 outputs when configured full scale (at 1 mV sensitivity).
to output X or Y. When the CH1 or CH2 outputs
are proportional to a display which is simply
3-13
SR830 Basics
The analog output with offset and expand is where offset is a fraction of 1 (50%-0.5), expand is
1, 10 or 100, and the display can not exceed
Output = (signal/sensitivity - offset) x Expand x10V 100%.
where offset is a fraction of 1 (50%=0.5), expand For example, if the sensitivity is 1V and CH1 dis-
is 1, 10 or 100, and the output can not exceed 10 play is showing X/Aux 1. If X= 500 mV and Aux 1=
V. In the above example, 2.34 V, then the display value is
(0.5/1.0)x100/2.34 or 21.37%. This value is affect-
Output = (0.91mV/1mV - 0.9) x 10 x 10V = 1V ed by the sensitivity, offset and X expand.
for a signal which is 10 µV greater than the 0.9 mV In the case of θ, the full scale sensitivity is always
nominal. (Offset = 0.9 and expand =10). 180°.
The X and Y offset and expand functions in the The Ratio indicator below the display is on when-
SR830 are output functions, they do NOT affect ever a display is showing a ratio quantity.
the calculation of R or θ. R has its own output
offset and expand. Display output scaling
What about CH1 or CH2 outputs proportional to
CH1 and CH2 Displays ratio displays? The output voltage will simply be
The CH1 display can show X, R, X Noise, Aux the displayed percentage times 10V full scale.
Input 1 or 2, or any of these quantities divided by
Aux Input 1 or 2. The CH2 display can show Y, θ, In the above example, the displayed ratio of
Y Noise, Aux Input 3 or 4, or any of these quanti- 21.37% will output 2.137V from the CH1 output.
ties divided by Aux Input 3 or 4.
Output offsets ARE reflected in the displays. For

example, if CH1 is displaying X, it is affected by
the X offset. When the X output is offset to zero,
the displayed value will drop to zero also. Any dis-
play which is showing a quantity which is affected
by a non-zero offset will display a highlighted
Offset indicator below the display.
Output expands do NOT increase the displayed

values of X, Y or R. Expand increases the resolu-
tion of the X, Y or R value used to calculate the
displayed value. For example, CH1 when display-
ing X does not increase its displayed value when
X is expanded. This is because the expand func-
tion increases the resolution with which the signal
is measured, not the size of the input signal. The
displayed value will show an increased resolution
but will continue to display the original value of X
minus the X offset. Any display which is showing a
quantity which is affected by a non-unity expand
will display a highlighted Expand indicator below
the display.
Ratio displays are displayed as percentages. The

displayed percentage for X/Aux 1 would be
Display % = (signal/sensitivity-offset)xExpandx100
Aux In 1 (in Volts)
3-14
SR830 Basics
DYNAMIC RESERVE
We've mentioned dynamic reserve quite a bit in because the DC output amplifier is running at very
the preceding discussions. It's time to clarify high gain and low frequency noise and offset drift
dynamic reserve a bit. at the PSD output or the DC amplifier input will be
amplified and appear large at the output. The
What is dynamic reserve really? noise is more tolerable than the DC drift errors
Suppose the lock-in input consists of a full scale since increasing the time constant will attenuate
signal at fref plus noise at some other frequency. the noise. The DC drift in an analog lock-in is usu-
The traditional definition of dynamic reserve is the ally on the order of 1000ppm/°C when using 60 dB
ratio of the largest tolerable noise signal to the full of dynamic reserve. This means that the zero point
scale signal, expressed in dB. For example, if full moves 1% of full scale over 10°C temperature
scale is 1 µV, then a dynamic reserve of 60 dB change. This is generally considered the limit of
means noise as large as 1 mV (60 dB greater than tolerable.
full scale) can be tolerated at the input without
overload. Lastly, dynamic reserve depends on the noise fre-
quency. Clearly noise at the reference frequency
The problem with this definition is the word 'tolera- will make its way to the output without attenuation.
ble'. Clearly the noise at the dynamic reserve limit So the dynamic reserve at fref is 0dB. As the noise
should not cause an overload anywhere in the frequency moves away from the reference fre-
instrument - not in the input signal amplifier, PSD, quency, the dynamic reserve increases. Why?
low pass filter or DC amplifier. This is accom- Because the low pass filter after the PSD attenu-
plished by adjusting the distribution of the gain. To ates the noise components. Remember, the PSD
achieve high reserve, the input signal gain is set outputs are at a frequency of |fnoise -fref|. The rate
very low so the noise is not likely to overload. This at which the reserve increases depends upon the
means that the signal at the PSD is also very low pass filter time constant and roll off. The
small. The low pass filter then removes the large reserve increases at the rate at which the filter
noise components from the PSD output which rolls off. This is why 24 dB/oct filters are better
allows the remaining DC component to be ampli- than 6 or 12 dB/oct filters. When the noise fre-
fied (a lot) to reach 10 V full scale. There is no quency is far away, the reserve is limited by the
problem running the input amplifier at low gain. gain distribution and overload level of each gain
However, as we have discussed previously, element. This reserve level is the dynamic reserve
analog lock-ins have a problem with high reserve
because of the linearity of the PSD and the DC off- actual reserve
sets of the PSD and DC amplifier. In an analog
60 dB 60 dB specified reserve
lock-in, large noise signals almost always disturb
the measurement in some way.
The most common problem is a DC output error 40 dB

caused by the noise signal. This can appear as an
offset or as a gain error. Since both effects are
dependent upon the noise amplitude and frequen- 20 dB
cy, they can not be offset to zero in all cases and low pass filter
will limit the measurement accuracy. Because the bandwidth
errors are DC in nature, increasing the time con- 0 dB
stant does not help. Most lock-ins define tolerable
noise as noise levels which do not affect the fref fnoise
output more than a few percent of full scale. This
is more severe than simply not overloading. referred to in the specifications.
Another effect of high dynamic reserve is to gener- The above graph shows the actual reserve vs the
ate noise and drift at the output. This comes about frequency of the noise. In some instruments, the
3-15
SR830 Basics
signal input attenuates frequencies far outside the decrease and the output noise will decrease also.
lock-in's operating range (fnoise>>100 kHz). In In general, do not run with more reserve than nec-
these cases, the reserve can be higher at these essary. Certainly don't use High Reserve when
frequencies than within the operating range. While there is virtually no noise at all.
this may be a nice specification, removing noise at
frequencies very far from the reference does not The frequency dependence of dynamic reserve is
require a lock-in amplifier. Lock-ins are used when inherent in the lock-in detection technique. The
there is noise at frequencies near the signal. Thus, SR830, by providing more low pass filter stages,
the dynamic reserve for noise within the operating can increase the dynamic reserve close to the ref-
range is more important. erence frequency. The specified reserve applies to
noise signals within the operating range of the
Dynamic reserve in the SR830 lock-in, i.e. frequencies below 100 kHz. The
The SR830, with its digital phase sensitive detec- reserve at higher frequencies is actually higher but
tors, does not suffer from DC output errors caused is generally not that useful.
by large noise signals. The dynamic reserve can
be increased to above 100 dB without measure- Minimum dynamic reserve (Low Noise)
ment error. Large noise signals do not cause The SR830 always has a minimum amount of
output errors from the PSD. The large DC gain dynamic reserve. This minimum reserve is the Low
does not result in increased output drift. Noise reserve setting. The minimum reserve
changes with the sensitivity (gain) of the instru-
In fact, the only drawback to using ultra high ment. At high gains (full scale sensitivity of 50 µV
dynamic reserves (>60 dB) is the increased output and below), the minimum dynamic reserve
noise due to the noise of the A/D converter. This increases from 37 dB at the same rate as the sen-
increase in output noise is only present when the sitivity increases. For example, the minimum
dynamic reserve is above 60 dB AND set to High reserve at 5 µV sensitivity is 57 dB. In many
Reserve or Normal. However, the Low Noise analog lock-ins, the reserve can be lower. Why
reserve can be very high as we'll see shortly. can't the SR830 run with lower reserve at this
sensitivity?
To set a scale, the SR830's output noise at 100 dB
dynamic reserve is only measurable when the The answer to this question is - Why would you
signal input is grounded. Let's do a simple experi- want lower reserve? In an analog lock-in, lower
ment. If the lock-in reference is at 1 kHz and a reserve means less output error and drift. In the
large signal is applied at 9.5 kHz, what will the SR830, more reserve does not increase the output
lock-in output be? If the signal is increased to the error or drift. More reserve can increase the output
dynamic reserve limit (100 dB greater than full noise though. However, if the analog signal gain
scale), the output will reflect the noise of the signal before the A/D converter is high enough, the
at 1 kHz. The spectrum of any pure sine generator 5 nV/√Hz noise of the signal input will be amplified
always has a noise floor, i.e. there is some noise to a level greater than the input noise of the A/D
at all frequencies. So even though the applied converter. At this point, the detected noise will
signal is at 9.5 kHz, there will be noise at all other reflect the actual noise at the signal input and not
frequencies, including the 1 kHz lock-in reference. the A/D converter's noise. Increasing the analog
This noise will be detected by the lock-in and gain (decreasing the reserve) will not decrease the
appear as noise at the output. This output noise output noise. Thus, there is no reason to decrease
will typically be greater than the SR830's own the reserve. At a sensitivity of 5 µV, the analog
output noise. In fact, virtually all signal sources will gain is sufficiently high so that A/D converter noise
have a noise floor which will dominate the lock-in is not a problem. Sensitivities below 5 µV do not
output noise. Of course, noise signals are general- require any more gain since the signal to noise
ly much noisier than pure sine generators and will ratio will not be improved (the front end noise dom-
have much higher broadband noise floors. inates). The SR830 does not increase the gain
below the 5 µV sensitivity, instead, the minimum
If the noise does not reach the reserve limit, the reserve increases. Of course, the input gain can
SR830's own output noise may become detectable be decreased and the reserve increased, in which
at ultra high reserves. In this case, simply lower case the A/D converter noise might be detected in
the dynamic reserve and the DC gain will the absence of any signal input.
3-16
SR830 Basics
SIGNAL INPUT AMPLIFIER and FILTERS

A lock-in can measure signals as small as a few with a 100 ms time constant and 6 dB/oct of filter
nanovolts. A low noise signal amplifier is required roll off. The ENBW of a 100 ms, 6 dB/oct filter is
to boost the signal to a level where the A/D con- 2.5 Hz. The lock-in will measure the input noise
verter can digitize the signal without degrading the with an ENBW of 2.5 Hz. This translates to
signal to noise. The analog gain in the SR830 7.9 nVrms at the input. At the output, this repre-
ranges from roughly 7 to 1000. As discussed pre- sents about 0.16% of full scale (7.9 nV/5 µV). The
viously, higher gains do not improve signal to peak to peak noise will be about 0.8% of full scale.
noise and are not necessary.
All of this assumes that the signal input is being
The overall gain (AC plus DC) is determined by driven from a low impedance source. Remember
the sensitivity. The distribution of the gain (AC resistors have Johnson noise equal to
versus DC) is set by the dynamic reserve. 0.13x√R nVrms/√Hz. Even a 50Ω resistor has
almost 1 nVrms/√Hz of noise! A signal source
Input noise impedance of 2kΩ will have a Johnson noise
The input noise of the SR830 signal amplifier is greater than the SR830's input noise. To deter-
about 5 nVrms/√Hz. What does this noise figure mine the overall noise of multiple noise sources,
mean? Let's set up an experiment. If an amplifier take the square root of the sum of the squares of
has 5 nVrms/√Hz of input noise and a gain of the individual noise figures. For example, if a 2kΩ
1000, then the output will have 5 µVrms/√Hz of source impedance is used, the Johnson noise will
noise. Suppose the amplifier output is low pass fil- be 5.8 nVrms/√Hz. The overall noise at the SR830
tered with a single RC filter (6 dB/oct roll off) with a input will be [52 + 5.82]1/2 or 7.7 nVrms/√Hz.
time constant of 100 ms. What will be the noise at
the filter output? We'll talk more about noise sources later in this
section.
Amplifier input noise and Johnson noise of resis-
tors are Gaussian in nature. That is, the amount of At lower gains (sensitivities above 50 µV), there is
noise is proportional to the square root of the not enough gain at high reserve to amplify the
bandwidth in which the noise is measured. A input noise to a level greater than the noise of the
single stage RC filter has an equivalent noise A/D converter. In these cases, the output noise is
bandwidth (ENBW) of 1/4T where T is the time determined by the A/D noise. Fortunately, at these
constant (RxC). This means that Gaussian noise sensitivities, the DC gain is low and the noise at
at the filter input is filtered with an effective band- the output is negligible.
width equal to the ENBW. In this example, the
filter sees 5 µVrms/√Hz of noise at its input. It has Notch filters
an ENBW of 1/(4x100ms) or 2.5 Hz. The voltage The SR830 has two notch filters in the signal
noise at the filter output will be amplifier chain. These are pre-tuned to the line fre-
5 µVrms/√Hz x √2.5Hz or 7.9 µVrms. quency (50 or 60 Hz) and twice the line frequency
For Gaussian noise, the peak to peak noise is (100 or 120 Hz). In circumstances where the larg-
about 5 times the rms noise. Thus, the output will est noise signals are at the power line frequencies,
have about 40 µV pk-pk of noise. these filters can be engaged to remove noise sig-
nals at these frequencies. Removing the largest
Input noise for a lock-in works the same way. For noise signals before the final gain stage can
sensitivities below about 5 µV full scale, the input reduce the amount of dynamic reserve required to
noise will determine the output noise (at minimum perform a measurement. To the extent that these
reserve). The amount of noise at the output is filters reduce the required reserve to either 60 dB
determined by the ENBW of the low pass filter. or the minimum reserve (whichever is higher), then
See the discussion of noise later in this section for some improvement might be gained. If the
more information on ENBW. The ENBW depends required reserve without these notch filters is
upon the time constant and filter roll off. For exam- below 60 dB or if the minimum reserve is suffi-
ple, suppose the SR830 is set to 5 µV full scale cient, then these filters do not significantly improve
3-17
SR830 Basics
the measurement.
Using either of these filters precludes making

measurements in the vicinity of the notch frequen-
cies. These filters have a finite range of attenua-
tion, generally 10 Hz or so. Thus, if the lock-in is
making measurements at 70 Hz, do not use the
60 Hz notch filter! The signal will be attenuated
and the measurement will be in error. When meas-
uring phase shifts, these filters can affect phase
measurements up to an octave away.
Anti-aliasing filter
After all of the signal filtering and amplification,
there is an anti-aliasing filter. This filter is required
by the signal digitization process. According to the
Nyquist criterion, signals must be sampled at a fre-
quency at least twice the highest signal frequency.
In this case, the highest signal frequency is
100 kHz and the sampling frequency is 256 kHz
so things are ok. However, no signals above 128
kHz can be allowed to reach the A/D converter.
These signals would violate the Nyquist criterion
and be undersampled. The result of this under-
sampling is to make these higher frequency sig-
nals appear as lower frequencies in the digital
data stream. Thus a signal at 175 kHz would
appear below 100 kHz in the digital data stream
and be detectable by the digital PSD. This would
be a problem.
To avoid this undersampling, the analog signal is

filtered to remove any signals above 154 kHz
(when sampling at 256 kHz, signals above
154 kHz will appear below 102 kHz). This filter has
a flat pass band from DC to 102 kHz so as not to
affect measurements in the operating range of the
lock-in. The filter rolls off from 102 kHz to 154 kHz
and achieves an attenuation above 154 kHz of at
least 100 dB. Amplitude variations and phase
shifts due to this filter are calibrated out at the fac-
tory and do not affect measurements. This filter is
transparent to the user.
Input Impedance
The input impedance of the SR830 is 10 MΩ. If a
higher input impedance is desired, then the SR550
remote preamplifier must be used. The SR550 has
an input impedance of 100 MΩ and is AC coupled
from 1 Hz to 100 kHz.
3-18
SR830 Basics
INPUT CONNECTIONS
In order to achieve the best accuracy for a given Differential Voltage Connection (A-B)
measurement, care must be taken to minimize the The second method of connection is the differen-
various noise sources which can be found in the tial mode. The lock-in measures the voltage differ-
laboratory. With intrinsic noise (Johnson noise, 1/f ence between the center conductors of the A and
noise or input noise), the experiment or detector B inputs. Both of the signal connections are shield-
must be designed with these noise sources in ed from spurious pick-up. Noise pickup on the
mind. These noise sources are present regardless shields does not translate into signal noise since
of the input connections. The effect of noise sourc- the shields are ignored.
es in the laboratory (such as motors, signal gener-
ators, etc.) and the problem of differential grounds When using two cables, it is important that both
between the detector and the lock-in can be mini- cables travel the same path between the experi-
mized by careful input connections. ment and the lock-in. Specifically, there should not
be a large loop area enclosed by the two cables.
There are two basic methods for connecting a volt- Large loop areas are susceptible to magnetic
age signal to the lock-in - the single-ended con- pickup.
nection is more convenient while the differential
connection eliminates spurious pick-up more Experiment SR830 Lock-In
effectively. Signal A
Source +
Single-Ended Voltage Connection (A) -
In the first method, the lock-in uses the A input in a B
Loop
single-ended mode. The lock-in detects the signal R
Area
as the voltage between the center and outer con-
ductors of the A input only. The lock-in does not
force the shield of the A cable to ground, rather it Grounds may be at different potentials
is internally connected to the lock-in's ground via a
resistor. The value of this resistor is selected by
the user. Float uses 10 kΩ and Ground uses 10Ω. Common Mode Signals
This avoids ground loop problems between the Common mode signals are those signals which
experiment and the lock-in due to differing ground appear equally on both center and shield (A) or
potentials. The lock-in lets the shield 'quasi-float' in both A and B (A-B). With either connection
order to sense the experiment ground. However, scheme, it is important to minimize both the
noise pickup on the shield will appear as noise to common mode noise and the common mode
the lock-in. This is bad since the lock-in cannot signal. Notice that the signal source is held near
reject this noise. Common mode noise, which ground potential in both illustrations above. If the
appears on both the center and shield, is rejected signal source floats at a nonzero potential, the
by the 100 dB CMRR of the lock-in input, but noise signal which appears on both the A and B inputs
on only the shield is not rejected at all. will not be perfectly cancelled. The common mode
rejection ratio (CMRR) specifies the degree of can-
cellation. For low frequencies, the CMRR of 100
Experiment SR830 Lock-In dB indicates that the common mode signal is can-
Signal celed to 1 part in 105. Even with a CMRR of
A
Source + 100 dB, a 100 mV common mode signal behaves
- like a 1 µV differential signal! This is especially
bad if the common mode signal is at the reference
R
frequency (this happens a lot due to ground
loops). The CMRR decreases by about 6 dB/
octave (20 dB/decade) starting at around 1 kHz.
Grounds may be at different potentials
3-19
SR830 Basics
Current Input (I) AC vs DC Coupling

The current input on the SR830 uses the A input The signal input can be either AC or DC coupled.
BNC. The current input has a 1 kΩ input impe- The AC coupling high pass filter passes signals
dance and a current gain of either 106 or above 160 mHz (0.16 Hz) and attenuates signals
108 Volts/Amp. Currents from 1 µA down to 2 fA at lower frequencies. AC coupling should be used
full scale can be measured. at frequencies above 160 mHz whenever possible.
At lower frequencies, DC coupling is required.
The impedance of the signal source is the most
important factor to consider in deciding between A DC signal, if not removed by the AC coupling
voltage and current measurements. filter, will multiply with the reference sine wave and
produce an output at the reference frequency. This
For high source impedances, greater than 1 MΩ signal is not normally present and needs to be
(106 gain) or 100 MΩ (108 gain), and small cur- removed by the low pass filter. If the DC compo-
rents, use the current input. Its relatively low impe- nent of the signal is large, then this output will be
dance greatly reduces the amplitude and phase large and require a long time constant to remove.
errors caused by the cable capacitance-source AC coupling removes the DC component of the
impedance time constant. The cable capacitance signal without any sacrifice in signal as long as the
should still be kept small to minimize the high fre- frequency is above 160 mHz.
quency noise gain of the current preamplifier.
The current input current to voltage preamplifier is
For moderate to low source impedances, or larger always DC coupled. AC coupling can be selected
currents, the voltage input is preferred. A small following the current preamplifier to remove any
value resistor may be used to shunt the signal cur- DC current signal.
rent and generate a voltage signal. The lock-in
then measures the voltage across the shunt resis-
tor. Select the resistor value to keep the shunt volt-
age small (so it does not affect the source current)
while providing enough signal for the lock-in to
measure.
Which current gain should you use? The current

gain determines the input current noise of the lock-
in as well as its measurement bandwidth. Signals
far above the input bandwidth are attenuated by
6 dB/oct. The noise and bandwidth are listed
below.
Gain Noise Bandwidth
106 130 fA/√Hz 70 kHz

108 13 fA/√Hz 700 Hz
3-20
SR830 Basics
INTRINSIC (RANDOM) NOISE SOURCES

Random noise finds its way into experiments in a
variety of ways. Good experimental design can Slope ENBW Wait Time
reduce these noise sources and improve the 6 dB/oct 1/(4T) 5T
measurement stability and accuracy. 12 dB/oct 1/(8T) 7T
18 dB/oct 3/(32T) 9T
There are a variety of intrinsic noise sources which 24 dB/oct 5/(64T) 10T
are present in all electronic signals. These sources
are physical in origin. The signal amplifier bandwidth determines the
amount of broadband noise that will be amplified.
Johnson noise This affects the dynamic reserve. The time con-
Every resistor generates a noise voltage across its stant sets the amount of noise which will be meas-
terminals due to thermal fluctuations in the elec- ured at the reference frequency. See the SIGNAL
tron density within the resistor itself. These fluctua- INPUT AMPLIFIER discussion for more informa-
tions give rise to an open-circuit noise voltage, tion about Johnson noise.
1/2
V noise (rms) = ( 4k TR∆f) Shot noise
Electric current has noise due to the finite nature
where k=Boltzmann's constant (1.38x10-23 J/°K), of the charge carriers. There is always some non-
T is the temperature in °Kelvin (typically 300°K), R uniformity in the electron flow which generates
is the resistance in Ohms, and ∆f is the bandwidth noise in the current. This noise is called shot
in Hz. ∆f is the bandwidth of the measurement. noise. This can appear as voltage noise when cur-
rent is passed through a resistor, or as noise in a
Since the input signal amplifier in the SR830 has a current measurement. The shot noise or current
bandwidth of approximately 300 kHz, the effective noise is given by
noise at the amplifier input is Vnoise = 70√R nVrms 1/2
or 350√R nV pk-pk. This noise is broadband and if Inoise (rms) = (2q I∆f)
the source impedance of the signal is large, can
determine the amount of dynamic reserve where q is the electron charge (1.6x10 -19
required. Coulomb), I is the RMS AC current or DC current
depending upon the circuit, and ∆f is the
The amount of noise measured by the lock-in is bandwidth.
determined by the measurement bandwidth.
Remember, the lock-in does not narrow its detec- When the current input of a lock-in is used to
tion bandwidth until after the phase sensitive measure an AC signal current, the bandwidth is
detectors. In a lock-in, the equivalent noise band- typically so small that shot noise is not important.
width (ENBW) of the low pass filter (time constant)
sets the detection bandwidth. In this case, the 1/f noise
measured noise of a resistor at the lock-in input, Every 10 Ω resistor, no matter what it is made of,
typically the source impedance of the signal, is has the same Johnson noise. However, there is
simply excess noise in addition to Johnson noise which
arises from fluctuations in resistance due to the
V noise (rms) = 0.13 R ENBW nV current flowing through the resistor. For carbon
composition resistors, this is typically 0.1 µV-3 µV
The ENBW is determined by the time constant and of rms noise per Volt of applied across the resis-
slope as shown in the following table. Wait time is tor. Metal film and wire-wound resistors have
the time required to reach 99% of its final value. about 10 times less noise. This noise has a 1/f
spectrum and makes measurements at low fre-
T= Time Constant quencies more difficult.
3-21
SR830 Basics
Other sources of 1/f noise include noise found in

vacuum tubes and semiconductors.
Total noise
All of these noise sources are incoherent. The
total random noise is the square root of the sum of
the squares of all the incoherent noise sources.
3-22
SR830 Basics
EXTERNAL NOISE SOURCES

In addition to the intrinsic noise sources discussed For example, if the noise source is a power circuit,
in the previously, there are a variety of external then f = 60 Hz and V noise = 120 V. Cstray can be
noise sources within the laboratory. estimated using a parallel plate equivalent capaci-
tor. If the capacitance is roughly an area of 1 cm2
Most of these noise sources are asynchronous, at a separated by 10 cm, then Cstray is 0.009 pF.
i.e. they are not related to the reference and do The resulting noise current will be 400 pA (at
not occur at the reference frequency or its harmon- 60 Hz). This small noise current can be thousands
ics. Examples include lighting fixtures, motors, of times larger than the signal current. If the noise
cooling units, radios, computer screens, etc. source is at a higher frequency, the coupled noise
These noise sources affect the measurement by will be even greater.
increasing the required dynamic reserve or length-
ening the time constant. If the noise source is at the reference frequency,
then the problem is much worse. The lock-in
Some noise sources, however, are related to the rejects noise at other frequencies, but pick-up at
reference and, if picked up in the signal, will add or the reference frequency appears as signal!
subtract from the actual signal and cause errors in
the measurement. Typical sources of synchronous Cures for capacitive noise coupling include:
noise are ground loops between the experiment,
detector and lock-in, and electronic pick up from 1) Removing or turning off the noise source.
the reference oscillator or experimental apparatus.
2) Keeping the noise source far from the
Many of these noise sources can be minimized experiment (reducing Cstray). Do not bring
with good laboratory practice and experiment the signal cables close to the noise
design. There are several ways in which noise source.
sources are coupled into the signal path.
3) Designing the experiment to measure volt-
Capacitive coupling ages with low impedance (noise current
An AC voltage from a nearby piece of apparatus generates very little voltage).
can couple to a detector via a stray capacitance.
Although Cstray may be very small, the coupled 4) Installing capacitive shielding by placing
noise may still be larger than a weak experimental both the experiment and detector in a
signal. This is especially damaging if the coupled metal box.
noise is synchronous (at the reference frequency).
Inductive coupling
Stray Capacitance An AC current in a nearby piece of apparatus can
Experiment Noise couple to the experiment via a magnetic field. A
Source changing current in a nearby circuit gives rise to a
changing magnetic field which induces an emf
(dØ B/dt) in the loop connecting the detector to the
Detector
experiment. This is like a transformer with the
experiment-detector loop as the secondary
winding.
We can estimate the noise current caused by a
stray capacitance by, B(t)
Experiment
i = C stray dV = ωC stray V noise

dt
Detector Noise
Source
where ω is 2π times the noise frequency, Vnoise is
the noise amplitude, and Cstray is the stray
capacitance.
3-23
SR830 Basics
Cures for inductively coupled noise include: Microphonics

Not all sources of noise are electrical in origin.
1) Removing or turning off the interfering Mechanical noise can be translated into electrical
noise source. noise by microphonic effects. Physical changes in
the experiment or cables (due to vibrations for
2) Reduce the area of the pick-up loop by example) can result in electrical noise over the
using twisted pairs or coaxial cables, or entire frequency range of the lock-in.
even twisting the 2 coaxial cables used in
differential connections. For example, consider a coaxial cable connecting
a detector to a lock-in. The capacitance of the
3) Using magnetic shielding to prevent the cable is a function of its geometry. Mechanical
magnetic field from crossing the area of vibrations in the cable translate into a capacitance
the experiment. that varies in time, typically at the vibration fre-
quency. Since the cable is governed by Q=CV,
4) Measuring currents, not voltages, from
high impedance detectors. C dV + V dC = dQ = i
dt dt dt
Resistive coupling or ground loops taking the derivative, we have
Currents flowing through the ground connections Mechanical vibrations in the cable which cause a
can give rise to noise voltages. This is especially a dC/dt will give rise to a current in the cable. This
current affects the detector and the measured
Experiment
Detector signal.
Some ways to minimize microphonic signals are:
1) Eliminate mechanical vibrations near the

I(t) experiment.
2) Tie down cables carrying sensitive signals

Noise Source so they do not move.
problem with reference frequency ground currents. 3) Use a low noise cable that is designed to
In this illustration, the detector is measuring the reduce microphonic effects.
signal relative to a ground far from the rest of the
experiment. The experiment senses the detector Thermocouple effects
signal plus the voltage due to the noise source's The emf created by junctions between dissimilar
ground return current passing through the finite metals can give rise to many microvolts of slowly
resistance of the ground between the experiment varying potentials. This source of noise is typically
and the detector. The detector and the experiment at very low frequency since the temperature of the
are grounded at different places which, in this detector and experiment generally changes slowly.
case, are at different potentials. This effect is large on the scale of many detector
outputs and can be a problem for low frequency
Cures for ground loop problems include: measurements, especially in the mHz range.
1) Grounding everything to the same physi- Some ways to minimize thermocouple effects are:
cal point.
1) Hold the temperature of the experiment or
2) Using a heavy ground bus to reduce the detector constant.
resistance of ground connections.
2) Use a compensation junction, i.e. a
3) Removing sources of large ground cur- second junction in reverse polarity which
rents from the ground bus used for small generates an emf to cancel the thermal
signals. potential of the first junction. This second
junction should be held at the same tem-
3-24 perature as the first junction.
SR830 Basics
NOISE MEASUREMENTS
Lock-in amplifiers can be used to measure noise. is computed. This is the mean value of X over
Noise measurements are generally used to char- some past history. The present mean value of X is
acterize components and detectors. subtracted from the present value of X to find the
deviation of X from the mean. Finally, the moving
The SR830 measures input signal noise AT the average of the absolute value of the deviations is
reference frequency. Many noise sources have a calculated. This calculation is called the mean
frequency dependence which the lock-in can average deviation or MAD. This is not the same as
measure. an RMS calculation. However, if the noise is
Gaussian in nature, then the RMS noise and the
How does a lock-in measure noise? MAD noise are related by a constant factor.
Remember that the lock-in detects signals close to
the reference frequency. How close? Input signals The SR830 uses the MAD method to estimate the
within the detection bandwidth set by the low pass RMS noise of X and Y. The advantage of this tech-
filter time constant and roll-off appear at the output nique is its numerical simplicity and speed.
at a frequency f=fsig -fref. Input noise near fref
appears as noise at the output with a bandwidth of The noise calculations for X and Y occur at
DC to the detection bandwidth. 512 Hz. At each sample, the mean and moving
average of the absolute value of the deviations is
For Gaussian noise, the equivalent noise band- calculated. The averaging time (for the mean and
width (ENBW) of a low pass filter is the bandwidth average deviation) depends upon the time con-
of the perfect rectangular filter which passes the stant. The averaging time is selected by the
same amount of noise as the real filter. SR830 and ranges from 10 to 80 times the time
constant. Shorter averaging times yield a very
The ENBW is determined by the time constant and poor estimate of the noise (the mean varies rapidly
slope as shown below. Wait time is the time and the deviations are not averaged well). Longer
required to reach 99% of its final value. averaging times, while yielding better results, take
a long time to settle to a steady answer.
T= Time Constant
To change the settling time, change the time con-
Slope ENBW Wait Time stant. Remember, shorter settling times use small-
6 dB/oct 1/(4T) 5T er time constants (higher noise bandwidths) and
12 dB/oct 1/(8T) 7T yield noisier noise estimates.
18 dB/oct 3/(32T) 9T
24 dB/oct 5/(64T) 10T X and Y noise are displayed in units of
Volts/√Hz. The ENBW of the time constant is
Noise estimation already factored into the calculation. Thus, the
The noise is simply the standard deviation (root of mean displayed value of the noise should not
the mean of the squared deviations)of the meas- depend upon the time constant.
ured X, Y or R .
The SR830 performs the noise calculations all of
The above technique, while mathematically sound, the time, whether or not X or Y noise are being
can not provide a real time output or an analog displayed. Thus, as soon as X noise is displayed,
output proportional to the measured noise. For the value shown is up to date and no settling time
these measurements, the SR830 estimates the X is required. If the sensitivity is changed, then the
or Y noise directly. noise estimate will need to settle to the correct
value.
To display the noise of X, for example, simply set
the CH1 display to X noise. The quantity X noise is
computed from the measured values of X using
the following algorithm. The moving average of X
3-25
SR830 Basics
3-26
FRONT PANEL
CH1 Display CH2 Display Ref Display
Signal Inputs Analog Outputs Ref Input Sine Output
Power The power switch is on the rear panel. The SR830 is turned on by push-
ing the switch up. The serial number (5 digits) is shown in the CH1 and
CH2 displays and the firmware version is shown in the Ref display at
power on.
A series of internal tests are performed at this point.
DATA Performs a read/write test to the processor RAM.
BATT The nonvolatile backup memory is tested. Instrument settings are stored
in nonvolatile memory and are retained when the power is turned off.
PROG Checks the processor ROM.
DSP Checks the digital signal processor (DSP).
rCAL If the backup memory check passes, then the instrument returns to the
settings in effect when the power was last turned off (User). If there is a
memory error, then the stored settings are lost and the standard (Std)
settings are used.
Reset To reset the unit, hold down the [Setup] key while the power is turned on.
The unit will use the standard settings. The standard setup is listed on
the next page.
[Keys] The keys are grouped and labelled according to function. This manual
will refer to a key with brackets such as [Key]. A complete description of
the keys follows in this section.
4-1
Front Panel
Knob The knob is used to adjust parameters in the Reference display. The
parameters which may be adjusted are internal reference frequency, ref-
erence phase shift, sine output amplitude, harmonic detect number, off-
sets, Aux Output levels, and various Setup parameters.
Local Lockout If the computer interface has placed the unit in the REMOTE state, indi-
cated by the REMOTE led, then the keys and the knob are disabled.
Attempts to change the settings from the front panel will display the mes-
sage 'LOCL LOut' indicating local control is locked out by the interface.
Reference Input The reference input can be a sine wave (rising zero crossing detected) or
a TTL pulse or square wave (rising or falling edge). The input impedance
is 1 MΩ AC coupled (>1 Hz) for the sine input. For low frequencies (<1
Hz), it is necessary to use a TTL reference signal. The TTL input pro-
vides the best overall performance and should be used whenever possi-
ble.
Sine Out The internal oscillator output has a 50Ω output impedance and varies in
amplitude from 4 mVrms to 5 Vrms. The output level is specified into a
high impedance load. If the output is terminated in a low impedance,
such as 50Ω, the amplitude will be less than the programmed amplitude
(half for a 50Ω load).
This output is active even when an external reference is used. In this

case, the sine wave is phase locked to the reference and its amplitude is
programmable.
A TTL sync output is provided on the rear panel. This output is useful for
triggering scopes and other equipment at the reference frequency. The
TTL sync output is a square wave derived from the zero crossings of the
sine output.
CH1 & CH2 Outputs The Channel 1 and Channel 2 outputs can be configured to output a volt-
age from -10 V to +10 V proportional to X or Y or the CH1 and CH2
Displays. ±10 V is full scale. The outputs can source 10 mA maximum.
Signal Inputs The input mode may be single-ended, A, or differential, A-B. The A and B
inputs are voltage inputs with 10 MΩ, 25 pF input impedance. Their con-
nector shields are isolated from the chassis by 10 Ω (Ground) or 1 kΩ
(Float). Do not apply more than 50 V to either input. The shields should
never exceed 1 V. The I (current) input is 1 kΩ to a virtual ground.
Key Click On/Off Press the [Phase] and [Harm#] keys together to toggle the key click on
and off.
Front Panel Display Test To test the front panel displays, press the [Phase] and [Freq] keys
together. All of the LED's will turn on. Press [Phase] to decrease the
number of on LED's to half on, a single LED and no LED's on. Use the
knob to move the turned on LED's across the panel. Press [Freq] to
increase the number of on LED's. Make sure that every LED can be
turned on. Press any other key to exit this test mode.
Display Off Operation To operate with the front panel displays off, press [Phase] and [Freq]
together to enter the front panel test mode. Press [Phase] to decrease
4-2
Front Panel
the number of on LED's until all of the LED's are off. The SR830 is still
operating, the output voltages are updated and the unit responds to inter-
face commands. To change a setting, press any key other than [Phase]
or [Freq] to return to normal operation, change the desired parameter,
then press [Phase] and [Freq] together to return to the test mode. Turn
the LED's all off with the [Phase] key.
Keypad Test To test the keypad, press the [Phase] and [Ampl] keys together. The
CH1 and CH2 displays will read 'PAd codE' and a number of LED indica-
tors will be turned on. The LED's indicate which keys have not been
pressed yet. Press all of the keys on the front panel, one at a time. As
each key is pressed, the key code is displayed in the Reference display,
and the nearest indicator LED turns off. When all of the keys have been
pressed, the display will return to normal. To return to normal operation
without pressing all of the keys, simply turn the knob.
4-3
Front Panel
STANDARD SETTINGS
If the [Setup] key is held down when the power is turned on, the lock-in settings will be set to the defaults
shown below rather than the settings that were in effect when the power was last turned off. The default set-
tings may also be recalled using the ❊RST command over the computer interface. In this case, the communi-
cations parameters and status registers are not changed.
REFERENCE / PHASE OUTPUT / OFFSET

Phase 0.000° CH1 Output X
Reference Source Internal CH2 Output Y
Harmonic # 1 All Offsets 0.00%
Sine Amplitude 1.000 Vrms All Expands 1
Internal Frequency 1.000 kHz
Ext Reference Trigger Sine AUX OUTPUTS
All Output Voltages 0.000 V
INPUT / FILTERS
Source A SETUP
Grounding Float Output To GPIB
Coupling AC GPIB Address 8
Line Notches Out RS232 Baud Rate 9600
Parity None
GAIN / TC Key Click On
Sensitivity 1V Alarms On
Reserve Low Noise Override Remote On
Time Constant 100 ms
Filter dB/oct. 12 dB DATA STORAGE
Synchronous Off Sample Rate 1 Hz
Scan Mode Loop
DISPLAY Trigger Starts No
CH1 X
CH2 Y STATUS ENABLE
Ratio None REGISTERS Cleared
Reference Frequency
4-4
Front Panel
Signal Input and Filters
[Input] The [Input] key selects the front end signal input configuration. The input
amplifier can be either a single-ended (A) or differential (A-B) voltage or
a current (I).
The voltage inputs have a 10 MΩ, 25 pF input impedance. Their connec-

tor shields are isolated from the chassis by either 10 Ω (Ground) or
10 kΩ (Float). Do not apply more than 50 V to either input. The shields
should never exceed 1 V.
The current input uses the A connector. The input is 1 kΩ to a virtual

ground. The largest allowable DC current before overload is 10 µA (1 M
gain) or 100 nA (100 M gain). No current larger than 10 mA should ever
be applied to this input.
The current gain determines the input current noise as well as the input
bandwidth. The 100 MΩ gain has 10 times lower noise but 100 times
lower bandwidth. Make sure that the signal frequency is below the input
bandwidth. The noise and bandwidth are listed below.
Gain Noise Bandwidth

1M 130 fA/√Hz 70 kHz
100M 13 fA/√Hz 700 Hz
The impedance of the current source should be greater than 1 MΩ when

using the 1M gain or 100 MΩ when using the 100M gain.
Changing the current gain does not change the instrument sensitivity.
Sensitivities above 10 nA require a current gain of 1 MΩ. Sensitivities
between 20 nA and 1 µA automatically select the 1 MΩ current gain. At
sensitivities below 20 nA, changing the sensitivity does not change the
current gain.
The message 'IGAn chG' is displayed to indicate that the current gain
has been changed to 1 MΩ as a result of changing the sensitivity.
4-5
Front Panel
INPUT OVLD The OVLD led in this section indicates an INPUT overload. This occurs
for voltage inputs greater than 1.4Vpk (unless removed by AC coupling)
or current inputs greater than 10 µA DC or 1.4 µA AC (1MΩ gain) or
100 nA DC or 14 nA AC (100MΩ gain). Reduce the input signal level.
[Couple] This key selects the input coupling. The signal input can be either AC or
DC coupled. The current input is coupled after the current to voltage con-
version. The current input itself is always DC coupled (1 kΩ to virtual
ground).
The AC coupling high pass filter passes signals above 160 mHz and
attenuates signals at lower frequencies. AC coupling should be used at
frequencies above 160 mHz whenever possible. At lower frequencies,
DC coupling is required. AC coupling results in gain and phase errors at
low frequencies.
Remember, the Reference Input is AC coupled when a sine refer-

ence is used. This also results in phase errors at low frequencies.
[Ground] This key chooses the shield grounding configuration. The shields of the
input connectors (A and B) are not connected directly to the lock-in chas-
sis ground. In Float mode, the shields are connected by 10 kΩ to the
chassis ground. In Ground mode, the shields are connected by 10 Ω to
ground. Typically, the shields should be grounded if the signal source is
floating and floating if the signal source is grounded. Do not exceed 1 V
on the shields.
[Notch] This key selects no line notch filters, the line frequency or twice line fre-
quency notch, or both filters. The line notch filters are pre-tuned to the
line frequency (50 or 60 Hz) and twice the line frequency (100 or 120
Hz).
These filters have an attenuation depth of at least 30 dB. These filters

have a finite range of attenuation, generally 10 Hz or so. If the reference
frequency is 70 Hz, do not use the 60 Hz notch filter! The signal will be
attenuated and the phase shifted. See the SR830 Basics section for a
discussion of when these filters improve a measurement.
4-6
Front Panel
Sensitivity, Reserve and Time Constants
[Sensitivity Up/Dn] The [Sensitivity Up] and [Sensitivity Down] keys select the full scale sen-
sitivity. The sensitivity is indicated by 1-2-5 times 1, 10 or 100 with the
appropriate units.
The full scale sensitivity can range from 2 nV to 1 V (rms) or 2 fA to 1 µA

(rms). The sensitivity indication is not changed by the X, Y, or R output
expand. The expand functions increase the output scale as well as the
display resolution.
Changing the sensitivity may change the dynamic reserve. Sensitivity

takes precedence over dynamic reserve. See the next page for more
details.
Auto Gain
Pressing the [AUTO GAIN] key will automatically adjust the sensitivity
based upon the detected signal magnitude (R). Auto Gain may take a
long time if the time constant is very long. If the time constant is greater
than 1 second, Auto Gain will abort.
RESERVE OVLD The OVLD led in the Sensitivity section indicates that the signal amplifier
is overloaded. Change the sensitivity or increase the dynamic reserve.
[Reserve] This key selects the reserve mode, either Low Noise, Normal or High
Reserve. The actual reserve (in dB) depends upon the sensitivity. When
the reserve is High, the SR830 automatically selects the maximum
reserve available at the present full scale sensitivity. When the reserve is
Low, the minimum available reserve is selected. Normal is between the
maximum and minimum reserve. Changing the sensitivity may change
the actual reserve, NOT the reserve mode.
4-7
Front Panel
The actual dynamic reserves (in dB) for each sensitivity are listed below.
Sensitivity Low Noise Normal High Reserve

1V 0 0 0
500 mV 6 6 6
200 mV 4 14 14
100 mV 0 10 20
50 mV 6 16 26
20 mV 4 24 34
10 mV 0 20 40
5 mV 6 26 46
2 mV 4 34 54
1 mV 10 40 60
500 µV 16 46 66
200 µV 24 54 74
100 µV 30 60 80
50 µV 36 66 86
20 µV 44 74 94
10 µV 50 80 100
5 µV 56 86 106
2 µV 64 94 114
1 µV 70 100 120
500 nV 76 106 126
200 nV 84 114 134
100 nV 90 120 140
50 nV 96 126 146
20 nV 104 134 154
10 nV 110 140 160
5 nV 116 146 166
2 nV 124 154 174
Do not use ultra high dynamic reserves above 120 dB unless absolutely
necessary. It will be very likely that the noise floor of any interfering
signal will obscure the signal at the reference and make detection difficult
if not impossible. See the SR830 Basics section for more information.
Auto Reserve
Pressing [AUTO RESERVE] will change the reserve mode to the mini-
mum reserve required. Auto Reserve will not work if there are low fre-
quency noise sources which overload infrequently.
[Time Constant Up/Dn] This key selects the time constant. The time constant may be set from 10
µs to 30 s (detection freq.>200 Hz) or 30 ks (detection freq. <200 Hz).
The detection frequency is the reference frequency times the harmonic
detect number. The time constant is indicated by 1 or 3 times 1, 10 or
100 with the appropriate units.
The maximum time constant is 30 s if the detection frequency is above

200 Hz and 30 ks if the detection frequency is below 200 Hz. The actual
range switches at 203.12 Hz when the frequency is increasing and at
199.21 Hz when the frequency is decreasing. The time constant may not
be adjusted beyond the maximum for the present detection frequency. If
the detection frequency is below 200 Hz and 100 s is the time constant
4-8
Front Panel
and the frequency increases above 200 Hz, the time constant WILL
change to 30 s. Decreasing the frequency back below 200 Hz will NOT
change the time constant back to 100 s.
The absolute minimum time constant is 10 µs. The actual minimum time
constant depends upon the filter slope and the DC gain in the low pass
filter (dynamic reserve plus expand). The minimum time constant is only
restricted if the dynamic reserve plus expand is high and the filter slope
is low - not a normal operating situation. The tables below list the mini-
mum time constants for the different filter slopes and gains.
6 dB/oct DC gain (dB) min time constant

<45 10 µs
<55 30 µs
<65 100 µs
<75 300 µs
<85 1 ms
<95 3 ms
<105 10 ms
<115 30 ms
<125 100 ms
<135 300 ms
<145 1s
<155 3s
<165 10 s
<175 30 s

<55 10 µs
<75 30 µs
<95 100 µs
<115 300 µs
<135 1 ms
<155 3 ms
<175 10 ms

<62 10 µs
<92 30 µs
<122 100 µs
<152 300 µs
<182 1 ms

<72 10 µs
<112 30 µs
<152 100 µs
<182 300 µs
To use these tables, choose the correct table for the filter slope in use.
Calculate the DC gain by adding the reserve to the expand (expressed in
dB). Find the smallest DC gain entry which is larger than the gain in use.
Read the minimum time constant for this entry. For example, if the slope
is 12 dB/oct, the reserve is 64 dB, and the X expand is 10 (20 dB), then
4-9
Front Panel
the DC gain is 84 dB and the min time constant is 100 µs.
Time constant is a low priority parameter. If the sensitivity, dynamic

reserve, filter slope, or expand is changed, and the present time constant
is below the new minimum, the time constant WILL change to the new
minimum. Remember, changing the sensitivity may change the reserve
and thus change the time constant.
The message 'tc chnG' will be displayed to indicate that the time constant
has been changed, either by increasing the detection frequency above
200 Hz, or by changing the sensitivity, dynamic reserve, filter slope, or
expand.
The time constant also determines the equivalent noise bandwidth

(ENBW) of the low pass filter. This is the measurement bandwidth for X
and Y noise and depends upon the time constant and filter slope. (See
the Noise discussion in the SR830 Basics section.)
FILTER OVLD The OVLD led in the Time Constant section indicates that the low pass
filters have overloaded. Increase the time constant or filter roll-off, or
decrease the dynamic reserve.
Analog Outputs with Short Time Constants

When using short time constants below 10 ms, the X and Y analog out-
puts from the rear panel or the CH1 and CH2 outputs configured to
output X or Y should be used. These outputs have a 100 kHz bandwidth
and are accurate even with short time constants. CH1 or CH2 outputs
proportional to the Displays (even if X or Y is displayed) are updated at a
512 Hz rate. These outputs do not accurately reflect high frequency out-
puts.
[Slope /oct] This key selects the low pass filter slope (number of poles). Each pole
contributes 6 dB/oct of roll off. Using a higher slope can decrease the
required time constant and make a measurement faster. The filter slope
affects the minimum time constant (see above). Changing the slope may
change the time constant if the present time constant is shorter than the
minimum time constant at the new filter slope.
[Sync Filter] Pressing this key selects no synchronous filtering or synchronous filtering
on below 200 Hz. In the second case, the synchronous filter is switched
on whenever the detection frequency decreases below 199.21 Hz and
switched off when the detection frequency increases above 203.12 Hz.
The detection frequency is the reference frequency times the harmonic
detect number. The SYNC indicator in the CH1 display is turned on
whenever synchronous filtering is active.
When the synchronous filter is on, the phase sensitive detectors (PSD's)
are followed by 2 poles of low pass filtering, the synchronous filter, then 2
more poles of low pass filtering. The low pass filters are set by the time
constant and filter slope. If the filter slope requires less then 4 poles
(<24 dB/oct), then the unused poles are set to a minimum time constant.
The poles which are set by the time constant are the ones closest to the
PSD's. For example, if the time constant is 100 ms with 12 dB/oct slope
and synchronous filtering is on, then the PSD's are followed by two poles
4-10
Front Panel
of low pass filtering with 100 ms time constant, the synchronous filter,
then two poles of minimum time constant.
Synchronous filtering removes outputs at harmonics of the reference fre-

quency, most commonly 2xf. This is very effective at low reference fre-
quencies since 2xf outputs would require very long time constants to
remove. The synchronous filter does NOT attenuate broadband noise
(except at the harmonic frequencies). The low pass filters remove out-
puts due to noise and interfering signals. See the SR830 Basics section
for a discussion of time constants and filtering.
Note :
The synchronous filter averages the outputs over a complete period.
Each period is divided into 128 equal time slots. At each slot, the aver-
age over the previous 128 slots is computed and output. This results in
an output rate of 128xf. This output is then smoothed by the two poles of
filtering which follow the synchronous filter.
The settling time of the synchronous filter is one period of the detection
frequency. If the amplitude, frequency, phase, time constant or slope is
changed, then the outputs will settle for one period. These transients are
because the synchronous filter provides a steady output only if the input
is repetitive from period to period. The transient response also depends
upon the time constants of the regular filters. Very short time constants
(<<period) have little effect on the transient response. Longer time con-
stants (<period) can magnify the amplitude of a transient. Much longer
time constants (≥ period) will increase the settling time far beyond a
period.
Use of the Synchronous filter results in a reduction in amplitude resolu-

tion.
4-11
Front Panel
CH1 Display and Output
[Display] This key selects the Channel 1 display quantity. Channel 1 may display
X, R, X Noise, Aux Input 1 or Aux Input 2. The numeric display has the
units of the input signal. The bar graph is ±full scale sensitivity for X, R
and X Noise, and ±10V for the Aux Inputs. Ratio displays are shown in %
and the bar graph is scaled to ±100%. See the SR830 Basics section for
a complete discussion of scaling.
OUTPUT OVLD The OVLD led in the display indicates that the Channel 1 output is over-
loaded (greater than 1.09 times full scale). This can occur if the sensitivi-
ty is too low or if the output is expanded such that the output voltage
would exceed 10V.
AUTO This indicator is turned while an auto function is in progress.
SYNC When the synchronous output filter is selected AND the detection fre-
quency is below 200 Hz, then the SYNC indicator will be on. If the detec-
tion frequency is above 200 Hz, synchronous filtering is not active and
SYNC is off.
[Ratio] This key selects ratio measurements on Channel 1. The Channel 1 dis-
play may show X, R, X Noise, Aux Input 1 or Aux Input 2 divided by Aux
Input 1 or 2. The denominator is indicated by the AUX IN leds above this
key. The Ratio indicator in the display is on to indicate a ratio measure-
4-12
Front Panel
ment. Pressing this key until the AUX IN leds and the Ratio indicator are
off returns the measurement to non-ratio mode.
[Output] This key selects the CH1 OUTPUT source. The Channel 1 Output can
provide an analog output proportional to the Display or X. The output pro-
portional to X has a bandwidth of 100 kHz (the output is updated at 256
kHz). This output is the traditional X output of a lock-in. Output propor-
tional to the display (even if the display is simply X) has a bandwidth of
200 Hz (updated at 512 Hz).
Remember, The X output has 100 kHz of bandwidth. The Display output
should only be used if the time constant is sufficiently long such that
there are no high frequency outputs.
CH1 Offset and Expand The X and R outputs may be offset and expanded separately. Choose
either X or R with the [Display] key to adjust the X or R offset and
expand.
X and R analog outputs are determined by
Output = (signal/sensitivity - offset) x Expand x 10 V
The output is normally 10 V for a full scale signal. The offset subtracts a
percentage of full scale from the output. Expand multiplies the remainder
by a factor from 1, 10 or 100.
Output offsets ARE reflected in displays which depend upon X or R.
X and Y offsets do NOT affect the calculation of R and θ.
Output expands do NOT increase the displayed values of X or R. Expand

increases the display resolution.
If the display is showing a quantity which is affected by an offset or a

non-unity expand, then the Offset and Expand indicators are turned on
below the display.
See the SR830 Basics section for a complete discussion of scaling, off-
sets and expands.
[Offset On/Off] Pressing this key turns the X or R offset (as selected by the [Display]
key) on or off. The Offset indicator below the display turns on when the
displayed quantity is offset. This key allows the offset to be turned on and
off without adjusting the actual offset percentage.
[Modify] This key displays the X or R offset percentage (as selected by the
[Display] key) in the Reference Display. Use the knob to adjust the offset.
The Channel 1 display reflects the offset as it is adjusted while the
Reference display shows the actual offset percentage. The offset ranges
from -105.00% to 105.00% of full scale. The offset percentage does
not change with sensitivity - it is an output function. To return the
Reference Display to its original display, press the desired reference
display key ([Phase], [Freq], [Ampl], [Harm #] or [Aux Out]).
4-13
Front Panel
[Auto Offset] Pressing this key automatically sets the X or R offset percentage to offset
the selected output quantity to zero.
[Expand] Pressing this key selects the X and R Expand. Use the [Display] key to
select either X or R. The expand can be 1 (no expand), 10 or 100. If the
expand is 10 or 100, the Expand indicator below the display will turn on.
The output can never exceed full scale when expanded. For example, if
an output is 10% of full scale, the largest expand (with no offset) which
does not overload is 10. An output expanded beyond full scale will be
overloaded.
Short Time Constant Limitations

A short time constant places a limit on the total amount of DC gain
(reserve plus expand) available. If the time constant is short, the filter
slope low and the dynamic reserve high, then increasing the expand may
change the time constant. See the table of time constants and DC gains
in the Gain and Time Constant section.
4-14
Front Panel
CH2 Display and Output
[Display] This key selects the Channel 2 display quantity. Channel 2 may display
Y, θ, Y Noise, Aux Input 3 or Aux Input 4. The numeric display has the
units of the input signal. The bar graph is ±full scale sensitivity for Y and
Y Noise, ±180 ° for θ, and ±10V for the Aux Inputs. Ratio displays are
shown in % and the bar graph is scaled to ±100%. See the SR830
Basics section for a complete discussion of scaling.
OUTPUT OVLD The OVLD led in the display indicates that the Channel 2 output is over-
loaded (greater than 1.09 times full scale). This can occur if the sensitivi-
ty is too low or if the output is expanded such that the output voltage
would exceed 10V.
AUTO This indicator is turned while an auto function is in progress.
TRIG The TRIG indicator flashes whenever a trigger is received at the rear
panel trigger input AND internal data storage is triggered.
[Ratio] This key selects ratio measurements on Channel 2. The Channel 2 dis-
play may show Y, θ, Y Noise, Aux Input 3 or Aux Input 4 divided by Aux
Input 3 or 4. The denominator is indicated by the AUX IN leds above this
key. The Ratio indicator in the display is on to indicate a ratio measure-
ment. Pressing this key until the AUX IN leds and the Ratio indicator are
off returns the measurement to non-ratio mode.
4-15
Front Panel
[Output] This key selects the CH2 OUTPUT source. The Channel 2 Output can
provide an analog output proportional to the Display or Y. The output pro-
portional to Y has a bandwidth of 100 kHz (the output is updated at 256
kHz). This output is the traditional Y output of a lock-in. Output propor-
tional to the display (even if the display is simply Y) has a bandwidth of
200 Hz (updated at 512 Hz).
Remember, The Y output has 100 kHz of bandwidth. The Display output
should only be used if the time constant is sufficiently long such that
there are no high frequency outputs.
CH2 Offset and Expand The Y output may be offset and expanded. Choose Y with the [Display]
key to adjust the Y offset and expand.
The Y analog output is determined by
Output = (signal/sensitivity - offset) x Expand x 10 V
The output is normally 10 V for a full scale signal. The offset subtracts a
percentage of full scale from the output. Expand multiplies the remainder
by a factor from 1, 10 or 100.
Y Output offset IS reflected in displays which depend upon Y.
X and Y offsets do NOT affect the calculation of R or θ.
Y Output expand does NOT increase the displayed value Y. Expand

increases the display resolution.
If the display is showing a quantity which is affected by an offset or a

non-unity expand, then the Offset and Expand indicators are turned on
below the display.
See the SR830 Basics section for a complete discussion of scaling, off-
sets and expands.
[Offset On/Off] Pressing this key turns the Y offset on or off. The Offset indicator below
the display turns on when the displayed quantity is offset. This key allows
the offset to be turned on and off without adjusting the actual offset per-
centage.
[Modify] This key displays the Y offset percentage in the Reference Display. Use
the knob to adjust the offset. The Channel 2 display reflects the offset as
it is adjusted while the Reference display shows the actual offset. The
offset ranges from -105.00% to 105.00% of full scale. The offset
percentage does not change with sensitivity - it is an output
function. To return the Reference Display to its original display, press
the desired reference display key ([Phase], [Freq], [Ampl], [Harm #] or
[Aux Out]).
[Auto Offset] Pressing this key automatically sets the Y offset percentage to offset the
Y output to zero.
4-16
Front Panel
[Expand] Pressing this key selects the Y Expand. The expand can be 1 (no
expand), 10 or 100. If the expand is 10 or 100, the Expand indicator
below the display will turn on. The output can never exceed full scale
when expanded. For example, if an output is 10% of full scale, the
largest expand (with no offset) which does not overload is 10. An output
expanded beyond full scale will be overloaded.
Short Time Constant Limitations

A short time constant places a limit on the total amount of DC gain
(reserve plus expand) available. If the time constant is short, the filter
slope low and the dynamic reserve high, then increasing the expand may
change the time constant. See the table of time constants and DC gains
in the Gain and Time Constant section.
4-17
Front Panel
Reference
[Phase] Pressing this key displays the reference phase shift in the Reference
display. The knob may be used to adjust the phase. The phase shift
ranges from -180° to +180° with 0.01° resolution.
When using an external reference, the reference phase shift is the phase
between the external reference and the digital sine wave which is multi-
plying the signal in the PSD. This is also the phase between the sine
output and the digital sine wave used by the PSD in either internal or
external reference mode. Changing this phase shift only shifts internal
sine waves. The effect of this phase shift can only be seen at the lock-in
outputs X, Y and θ. R is phase independent.
Auto Phase
Pressing [AUTO PHASE] will adjust the reference phase shift so that the
measured signal phase is 0°. This is done by subtracting the present
measured value of θ from the reference phase shift. It will take several
time constants for the outputs to reach their new values. Auto Phase may
not result in a zero phase if the measurement is noisy or changing. If θ is
not stable, Auto Phase will abort.
4-18
Front Panel
[+90°] and [-90°] The [+90°] and [-90°] keys add or subtract 90.000° from the reference
phase shift. The phase does not need to be displayed to use these keys.
Zero Phase
Pressing the [+90°] and [-90°] keys together will set the reference phase
shift to 0.00°.
[Freq] Pressing this key displays the reference frequency in the Reference dis-
play.
If the reference mode is external, then the measured reference frequency

is displayed. The knob does nothing in this case. If the harmonic number
is greater than 1 and the external reference goes above 102 kHz/N
where N is the harmonic number, then the harmonic number is reset to 1.
The reference will always track the external reference signal.
If the reference mode is internal, then the internal oscillator frequency is

displayed. The oscillator frequency may adjusted with the knob. The fre-
quency has 4 1/2 digits or 0.1 mHz resolution, whichever is larger. The
frequency can range from 0.001 Hz to 102.00 kHz. The upper limit is
decreased if the harmonic number is greater than 1. In this case, the
upper limit is 102 kHz/N where N is the harmonic number.
[Ampl] Pressing this key displays the Sine Output Amplitude in the Reference
display. Use the knob to adjust the amplitude from 4 mVrms to 5 Vrms
with 2 mV resolution. The output impedance of the Sine Out is 50Ω. If the
signal is terminated in 50Ω, the amplitude will be half of the programmed
value.
When the reference mode is internal, this is the excitation source provid-
ed by the SR830. When an external reference is used, this sine output
provides a sine wave phase locked to the external reference.
The rear panel TTL Output provides a TTL square wave at the reference
frequency. This square wave is generated by discriminating the zero
crossings of the sine output. This signal can provide a trigger or sync
signal to the experiment when the internal reference source is used. This
signal is also available when the reference is externally provided. In this
case, the TTL Output is phase locked to the external reference.
[Harm #] The SR830 can detect signals at harmonics of the reference frequency.
The SR830 multiplies the input signal with digital sine waves at a multiple
of the reference. Only signals at this harmonic will be detected. Signals
at the original reference frequency are not detected and are attenuated
as if they were noise.
Whenever the harmonic detect number is greater than 1, the HARM#

indicator in the Reference display will flash to remind you that the
SR830 is detecting signals at a multiple of the reference frequency.
Always check the harmonic detect number before making any

measurements.
If the harmonic number is set to N, then the internal reference fre-
4-19
Front Panel
quency is limited to 102 kHz/N.
If an external reference is used and the reference frequency

exceeds 102 kHz/N, then N is reset to 1. The SR830 will always track
the external reference.
Pressing this key displays the harmonic number in the Reference dis-
play. The harmonic number may be adjusted using the knob. Harmonics
up to 19999 times the reference can be detected as long as the harmonic
frequency does not exceed 102 kHz. An attempt to increase the harmon-
ic frequency above 102 kHz will display the message 'hAr ovEr' indicat-
ing harmonic number over range.
[Source] This key selects the reference mode. The normal mode is External refer-
ence (no indicator). The Internal mode is indicated by the INTERNAL led.
When the reference source is External, the SR830 will phase lock to the
external reference provided at the Reference Input BNC. The SR830 will
lock to frequencies between 0.001 Hz and 102.0 kHz. Use the [Freq] key
to display the external frequency.
When the reference source is Internal, the SR830's synthesized internal

reference is used as the reference. The Reference Input BNC is ignored
in this case. In this mode, the Sine Out or TTL Sync Out provides the
excitation for the measurement. Use the [Freq] key to display and adjust
the frequency.
[Trig] This key selects the external reference input trigger mode.
When either POS EDGE or NEG EDGE is selected, the SR830 locks to
the selected edge of a TTL square wave or pulse train. For reliable oper-
ation, the TTL signal should exceed 3.5 V when high and be less then
0.5 V when low. The input is directed past the analog discriminator and is
DC coupled into a TTL input gate. This input mode should be used when-
ever possible since it is less noise prone than the sine wave discrimina-
tor.
For very low frequencies (<1 Hz), a TTL reference MUST be used.
SINE input mode locks the SR830 to the rising zero crossings of an
analog signal at the Reference Input BNC. This signal should be a clean
sine wave at least 200 mVpk in amplitude. In this input mode, the
Reference Input is AC coupled (above 1 Hz) with an input impedance of
1 MΩ.
Sine reference mode can not be used at frequencies far below 1 Hz.
At very low frequencies, the TTL input modes must be used.
UNLOCK The UNLOCK indicator turns on if the SR830 can not lock to the external
reference.
4-20
Front Panel
setup the SR830 to measure the input signal.
1.Press [AUTO GAIN] to set the sensitivity.
2.Press [AUTO RESERVE].
3.Adjust the time constant and roll-off until there is no Time Constant
overload.
4.Press [AUTO PHASE] if desired.
5.Repeat if necessary.
At very low frequencies, the auto functions may not function properly.
This is because very low frequency signals overload very infrequently
and the time constants used tend to be very long.
4-22
Front Panel
Setup
[Save] Nine amplifier setups may be stored in non-volatile memory.To save a

setup, press [Save] to display the buffer number (1..9) in the CH2 dis-
play. Use the knob to select the desired buffer number. Press [Save]
again to store the setup in the buffer, or any other key to abort the save
process.
The message 'SAvE n donE' is displayed if the setup is successfully

saved. The message 'SAve not donE' is displayed if the save process is
aborted.
[Recall] Nine amplifier setups may be stored in non-volatile memory.To recall a

setup, press [Recall] to display the buffer number (1..9) in the CH2 dis-
play. Use the knob to select the desired buffer number. Press [Recall]
again to recall the setup in the buffer, or any other key to abort the
recall process. When a setup is recalled, any data presently in the data
buffer is lost.
The message 'rcal n donE' is displayed if the setup is successfully

recalled. The message 'rcal not donE' is displayed if the recall process is
aborted. The message 'rcal dAtA Err' is displayed if the recalled setup is
not valid. This is usually because a setup has never been saved into the
selected buffer.
[Aux Out] The 4 Aux Outputs may be programmed from the front panel. Press
[Aux Out] until the desired output (1-4) is displayed in the Reference dis-
play. The AxOut indicators below the display indicate which output (1-4)
is displayed. The knob may then be used to adjust the output level from
-10.5V to +10.5V. Press [Phase], [Freq], [Ampl] or [Harm#] to return the
display to normal.
4-23
Front Panel
Interface
[Setup] Pressing the [Setup] key cycles through GPIB/RS232, ADDRESS,

BAUD, PARITY and QUEUE. In each case, the appropriate parameter is
displayed in the Reference display and the knob is used for adjustment.
Press [Phase], [Freq], [Ampl], [Harm#] or [Aux Out] to return the display
to normal and leave Setup.
GPIB/RS232 The SR830 only outputs data to one interface at a time. Commands may
be received over both interfaces but responses are directed only to the
selected interface. Make sure that the selected interface is set correctly
before attempting to program the SR830 from a computer. The first com-
mand sent by any program should be to set the output to the correct
interface.
Setup GPIB/RS232 displays the output interface. Use the knob to select
GPIB or RS232.
ADDRESS Setup ADDRESS displays the GPIB address. Use the knob to select an
address from 0 to 30.
BAUD Setup BAUD displays the RS232 baud rate. Use the knob to adjust the
baud rate from 300 to 19200 baud.
PARITY Setup PARITY displays the RS232 parity. Use the knob to select Even,
Odd or None.
QUEUE The last 256 characters received by the SR830 may be displayed to help
find programming errors. Setup QUEUE will display 6 characters (2 per
display) in hexadecimal (see below). Turn the knob left to move farther
back in the buffer, turn the knob right to move towards the most recently
received characters. A '.' is displayed to indicate the ends of the buffer.
All characters are changed to upper case, spaces are removed, and
command delimiters are changed to linefeeds (0A).
To leave this display, press [Setup] to return to GPIB/RS232 before

pressing [Phase], [Freq], [Ampl], [Harm#] or [Aux Out] to return the dis-
play to normal and leave Setup.
4-24
Front Panel
Hex ASCII Hex ASCII

2A ❋ 34 4
2B + 35 5
2C , 36 6
2D - 37 7
2E . 38 8
30 0 39 9
31 1 3B ;
32 2 3F ?
33 3
Hex ASCII Hex ASCII

0A linefeed 50 P
41 A 51 Q
42 B 52 R
43 C 53 S
44 D 54 T
45 E 55 U
46 F 56 V
47 G 57 W
48 H 58 X
49 I 59 Y
4A J 5A Z
4B K
4C L
4D M
4E N
4F O
[Local] When a host computer places the unit in the REMOTE state, no keypad
input or knob adjustment is allowed. The REMOTE indicator is on above
the [Local] key. To return to front panel operation, press the [Local] key.
REMOTE This led is on when the front panel is locked out by a computer interface.
No front panel adjustments may be made.
SRQ This indicator is on whenever a GPIB Service Request is generated by

the SR830. SRQ stays on until a serial poll is completed.
ACTIVE This indicator flashes when there is activity on the computer interface.
ERROR Flashes whenever there is a computer interface error such as an illegal

command or out of range parameter is received.
4-25
Front Panel
WARNING MESSAGES
The SR830 displays various warning messages whenever the operation of the instrument is not obvious. The
two tone warning alarm sounds when these messages are displayed.
Display Warning Message Meaning
LOCL LOut LOCAL LOCKOUT If the computer interface has placed the unit in the REMOTE
state, indicated by the REMOTE led, then the keys and the knob
are disabled. Attempts to change the settings from the front
panel will display this message.
IGAn chG IGAIN CHANGE Indicates that the current conversion gain has been changed to
1 MΩ as a result of changing the sensitivity. Sensitivities from
20 nA to 1 µA require 1 MΩ current gain.
tc chnG TC CHANGE Indicates that the time constant has been changed, either by
increasing the detection frequency from below 200 Hz to above
200 Hz, or by changing the sensitivity, dynamic reserve, filter
slope, or expand.
hAr ovEr HARMONIC OVER An attempt to increase the harmonic detect frequency above
102 kHz will display this message.
tc ovEr TC OVER Indicates that the time constant is too long (>1s) for Auto Gain to
run.
PhAS bAd PHASE BAD Indicates that the phase is unstable and Auto Phase will not run.
rcal dAtA Err RECALL DATA ERR This message is displayed if the recalled setup is not valid. This
is usually because a setup has never been saved into the select-
ed buffer.
undr UNDR Indicates unit may not be precisely locked at very low frequency.
4-26
REAR PANEL
Power Entry Module The power entry module is used to fuse the AC line voltage input, select
the line voltage, and block high frequency noise from entering or exiting
the instrument. Refer to the first page of this manual for instructions on
selecting the correct line voltage and fuse.
IEEE-488 Connector The 24 pin IEEE-488 connector allows a computer to control the SR830
via the IEEE-488 (GPIB) instrument bus. The address of the instrument
is set with the [Setup] key.
RS232 Connector The RS232 interface connector is configured as a DCE (transmit on pin
3, receive on pin 2). The baud rate and parity are programmed with the
[Setup] key. To connect the SR830 to a PC serial adapter, which is usu-
ally a DTE, use a straight thru serial cable.
AUX IN 1-4 (A/D Inputs) These are auxiliary analog inputs which can be digitized by the SR830.
The range is -10.5V to +10.5V and the resolution is 16 bits (1/3 mV). The
input impedance is 1 MΩ.
These inputs may be displayed on the CH1 and CH2 displays. These
inputs allow signals other than the lock-in outputs to be acquired (and
stored). Furthermore, ratio quantities such as X/Aux1 may be displayed
(and stored).
AUX OUT 1-4 (D/A Outputs) These are auxiliary analog outputs. The range is -10.5V to +10.5V and
the resolution is 1 mV. The output impedance is <1Ω and the output cur-
rent is limited to 10 mA.
These outputs may be programmed from the front panel ([Aux Out])or via
the computer interfaces.
X and Y The X and Y lock-in outputs are always available at these connectors.
The bandwidth of these outputs is 100 kHz. A full scale input signal will
generate ±10V at these outputs. The output impedance is <1Ω and the
output current is limited to 10 mA.
4-27
Rear Panel
These outputs are affected by the X and Y offsets and expands. The
actual outputs are
X Output = (X/sensitivity - offset)xExpandx10V

Y Output = (Y/sensitivity - offset)xExpandx10V
where the offset is a percentage of full scale and the expand is an integer
from 1, 10 or 100. The offsets and expand are set from the front panel.
MONITOR OUT This BNC provides a buffered output from the signal amplifiers and prefil-
ters. This is the signal just before the A/D converter and PSD. The output
impedance is <1Ω and the output current is limited to 10 mA.
The gain from the signal input to the monitor output is the overall gain
minus the dynamic reserve minus 3dB. The overall gain is 10V divided
by the sensitivity. The actual dynamic reserve is specified in the descrip-
tion of the [Reserve] key. For example, if the sensitivity is 10 mV, the
gain is 60dB. If the dynamic reserve is 20dB, then the gain from the input
to the monitor output is 60-20-3=37dB or a gain of 71. A 10 mV (rms)
input will result in a .7 Vrms or1 Vpk output. The gain is only accurate to
about 1.5dB or 20%.
This output is useful for determining the cause of input overloads and the
effects of prefiltering. However, because the analog gain never exceeds
2000, very small signals may not be amplified enough to viewed at the
monitor output.
TRIG IN This TTL input may be used to trigger stored data samples and/or to start
data acquisition. If Trigger Start is selected, then a rising edge will start
data storage. If the sample rate is also Trigger, then samples are record-
ed at every subsequent trigger. (The first trigger starts the scan and
takes the first data point, subsequent triggers record the rest of the data
points.) When the sample rate is set to Trigger, samples are recorded
whenever there is a rising edge at the Trigger input. The maximum
sample rate is 512 Hz. Data storage is available through the computer
interface only.
TTL OUT This output is the TTL sync output for the internal oscillator. The output is
a square wave whose edges are linked to the sine wave zero crossings.
This is useful when the sine output amplitude is small and a synchronous
trigger is required (to a scope for example). This output is active even
when locked to an external reference.
PREAMP CONNECTOR This 9 pin "D" connector provides power and control signals to external
preamplifiers such as the SR550 and SR552. The power connections are
described below.
Pin Voltage
1 +20V
2 +5V
6 -20V
7 Signal Ground
8 Ground
4-28
Rear Panel
Using SRS Preamps When using either the SR550 or SR552, connect the power cable (stan-
dard 9 pin D connectors) from the preamp to the rear panel preamp con-
nector on the SR830. Use BNC cables to connect the A output from the
preamp to the A input of the SR830. The B output from the preamp
(preamp ground) may be connected to the B input of the SR830. In this
case, use A-B as the input configuration. Be sure to twist the A and B
cables so that there is no differential noise pickup between the cables.
The SR550 and SR552 are AC coupled from 1 Hz to

100 kHz. Set the SR830 to AC coupled since the signal must be above
1 Hz. The SR550 has an input impedance of 100 MΩ, the SR552 has
100 kΩ.
The SR830 does NOT compensate for the gain of the

preamp. The SR830 sets both preamps to their maximum gains.
Measurements made by the SR830 with a preamp need to be divided by
the gain of the preamp. The SR550 has a gain of 10 and the SR552 has
a gain of 100.
4-29
Rear Panel
4-30
REMOTE PROGRAMMING
INTRODUCTION
The SR830 DSP Lock-in Amplifier may be remote- completed.

ly programmed via either the RS232 or GPIB To help find program errors, the SR830 can dis-
(IEEE-488) interfaces. Any computer supporting play its receive buffer on the displays. Use the
one of these interfaces may be used to program [Setup] key to access the QUEUE display. The
the SR830. Both interfaces are receiving at all last 256 characters received by the SR830 may be
times, however, the SR830 will send responses displayed in hexadecimal ASCII. See the
to only one interface. Specify the output inter- OPERATION section for a complete description.
face with the [Setup] key or use the OUTX com-
mand at the beginning of every program to COMMAND SYNTAX
direct the responses to the correct interface.
Communications with the SR830 uses ASCII char-
COMMUNICATING WITH GPIB acters. Commands may be in either UPPER or
lower case and may contain any number of
The SR830 supports the IEEE-488.1 (1978) inter- embedded space characters. A command to the
face standard. It also supports the required SR830 consists of a four character command
common commands of the IEEE-488.2 (1987) mnemonic, arguments if necessary, and a com-
standard. Before attempting to communicate with mand terminator. The terminator must be a line-
the SR830 over the GPIB interface, the SR830's feed <lf> or carriage return <cr> on RS232, or a
device address must be set. The address is set linefeed <lf> or EOI on GPIB. No command pro-
with the [Setup] key and may be set between 1 cessing occurs until a command terminator is
and 30. received. Commands function identically on GPIB
and RS232 whenever possible. Command mne-
COMMUNICATING WITH RS232 monics beginning with an asterisk "❊" are IEEE-
488.2 (1987) defined common commands. These
The SR830 is configured as a DCE ( transmit on commands also function identically on RS232.
pin 3, receive on pin 2) device and supports CTS/ Commands may require one or more parameters.
DTR hardware handshaking. The CTS signal (pin Multiple parameters are separated by commas (,).
5) is an output indicating that the SR830 is ready,
while the DTR signal (pin 20) is an input that is Multiple commands may be sent on one command
used to control the SR830's data transmission. If line by separating them with semicolons (;). The
desired, the handshake pins may be ignored and a difference between sending several commands on
simple 3 wire interface (pins 2,3 and 7) may be the same line and sending several independent
used. The RS232 interface baud rate and parity commands is that when a command line is parsed
must be set. These are set with the [Setup] key. and executed, the entire line is executed before
The RS232 word length is always 8 bits. any other device action proceeds.
STATUS INDICATORS AND QUEUES There is no need to wait between commands. The
SR830 has a 256 character input buffer and pro-
To assist in programming, the SR830 has 4 inter- cesses commands in the order received. If the
face status indicators. The ACTIVE indicator flash- buffer fills up, the SR830 will hold off handshaking
es whenever a character is received or transmitted on the GPIB and attempt to hold off handshaking
over either interface. The ERROR indicator flash- on RS232. Similarly, the SR830 has a 256 charac-
es when an error, such as an illegal command, or ter output buffer to store outputs until the host
parameter out of range, has been detected. The computer is ready to receive. If either buffer over-
REMOTE indicator is on whenever the SR830 is in flows, both buffers are cleared and an error
a remote state (front panel locked out). The SRQ reported.
indicator is on when the SR830 generates a ser-
vice request. SRQ stays on until a serial poll is The present value of a particular parameter may
5-1
Remote Programming
be determined by querying the SR830 for its and LIAS? status query commands may be used
value. A query is formed by appending a question to query the Status Bytes. Since the SR830 pro-
mark "?" to the command mnemonic and omitting cesses one command at a time, the status query
the desired parameter(s) from the command. will not be processed until the previous operation
Values returned by the SR830 are sent as a string is finished. Thus a response to the status query in
of ASCII characters terminated by a carriage itself signals that the previous command is fin-
return <cr> on RS232 and by a line-feed <lf> on ished. The query response may then be checked
GPIB. If multiple queries are sent on one com- for various errors.
mand line (separated by semicolons, of course)
the answers will be returned individually, each with GET (GROUP EXECUTE TRIGGER)
a terminator.
The GPIB interface command GET is the same as
Examples of Command Formats the TRIG command. GET is the same as a trigger
input. GET only has an effect if the sampling rate
FMOD 1 <lf> Set reference source to is triggered or if triggers start a scan.
internal
FREQ 10E3 <lf> Set the internal reference fre-
quency to 10000 Hz (10 kHz)
❊IDN? <lf> Queries the device
identification
STRT <lf> Starts data acquisition
OUTP? 1 <lf> Queries the value of X
INTERFACE READY AND STATUS
The Interface Ready bit (bit 1) in the Serial Poll

Status Byte signals that the SR830 is ready to
receive and execute a command. When a com-
mand is received, this bit is cleared indicating that
an operation is in progress. While the operation is
in progress, no other commands will be pro-
cessed. Commands received during this time are
stored in the buffer to be processed later. Only
GPIB serial polling will generate a response while
a command is in progress. When the command
execution terminates, the Interface Ready bit is set
again and new commands will be processed.
Since most commands execute very quickly, the
host computer does not need to continually check
the Interface Ready bit. Commands may be sent
one after another and they will be processed
immediately.
When using the GPIB interface, serial polling may

be used to check the Interface Ready bit in the
Serial Poll Byte while an operation is in progress.
After the Interface Ready bit becomes set, signal-
ling the completion of the command, then the ERR
or ESB bit may be checked to verify successful
completion of the command.
If the RS232 interface is used, or serial polling is

not available, then the ❊STB?, ❊ESR?, ERRS?,
5-2
Remote Programming
DETAILED COMMAND LIST

The four letter mnemonic in each command sequence specifies the command. The rest of the sequence con-
sists of parameters. Multiple parameters are separated by commas. Parameters shown in { } are optional or
may be queried while those not in { } are required. Commands that may be queried have a question mark in
parentheses (?) after the mnemonic. Commands that may ONLY be queried have a ? after the mnemonic.
Commands that MAY NOT be queried have no ?. Do not send ( ) or { } as part of the command.
The variables are defined as follows.

i, j, k, l, m integers
x, y, z real numbers
f frequency
s string
All numeric variables may be expressed in integer, floating point or exponential formats ( i.e., the number five
can be either 5, 5.0, or .5E1). Strings are sent as a sequence of ASCII characters.
Remember!
All responses are directed only to the selected output interface!
Use the OUTX command to select the correct interface at the beginning of every
program.
5-3
Remote Programming
REFERENCE and PHASE COMMANDS
PHAS (?) {x} The PHAS command sets or queries the reference phase shift. The
parameter x is the phase (real number of degrees). The PHAS x com-
mand will set the phase shift to x. The value of x will be rounded to 0.01°.
The phase may be programmed from -360.00 ≤ x ≤ 729.99 and will be
wrapped around at ±180°. For example, the PHAS 541.0 command will
set the phase to -179.00° (541-360=181=-179). The PHAS? queries the
phase shift.
FMOD (?) {i} The FMOD command sets or queries the reference source. The parame-
ter i selects internal (i=1) or external (i=0).
FREQ (?) {f} The FREQ command sets or queries the reference frequency. The
FREQ? query command will return the reference frequency (in internal or
external mode).
The FREQ f command sets the frequency of the internal oscillator. This
command is allowed only if the reference source is internal. The parame-
ter f is a frequency (real number of Hz). The value of f will be rounded to
5 digits or 0.0001 Hz, whichever is greater. The value of f is limited to
0.001 ≤ f ≤ 102000. If the harmonic number is greater than 1, then the
frequency is limited to nxf ≤ 102 kHz where n is the harmonic number.
RSLP (?) {i} The RSLP command sets or queries the reference trigger when using the
external reference mode. The parameter i selects sine zero crossing
(i=0), TTL rising edge (i=1), , or TTL falling edge (i=2). At frequencies
below 1 Hz, the a TTL reference must be used.
HARM (?) {i} The HARM command sets or queries the detection harmonic. This
parameter is an integer from 1 to 19999. The HARM i command will set
the lock-in to detect at the ith harmonic of the reference frequency. The
value of i is limited by ixf ≤ 102 kHz. If the value of i requires a detection
frequency greater than 102 kHz, then the harmonic number will be set to
the largest value of i such that ixf ≤ 102 kHz.
SLVL (?) {x} The SLVL command sets or queries the amplitude of the sine output.
The parameter x is a voltage (real number of Volts). The value of x will
be rounded to 0.002V. The value of x is limited to 0.004 ≤ x ≤ 5.000.
5-4
Remote Programming
INPUT and FILTER COMMANDS
ISRC (?) {i} The ISRC command sets or queries the input configuration. The parame-
ter i selects A (i=0), A-B (i=1), I (1 MΩ) (i=2) or I (100 MΩ) (i=3).
Changing the current gain does not change the instrument sensitivity.
Sensitivities above 10 nA require a current gain of 1 MΩ. Sensitivities
between 20 nA and 1 µA automatically select the 1 MΩ current gain. At
sensitivities below 20 nA, changing the sensitivity does not change the
current gain.
IGND (?) {i} The IGND command sets or queries the input shield grounding. The
parameter i selects Float (i=0) or Ground (i=1).
ICPL (?) {i} The ICPL command sets or queries the input coupling. The parameter i
selects AC (i=0) or DC (i=1).
ILIN (?) {i} The ILIN command sets or queries the input line notch filter status. The
parameter i selects Out or no filters (i=0), Line notch in (i=1), 2xLine
notch in (i=2) or Both notch filters in (i=3).
5-5
Remote Programming
GAIN and TIME CONSTANT COMMANDS
SENS (?) {i} The SENS command sets or queries the sensitivity. The parameter i
selects a sensitivity below.
i sensitivity i sensitivity
0 2 nV/fA 13 50 µV/pA
1 5 nV/fA 14 100 µV/pA
2 10 nV/fA 15 200 µV/pA
3 20 nV/fA 16 500 µV/pA
4 50 nV/fA 17 1 mV/nA
5 100 nV/fA 18 2 mV/nA
6 200 nV/fA 19 5 mV/nA
7 500 nV/fA 20 10 mV/nA
8 1 µV/pA 21 20 mV/nA
9 2 µV/pA 22 50 mV/nA
10 5 µV/pA 23 100 mV/nA
11 10 µV/pA 24 200 mV/nA
12 20 µV/pA 25 500 mV/nA
26 1 V/µA
RMOD (?) {i} The RMOD command sets or queries the reserve mode. The parameter i
selects High Reserve (i=0), Normal (i=1) or Low Noise (minimum) (i=2).
See the description of the [Reserve] key for the actual reserves for each
sensitivity.
OFLT (?) {i} The OFLT command sets or queries the time constant. The parameter i
selects a time constant below.
i time constant i time constant

0 10 µs 10 1s
1 30 µs 11 3s
2 100 µs 12 10 s
3 300 µs 13 30 s
4 1 ms 14 100 s
5 3 ms 15 300 s
6 10 ms 16 1 ks
7 30 ms 17 3 ks
8 100 ms 18 10 ks
9 300 ms 19 30 ks
Time constants greater than 30s may NOT be set if the

harmonic x ref. frequency (detection frequency) exceeds 200 Hz. Time
constants shorter than the minimum time constant (based upon the filter
slope and dynamic reserve) will set the time constant to the minimum
allowed time constant. See the Gain and TIme Constant operation
section.
OFSL (?) {i} The OFSL command sets or queries the low pass filter slope. The
parameter i selects 6 dB/oct (i=0), 12 dB/oct (i=1), 18 dB/oct (i=2) or
24 dB/oct (i=3).
5-6
Remote Programming
SYNC (?) {i} The SYNC command sets or queries the synchronous filter status. The
parameter i selects Off (i=0) or synchronous filtering below 200 Hz (i=1).
Synchronous filtering is turned on only if the detection frequency (refer-
ence x harmonic number) is less than 200 Hz.
5-7
Remote Programming
DISPLAY and OUTPUT COMMANDS
DDEF (?) i {, j, k} The DDEF command selects the CH1 and CH2 displays. The parameter
i selects CH1 (i=1) or CH2 (i=2) and is required. The DDEF i, j, k com-
mand sets display i to parameter j with ratio k as listed below.
CH1 (i=1) CH2 (i=2)

j display j display
0 X 0 Y
1 R 1 θ
2 X Noise 2 Y Noise
3 Aux In 1 3 Aux In 3
k ratio k ratio
0 none 0 none
The DDEF? i command queries the display and ratio of display i. The
returned string contains both j and k separated by a comma. For exam-
ple, if the DDEF? 1 command returns "1,0" then the CH1 display is R
with no ratio.
FPOP (?) i {, j} The FPOP command sets or queries the front panel (CH1 and CH2)
output sources. The parameter i selects CH1 (i=1) or CH2 (i=2) and is
required. The FPOP i, j command sets output i to quantity j where j is
listed below.
CH1 (i=1) CH2 (i=2)

j output quantity j output quantity
0 CH 1 Display 0 CH 2 Display
1 X 1 Y
OEXP (?) i {, x, j} The OEXP command sets or queries the output offsets and expands.
The parameter i selects X (i=1), Y (i=2) or R (i=3) and is required. The
parameter x is the offset in percent (-105.00 ≤ x ≤ 105.00). The parame-
ter j selects no expand (j=0), expand by 10 (j=1) or 100 (j=2). The OEXP
i, x, j command will set the offset and expand for quantity i. This com-
mand requires BOTH x and j. The OEXP? i command queries the offset
and expand of quantity i. The returned string contains both the offset and
expand separated by a comma. For example, if the OEXP? 2 command
returns "50.00,1" then the Y offset is 50.00% and the Y expand is 10.
Setting an offset to zero turns the offset off. Querying an offset which is
off will return 0% for the offset value.
AOFF i The AOFF i command automatically offsets X (i=1), Y (i=2) or R (i=3) to

zero. The parameter i is required. This command is equivalent to press-
ing the [Auto Offset] keys.
5-8
Remote Programming
AUX INPUT and OUTPUT COMMANDS
OAUX? i The OAUX? command queries the Aux Input values. The parameter i
selects an Aux Input (1, 2, 3 or 4) and is required. The Aux Input voltages
are returned as ASCII strings with units of Volts. The resolution is
1/3 mV. This command is a query only command.
AUXV (?) i {, x} The AUXV command sets or queries the Aux Output voltage when the
output. The parameter i selects an Aux Output (1, 2, 3 or 4) and is
required. The parameter x is the output voltage (real number of Volts)
and is limited to -10.500 ≤ x ≤ 10.500. The output voltage will be set to
the nearest mV.
5-9
Remote Programming
SETUP COMMANDS
OUTX (?) {i} The OUTX command sets the output interface to RS232 (i=0) or GPIB
(i=1). The OUTX i command should be sent before any query com-
mands to direct the responses to the interface in use.
OVRM i In general, every GPIB interface command will put the SR830 into the
REMOTE state with the front panel deactivated. To defeat this feature,
use the OVRM 1 command to overide the GPIB remote. In this mode, the
front panel is not locked out when the unit is in the REMOTE state. The
OVRM 0 command returns the unit to normal remote operation.
KCLK (?) {i} The KCLK command sets or queries the key click On (i=1) or Off (i=0)
state.
ALRM (?) {i} The ALRM command sets or queries the alarm On (i=1) or Off (i=0)
state.
SSET i The SSET i command saves the lock-in setup in setting buffer i (1≤i≤9).
The setting buffers are retained when the power is turned off.
RSET i The RSET i command recalls the lock-in setup from setting buffer i
(1≤i≤9). Interface parameters are not changed when a setting buffer is
recalled with the RSET command. If setting i has not been saved prior to
the RSET i command, then an error will result.
5-10
Remote Programming
AUTO FUNCTIONS
AGAN The AGAN command performs the Auto Gain function. This command is
the same as pressing the [Auto Gain] key. Auto Gain may take some
time if the time constant is long. AGAN does nothing if the time constant
is greater than 1 second. Check the command execution in progress bit
in the Serial Poll Status Byte (bit 1) to determine when the function is
finished.
ARSV The ARSV command performs the Auto Reserve function. This com-
mand is the same as pressing the [Auto Reserve] key. Auto Reserve
may take some time. Check the command execution in progress bit in
the Serial Poll Status Byte (bit 1) to determine when the function is
finished.
APHS The APHS command performs the Auto Phase function. This command
is the same as pressing the [Auto Phase] key. The outputs will take many
time constants to reach their new values. Do not send the APHS com-
mand again without waiting the appropriate amount of time. If the phase
is unstable, then APHS will do nothing. Query the new value of the phase
shift to see if APHS changed the phase shift.
AOFF i The AOFF i command automatically offsets X (i=1), Y (i=2) or R (i=3) to

zero. The parameter i is required. This command is equivalent to press-
ing the [Auto Offset] keys.
5-11
Remote Programming
DATA STORAGE COMMANDS
Data Storage
The SR830 can store up to 16383 points from both the Channel 1 and Channel 2 displays in an internal data
buffer. The data buffer is NOT retained when the power is turned off. The data buffer is accessible only via
the computer interface.
Configure the displays to show the desired quantity (with appropriate ratio, offset and expand). The data
buffer stores the quantities which are displayed. Only quantities which are displayed on the CH1 or CH2 dis-
plays can be stored. Frequency, for example, can not be stored.
Data Points and Bins

Data points stored in the buffer are sometimes referred to by their bin position within the buffer. The oldest
data point is bin0, the next point is bin1, etc. A buffer with N points numbers them from 0 to N-1.
Sample Rate
The Sample Rate can be varied from 512 Hz down to 62.5 mHz (1 point every 16 sec). The sample rate sets
how often points are added to the storage buffer. Both displays are sampled at the same rate (and at the
same times).
In addition to the internal sample rates, samples can be triggered by an external TTL trigger. In this mode, a
sample is recorded within 2 ms of a rising edge trigger on the rear panel Trigger input. Triggers which occur
faster than 512 Hz are ignored.
Storage Time
The buffer holds 16383 samples taken at the sample rate. The entire storage time is 16383 divided by the
sample rate.
End of Scan
When the buffer becomes full, data storage can stop or continue.
The first case is called 1 Shot (data points are stored for a single buffer length). At the end of the buffer, data
storage stops and an audio alarm sounds.
The second case is called Loop. In this case, data storage continues at the end of the buffer. The data buffer
will store 16383 points and start storing at the beginning again. The most recent 16383 points will be con-
tained in the buffer. Once the buffer has looped around, the oldest point (at any time) is at bin#0 and the most
recent point is at bin#16382.
The default mode is Loop.
Starting and Stopping a Scan

The STRT, PAUS and REST commands are used to control data storage. Basically, the STRT command
starts data storage after a reset or pause. The PAUS command pauses data storage but does not reset the
buffer. The REST stops data storage and resets the buffer data.
In addition, the rear panel Trigger input can be used to start data storage. To select this mode, use the TSTR
command. In this mode, a rising TTL trigger will act the same as the STRT command. The sample rate can
be either internal or Triggered. In the first case, the trigger starts the storage and data is sampled at the pro-
grammed sample rate (up to 512 Hz). In the latter case, the first trigger will start the storage and data will be
sampled at every subsequent trigger.
5-12
Remote Programming
Aliasing Effects
In any sampled data stream, it is possible to sample a high frequency signal such that it will appear to be a
much lower frequency. This is called aliasing.
For example, suppose the lock-in is detecting a signal near 1 Hz with a relatively short time constant. The X
output will have a DC component and a 2 Hz component (2xf). If the sample rate is 2 Hz, then the samples
may be taken as illustrated below.
1 second
The samples represent a sine wave much slower than 2 Hz that isn't actually present in the output! In this
case, a much higher sampling rate will solve the problem.
Aliasing occurs whenever the output signal being sampled contains signals at frequencies greater
than 1/2 the sample rate. The effect is most noticeable when trying to sample an output frequency at an inte-
ger multiple of the sample rate (as above). The above aliasing problem will be the same for a 1 kHz output
(500 times the sample rate) as for the 2 Hz output.
Generally, the highest possible sample rate should be used given the desired storage time. The lock-in time
constant and filter slope should be chosen to attenuate signals at frequencies higher than 1/2 the sample rate
as much as possible.
SRAT (?) {i} The SRAT command sets or queries the data sample rate. The parame-
ter i selects the sample rate listed below.
i quantity i quantity
0 62.5 mHz 7 8 Hz
1 125 mHz 8 16 Hz
2 250 mHz 9 32 Hz
3 500 mHz 10 64 Hz
4 1 Hz 11 128 Hz
5 2 Hz 12 256 Hz
6 4 Hz 13 512 Hz
14 Trigger
SEND (?) {i} The SEND command sets or queries the end of buffer mode. The param-
eter i selects 1 Shot (i=0) or Loop (i=1). If Loop mode is used, make sure
to pause data storage before reading the data to avoid confusion about
which point is the most recent.
TRIG The TRIG command is the software trigger command. This command
has the same effect as a trigger at the rear panel trigger input.
TSTR (?) {i} The TSTR command sets or queries the trigger start mode. The parame-
ter i=1 selects trigger starts the scan and i=0 turns the trigger start fea-
ture off.
STRT The STRT command starts or resumes data storage. STRT is ignored if
storage is already in progress.
5-13
Remote Programming
PAUS The PAUS command pauses data storage. If storage is already paused
or reset then this command is ignored.
REST The REST command resets the data buffers. The REST command can
be sent at any time - any storage in progress, paused or not, will be
reset. This command will erase the data buffer.
5-14
Remote Programming
DATA TRANSFER COMMANDS
OUTP ? i The OUTP? i command reads the value of X, Y, R or θ. The parameter

i selects X (i=1), Y (i=2), R (i=3) or θ (i=4). Values are returned as ASCII
floating point numbers with units of Volts or degrees. For example, the
response might be "-1.01026". This command is a query only command.
OUTR ? i The OUTR? i command reads the value of the CH1 or CH2 display.
The parameter i selects the display (i=1 or 2). Values are returned as
ASCII floating point numbers with units of the display. For example, the
response might be "-1.01026". This command is a query only command.
SNAP ? i,j {,k,l,m,n} The SNAP? command records the values of either 2, 3, 4, 5 or 6 param-
eters at a single instant. For example, SNAP? is a way to query values of
X and Y (or R and θ) which are taken at the same time. This is important
when the time constant is very short. Using the OUTP? or OUTR? com-
mands will result in time delays, which may be greater than the time con-
stant, between reading X and Y (or R and θ).
The SNAP? command requires at least two parameters and at most six
parameters. The parameters i, j, k, l, m, n select the parameters below.
i,j,k,l,m,n parameter
1 X
2 Y
3 R
4 θ
5 Aux In 1
6 Aux In 2
7 Aux In 3
8 Aux In 4
9 Reference Frequency
10 CH1 display
11 CH2 display
The requested values are returned in a single string with the values sep-
arated by commas and in the order in which they were requested. For
example, the SNAP?1,2,9,5 will return the values of X, Y, Freq and
Aux In 1. These values will be returned in a single string such as
"0.951359,0.0253297,1000.00,1.234".
The first value is X, the second is Y, the third is f, and the fourth is
Aux In 1.
The values of X and Y are recorded at a single instant. The values of R

and θ are also recorded at a single instant. Thus reading X,Y OR R,θ
yields a coherent snapshot of the output signal. If X,Y,R and θ are all
read, then the values of X,Y are recorded approximately 10µs apart from
R,θ. Thus, the values of X and Y may not yield the exact values of R and
θ from a single SNAP? query.
The values of the Aux Inputs may have an uncertainty of up to 32µs. The
frequency is computed only every other period or 40 ms, whichever is
longer.
5-15
Remote Programming
The SNAP? command is a query only command. The SNAP? command

is used to record various parameters simultaneously, not to transfer data
quickly.
OAUX? i The OAUX? command reads the Aux Input values. The parameter i
selects an Aux Input (1, 2, 3 or 4) and is required. The Aux Input voltages
are returned as ASCII strings with units of Volts. The resolution is
1/3 mV. This command is a query only command.
SPTS ? The SPTS? command queries the number of points stored in the buffer.
Both displays have the same number of points. If the buffer is reset, then
0 is returned. Remember, SPTS? returns N where N is the number of
points - the points are numbered from 0 (oldest) to N-1 (most recent).
The SPTS? command can be sent at any time, even while storage is in
progress. This command is a query only command.
TRCA ? i, j, k The TRCA? command queries the points stored in the Channel i buffer.
The values are returned as ASCII floating point numbers with the units of
the trace. Multiple points are separated by commas and the final point is
followed by a terminator. For example, the response with two points
might be "-1.234567e-009,+7.654321e-009,".
The parameter i selects the display buffer (i=1, 2) and is required. Points
are read from the buffer starting at bin j (j≥0). A total of k bins are read
(k≥1). To read a single point, set k=1. Both j and k are required. If j+k
exceeds the number of stored points (as returned by the SPTS? query),
then an error occurs. Remember, SPTS? returns N where N is the total
number of bins - the TRCA? command numbers the bins from 0 (oldest)
to N-1 (most recent). If data storage is set to Loop mode, make sure that
storage is paused before reading any data. This is because the points
are indexed relative to the most recent point which is continually
changing.
TRCB ? i, j, k The TRCB? command queries the points stored in the Channel i buffer.
The values are returned as IEEE format binary floating point numbers
(with the units of the trace). There are 4 bytes per point. Multiple points
are not separated by any delimiter. The bytes can be read directly into a
floating point array (in most languages).
Do not query the IFC (no command in progress) status bit after sending
the TRCB command. This bit will not be set until the transfer is complete.
When using the GPIB interface, EOI is sent with the final byte. The points
must be read using a binary transfer (see your GPIB interface card soft-
ware manual). Make sure that the software is configured to NOT termi-
nate reading upon receipt of a CR or LF.
When using the RS232 interface, the word length must be 8 bits. The
points must be read as binary bytes (no checking for linefeeds, carriage
returns or other control characters). Most serial interface drivers are
designed for ASCII text only and will not work here. The data transfer does
not pause between bytes. The receiving interface must always be ready
to receive the next byte. In general, using binary transfers on the RS232
5-16
Remote Programming
interface is not recommended.
The parameter i selects the display buffer (i=1, 2) and is required. Points
are read from the buffer starting at bin j (j≥0). A total of k bins are read
(k≥1) for a total transfer of 4k bytes. To read a single point, set k=1. Both
j and k are required. If j+k exceeds the number of stored points (as
returned by the SPTS? query), then an error occurs. Remember, SPTS?
returns N where N is the total number of bins - the TRCB? command
numbers the bins from 0 (oldest) to N-1 (most recent). If data storage is
set to Loop mode, make sure that storage is paused before reading any
data. This is because the points are indexed relative to the most recent
point which is continually changing.
TRCL ? i, j, k The TRCL? command queries the points stored in the Channel i buffer.
The values are returned in a non-normalized floating point format (with
the units of the trace). There are 4 bytes per point. Multiple points are not
separated by any delimiter. The bytes CANNOT be read directly into a
floating point array.
Each point consists of four bytes. Byte 0 is the LSB and Byte 3 is the
MSB. The format is illustrated below.
16 bits 16 bits
0 exp mantissa
byte3 byte2 byte1 byte0
The mantissa is a signed 16 bit integer (-32768 to 32767). The exponent

is a signed integer whose value ranges from 0 to 248 (thus byte 3 is
always zero). The value of a data point is simply,
value = m x 2 (exp-124)
where m is the mantissa and exp is the exponent.
The data within the SR830 is stored in this format. Data transfers using
this format are faster than IEEE floating point format. If data transfer
speed is important, the TRCL? command should be used.
Do not query the IFC (no command in progress) status bit after sending
the TRCL command. This bit will not be set until the transfer is complete.
When using the GPIB interface, EOI is sent with the final byte. The points
must be read using a binary transfer (see your GPIB interface card soft-
ware manual). Make sure that the software is configured to NOT termi-
nate reading upon receipt of a CR or LF.
When using the RS232 interface, the word length must be 8 bits. The
points must be read as binary bytes (no checking for linefeeds, carriage
returns or other control characters). Most serial interface drivers are
designed for ASCII text only and will not work here. In addition, the data
transfer does not pause between bytes. The receiving interface must
5-17
Remote Programming
always be ready to receive the next byte. In general, using binary transfers on the
RS232 interface is not recommended.
The parameter i selects the display buffer (i=1, 2) and is required. Points are read
starting at bin j (j≥0). A total of k bins are read (k≥1) for a total transfer of 4k bytes. To
read a single point, set k=1. Both j and k are required. If j+k exceeds the number of
stored points (as returned by the SPTS? Query), then an error occurs. Remember,
SPTS? Returns N where N is the total number of bins – the TRCB? command numbers
the bins from 9 (oldest) to N-1 (most recent). If data storage is set to Loop mode, make
sure that storage is paused before reading any data. This is because the points are
indexed relative to the most recent point which is continually changing.
FAST (?) {i} The FAST command sets the data transfer mode on and off. The parameter i selects:
i=0: Off
i=1: On (DOS programs or other dedicated data collection computers)
i=2: On (Windows Operating System Programs)
When the fast transfer mode is on, whenever data is sampled (during a scan), the
values of X and Y are automatically transmitted over GPIB (not available over RS232).
The sample rate sets the frequency of the data transfers. It is important that the
receiving interface be able to keep up with the transfers.
To use the FAST2 mode, a ROM version of 1.06 or higher is required. The FAST2
version uses the lock-in transmit queue to buffer the GPIB data being sent to the host.
Since the transmit queue can buffer a maximum of 63 X and Y data pairs, the host can
only be diverted for short periods of time (e.g. 120mS at 512Hz sample rate) without
causing the lock-in to "time out" and abort the FAST mode data transfer.
The values of X and Y are transferred as signed integers, 2 bytes long (16 bits). X is
sent first followed by Y for a total of 4 bytes per sample. The values range from -32768
to 32767. The value ±30000 represents ±full scale (i.e. the sensitivity).
Offsets and expands are included in the values of X and Y. The transferred values are
(raw data - offset) x expand. The resulting value must still be a 16 bit integer. The value
±30000 now represents ±full scale divided by the expand factor.
At fast sample rates, it is important that the receiving interface be able to keep up. If the
SR830 finds that the interface is not ready to receive a point, then the fast transfer
mode is turned off. The fast transfer mode may be turned off with the FAST0 command.
The transfer mode should be turned on (using FAST1 or FAST 2) before a scan is
started. Then use the STRD command (see below) to start a scan. After sending the
STRD command, immediately make the SR830 a talker and the controlling interface a
listener. Remember, the first transfer will occur with the first point in the scan. If the
scan is started from the front panel or from a trigger, then make sure that the SR830 is
a talker and the controlling interface a listener BEFORE the scan actually starts.
STRD After using FAST1 or FAST 2 to turn on fast data transfer, use the STRD command to
start the scan. STRD starts a scan after a delay of 0.5 sec. This delay allows the
controlling interface to place itself in the read mode before the first data points are
transmitted. Do not use the STRT command to start the scan. See the programming
examples at the end of this section.
5-18
Remote Programming
INTERFACE COMMANDS
❊RST The ❊RST command resets the SR830 to its default configurations. The
communications setup is not changed. All other modes and settings are
set to their default conditions and values. This command takes some
time to complete. This command resets any data scan in progress. Data
stored in the buffers will be lost.
❊IDN? The ❊IDN? query returns the SR830's device identification string. This
string is in the format
"Stanford_Research_Systems,SR830,s/n00111,ver1.000".
In this example, the serial number is 00111 and the firmware version is
1.000.
LOCL (?) {i} The LOCL command sets the local/remote function. If i=0 the SR830 is
LOCAL, if i=1 the SR830 will go REMOTE, and if i=2 the SR830 will go
into LOCAL LOCKOUT state. The states duplicate the GPIB local/remote
states. In the LOCAL state both command execution and keyboard input
are allowed. In the REMOTE state command execution is allowed but the
keyboard and knob are locked out except for the [LOCAL] key which
returns the SR830 to the LOCAL state. In the LOCAL LOCKOUT state all
front panel operation is locked out, including the [LOCAL] key.
The REMOTE indicator is directly above the [LOCAL] key.
The Overide Remote mode must be set to No in order for the front panel
to be locked out. If Overide Remote is Yes, then the front panel is active
even in the REMOTE state.
OVRM (?) {i} The OVRM command sets or queries the GPIB Overide Remote Yes/No
condition. The parameter i selects No (i=0) or Yes (i=1). When Overide
Remote is set to Yes, then the front panel is not locked out when the unit
is in the REMOTE state. The REMOTE indicator will still be on and the
[LOCAL] key will still return the unit to the Local state.
The default mode is Overide Remote Yes. To lock-out the front panel,
use the OVRM0 command before local lock-out.
TRIG The TRIG command is the software trigger command. This command
has the same effect as a trigger at the rear panel trigger input.
5-19
Remote Programming
STATUS REPORTING COMMANDS
The Status Byte definitions follow this section.
❊CLS The ❊CLS command clears all status registers. The status enable regis-
ters are NOT cleared.
❊ESE (?) {i} {,j} The ❊ESE i command sets the standard event enable register to the
decimal value i (0-255). The ❊ESE i,j command sets bit i (0-7) to j (0 or
1). The ❊ESE? command queries the value (0-255) of the status byte
enable register. The ❊ESE? i command queries the value (0 or 1) of bit i.
❊ESR? {i} The ❊ESR? command queries the value of the standard event status
byte. The value is returned as a decimal number from 0 to 255. The
❊ESR? i command queries the value (0 or 1) of bit i (0-7). Reading the
entire byte will clear it while reading bit i will clear just bit i.
❊SRE (?) {i} {,j} The ❊SRE i command sets the serial poll enable register to the deci-
mal value i (0-255). The ❊SRE i,j command sets bit i (0-7) to j (0 or
1).The ❊SRE? command queries the value (0-255) of the serial poll
enable register. The ❊SRE? i command queries the value (0 or 1) of bit i.
❊STB? {i} The ❊STB? command queries the value of the serial poll status byte.
The value is returned as a decimal number from 0 to 255. The ❊STB? i
command queries the value (0 or 1) of bit i (0-7). Reading this byte has
no effect on its value.
❊PSC (?) {i} The ❊PSC command sets the value of the power-on status clear bit. If
i=1 the power-on status clear bit is set and all status registers and enable
registers are cleared on power up. If i=0 the bit is cleared and the status
enable registers maintain their values at power down. This allows a ser-
vice request to be generated at power up.
ERRE (?) {i} {,j} The ERRE i command sets the error status enable register to the deci-
mal value i (0-255). The ERRE i,j command sets bit i (0-7) to j (0 or 1).
The ERRE? command queries the value (0-255) of the error status
enable register. The ERRE? i command queries the value (0 or 1) of bit i.
ERRS? {i} The ERRS? command queries the value of the error status byte. The
value is returned as a decimal number from 0 to 255. The ERRS? i com-
mand queries the value (0 or 1) of bit i (0-7). Reading the entire byte will
clear it while reading bit i will clear just bit i.
LIAE (?) {i} {,j} The LIAE command sets the lock-in (LIA) status enable register to the
decimal value i (0-255). The LIAE i,j command sets bit i (0-7) to j (0 or 1).
The LIAE? command queries the value of the LIA status enable register.
The LIAE? i command queries the value (0 or 1) of bit i.
LIAS? {i} The LIAS? command queries the value of the lock-in (LIA) status byte.
The value is returned as a decimal number from 0 to 255. The LIAS? i
command queries the value (0 or 1) of bit i (0-7). Reading the entire byte
will clear it while reading bit i will clear just bit i.
5-20
Remote Programming
STATUS BYTE DEFINITIONS
The SR830 reports on its status by means of four status bytes: the Serial Poll Status byte, the Standard Event
Status byte, the LIA Status byte, and the Error Status byte.
The status bits are set to 1 when the event or state described in the tables below has occurred or is present.
SERIAL POLL bit name usage

STATUS BYTE
0 SCN No scan in progress (Stop or Done). A Paused
scan is considered to be in progress.
1 IFC No command execution in progress.
2 ERR An enabled bit in the error status byte has been

set.
3 LIA An enabled bit in the LIA status byte has been

set.
4 MAV The interface output buffer is non-empty.
5 ESB An enabled bit in the standard status byte has

been set.
6 SRQ SRQ (service request) has occurred.
7 Unused
The ERR, LIA, and ESB bits are set whenever any bit in both their respective status bytes AND enable regis-
ters is set. Use the ✳SRE, ✳ESE, ERRE and LIAE commands to set enable register bits. The ERR, LIA and
ESB bits are not cleared until ALL enabled status bits in the Error, LIA and Standard Event status bytes are
cleared (by reading the status bytes or using ✳CLS).
Using ✳STB? to read the Serial Poll Status Byte
A bit in the Serial Poll status byte is NOT cleared by reading the status byte using ✳STB?. The bit stays set
as long as the status condition exists. This is true even for SRQ. SRQ will be set whenever the same bit in the
serial poll status byte AND enable register is set. This is independent of whether a serial poll has occurred to
clear the service request.
Using SERIAL POLL
Except for SRQ, a bit in the Serial Poll status byte is NOT cleared by serial polling the status byte. When
reading the status byte using a serial poll, the SRQ bit signals that the SR830 is requesting service. The SRQ
bit will be set (1) the first time the SR830 is polled following a service request. The serial poll automatically
clears the service request. Subsequent serial polls will return SRQ cleared (0) until another service request
occurs. Polling the status byte and reading it with ✳STB? can return different values for SRQ. When polled,
SRQ indicates a service request has occurred. When read, SRQ indicates that an enabled status bit is set.
5-21
Remote Programming
SERVICE REQUESTS (SRQ)
A GPIB service request (SRQ) will be generated whenever a bit in both the Serial Poll Status byte AND Serial
Poll Enable register is set. Use ✳SRE to set bits in the Serial Poll Enable register. A service request is only
generated when an enabled Serial Poll Status bit becomes set (changes from 0 to 1). An enabled status bit
which becomes set and remains set will generate a single SRQ. If another service request from the same
status bit is desired, the requesting status bit must first be cleared. In the case of the ERR, LIA and ESB bits,
this means clearing the enabled bits in the ERR, LIA and ESB status bytes (by reading them). Multiple ena-
bled bits in these status bytes will generate a single SRQ. Another SRQ (from ERR, LIA or ESB) can only be
generated after clearing the ERR, LIA or ESB bits in the Serial Poll status byte. To clear these bits, ALL ena-
bled bits in the ERR, LIA or ESB status bytes must be cleared.
The controller should respond to the SRQ by performing a serial poll to read the Serial Poll status byte to
determine the requesting status bit. Bit 6 (SRQ) will be reset by the serial poll.
For example, to generate a service request when a RESRV overload occurs, bit 0 in the LIA Status Enable
register needs to be set (LIAE 0,1 command) and bit 3 in the Serial Poll Enable register must be set
(✳SRE 3,1 command). When a reserve overload occurs, bit 0 in the LIA Status byte is set. Since bit 0 in the
LIA Status byte AND Enable register is set, this ALSO sets bit 3 (LIA) in the Serial Poll Status byte. Since bit
3 in the Serial Poll Status byte AND Enable register is set, an SRQ is generated. Bit 6 (SRQ) in the Serial Poll
Status byte is set. Further RESRV overloads will not generate another SRQ until the RESRV overload status
bit is cleared. The RESRV status bit is cleared by reading the LIA Status byte (with LIAS?). Presumably, the
controller is alerted to the overload via the SRQ, performs a serial poll to clear the SRQ, does something to
try to remedy the situation (change gain, experimental parameters, etc.) and then clears the RESRV status bit
by reading the LIA status register. A subsequent RESRV overload will then generate another SRQ.
STANDARD EVENT bit name usage

STATUS BYTE
0 INP Set on input queue overflow (too many com-
mands received at once, queues cleared).
1 Unused
2 QRY Set on output queue overflow (too many

responses waiting to be transmitted, queues
cleared).
3 Unused
4 EXE Set when a command can not execute correctly

or a parameter is out of range.
5 CMD Set when an illegal command is received.
6 URQ Set by any key press or knob rotation.
7 PON Set by power-on.
The bits in this register remain set until cleared by reading them or by the ❊CLS command.
5-22
Remote Programming
LIA STATUS BYTE bit name usage
0 INPUT/RESRV Set when an Input or Amplifier overload is

detected.
1 FILTR Set when a Time Constant filter overload is

detected.
2 OUTPT Set when an Output overload is detected.
3 UNLK Set when a reference unlock is detected.
4 RANGE Set when the detection frequency switches

ranges (harmonic x ref. frequency decreases
below 199.21 Hz or increases above
203.12 Hz). Time constants above 30 s and
Synchronous filtering are turned off in the upper
frequency range.
5 TC Set when the time constant is changed indirect-

ly, either by changing frequency range, dynamic
reserve, filter slope or expand.
6 TRIG Set when data storage is triggered. Only if sam-

ples or scans are in externally triggered mode.
7 unused
The LIA Status bits stay set until cleared by reading or by the ❊CLS command.
ERROR STATUS BYTE bit name usage
0 Unused
1 Backup Error Set at power up when the battery backup has

failed.
2 RAM Error Set when the RAM Memory test finds an error.
3 Unused
4 ROM Error Set when the ROM Memory test finds an error.
5 GPIB Error Set when GPIB fast data transfer mode aborted.
6 DSP Error Set when the DSP test finds an error.
7 Math Error Set when an internal math error occurs.
The Error Status bits stay set until cleared by reading or by the ❊CLS command.
5-23
Remote Programming
5-24
Remote Programming
EXAMPLE PROGRAM 1
Using Microsoft C (v5.1) with the National Instruments GPIB card

on the IBM PC.
To successfully interface the SR830 to a PC via the GPIB interface, the instrument, interface card, and inter-
face drivers must all be configured properly. To configure the SR830, the GPIB address must be set using the
[Setup] key. The default GPIB address is 8; use this address unless a conflict occurs with other instruments in
your system. The SR830 will be set to GPIB address 8 whenever a reset is performed (power on with the
[Setup] key down).
Make sure that you follow all the instructions for installing the GPIB card. The National Instruments card
cannot be simply unpacked and put into your computer. To configure the card you must set jumpers and
switches on the card to set the I/O address and interrupt levels. You must run the program "IBCONF" to con-
figure the resident GPIB driver for you GPIB card. Please refer to the National Instruments manual for infor-
mation. In this example, the following options must be set with IBCONF:
Device name: LIA

Device address: 8
Terminate Read on EOS: No (for binary transfers)
Once all the hardware and GPIB drivers are configured, use "IBIC". This terminal emulation program allows
you to send commands to the SR830 directly from your computer's keyboard. If you cannot talk to the SR830
via "IBIC", then your programs will not run. Use the simple commands provided by National Instruments. Use
"IBWRT" and "IBRD" to write and read from the SR830. After you are familiar with these simple commands,
you can explore more complex programming commands.
/*******************************************************************************************************/
/* Example program using Microsoft C V5.1 and the National Instruments GPIB card.
Connect the Sine Out to the A Input with a BNC cable.
Run this program by typing the program name followed by a space and the device name.
The device name is the name used in IBCONF to configure the National Instruments driver.
For example, if the program is called LIATEST and the above configuration is used,
then type LIATEST LIA.
Binary X and Y data will be transferred for 10 seconds to the PC using the FAST transfer command.
After the fast transfer is complete, the existing magnitude (R) data in the data buffer will be transferred
in IEEE floating point format as well as the LIA non-normalized floating point format (faster transfer) */
#include <conio.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include "decl.h"
#define SR830 argv[1]
/* function prototypes */
5-25
Remote Programming
void main(int, char *[]);

void txLia(char *);
void initGpib(char *);
void setupLia(void);
void printOutBinaryResults(void);
void printOutIEEEResults(void);
void printOutLIAResults(void);
/* National Instruments Interface Function Prototypes (488.1 Calls - see the National software manual).
These are declared in "decl.h"
int ibfind(char*);
void ibwrt(int,char *,int);
void ibrd(int,char *,unsigned long);
void ibrsp(int,char *);
void ibeos(int,int);
void ibtmo(int,int);
*/
/* global variables */
int lia; /* SR830 handle */

int rxBuf[660*2]; /* FAST mode data buffer */
float rfBuf[1000]; /* Floating point data buffer */
void main(int argc, char *argv[])

{
int nPts,i;
char tstr[20];
if (argc<2) {
printf("\nUsage: liatest <devName>\n");
exit(1);
}
else
initGpib(SR830);
txLia("OUTX1"); /* Set the SR830 to output responses to the GPIB port */

setupLia(); /* Setup the SR830 */
printf("\nAcquiring Data\n");
ibtmo(lia,0); /* turn off timeout for lia or set the timeout longer than the scan (10 seconds). The
timeout measures the time to transfer the FULL number of bytes, not the time since
the most recent byte is received.*/
txLia("FAST2;STRD"); /* Turn FAST mode data transfer ON, then start scan using the STRD start
after delay command. The STRD command MUST be used if the scan is to
be started by this program! Do NOT use STRT. */
/* take data for 10 seconds and then stop */

ibrd(lia,(char *)rxBuf,2564L); /* get FAST mode data for 10 seconds.
10 seconds of data at 64 Hz sample rate has 64*10 + 1 points,
each point consists of X (2 bytes) and Y (2 bytes) for a total of
4*(64*10+1) = 2564 bytes. */
i=(int)ibcnt; /* save total number of bytes read */
5-26
Remote Programming
i=(int)ibcnt; /* save total number of bytes read */
txLia("PAUS"); /* pause the data storage so no new points are taken */

printOutBinaryResults(); /* format and print the results */
printf("\n%d bytes received.\nPress <Enter> to continue.",i);

getch(); printf("\n");
printf("Reading Results in IEEE Binary Format\n");

txLia("SPTS?"); /* how many points in CH1 (R) buffer? */
ibrd(lia,tstr,20L); /* get the answer */
sscanf(tstr,"%d",&nPts); /* convert from a string to an int */
printf ("SPTS?=%d\n",nPts);
sprintf(tstr,"TRCB?1,0,%d",nPts); /* use TRCB? to read the points in IEEE floating point format */
ibwrt(lia,tstr,strlen(tstr)); /* note that we cannot use txLia here because the IFC RDY bit will
not be set until the transfer is complete! */
ibrd(lia,(char *)rfBuf,(long)nPts*4L); /* read directly into a FLOAT array, 4 bytes per point */
printf ("\nReceived %d bytes in IEEE binary format\n",ibcnt);

printOutIEEEResults(); /* format and print results */
printf ("Press <Enter> to continue");
getch(); printf("\n");
printf("Reading Results in LIA Binary Format\n");

sprintf(tstr,"TRCL?1,0,%d",nPts); /* use TRCL? to read the points in LIA floating point format */
ibwrt(lia,tstr,strlen(tstr)); /* note that we cannot use txLia here because the IFC RDY bit will
not be set until the transfer is complete! */
ibrd(lia,(char *)rfBuf,(long)nPts*4L); /* read into FLOAT array but the values are NOT floats! */
printf ("\nReceived %d bytes in LIA binary format\n",ibcnt);

printOutLIAResults(); /* format and print results */
printf ("End of Program");
}
void printOutBinaryResults(void)
{
/* calculates the first 10 values of R based on the X and Y values taken in FAST mode by the SR830 */
int i;
float x,y,r;
int *ptr;
printf("\n\n");
ptr = rxBuf; /* ptr points to the first X,Y pair of values. X and Y are each integers. */
for (i=0;i<10;i++) {
x = (float) (*ptr++) /(float) 30000.0; /* 30000 is full scale which is 1 V in this case */
y = (float) (*ptr++) /(float) 30000.0; /* for other scales, multiply by the full scale voltage */
r = (float) sqrt(x*x + y*y); /* compute R from X and Y */
printf("%d %e\n",i,r);
}
}
5-27
Remote Programming
void printOutIEEEResults(void)
{
/* prints the first 10 values of R transferred in IEEE floating point format by the SR830 */
int i;
printf("\n\n");
for (i=0;i<10;i++)
printf("%d %e\n",i,rfBuf[i]); /* this is simple since the values are already IEEE floats */
}
void printOutLIAResults(void)
{
/* calculates the first 10 values of R transferred in LIA float format by the SR830 */
int i,mant,exp;
int *ptr;
float val;
printf("\n\n");
ptr =(int *) rfBuf; /* ptr points to integers in rfBuf, not floats! */
for (i=0;i<10;i++) {
mant = *ptr++; /* first comes the mantissa (16 bits) */
exp = *ptr++ - 124; /* then the binary exponent (16 bits) offset by 124 */
val = (float) mant * (float) pow(2.0,(double) exp);
printf("%d %e\n",i,val);
}
}
void initGpib(char *devName)

{
if ((lia=ibfind(devName))<0) {
printf("\nCannot Find SR830 \n\a");
exit(1);
}
}
void txLia(char *str)

{
char serPol;
ibwrt(lia,str,strlen(str));
do {
ibrsp(lia,&serPol); /* now poll for IFC RDY */
} while ((serPol&2)==0); /* until the command finishes executing */
}
void setupLia(void)
{
txLia("*RST"); /* initialize the lock-in */
5-28
Remote Programming
txLia("SRAT10; SEND0"); /* set 64 Hz sample rate, stop at end */

txLia("DDEF1,1,0; DDEF2,1,0"); /* set CH1=R, CH2=theta. Buffers store CH1 and CH2 */
printf("Scan is Initialized, Press <Enter> to Begin Scan...");

getch();
}
5-29
Remote Programming
5-30
Remote Programming
USING SR530 PROGRAMS WITH THE SR830
The SR830 responds to most SR530 programming commands. This allows the SR830 to drop into an existing
SR530 application with a minimum of program changes. Of course, some changes will be required and some
features are unique to one instrument or the other. For example, SR530 commands can not put the SR830
into a configuration which is not allowed by the SR830. All program routines which query the SR530
status MUST be rewritten to query the equivalent SR830 status using the SR830 status commands.
The SR530 emulation mode is intended to facilitate the transition to the SR830. New applications programs
should use the SR830 commands in order to take advantage of all of the SR830 features.
The SR575 program will NOT run reliably with the SR830. This is because the SR575 is optimized for
speed and the SR830 command execution time for some commands is longer than in the SR530.
The SR530 commands are documented in the SR530 manual. SR530 command parameters follow the
SR530 conventions. Exceptions are noted below.
OUTX i The SR830 OUTX i command sets the output interface to RS232 (i=0) or
GPIB (i=1). The OUTX i command MUST be at the start of ANY
SR830 program to direct responses to the interface in use.
FMOD i The SR530 is always in external reference mode. Use the FMOD 0 com-
mand to set the SR830 to external reference. To use the SR830
internal oscillator, use the FMOD 1 command.
AX
AY
AR The AX, AY and AR commands auto offset the X, Y and R outputs.
Unlike the SR530, the X and Y offsets have no effect on R.
AP The AP command performs the Auto Phase function. AP has no effect if

the phase is unstable.
B {n} The SR830 has no bandpass filter. This command is emulated but no
changes are made to the SR830 configuration.
C {n} Changes the Reference display.
D {n} Change the dynamic reserve. Unlike the SR530, all reserves are
allowed at all sensitivities.
E m {,n} Change the Channel m expand. n=2 selects expand by 100. Note that
expands in the SR830 affect the X and Y BNC outputs as well as the
Display outputs.
F {x} The F command Reads the frequency. The F x command sets the
internal oscillator frequency to x Hz.
G {n} Change the sensitivity from 10 nV (n=1) to 500 mV (n=24). Settings

below 100 nV are always allowed. The 1V sensitivity can be set
using G25. Querying this sensitivity returns a value of 24.
5-31
Remote Programming
H The SR830 does not sense the pre-amplifier. This command is emulat-
ed and always returns 0.
I {n} Change the remote/local status. The SR830 Override Remote mode
can override the I2 command. Use the OVRM command to change
this.
J Not implemented. Do not use.
K Not implemented. Do not use.
L m {,n} Change the line notch filter status.
M {n} Change the reference mode to 2f. This command actually sets the
harmonic detect number to n+1 in order to access harmonics
higher than 2f.
N {m} Change the noise bandwidth. This command has no effect on the time
constants. If the S4 command is used to change the display to
Xnoise,Ynoise, then the N m command changes the effective ENBW
with which the output noise will be reported when queried using the
Q1 or Q2 commands. The N command only affects the response to
Q1 or Q2 and only if the S4 command is used first.
OX {n} {,v}
OY {n} {,v}
OR {n} {,v} Change the X, Y or R offsets. Remember, v is an input voltage (not a
percentage) for the SR530. Unlike the SR530, the X and Y offsets
have no effect on R.
P {v} Change the reference phase shift. The value of v is limited to

-360.0≤v≤729.99. The phase shift is also defined differently for the
SR830. Check the sense of phase rotation if your application is
phase sensitive.
Q1
Q2
QX
QY Read the output values in Volts or degrees. When the current input is
selected, the outputs are returned in Amps.
R {n} Change the reference input mode.
S {n} Change the Output displays. The SR830 only responds if n=0 (X,Y),
n=2 (R,θ) or n=4 (Xnoise,Ynoise).
T m {,n} Change the time constant.
If m=1, then T1,n sets the time constant from 1 ms (n=1) to 30 ks

(n=16). Time constants greater than 30 s are available only if the
detection frequency is below 200 Hz. The time constant slope is not
changed. The T1 query returns a maximum value of 11, even if the
time constant is greater than 100 s.
5-32
Remote Programming
If m=2:
T2,0 changes the slope to 6 dB/oct, time constant not changed.
T2,1 changes the time constant to 100 ms with 12 dB/oct slope.
T2,2 changes the time constant to 1 s with 12 dB/oct slope.
Use the T2,n command to change the filter slope, then use T1,n to
select the time constant.
U m {,n} Not implemented. Do not use.
V {n} Change the value of the SRQ mask. This command changes the serial
poll enable register of the SR830. The serial poll byte is that of the
SR830 not the SR530! Programs which query the SR530 status need
to be changed to query the equivalent SR830 status byte.
Wn Not implemented. Do not use.
X n {,v} Set or query the auxiliary analog ports. If n=1,2,3 or 4, the value of Aux
Input n is returned. If n=5 or 6, then the Xn,v sets the value of Aux
Output 1 or 2 to v Volts. The X5 ratio is NOT implemented. Ratio out-
puts must be done using the SR830 display ratio mode.
Y {n} Not implemented. Do not use. Use the SR830 status commands to
read the SR830 status bytes.
Z Reset the SR830. The instrument is reset to the SR830 default setup
listed in the Operation section. This differs slightly from the SR530
default. (The sensitivity is set to 1 V, not 500 mV).
5-33
Remote Programming
5-34
PERFORMANCE TESTS
Introduction The performance tests described in this section are designed to verify
with a high degree of confidence that the unit is performing correctly.
The results of each test may be recorded on the test sheet at the end of
this section.
Serial Number If you need to contact Stanford Research Systems, please have the
serial number of your unit available. The 5-digit serial number is printed
on a label affixed to the rear panel. The serial number is also displayed
on the CH1 and CH2 displays when the unit is powered on.
Firmware Revision The firmware revision code is shown on the Reference display when the
unit is powered on.
Preset Throughout this section, it will be necessary to preset the lock-in into a
known default state. To do this, turn the power off. Turn the power back
on while holding down the [Setup] key. The unit will perform power up
tests and then assume the default settings. Each test generally starts
with a preset. This procedure will be referred to as {PRESET}.
Warm Up The lock-in should be turned on and allowed to warm up for at least an
hour before any tests are performed. The self test does not require any
warm up period.
It is necessary to turn the unit off and on to preset it. As long as the unit
is powered on immediately, this will not affect the test results.
Test Record Make a copy of the SR830 Performance Test Record at the end of this
section. Fill in the results of the tests on this record. This record will allow
you to determine whether the tests pass or fail and also to preserve a
record of the tests.
If A Test Fails If a test fails, you should check the settings and connections of any exter-
nal equipment and, if possible, verify its operation using a DVM, scope or
some other piece of test equipment.
After checking the setup, repeat the test from the beginning to make sure
that the test was performed correctly.
If the test continues to fail, contact Stanford Research Systems for fur-
ther instructions. Make sure that you have the unit's serial number and
firmware revision code handy. Have the test record on hand as well.
Necessary Equipment The following equipment is necessary to complete the performance tests.
The suggested equipment or its equivalent should be used.
1. Frequency Synthesizer
Freq Range 1 Hz to 1 MHz
Freq Accuracy better than 5 ppm
Amplitude Accuracy 0.2 dB from 1 Hz to 100 kHz
Harmonic Distortion ≤ -65 dBc
6-1
Performance Tests
Spurious ≤ -55 dBc

TTL SYNC available
Recommended SRS DS335
2. AC Calibrator
Freq Range 10 Hz to 100 kHz
Amplitude 1 mV to 10 V
Accuracy 0.1%
External phase locking capability
Recommended Fluke 5200A
3. DC Voltmeter
Range 19.999 V, 4 1/2 digits
Accuracy 0.005%
Recommended Fluke 8840A
4. Feedthrough Terminations
Impedance 50 Ω
Front Panel Display Test To test the front panel displays, press the [Phase] and [Freq] keys
together. All of the LED's will turn on. Press [Phase] to decrease the
number of on LED's to half on, a single LED and no LED's on. Use the
knob to move the turned on LED's across the panel. Press [Freq] to
increase the number of on LED's. Make sure that every LED can be
turned on. Press any other key to exit this test mode.
Keypad Test To test the keypad, press the [Phase] and [Ampl] keys together. The
CH1 and CH2 displays will read 'Pad code' and a number of LED indica-
tors will be turned on. The LED's indicate which keys have not been
pressed yet. Press all of the keys on the front panel, one at a time. As
each key is pressed, the key code is displayed in the Reference display,
and nearest indicator LED turns off. When all of the keys have been
pressed, the display will return to normal. To return to normal operation
without pressing all of the keys, simply turn the knob.
6-2
Performance Tests
1. Self Tests
The self tests check the lock-in hardware. These are functional tests and do not relate to the specifications.
These tests should be checked before any of the performance tests.
Setup
No external setup is required for this test.
Procedure
1) {PRESET} (Turn on the lock-in with the [Setup] key pressed)
Check the results of the DATA, BATT, PROG and DSP tests.
2) This completes the functional hardware tests. Enter the results of this test in the test record at the end
of this section.
6-3
Performance Tests
6-4
Performance Tests
2. DC Offset
This test measures the DC offset of the input.
Setup
Connect a 50Ω terminator to the A input. This shorts the input so the lock-in's own DC offset will be
measured.
Procedure
1) {PRESET} (Turn the lock-in off and on with the [Setup] key pressed)
2) Press the keys in the following sequence:
[Freq]
Use the knob to set the frequency to 1.00 Hz.
[Sensitivity Down]
Set the sensitivity to 1 mV.
[CH1 Display]
Set the Channel 1 display to R.
3) Wait at least 10 seconds, then record the reading of R.
4) Press
[Couple]
Select DC coupling.
5) Wait 10 seconds, then record the reading of R.
6) This completes the DC offset test. Enter the results of this test in the test record at the end of this
section.
6-5
Performance Tests
6-6
Performance Tests
3. Common Mode Rejection

This test measures the common mode rejection of the lock-in.
Setup
We will use the internal oscillator sine output to provide the signal.
Connect the Sine Out to both the A and B inputs of the lock-in. Use equal length cables from A and B to a
BNC TEE. Connect the cable from the Sine Out to the TEE. Do not use any termination.
Procedure
[Freq]
Use the knob to adjust the frequency to 100.0 Hz.
[Channel 1 Display]
3) The value of R should be 1.000 V (within 2%).
4) Press
[Couple]
Select DC coupling.
[Input]
Select A-B.
[Sensitivity Down]
Set the sensitivity to 200 µV.
5) Record the value of R.
6) This completes the CMRR measurement test. The common mode rejection is 20log(1.0/R) where R is
in Volts. Enter the results of this test in the test record at the end of this section.
6-7
Performance Tests
6-8
Performance Tests
4. Amplitude Accuracy and Flatness

This test measures the amplitude accuracy and frequency response.
Setup
We will use the frequency synthesizer to provide an accurate frequency and the AC calibrator to provide a
sine wave with an exact amplitude.
Connect the output of the frequency synthesizer to the phase lock input of the calibrator. Connect the output
of the AC calibrator to the A input of the lock-in. Be sure to use the appropriate terminations where required.
Connect the TTL SYNC output of the synthesizer to the Reference Input of the lock-in.
Set the Synthesizer to: Set the AC Calibrator to:

Function Sine Frequency 1 kHz
Frequency 1 kHz Amplitude 1.000 Vrms
Amplitude 0.5 Vrms Voltage Off
Offset off or 0V Phase Lock On
Sweep off Sense Internal
Modulation none
Procedure
[Source]
Select External reference mode (INTERNAL led off).
[Trig]
Select POS EDGE.
[Channel 1 Display]
[Slope/Oct]
Select 24 dB/oct.
3) Amplitude accuracy is verified at 1 kHz and various sensitivities. For each sensitivity setting in the
table below, perform steps 3a through 3c.
Sensitivity AC Calibrator Amplitude

1V 1.0000 Vrms
200 mV 200.00 mVrms
100 mV 100.000 mVrms
20 mV 20.000 mVrms
10 mV 10.000 mVrms
a) Set the AC calibrator to the amplitude shown in the table.
6-9
Performance Tests
b) Press
[Sensitivity Up/Dn]
Select the sensitivity from the table.
c) Wait for the R reading to stabilize. Record the value of R for each sensitivity.
4) Frequency response is checked at frequencies above 1 kHz. The test frequencies are listed below.
Test Frequencies
24 kHz
48 kHz
72 kHz
96 kHz
a) Set the AC calibrator to 1 kHz and an amplitude of 200.00 mVrms.
b) Set the frequency synthesizer to 1 kHz.
c) Press
[Sensitivity Up/Dn]
Set the sensitivity 200 mV.
d) Set the AC calibrator and frequency synthesizer to the frequency in the table.
e) Wait for the R reading to stabilize. Record the value of R.
f) Repeat steps 4d and 4e for all of the frequencies listed.
5) This completes the amplitude accuracy and frequency response test. Enter the results of this test in
the test record at the end of this section.
6-10
Performance Tests
5. Amplitude Linearity
This test measures the amplitude linearity. This tests how accurately the lock-in measures a signal smaller
than full scale.
Setup
We will use the frequency synthesizer to provide an accurate frequency and the AC calibrator to provide a
sine wave with an exact amplitude.
Connect the output of the frequency synthesizer to the phase lock input of the calibrator. Connect the output
of the AC calibrator to the A input of the lock-in. Be sure to use the appropriate terminations where required.
Connect the TTL SYNC output of the synthesizer to the Reference Input of the lock-in.
Set the Synthesizer to: Set the AC Calibrator to:

Function Sine Frequency 1 kHz
Frequency 1 kHz Amplitude 1.0000 Vrms
Amplitude 0.5 Vrms Voltage Off
Offset off or 0V Phase Lock On
Sweep off Sense Internal
Modulation none
Procedure
[Source]
[Trig]
Select POS EDGE.
[Channel 1 Display]
[Slope/Oct]
Select 24 dB/oct.
3) For each of the amplitudes listed below, perform steps 3a through 3c.
AC Calibrator Amplitudes
1.0000 Vrms
100.00 mVrms
10.000 mVrms
a) Set the AC calibrator to the amplitude in the table.
b) Wait for the R reading to stabilize. Record the value of R.
4) This completes the amplitude linearity test. Enter the results of this test in the test record at the end of
this section.
6-11
Performance Tests
6-12
Performance Tests
6. Frequency Accuracy
This test measures the frequency accuracy of the lock-in. This tests the accuracy of the frequency counter
inside the unit. The counter is used only in external reference mode. The internal oscillator frequency is set by
a crystal and has 25 ppm frequency accuracy.
Setup
We will use the frequency synthesizer to provide the reference signal.
Connect the TTL SYNC output of the frequency synthesizer to the Reference input of the lock-in.
Procedure
2) Set the frequency synthesizer to a frequency of 10 kHz.
[Source]
[Trig]
Select POS EDGE.
4) The lock-in should be locked to the external reference. The frequency is displayed at the bottom of
the screen. Record the frequency reading.
5) This completes the frequency accuracy test. Enter the results of this test in the test record at the end
of this section.
6-13
Performance Tests
6-14
Performance Tests
7. Phase Accuracy
This test measures the phase accuracy of the lock-in. Due to the design of the lock-in, the phase accuracy
can be determined by measuring the phase of the internal oscillator Sine Out.
Setup
Connect the Sine Out to the A input of the lock-in using a 1 meter BNC cable. Do not use any termination.
Procedure
[Slope /Oct]
Select 24 dB/oct.
[Couple]
Select DC coupling.
[Channel 1 Display]
[Channel 2 Display]
Set the Channel 2 display to θ.
3) The value of R should be 1.000 V (±2%) and the value of θ should 0° (±1°).
4) Phase accuracy is checked at various frequencies. The test frequencies are listed below.
Test Frequencies
10 Hz
100 Hz
1 kHz
10 kHz
a) Press
[Freq]
Use the knob to set the internal oscillator to the frequency from the table.
b) Wait for the readings to stabilize. Record the value of θ.
c) Repeat steps 4a and 4b for all frequencies in the table.
5) This completes the phase accuracy test. Enter the results of this test in the test record at the end of
this section.
6-15
Performance Tests
6-16
Performance Tests
8. Sine Output Amplitude Accuracy and Flatness

This test measures the amplitude accuracy and frequency response of the internal oscillator Sine Out.
Setup
We will use the lock-in to measure the Sine Out. Connect the Sine Out to the A input of the lock-in.
Procedure
[Channel 1 Display]
3) Amplitude accuracy is verified at 1 kHz using various sensitivities. For each sine amplitude and sensi-
tivity setting in the table below, perform steps 3a through 3b.
Sensitivity Sine Output Amplitude

1V 1.000 Vrms
200 mV 0.200 Vrms
50 mV 0.050 Vrms
10 mV 0.010 Vrms
a) Press
[Ampl]
Use the knob to set the sine amplitude to the value in the table.
[Sensitivity Up/Dn]
Set the sensitivity to the value in the table.
b) Wait for the R reading to stabilize. Record the value of R.
c) Repeat 3a and 3b for each amplitude in the table.
4) Frequency response is checked at frequencies above 1 kHz. The sine amplitude is set to 1 Vrms for
all frequencies. The test frequencies are listed below.
Test Frequencies
24 kHz
48 kHz
72 kHz
96 kHz
c) Press
[Sensitivity Up]
Set the sensitivity to 1 V.
[Ampl]
Use the knob to set the sine amplitude to 1.00 V.
6-17
Performance Tests
d) Press
[Freq]
Use the knob to set the internal oscillator frequency to the value in the table.
e) Wait for the R reading to stabilize. Record the value of R.
f) Repeat steps 4d and 4e for all of the frequencies listed.
5) This completes the sine output amplitude accuracy and frequency response test. Enter the results of
this test in the test record at the end of this section.
6-18
Performance Tests
9. DC Outputs and Inputs

This test measures the DC accuracy of the DC outputs and inputs of the lock-in.
Setup
We will use the digital voltmeter (DVM) to measure the DC outputs of the lock-in. Then we will use one of the
outputs to generate a voltage to measure on the DC inputs.
Connect a 50Ω termination to the A input.
Procedure
2) For the CH1 and CH2 outputs, repeat steps 2a through 2e.
a) Connect the CH1 (or CH2) output to the DVM. Set the DVM to 19.999 V range.
b) Press
[Channel 1 (or 2) Offset On/Off]
Turn the offset on.
c) For each of the offsets in the table below, repeat steps 2d and 2e.
Offsets (%)
-100.00
-50.00
0.00
50.00
100.00
d) Press
[Channel 1 (or 2) Offset Modify]
Show the offset in the Reference display.
Use the knob to set the offset to the value in the table.
e) Record the DVM reading.
3) For each Aux Output (1, 2, 3 and 4), repeat steps 3a through 3e.
a) Press
[Aux Out]
Display the correct Aux Output level on the Reference display.
b) Connect the selected Aux Output (on the rear panel) to the DVM.
6-19
Performance Tests
c) For each output voltage in the table below, repeat steps 3d and 3e.
Output Voltages
-10.000
-5.000
0.000
5.000
10.000
d) Use the knob to adjust the Aux Output level to the value from the table.
e) Record the DVM reading.
4) Press
[Aux Out]
Display Aux Out 1 on the Reference display.
5) For Aux Inputs 1 and 2, repeat steps 5a through 5e.
a) Connect Aux Out 1 to Aux Input 1 (or 2) with a BNC cable.
b) Press
[Channel 1 Display]
Set the Channel 1 display to AUX IN 1 (or 2)
c) For each output voltage in table 3c above, repeat steps 5d and 5e.
d) Use the knob to adjust the Aux Out 1 level to the values from the table above.
e) Record the Aux Input 1 (or 2) value from the Channel 1 display.
6) For Aux Inputs 3 and 4, repeat steps 6a through 6e.
a) Connect Aux Out 1 to Aux Input 3 (or 4) with a BNC cable.
b) Press
[Channel 2 Display]
Set the Channel 2 display to AUX IN 3 (or 4)
c) For each output voltage in table 3c above, repeat steps 6d and 6e.
d) Use the knob to adjust the Aux Out 1 level to the values from the table above.
e) Record the Aux Input 3 (or 4) value from the Channel 1 display.
7) This completes the DC outputs and inputs test. Enter the results of this test in the test record at the
end of this section.
6-20
Performance Tests
10. Input Noise

This test measures the lock-in input noise.
Setup
Connect a 50Ω termination to the A input. This grounds the input so the lock-in's own noise is measured.
Procedure
[Sensitivity Down]
Set the sensitivity to 100 nV.
[Channel 1 Display]
Set the Channel 1 display to X Noise.
3) Wait until the reading of Channel 1 stabilizes. Record the value of Channel 1.
4) This completes the noise test. Enter the results of this test in the test record at the end of this section.
6-21
Performance Tests
6-22
Page 1 of 4
SR830 Performance Test Record

Serial Number Tested By
Firmware Revision Date
Equipment Used
1. Self Tests
Test Pass Fail
DATA ____ ____
BATT ____ ____
PROG ____ ____
DSP ____ ____
2. DC Offset
Input Coupling Reading Upper Limit
AC _______ 0.500 mV
DC _______ 0.500 mV
3. Common Mode Rejection

Frequency Reading Upper Limit
100 Hz _______ 30 µV
4. Amplitude Accuracy and Flatness

Sensitivity Calibrator Ampl. Lower Limit Reading Upper Limit
1V 1.0000 Vrms 0.9900 V _______ 1.0100 V
200 mV 200.00 mVrms 198.00 mV _______ 202.00 mV
100 mV 100.000 mVrms 99.00 mV _______ 101.00 mV
20 mV 20.000 mVrms 19.800 mV _______ 20.200 mV
10 mV 10.000 mVrms 9.900 mV _______ 10.100 mV
Sensitivity Frequency Lower Limit Reading Upper Limit

200 mV 24 kHz 198.00 mV _______ 202.00 mV
200 mV 48 kHz 198.00 mV _______ 202.00 mV
200 mV 72 kHz 198.00 mV _______ 202.00 mV
200 mV 96 kHz 198.00 mV _______ 202.00 mV
6-23
Page 2 of 4

5. Amplitude Linearity
Sensitivity Calibrator Ampl. Lower Limit Reading Upper Limit
1V 1.0000 Vrms 0.9900 V _______ 1.0100 V
100.00 mVrms 0.0990 V _______ 0.1010 V
10.000 mVrms 0.0098 V _______ 0.0102 V
6. Frequency Accuracy
Input Frequency Lower Limit Reading Upper Limit
10 kHz 9.990 kHz _______ 10.010 kHz
7. Phase Accuracy
Frequency Lower Limit Reading Upper Limit
10 Hz -1.0 deg _______ +1.0 deg
100 Hz -1.0 deg _______ +1.0 deg
1 kHz -1.0 deg _______ +1.0 deg
10 kHz -1.0 deg _______ +1.0 deg
8. Sine Output Amplitude and Flatness

Sensitivity Sine Output Ampl. Lower Limit Reading Upper Limit
1V 1.000 Vrms 0.9800 V _______ 1.0200 V
200 mV 0.200 Vrms 196.00 mV _______ 204.00 mV
50 mV 0.050 Vrms 49.000 mV _______ 51.000 mV
10 mV 0.010 Vrms 9.800 mV _______ 10.200 mV
Sine Ampl. Frequency Lower Limit Reading Upper Limit

1.000 Vrms 24 kHz 0.9800 V _______ 1.0200 V
48 kHz 0.9800 V _______ 1.0200 V
72 kHz 0.9800 V _______ 1.0200 V
96 kHz 0.9800 V _______ 1.0200 V
9. DC Outputs and Inputs

Output Offset Lower Limit Reading Upper Limit
CH1 -100.00 9.960 V _______ 10.040 V
-50.00 4.960 V _______ 5.040 V
0.00 -0.020 V _______ 0.020 V
50.00 -5.040 V _______ -4.960 V
100.00 -10.040 V _______ -9.960 V
6-24
Page 3 of 4

9. DC Outputs and Inputs (continued)
Output Offset Lower Limit Reading Upper Limit
CH2 -100.00 9.960 V _______ 10.040 V
-50.00 4.960 V _______ 5.040 V
0.00 -0.020 V _______ 0.020 V
50.00 -5.040 V _______ -4.960 V
100.00 -10.040 V _______ -9.960 V
Output Voltage Lower Limit Reading Upper Limit

AUX OUT 1 -10.000 -10.040 V _______ -9.960 V
-5.000 -5.040 V _______ -4.960 V
0.000 -0.020 V _______ 0.020 V
5.000 4.960 V _______ 5.040 V
10.000 9.960 V _______ 10.040 V

AUX OUT 2 -10.000 -10.040 V _______ -9.960 V
-5.000 -5.040 V _______ -4.960 V
0.000 -0.020 V _______ 0.020 V
5.000 4.960 V _______ 5.040 V
10.000 9.960 V _______ 10.040 V

AUX OUT 3 -10.000 -10.040 V _______ -9.960 V
-5.000 -5.040 V _______ -4.960 V
0.000 -0.020 V _______ 0.020 V
5.000 4.960 V _______ 5.040 V
10.000 9.960 V _______ 10.040 V

AUX OUT 4 -10.000 -10.040 V _______ -9.960 V
-5.000 -5.040 V _______ -4.960 V
0.000 -0.020 V _______ 0.020 V
5.000 4.960 V _______ 5.040 V
10.000 9.960 V _______ 10.040 V
6-25
Page 4 of 4

9. DC Outputs and Inputs (continued)
Input Voltage Lower Limit Reading Upper Limit
AUX IN 1 -10.000 -10.040 V _______ -9.960 V
-5.000 -5.040 V _______ -4.960 V
0.000 -0.020 V _______ 0.020 V
5.000 4.960 V _______ 5.040 V
10.000 9.960 V _______ 10.040 V

AUX IN 2 -10.000 -10.040 V _______ -9.960 V
-5.000 -5.040 V _______ -4.960 V
0.000 -0.020 V _______ 0.020 V
5.000 4.960 V _______ 5.040 V
10.000 9.960 V _______ 10.040 V

AUX IN 3 -10.000 -10.040 V _______ -9.960 V
-5.000 -5.040 V _______ -4.960 V
0.000 -0.020 V _______ 0.020 V
5.000 4.960 V _______ 5.040 V
10.000 9.960 V _______ 10.040 V

AUX IN 4 -10.000 -10.040 V _______ -9.960 V
-5.000 -5.040 V _______ -4.960 V
0.000 -0.020 V _______ 0.020 V
5.000 4.960 V _______ 5.040 V
10.000 9.960 V _______ 10.040 V
10. Input Noise

Frequency Sensitivity Reading Upper Limit
1 kHz 100 nV _______ 8 nV/√Hz
Min Reserve
6-26
CIRCUIT DESCRIPTION
CPU and Power Supply Board
DSP Logic Board
Analog Input Board
Display Board
Keypad Board
CAUTION CIRCUIT BOARDS

The SR830 has five main printed circuit boards.
Always disconnect the power cord and The five boards shown contain most of the active
wait at least one minute before open- circuitry of the unit. The rear panel circuit board
ing the unit. Dangerous power supply only provides connections to the BNC connectors
voltages may be present even after the on the rear panel.
unit has been unplugged.
Check the LED at the front edge of the

power supply board. The unit is safe NOTICE: Schematics may not
only if the LED is OFF. If the LED is show current part numbers or
ON, then DO NOT attempt any service values.
on the unit. Refer to parts list for current
part numbers or values.
This unit is to be serviced by qualified
service personnel only. There are no
user serviceable parts inside.
7-1
Circuit Description
7-2
Circuit Description
CPU and POWER SUPPLY BOARD

The CPU board contains the microprocessor SPIN KNOB
system. All display, front panel, disk, and comput-
er interfaces are on this board. The knob is an optical encoder buffered by U612.
Each transition of its outputs is clocked into U610
MICROPROCESSOR SYSTEM or U611 and generates an interrupt at the output
of U602A. The processor keeps track of the knob's
The microprocessor, U101, is an 80C186 micro- position continuously.
controller which integrates a fast 16 bit processor,
counter-timers, interrupt controller, DMA controller, SPEAKER
and I/O decoding into a single component.
The speaker is driven by a timer on the 80C186.
The 80C186 uses a 24.00 MHz crystal, X101, as The timer outputs a square wave which is enabled
its oscillator. The instruction clock cycle is 2 oscil- by U602B and drives the speaker through Q705.
lator cycles or 12.0 MHz. The data and lower 16
bits of address are multiplexed on AD0-AD15. GPIB INTERFACE
U201, U202, U203 latch the address A0-A19 at
the beginning of each memory or I/O cycle. U204 The GPIB (IEEE-488) interface is provided by
and U205 are bidirectional data bus drivers which U902, a TMS9914A controller. U903 and U904
are active during the data read/write portion of buffer data I/O to the GPIB connector. U902 is pro-
each memory or I/O cycle. grammed to provide an interrupt to the processor
whenever there is bus activity addressed to the
The 80C186 can address 1 Mbyte of memory and unit.
64k of I/O space. The memory is mapped into 2
256kbyte blocks. Each block has 2 sockets, one RS232 INTERFACE
for the low byte and one for the high byte of data.
The SCN2641 UART, U905, provides all of the
U303 and U304 are 128kbyte EPROMS holding UART functions as well as baud rate generation.
the program boot firmware. This memory is Standard baud rates up to 19.2k can be generated
mapped at C0000H to FFFFFH (256k). from the 3.6864 MHz clock. U906 buffers the out-
going data and control signals. Incoming signals
U401 and U402 are 128kbyte CMOS static RAMs are received by U705A and U705B. If the host
mapped at 00000H to 3FFFFH (256k). U401 and computer asserts DTR, RS232 data output from
U402 are backed up by the battery. Q401 provides the unit will cease.
power down RAM protection. This memory is
system memory. The RS232 port is a DCE and may be connected
to a PC using a standard serial cable (not a "null
3 of the 7 80C186's peripheral chip select strobes modem" cable).
are used by peripherals on the CPU board. -PCS0
is decoded into 16 I/O strobes which access the EXPANSION CONNECTOR
displays, keypad and knob, etc. -PCS1 decodes
the the GPIB controller. -PCS2 selects the UART. All control of the data acquisition hardware is
through the signals on the 30 pin expansion
FRONT PANEL INTERFACE connector.
U614 and U615 buffer the front panel connector

cable. The Display Board holds the front panel
logic.
7-3
Circuit Description
POWER SUPPLY
The 24 VDC brushless fan cools the heat sink and
CAUTION: Dangerous voltages are present on power supply rectifiers.
this circuit board whenever the instrument is
attached to an AC power source and the rear
panel power switch is "on".
Always disconnect the power cord and wait at

least one minute before opening the unit.
Check the LED at the front edge of the power
supply board. The unit is safe only if the LED is
OFF. If the LED is ON, then DO NOT attempt
any service on the unit.
UNREGULATED POWER SUPPLIES
A power entry module, with RF line filter, is used

to configure the unit for 100, 120, 220, or 240
VAC. The line filter reduces noise from the instru-
ment and reduces the unit's susceptibility to line
voltage noise.
Bridge rectifiers are used to provide unregulated

DC at ±24V, ±20V and ±8V. Schottky diodes are
used for all supplies to reduce rectifier losses.
Resistors provide a bleed current on all of the

unregulated supply filter capacitors. Because of
the large capacitances in this circuit, the time for
the voltages to bleed to zero is about a minute
after the power is turned off.
POWER SUPPLY REGULATORS
The voltage regulators provide outputs at +5V,

-5V, ±15V, and ±12V. The +5V regulators are
designed to operate with a very low drop-out
voltage.
There are 2 +5V supplies, one to power the CPU

board and front panel displays (+5V_P), and one
to power the DSP Logic Board (+5V_I).
U6 and U8 are the ±12V regulators. U5 is the -5V

regulator.
U9 and U10 provide ±20V sources which are not

referenced to the digital ground (as are all of the
supplies mentioned above). This allows the analog
input board to establish a ground at the signal
input without digital ground noise.
U1 provides power-up and power-down reset.
7-4
Circuit Description
DSP LOGIC BOARD

OVERVIEW also sets the internal reference frequency
accuracy.
The DSP LOGIC BOARD takes a digital input from
the A/D Converter on the Analog Input Board and When the reference mode is external, the VCO
performs all of the computations related to the (voltage controlled oscillator, U110) is used as the
measurement before it is displayed on the screen. system clock. The VCO nominally runs at 30 MHz
This includes generating the digital reference sine as well. U105 is a phase comparator. The external
wave, demodulating the signal, low-pass filtering reference input, discriminated by U103 (or TTL
the results, and offset and expanding the outputs. buffered through U104D) is one of the inputs to
The internal oscillator sine output and Aux D/A the phase comparator. The other input is the inter-
outputs are generated on this board as well. The nal reference. The DSP always synthesizes a sine
reference phase lock loop controls the clock of this wave at the reference frequency. This is the Sine
board whenever the reference mode is external. Output. This sine output is discriminated by U209
These functions are implemented within a system into a TTL square wave (TTL Sync Out) and is the
comprised of five functional blocks: the Digital other input to the phase comparator. The phase
Signal Processor (DSP), the DAC Outputs, the lock loop then controls the VCO which is the clock
Timing Signal Generator, the Reference Clock to the DSP. This in turn changes the sine output
Generator and the I/O Interface. Through the use frequency to maintain frequency lock with the
of highly efficient algorithms, the system is capa- external reference. The DSP is constantly getting
ble of real-time lock-in operation to 100 kHz with external frequency information from the host
24 dB/oct filtering on both X and Y as well as pro- (based upon counter U622) which allows the DSP
viding a synthesized analog sine output. to synthesize nearly the correct reference frequen-
cy assuming a 30 MHz clock. This keeps the VCO
DSP PROCESSOR within range at all frequencies.
The SR830 utilizes a Motorola 24-bit DSP56001 TIMING GENERATOR

digital signal processor (U501). The DSP is config-
ured without external memory. The lock-in algo- All timing signals for the DSP and Analog boards
rithms run entirely within the internal program and are derived from the system clock by PALs (U601-
data memory of the DSP itself. The Host proces- 604). These PALs generate the clocks for the
sor bus is connected to the main CPU Board via DACs and A/D converter, the multiplexing signals
the I/O Interface on the DSP Logic Board. The for the Aux inputs and outputs, etc.
80C186 processor on the CPU Board acts as the
"host" processor to the DSP. DSP firmware and SERIAL CHANNELS
commands are downloaded from the CPU Board
to invoke different operating modes. The DSP also There are two serial data streams from the A/D
has two dedicated serial ports: one for receiving, converter on the Analog Input board which need to
and one for transmitting. be received by the DSP. The digitized input signal
is received directly via the DSP's serial input port.
REFERENCE CLOCK SOURCE The Aux A/D input data is shifted into a pair of
serial-to-parallel registers (U502 and U503) and is
The clock to the DSP is derived from the timing read via the DSP data bus. Each A/D input chan-
generator. U120, U121 and U122 are gates which nel provides a new sample every 4 µs.
select the clock source for the entire digital board.
There are two dual-channel D/A converters on this
When the reference mode is internal, the board for a total of four D/A output channels. Each
30.208 MHz crystal (U111) is used. The A/D output channel provides a new output every 4 µs.
inputs and D/A outputs run with a 256 kHz cycle This means that 4 output values must be written
and the DSP performs 59 instructions each cycle by the DSP each 4 µs cycle. The DSP writes to
(each instruction takes two clocks). The crystal one channel of each D/A converter via its serial
7-5
Circuit Description
transmit port each cycle. The transmit port oper- ±22V from the power supply is used to generate
ates at twice the frequency of the receive port. The ±15V for the op amps. ±5.6V for analog switches
DSP writes to the other channel of each DAC via a and op amps is generated from the ±15V supplies.
pair of parallel-to-serial registers (U504 and The reference and sine discriminators use separ-
U505). ate ±5V supplies regulated from the ±15V supplies
as well.
DAC OUTPUTS
Three of the DAC output channels provide Sine

Out, X and Y. The fourth channel is multiplexed
into eight slow outputs. Two of these are the front
panel CH1 and CH2 outputs when the outputs are
proportional to a trace. Four of these are the Aux
D/A outputs. The last two are used to provide
internal offset trims to the reference and sine
discriminators.
The DSP generates sine waves using direct digital

synthesis. At each 4 µs cycle, the DSP calculates
the next sine output value based upon the desired
reference frequency. This value is output via a
DAC and converted to an analog output. This
output is a sampled sine wave. To convert this to a
smooth, low distortion analog sine wave, the
output is filtered to remove frequency components
above 100 kHz (U201-203). The filter output is
scaled by DAC U206 and output by driver U207.
U209 discriminates the zero crossings to provide a
TTL square wave at the reference frequency. This
is the TTL SYNC out as well as the feedback to
the phase lock loop in external reference mode.
I/O INTERFACE TO CPU BOARD
The I/O interface provides the communication

pathway between the DSP Logic Board and the
main CPU Board. U610 and U613 are buffers for
the address and data bus connections. Both buffer
chips are enabled only when the CPU Board is
writing to the DSP Logic Board. This helps isolate
the activity on the CPU Board from affecting cir-
cuitry on the DSP Logic Board. U608 and U609
are simple D-type latches used to hold configura-
tion data for the DSP Logic Board. U606 is the
main decoder PAL and generates all of the chip
selects and strobes needed by the DSP Logic
Board.
POWER
The bulk of the digital circuitry, the DSP and the

timing PALs and the interface circuits are all pow-
ered by +5V from the power supply board. The
7-6
Circuit Description
ANALOG INPUT BOARD

OVERVIEW and frequency adjustment. (60 Hz - depth:P222
and freq:P221 120 Hz - depth:P202 and
The Analog Input Board provides the very impor- freq:P201). The 120 Hz notch filter has a configur-
tant link between the user's input signal and the able gain of either 1 or 3.17.
DSP processor. From the front panel BNC, the
user's signal passes through a low distortion front- The notch filters are followed by two gain stages,
end amplifier, gain stages, notch filters, anti- each configurable up to a gain of 10.
aliasing filter, and finally an A/D Converter. Once
converted to digital form, the input signal is ready Overloads are sensed at the input amplifier and
to be processed by the Digital Signal Processor. the final amplifier outputs. Since there is no attenu-
ation in the amplifier chain, this is sufficient.
INPUT AMPLIFIER
ANTI-ALIASING FILTER
The goal of any measurement instrument is to per-
form some given measurement while affecting the To prevent aliasing, the input signal passes
quantities to be measured as little as possible. As through a low-pass filter so that all frequency com-
such, the input amplifier is often the most critical ponents greater than half the sampling frequency
stage in the entire signal path. The design of the are attenuated by at least 96 dB. This is accom-
front end input amplifier in the SR830 was driven plished with an 8-zero 9-pole elliptical low pass
by an effort to provide optimum performance in the filter. The pass band of this filter is DC to 102kHz.
following areas: input voltage noise, input current The stopband begins at 154 kHz. Stopband atten-
noise, input capacitance, harmonic distortion, and uation is nominally 100 dB.
common mode rejection (CMR). To provide such
performance, a FET input differential amplifier with The architecture of the filter is based on a singly
common-mode feedback architecture was chosen. terminated passive LC ladder filter. L's are simulat-
The input signal is first passed through a series of ed with active gyrators formed by op-amp pairs
relays to select input mode and input coupling. (U311, U321, U331, U341). Passive LC ladder fil-
The input FETs U100A and U100B are extremely ters have the special characteristic of being very
low-noise matched FETs. To improve distortion tolerant of variations in component values.
performance, the input FETs are cascoded to Because no section of the ladder is completely iso-
maintain a constant drain-source voltage across lated from the other, a change in value of any
each FET. This prevents modulation of the drain- single component affects the entire ladder. The
source voltage by the input voltage. U109 senses design of the LC ladder however, is such that the
the source voltages and maintains the same volt- characteristics of the rest of the ladder will shift to
age at the drains (via FETs U108A and B) with account for the change in such a way as to mini-
some DC offset determined by resistors N102 and mize its effect on the ladder. Not only does this
N103. U105 provides common-mode feedback loosen the requirement for extremely high accura-
and maintains a constant drain current in each cy resistors and capacitors, but it also makes the
FET. The gain of the front end is fixed. U103 pro- filter extremely stable despite wide temperature
vides the output. The DC offset is adjusted by variations. As such, the anti-aliasing filter used in
P101 and the CMR by P102. the SR830 does not ever require calibration to
meets its specifications.
GAIN STAGES AND NOTCH FILTERS
Following the anti-aliasing filter is the signal moni-
Collectively, the front end amplifier and following tor buffer (U386) and A/D driver stage (U301).
gain stages provide gain up to about 2000.
A/D CONVERTER
The notch filters are simple single stage, inverting
band pass filters summing with their inputs to The SR830 uses a dual channel A/D converter
remove 60 Hz or 120 Hz. Each filter has a depth (U407). Each channel samples simultaneously at
7-7
Circuit Description
a rate of 256 kHz. One channel is dedicated to the

input signal. The other channel reads one of the
Aux A/D inputs. The Aux inputs are multiplexed so
that each input is read every four cycles. The two
digital output streams are buffered by U406 and
sent to the DSP board.
I/O INTERFACE
The Analog Input Board communicates with the

CPU Board via its I/O Interface. U504 and U506
are simple latches which hold configuration data
for the analog board. They are written via the iso-
lated data bus from the DSP board. This data bus
is active only when the Analog board is
addressed. This prevents noise from the CPU and
DSP boards from entering the Analog Board.
Timing signals for the A/D Converter are buffered
by U406.
POWER
Several voltages are generated on the Analog

Input Board locally. ±15V is generated for most of
the analog IC's. A dedicated ±15V supply is also
generated for the front-end amplifier. ±5.6V is gen-
erated for the digital circuitry as well as some of
the drivers. The A/D Converter has its own ±5V
supply.
7-8
PARTS LIST
DSP Logic Board Parts List

REF. SRS PART# VALUE DESCRIPTION
C 101 5-00060-512 1.0U Cap, Stacked Metal Film 50V 5% -40/+85c
C 114 5-00100-517 2.2U Capacitor, Tantalum, 35V, 20%, Rad
C 119 5-00259-501 .002U Capacitor, Ceramic Disc, 50V, 10%, SL
C 120 5-00092-523 1P Capacitor, Silver Mica, Miniature
C 121 5-00023-529 .1U Cap, Monolithic Ceramic, 50V, 20%, Z5U
C 135 5-00002-501 100P Capacitor, Ceramic Disc, 50V, 10%, SL
C 140 5-00053-512 .033U Cap, Stacked Metal Film 50V 5% -40/+85c
C 143 5-00121-566 .0047U Cap, Polyester Film 50V 5% -40/+85c Rad
C 180 5-00038-509 10U Capacitor, Electrolytic, 50V, 20%, Rad
C 202 5-00148-545 1000P Capacitor, Monolithic Ceramic, COG, 1%
7-9
PARTS LIST
7-10
PARTS LIST
C 450 5-00098-517 10U Capacitor, Tantalum, 35V, 20%, Rad
C 601 5-00027-503 .01U Capacitor, Ceramic Disc, 50V, 20%, Z5U
C 604 5-00239-562 680P Cap., NPO Monolithic Ceramic, 50v, 5% Ra
C 650 5-00225-548 .1U AXIAL Capacitor, Ceramic, 50V,+80/-20% Z5U AX
CU401 5-00002-501 100P Capacitor, Ceramic Disc, 50V, 10%, SL
CU402 5-00002-501 100P Capacitor, Ceramic Disc, 50V, 10%, SL
CX623 5-00225-548 .1U AXIAL Capacitor, Ceramic, 50V,+80/-20% Z5U AX
D 103 3-00465-301 MV209 Diode
D 104 3-00004-301 1N4148 Diode
D 105 3-00004-301 1N4148 Diode
D 180 3-00004-301 1N4148 Diode
D 181 3-00004-301 1N4148 Diode
D 280 3-00004-301 1N4148 Diode
D 281 3-00004-301 1N4148 Diode
JP301 1-00035-130 20 PIN DIL Connector, Male
K 101 3-00196-335 HS-212S-5 Relay
7-11
PARTS LIST
K 201 3-00444-335 BS-211-DC5 GF Relay
L 101 6-00107-606 .8UH Inductor, Variable
L 601 6-00006-602 33U Inductor, Radial
N 101 4-00693-421 270X5 Res. Network, SIP, 1/4W,2% (Isolated)
N 102 4-00690-421 3.3KX4 Res. Network, SIP, 1/4W,2% (Isolated)
N 420 4-00244-421 10KX4 Res. Network, SIP, 1/4W,2% (Isolated)
N 502 4-00334-425 10KX5 Resistor Network SIP 1/4W 2% (Common)
N 601 4-00767-420 270X8 Resistor Network, DIP, 1/4W,2%,8 Ind
PC1 7-00356-701 L/I DIGITAL Printed Circuit Board
Q 101 3-00021-325 2N3904 Transistor, TO-92 Package
R 102 4-00022-401 1.0M Resistor, Carbon Film, 1/4W, 5%
R 103 4-00130-407 1.00K Resistor, Metal Film, 1/8W, 1%, 50PPM
R 114 4-00056-401 22 Resistor, Carbon Film, 1/4W, 5%
R 115 4-00142-407 100K Resistor, Metal Film, 1/8W, 1%, 50PPM
R 118 4-00193-407 499 Resistor, Metal Film, 1/8W, 1%, 50PPM
R 120 4-00074-401 33K Resistor, Carbon Film, 1/4W, 5%
R 173 4-00292-401 1.1K Resistor, Carbon Film, 1/4W, 5%
7-12
PARTS LIST
R 180 4-00781-402 56 Resistor, Carbon Comp, 1/2W, 5%
R 203 4-00771-407 66.5 Resistor, Metal Film, 1/8W, 1%, 50PPM
R 205 4-00409-408 1.210K Resistor, Metal Film, 1/8W, 0.1%, 25ppm
R 226 4-00782-448 54.9 Resistor, Metal Film, 1W, 1%,
R 228 4-00704-407 54.9 Resistor, Metal Film, 1/8W, 1%, 50PPM
R 385 4-00795-412 24 Resistor, Carbon Film 1/2W 5%
R 386 4-00795-412 24 Resistor, Carbon Film 1/2W 5%
7-13
PARTS LIST
RX623 4-00053-401 200 Resistor, Carbon Film, 1/4W, 5%
T 201 6-00137-601 15MH Inductor
TP101 1-00143-101 TEST JACK Vertical Test Jack
U 101 3-00461-340 OPA2604 Integrated Circuit (Thru-hole Pkg)
U 103 3-00211-340 LT1016 Integrated Circuit (Thru-hole Pkg)
U 104 3-00262-340 74HC86 Integrated Circuit (Thru-hole Pkg)
U 110 3-00437-340 AD9696KN Integrated Circuit (Thru-hole Pkg)
7-14
PARTS LIST
U 111 6-00110-621 30.208 MHZ Crystal Oscillator
U 120 3-00238-340 74F74 Integrated Circuit (Thru-hole Pkg)
U 121 3-00238-340 74F74 Integrated Circuit (Thru-hole Pkg)
U 180 3-00116-325 78L05 Transistor, TO-92 Package
U 201 3-00130-340 5532A Integrated Circuit (Thru-hole Pkg)
U 206 3-00058-340 AD7524 Integrated Circuit (Thru-hole Pkg)
U 207 3-00383-340 LM6321 Integrated Circuit (Thru-hole Pkg)
U 209 3-00211-340 LT1016 Integrated Circuit (Thru-hole Pkg)
U 301 3-00087-340 LF347 Integrated Circuit (Thru-hole Pkg)
U 380 3-00149-329 LM317T Voltage Reg., TO-220 (TAB) Package
U 401 3-00328-340 PCM1700P Integrated Circuit (Thru-hole Pkg)
U 402 3-00328-340 PCM1700P Integrated Circuit (Thru-hole Pkg)
U 501 3-00611-360 DSP56002FC-40 Integrated Circuit (Surface Mount Pkg)
U 601 3-00495-343 SR850 U601 GAL/PAL, I.C.
U 602 3-00496-343 SR850 U602 GAL/PAL, I.C.
U 603 3-00497-343 SR850 U603 GAL/PAL, I.C.
U 604 3-00498-343 SR850 U604 GAL/PAL, I.C.
U 606 3-00499-343 SR850 U606 GAL/PAL, I.C.
U 622 3-00491-340 UPD71054C Integrated Circuit (Thru-hole Pkg)
Z0 0-00012-007 TO-220 Heat Sinks
7-15
PARTS LIST
Z0 0-00043-011 4-40 KEP Nut, Kep
Z0 0-00373-000 CARD EJECTOR Hardware, Misc.
Z0 0-00388-000 RCA PHONO Hardware, Misc.
Z0 0-00438-021 4-40X5/16PP Screw, Panhead Phillips
Analog Input Board Parts List

C102 5-00183 .1U - 2% Capacitor, Polypropylene, Rad
C103 5-00183 .1U - 2% Capacitor, Polypropylene, Rad
C104 5-00159 6.8P Capacitor, Ceramic, 50V, 10%, SL, Rad
C106 5-00100 2.2U Capacitor, Tantalum, 35V, 10%, Rad
C111 5-00023 .1U Capacitor, Mono, 50V, 20%, Z5U, Rad
C150 5-00098 10U Capacitor, Tantalum, 35V, 10%, Rad
C180 5-00038 10U Capacitor, Electrolytic, 50V, 20%, Rad
C181 5-00038 10U Capacitor, Electrolytic, 50V, 20%, Rad
C199 5-00233 22P Capacitor, Ceramic, 50V, 10%, NPO, Rad
C201 5-00060 1.0U Cap, Stacked Metal Film, 50V, 5%, -40/+85c
C225 5-00007 220P Capacitor, Ceramic, 50V, 10%, SL, Rad
C311 5-00148 1000P - 50V Capacitor, Mono, 1%, COG, Rad
C362 0-00772 1.5" WIRE
C363 5-00022 .001U - Y5P Capacitor, Ceramic, 50V, 10%, SL, Rad
7-16
PARTS LIST
D101 3-00489 1N5232 5.6V, 500 mW, DO-35 ZENER DIODE
D180 3-00004 1N4148 1N4148, 75V, 300mA, 4nS DIODE
D181 3-00004 1N4148 1N4148, 75V, 300mA, 4nS DIODE
D480 3-00004 1N4148 1N4148, 75V, 300mA, 4nS DIODE
D481 3-00004 1N4148 1N4148, 75V, 300mA, 4nS DIODE
J101 0-00388 RCA PHONO
J102 0-00388 RCA PHONO
JP201 1-00006 2 PIN DI Header, SIM
JP221 1-00006 2 PIN DI Header, SIM
JP401 1-00184 32 PIN DIL Header, DIM, Latching Clips
K101 3-00196 HS-212S-5 HS-212S-5, DPDT, 12V
7-17
PARTS LIST
K102 3-00444 BS-211-DC5 GF HS-211-5, SPDT 5V
K103 3-00444 BS-211-DC5 GF HS-211-5, SPDT 5V
K104 3-00196 HS-212S-5 HS-212S-5, DPDT, 12V
K105 3-00444 BS-211-DC5 GF HS-211-5, SPDT 5V
L501 6-00734 33UH
N101 4-00560 47KX3 Network, SIP, Isolated, 1/4W, 2%, 200 ppm
N103 4-00497 1.5KX4 Network, SIP, Isolated, 1/4W, 2%, 200 ppm
N401 4-00756 1.0MX4 Network, SIP, Isolated, 1/4W, 2%, 200 ppm
N403 4-00756 1.0MX4 Network, SIP, Isolated, 1/4W, 2%, 200 ppm
N405 4-00694 270X4 Network, SIP, Isolated, 1/4W, 2%, 200 ppm
N406 4-00694 270X4 Network, SIP, Isolated, 1/4W, 2%, 200 ppm
N501 4-00758 15KX5 Network, SIP, Common, 1/4W 2%, 200ppm
P101 4-00015 100K Pot, Multi Turn, Side Adjust
P102 4-00354 20 Pot, Multi Turn, Side Adjust
P103 4-00015 100K Pot, Multi Turn, Side Adjust
PC1 7-00355 L/I ANALOG
R101 4-00021 1.0K Resistor, Carbon Film, 1/4W, 5%
R102 4-00131 1.00M Resistor, Metal Film, 1/8W, 1%, 50PPM
R103 4-00306 100M Resistor, Metal Film, 1/8W, 1%, 100PPM
R104 4-00034 10K Resistor, Carbon Film, 1/4W, 5%
R106 4-00191 49.9 Resistor, Metal Film, 1/8W, 1%, 50PPM
R110 4-00192 49.9K Resistor, Metal Film, 1/8W, 1%, 50PPM
R111 4-02471 768
R114 4-02471 768
R115 4-02479 130 OHM - 0.1%
R119 4-02471 768
R120 4-02479 130 OHM - 0.1%
R124 4-02471 768
R125 4-00030 10 Resistor, Carbon Film, 1/4W, 5%
R126 4-00142 100K Resistor, Metal Film, 1/8W, 1%, 50PPM
7-18
PARTS LIST
R199 4-00720 115 Resistor, Metal Film, 1/8W, 1%, 50PPM
R301 4-00066 3.3M Resistor, Carbon Film, 1/4W, 5%
R307 4-00217 1.000K Resistor, Metal Film, 1/8W, 0.1%, 25ppm
7-19
PARTS LIST
R480 4-00108 150 Resistor, Carbon Comp, 1/2W, 5%
7-20
PARTS LIST
SO101 1-00173 8 PIN MACH DIP Socket, 8 Pin Machined
SO102 1-01098 917-93-108-41
SO108 1-01098 917-93-108-41
SO361 1-00173 8 PIN MACH DIP Socket, 8 Pin Machined
TP101 1-00143 TEST JACK Vertical Test Jack
Low noise 10nV/Hz , low drift 1uV/C FET op
U101 3-00494 LT1793CN8 amp
U102 3-01674 LSK389B
U103 3-00423 5534A 5534 low noise op-amp
Low Power Low Offset Voltage Dual
U104 3-00143 LM393 Comparator
Dual FET-Input, Low Distortion Operational
U105 3-00461 OPA2604 Amplifier
LM393 Low Power Low Offset Voltage Dual
U108 3-01674 LSK389B
U180 3-00118 78L15 78L15, +15V, LOW POWER REGULATOR
U181 3-00124 79L15 79L15, -15V LOWER POWER REGULATOR
74HC4053, Triple 2-Channel Analog
U202 3-00385 74HC4053 Multiplexer
7-21
PARTS LIST
U241 3-00385 74HC4053 Triple 2-Channel Analog Multiplexer
5532A, Internally Compensated Dual Low
U301 3-00130 5532A Noise Op-Amp
U303 3-00130 5532A Noise Op-Amp
U304 3-00130 5532A Noise Op-Amp
U311 3-00130 5532A Noise Op-Amp
U321 3-00130 5532A Noise Op-Amp
U331 3-00130 5532A Noise Op-Amp
U341 3-00130 5532A Noise Op-Amp
U361 3-00089 LF357 Wideband JFET OpAmp
U362 3-00089 LF357 Wideband JFET OpAmp
U371 3-00130 5532A Noise Op-Amp
U381 3-00130 5532A Noise Op-Amp
LF353 Wide bandwitdh Dual JFET Input
U391 3-00088 LF353 OpAmp
LF347 Wide bandwidth Quad JFET Input
U401 3-00087 LF347 OpAmp
U402 3-00402 74HC4052 74HC4052, Dual 4-Channel Analog Multiplexer
U406 3-00155 74HC04 74HC04, Hex Inverter
U407 3-00392 PCM1750P Dual 18- Bit CMOS Monolithic Audio ADC
U480 3-00116 78L05 78L05, +5V, LOW POWER REGULATOR
U481 3-00122 79L05 79L05, -5V LOW POWER REGULATOR
U504 3-00411 74HC273 Octal D Flip-Flops with Clear
U506 3-00411 74HC273 Octal D Flip-Flops with Clear
U508 3-00149 LM317T ADJUSTABLE POSITIVE REGULATOR
U509 3-00141 LM337T THIN ADJUSTABLE NEGATIVE REGULATOR
U510 3-00149 LM317T ADJUSTABLE POSITIVE REGULATOR
U511 3-00141 LM337T THIN ADJUSTABLE NEGATIVE REGULATOR
NPN BJT (tansistor) array, common collector,
U530 3-00195 CA3082 100mA Ic, 0.4v Vsat
Z0 1-00087 2 PIN JUMPER 2 PIN JUMPER
7-22
PARTS LIST
Z1 0-00043 4-40 KEP
Z2 0-00187 4-40X1/4PP
Z3 0-00243 TO-220
Z4 0-00373 CARD EJECTOR
CPU and Power Supply Parts List

BT701 6-00001-612 BR-2/3A 2PIN PC Battery
C1 5-00124-526 5600U Capacitor, Electrolytic, 35V, 20%, Rad
C7 5-00023-529 .1U Cap, Monolythic Ceramic, 50V, 20%, Z5U
C 19 5-00192-542 22U MIN Cap, Mini Electrolytic, 50V, 20% Radial
C 103 5-00028-507 100P Capacitor, Ceramic Disc,250V, 10%, Y5P
C 903 5-00022-501 .001U Capacitor, Ceramic Disc, 50V, 10%, SL
7-23
PARTS LIST
D2 3-00391-301 MBR360 Diode
D3 3-00391-301 MBR360 Diode
D4 3-00391-301 MBR360 Diode
D5 3-00391-301 MBR360 Diode
D6 3-00391-301 MBR360 Diode
D7 3-00391-301 MBR360 Diode
D8 3-00391-301 MBR360 Diode
D9 3-00391-301 MBR360 Diode
D 15 3-00391-301 MBR360 Diode
D 16 3-00001-301 1N4001 Diode
D 18 3-00001-301 1N4001 Diode
D 19 3-00001-301 1N4001 Diode
D 20 3-00001-301 1N4001 Diode
D 30 3-00479-301 MUR410 Diode
D 31 3-00479-301 MUR410 Diode
D 32 3-00479-301 MUR410 Diode
D 33 3-00479-301 MUR410 Diode
D 34 3-00391-301 MBR360 Diode
D 35 3-00391-301 MBR360 Diode
D 36 3-00391-301 MBR360 Diode
D 37 3-00391-301 MBR360 Diode
D 38 3-00001-301 1N4001 Diode
D 401 3-00004-301 1N4148 Diode
D 701 3-00203-301 1N5711 Diode
DS1 3-00011-303 RED LED, T1 Package
JP4 1-00171-130 34 PIN ELH Connector, Male
JP302 0-00772-000 1.5" WIRE Hardware, Misc.
7-24
PARTS LIST
JP902 1-00160-162 IEEE488/STAND. Connector, IEEE488, Standard, R/A, Femal
JP903 1-00016-160 RS232 25 PIN D Connector, D-Sub, Right Angle PC, Female
L1 0-00772-000 1.5" WIRE Hardware, Misc.
LS701 6-00096-600 MINI Misc. Components
PC1 7-00512-701 SR810/830 CPU Printed Circuit Board
Q3 3-00021-325 2N3904 Transistor, TO-92 Package
Q4 3-00021-325 2N3904 Transistor, TO-92 Package
R3 4-00034-401 10K Resistor, Carbon Film, 1/4W, 5%
R6 4-00046-401 2.0M Resistor, Carbon Film, 1/4W, 5%
R7 4-00065-401 3.3K Resistor, Carbon Film, 1/4W, 5%
SO101 1-00108-150 PLCC 68 TH Socket, THRU-HOLE
SO303 1-00156-150 32 PIN 600 MIL Socket, THRU-HOLE
SO304 1-00156-150 32 PIN 600 MIL Socket, THRU-HOLE
SW1 2-00039-218 SR810/830 Switch, Panel Mount, Power, Rocker
7-25
PARTS LIST
T1 1-00152-116 11 PIN, WHITE Header, Amp, MTA-156
U1 3-00039-340 74HC14 Integrated Circuit (Thru-hole Pkg)
U3 3-00549-329 LT1085CT-5 Voltage Reg., TO-220 (TAB) Package
U4 3-00550-329 LT1086CT-5 Voltage Reg., TO-220 (TAB) Package
U5 3-00119-329 7905 Voltage Reg., TO-220 (TAB) Package
U9 3-00149-329 LM317T Voltage Reg., TO-220 (TAB) Package
U 101 3-00354-360 80C186-12 Integrated Circuit (Surface Mount Pkg)
U 201 3-00340-340 74ALS373 Integrated Circuit (Thru-hole Pkg)
U 401 3-00551-341 128KX8-70 STATIC RAM, I.C.
U 402 3-00551-341 128KX8-70 STATIC RAM, I.C.
U 601 3-00467-340 74HCT74 Integrated Circuit (Thru-hole Pkg)
U 701 3-00051-340 74HCU04 Integrated Circuit (Thru-hole Pkg)
U 705 3-00110-340 MC1489 Integrated Circuit (Thru-hole Pkg)
U 902 3-00645-340 NAT9914BPD Integrated Circuit (Thru-hole Pkg)
U 903 3-00078-340 DS75160A Integrated Circuit (Thru-hole Pkg)
U 904 3-00079-340 DS75161A Integrated Circuit (Thru-hole Pkg)
U 905 3-00247-340 SCN2641 Integrated Circuit (Thru-hole Pkg)
U 906 3-00109-340 MC1488 Integrated Circuit (Thru-hole Pkg)
X 101 6-00068-620 24.000 MHZ Crystal
X 902 6-00037-620 3.6864 MHZ Crystal
Z0 0-00158-070 60MM 24V Fans, & Hardware
Z0 0-00186-021 6-32X1-3/8PP Screw, Panhead Phillips
Z0 0-00231-043 1-32, #4 SHOULD Washer, nylon
Z0 0-00246-043 #8 X 1/16 Washer, nylon
Z0 0-00316-003 PLTFM-28 Insulators
Z0 0-00477-021 8-32X1/2 Screw, Panhead Phillips
Z0 5-00262-548 .01U AXIAL Capacitor, Ceramic, 50V,+80/-20% Z5U AX
Z0 7-00501-720 SR830-8 Fabricated Part
7-26
PARTS LIST
Front Panel Display Board Parts List

B1 3-00546-340 HDSP-4830 Integrated Circuit (Thru-hole Pkg)
C1 5-00023-529 .1U Cap, Monolithic Ceramic, 50V, 20%, Z5U
CX30 5-00219-529 .01U Cap, Monolithic Ceramic, 50V, 20%, Z5U
D1 3-00884-306 RED LED, Rectangular
7-27
PARTS LIST
D2 3-00885-306 YELLOW LED, Rectangular
D7 3-00547-310 RED COATED LED, Coated Rectangular
D 10 3-00547-310 RED COATED LED, Coated Rectangular
D 19 3-00884-306 RED LED, Rectangular
D 20 3-00885-306 YELLOW LED, Rectangular
D 49 3-00575-311 GREEN MINI LED, Subminiature
7-28
PARTS LIST
D 54 3-00576-311 RED MINI LED, Subminiature
7-29
PARTS LIST
D 125 3-00004-301 1N4148 Diode
D 126 3-00004-301 1N4148 Diode
D 127 3-00004-301 1N4148 Diode
D 128 3-00004-301 1N4148 Diode
D 129 3-00004-301 1N4148 Diode
D 130 3-00004-301 1N4148 Diode
D 131 3-00004-301 1N4148 Diode
D 132 3-00004-301 1N4148 Diode
J1 1-00202-131 36 PIN SI SOCK Connector, Female
J6 1-00204-130 36 PIN SI Connector, Male
J 10 1-00205-130 12 PIN SI Connector, Male
J 2001 1-00010-130 20 PIN ELH Connector, Male
J 2002 1-00171-130 34 PIN ELH Connector, Male
J 2003 1-00181-165 9 PIN STRAIGHT Connector, D-Sub, Female
JP5 1-00138-130 5 PIN SI Connector, Male
N1 4-00468-420 300X8 Resistor Network, DIP, 1/4W,2%,8 Ind
7-30
PARTS LIST
N 11 4-00421-420 220X7 Resistor Network, DIP, 1/4W,2%,8 Ind
N 13 4-00263-425 1.0KX7 Resistor Network SIP 1/4W 2% (Common)
PC1 7-00492-701 SR830 DISPLAY Printed Circuit Board
PC2 7-00493-701 SR830 KPD BD Printed Circuit Board
PC3 7-00437-701 FFT/DSP LI Printed Circuit Board
PC4 7-00513-701 SR810/830 AB IN Printed Circuit Board
PC5 7-00514-701 SR830 RP INPUT Printed Circuit Board
Q1 3-00264-340 MPQ3467 Integrated Circuit (Thru-hole Pkg)
Q2 3-00264-340 MPQ3467 Integrated Circuit (Thru-hole Pkg)
R1 4-00142-407 100K Resistor, Metal Film, 1/8W, 1%, 50PPM
U1 3-00064-340 CA3081 Integrated Circuit (Thru-hole Pkg)
U2 3-00401-340 74HCT244 Integrated Circuit (Thru-hole Pkg)
U6 3-00199-340 74HC4538 Integrated Circuit (Thru-hole Pkg)
U 14 3-00289-340 HDSP-H107 Integrated Circuit (Thru-hole Pkg)
Z0 0-00014-002 6J4 Power Entry Hardware
Z0 0-00025-005 3/8" Lugs
Z0 0-00043-011 4-40 KEP Nut, Kep
Z0 0-00079-031 4-40X3/16 M/F Standoff
7-31
PARTS LIST
Z0 0-00084-032 36154 Termination
Z0 0-00089-033 4" Tie
Z0 0-00097-040 #6 FLAT Washer, Flat
Z0 0-00100-040 1/4X1/16 Washer, Flat
Z0 0-00104-043 #4 NYLON Washer, nylon
Z0 0-00108-054 1" #26 Wire #26 UL1061
Z0 0-00122-053 2-1/4" #24 Wire #24 UL1007 Strip 1/4x1/4 Tin
Z0 0-00125-050 3" #18 Wire #18 UL1007 Stripped 3/8x3/8 No Tin
Z0 0-00126-053 3-1/2" #24 Wire #24 UL1007 Strip 1/4x1/4 Tin
Z0 0-00127-050 4" #18 Wire #18 UL1007 Stripped 3/8x3/8 No Tin
Z0 0-00130-050 5-5/8" #18 Wire #18 UL1007 Stripped 3/8x3/8 No Tin
Z0 0-00149-020 4-40X1/4PF Screw, Flathead Phillips
Z0 0-00212-021 6-32X2PP Screw, Panhead Phillips
Z0 0-00256-043 #6 SHOULDER Washer, nylon
Z0 0-00257-000 HANDLE3 Hardware, Misc.
Z0 0-00259-021 4-40X1/2"PP Screw, Panhead Phillips
Z0 0-00310-010 HEX 3/8-32 Nut, Hex
Z0 0-00351-029 4-40X1/4TRUSSPH Screw, Truss Phillips
Z0 0-00372-000 BE CU / FFT Hardware, Misc.
Z0 0-00377-004 SR760/830/780 Knobs
Z0 0-00378-004 CAP 760/830/780 Knobs
Z0 0-00382-000 CARD GUIDE 4.5" Hardware, Misc.
Z0 0-00389-000 PHONO PLUG Hardware, Misc.
Z0 0-00390-024 1-72X1/4 Screw, Slotted
Z0 0-00391-010 1-72X5/32X3/64 Nut, Hex
Z0 0-00407-032 SOLDR SLV RG174 Termination
Z0 0-00418-000 CLIP, CABLE Hardware, Misc.
Z0 0-00455-020 6-32X3/8PF UNC Screw, Flathead Phillips
Z0 0-00481-000 BUMPER/CORD WRP Hardware, Misc.
Z0 0-00482-043 3/8X1/2X1/16THK Washer, nylon
Z0 0-00483-000 FAN GUARD III Hardware, Misc.
Z0 0-00484-000 CABLE Hardware, Misc.
Z0 0-00485-057 GROMMET Grommet
Z0 0-00486-000 CABLE Hardware, Misc.
Z0 0-00491-005 #10 SOLDER Lugs
Z0 0-00492-026 6-32X1/2FP BLK Screw, Black, All Types
Z0 0-00500-000 554808-1 Hardware, Misc.
Z0 0-00525-050 8-1/4" #18 Wire #18 UL1007 Stripped 3/8x3/8 No Tin
Z0 0-00590-066 0097-0555-02 Copper Foil Tape, Self Adhesive
Z0 0-00893-026 8-32X3/8PF Screw, Black, All Types
Z0 1-00073-120 INSL Connector, BNC
Z0 1-00132-171 34 COND Cable Assembly, Ribbon
Z0 1-00153-113 11 PIN,18AWG/OR Connector, Amp, MTA-156
Z0 1-00223-141 BULKHEAD JACK SMB Connector
7-32
PARTS LIST
Z0 1-00224-141 STRAIGHT PLUG SMB Connector
Z0 1-00225-169 26/40 IDC-40 CE Cable Assembly, Custom
Z0 1-00226-169 34/60 IDC-60 CE Cable Assembly, Custom
Z0 2-00034-220 ENA1J-B20 SOFTPOT
Z0 4-00681-436 SG240 Thermistor, ICL (Inrush Current Limiter)
Z0 5-00134-529 100P Cap, Monolythic Ceramic, 50V, 20%, Z5U
Z0 6-00004-611 1A 3AG Fuse
Z0 6-00089-610 PLTFM II Transformer
Z0 6-00212-630 1"X.25"CYL Ferrite Beads
Z0 6-00214-630 .5"X.25"CYL Ferrite Beads
Z0 7-00124-720 TRANSCOVER2-MOD Fabricated Part
Z0 7-00497-740 SR830-1 Keypad, Conductive Rubber
Z0 7-00499-735 SR830-4/-5 Injection Molded Plastic
Z0 7-00500-709 SR830 Lexan Overlay
Z0 7-00502-721 SR830-9 Machined Part
Z0 7-00507-709 SR810/830 RP Lexan Overlay
Z0 7-00510-720 SR830-18/SR810 Fabricated Part
Z0 9-00267-917 GENERIC Product Labels
Z0 9-00552-924 COPPERFOIL;1" Tape, All types
Z1 1-00141-171 5 PIN SIL Cable Assembly, Ribbon
Miscellaneous Parts List

U 303 3-00345-342 27C512-120 EPROM/PROM, I.C.
U 304 3-00345-342 27C512-120 EPROM/PROM, I.C.
Z0 0-00179-000 RIGHT FOOT Hardware, Misc.
Z0 0-00180-000 LEFT FOOT Hardware, Misc.
Z0 0-00204-000 REAR FOOT Hardware, Misc.
Z0 0-00248-026 10-32X3/8TRUSSP Screw, Black, All Types
Z0 0-00315-021 6-32X7/16 PP Screw, Panhead Phillips
Z0 7-00147-720 BAIL Fabricated Part
Z0 7-00580-709 SR830-22 Lexan Overlay
7-33
PARTS LIST
NOTICE: Schematics may not show current part numbers or values. Refer to parts
list for current part numbers or values.
7-34

Model Sr830: DSP Lock-In Amplifier

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Model Sr830: DSP Lock-In Amplifier

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MODEL SR830

DSP Lock-In Amplifier

1290-D Reamwood Avenue

Copyright © 1993, 2011 by SRS, Inc.

Revision 2.5 (10/2011)

GENERAL INFORMATION REAR PANEL

SR830 BASICS PROGRAMMING

Conversion to other AC input voltages requires a ENVIRONMENTAL CONDITIONS

Caution - risk of electric shock

Frame or chassis terminal

Caution - refer to accompanying documents

Earth (ground) terminal

INPUTS AND OUTPUTS

REFERENCE and PHASE page description

INPUT and FILTER page description

GAIN and TIME CONSTANT page description

DISPLAY and OUTPUT page description

AUX INPUT/OUTPUT page description

SETUP page description

AUTO FUNCTIONS page description

DATA STORAGE page description

DATA TRANSFER page description

INTERFACE page description

STATUS page description

STATUS BYTE DEFINITIONS

SERIAL POLL STATUS BYTE (5-21) LIA STATUS BYTE (5-23)

bit name usage bit name usage

STANDARD EVENT STATUS BYTE (5-22) ERROR STATUS BYTE (5-23)

bit name usage bit name usage

YOUR FIRST MEASUREMENTS

THE BASIC LOCK-IN

The Channel 1 display shows X and Channel 2

The input impedance of the lock-in is 10 MΩ. The

The sine amplitude is 1.000 Vrms and the

3. Press [Auto Phase] Automatically adjust the reference phase shift to

4. Press [Phase] Display the reference phase shift in the Reference

The knob is used to adjust parameters which are

Use the Auto Phase function to return Y to zero

Show the internal oscillator frequency in the

The knob now adjusts the frequency. The meas-

The internal oscillator is crystal synthesized with

Show the sine output amplitude in the Reference

As the amplitude is changed, the measured value

The Auto Gain function will adjust the sensitivity so

Parameters which have many options, such as

The values of X and Y become noisy. This is

Let's leave the time constant short and change the

Parameters which have only a few values, such as

The X and Y outputs are somewhat noisy at this

The outputs are less noisy with 2 poles of filtering.

Let's leave the filtering short and the outputs noisy

Show the internal reference frequency on the

This turns on synchronous filtering whenever the

The outputs are now very quiet and steady, even

This concludes this measurement example. You

The Channel 1 display shows X and Channel 2

The internal oscillator is crystal synthesized so

3. Press [Freq] Show the internal oscillator frequency on the

should now oscillate at about 0.2 Hz (the accuracy