Received 15 May 2023, accepted 5 June 2023, date of publication 9 June 2023, date of current version 16 June 2023.

Digital Object Identifier 10.1109/ACCESS.2023.3285113

AMS Circuit Design Optimization Technique

Based on ANN Regression Model
With VAE Structure
JIN-WON HYUN AND JAE-WON NAM , (Member, IEEE)
Department of Electronic Engineering, Seoul National University of Science and Technology, Seoul 01811, South Korea
Corresponding author: Jae-Won Nam ([email protected])
This work was supported in part by the Ministry of Science and Information and Communications Technology (MSIT), South Korea,
through the Information Technology Research Center (ITRC) Support Program, Supervised by the Institute for Information and
Communications Technology Planning and Evaluation (IITP), under Grant IITP-2023-RS-2022-00156295.

ABSTRACT The advanced design of an analog mixed-signal circuit is not simple enough to meet the
requirements of the performance matrix as well as robust operations under process-voltage-temperature
(PVT) changes. Even commercial products demand stringent specifications while maintaining the system’s
performance. The main objectives of this study are to increase the efficiency of the design optimization
process by configuring the design process in multiple regression modeling stages, to characterize our target
circuit into a regression model including PVT variations, and to enable a search for co-optimum design
points while simultaneously checking performance sensitivity. We used an artificial neural network (ANN)
to develop a regression model and divided the ANN modeling process into coarse and fine simulation steps.
In addition, we applied a variational autoencoder (VAE) structure to the ANN model to reduce the training
error due to an insufficient input sample. According to the proposed algorithm, the AMS circuit designer
can quickly search for the co-optimum point, which results in the best performance, while the least sensitive
operation as the design process uses a regression model instead of launching heavy SPICE simulations.
In this study, a voltage-controlled oscillator (VCO) is selected to prove the proposed algorithm. Under
various design conditions (CMOS 180 nm, 65 nm, and 45 nm processes), we proceed with the proposed
design flow to obtain the best performance score that can be evaluated by a figure-of-merit (FoM). As a
result, the proposed regression model-based design flow achieves twice accurate results in comparison to
that of the conventional single-step design flow.

INDEX TERMS Analog circuit design automation, variational-autoencoder, regression model, artificial-
neural-network, voltage-controlled-oscillator.

I. INTRODUCTION reduced by shortening the transistor length. Also, in the case

With advancements in semiconductor processing technology, of digital circuits, the performance of transistors improves as
high-performance digital processing can be applied for rea- the processing unit decreases. Therefore, as the process tech-
sons such as significant power loss reduction, high operating nology has developed to a few nanometers, the performance
frequency, and area reduction. The finer the process, the lower of digital circuits has improved significantly. In addition, even
the supply voltage that can be applied, and the shorter the if the process is different, the logic structure of the digital
minimum length of the transistor. And power consumption is circuit has the same structure, and because the digital circuit
reduced by the square of the supply voltage, and the area is has binary inputs and outputs, it is robust against noise. For
this reason, if only a standard cell is made, various circuits
The associate editor coordinating the review of this manuscript and can be easily implemented because there are few variables to
approving it for publication was Ludovico Minati . be adjusted.
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.
58850 For more information, see https://creativecommons.org/licenses/by-nc-nd/4.0/ VOLUME 11, 2023
J.-W. Hyun, J.-W. Nam: AMS Circuit Design Optimization Technique

Digital circuit design has standardized design automation

with a programming language. Because the circuit is gener-
ated by matching it with the programming language, even
if the processing unit is different, it can be expressed at the
same logic level. This has the advantage of easy migration of
the circuits to another process. Design automation is made
possible by the synthesis step that converts the HDL code
into a digital logic circuit, and the place and route steps that
design the layout using algorithms such as the Kernighan-Lin
algorithm or Fiduccia-Mattheyses algorithm. Based on this
FIGURE 1. ANN regression model structure.
design flow, many design automation algorithms have been
implemented for digital circuit design [1].
The characteristics and performance of Metal-Oxide-
Silicon Field-Effect-Transistor (MOSFET) vary depending II. METHOD
on the process technology node. In addition, the mismatch In analog circuit design automation, reducing computer pro-
between transistors becomes more severe as the process pro- cessing time is an important task. if it is much slower
gresses to a smaller length of the MOSFET [2]. Accord- than the designer’s direct optimization design time without
ingly, when designing an analog circuit, correction circuits design automation, there is no advantage to design automa-
that compensate for this mismatch are added. In the case tion. Therefore, to reduce the computer processing time,
of the latest process, the correction circuit is almost indis- the machine learning model structure and algorithms are
pensable owing to a severe mismatch. Because of various developed.
other problems, analog design flow is redesigned based on
the designer’s experience [1]. This is because in the heuristic A. ANN REGRESSION MODEL STRUCTURE
design method, even experienced designers may not recog- In this study, a regression model trained using simulation data
nize or misplace optimization points. In addition, analog cir- finds an optimization point. The simulation data consist of
cuit design has many variables to consider compared to digital the results concerning specific points discretely partitioned
circuit design, so there are many difficulties in developing the within the entire range. A parametric search through SPICE
automated design of analog circuits. Although research on simulation shows detailed performance results over the entire
the automation of analog circuit design is in progress, much range. However, the design time will increase infinitely.
more computer processing time is required than digital design To address the issue of time constraints, we utilize a regres-
time. sion model that interpolates simulation results at desired
The purpose of this research is to reduce the time required design points. Furthermore, considering the limited availabil-
to automate the optimization design with Analog and Mixed- ity of training data for the regression model, an Artificial Neu-
Signal (AMS) circuits and to obtain more accurate results. ral Network (ANN) model is deemed more appropriate than a
We implemented an algorithm for automatic circuit design deep learning model like a Recurrent Neural Network (RNN),
utilizing the zoom-in algorithm proposed by Hyun and Nam Convolutional Neural Network (CNN), or Deep Neural Net-
[3], along with a regression model and a variational autoen- work (DNN) [4]. The process of training the ANN regression
coder structure. The proposed algorithm is applied to the model is optimized using the MSE-type loss function and the
automated design of a voltage-controlled oscillator (VCO) Adam optimizer, as defined in Algorithm 1.
that consists of a ring oscillator circuit. It is designed to verify Fig. 1 illustrates the structure of the ANN regression
the range of design parameters that the designer may not model. It consists of three layers: an input layer, a hid-
recognize. If the amount of data is increased based on the den layer, and an output layer. The input layer represents
proposed algorithm, high accuracy can be obtained. However, the design parameters, while the output layer represents the
we aim to design automation with less computer processing desired design specifications. The hidden layer refers to
time than that in previous studies. To realize this, we train the layer excluding the input and output layers. The size of
a regression model using the zoom-in algorithm. And we the hidden layer depends on the dataset size. If the dataset
implement to reduce the error of the regression model through size significantly differs from the ANN model size, it can lead
a variational autoencoder (VAE) structure. Moreover, a ver- to accuracy issues like overfitting or underfitting. To address
ification step is added to robustly design process-voltage- this, it is advisable to adjust the size of the ANN model
temperature (PVT) variations. proportionally to the dataset size, ensuring better accuracy.
In this paper, Section II describes the structure of the Additionally, due to varying weights for each input-output
regression model and key optimization algorithms. In Sec- relationship, we partitioned the hidden layer connected to
tion III, the design optimization flow is explained in detail, the input and output of the ANN regression model. This
and in Section IV, the simulation setup is illustrated for this partitioning helps avoid biased learning towards a specific
work. In Section V and Section VI, we present the simulation design parameter and provides separate training guidelines
results and conclusions, respectively. for input and output components.

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Algorithm 1 Training ANN Regression Model In this study, the zoom-in algorithm sets the number of
1: Input: P = {p1 , p2 , . . . , pN } simulations of the narrow sweep range by 1/(N + 1) times
▷ Dataset containing N design parameters the total number of simulations for a wide sweep range. N is
2: Output: R = {r1 , r2 , . . . , rM } the number of narrow sweep range (Narrow S.R) candidates.
▷ Dataset containing M performances That is, the size of the training dataset is set to be the same
3: for both fine and coarse simulation steps. Fig. 2 illustrates
4: Initialize weights and data standardization the range settings for the coarse and fine simulation steps
5: for epoch in 1, 2, . . . , e do in the zoom-in algorithm. After selecting the best candidate
6: compute the loss function L = 21 6i=1
b (y − t )2
i i
group in the coarse simulation, the range is divided during the
7: for mini-batch in 1, 2, . . . do fine simulation. With 2 design parameters and 5 candidates
8: optimize weights by Adam optimizer for the fine simulation, both the fine and coarse simulations
9: end for involve a dataset size of (6×6), resulting in 216 data points for
10: b is a mini-batch size optimizing the design parameters. In contrast, the single-step
11: yi is a prediction of output approach would require a larger dataset size of (6 × 6) ×
12: ti is a validation of output (6 × 6) when assuming a 10 % fine simulation range. This
13: end for would amount to 1296 data points needed for optimization.
The zoom-in algorithm significantly reduces the dataset size,
leading to improved efficiency and computational savings.
B. ZOOM-IN ALGORITHM The ranges of the fine simulations vary for each candidate,
When designing a circuit, designers optimize it through as they are specified based on the error rate compared to the
numerous trials and errors. Additionally, without utiliz- results of the SPICE simulation and the regression model.
ing a machine learning-based learning model, a significant More specifically, the range of the fine simulation is selected
amount of data covering the global range is required to to be between 5 % and 15 % of the range of the coarse simu-
find the optimal point. To enhance the design optimiza- lation. This approach compensates for poorly trained regions
tion process, our proposed zoom-in algorithm in this study in the regression model, ensuring they are not discarded.
achieves greater precision and efficiency compared to previ-
ous research efforts. While previous studies have explored the
use of regression models for analog circuit design automa- C. REFLECTING PVT VARIATION
tion [3], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], The analog circuit designer selects the optimization point
[15], the original zoom-in algorithm presented in [3] had with the best Figure-of-Merit (FoM) performance when
a limitation in the accuracy of the regression model during designing the circuit. However, as the process advances, the
the initial step due to a smaller amount of data compared mismatch between devices increases. Due to this, designing
to single-step approaches. To address this limitation, our an analog circuit is more difficult than before. Although pre-
study focuses on improving accuracy by incorporating the diction techniques such as Monte Carlo have been created, the
variational autoencoder (VAE) structure and refining the ver- Monte Carlo simulation takes significant time for processing
ification step within the algorithm. a detailed design [16]. To replace this, we predicted the value
The proposed zoom-in algorithm is divided into a coarse by applying limited PVT variations through a regression
simulation in a wide sweep range and a fine simulation in model and verification step.
a narrow sweep range. A coarse simulation step does not Analog designers can be very good at optimizing designs;
require high accuracy because it only needs to determine the however, they tend to rely on their experience. Even skilled
rough optimal points. The coarse simulation step properly designers can select different design points for the same
lists up to candidate groups based on the trend of change in the circuit. In contrast, the regression model finds better points
result values. In contrast, the purpose of the fine simulation is that the designer does not consider. To be more specific, the
to perform precise optimization by equally performing each regression model searches points with similar performance
predicted point within a small range. If the model is trained metrics. In each of the searched points, while the performance
with a large dataset without dividing the steps, the amount metrics are similar, the variations in performance resulting
of data required increases exponentially, and the processing from mismatches differ. Therefore, it is necessary to optimize
time can be infinitely long. Consequently, if the optimization the design values for various points and compare the PVT
steps are divided, the time required to compute unnecessary variations. Fig. 3 shows an example of how the FoM can vary
simulation results can be saved. Although the zoom-in algo- by changing the design parameters. The result of point B is
rithm can be divided into multiple stages instead of 2 stages, larger than that of point A. In contrast, the same performance
assuming the same amount of data, there is a high possibility as the reference point cannot always be obtained, since there
that it can be optimized to the local optima since the accuracy are mismatches between processes. Both points A and B are
of the first stage is lower than previously. Alternatively, it is given the same change in parameter values, but the amount
suitable for cases in which there are many parameters to be of change in the FoM is different. If the mismatch between
considered or optimized over a wider range. processes is considered, the designer will choose point A.

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FIGURE 2. Example of zoom-in algorithm about 2-axis design parameter.

Therefore, considering the PVT variations, optimization with is responsible for transforming the input into latent space.
simulation results over a wide range can design a circuit with The purpose of the encoder is to estimate the distribution of
better performance. Similarly, studies including corner sim- the latent space vector z, that is, q(z|x). Find the parameters
ulation, layout generator, and Monte Carlo simulation have of the mean (µ) and standard deviation (σ ) by selecting the
been developed to consider PVT variations [10], [11], [12], normal distribution that best represents q(z|x). In contrast to
[13], [14]. These simulations to check PVT variations have an encoder, a decoder is responsible for transforming a latent
the disadvantage of requiring a significant computer process- space into an input. The goal of the decoder is to estimate
ing time. In this study, the PVT variations are considered q(z|x) given the latent space vector z as the input. Because
with less computer processing time. We directly derived the it generates data x again according to a given vector z, the
results for each variance using the trained regression model, decoder serves as a generative model. Latent space refers to
and the method for restrictively applying the PVT variations any hidden vector. Unlike autoencoders, a VAE samples noise
is described in detail in Section III. and creates a latent space to generate data. The VAE finds θ
that maximizes pθ (x) using a maximum likelihood estima-
D. APPLYING VAE STRUCTURE tion (MLE) approach. Equation (1a)–(1d) are the process for
We selected candidates from a wide range using a zoom- maximizing the log-likelihood through the MLE approach.
in algorithm. Although studies that have applied automated Z
design using an ANN-based regression model already exist, log pθ (x) = qφ (z|x) log pθ (x)dz (1a)
the regression model may be trained partially incorrectly. Z
This is because it predicts values based on limited simulation pθ (x|z)p(z)
= qφ (z|x) log dz (1b)
data. Therefore, to solve this problem, we predict values over pθ (z|x)
Z
a wide range using an ANN-based regression model and pθ (x|z)p(z) qφ (z|x)
= qφ (z|x) log dz (1c)
apply additional compensation methods. We created another pθ (z|x) qφ (z|x)
Z
model that is trained by reversing the input and output. Fig. 4
shows the VAE structure and the structure of the proposed = qφ (z|x) log pθ (x)dz − KL(qφ (z|x)||p(z))
method. In Fig. 4(a), the VAE is divided into the encoder and + KL(qφ (z|x)||p(z|x)) (1d)
decoder parts. Z
The VAE is a type of generative model like GAN (Genera- ≥ qφ (z|x) log pθ (x)dz − KL(qφ (z|x)||p(z))
tive Adversarial Networks (GAN) and diffusion models [17]. (1e)
It is an advanced model of an autoencoder (AE) that creates
a meaningful latent space by making the input and output In (1b), Bayes’ rule is applied in (1a), and (1c) is multiplied
equal and derives the latent space using an encoder and a by the same q equation for the denominator and numerator
decoder. The desired output is decoded from this latent space in (1b). In (1d), Kullback–Leibler (KL) divergence in (1c)
for data generation. The VAE aims to approximate the true is applied. The first term in (1d) is equal to the negative
distribution of input data p(x). To this end, the VAE consists cross-entropy between p(x|z) and q(z|x). The second term
of an encoder, a decoder, and a latent space. The encoder is equal to the KL divergence between q(z|x) and p(z). The

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FIGURE 3. Apply PVT variation using results of ANN regression model.

last term cannot be computed because p(z|x) is unknown.

However, because KL divergence is always positive, the last
expression can be expressed as an inequality, as in (1e).
The right-hand side of inequality (1e) is referred to as evi-
dence lower bound (ELBO). By maximizing this ELBO, the
log-likelihood can also be maximized. After learning the
encoder and decoder while maximizing the aforementioned
ELBO, the desired data can be generated using the learned
decoder.
Subsequently, to the employment of all the above-
mentioned terms, our model finds other points with similar
results to the design optimization point. Therefore, based
on this concept, we trained 2 models to predict inputs as
well as the traditional model to predict outputs, as shown in
Fig. 4(b). Using this model, we add validation of the preex-
isting results. And we find new design parameter candidates
that are obtained using the preexisting results. In other words,
we also added candidates by adding random noise to find the
parameters in other locations with similar results.

III. DESIGN FLOW

Fig. 5 shows the overall automation design flow used in this FIGURE 4. (a) General VAE structure (b) The VAE structure employed in
study. This section details each step in the design automation this work.

flow.

A. COARSE SIMULATION (WIDE RANGE SEARCHING) with small simulations. By employing uniform division, the
First, we need to determine how to divide each design param- evenly distributed data across the entire range reduces the
eter. Each design parameter is divided over a wide range. occurrence of poorly trained regions. Therefore, a uniform
A representative dividing method randomly or uniformly division with small simulations is the most reasonable way to
divides the sections. In this study, each design parameter is train a regression model.
evenly divided over a wide sweep range based on the set
value. This is because, if the simulation results are small, B. TRAINING VAE STRUCTURE REGRESSION MODEL
random division can be a problem. A method that randomly As mentioned in Section II-C, we should not simply find
divides the range about small simulations can be biased to the point with the highest performance specification but
one side and split. This is because in that case, the simulation also find a point that is robust against a process mismatch.
results are not linear, and the accuracy of the regression model We employed the VAE structure to validate the predicted
for the opposite side can be very small. On the other hand, results or to find a new point. The purpose of adding ran-
we just need to obtain a rough location for the largest FoM dom noise is to find other points that have similar results.

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FIGURE 5. Overall automation design flow.

In this study, a regression model of a VAE structure, such as Finally, regarding the final 5 candidates, the simulation and
that shown in Fig. 4 is trained using the coarse simulation prediction results are compared, and the narrow sweep range
results. The trained model predicted all outcomes within a is adjusted in proportion to the error rate in the range of 5 to
wide sweep range. And the 10 best-performing candidates 15 % of the wide sweep range. A detailed description of this
are selected by comparing the predicted results through the step is presented in Algorithm 2.
encoder. In this process, the results around the candidate point
are initialized each time a candidate group is selected such D. FINE SIMULATION (NARROW RANGE SEARCHING)
that the sweep range between the candidates does not overlap. First, we shortened the design time by running 10 SPICE
Thereafter, we take 10 candidates as input to the decoder programs simultaneously and proceeding with fine simula-
part and add only decoder outputs that do not overlap with tions. The same amount of dataset is extracted as a coarse
existing candidates. And random noise is added to each of simulation. And the process of extracting the overall sim-
the 10 candidates and fed into the model. Similarly, only ulation results is handled in the same manner as for the
candidates that do not overlap with the existing candidate coarse simulation. Similarly, when the range is evenly divided
group are added. at the fine simulation, a much more accurate prediction
is possible than at the coarse simulation. As the distance
C. VERIFICATION STEP (I) of input parameters between each result is smaller than
Using the VAE structure, we obtained a maximum of 40 can- before.
didates from the existing 10 candidates. Because 40 candi-
dates is a large number to train into each regression model, E. TRAINING REGRESSION MODELS WITH FINE
the best-performing point must be predicted and reselected SIMULATION
through this step. First, we computed only the top 10 candi- The regression models are trained to interpolate each narrow
dates with the best FoM performance out of 40 candidates. sweep range. The structure of the regression models is the
Then, for the remaining 10 candidates, simulations are con- same as that of the encoder in the VAE structure. The narrow
ducted under Slow-Slow (SS) and Fast-Fast (FF) transistor sweep range is a very small area compared to the wide sweep
conditions. According to the simulations, the final 5 candi- range, and the number of simulation data points is the same.
dates with the smallest performance variation are selected. That is to say, the accuracy of the predicted results derived

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Algorithm 2 Verification Step (I) Algorithm (Section III-C) Algorithm 3 Verification Step (II) Algorithm (Section III-F)
1: Input: I = {i1 , i2 , . . . , iN } 1: Input: D = {d1 , d2 , . . . , dT }
▷ N candidates of fine simulation step ▷ Dataset containing T results of each ANN regression
2: Output: O = {o1 , o2 , . . . , oM } model
▷ M selected ranges of fine simulation step ▷ T : The number of predicted results
3: 2: Output: Y = {y1 , y2 , . . . , yE }
4: Step 1: FoM comparision ▷ E selected values of design parameters
5: ii = ⟨pi,1 , pi,2 , . . . , pi,U ⟩ ▷ E : The number of design parameters
▷ pi,j : The jth design parameter or performance of ii 3:
▷ U : The number of design parameters and 4: Step 1: Select the best FoM of each model
performances 5: di = ⟨wi,1 , wi,2 , . . . , wi,U ⟩
6: H = {h1 , h2 , . . . , hK } ▷ wi,j : The jth design parameter or performance of di
▷ hn : ii with the nth best FoM ▷ U : The number of design parameters and
▷ K : The number of selected candidates at step 1 performances
7: procedure 6: F = {f1 , f2 , . . . , fK }
8: for j ← 1 to N do ▷ fn : di with the nth best FoM
9: Compute pi,j from SPICE with TT condition 7: procedure
10: Calculate FoMj 8: for i ← 1 to M do
11: end for ▷ M : The number of fine simulation candidates
12: H ← select(pi,j , FoMj , K ) 9: for j ← 1 to T do
▷ select: A function that selects and returns the K 10: Calculate FoMj
lowest pi,j based on FoMj 11: end for
13: end procedure 12: fi ← select(di,j , FoMj , 1)
14: ▷ select: A function that selects and returns the
15: Step 2: Temperature variation comparison lowest di,j based on FoMj
16: oi = ⟨qi,1 , qi,2 , . . . , qi,U ⟩ 13: end for
▷ qi,j : The jth design parameter or performance of oi 14: end procedure
▷ U : The number of design parameters and 15:
performances 16: Step 2: PVT variation comparison
17: V = {v1 , v2 , . . . , vK } 17: minFoMi : The minimum FoM of ith candidates
▷ The variation of FoM of hk 18: maxFoMi : The maximum FoM of ith candidates
18: H = {h1 , h2 , . . . , hK } 19: procedure
▷ hn : ii with the nth best FoM 20: for i ← 1 to M do
19: procedure 21: for j ← 1 to T do
20: for j ← 1 to K do 22: if (fi − di )/fi ∗ 100% ≤ 5% then
21: Compute qi,j from SPICE with SS and FF condi- 23: Calculate FoMj
tion 24: if FoMj ≤ minFoMi then
22: Calculate vj 25: minFoMi ← FoMj
23: end for 26: end if
24: O ← select(hi,j , vj , M ) 27: if maxFoMi ≤ FoMj then
▷ select: A function that selects and returns the M 28: maxFoMi ← FoMj
lowest hi,j based on vj 29: end if
25: end procedure 30: end if
26: 31: end for
27: Step 3: Sweep range setting 32: Y ← select(fi , maxFoMi − maxFoMi , 1)
28: procedure ▷ select: A function that selects and returns the
29: Calculate error rate lowest fi based on (maxFoMi − maxFoMi )
30: Set sweep range based on the error rate 33: end for
31: end procedure 34: end procedure

from the regression models is higher than a regression model therefore, it is not required an entire part of the VAE struc-
that is trained at the coarse simulation step. Moreover, we just ture in the fine simulation step. Consequently, we train each
use the encoder part of VAE-structured to verify the results. regression model using the encoder part. And the point
The VAE structure is an additional method to compensate with the highest FoM is selected based on each regression
for or verify the accuracy of the model owing to problems; model.

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FIGURE 6. Designed VCO block diagram and schematic circuit.

oscillator that is connected to a 7-stage inverter. Because the

LC oscillator has a standardized design flow, the ring oscil-
lator is designed to be more suitable for automated design.
The inverter is a current-starved structure, as shown in Fig. 6.
The NC and PC wires are connected to a diode-connected
transistor. In other words, the current-starved inverter uses
the current mirrors of the PMOS and NMOS to control the
charge flow and change the frequency. For the VDD , power
supply voltages of 1 V, 1.2 V, and 1.8 V are applied to the
FIGURE 7. ANN regression model’s input and output. 45 nm, 65 nm, and 180 nm processes, respectively.

B. DESIGN PARAMETER
F. VERIFICATION STEP (II) Fig. 7 illustrates the parameters used in the design of a
In this step, data processing is performed in a flow similar current-starved inverter. The control voltage (VC ) is an impor-
to that described in Section III-B. Although a mismatch can tant parameter as it determines the frequency of the output
be applied for each element to predict the precise PVT vari- signal in the VCO circuit. The ratio of PMOS to NMOS
ations, this method is time-consuming. Furthermore, in the (Wp /Wn ) significantly affects the duty cycle of the VCO.
verification step (II), calculations need to be performed for The W/L ratio, representing the width and length ratio of the
PVT variations of 5 candidates. To minimize processing time, transistor, determines the frequency range generated by the
the approach described in Section II-C is employed to select VCO circuit. To account for PVT variations, we introduce
candidates with the least variation. Specifically, the design process variations by examining the differences in Figure of
parameters of the optimized point calculated within each Merit (FoM) resulting from changes in the PMOS, NMOS,
narrow sweep range are altered by 5 %. The point exhibiting and W/L ratios. We also consider voltage variations by com-
the least variation, as determined by the FoM result, is then paring the FoM differences based on control voltage varia-
chosen as the final result. The final result is optimized; how- tions. Furthermore, temperature variations are incorporated
ever, the designer may need to make slight adjustments for through corner simulations in the verification step (I).
subsequent layout design. Additionally, it is recommended
to perform simulations to verify PVT variations before the C. SIMULATION ENVIRONMENT
layout design phase. The detailed flow of the algorithm for Fig. 7 shows the input-output relationship of the regression
this step is described in Algorithm 3. model to be trained. The result derives the random jitter,
average cycle, duty cycle, power dissipation, rising time,
IV. CIRCUIT DESIGN and falling time. We adopt the FoMJ (Figure of Merit for
In this study, an algorithm for the automated design of jitter-power based on the PLL) proposed by Gao et al. [18]
a 1 GHz VCO is implemented, and the circuit is optimized. and replace the overall power dissipation of the PLL with the
The FoM is calculated using the root-mean-square (RMS) power dissipation of the VCO (PVCO ). Thus, we utilize the
value of the random jitter and power dissipation. revised VCO FoM as follows:
σrms 2 PVCO
  
A. VOLTAGE-CONTROLLED-OSCILLATOR (VCO) FoM = 10 log , (2)
1s 1mW
The VCO circuit generates an actual clock from the Phase-
Locked-Loop (PLL) circuit. The clock frequency changes where σrms is the value for rms jitter. A VCO circuit is the
in proportion to the size of the voltage. We designed a ring most important operating reference for synchronous circuits.

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FIGURE 8. ANN regression model accuracy comparison between coarse and fine simulations in CMOS 65nm.

If the clock generated by a clock generator differs signifi- design point, such as when an operating frequency of 1 GHz
cantly from the average period of the clock, the probability cannot be obtained or when the difference in the duty cycle is
of malfunction increases. Power consumption is an important affected to the circuit. Therefore, a selection filter is required
performance specification for every circuit. Therefore, the that prioritizes the FoM, but excludes out candidates with
performance result is compared with the value of the product specifications below the standard in constructing the rest of
of the random jitter and power dissipation, as shown in (2). the circuit. We use a selection filter to determine whether the
Regarding the remaining parameters, it is not a criterion for circuit is operating normally with the rest of the parameters
selecting the optimized point, but the average cycle, duty except the FoM. And select the best result through random
cycle, rising time, and falling time are required to verify a jitter and power dissipation.
circuit that operates normally.

E. SIMULATION SETUP
D. SELECTION FILTER The simulation result is derived from the transition time
When the design of analog circuits is automated, specifica- analysis of the SPICE simulation, and it is used to opti-
tions other than the FoM may not be considered. Taking the mize with the goal of a 1 GHz VCO that has low jitter
VCO circuit as an example, it is not possible to find a proper and power dissipation. Additionally, the setup to add noise

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FIGURE 9. ANN regression model standard deviation of error comparison about multi-step (coarse, fine) and single-step
simulation.

TABLE 1. Accuracy of the final result in CMOS 180nm, 65nm, and 45nm processes.

is required, because the FoM is calculated with rms jitter. Therefore, 100 ns, which is 100 cycles based on 1 GHz,
In the case of rms jitter rather than peak-to-peak jitter, there is designated as the transition time. Based on this setup,
is no significant difference, even if the transition time is long. the design parameters are automatically changed, and an

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 J.-W. Hyun, J.-W. Nam: AMS Circuit Design Optimization Technique

random nature, it is difficult to obtain accurate results solely

through transition time simulations. As a result, although the
error is larger than that of the other results, considering that
units are between femto seconds and pico seconds, it does
not occupy a large proportion. Excluding the random jitter,
it can be seen that the error for the coarse simulation mostly
exists within 30 %, and for the fine simulation, it exists within
approximately 5 %. The encoder structure of the ANN model
is designed as shown in Fig. 10, and the decoder structure
is designed in the reverse order of the encoder. The size of
the verified and trained datasets is 1225. In addition, the
ratio of the sizes of the training and validation datasets is
divided by 9:1.

B. FINAL RESULT
We compare the final result of applying our proposed algo-
rithm and the SPICE simulation results. Table 1 shows the
results and error rates applied to CMOS 180 nm, 65 nm, and
45 nm processes. The reason for applying the proposed algo-
rithm to various processes is to prove that migration between
processes is possible. In the case of the FoM, the difference
is calculated instead of the error rate. As can be seen from
this table, there is no significant difference in the error rate;
FIGURE 10. Encoder part of structure in ANN regression model employed therefore, it can be considered suitable for migrating to other
VAE structure. processes.
According to the FoM performance comparison in Table 1,
TABLE 2. Comparison of overall running time and normalized step size the final results from our proposed multi-step design flow
between multi-step and single-step simulation.
show remarkably improved accuracy performance than that
of the single-step design approach. Although the final cir-
cuit’s FoM performance through the multi-step algorithm is
slightly lower than that of the single-step approach, the final
result of the multi-step algorithm is robust to PVT variations
as it has passed the sensitivity comparing process against PVT
variations.

C. COMPARE SINGLE-STEP ANN REGRESSION MODEL

We additionally train and verify the algorithm that pre-
dicts the best point only for a wide range, not the zoom-in
algorithm that we propose, the method applying the VAE
structure, or the method that calculates the result through
automated design is implemented using a code that can be verification. The total amount of training data is configured
run. equal to the sum of the data used in this study.
Fig. 9 shows the standard deviation of the error between
V. RESULTS the prediction result using only the ANN regression model
We optimized the circuit by applying all previously suggested and the SPICE simulation result. We compared the results of
methods. The circuit is optimized based on 45 nm, 65 nm, the multi-step simulation consisting of coarse and fine sim-
and 180 nm Process-Design-Kit (PDK) to prove that it is easy ulations, which are our proposed algorithms, and single-step
to migrate to other tech nodes such as digital circuits. In the simulation results. In addition, we applied this algorithm to
verification step, the temperature is set to 120 ◦ C in the SS the 45 nm, 65 nm, and 180 nm processes and compared the
condition, and the FF is set to - 40 ◦ C for the simulation. results. In the case of random jitter, since the required dimen-
sion of a regression model is much higher than the others,
A. COARSE AND FINE SIMULATION RESULT the final accuracy of the random jitter will be lower than
Fig. 8 illustrates the error graph for the coarse and fine that of other performance indicators. However, the remaining
simulations in CMOS 65 nm. Random jitter is related to the results did not show significant errors. We can observe that
size of the transistor; however, it varies in value for many the standard deviation of the fine simulation in the multi-step
other reasons and is highly variable. For instance, due to the simulation is smaller than that of the coarse and single-step

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TABLE 3. Comparison of final result about proposed multi-step, and multi-step without VAE structure and corner simulation.

simulations. In most of the results, the fine simulation results parameters are optimized to ensure robust performance in
have significantly smaller standard deviation values than the corner simulation scenarios.
single-step simulation results; therefore, it is more efficient
to divide the simulation steps. On the other hand, as a pro- VI. CONCLUSION
cess criterion, the smaller the unit process, the larger the In this study, we propose several methods to achieve maxi-
standard deviation. Although it can be predicted that the mum efficiency with minimal simulation data. The zoom-in
smaller the unit of the process, the lower the accuracy due algorithm divides the sweep range of the design parameters
to mismatches and various errors, it is considered to be into coarse and fine simulations. In other words, the role
an acceptable error and is sufficiently applicable to other of each step can be divided into finding and predicting the
processes. accurate points. Thus, the zoom-in algorithm makes efficient
Table 2 presents the overall running time and normalized searching possible. In addition, the VAE structure detects
step size for both multi-step and single-step simulations. the points at which the ANN model is mistrained. Finally,
The running time is determined by concurrently execut- through the verification step, a design point robust to PVT
ing 10 SPICE simulations. The step size in the single-step variations is determined.
simulation is defined as a normalized step size for compari- Furthermore, the fine simulation predicts the necessary
son, while in the multi-step simulation, it is relative to the step points for a specific candidate group, but the ANN model
size of the fine simulation. Comparing the normalized step created in the coarse simulation uses data computed based
size, the average value in the single-step simulation is more on the overall simulation range. Models trained with coarse
than three times higher than in the multi-step simulation. simulation data have the advantage that they can be reused
This discrepancy becomes more pronounced as the dataset if other VCO performance is needed. Thus, when a VCO
size increases, emphasizing the importance of training the is required in another circuit, it is possible to immediately
regression model with denser data for improved simulation designate a candidate group using the created ANN Model.
accuracy and efficiency. In addition, if the ANN model is trained with a much larger
dataset, the design time is significantly reduced, and the accu-
D. COMPARE MULTI-STEP ANN REGRESSION MODEL racy is higher. Therefore, it has tremendous advantages when
WITHOUT VAE STRUCTURE AND CORNER SIMULATION designing various specifications in the same circuit topology.
Table 3 shows that the maximum error values in the proposed
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