AVR PERIPHERAL FUNCTIONALITY

SERIAL COMMUNICATION
DR T WALINGO

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MAIN CONTENT
• BASICS OF SERIAL COMMUNICATIONS.

• THE RS232.

• USART.

• AVR SERIAL USART PROGRAMMING.

– POLLING BASED.

– INTERRUPT BASED.

• THE SPI PROTOCOL

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BASICS OF SERIAL COMMUNICATION
• Computers transfer data in two ways: parallel and serial.
• Parallel data transfer:- several data bits are transferred
simultaneously, e.g. to printers and hard disks.
• Serial data transfer:-Data transferred bit by bit, one at a
time.
• Advantages of serial communications over parallel: Lower
cost and power, longer distances, easier to synchronize,
fewer I/O pins, simple programming interface, can also
provide high performance, many protocols: USART, SPI,
I2C; USB, etc, easy data conversion between different
physical medias etc.
• What are the disadvantages?

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SYNCHRONOUS VS ASSYNCHRONOUS SERIAL DATA TRANSFER
• Synchronous serial communications:
– Common clock to synchronize the receiver with the transmitter.
Example SPI.
• Asynchronous serial communications
– The clocks of the sender and receiver are not synchronized.
– Examples: RS232, USART.
Advantages Disadvantages

•Simple, doesn't require synchronization of both

Large relative overhead, a
communication sides
high proportion of the
Asynchronou •Cheap, timing is not as critical as for synchronous
transmitted bits are uniquely
s transmission, therefore hardware can be made cheaper
for control purposes and
transmission •Set-up is very fast, so well suited for applications where
thus carry no useful
messages are generated at irregular intervals, for
information
example data entry from the keyboard

Synchronous •Slightly more complex

•Lower overhead and thus, greater throughput
transmission •Hardware is more expensive

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SERIAL COMMUNICATION TERMS
• Simplex : Communication occurs in one direction only.
• Half Duplex : Communication in both directions, but only
one direction at a time (not simultaneously).
• Full Duplex: Communication occurs in both directions
simultaneously.
• Bit rate: the rate at which data is transmitted, measured
in bits per second (bps).
• Baud rate: the number of symbols transferred per
second. For AVR USART same as bit rate.
• Parity bit: a single bit that is sent together with data bits
to make the total number of 1’s even (for even parity) or
odd (for odd parity). Used for error checking.
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ASYNCHRONOUS SERIAL COMMUNICATION AND DATA FRAMING
• A protocol is required for communication. Framing and data transfer rate
• Framing - Placing each character between start and stop bit(s).
• The start bit is always a 0 (low) and the stop bit(s) a 1 (high).
• The LSB goes out first (in most cases, default).
• With no transfer the signal is a 1 (high), which is referred to as a mark. The 0
(low) is referred to as a space.
• Data can be 7 or 8 bits wide. Stop bits can be one or two.
• In some systems a parity bit is added to maintain data integrity. In odd parity the
number of 1s in the data bits including the parity bit is odd.

Goes out last

Goes out first
Sending ‘A’
0b 0100001

Stop 0 0 0 0 0 1 Start
1 0
bit bit

D7 D0 Space Mark

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THE RS232 INTERFACING STANDARD
• The RS232 standard covers four main aspects:
– Electrical: voltage level, rise and fall time, data rate, distance.
– Functional: function of each signal.
– Mechanical: number of pins, shape & dimension of connectors.
– Procedural: sequence of events for transmitting data.
• RS232 restricts baud rate to 20 Kbps and cable length to 15 m. In
practice, it can support up to 56 Kbps & 30 m of shielded cables.
• It defines 25-pin D connectors. In many cases, 9-pin connectors are also
used.
• There are two important terms in the RS232.
– Data Terminal Equipment (DTE) essentially refers to terminals and
computers that send and receive data.
– Data Communication Equipment (DCE) essentially refers to
communication equipment such as modems that are responsible for
transferring data.
• Both COM1 and COM2 of the x86PC’s are RS232. One has been replaced
by the USB port.

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RS232 SIGNALS
• DTR (data terminal ready) – when the terminal is turned on, after going
through a self test, it sends out signal DTR to indicate that it is ready for
communication.
• DSR (data set ready) -- when the DCE is turned on, after going through a self
test, it sends out signal DSR to indicate that it is ready for communication.
• RTS (request to send) – when the DTE device has a byte to transmit, it asserts
RTS to signal the modem that it has a byte of data to transmit.
• CTS (clear to send) – in response to RTS, when the modem has room to store
the data it is to receive, it sends out signal CTS to the DTE to indicate that it can
receive the data now.
• DCD (data carrier detect) – the modem asserts signal DCD to inform the DTE
that a valid carrier has been detected and that contact between it and the
other modem is established.
• RI (ring indicator) – an output from the modem (DCE) and an input to a PC
(DTE) indicates that the telephone is ringing.
• TxD (Transmitted data) – For data transmitting.
• RxD (received data) – For data reception.
• GND (signal ground) – ground for the signals.

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AVR CONNECTION TO RS232 – MAX232
• The RS232 is not TTL compatible. A 1 is represented by -3 to -25V while a 0 bit is +3
to +25, making -3 to +3 undefined. TTL voltage levels use 5.0 volts, with a high
being any voltage above about 2 volts and a low being any voltage below 0.8 volts
• A line driver such as the MAX232 chip is required to convert RS232 voltage levels to
TTL levels and vice versa.
• The MAX232 uses the same voltage as the AVR +5V.

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AVR SERIAL PORT PROGRAMMING – ATMEGA 32 USART OVERVIEW
• Full Duplex Operation (Independent Serial
Receive and Transmit Registers).
• Asynchronous or Synchronous Operation.
• Master or Slave Clocked Synchronous
Operation.
• High Resolution Baud Rate Generator.
• Supports Serial Frames with 5, 6, 7, 8, or 9
Data Bits and 1 or 2 Stop Bits.
• Odd or Even Parity Generation and Parity
Check Supported by Hardware.
• Data OverRun Detection.
• Framing Error Detection.
• Noise Filtering Includes False Start Bit
Detection and Digital Low Pass Filter.
• Three Separate Interrupts on TX Complete,
TX Data Register Empty, and RX Complete.
• Multi-processor Communication Mode.
• Double Speed Asynchronous
Communication Mode. Where are the serial
communications pins

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USART – FRAME FORMAT
• Character size: 5 to 9 bits.
• 1 start bit,
• 1 or 2 stop bits,
• Parity bit; no, even or odd parity.
• Set by UCSZ2:0, UPM1:0 and USBS bits in the UCSRB and
UCSRC. Parity

Stop

Start

Draw the frame for sending ‘A’,

0b 00100001, 8 bit, 1 start bit, 2
stop bits, even parity.

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HARDWARE ELEMENTS
• USART Clock Generator:
– to provide clock source.
– to set baud rate using UBRR register.
• USART Transmitter:
– to send a character through TxD pin.
– to handle start/stop bit framing, parity bit, shift register.
• USART Receiver:
– to receive a character through RxD pin.
– to perform the reverse operation of the transmitter.
• USART Registers:
– to configure, control and monitor the serial USART.

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CLOCK GENERATOR
• USART supports four modes of clock generation:
– Normal asynchronous,
– Double speed asynchronous,
– Master synchronous ,
– Slave synchronous mode.

• The UMSEL bit in UCSRC chooses between synchronous and

asynchronous.

• The U2X in the UCSRA is used to select double speed.

• The external clock can also be used in some modes.

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THE TRANSMITTER
• Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the
UCSRB Register. The normal port operation of the TxD pin is overridden.
• The baud rate, mode of operation and frame format must be set up
once before doing any transmissions.
• A data transmission is initiated by loading the transmit buffer with the
data to be transmitted. Done by writing to the UDR I/O location.
• The buffered data in the transmit buffer will be moved to the shift
register when the shift register is ready to send a new frame.
• The shift register is loaded with new data if it is in idle state (no ongoing
transmission) or immediately after the last stop bit of the previous
frame is transmitted.
• When the shift register is loaded with new data, it will transfer one
complete frame at the rate given by the baud register, U2X bit or by XCK
depending on mode of operation.
TxD
UDR (Tx buffer) Tx Shift register Framing

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TRANSMITTER FLAGS AND INTERRUPTS
• The USART transmitter has two flags that indicate its state: USART Data Register
Empty (UDRE) and Transmit Complete (TXC). Both flags can be used for generating
interrupts.
• The Data Register Empty (UDRE) flag indicates whether the transmit buffer is ready
to receive new data. This bit is set when the transmit buffer is empty, and cleared
when the transmit buffer contains data to be transmitted that has not yet been
moved into the shift register.
• When the Data Register empty Interrupt Enable (UDRIE) bit in UCSRB is written to
one, the USART Data Register Empty Interrupt will be executed as long as UDRE is set
(provided that global interrupts are enabled). UDRE is cleared by reti or writing data
to UDR.
• The Transmit Complete (TXC) flag bit is set to one when the entire frame in the
Transmit Shift Register has been shifted out and there are no new data currently
present in the transmit buffer.
• When the Transmit Complete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART
Transmit Complete Interrupt will be executed when the TXC Flag becomes set
(provided that globial interrupts are enabled). The flag is cleared by reti or writing a
one to its bit location
TxD
UDR(TX buffer) Tx Shift register Framing

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USART TRANSMITTER CODE

• Note: the procedure of sending a 9 bit character is a bit

different.

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THE USART RECEIVER
• The USART Receiver is enabled by writing the Receive Enable (RXEN) bit
in the UCSRB Register to one. The normal pin operation of the RxD pin is
overridden.
• The baud rate, mode of operation and frame format must be set up
once before any serial reception can be done.
• The Receiver starts data reception when it detects a valid start bit. Each
bit that follows the start bit will be sampled at the baud rate or XCK
clock, and shifted into the Receive Shift Register until the first stop bit of
a frame is received.
• When the first stop bit is received, i.e., a complete serial frame is
present in the Receive Shift Register, the contents of the Shift Register
will be moved into the receive buffer. The receive buffer can then be
read by reading the UDR I/O location.

RxD

Rx Shift register UDR (Rx buffer)

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RECEIVE COMPETE FLAG AND INTERRUPT
• The Receive Complete (RXC) flag indicates that unread data is present in
the receive buffer.
 This flag is one when unread data exist in the receive buffer, and
zero when the receive buffer is empty (i.e. does not contain any
unread data).
 If the receiver is disabled (RXEN = 0), the receive buffer will be
flushed and consequently the RXC bit will become zero.
• When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set,
the USART Receive Complete Interrupt will be executed as long as the
RXC flag is set (provided that global interrupts are enabled).
• When interrupt-driven data reception is used, the receive complete
routine must read the received data from UDR in order to clear the RXC
flag; otherwise a new interrupt will occur once the interrupt routine
terminates.
RxD

Rx Shift register UDR (Rx buffer)

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USART RECEIVE CODE

Note: the procedure of receiving a 9 bit character is a bit different.

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RECEIVE ERROR FLAGS
• Frame errors:- UCSRA<4> : Bit 4 – FE: Frame Error: This bit is set if
the next character in the receive buffer had a Frame Error when
received. For example, when the first stop bit of the next
character in the receive buffer is zero.
• Data overrun errors:- UCSRA<3> : Bit 3 – DOR: Data OverRun: This
bit is set if a Data OverRun condition is detected. A Data OverRun
occurs when the receive buffer is full (two characters), a new
character waiting in the Receive Shift Register, and a new start bit
is detected.
• Parity Error : UCSRA<2> : Bit 2 – PE: Parity Error: This bit is set if
the next character in the receive buffer had a Parity Error when
received.
• Note: All the above bits are valid until the receive buffer (UDR) is
read.

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USART SUMMARY
RxC flag set when full. UDRE flag set when empty.
RXCIE interrupt when enabled UDRIE interrupt when enabled
Flag cleared by reading UDR or reti Flag cleared by writing to UDR or reti

Data bus

Transmit data
put here
Received data UDR UDR
read from here (Rx buffer) (Tx buffer)

RxD 1 TX shift register 0 TxD

1 RX shift register 0
pin pin

TxC flag set when empty.

TXCIE interrupt when enabled

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USART I/O DATA REGISTER –UDR
• Register UDR is the buffer for characters sent or received through the
serial port.
• Transmit and Receive Buffer (TXB and RXB) share the same address
called the USART Data Register (UDR).
• To start sending a character, write it to UDR. To check a received
character, read it from UDR.
• Reading from UDR returns current contents of the RXB. Writing to UDR
stores value to TXB and initiates transmission.
• The transmit buffer can only be written when the UDRE Flag in the
UCSRA Register is set.
• ISR must read/write data from/to UDR or disable the UDR-Interrupt

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REGISTER BITS AND VALUES

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USART BAUD RATE REGISTER UBRRL AND UBRRH

• Determines the speed of data transfer

• The UBRRH shares the same I/O location as the UCSRC. URSEL
bit is used to choose between the two.

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What of a clock of 8MHz
normal mode a) 1200bps
b) 4800bps

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ACCESSING UBRRH/UCSRC REGISTERS
• The UBRRH Register shares the same I/O location as the UCSRC Register.
• USART Register Select (URSEL) bit, controls which one of the two registers that
will be written. If URSEL is zero the UBRRH value will be updated. If URSEL is one,
the UCSRC setting will be updated.
• The read access is controlled by a timed sequence. Reading the I/O location
once returns the UBRRH Register contents. If the register location was read in
previous system clock cycle, reading the register in the current clock cycle will
return the UCSRC contents.
• The read operation is relatively complex and mostly not required. It is clock
controlled and alternates.

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USART INITIALIZATION
• Setting the baud rate.

• Enabling the Transmitter and Receiver.

• Setting the frame format.

– Parity (even/odd/none).
– Number of data bits (4-9).
– Framing ( 1 or 2 stop bits).

• Set the USART Mode

– Asynchronous

• Enabling interrupts; if using them.

Note: A character can now be sent and

received using the given codes.
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SENDING A CHARACTER

To Transmit:
• Poll UDRE bit in USCRA
until set.
• Place character to be
written in UDR.
• Repeat.

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RECEIVING A CHARACTER

To Receive:
• Poll RXC bit in UCSRA
until set.
• Received char in UDR.
• Repeat.

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USING HYPERTERMINAL
• Start program in Accessories | Communications |
Hyper Terminal.
• Configure Hyper Terminal for given baud rate,
parity, data bit, stop bit, flow control.

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PROGRAMMING THE AVR TO TRANSFER DATA SERIALLY
1. The UCSRB register is loaded with the value enabling the
USART transmitter. The transmitter will override normal
port operation for the TxD pin when enabled.
2. The UCSRC register is loaded with the value indicating
asynchronous mode and framing information.
3. The UBRR is loaded with the baud rate value to set the
baud rate for serial data transfer.
4. The character to be transmitted serially is written into the
UDR register.
5. Monitor the UDRE bit of the UCSRA register to make sure
UDR is ready for the next byte.
6. To transmit the next character, go to step 4.
Write a program to transmit the message “YES” serially at 9600 baud, 8-bit data,
and 1 stop bit continuously. Assume the XTAL is 8Mhz

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CLASS EXERCISE 1 - POLLING
• Write a program to transmit the message “YES” serially at 9600 baud, 8-bit data, and 1
stop bit continuously. Assume the XTAL is 8Mhz
; ************************************************ ;***********************************************
.org 0x00 Start:
ldi Temp, ‘Y’ ;move Y to Temp
rjmp Init call TRANSMIT ;Transmit
;************************************************ ldi Temp, ‘E’
call TRANSMIT
;CONFIGURATION SECTION
ldi Temp, ‘S’
Init: ldi temp, low(RAMEND) call TRANSMIT
out SPL, Temp ldi Temp, ‘ ’
call TRANSMIT
ldi temp, high(RAMEND)
rjmp Start
out SPH, Temp
;***********************************************
ldi Temp, (1<<TXEN)
TRANSMIT:
out UCSRB, Temp ;Enable Transmitter
ldi Temp, (1<<UCSZ1)| (1<<UCSZ0)|(1<<URSEL) ; sbis UCSRA, UDRE ;is UDR empty
rjmp TRANSMIT ;wait
out UCSRC, Temp ; 8 bit, no parity, 1 stop, out UDR, Temp ;transmit
ldi Temp, 0x33
out UBRRL, Temp ;baud 9600
Ret
rjmp start ;***********************************************
;***********************************************
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PROGRAMMING THE AVR TO RECEIVE DATA SERIALLY
1. The UCSRB register is loaded with the value enabling the
USART receiver. The receiver will override normal port
operation for the RxD pin when enabled.
2. The UCSRC register is loaded with the value indicating
asynchronous mode and framing information.
3. The UBRR is loaded with the baud rate value to set the
baud rate for serial data transfer.
4. The RXC flag of the UCSRA register is monitored for a HIGH
to see if an entire character has been received yet.
5. When RXC is raised, the UDR register has the byte. Its
contents are moved to a safe place.
6. To receive the next character, go to step 5.
Write a program to receive bytes of data serially and put them on PORTB. Set the
baud rate at 9600, 8 bit data and 1 stop bit. Assume the XTAL is 8Mhz

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CLASS EXERCISE 2-POLLING
• Write a program to receive bytes of data serially and put them on PORTB. Set the baud
rate at 9600, 8 bit data and 1 stop bit. Assume the XTAL is 8Mhz
; ************************************************ ;***********************************************
.org 0x00 RECEIVE:

rjmp Init sbis UCSRA, RXC ; is any byte in UDR

;************************************************ rjmp RECEIVE ;wait
in Temp UDR ;receive
;CONFIGURATION SECTION
Init:
ldi Temp, (1<<RXEN) out PORTB, Temp

out UCSRB, Temp ;Enable Receiver rjmp RECEIVE

ldi Temp, (1<<UCSZ1)| (1<<UCSZ0)|(1<<URSEL) ;
;***********************************************
out UCSRC, Temp ; 8 bit, no parity, 1 stop,
ldi Temp, 0x..
out UBRRL, Temp ;baud 9600

ldi Temp, 0xFF

out DDRB, Temp ;PORTB is output

rjmp RECEIVE
;***********************************************

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CLASS EXERCISE 3 -POLLING
• Write a program with the following parts: a) send a message “YES” once to the PC screen, b) get data
from switches on PORTA and transmit it via a serial port to the PC screen, and c)receive any key press
sent by HyperTerminal and put it on LED’s on PORTB. The program must do parts b) and c) continuously.
; ************************************************ Start: ldi Temp, ‘Y’ ;move Y to Temp
;CONFIGURATION SECTION call TRANSMIT ;Transmit
ldi Temp, ‘E’
Init: ldi temp, low(RAMEND) call TRANSMIT
out SPL, Temp ldi Temp, ‘S’
call TRANSMIT
ldi temp, high(RAMEND) ldi Temp, ‘ ’
call TRANSMIT
out SPH, Temp
ldi Temp, 0x00 AGAIN: sbis UCSRA, RXC ; is there new data
rjmp SKIP_RX ;skip receive commands
out DDRA, Temp ;PORTA is input
in Temp, UDR ;move UDR to Temp
ldi Temp, 0xFF out PORTB, Temp
out DDRB, Temp ;PORTB is output
SKIP_RX : sbis UCSRA, UDRE ;is UDR empty
ldi Temp, (1<<TXEN) |(1<<RXEN)
rjmp SKIP_TX ;skip transmit commands
out UCSRB, Temp ;Enable Transmitter receiver in Temp, PINA ; move PORTA to Temp
ldi Temp, (1<<UCSZ1)| (1<<UCSZ0)|(1<<URSEL) ; out UDR, Temp ;transmit
out UCSRC, Temp ; 8 bit, no parity, 1 stop, SKIP_TX: rjmp AGAIN
ldi Temp, 0x..
out UBRRL, Temp ;baud 9600 TRANSMIT: sbis UCSRA, UDRE ;is UDR empty
rjmp TRANSMIT ;wait
rjmp start out UDR, Temp ;transmit
;*********************************************** Ret
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AVR INTURRUPT BASED TRANSMISSION
• Write a program to transmit the letter ‘G’ serially at 9600 baud rate continuously. Assume XTAL = 8MHz.
Use receive complete interrupt instead of polling method. Assume the XTAL is 8Mhz

; ************************************************ ldi Temp, 0x33

.org 0x00 out UBRRL, Temp ;baud 9600
rjmp Init sei
.org UDREaddr rjmp start
rjmp UDRE_INT_HANDLER ;***********************************************
; ************************************************ Start: rjmp Start
;CONFIGURATION SECTION
;**********************************************
Init: ldi temp, low(RAMEND)
out SPL, Temp UDRE_INT_HANDLER:

ldi temp, high(RAMEND) ldi Temp, ‘G’ ; transmit G

out SPH, Temp out UDR, Temp

ldi Temp, (1<<TXEN) |(1<<UDRIE) RETI

out UCSRB, Temp ;Enable transmitter and interrupt
How does the section
ldi Temp, (1<<UCSZ1)| (1<<UCSZ0)|(1<<URSEL) ;
change for a baud rate
out UCSRC, Temp ; 8 bit, no parity, 1 stop,
of 1200

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AVR INTURRUPT BASED RECEPTION
• Program the AVR to receive bytes of data serially and put them on PORTB. Set the baud rate to 9600,
8MHz, 8 bit data and 1 stop bit. Use receive complete interrupt instead of polling method.

; ************************************************ ldi Temp, 0x33

.org 0x00 out UBRRL, Temp ;baud 9600
rjmp Init sei
.org URXCaddr rjmp start
rjmp URXC_INT_HANDLER ;***********************************************
; ************************************************ Start: rjmp Start
;CONFIGURATION SECTION
;**********************************************
Init: ldi temp, low(RAMEND)
out SPL, Temp URXC_INT_HANDLER:

ldi temp, high(RAMEND) in Temp, UDR

out SPH, Temp out PORTB, Temp

ldi Temp, 0xFF RETI

out DDRB, Temp ;PORTB is output
How does the section
ldi Temp, (1<<RXEN) |(1<<RXCIE)
change for a baud rate
out UCSRB, Temp ;Enable receiver and interrupt
of 2400
ldi Temp, (1<<UCSZ1)| (1<<UCSZ0)|(1<<URSEL) ;
out UCSRC, Temp ; 8 bit, no parity, 1 stop,

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OTHER MODES OF OPERATION
• Synchronous Operation of USART
– When Synchronous mode is used (UMSEL = 1), the XCK pin will be
used as either clock input (Slave) or clock output (Master).
– The basic principle is that data input (on RxD) is sampled at the
opposite XCK clock edge of the edge the data output (TxD) is changed.
– When the Shift Register is loaded with new data, it will transfer one
complete frame at the rate given by the Baud Register, U2X bit or by
XCK depending on mode of operation.
• Multi-processor Communication Mode
– Enables several slave MCUs to receive data from a master MCU.
– This is done by first decoding an address frame to find out which MCU
has been addressed. If a particular Slave MCU has been addressed, it
will receive the following data frames as normal, while the other slave
MCUs will ignore the received frames until another address frame is
received.

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THE SPI PROTOCOL
• The Serial Peripheral Interface (SPI) protocol employs synchronous
transmission.
• During an SPI transfer, data is simultaneously transmitted (shifted
out serially) and received (shifted in serially).
• A serial clock line synchronises shifting and sampling of the
information on the two serial data lines. The master provides the
clock signal.
• A slave select line allows individual selection of a slave SPI device;
Slave devices that are not selected do not interfere with SPI bus
activities.
• On a master SPI device, the slave select line can optionally be used
to indicate a multiple-master bus contention.

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THE SPI PROTOCOL
• The master sets the SS (Slave Select – often called CS – chip select) pin low to tell
the slave that communication is about to start.
• The master and slave write information in the shift registers, a bit of information is
shifted onto the MOSI (Master Out Slave In) wire and the slave does the same on
the MISO wire (either of these can be omitted if the data transfer is one way),
eight bits transferred at a time.
• The master ticks the clock line SCLK it will read the value of MISO (Master In Slave
Out) wire (which the Slave has written) and the slave will read the value of the
MOSI wire (whether the data is sampled as the clock rises or falls depends on
which mode is in operation)
• The process is repeated by transferring a bit of data on each pulse of the clock until
all data is transferred
• Additional devices can be added to the same ‘bus’ with the addition of only a
single selection wire for each device

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THE SPI PROTOCOL
• The system consists of a master and slave shift registers and a master clock generator.
• The SPI Master initiates the communication cycle when pulling low the Slave Select SS
pin of the desired Slave. Master and Slave prepare the data to be sent in their
respective Shift Registers, and the master generates the required clock pulses on the
SCK line to interchange data.
• Writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware
shifts the 8 bits into the Slave. After shifting one byte, the SPI clock generator stops,
setting the end of Transmission Flag (SPIF).
• Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line,
and from Slave to Master on the Master In – Slave Out, MISO, line. After each data
packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line.

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THE SPI PROTOCOL
• When configured as a Master, the SPI interface has no automatic
control of the SS line. This must be handled by user software before
communication can start.

• When configured as a Slave, the SPI interface will remain sleeping with
MISO tri-stated as long as the SS pin is driven high. In this state,
software may update the contents of the SPI Data Register, SPDR, but
the data will not be shifted out by incoming clock pulses on the SCK pin
until the SS pin is driven low.

• After shifting one byte of data, the end of Transmission Flag (SPIF) is
set. If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an
interrupt is requested.

• The Slave may continue to place new data to be sent into SPDR before
reading the incoming data. The last incoming byte will be kept in the
Buffer Register for later use.

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ATMEGA32 SPI FEATURES
• Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

Identify the SPI pins

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SPI CONTROL REGISTER – SPCR

Bit 0 and 1 in selecting the prescaler value

To determines data sampling edge. 1 trailing edge.

To determines clock polarity. 1SCK is high when idle

To set SPI mode. 1master, 0slave

To determine which bit is sent first. 1LSB transmitted first

To enable SPI. 1SPI enabled

To enable SPI interrupt. 1SPI interrupt enabled

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SPI STATUS REGISTER – SPSR

To change the SPI speed. 1Speed doubled

The WCOL bit is set if the SPI Data Register (SPDR) is written
during a data transfer. The WCOL bit (and the SPIF bit) are cleared
by first reading the SPI Status Register with WCOL set, and then
accessing the SPI Data Register.

SPI flag set when a serial transfer is complete. An interrupt is generated if SPIE
in SPCR is set and global interrupts are enabled.

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SPI DATA REGISTER – SPDR

• The SPI Data Register is a read/write register used for data transfer
between the Register File and the SPI Shift Register.

• Writing to the register initiates data transmission.

• Reading the register causes the Shift Register Receive buffer to be read.

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CONFIGURING THE SPI – SPCR
• The SPI must be enabled: SPE –> 1.
• The SPI must be configured as master or slave: MSTR
• The SPI clock frequency must be selected; SPR0, SPR1,
SPXI2 in SPSR.
• The SPI timing mode must be chosen; CPOL, CPHA
• The order of sending data must be determined; DORD.
• Interrupts must be enabled if used; SPIE

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CONFIGURING THE SPI

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CONFIGURING THE SPI - PINS
• When the SPI is enabled, the data direction of the
MOSI, MISO, SCK, and SS pins is overridden
according to Table 55.

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STEPS FOR SENDING/WRITING DATA TO AN SPI DEVICE
SINGLE BYTE WRITE

1. Make SS = 0 to begin writing.

2. The SPI device expects to receive the data to be written.
3. The 8 bit data provided is shifted in one bit at a time, with each edge
of the SCLK on the MISO pin.
4. Make SS = 1 to indicate the end of the write cycle.

MULTI-BYTE WRITE

1. Make SS = 0 to begin writing.

2. The SPI device expects to receive the data to be written.
3. The first 8 bit data provided is shifted in, one bit at a time, with each
SCLK on the MISO pin. From then on, we simply provide consecutive
bytes of data to be written. In the process SS must stay low to indicate
that this is a burst mode multi-byte operation.
4. Make SS = 1 to indicate the end of the write cycle.

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STEPS FOR RECEIVING/READING FROM AN SPI DEVICE
SINGLE BYTE READ

1. Make SS = 0 to begin reading.

2. The 8 bit data is sent by the SPI device is provided in its buffer.
3. The 8 bit data is shifted out one bit at a time , with each edge of the
SCLK on the MOSI pin.
4. Make SS= 1 to indicate the end of the read cycle.

MULTI-BYTE READ

1. Make SS = 0 to begin reading.

2. The 8 bit data is sent by the SPI device is provided in its buffer.
3. The 8 bit data is shifted out one bit at a time , with each edge of the
SCLK on the MOSI pin. From then on, we simply keep getting
consecutive bytes of data to be received. In the process SS must stay
low to indicate that this is a burst mode multi-byte operation.
4. Make SS= 1 to indicate the end of the read cycle.

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SPI SUBROUTINES

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SPI PROGRAMMING IN AVR – MASTER OPERATING MODE
• Write an AVR program to initialize the SPI for master, Mode 0, with CLCK frequency Fosc/16,
and then transmit ‘G via SPI repeatedly. The received data should be displayed on PORTA.
; ************************************************
;HARDWARE CONNECTIONS ;***********************************************

;CONNECTIONS ARE ON PORT B Start:

.equ MOSI = 5 ; According to the MCU pins TRANSMIT:

.equ SCLK = 7
cbi PORTB, SS ;enable slave device
.equ SS = 4
; ************************************************ ldi Temp, ‘G’ ;Temp =‘G’
;CONFIGURATION SECTION out SPDR, Temp ;transmit
Init: ldi Temp, 0xFF
WAIT:
out DDRA, Temp ;PORTA is output
sbis SPSR, SPIF ;wait for transmission

ldi Temp, (1<<MOSI)| (1<<SCLK)|(1<<SS) ; rjmp WAIT ;to complete

out DDRB, Temp ; Pins defined as output in Temp1, SPDR ;read received data
out PORTA, Temp1
ldi Temp, (1<<SPE) |(1<<MSTR)
out SPCR, Temp ;Enable SPI, set clock edge, prescaler
sbi PORTB, SS ;disable slave device
rjmp Start
;*********************************************** rjmp TRANSMIT.

Do it for the slave

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SPI PROGRAMMING IN AVR – SLAVE OPERATING MODE
• Write an AVR program to initialize the SPI for slave, Mode 0, with CLCK frequency Fosc/16,
and then transmit ‘G via SPI repeatedly. The received data should be displayed on PORTA.
; ************************************************
;HARDWARE CONNECTIONS ;***********************************************

;CONNECTIONS ARE ON PORT B Start:

.equ MIS0 = 6 ; According to the MCU pins ldi Temp, ‘G’ ;Temp =‘G’
; ************************************************ out SPDR, Temp ;transmit
;CONFIGURATION SECTION
WAIT:
Init: ldi Temp, 0xFF
out DDRA, Temp ;PORTA is output sbis SPSR, SPIF ;wait for transmission
rjmp WAIT ;to complete
ldi Temp, (1<<MISO) ; in Temp1, SPDR ;read received data
out DDRB, Temp ; Pins defined as output out PORTA, Temp1

ldi Temp, (1<<SPE)

rjmp Start
out SPCR, Temp ;Enable SPI slave mode
rjmp Start
;*********************************************** ;Note that the slave will not start transfer or receive until
it senses clock from master
Make it interrupt based.
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