VLSI Testing

Introduction
Virendra Singh
Associate Professor
Computer Architecture and Dependable Systems Lab
Department of Electrical Engineering
Indian Institute of Technology Bombay
http://www.ee.iitb.ac.in/~viren/
E-mail: [email protected]

Testing & Verification of VLSI Circuits

Lecture 3 CADSL
 Introduction
• Many integrated circuits contain fabrication
defects upon manufacture
• Only 20-60% for high end circuits
manufactured may be defect free
• ICs must be carefully tested to screen out
faulty parts before integration in systems
• Latent faults that cause early life failure must
also be screened out through “burn-in” stress
tests
21 Jan 2013 EE-709@IITB 2 CADSL
 VLSI Realization Process
Customer’s need

Determine requirements

Write specifications

Design synthesis and Verification

Test development
Fabrication
Manufacturing test

Chips to customer

21 Jan 2013 EE-709@IITB 3 CADSL

 Contract between a design
house and a fab vendor
• Design is complete and checked (verified)
• Fab vendor: How will you test it?
• Design house: I have checked it and …
• Fab vendor: But, how would you test it?
• Desing house: Why is that important? It is
between I and my clients – it is none of your
business
• Fab vendor – Sorry you can take your
business some where else.

complete the story and determine the reasons

for the importance of test generation etc.
21 Jan 2013 EE-709@IITB 4 CADSL
Contract between design …
Hence:
• “Test” must be comprehensive
• It must not be “too long”
Issues:
• Model possible defects in the process
– Understand the process
• Develop logic simulator and fault simulator
• Develop test generator
• Methods to quantify the test efficiency

21 Jan 2013 EE-709@IITB 5 CADSL

 Need for Testing
• Functionality issue
– Does the circuit (large or small) work?
• Application issue
– Life critical applications
• Maintenance issue
– Need to identify failed components
• Cost of doing business
• What does testing achieve?
– Discard only the “bad product”? – see next three
slides

21 Jan 2013 EE-709@IITB 6 CADSL

 Verification vs. Test
Verification Test
 Verifies correctness of  Verifies correctness of
design. manufactured hardware.
 Performed by simulation,  Two-part process:
hardware emulation, or 1. Test generation: software
formal methods. process executed once during
design
2. Test application: electrical tests
applied to hardware
 Performed once prior to  Test application performed on
manufacturing. every manufactured device.
 Responsible for quality of  Responsible for quality of devices.
design.

21 Jan 2013 EE-709@IITB 7 CADSL

 Problems of Ideal Tests
 Ideal tests detect all defects produced in
the manufacturing process.
 Ideal tests pass all functionally good
devices.
 Very large numbers and varieties of
possible defects need to be tested.
 Difficult to generate tests for some real
defects. Defect-oriented testing is an
open problem.
21 Jan 2013 EE-709@IITB 8 CADSL
 Real Tests
• Based on analyzable fault models, which may
not map on real defects.
• Incomplete coverage of modeled faults due to
high complexity.
• Some good chips are rejected. The fraction (or
percentage) of such chips is called the yield
loss.
• Some bad chips pass tests. The fraction (or
percentage) of bad chips among all passing
chips is called the defect level.

21 Jan 2013 EE-709@IITB 9 CADSL

 Testing as Filter Process

Good chips Prob(pass test) = high Mostly

good
Prob(good) = y Pr w
ob l o chips
( fa t)=
il s
te
Fabricated Tested
s te
chips s st chips
)=
( pa l ow
o b
Pr
Defective chips Mostly
bad
Prob(bad) = 1- y Prob(fail test) = high chips

21 Jan 2013 EE-709@IITB 10 CADSL

 Students Examination

Pass quality Prob(P/PQ) = .95 Prob (P) =

Prob(PQ) = .75 0.72
Pr
ob .0 5
=
(F
/P
All Q)
Q )
Students P /F
b( =.
r o 05
P
Fail quality Prob (F)
Prob(FQ) = .25 0.27
Prob(F/FQ) = .95

21 Jan 2013 EE-709@IITB 11 CADSL

 Roles of Testing
 Detection: Determination whether or not the
device under test (DUT) has some fault.
 Diagnosis: Identification of a specific fault that
is present on DUT.
 Device characterization: Determination and
correction of errors in design and/or test
procedure.
 Failure mode analysis (FMA): Determination of
manufacturing process errors that may have
caused defects on the DUT.

21 Jan 2013 EE-709@IITB 12 CADSL

IC Testing is a Difficult Problem
• Need 23 = 8 input patterns to
exhaustively test a 3-input NAND
• 2N tests needed for N-input circuit
3-input NAND
• Many ICs have > 100 inputs

2100 = 1.27 x 1030

Applying 1030 tests at 109 per second (1 GHZ) will
require 1021 secs = 400 billion centuries!
• Only a very few input combinations
can be applied in practice
21 Jan 2013 EE-709@IITB 13 CADSL
 IC Testing in Practice
For high end circuits
• A few seconds of test time on very expensive
production testers
• Many thousand test patterns applied
• Test patterns carefully chosen to detect likely
faults
• High economic impact
-test costs are approaching manufacturing costs
Despite the costs, testing is always imperfect!
21 Jan 2013 EE-709@IITB 14 CADSL
 How well must we test?
Approximate order of magnitude estimates
• Number of parts per typical system: 100
• Acceptable system defect rate: 1% (1 per 100)
• Therefore, required part reliability
1 defect in 10,000
100 Defects Per Million (100 DPM)
Requirement ~100 DPM for commercial ICs
~1000 DPM for ASICs
“Zero Defect” target for automotive
21 Jan 2013 EE-709@IITB 15 CADSL
 How well must we test?
Assume 2 million ICs manufactured with 50% yield

 1 million GOOD >> shipped

 1 million BAD >> test escapes cause defective
parts to be shipped
 For 100 BAD parts in 1M shipped (DPM=100)
Test must detect 999,900
out of the 1,000,000 BAD
For 100 DPM: Needed Test Coverage = 99.99%
21 Jan 2013 EE-709@IITB 16 CADSL
 DPM and System Failure
Probability
Defective Parts per Million parts shipped:
 ~ 100 DPM (0.01%) for commercial ICs
 System with 10 ICs => 0.1% Failure Probability
 System with 100 ICs => 1.0% Failure Probability
 System with 500 ICs => 5.0% Failure Probability

 < 10 DPM Automotive Industry

Target : “Zero” defects!
21 Jan 2013 EE-709@IITB 17 CADSL
 Classical Yield Models
Two classes of Manufacturing Defects

 Gross or area defects

 Random Spot Defects

In mature well controlled processes, die yield

is mostly limited by random spot defects
- impossible to completely eliminate

21 Jan 2013 EE-709@IITB 18 CADSL

 Yield and Defect Density
The simplest defect distribution
x
model for semiconductor x x
wafers assumes that x
x x x
random spot defects are x
uniformly distributed
x x

=e −λ x
Die Yield

λ = Average number of defects per Die

= Defect Density (~ 0.2 - 1.0 per cm2) x Die Area

21 Jan 2013 EE-709@IITB 19 CADSL

 Yield and Defect Density

=e −λ
Die Yield x
λ = Average number x x
x
of defects per Die
x x x
= Defect Density x
x Die Area
x x

x
 Yield = 1/e (37%) for λ = 1
 Defect Density ~ 0.5 defects/sq cm
 Largest Die are ~ 2 sq cms

21 Jan 2013 EE-709@IITB 20 CADSL

 Defect Clustering on Wafers
The Poisson model has been
found to consistently x
underestimate yield x x x

This suggests, defects on x

semiconductor wafers are not x

uniformly distributed but are x

clustered x x
x

 For a given total number of defects on the

wafer, defect clustering results in more die with
multiple defects, and therefore more defect free
die (higher yield)
21 Jan 2013 EE-709@IITB 21 CADSL
 DPM depends on Yield
For Test Coverage: 99.99%
(Escapes 100 per million defective)
- 1 Million Parts @ 10% Yield
0.1 million GOOD >> shipped
0.9 million BAD >> 90 test escapes
DPM = 90 /0.1 = 900
- 1 Million Parts @ 90% Yield
0.9 million GOOD >> shipped
0.1 million BAD >> 10 test escapes
DPM = 10/0.9 = 11
21 Jan 2013 EE-709@IITB 22 CADSL
 Testing Large Complex Die
Testing large, complex low yielding die is the
biggest challenge

• Higher DPM even for equally effective (similar

“coverage” ) tests because of lower yields

• Difficult to achieve high coverage testing for

large complex die

• DPM increases non linearly with die complexity

21 Jan 2013 EE-709@IITB 23 CADSL

 Real Defect Types
Actual manufacturing defects, flaws,
variability etc. can have very complex
interactions leading to unpredictable
anomalous electrical behavior

• Permanent or hard faults

• Difficult to achieve high coverage testing for

large complex die

• DPM increases quite non-linearly with die

complexity
21 Jan 2013 EE-709@IITB 24 CADSL
 VLSI Testing
Fault Modeling
Virendra Singh
Associate Professor
Computer Architecture and Dependable Systems Lab
Department of Electrical Engineering
Indian Institute of Technology Bombay
http://www.ee.iitb.ac.in/~viren/
E-mail: [email protected]

Testing & Verification of VLSI Circuits

Lecture 6 CADSL
 Failure Rate Vs Product Lifetime

27 Jan 2013 EE-709@IITB 2 CADSL

 Definitions
Defect: A defect in an electronic system
is the unintended difference between the
implemented hardware and its intended
design
Error: A wrong output signal produced by
defective system is called error. An error
is an effect whose cause is some defect
Fault: A representation of a defect at the
abstracted function level is called a fault

27 Jan 2013 EE-709@IITB 3 CADSL

 Why Model Faults?
I/O function tests inadequate for
manufacturing (functionality versus
component and interconnect testing)
Real defects (often mechanical) too
numerous and often not analyzable
A fault model identifies targets for
testing
A fault model makes analysis possible
Effectiveness measurable by
experiments
27 Jan 2013 EE-709@IITB 4 CADSL
 Some Real Defects in Chips
 Processing defects
 Missing contact windows
 Parasitic transistors
 Oxide breakdown
 ...
 Material defects
 Bulk defects (cracks, crystal imperfections)
 Surface impurities (ion migration)
. . .
 Time-dependent failures
 Dielectric breakdown
 Electromigration
. . .
 Packaging failures
 Contact degradation
 Seal leaks
. . .

Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation -

Semiconductor Devices and Circuits, Wiley, 1981.

27 Jan 2013 EE-709@IITB 5 CADSL

 Electromigration
(a)

(b)

(c)

(a) Open in a line

(b) Short between two lines (whisker)
(c) Short between lines on different layers (hillock)

27 Jan 2013 EE-709@IITB

CADSL
6
Mapping Physical Defect into Faults 1

 Both the defective resistance in bipolar and a

the oxide breakdown in oxide between the
source and drain of the NMOS transistor form
a short failure mode
 Both cases are mapped into a stuck-at fault
27 Jan 2013 EE-709@IITB
CADSL
7
Mapping Physical Defect into Faults 2

A
A
A
Z Z Z

Poly Metal Diffusion

 Physical defect: A missing metal

o NMOS is missing the gate
 Failure mode: an open
 Fault: open
 A possible circuit representation is shown
27 Jan 2013 EE-709@IITB
CADSL
8
Mapping Physical Defect into Faults 3

L1 L1
L1 L1

L2 L2
L2 L2
(a ) (b )
(a ) (b )

S tu c k - a t 1 S tu c k -a t 0
V d d S tu c k -a t 1 G N D S tu c k -a t 0
V dd G N D
(c )
(c )

B r id g in g F a u lt
B r id g in g F a u lt
(d )
(d )

27 Jan 2013 EE-709@IITB 9 CADSL

 Observed PCB Defects

Defect classes Occurrence frequency (%)

Shorts 51
Opens 1
Missing components 6
Wrong components 13
Reversed components 6
Bent leads 8
Analog specifications 5
Digital logic 5
Performance (timing) 5
Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.

27 Jan 2013 EE-709@IITB 10 CADSL

 Failure Classification
IC Failures

Mode Duration

Incorrect Design Permanant

Hard
Parameter Degradation
Temporaty
Soft

Transient

Intermittent

27 Jan 2013 EE-709@IITB 11 CADSL

 Common Fault Models
Single stuck-at faults
Transistor open and short faults
Memory faults
PLA faults (stuck-at, cross-point,
bridging)
Functional faults (processors)
Delay faults (transition, path)
Analog faults

27 Jan 2013 EE-709@IITB 12 CADSL

 Single Stuck-at Fault
 Three properties define a single stuck-at fault
Only one line is faulty
The faulty line is permanently set to 0 or 1
The fault can be at an input or output of a gate
 Example: XOR circuit has 12 fault sites ( ) and 24 single
stuck-at faults Faulty circuit value
Good circuit value
c j
s-a-0 0(1)
a d 1(0)
1 g h
z
0 1 i
b e 1

f k
Test vector for h s-a-0 fault

27 Jan 2013 EE-709@IITB 13 CADSL

 SA Faults

27 Jan 2013 EE-709@IITB 14 CADSL

 SA Faults

27 Jan 2013 EE-709@IITB 15 CADSL

 Fault Equivalence
 Number of fault sites in a Boolean gate circuit =
#PI + #gates + # (fanout branches).
 Fault equivalence: Two faults f1 and f2 are
equivalent if all tests that detect f1 also detect f2.
 If faults f1 and f2 are equivalent then the
corresponding faulty functions are identical.
 Fault collapsing: All single faults of a logic circuit
can be divided into disjoint equivalence subsets,
where all faults in a subset are mutually
equivalent. A collapsed fault set contains one
fault from each equivalence subset.

27 Jan 2013 EE-709@IITB 16 CADSL

 Equivalence Rules
sa0 sa0
sa1 sa1
sa0 sa1 sa0 sa1 WIRE
sa0 sa1 sa0 sa1
AND OR

sa0 sa1 sa0 sa1

sa0 sa1
NOT
sa1 sa0

sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1 sa0
NAND NOR
sa1
sa0
sa0 sa1 sa0 sa1
sa1
sa0
FANOUT sa1

27 Jan 2013 EE-709@IITB 17 CADSL

 Equivalence Example
sa0 sa1
Faults in red
sa0 sa1 removed by
sa0 sa1 equivalence
collapsing
sa0 sa1 sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1 sa0 sa1
sa0 sa1

sa0 sa1 sa0 sa1

sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
20
Collapse ratio = ----- = 0.625
32

27 Jan 2013 EE-709@IITB 18 CADSL

 Fault Dominance
 If all tests of some fault F1 detect another fault F2,
then F2 is said to dominate F1.
 Dominance fault collapsing: If fault F2 dominates
F1, then F2 is removed from the fault list.
 When dominance fault collapsing is used, it is
sufficient to consider only the input faults of Boolean
gates.
 In a tree circuit (without fanouts) PI faults form a
dominance collapsed fault set.
 If two faults dominate each other then they are
equivalent.
27 Jan 2013 EE-709@IITB 19 CADSL
 Dominance Example
All tests of F2
F1
s-a-1 001
F2
s-a-1 110 010
000
101 011
100

s-a-1 Only test of F1

s-a-1
s-a-1
s-a-0
A dominance collapsed fault set

27 Jan 2013 EE-709@IITB 20 CADSL

 Checkpoints
 Primary inputs and fanout branches of a combinational
circuit are called checkpoints.
 Checkpoint theorem: A test set that detects all single
(multiple) stuck-at faults on all checkpoints of a
combinational circuit, also detects all single (multiple)
stuck-at faults in that circuit.
Total fault sites = 16

Checkpoints ( ) = 10

27 Jan 2013 EE-709@IITB 21 CADSL

 Multiple Stuck-at Faults
 A multiple stuck-at fault means that any set of
lines is stuck-at some combination of (0,1)
values.
 The total number of single and multiple stuck-at
faults in a circuit with k single fault sites is 3k-1.
 A single fault test can fail to detect the target
fault if another fault is also present, however,
such masking of one fault by another is rare.
 Statistically, single fault tests cover a very large
number of multiple faults.

27 Jan 2013 EE-709@IITB 22 CADSL

 Design Verification
Combinational Equivalence
Checking
Virendra Singh
Associate Professor
Computer Architecture and Dependable Systems Lab
Department of Electrical Engineering
Indian Institute of Technology Bombay
http://www.ee.iitb.ac.in/~viren/
E-mail: [email protected]

Testing & Verification of VLSI Circuits

Lecture 7 CADSL
 Example OBDD
Initial Graph Reduced Graph
x1 x1 (x1+x2)· x3

x2 x2 x2

x3 x3 x3 x3 x3

0 0 0 1 0 1 0 1 0 1

• Canonical representation of Boolean function

 For given variable ordering
 Two functions equivalent if and only if graphs
isomorphic
o Can be tested in linear time
 Desirable property: simplest form is canonical.
Jan 28, 2012 EE-709@IITB 2 CADSL
 Example Functions
Constants Variable

0 Unique unsatisfiable function x

Treat variable
1 Unique tautology as function
0 1

Typical Function Odd Parity

x1  (x1 ∨ x2 ) ∧ x4 x1

x2  No vertex labeled x3 x2 x2 Linear

 independent of x3 representation
x3 x3
 Many subgraphs shared
x4 x4 x4

0 1 0 1

Jan 28, 2012 EE-709@IITB 3 CADSL

Effect of Variable Ordering
(a ∧ b ) ∨ (a ∧ b ) ∨ (a ∧ b )
1 1 2 2 3 3
Good Ordering Bad Ordering
a1 a1

b1 a2 a2

a2 a3 a3 a3 a3

b2 b1 b1 b1 b1

a3 b2 b2

b3 b3

0 1 0 1
Linear Growth Exponential Growth

Jan 28, 2012 EE-709@IITB 4 CADSL

Selecting Good Variable Ordering
• Intractable Problem
 Even when problem represented as OBDD
i.e., to find optimum improvement to current
ordering

• Application-Based Heuristics
 Exploit characteristics of application
 e.g., Ordering for functions of combinational circuit
Traverse circuit graph depth-first from outputs to
inputs
Assign variables to primary inputs in order
encountered
Jan 28, 2012 EE-709@IITB 5 CADSL
 Sample Function Classes

Function Class Best Worst Ordering Sensitivity

ALU (Add/Sub) linear exponential High
Symmetric linear quadratic None
Multiplication exponential exponential Low

 General Experience
Many tasks have reasonable OBDD
representations
Algorithms remain practical for up to 500,000 node
OBDDs
Heuristic ordering methods generally satisfactory

Jan 28, 2012 EE-709@IITB 6 CADSL

 ROBDD sizes & variable ordering
• Bad News
– Finding optimal variable ordering NP-Hard
– Some functions have exponential BDD size for all orders
e.g. multiplier
• Good News
– Many functions/tasks have reasonable size ROBDDs
– Algorithms remain practical up to 500,000 node OBDDs
– Heuristic ordering methods generally satisfactory
• What works in Practice
– Application-specific heuristics e.g. DFS-based ordering for
combinational circuits
– Dynamic ordering based on variable sifting (R. Rudell)

Jan 28, 2012 EE-709@IITB 7 CADSL

 Operations with BDD (1/5)
 Restriction: A restriction to a function to x=d,
denoted f|x=d, where x ϵ var (f), and d ϵ {0,1},
is equal to f after assigning x = d.
 Given BDD of f, deriving BDD of f|x=d is simple

Jan 28, 2012 EE-709@IITB 8 CADSL

 Operations with BDD (2/5)
 Let v1, v2 denote root nodes of f1, f2
respectively , with var(v1) = x1 and var(v2) = x2
 If v1 and v2 are leafs, f1 OP f2 is a leaf node with
value val(v1) OP val(v2)

Jan 28, 2012 EE-709@IITB 9 CADSL

 Operations with BDD (3/5)
 If x1 = x2 = x, apply shanon’s expansion

f1 OP f2 = x’ . (f1|x=0 OP f2|x=0) + x . (f1|x=1 OP f2|x=1)

X OP X

BDD for BDD for BDD for BDD for

f1|x=0 f1|x=1 f2|x=0 f2|x=1

Jan 28, 2012 EE-709@IITB 10 CADSL

 Operations with BDD (4/5)
X X
OP

BDD for BDD for BDD for BDD for

f1|x=0 f1|x=1 f2|x=0 f2|x=1

BDD for BDD for

f1|x=0 OP f2|x=0 f1|x=1 OP f2|x=1

Jan 28, 2012 EE-709@IITB 11 CADSL

 Operations with BDD (5/5)
 Else suppose x1 < x2 = x, in variable order

f1 OP f2 = x’1 (f1|x1=0 OP f2) + x1 (f1|x1=1 OP f2)

X1

BDD for BDD for

f1|x1=0 OP f2 f1|x1=1 OP f2

Jan 28, 2012 EE-709@IITB 12 CADSL

 Operations with BDD: Example

X1

+
BDD for BDD for
f1|x1=0 OP f2 f1|x1=1 OP f2

f1=X1XNOR X2
f2=X’2

BDD for + =
=
f1|x1=0 OP f2

Jan 28, 2012 EE-709@IITB 13 CADSL

Operations with BDD: Example

X1
=

OP
BDD for BDD for
f1|x1=0 OP f2 f1|x1=1 OP f2

f1=X1XNOR X2
f2=X’2

= =

Jan 28, 2012 EE-709@IITB 14 CADSL

Operations with BDD: Example

Jan 28, 2012 EE-709@IITB 15 CADSL

 From Circuits to BDD
X1 G2

G1 G4

G3
X2
X1 X1 X1 X1 X1
1 0 1 0 0 1 0 1
0 1
X2 X2 X2 X2 X2 X2
1 0 1 0 1 1
0 1 0 1 0 0

0 1 0 1 0 1 0 1 0 1 0 1

Jan 28, 2012 EE-709@IITB 16 CADSL

 Variants of Decision Diagrams
• Multiterminal BDDs (MTBDD) – Pseudo Boolean functions
Bn → N, terminal nodes are integers
• Ordered Kronecker FunctionalDecision Diagrams (OKFDD)
– uses XOR in OBDDs
• Binary Moment Diagrams (BMD) – good for arithmetic
operations and word-level representation
• Zero-suppressed BDD (ZDD) – good for representing
sparse sets
• Partitioned OBDDs (POBDD) – highly compact
representation which retains most of the features of
ROBDDs
• BDD packages –
– CUDD from Univ. of Colorado, Boulder,
– CMU BDD package from Carnegie Mellon Univ.
– In addition, companies like Intel, Fujitsu, Motorola etc.
Jan 28, 2012 EE-709@IITB
have their own internal BDD packages
17 CADSL
 Formal Equivalence Checking
• Satisfiability Formulation A 0
1 T3
– Search for input assignment B 1 1 O2
1
giving different outputs C Diff
0 T1
• Branch & Bound A 0 0
1 1
– Assign input(s) C
1 O1
1
– Propagate forced values B T2
– Backtrack when cannot succeed

• Challenge
– Must prove all assignments fail
• Co-NP complete problem
– Typically explore significant
fraction of inputs
– Exponential time complexity

Jan 28, 2012 EE-709@IITB 18 CADSL

 SAT Problem definition

Given a CNF formula, f :

 A set of variables, V (a,b,c)
 Conjunction of clauses (C1,C2,C3)

 Each clause: disjunction of literals over V

Does there exist an assignment of Boolean values to the

variables, V which sets at least one literal in each clause
to ‘1’ ?
Example : (a + b + c)( a + c)( a + b + c)
a=b=c=1
C1 C2 C3

Jan 28, 2012 EE-709@IITB 19 CADSL

 DPLL algorithm for SAT
[Davis, Putnam, Logemann, Loveland 1960,62]
Given : CNF formula f(v1,v2,..,vk) , and an
ordering function Next_Variable
Example : a
0 1
(a + b)( a + c)( a + b)
b c
0 1 0 1
C1 C2 C3
CONFLICT!   
SAT!
C1 C3 C2 SAT!

Jan 28, 2012 EE-709@IITB 20 CADSL

 DPLL algorithm: Unit clause rule

Rule: Assign to true any single literal clauses.

(a + b + c)
c=1
=
=
0 0
Apply Iteratively: Boolean Constraint Propagation (BCP)

a ( a + c )( b + c )( a + b + c )( c + e)( d + e)( c + d + e)

c(b + c )( c + e)( d + e)( c + d + e)

e( d + e )
Jan 28, 2012 EE-709@IITB 21 CADSL
 Anatomy of a modern SAT solver

DPLL Algorithm Efficient BCP

Clause database Search Restarts

management To correct for bad
SAT choices in variable
Discard useless
clauses (e.g. inactive or Solver ordering
Restart algorithm
large clauses)
“periodically”
 Efficient garbage Retain some/all
collection recorded clauses
Conflict-driven
learning

Jan 28, 2012 EE-709@IITB 22 CADSL

 Pure Literal Rule
• A variable is pure if its literals are either
all positive or all negative
• Satisfiability of a formula is unaffected
by assigning pure variables the values
that satisfy all the clauses containing
them
ϕ = (a +c )(b+ c )(b + ¬d)(¬a + ¬b + d)

 Set c to 1; if ϕ becomes unsatisfiable, then it is also unsatisfiable when

c is set to 0.

Jan 28, 2012 EE-709@IITB 23 CADSL

 VLSI Testing
Automatic Test Pattern
Generation
Virendra Singh
Associate Professor
Computer Architecture and Dependable Systems Lab
Department of Electrical Engineering
Indian Institute of Technology Bombay
http://www.ee.iitb.ac.in/~viren/
E-mail: [email protected]

EE­709: Testing & Verification of VLSI Circuits

Lecture 14 (14 Feb 2013) CADSL
 ATPG - Algorithmic
 Path Sensitization Method
 Fault Sensitization
 Fault Propagation
 Line Justification

 Path Sensitization Algorithms

 D- Algorithm (Roth)
 PODEM (P. Goel)
 FAN (Fujiwara)
 SOCRATES (Schultz)
 SPIRIT (Emil & Fujiwara)

14 Feb 2013 EE-709@IITB 2 CADSL

Path Oriented DEcision
Making
(PODEM)
P. Goel, IBM, 1981

14 Feb 2013 EE-709@IITB 3 CADSL

 Motivation
 IBM introduced semiconductor DRAM
memory into its mainframes – late 1970’s
 Memory had error correction and
translation circuits – improved reliability
– D-ALG unable to test these circuits
Search too undirected
Large XOR-gate trees
Must set all external inputs to define
output
– Needed a better ATPG tool
14 Feb 2013 EE-709@IITB 4 CADSL
 PODEM
• New concepts introduced:
Expand binary decision tree only around
primary inputs
Use X-PATH-CHECK to test whether D-
frontier still there
Objectives -- bring ATPG closer to
propagating D (D’) to PO
Backtracing

14 Feb 2013 EE-709@IITB 5 CADSL

 PODEM High-Level Flow
1. Assign binary value to unassigned PI
2. Determine implications of all PIs
3. Test Generated? If so, done.
4. Test possible with more assigned PIs? If
maybe, go to Step 1
5. Is there untried combination of values on
assigned PIs? If not, exit: untestable fault
6. Set untried combination of values on
assigned PIs using objectives and backtrace.
Then, go to Step 2

14 Feb 2013 EE-709@IITB 6 CADSL

 PODEM-Algorithm
Start

Assign binary value to an unssigned PI

Deternine implications of all PIs

Yes
Test Is there a D or D’
generated on any PO?
No
May be
Test Possible with additional
Assigned PIs?

No

Is there an untried combination of No No test

No PIs?
Values on assigned exists
Yes
Set untried combination of vaues
On assigned PIs

14 Feb 2013 EE-709@IITB 7 CADSL

 PODEM

14 Feb 2013 EE-709@IITB 8 CADSL

 D-Algorithm : Example

1
D’

1
D

1
D’ D’
D’

1 0
1 D’ 1

14 Feb 2013 EE-709@IITB 9 CADSL

 PODEM : Example

14 Feb 2013 EE-709@IITB 10 CADSL

 PODEM : Value Comp

14 Feb 2013 EE-709@IITB 11 CADSL

 PODEM : Decision Tree

14 Feb 2013 EE-709@IITB 12 CADSL

 PODEM
PODEM doesn’t need
 Consistency check – conflict can never
occur
 J-frontier – there are no values that
require justification
 Backward implication – values are
propagated only in forward directions

14 Feb 2013 EE-709@IITB 13 CADSL

 Example
• Select path s – Y for fault propagation

sa1

14 Feb 2013 EE-709@IITB 14 CADSL

 Example -- Step 2 s sa1
• Initial objective: Set r to 1 to sensitize fault

sa1

14 Feb 2013 EE-709@IITB 15 CADSL

 Example -- Step 3 s sa1
• Backtrace from r

sa1

14 Feb 2013 EE-709@IITB 16 CADSL

 Example -- Step 4 s sa1
• Set A = 0 in implication stack

sa1

14 Feb 2013 EE-709@IITB 17 CADSL

 Example -- Step 5 s sa1
• Forward implications: d = 0, X = 1
1
1

0
0

sa1

14 Feb 2013 EE-709@IITB 18 CADSL

 Example -- Step 6 s sa1
• Initial objective: set r to 1
1
1

0
0

sa1

14 Feb 2013 EE-709@IITB 19 CADSL

 Example -- Step 7 s sa1
• Backtrace from r again
1
1

0
0

sa1

14 Feb 2013 EE-709@IITB 20 CADSL

 Example -- Step 8 s sa1
• Set B to 1. Implications in stack: A = 0, B = 1
1
1

0
0

1 sa1

14 Feb 2013 EE-709@IITB 21 CADSL

 Example -- Step 9 s sa1
• Forward implications: k = 1, m = 0, r = 1, q = 1,
Y = 1, s = D, u = D, v = D, Z = 1
1
1
0
0

1 0 sa1 D 1

1 1

D
D
1

14 Feb 2013 EE-709@IITB 22 CADSL

 Backtrack -- Step 10 s sa1
• X-PATH-CHECK shows paths s – Y and s–u–v–Z
blocked (D-frontier disappeared)
1
1

0
0

sa1

14 Feb 2013 EE-709@IITB 23 CADSL

 Step 11 -- s sa1
• Set B = 0 (alternate assignment)

0 sa1

14 Feb 2013 EE-709@IITB 24 CADSL

 Backtrack -- s sa1
• Forward implications: d = 0, X = 1, m = 1, r = 0,
s = 1, q = 0, Y = 1, v = 0, Z = 1. Fault not sensitized.
1
0
0
0
1
0 1 sa1
1
0

0
1

14 Feb 2013 EE-709@IITB 25 CADSL

 Step 13 -- s sa1
• Set A = 1 (alternate assignment)

sa1

14 Feb 2013 EE-709@IITB 26 CADSL

 Step 14 -- s sa1
• Backtrace from r again

sa1

14 Feb 2013 EE-709@IITB 27 CADSL

 Step 15 -- s sa1
• Set B = 0. Implications in stack: A = 1, B = 0

1
1

0 sa1

14 Feb 2013 EE-709@IITB 28 CADSL

 Backtrack -- s sa1
• Forward implications: d = 0, X = 1, m = 1, r = 0. Conflict: fault
not sensitized. Backtrack
1
0

1
0
1
0 sa1
1
1
0

0
1

14 Feb 2013 EE-709@IITB 29 CADSL

 Step 17 -- s sa1
• Set B = 1 (alternate assignment)

1 sa1

14 Feb 2013 EE-709@IITB 30 CADSL

 Fault Tested - Step 18 s sa1
• Forward implications: d = 1, m = 1, r = 1, q = 0, s = D, v = D, X = 0,
Y=D
0
1
1
1

1 1 sa1 D
D
0

D
D

14 Feb 2013 EE-709@IITB 31 CADSL

 Backtrace (s, vs)Pseudo-Code

v = vs;
while (s is a gate output)
if (s is NAND or INVERTER or NOR) v = v;
if (objective requires setting all inputs)
select unassigned input a of s with hardest
controllability to value v;
else
select unassigned input a of s with easiest
controllability to value v;
s = a;
return (s, v) /* Gate and value to be assigned */;

14 Feb 2013 EE-709@IITB 32 CADSL

 Objective Selection Code

if (gate g is unassigned) return (g, v);

select a gate P from the D-frontier;
select an unassigned input l of P;
if (gate g has controlling value)
c = controlling input value of g;
else if (0 value easier to get at input of
XOR/EQUIV gate)
c = 1;
else c = 0;
return (l, c );

14 Feb 2013 EE-709@IITB 33 CADSL

 PODEM Algorithm
while (no fault effect at POs)
if (xpathcheck (D-frontier))
(l, vl) = Objective (fault, vfault);
(pi, vpi) = Backtrace (l, vl);
Imply (pi, vpi);
if (PODEM (fault, vfault) == SUCCESS) return (SUCCESS);
(pi, vpi) = Backtrack ();
Imply (pi, vpi);
if (PODEM (fault, vfault) == SUCCESS) return (SUCCESS);
Imply (pi, “X”);
return (FAILURE);
else if (implication stack exhausted)
return (FAILURE);
else Backtrack ();
return (SUCCESS);
14 Feb 2013 EE-709@IITB 34 CADSL
FANout oriented test generation

FAN
(Fujiwara and Shimono, 1983)

14 Feb 2013 EE-709@IITB 35 CADSL

 Prof. Hideo Fujiwara
• Prof. Fujiwara is Eminent Researcher
and Academician in VLSI Testing
• Many contributions to VLSI Testing
• Co-founder of ATS and WRTLT
• Special Workshop was organized in
his honour with 20th IEEE ATS 2011

14 Feb 2013 EE-709@IITB 36 CADSL

 TG Algorithms

Objective

TG time reduction

 Reduce number of backtracks
 Find out the non-existence of
solution as soon as possible
 Branch and bound
14 Feb 2013 EE-709@IITB 37 CADSL
 FAN Algorithm

 New concepts:
Immediate assignment of
uniquely-determined signals
Unique sensitization
Stop Backtrace at head lines
Multiple Backtrace

14 Feb 2013 EE-709@IITB 38 CADSL

 FAN Algorithm
Strategies:
Strategy1:
 In step of the algorithm determine as many
signal values as possible
 Implication

Strategy 2:
 Assign faulty signal D or D’ that is
uniquely determined or implied by the
fault in question
14 Feb 2013 EE-709@IITB 39 CADSL
PODEM Fails to Determine Unique
Signals

• Backtracing operation fails to set all 3 inputs of

gate L to 1
– Causes unnecessary search

14 Feb 2013 EE-709@IITB 40 CADSL

FAN -- Early Determination of Unique
Signals

• Determine all unique signals implied by

current decisions immediately
– Avoids unnecessary search
14 Feb 2013 EE-709@IITB 41 CADSL
 PODEM Makes Unwise Signal
Assignments

0
0 1 0
1

Blocks fault propagation due to assignment J = 0

14 Feb 2013 EE-709@IITB 42 CADSL

 FAN – Unique sensitization

J=1
A=1 C=1 F =D’ H =D
K M
B=0

E =D
G =1 L=1

FAN immediately sets necessary signals to propagate fault

Unique sensitization and implication

Partial sensitization, which uniquely
determined, is called unique sensitization
14 Feb 2013 EE-709@IITB 43 CADSL
 FAN Algorithm

Strategies:
Strategy 3:
 When the D­frontier consists of a single gate, apply a unique
sensitization

Strategy 4:
 Stop the backtrace at a headline, and postpone the line
justification for the headline to later

14 Feb 2013 EE-709@IITB 44 CADSL

 Headlines
H M
E
F

K
A J

B L
C

• When a line L is reachable from a fanout point, L is

said to be bound
• A signal line that is not bound is said to be free
• When a line is adjacent to some bound line, it is said
to be head line
14 Feb 2013 EE-709@IITB 45 CADSL
 Decision Trees
H M
E
F

K
A J

B 0 L
C

A=1

J=1
B=1
B=0
J=0
C=1
C=0 Backtracking at Head-lines
PODEM

14 Feb 2013 EE-709@IITB 46 CADSL

 FAN Algorithm
Strategies:
Strategy 5:
 Multiple backtracing (concurrent
backtracing of more than one path) is more
efficient than backtracing along a single
path

Objective for multiple backtrace

 Triplet
 (s, n0(s), n1(s))
14 Feb 2013 EE-709@IITB 47 CADSL
 Multiple Backtrace

FAN – breadth-first
passes –
1 time

PODEM –
depth-first
passes – 6 times

14 Feb 2013 EE-709@IITB 48 CADSL

 VLSI Testing
Sequential ATPG
Virendra Singh
Associate Professor
Computer Architecture and Dependable Systems Lab
Department of Electrical Engineering
Indian Institute of Technology Bombay
http://www.ee.iitb.ac.in/~viren/
E-mail: [email protected]

EE­709: Testing & Verification of VLSI Circuits

Lecture 17 (28 Feb 2013) CADSL
 Sequential Circuits
 A sequential circuit has memory in addition to
combinational logic
 Test for a fault in a sequential circuit is a
sequence of vectors, which
 Initializes the circuit to a known state
 Activates the fault, and
 Propagates the fault effect to a PO
 Methods of sequential circuit ATPG
Time-frame expansion methods
Simulation-based methods
28 Feb 2013 EE-709@IITB 2 CADSL
 Example: A Serial Adder
An Bn
1 1
s-a-0
D
1

1 D
X
Cn
Cn+1
X
Combinational logic 1
Sn X
FF

28 Feb 2013 EE-709@IITB 3 CADSL

 Time-Frame Expansion

An-1 Bn-1 An Bn
Time-frame -1 Time-frame 0
1 1 1
s-a-0 1
D X s-a-0
D D
1 1
Cn-1 1 D X D
Cn 1 1
Cn+1
X
1
Combinational logic Combinational logic 1
Sn-1 Sn
X
D

FF

28 Feb 2013 EE-709@IITB 4 CADSL

 Concept of Time-Frames
 If the test sequence for a single stuck-at fault
contains n vectors,
 Replicate combinational logic block n times
 Place fault in each block
 Generate a test for the multiple stuck-at fault
using combinational ATPG with 9-valued logic
Vector -n+1 Vector -1 Vector 0
Fault

Unknown
Time- State Time- Time- Next
or given
frame variables frame frame state
Init. state
-n+1 -1 0
Comb.
block PO -n+1 PO -1 PO 0

28 Feb 2013 EE-709@IITB 5 CADSL

 Example for Logic Systems

FF1
B

A FF2
s-a-1

28 Feb 2013 EE-709@IITB 6 CADSL

 Five-Valued Logic (Roth)

A 0 A 0

s-a-1 s-a-1
D D
X X X
FF1 FF1

X D D
FF2 FF2

B X B X
Time-frame -1 Time-frame 0

28 Feb 2013 EE-709@IITB 7 CADSL

 Nine-Valued Logic (Muth)

A 0 A X

s-a-1 s-a-1
0/1 X/1
X 0/X 0/X
FF1 FF1

X 0/1 X/1
FF2 FF2

B X B 0/1
Time-frame -0 Time-frame

28 Feb 2013 EE-709@IITB 8 CADSL

 Implementation of ATPG
 Select a PO for fault detection based on drivability
analysis.
 Place a logic value, 1/0 or 0/1, depending on fault type
and number of inversions.
 Justify the output value from PIs, considering all
necessary paths and adding backward time-frames.
 If justification is impossible, select another PO and
repeat justification (use drivability).
 If the procedure fails for all reachable POs, then the
fault is untestable.
 If 1/0 or 0/1 cannot be justified at any PO, but 1/X or
0/X can be justified, the the fault is potentially
detectable.
28 Feb 2013 EE-709@IITB 9 CADSL
 Complexity of ATPG
Synchronous circuit -- All flip-flops controlled by clocks;
PI and PO synchronized with clock:
Cycle-free circuit – No feedback among flip-flops:
Test generation for a fault needs no more than
dseq + 1 time-frames, where dseq is the
sequential depth.
Cyclic circuit – Contains feedback among flip-
flops: May need 9Nff time-frames, where Nff is the
number of flip-flops.
Asynchronous circuit – Higher complexity!
Smax Time- Time- Time- Time- Time-
S3 S2 S1 S0
Frame Frame Frame Frame Frame
max-1 max-2 -2 -1 0

max = Number of distinct vectors with 9-valued elements = 9Nff

28 Feb 2013 EE-709@IITB 10 CADSL

 Cycle-Free Circuits
Characterized by absence of cycles
among flip-flops and a sequential depth,
dseq.
dseq is the maximum number of flip-
flops on any path between PI and PO.
Both good and faulty circuits are
initializable.
Test sequence length for a fault is
bounded by dseq + 1.
28 Feb 2013 EE-709@IITB 11 CADSL
 Cycle-Free Example
Circuit

F2

F3
F1
3
Level = 1 F2

2
s - graph
F1 F3 dseq = 3
Level = 1 3

All faults are testable.

28 Feb 2013 EE-709@IITB 12 CADSL

 Cycle-Free Example

0 1 2
­1

28 Feb 2013 EE-709@IITB 13 CADSL

 Difficulties in Seq. ATPG
 Poor initializability.
 Poor controllability/observability of state variables.
 Gate count, number of flip-flops, and sequential
depth do not explain the problem.
 Cycles are mainly responsible for complexity.
 An ATPG experiment:
Circuit Number of Number of Sequential ATPG Fault
gates flip-flops depth CPU s coverage

TLC 355 21 14* 1,247 89.01%

Chip A 1,112 39 14 269 98.80%

* Maximum number of flip-flops on a PI to PO path

28 Feb 2013 EE-709@IITB 14 CADSL

 Benchmark Circuits
Circuit s1196 s1238 s1488 s1494
PI 14 14 8 8
PO 14 14 19 19
FF 18 18 6 6
Gates 529 508 653 647
Structure Cycle-free Cycle-free Cyclic Cyclic
Sequential depth 4 4 -- --
Total faults 1242 1355 1486 1506
Detected faults 1239 1283 1384 1379
Potentially detected faults 0 0 2 2
Untestable faults 3 72 26 30
Abandoned faults 0 0 76 97
Fault coverage (%) 99.8 94.7 93.1 91.6
Fault efficiency (%) 100.0 100.0 94.8 93.4
Max. sequence length 3 3 24 28
Total test vectors 313 308 525 559
Gentest CPU s (Sparc 2) 10 15 19941 19183

28 Feb 2013 EE-709@IITB 15 CADSL

 VLSI Testing
Sequential ATPG
Virendra Singh
Associate Professor
Computer Architecture and Dependable Systems Lab
Department of Electrical Engineering
Indian Institute of Technology Bombay
http://www.ee.iitb.ac.in/~viren/
E-mail: [email protected]

EE­709: Testing & Verification of VLSI Circuits

Lecture 18 (04 March 2013) CADSL
 Sequential Circuits
 A sequential circuit has memory in addition to
combinational logic
 Test for a fault in a sequential circuit is a
sequence of vectors, which
 Initializes the circuit to a known state
 Activates the fault, and
 Propagates the fault effect to a PO
 Methods of sequential circuit ATPG
Time-frame expansion methods
Simulation-based methods
28 Feb 2013 EE-709@IITB 2 CADSL
 Difficulties in Seq. ATPG
 Poor initializability.
 Poor controllability/observability of state variables.
 Gate count, number of flip-flops, and sequential
depth do not explain the problem.
 Cycles are mainly responsible for complexity.
 An ATPG experiment:
Circuit Number of Number of Sequential ATPG Fault
gates flip-flops depth CPU s coverage

TLC 355 21 14* 1,247 89.01%

Chip A 1,112 39 14 269 98.80%

* Maximum number of flip-flops on a PI to PO path

28 Feb 2013 EE-709@IITB 3 CADSL

 Benchmark Circuits
Circuit s1196 s1238 s1488 s1494
PI 14 14 8 8
PO 14 14 19 19
FF 18 18 6 6
Gates 529 508 653 647
Structure Cycle-free Cycle-free Cyclic Cyclic
Sequential depth 4 4 -- --
Total faults 1242 1355 1486 1506
Detected faults 1239 1283 1384 1379
Potentially detected faults 0 0 2 2
Untestable faults 3 72 26 30
Abandoned faults 0 0 76 97
Fault coverage (%) 99.8 94.7 93.1 91.6
Fault efficiency (%) 100.0 100.0 94.8 93.4
Max. sequence length 3 3 24 28
Total test vectors 313 308 525 559
Gentest CPU s (Sparc 2) 10 15 19941 19183

28 Feb 2013 EE-709@IITB 4 CADSL

 Finite State Machines
 A fault in a machine M0 transforms into another
machine Mi with n or fewer states
 A test sequence is a sequence of inputs that
distinguishes M0 from each of Mi defined by a fault
 A synchronizing sequence for a sequential
machine M is an input sequence whose
application is guaranteed to leave M in a certain
final state irrespective of initial state of M
 A homing sequence for M is an input sequence
whose application makes it possible to determine
the final state of M by observing the corresponding
output sequence that M produces
28 Feb 2013 EE-709@IITB 5 CADSL
 Finite State Machines
 A distinguishing sequence is an input sequence
whose application makes it possible to determine
the initial state of M by observing the
corresponding output sequence M produces


28 Feb 2013 EE-709@IITB 6 CADSL

 Scan Design
Circuit is designed using pre-specified design
rules.
Test structure (hardware) is added to the verified
design:
Add a test control (TC) primary input.
Replace flip-flops by scan flip-flops (SFF) and connect
to form one or more shift registers in the test mode.
Make input/output of each scan shift register
controllable/observable from PI/PO.
Use combinational ATPG to obtain tests for all
testable faults in the combinational logic.
Add shift register tests and convert ATPG tests
into scan sequences for use in manufacturing test.
28 Feb 2013 EE-709@IITB 7 CADSL
 Scan Flip-Flop (SFF)
D Master latch Slave latch
TC
Logic
Q
overhead

MUX
SD Q

CK D flip-flop

CK Master open Slave open

t

TC Normal mode, D selected Scan mode, SD selected

t

28 Feb 2013 EE-709@IITB 8 CADSL

Level-Sensitive Scan-Design Flip-Flop
(LSSD-SFF)
Master latch Slave latch
D
Q

MCK Q

SCK D flip-flop

SD
MCK

Normal
mode
Logic TCK
overhead
TCK MCK

mode
Scan
TCK

SCK
t
28 Feb 2013 EE-709@IITB 9 CADSL
 Adding Scan Structure

PI PO

Combinational SFF SCANOUT

logic SFF

SFF

TC or TCK Not shown: CK or

MCK/SCK feed all
SCANIN SFFs.

28 Feb 2013 EE-709@IITB 10 CADSL

 Comb. Test Vectors

PI I1 I2 O1 O2 PO

Combinational
SCANIN
SCANOUT
TC
logic
Next
Present S1 S2 N1 N2 state
state

28 Feb 2013 EE-709@IITB 11 CADSL

 Comb. Test Vectors
Don’t care
or random
PI I1 I2 bits

SCANIN S1 S2
TC 0000000 1 0000000 1 0000000

PO O1 O2

SCANOUT N1 N2

Sequence length = (ncomb + 1) nsff + ncomb clock periods

ncomb = number of combinational vectors
nsff = number of scan flip-flops

28 Feb 2013 EE-709@IITB 12 CADSL

 Testing Scan Register
 Scan register must be tested prior to
application of scan test sequences.
 A shift sequence 00110011 . . . of length nsff+4
in scan mode (TC=0) produces 00, 01, 11 and
10 transitions in all flip-flops and observes the
result at SCANOUT output.
 Total scan test length: (ncomb + 2) nsff + ncomb +
4 clock periods.
 Example: 2,000 scan flip-flops, 500 comb.
vectors, total scan test length ~ 106 clocks.
 Multiple scan registers reduce test length.
28 Feb 2013 EE-709@IITB 13 CADSL
 Multiple Scan Registers
 Scan flip-flops can be distributed among any
number of shift registers, each having a
separate scanin and scanout pin.
 Test sequence length is determined by the
longest scan shift register.
 Just one test control (TC) pin is essential.
PI/SCANIN PO/
Combinational
M SCANOUT
logic U
SFF X

SFF
SFF

TC

CK

28 Feb 2013 EE-709@IITB 14 CADSL

 Scan Overheads
• IO pins: One pin necessary.
• Area overhead:
– Gate overhead = [4 nsff/(ng+10nff)] x 100%,
where ng = comb. gates; nff = flip-flops; Example
– ng = 100k gates, nff = 2k flip-flops, overhead
= 6.7%.
– More accurate estimate must consider scan
wiring and layout area.
• Performance overhead:
– Multiplexer delay added in combinational path;
approx. two gate-delays.
– Flip-flop output loading due to one additional
fanout;
28 Feb 2013approx. 5-6%.
EE-709@IITB 15 CADSL
 Hierarchical Scan
 Scan flip-flops are chained within
subnetworks before chaining subnetworks.
 Advantages:
Automatic scan insertion in netlist
Circuit hierarchy preserved – helps in
debugging and design changes
 Disadvantage: Non-optimum chip layout.
Scanin Scanout
SFF1 SFF4
SFF1 SFF3
Scanin
Scanout
SFF2 SFF3 SFF4 SFF2

Hierarchical netlist Flat layout

28 Feb 2013 EE-709@IITB 16 CADSL

 Optimum Scan Layout
X’
X

IO SFF
pad cell

SCANIN
Flip-
flop
cell
Y Y’

TC SCAN
OUT

Routing
channels
Interconnects Active areas: XY and X’Y’

28 Feb 2013 EE-709@IITB 17 CADSL

 ATPG Example: S5378

Original Full-scan
Number of combinational gates 2,781 2,781
Number of non-scan flip-flops (10 gates each) 179 0
Number of scan flip-flops (14 gates each) 0 179
Gate overhead 0.0% 15.66%
Number of faults 4,603 4,603
PI/PO for ATPG 35/49 214/228
Fault coverage 70.0% 99.1%
Fault efficiency 70.9% 100.0%
CPU time on SUN Ultra II, 200MHz processor 5,533 s 5s
Number of ATPG vectors 414 585
Scan sequence length 414 105,662

28 Feb 2013 EE-709@IITB 18 CADSL

Thank You

28 Feb 2013 EE-709@IITB 19 CADSL

 Design Verification
Sequential Equivalence
Checking
Virendra Singh
Associate Professor
Computer Architecture and Dependable Systems Lab
Department of Electrical Engineering
Indian Institute of Technology Bombay
http://www.ee.iitb.ac.in/~viren/
E-mail: [email protected]

EE-709: Testing & Verification of VLSI Circuits

Lecture 19 (05 March 2013) CADSL
 How to Represent States ?
❖ Not practical to represent individual states

❖ Represents set of states symbolically

❖ OBDD encodes boolean functions

❖ Code elements S
❖ Represent a subset T as boolean function fT

❖ fT = {0,1}n → {0.1}

05 Mar 2013 EE-709@IITB 2 CADSL

 How to Represent States ?
❖ Computation uses symbolic BFS approach
to all reachable states by shortest path
❖ Key step is image computation
➢ Img( δ(s,x), C(s))
❖ BFS allows to deal multiple states
simultaneously
❖ BDD is used to represent TF
❖ Let ti = δi(s,x) i = 1,2,…n
❖ C(s) is a symbolic state set

05 Mar 2013 EE-709@IITB 3 CADSL

 How to Represent TF ?
❖ Given a deterministic transition function (s,x) the
corresponding transition relation is defined by
➢ T(s,x,t) = Π (ti = δi(s,x))
❖ T(s,x,t) = 1 denotes a set of encoded tripples
(s,x,t) , each representing a transition in the FST
of a given FSM
❖ Straight forward to compute image
❖ Need new boolean operation
➢ Existential Abstraction
➢ $ xi.f = fxi + fx’i
➢ fxi- smallest (fewest minterm) function that contains
all minterms of f and independent of xi

05 Mar 2013 EE-709@IITB 4 CADSL

 How to Represent TF ?
❖ Given f(s,x) = f(s, .. sn, x1, …xm) the existential
abstraction w.r.t a set of variables is defined as
➢$x .f(s,x,) = $x1( $ x2( .. … $xm(f(s,x)))

❖ Procedure
➢ Compute TF, T(s,x,t)
➢ Compute conjunction of T and C
➢ Existentially abstract all s variable and all x
variable - provides I(t)
➢ I(t) is the smallest function independent of s
and x which contains all the tripples in f(s,x,t)

05 Mar 2013 EE-709@IITB 5 CADSL

State Reachability in Product FSM

00/0, 01/0, 11/0 00/1, 01/1, • t1 = δ11 = s’1x1x2’ + s1(x1 + x2)

11/0 10/1
0 1
• λ1 = δ11
M1 10/1

• Encoding: 0=00, 1=01, 2 =10

00/0, 01/0, 11/0

2 • t2 = δ22 = s3x1x2 + s2(x’1 + x2)

10/1 11/0
00/0, 01/0, 00/1, 01/1,
11/0 10/1
0
10/1
1 • t3 = δ23 = s’2x1x’2 + s3x’1
M2
• λ2 = s3x’1 + x1x’2

05 Mar 2013 EE-709@IITB 6 CADSL

 Symbolic FSM Traversal
Transition relation of the product machine
❖ T(s, x, t) = (t1 ≡ δ11). (t2 ≡ δ22). (t3 ≡ δ23)

❖ Initial State is s’1s’2s’3

❖ T(s,x,t).C(s) = T(s,x,t).s’1s’2s’3
= (t1≡s’1x1x2).(t2≡0).(t3≡s’2x1x’2). s’1s’2s’3

• Since this conjunction evaluate to 1 for just

one s-minterm (s’1s’2s’3)

05 Mar 2013 EE-709@IITB 7 CADSL

 Symbolic FSM Traversal
G(x,t) = $s(T(s,x,t).C(s))
= (t1 ≡ x1x’2).(t2 ≡ 0).(t3 ≡ x1x’2)
• Since this conjunction evaluate to 1 for just
one s-minterm (s’1s’2s’3)
• gx1x’2 = (t1 ≡ 1).(t2 ≡ 0).(t3 ≡ 1)
• gx’1x2 = gx’1x’2 = gx1x2 = (t1 ≡ 0).(t2 ≡ 0).(t3 ≡ 0)
• Img (T,C) = g (x,t) = t’1t’2t’3 + t1t’2t3

0.0 1.1

05 Mar 2013 EE-709@IITB 8 CADSL

 Symbolic FSM Traversal

❖ Implicit representation
❖ Graphs and their traversal are converted to
Boolean functions and Boolean operations
❖ BDD can be use for symbolic computation

05 Mar 2013 EE-709@IITB 9 CADSL

 Symbolic FSM Representation
• M (Q, S, d, q0, F)
• Characteristic Function

• Transition Function

05 Mar 2013 EE-709@IITB 10 CADSL

 Symbolic FSM Traversal

Relational representation of transition function

s2 = p1 + a2

05 Mar 2013 EE-709@IITB 11 CADSL

 Symbolic FSM Traversal
Transition relation

Next state
Present state: 00, Input: 10
T(0,0,s1,s2,0,1) = S1 . S2
11

Set of all next state for all possible inputs

05 Mar 2013 EE-709@IITB 12 CADSL

 Symbolic FSM Traversal
➢ set of all next states if the present state is either 00 or 11

characteristic function

Next state

05 Mar 2013 EE-709@IITB 13 CADSL

 Symbolic FSM Traversal
N(S1 , S2 ) = S1 + S2

Next Sates: 01, 10, 11

05 Mar 2013 EE-709@IITB 14 CADSL

 Forward Reachability
Forward Reachable States by Symbolic Computation
Input: transition relation T(p, s, a) and initial state I(s)
Output: a characteristic function R(s) of all reachable states
ReachableState(T, I):
1. Set S = I
2. Compute N(s) = $ (p,a)(T(p,s,a)·S(p))
3. R = S + N
4. If R S, set S = R and repeat steps 2 and 3; otherwise,
return R.

05 Mar 2013 EE-709@IITB 15 CADSL

 Forward Reachability
• BDD is used

05 Mar 2013 EE-709@IITB 16 CADSL

 Symbolic Model Checking
Forward Faulty State Reachability Analysis
Input: transition relation T(p, s, a), initial state I(s), and a fault
state F(s)
Output: a resolution on whether any faulty state is reachable
FaultyStateReachability(T, I, F):
1. Set S = I.
2. If (S·F) 0, return YES.
3. Compute N(s) = $(p, a)(T(p, s, a) ·S(p)).
4. R = S + N.
5. If R S, set S = R and repeat steps 2 through 5; otherwise,
return NO.

05 Mar 2013 EE-709@IITB 17 CADSL

CIRCUIT 1 Solving Seq. EC as Comb. EC

PI Comb. PO
Logic Combinational Equiv. Checking
PS1 NS1

Comb. PO
MATCH
LATCHES PI Logic 1 NS ?
=
PS PO
Comb.
CIRCUIT 2

Logic 2 NS
PS2 NS2
Comb.
PI Logic PO

05 Mar 2013 EE-709@IITB 18 CADSL

CIRCUIT 1 Combinational EC with BDD and SAT

PI Comb. PO
Logic Combinational Equiv. Checking
PS1 NS1

Comb. PO
MATCH
LATCHES PI Logic 1 NS ?
=
PS PO
Comb.
CIRCUIT 2

Logic 2 NS
PS2 NS2
Comb. Represent logic functions for this
PI Logic PO entire circuit with BDD or SAT

05 Mar 2013 EE-709@IITB 19 CADSL

 Methods for Latch Mapping
• Incomplete Methods
– Regular expression-based using latch names
– Using simulation (Cho & Pixley ‘97):
• Group latches with identical simulation signatures
– Group based on structural considerations e.g. cone of
influence
– Incomplete run of complete method below
(Anastasakis et al DAC ‘02)
• Complete Methods
– Functional fixed-point iteration based on Van Eijk’s
algorithm (van Eijk ’95)

05 Mar 2013 EE-709@IITB 20 CADSL

Van Eijk’s Method for Latch Mapping
Initial Latch
Mapping
Approximation
Comb.
NS Verify Latch
PI Logic 1
? Mapping
Apply Latch =
Assumptions
Mapping PS Comb. NS
Assumptions Logic 2

Iterate No Fixed-point ?

Yes
Done !!

05 Mar 2013 EE-709@IITB 21 CADSL

 Methods for Latch Mapping
• Incomplete Methods
– Regular expression-based using latch names
– Using simulation (Cho & Pixley ‘97):
• Group latches with identical simulation signatures
– Group based on structural considerations e.g. cone of
influence
– Incomplete run of complete method below
(Anastasakis et al DAC ‘02)
• Complete Methods
– Functional fixed-point iteration based on Van Eijk’s
algorithm (van Eijk ’95)

Feb 14, 2012 EE-709@IITB 23 CADSL

Move to System-Level Design
System-level design Architecture exploration

Barrier to adoption of
Manual effort System-level design
Methodology!

RTL
Current design
iterations
Gate-level design

Feb 14, 2012 EE-709@IITB 24 CADSL

 System-Level Verification
Property & Model
Checking

Manual effort
Equivalence
Checking

RTL

Gate-level design

Feb 14, 2012 EE-709@IITB 25 CADSL

 System-level Synthesis
System-level design

Automatic
Manual effort Synthesis

RTL

Gate-level design

Feb 14, 2012 EE-709@IITB 26 CADSL

 Quote from Clarke & Emerson 81

“The task of proof construction is in general quite tedious and a good deal of
ingenuity may be required to organize the proof in a manageable fashion.

We argue that proof construction is unnecessary in the case of finite state

concurrent systems and can be replaced by a model-theoretic approach which
will mechanically determine if the system meets a specification expressed in
propositional temporal logic.

The global state graph of the concurrent systems can be viewed as a finite Kripke
structure and an efficient algorithm can be given to determine whether a structure
is a model of a particular formula (i.e. to determine if the program meets its
specification)”.

Feb 14, 2012 EE-709@IITB 27 CADSL

 Design Verification
Model/Property Checking

Virendra Singh
Associate Professor
Computer Architecture and Dependable Systems Lab
Department of Electrical Engineering
Indian Institute of Technology Bombay
http://www.ee.iitb.ac.in/~viren/
E-mail: [email protected]

EE-709: Testing & Verification of VLSI Circuits

Lecture 24 (19 March 2013) CADSL
 Computation Tree Logics

P,q
P,q

q,r r r
q,r

p,q r r

q,r r r r

19 Mar 2013 EE­709@IITB 2 CADSL

 Semantics of LTL
• A transition system M = (S, →, L) is a set of
states S endowed with a transition relation
→ ( a binary relation on S), such that every
s ϵ S has some s’ ϵ S with s → s’, and a
labeling function L:S →P (Atomic)

• A path in a model M = (S, →, L) is an

infinite sequence of states s1, s2, s3, . . . . in
S such that, for each i ≥ 1, si → si+1.

• Path is represented as π = s1 → s2 → s3
→...
• πs1 = s → s2 → s3EE­709@IITB
→ . . . (path starting from
19 Mar 20131 3 CADSL
 Computation Tree Logics

P,q
P,q

q,r r r
q,r

p,q r r

π 1
1
q,r r r r

π 1
2

19 Mar 2013 EE­709@IITB 4 CADSL

 Syntax of LTL
Backus Naur Form

φ ::= T | ¬T | p | ¬φ | (φ ∧ φ ) | (φ ∨ φ ) | (φ → φ )
| ( X φ ) | (Fφ ) | (Gφ ) | (φUφ ) | (φW φ ) | (φ Rφ )

19 Mar 2013 EE­709@IITB 5 CADSL

 Semantics of LTL
Let be a model M = (S, →, L) and π = s1 → s2
… be a path in M. Whether π satisfy an LTL
formula is defined by the satisfaction relation |
π |follows:
=1..as =T
2.π |≠ I
3.π |= p, iff , p ∈ L( s1 )
4.π |= ¬φ , iff , π |≠ φ
5.π |= φ1 ∧ φ2 , iff , π |= φ1and , π |= φ2
6.π |= φ1 ∨ φ2 , iff , π |= φ1or , π |= φ2
7.π |= φ1 → φ2 , iff , π |= φ2 whenever , π |= φ1
19 Mar 2013 EE­709@IITB 6 CADSL
 Semantics of LTL
8.π |= X φ ,iff , π 2 |= φ
9.π |= Gφ ,iff ,∀i ≥ 1,π i |= φ
10.π |= Fφ ,iff ,∃i ≥ 1,s.t, π i |= φ
11.π |= φUϕ ,iff ,∃i ≥ 1,s.t, π i |= ϕ ,
and∀j = 1,2,...,i − 1, π j |= φ
12.π |= φW ϕ ,iff ,either∃i ≥ 1,s.t,π i |= ϕ ,
and∀j = 1,2,...,i − 1, π j |= φ ;or∀k ≥ 1, π k |= φ
13.π |= φ Rϕ ,iff ,either∃i ≥ 1,s.t, π |= ϕ ,
i

and∀j = 1,2,...,i, π j |= φ ;or∀k ≥ 1, π k |= φ

19 Mar 2013 EE­709@IITB 7 CADSL

 LTL Formula

19 Mar 2013 EE­709@IITB 8 CADSL

 Linear Temporal Logic
Rules
1. Fg. This operation succeeds if g holds at some Future
state, F. It can be expressed in terms of X and U as
(TRUE U g).
2. Gf. This operation succeeds if f holds at every state
along the path. In other words, f is Globally true. It can
be expressed as (~(F~f)).
3. fRg. This is the Release operator and it is equivalent to
~(~f U ~g). To understand its meaning, consider its
inverse, (~f U ~g), which has the interpretation of "f
held by g." If f and g are mutually exclusive (at most,
one can be high at any time), then (~f U ~g) means
that f must be low until g becomes low. In other words,
f must be held low when g is high. The inverse of "f
held by g" is f released
19 Mar 2013 by g or (f R g). 9
EE­709@IITB CADSL
 Linear Temporal Logic
Examples:
1. s0 |= p ^ q P,q

2. s0 |= ~r q,r r

3. s0 |= Xr
4. s0 |= X(q ^ r) does not hold p,q r r

5. s0 |= G ~(p ^ r) q,r r r r

19 Mar 2013 EE­709@IITB 10 CADSL

 Linear Temporal Logic ­ Equivalence

1. ¬ (φ ∧ ψ) Ξ (¬ φ ∨ ¬ ψ)
2. ¬ (φ ∨ ψ) Ξ (¬ φ ∧ ¬ ψ)
3. ¬ G φ Ξ F ¬ φ
4. ¬ F φ Ξ G ¬ φ
5. ¬ Xφ Ξ X ¬ φ

19 Mar 2013 EE­709@IITB 11 CADSL

 Linear Temporal Logic ­ Equivalence

1. ¬ (φ U ψ) Ξ (¬ φ R ¬ ψ)
2. ¬ (φ R ψ) Ξ (¬ φ U ¬ ψ)
3. F φ Ξ T U φ

4. G φ Ξ ¬T Rφ
5. φ U ψ Ξ φ Wψ ∧ F ψ

19 Mar 2013 EE­709@IITB 12 CADSL

 Linear Temporal Logic ­ Equivalence

1. φ W ψ Ξ φ Uψ ∨ G φ
2. φ W ψ Ξ ψ R (ψ ∨φ)

3. φ R ψ Ξ ψ W (ψ ∧ φ)
Essential Set
1. {U , X}
2. {R, X}
3. {W , X}

19 Mar 2013 EE­709@IITB 13 CADSL

 Delay Test
Virendra Singh
Associate Professor
Computer Architecture and Dependable Systems Lab
Department of Electrical Engineering
Indian Institute of Technology Bombay
http://www.ee.iitb.ac.in/~viren/
E-mail: [email protected]

EE­709: Testing & Verification of VLSI Circuits

Lecture 27 (26 March 2013) CADSL
 Definitions
Controlling value (cv) : An input of a gate
is said to have a controlling value if it
uniquely determines the output of the gate
independent of other inputs
For example, 0 for AND or NAND

A path R in a circuit is a sequence

(g0g1……gr), where g0 is a PI, g1g2.. are
gate outputs, gr is a PO
25 Mar 2013 EE-709@IITB 2 CADSL
 Definitions
 An on-input of path R is a connection
between two gates along path R

 A side-input (off-input) of path R is any

connection to a gate along path R other than
its on-input

 A path that starts at a primary input and ends

at a side-input of path R is called a side-path
of R

25 Mar 2013 EE-709@IITB 3 CADSL

 Transition Delay Fault

Two faults per gate; slow-to-rise and

slow-to-fall.
Tests are similar to stuck-at fault tests.
For example, a line is initialized to 0 and
then tested for s-a-0 fault to detect
slow-to-rise transition fault.
Models spot (or gross) delay defects.

25 Mar 2013 EE-709@IITB 4 CADSL

 Transition Delay Test

Path P1
1

D 1
D

P2 1
1
D’
1 D D
2 3
SA0 P3
1

25 Mar 2013 EE-709@IITB 5 CADSL

 Transition Delay Test
Single lumped inertial delay modeled for each gate
PI transitions assumed to occur without time skew
Path P1
0

D 1
0

D’
P2 1

D’
1 D D
2 3
SA0 P3
1

25 Mar 2013 EE-709@IITB 6 CADSL

 Transition Delay Test

Path P1
X0

0D 1
00

1D’
P2 1

1D’
01 0D 0D
2 3
SA0 P3
01

25 Mar 2013 EE-709@IITB 7 CADSL

 Path Delay Fault

Cheng’s classification
 Robustly testable
 Non-robustly (NR) testable
 Functional sensitizable (FS) testable
 Functionally unsensitizable (functionally
redundant)

25 Mar 2013 EE-709@IITB 8 CADSL

 Path Delay Fault
Robust testable : detect target PDF
independent of delays in rest of the
circuit.
It must satisfies the following conditions
It launches the desired transition at primary
input
All side inputs of target path settle to non-
controlling values under V2
Whenever the logic transition at an on-input
is from non-controlling to controlling value
(ncv to cv), each side-input should maintain
steady non-controlling value (ncv)
25 Mar 2013 EE-709@IITB 9 CADSL
 Path Delay Fault
Robust testable

25 Mar 2013 EE-709@IITB 10 CADSL

 Path Delay Fault
Non-Robust (NR ) testable :
 It must satisfies the following conditions
 It launches the desired transition at primary
input
 All side-inputs of target path settle to non-
controlling values (ncv) under V2

25 Mar 2013 EE-709@IITB 11 CADSL

 Path Delay Fault
Functional Sensitizable (FS) testable:
 Detection of faults on paths that are sensitizable
under FS criterion depends on the delays on
signals outside the target path
 It must satisfies the following conditions
It launches the desired transition at primary
input
Whenever the logic transition at an on-input
is non-controlling value (ncv) under vector
V2, each side-input should have non-
controlling value (ncv) under V2
25 Mar 2013 EE-709@IITB 12 CADSL
 Delay Test
Virendra Singh
Associate Professor
Computer Architecture and Dependable Systems Lab
Department of Electrical Engineering
Indian Institute of Technology Bombay
http://www.ee.iitb.ac.in/~viren/
E-mail: [email protected]

EE­709: Testing & Verification of VLSI Circuits

Lecture 28 (28 March 2013) CADSL
 Path Delay Fault

Cheng’s classification
 Robustly testable
 Non-robustly (NR) testable
 Functional sensitizable (FS) testable
 Functionally unsensitizable (functionally
redundant)

28 Mar 2013 EE-709@IITB 2 CADSL

 Path Delay Fault
Robust testable : detect target PDF
independent of delays in rest of the
circuit.
It must satisfies the following conditions
It launches the desired transition at primary
input
All side inputs of target path settle to non-
controlling values under V2
Whenever the logic transition at an on-input
is from non-controlling to controlling value
(ncv to cv), each side-input should maintain
28 Mar 2013 EE-709@IITB
steady non-controlling value (ncv)
3 CADSL
 Path Delay Fault
Robust testable

28 Mar 2013 EE-709@IITB 4 CADSL

 Path Delay Fault
Non-Robust (NR ) testable :
 It must satisfies the following conditions
 It launches the desired transition at primary
input
 All side-inputs of target path settle to non-
controlling values (ncv) under V2

28 Mar 2013 EE-709@IITB 5 CADSL

 Path Delay Fault
Functional Sensitizable (FS) testable:
 Detection of faults on paths that are sensitizable
under FS criterion depends on the delays on
signals outside the target path
 It must satisfies the following conditions
It launches the desired transition at primary
input
Whenever the logic transition at an on-input
is non-controlling value (ncv) under vector
V2, each side-input should have non-
controlling value (ncv) under V2
28 Mar 2013 EE-709@IITB 6 CADSL
 Path Delay Fault

28 Mar 2013 EE-709@IITB 7 CADSL

 Path Delay Fault
Functionally unsensitizable

28 Mar 2013 EE-709@IITB 8 CADSL

 Path Delay Fault
On-input Side-inputs Testability
cv -> ncv Stable cv Untestable
Stable ncv Robust
cv -> ncv
ncv -> cv Untestable
ncv -> cv Stable cv Untestable
Stable ncv Robust
cv -> ncv NR
ncv -> cv FS
28 Mar 2013 EE-709@IITB 9 CADSL
 Robust Test Conditions
 Real events on target path.
 Controlling events via target path.
V1 V2 V1 V2
V1 V2
V1 V2 U0
U1
U0
U1
U0/F0 U0/F0
U1/R1 U1/R1

V1 V2 V1 V2
S1 S0
S1 S0
U0/F0 U0/F0 U1/R1 U1/R1

28 Mar 2013 EE-709@IITB 10 CADSL

 A Five-Valued Algebra
 Signal States: S0, U0 (F0), S1, U1 (R1), XX.
 On-path signals: F0 and R1.
 Off-path signals: F0=U0 and R1=U1.
Input 1 Input 1
AND S0 U0 S1 U1 XX OR S0 U0 S1 U1 XX

S0 S0 S0 S0 S0 S0 S0 S0 U0 S1 U1 XX
U0 S0 U0 U0 U0 U0 U0 U0 U0 S1 U1 XX
Input 2

Input 2
S1 S0 U0 S1 U1 XX S1 S1 S1 S1 S1 S1
U1 S0 U0 U1 U1 XX U1 U1 U1 S1 U1 U1
XX S0 U0 XX XX XX XX XX XX S1 U1 XX

Input
S0 U0 S1 U1 XX Ref.:
NOT
Lin-Reddy
S1 U1 S0 U0 XX IEEETCAD-87

28 Mar 2013 EE-709@IITB 11 CADSL

 Robust Test Generation
Test for P3 – falling transition through path P3: Steps A through E

E. Set input of AND gate to

S0 to justify S0 at output
XX S0 S0
U0 D. Change off-path input
C. F0 interpreted as U0;
to S0 to Propagate R1
propagates through U0
through OR gate
AND gate

A. Place F0 at R1
path origin
Path P3
F0

XX F0 R1
U0 Robust Test:
B. Propagate F0 through OR gate; S0, F0, U0
also propagates as R1 through
NOT gate

28 Mar 2013 EE-709@IITB 12 CADSL

 Non-Robust Test Generation
Fault P2 – rising transition through path P2 has no robust test.

C. Set input of AND gate to

propagate R1 to output D. R1 non-robustly propagates
XX U1 through OR gate since off-
R1 path input is not S0
R1

Path P2 U1
A. Place R1 at
path origin
R1
R1 U1 U0 Non-robust test requires
XX Static sensitization:
S0=U0, S1=U1
U0
B. Propagate R1 through OR gate;
interpreted as U1 on off-path signal; Non-robust test:
propagates as U0 through NOT gate U1, R1, U0

28 Mar 2013 EE-709@IITB 13 CADSL

Functional Sensitizable TG

28 Mar 2013 EE-709@IITB 14 CADSL

 FS Untestable Faults
Fault P2 – falling transition through path P2 has no test.
D. F0 cannot be propagated
C. Set input of AND gate to through OR gate since off-
propagate F0 to output path input is not S0
XX S1
F0
F0

Path P2 S1
A. Place R1 at
path origin
F0
F0 U0 U1 NO TEST
XX
U0
B. Propagate R1 through OR gate;
interpreted as U1 on off-path signal; Non-robust test:
propagates as U0 through NOT gate U1, R1, U0

28 Mar 2013 EE-709@IITB 15 CADSL

 Slow-Clock Test
Input Combinational Output
latches circuit latches

Input Output
test clock Test Rated test clock
clock clock
period period
Input
test clock
Output
test clock
V1 V2
applied applied Output
latched

28 Mar 2013 EE-709@IITB 16 CADSL

 Enhanced-Scan Test
CK
period

PI Combinational PO
CK
circuit
CK TC

SCAN- HOLD
OUT HL SFF
Scanout
V1 settles result
HL SFF
SCANIN

Normal
Normal

mode
HOLD

mode
Scan mode
CK TC TC
CK: system clock Scanin Scanin
TC: test control V1 V2 states Result
HOLD: hold signal states latched
SFF: scan flip-flop V1 PI V2 PI
HL: hold latch applied applied

28 Mar 2013 EE-709@IITB 17 CADSL

 Normal-Scan Test
V2 states generated, (A) by one-bit scan shift of V1, or
(B) by V1 applied in functional mode. Result
latched
V1 PIs V2 PIs
PI Combinational PO applied applied
Scanin Gen. V2 Path Result
circuit tested
V1 states states scanout
SCAN- CK TC t
OUT Slow clock Rated
SFF CK period

TC

Normal
mode
Scan mode Scan mode
SFF (A)
SCANIN
Slow CK
CK TC period

CK: system clock TC

(B) Scan mode Normal mode Scan mode
TC: test control
SFF: scan flip-flop

28 Mar 2013 EE-709@IITB 18 CADSL

Built-In Self- Test
(BIST)
Virendra Singh
Associate Professor
Computer Architecture and Dependable Systems Lab
Department of Electrical Engineering
Indian Institute of Technology Bombay
http://www.ee.iitb.ac.in/~viren/
E-mail: [email protected]

EE­709: Testing & Verification of VLSI Circuits

Lecture 33 (08 April 2013) CADSL
 BIST Architecture

Note: BIST cannot test wires and transistors:

 From PI pins to Input MUX
 From POs to output pins

08 Apr 2013 EE-709@IITB 2 CADSL

 Pattern Generation
 Store in ROM – too expensive
 Exhaustive
 Pseudo-exhaustive
 Pseudo-random (LFSR) – Preferred method
 Binary counters – use more hardware than
LFSR
 Modified counters
 Test pattern augmentation
 LFSR combined with a few patterns in ROM
 Hardware diffracter – generates pattern
cluster in neighborhood of pattern stored in
08 Apr 2013 EE-709@IITB 3 CADSL
 Pseudo-Random Pattern
Generation

 Standard Linear Feedback Shift Register (LFSR)

 Produces patterns algorithmically – repeatable
 Has most of desirable random # properties
 Need not cover all 2n input combinations
 Long sequences needed for good fault coverage
08 Apr 2013 EE-709@IITB 4 CADSL
 Matrix Equation for Standard
LFSR

X0 (t + 1) 0 1 0 … 0 0 X0 (t)
0 0 1 … 0 0
X1 (t + 1) . . . . . X1 (t)
. . . . .
. = . . . . . .
. .
. 0 0 0 … 1 0 .
Xn­3 (t + 1) 0 0 0 … 0 1 Xn-3 (t)
1 h h2 … hn-2 hn-1
Xn­2 (t + 1) 1 Xn-2 (t)
Xn­1 (t + 1) Xn-1 (t)
X (t + 1) = Ts X (t) (Ts is companion matrix)

08 Apr 2013 EE-709@IITB 5 CADSL

 Response Compaction
 Severe amounts of data in CUT response to
LFSR patterns – example:
Generate 5 million random patterns
CUT has 200 outputs
Leads to: 5 million x 200 = 1 billion bits
response
 Uneconomical to store and check all of these
responses on chip
 Responses must be compacted

08 Apr 2013 EE-709@IITB 6 CADSL

 Definitions
 Aliasing – Due to information loss, signatures of
good and some bad machines match
 Compaction – Drastically reduce # bits in original
circuit response – lose information
 Compression – Reduce # bits in original circuit
response – no information loss – fully invertible
(can get back original response)
 Signature analysis – Compact good machine
response into good machine signature. Actual
signature generated during testing, and
compared with good machine signature
 Transition Count Response Compaction – Count
# transitions from 0 1 and 1 0 as a
signature
08 Apr 2013 EE-709@IITB 7 CADSL
 1’s Count Signature

4 3

4 3 3
2

08 Apr 2013 EE-709@IITB 8 CADSL

 Transition Counting

 Transition count:
m

C (R) = Σi =(r1i ⊕) for all m primary outputs

ri-1

 To maximize fault coverage:

Make C (R0) – good machine transition count
– as large or as small as possible

08 Apr 2013 EE-709@IITB 9 CADSL

 Transition Counting

08 Apr 2013 EE-709@IITB 10 CADSL

 LFSR for Response Compaction
• Use cyclic redundancy check code (CRCC) generator
(LFSR) for response compacter
• Treat data bits from circuit POs to be compacted as a
decreasing order coefficient polynomial
• CRCC divides the PO polynomial by its characteristic
polynomial
 Leaves remainder of division in LFSR
 Must initialize LFSR to seed value (usually 0) before
testing
• After testing – compare signature in LFSR to known
good machine signature
• Critical: Must compute good machine signature
08 Apr 2013 EE-709@IITB 11 CADSL
Example Modular LFSR
Response Compacter

• LFSR seed value is “00000”

08 Apr 2013 EE-709@IITB 12 CADSL

 Polynomial Division
Inputs X0 X1 X2 X3 X4
Initial State 0 0 0 0 0
1 1 0 0 0 0
0 0 1 0 0 0
Logic 0 0 0 1 0 0
Simulation: 0 0 0 0 1 0
1 1 0 0 0 1
0 1 0 0 1 0
1 1 1 0 0 1
0 1 0 1 1 0
Logic simulation: Remainder = 1 + x2 + x3
0 1 0 1 0 0 0 1
0 . x0 + 1 . x1 + 0 . x2 + 1. x3 + 0 . x4 + 0 .x5 + 0 .x6 + 1 .x7
08 Apr 2013 EE-709@IITB 13 CADSL
 Symbolic Polynomial Division

x2 +1
x5 + x3 + x + 1 +x
7 + x3
x
+ x5 + x3 + x2
x7 +x
x5 + x2
+x +1
remainder x5 + x3 +1
3 + x2
x
Remainder matches that from logic simulation
of the response compacter!

08 Apr 2013 EE-709@IITB 14 CADSL

 Multiple-Input Signature
Register (MISR)
• Problem with ordinary LFSR response compacter:
 Too much hardware if one of these is put on
each primary output (PO)
• Solution: MISR – compacts all outputs into one
LFSR
 Works because LFSR is linear – obeys
superposition principle
 Superimpose all responses in one LFSR – final
remainder is XOR sum of remainders of
polynomial divisions of each PO by the
characteristic
08 Apr 2013
polynomial
EE-709@IITB 15 CADSL
 MISR Matrix Equation

• di (t) – output response on POi at time t

X0 (t + 1) 0 1 … 0 0 X0 (t) d0 (t)
0 0 … 0 0
X1 (t + 1) . . . . X1 (t) d1 (t)
. . . .
. . . . . . .
. = 0 . .
. 0 … 1 0 . + .
Xn-3 (t + 1) 0 0 … 0 1 Xn-3 (t) dn-3 (t)
1 h1 … h
Xn-2 (t + 1) n-2 hn-1 Xn-2 (t) dn-2 (t)
Xn-1 (t + 1) Xn-1 (t) dn-1 (t)
08 Apr 2013 EE-709@IITB 16 CADSL
 Modular MISR Example

X0 (t + 1) 0 0 1 X0 (t) d0 (t)
= 1 0 1 +
X1 (t + 1) 0 1 0 X1 (t) d1 (t)
X2 (t + 1) X2 (t) d2 (t)
08 Apr 2013 EE-709@IITB 17 CADSL
 Multiple Signature Checking
• Use 2 different testing epochs:
1st with MISR with 1 polynomial
2nd with MISR with different polynomial
• Reduces probability of aliasing –
Very unlikely that both polynomials will alias
for the same fault
• Low hardware cost:
A few XOR gates for the 2nd MISR polynomial
A 2-1 MUX to select between two feedback
polynomials
08 Apr 2013 EE-709@IITB 18 CADSL
 Aliasing Probability
• Aliasing – when bad machine signature equals
good machine signature
• Consider error vector e (n) at POs
 Set to a 1 when good and faulty machines
differ at the PO at time t
• Pal ≡ aliasing probability
• p ≡ probability of 1 in e (n)
• Aliasing limits:
 0 < p≤ ½, ≤ pk P≤al (1 – p)k
≤ ≤ ≤k ≤
½ p 1, (1 – p) Pal pk
08 Apr 2013 EE-709@IITB 19 CADSL
 Aliasing Theorems
• Theorem : Assuming that each PO dij has probability
pj of being in error, where the pj probabilities are
independent, and that all outputs dij are independent,
in a k-bit MISR, Pal = 1/(2k), regardless of the
initial condition.

08 Apr 2013 EE-709@IITB 21 CADSL

 Transition Counting vs. LFSR
• LFSR aliases for f sa1, transition counter for a sa1

Pattern Responses
abc Good a sa1 f sa1 b sa1
000 0 0 1 0
001 1 1 1 0
010 0 1 1 0
011 0 1 1 0
100 0 0 1 1
101 1 1 1 1
110 1 1 1 1
111 1 1 1 1
Signatures
Transition Count 3 3 0 1
LFSR 001 101 001 010

08 Apr 2013 EE-709@IITB 22 CADSL

 Logic BIST
• Complex systems with multiple chips demand
elaborate logic BIST architectures
BILBO and test / clock system
Shorter test length, more BIST hardware
STUMPS & test / scan systems
Longer test length, less BIST hardware
• Benefits: cheaper system test, Cost: more hdwe.
• Must modify fully synthesized circuit for BIST to
boost fault coverage
 Initialization, loop-back, test point hardware
08 Apr 2013 EE-709@IITB 23 CADSL
 Test / Clock System Example
• New fault set tested every clock period
• Shortest possible pattern length
 10 million BIST vectors, 200 MHz test / clock
 Test Time = 10,000,000 / 200 x 106 = 0.05 s
 Shorter fault simulation time than test / scan

08 Apr 2013 EE-709@IITB 24 CADSL

 BILBO – Works as PG and RC

 Built-in Logic Block Observer (BILBO) -- 4 modes:

1. Flip-flop
2. LFSR pattern generator
3. LFSR response compacter
4. Scan chain for flip-flops
08 Apr 2013 EE-709@IITB 25 CADSL
 Complex BIST Architecture

• Testing epoch I:
 LFSR1 generates tests for CUT1 and CUT2
 BILBO2 (LFSR3) compacts CUT1 (CUT2)
• Testing epoch II:
 BILBO2 generates test patterns for CUT3
 LFSR3 compacts CUT3 response

08 Apr 2013 EE-709@IITB 26 CADSL

 Bus-Based BIST Architecture

 Self-test control broadcasts patterns to each CUT over bus –

parallel pattern generation
 Awaits bus transactions showing CUT’s responses to the
patterns: serialized compaction
08 Apr 2013 EE-709@IITB 27 CADSL
 Built-in Logic Block Observer
(BILBO)
• Combined functionality of D flip-flop, pattern generator,
response compacter, & scan chain
 Reset all FFs to 0 by scanning in zeros

08 Apr 2013 EE-709@IITB 28 CADSL

 Example BILBO Usage
 SI – Scan In
 SO – Scan Out
 Characteristic polynomial: 1 + x + … + xn
 CUTs A and C: BILBO1 is MISR, BILBO2 is LFSR
 CUT B: BILBO1 is LFSR, BILBO2 is MISR

08 Apr 2013 EE-709@IITB 29 CADSL

 BILBO Serial Scan Mode
 B1 B2 = “00”
 Dark lines show enabled data paths

08 Apr 2013 EE-709@IITB 30 CADSL

 BILBO LFSR Pattern
Generator Mode
• B1 B2 = “01”

08 Apr 2013 EE-709@IITB 31 CADSL

 BILBO in D FF (Normal) Mode

• B1 B2 = “10”

08 Apr 2013 EE-709@IITB 32 CADSL

 BILBO in MISR Mode

• B1 B2 = “11”

08 Apr 2013 EE-709@IITB 33 CADSL

 Test / Scan System
 New fault tested during 1 clock vector with a complete
scan chain shift
 Significantly more time required per test than test / clock
 Advantage: Judicious combination of scan chains and
MISR reduces MISR bit width
 Disadvantage: Much longer test pattern set length,
causes fault simulation problems
• Input patterns – time shifted & repeated
 Become correlated – reduces fault detection
effectiveness
 Use XOR network to phase shift & decorrelate
08 Apr 2013 EE-709@IITB 34 CADSL
 STUMPS Example
 SR1 … SRn – 25 full-scan chains, each 200 bits
 500 chip outputs, need 25 bit MISR (not 5000 bits)

08 Apr 2013 EE-709@IITB 35 CADSL

 STUMPS
 Test procedure:
1. Scan in patterns from LFSR into all scan chains (200
clocks)
2. Switch to normal functional mode and clock 1 x with
system clock
3. Scan out chains into MISR (200 clocks) where test
results are compacted
 Overlap Steps 1 & 3
 Requirements:
 Every system input is driven by a scan chain
 Every system output is caught in a scan chain or drives
another chip being sampled
08 Apr 2013 EE-709@IITB 36 CADSL
 Summary
 LFSR pattern generator and MISR response
compacter – preferred BIST methods
 BIST has overheads: test controller, extra circuit
delay, Input MUX, pattern generator, response
compacter, DFT to initialize circuit & test the test
hardware
 BIST benefits:
 At-speed testing for delay & stuck-at faults
 Drastic ATE cost reduction
 Field test capability
 Faster diagnosis during system test
 Less effort to design testing process
 Shorter test application times
08 Apr 2013 EE-709@IITB 37 CADSL
Thank You

08 Apr 2013 EE-709@IITB 38 CADSL

 Problem
• Consider a circuit with no self loops and
an S-graph that is a complete graph. In a
complete graph, a directed edge from a
vertex vi to vertex vj exists for all i and j.
Show that to convert into acyclic graph for
test generation you need to scan all but
one flip-flop.

08 Apr 2013 EE-709@IITB 39 CADSL