0% found this document useful (0 votes)
31 views6 pages

Bit Counter

Uploaded by

divyajhoshi5
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
31 views6 pages

Bit Counter

Uploaded by

divyajhoshi5
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 6

Bit Counter

Code-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity counter is

Port ( clk : in STD_LOGIC;

clr : in STD_LOGIC;

q : out STD_LOGIC_VECTOR(3 DOWNTO 0));

end counter;

architecture Behavioral of counter is

SIGNAL TMP: STD_LOGIC_VECTOR(3 DOWNTO 0);

begin
PROCESS(CLK,CLR)

BEGIN

IF(CLR='1') THEN

TMP<="0000";

ELSIF (CLK'EVENT AND CLK='1') THEN

TMP<=TMP+1;

END IF;

Q<=TMP;

END PROCESS;

end Behavioral;
Test bench-

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY counter_tb IS

END counter_tb;

ARCHITECTURE behavior OF counter_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT counter

PORT(

clk : IN std_logic;

clr : IN std_logic;

q : OUT std_logic_vector(3 downto 0)

);

END COMPONENT;

--Inputs

signal clk : std_logic := '0';

signal clr : std_logic := '0';

--Outputs
signal q : std_logic_vector(3 downto 0);

-- Clock period definitions

-- constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: counter PORT MAP (

clk => clk,

clr => clr,

q => q

);

-- Clock process definitions

process(clk)

begin

clk<='1';

clk<=not clk after 20ns;

end process;

process

begin

clr<='1'; wait for 20ns;

clr<='0'; wait;

end process;

end;

You might also like