Bit Counter
Bit Counter
Code-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
--use IEEE.NUMERIC_STD.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
clr : in STD_LOGIC;
end counter;
begin
PROCESS(CLK,CLR)
BEGIN
IF(CLR='1') THEN
TMP<="0000";
TMP<=TMP+1;
END IF;
Q<=TMP;
END PROCESS;
end Behavioral;
Test bench-
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.numeric_std.ALL;
ENTITY counter_tb IS
END counter_tb;
COMPONENT counter
PORT(
clk : IN std_logic;
clr : IN std_logic;
);
END COMPONENT;
--Inputs
--Outputs
signal q : std_logic_vector(3 downto 0);
BEGIN
q => q
);
process(clk)
begin
clk<='1';
end process;
process
begin
clr<='0'; wait;
end process;
end;