What is difference between IP and SOC?

Scope: IP verification involves verifying individual blocks or components (such as

CPUs, GPUs, memory controllers, etc.) that are designed to be reused across
multiple chip designs.

Scope: SoC verification involves verifying the entire system that includes multiple
IP blocks interconnected through buses, protocols, and other interfaces.

1.What is difference between AHB and AXI?

1.AHB: Has 1 address channel, 1 read data channel, 1 write data channel.

2.No concept of channels.

3.Burst Lengths are fixed i.e 1, 2, 6, 16 except for INCR types, where it can be
anything as long as it does not cross 4K boundary.

4.Write Strobes are not supported.

AXI:

1.Has 1 read address channel, 1 write address channel, 1 read data channel, 1 write
data channel. 1 write response channel That is altogether it has 5 parallel
channels. (The first AXI version had just 1 address channel)

2.AXI supports transaction IDs.

3.Burst lengths can be anything, from 1-16 for AXI3, and 1-256 for AXI4.

Write Strobes Are supported

2.Difference between Interleaving and Out of order?

Interleaving : It is like dividing a big task into smaller pieces and working on
them at the same time.

It helps speed up the process of getting the data from memory

Out of order:

It is like rearranging tasks in a to-do list to get things done faster.Both

techniques aim to improve system performance but at different.

3.What is polymorphism?

A.Polymorphism means having many forms. A base class handle can invoke methods of
its child class which has the same name. Hence, an object can take many forms.

(Or)

A) Any extended class object can be assigned to base class handle ,vise-versa not
possible.

On declaring a method as a virtual method, a base class handle can call the method
of its child class.

Class parent;

bit[31:0]data;

Int id;
Virtual function void display();

$display(“base: value of data=%0d,id=%0d”,data,id);

Endfunction

Endclass

class child_A extends parent;

function void display();

$display("Child_A: Value of data = %0d, id = %0d", data, id);

endfunction

endclass

class child_B extends parent;

function void display();

$display("Child_B: Value of data = %0d, id = %0d", data, id);

endfunction

endclass

class child_C extends parent;

function void display();

$display("Child_C: Value of data = %0d, id = %0d", data, id);

endfunction

endclass
What is difference between class and module?
A. modules are used to describe a hardware, so hardware is static~

classes are used to describe a testbench and as testbench can be changed, hence
they are dynamic.

What is difference between pass by reference and pass by value?

A. Pass by value : Pass by value is the default method through which arguments are
passed into functions and tasks. Each subroutine retains a local copy of the
argument. If the arguments are changed within the subroutine declaration, the
changes do not affect the caller.

In verilog, method arguments takes as pass by value.The inputs are copyed when the
method is called and the outputs are assigned to outputs when exiting the method.

(or)

Pass by value: if we update the value it will not update the value in the main
program.the reason behind is we have separate local copies for the variable

Pass by reference:

Ref is the keyword

In pass by reference functions and tasks directly access the specified variables
passed as arguments.Its like passing pointer of the variable.
In System Verilog ,methods can have pass by reference.Arguments passed by reference
are not copied into the subroutine area, rather, a reference to the original
argument is passed to the subroutine.

When we are working on arrays we use pass by reference

When we are working on scalar we using pass by value.

If we don’t want to change the array by task or function we will use

Const ref int a[];

Eg code for pass by value and pass by reference

module tb;

//////pass by value

task swap ( input bit [1:0] a, [1:0] b);

bit [1:0] temp;
temp = a;
a = b;
b = temp;
$display("Value of a : %0d and b : %0d", a,b);
endtask

//////pass by reference

task automatic swap ( ref bit [1:0] a, [1:0] b); /// function automatic bit [1:0]
add (arguments);
bit [1:0] temp;
temp = a;
a = b;
b = temp;

$display("Value of a : %0d and b : %0d", a,b);

endtask

////restrict access to variables

task automatic swap (const ref bit [1:0] a, ref bit [1:0] b); /// function
automatic bit [1:0] add (arguments);
bit [1:0] temp;

temp = a;
// a = b;
b = temp;

$display("Value of a : %0d and b : %0d", a,b);

endtask

bit [1:0] a;
bit [1:0] b;

initial begin
a = 1;
b = 2;

swap(a,b);

$display("Value of a : %0d and b : %0d", a,b);

end

endmodule

what are different types of array in systemverilog?

A. There are four types of arrays in system verilog

Static array
Dynamic array
Associative array
Queues

Array: An array is a collection of variables, all of the same type, and accessed
using the same name plus.
Static array:

A static array is one whose size is know before compilation time.

Static arrays are further categorized into packed and un packed array.

Packed array: A packed array is used to refer to dimensions declared before the
variable name.

bit[3:0] data;

Unpacked array: refer to dimensions declared after variable name

Byte stack [8];

Dynamic array:

A dynamic is an unpacked array whose size can be set or changed at the run time.

The default value of dynamic array is zero until it is set by the

new()constructor.

A dynamic array dimension are specified by empty square brackets.

1.function void delete()

2.New[]

3.function int size

Associative Arrays:
When size of a collection is unknown an associative array is a better
option .Associative array do not have any storage allocated until it is used.

QUEUES:

A system verilog Queues is a FIFO

It is similar to a one dimensional un packed array that grows and shrinks

automatically .Queues can passed to task/function as a ref or non ref arguments

Queues can be two types

1.bounded. (limited entry)

2.Un bounded(Unlimited entry)

7.Why IDs are used in channels?

A.system. They provide a structured and organized approach to manage data

exchanges, making complex systems more manageable and predictable.

8.How Burst transaction is reguired. exolain?

A.Burst transactions are required to efficiently transfer a large amount of data

between components in a

With burst transactions, the CPU can initiate a single read command, specitying the
starting address of the block and the number of data items it needs to read. The
memory controller then automatically sends a

9.What is deadlock condition?

A A deadlock condition can occur if the slave is waiting for WVALID before
asserting AWREADY.
What is super keyword?
A. With in a subclass to refer properties and methods of base class it is
mandatory to use super keyboard to access properties and methods.

Difference between p_sequencer and M_sequencer?

A.M_sequencer: m_sequencer is associated with a monitor and is responsible for

driving sequences.

m_sequencer is a handle available by default in a sequence.

No separate macro is needed for the declaration

P_sequencer:

p_sequencer does not actively drive sequences or generate transactions, thus is

also called a virtual sequencer

All sequences have a m_sequencer handle but they do not have a p_sequencer handle.

It is defined using macro `uvm_declare_p_sequencer(sequencer_name).

What are different types of code coverages?

A. There are four common ways to collect and calculate code coverage: function,
line, branch, and statement coverage.

1.Function coverage : 50%

2.Line Coverage: 62.5%

3.Branch Coverage: 80%

4.Statement Coverage: 55.55%

14.How will you use UVM and integrate it with c based test case?

A. By using DPI -C (Direct programming interface)

15.difference between SRAM and DRAM, bloacking and non blocking statement

A. SRAM (Static Random Access Memory) is faster, more expensive, and consumes more
power than DRAM (Dynamic Random Access Memory).

SRAM stores data in a flip-flop circuit, while DRAM stores data in a capacitor.
SRAM does not need to be refreshed, while DRAM requires periodic refreshing.

What is setup and hold time?

Setup time is the amount of time data must be stable before the clock edge for it
to be reliably captured.

Hold time is the amount of time data must be stable after the clock edge for it to
be reliably captured.

What is Synchronous reset and Asynchronous rest?

A. Synchronous reset means reset is sampled with respect to clock. In other words,
when reset is enabled, it will not be effective till the next active clock edge.

In asynchronous reset, reset is sampled independent of clk. That means, when reset
is enabled it will be effective immediately and will not check or wait for the
clock edges.

What is race condition?

A race condition occurs when two or more threads are using the same resources.
There are many examples of race conditions. A few are listed below.

Use synchronous updates where ever possible.

What is extern method?

An extern method provides a facility for class methods to define them outside of
the class body.

Factory Over ride methods?

Set_type_override_by_type
Set_type_override_by_name
Set_inst_override_by_type
set_inst_override_by_name

What are UVM components?

A. UVM _driver - Drives the signals to DUT

UVM_monitor- Monitor

UVM_Sequencer- Creates different Test patterns

UVM_agent

UVM_env - Contains all verification components

UVM_scoreboard- checks test is pass or fail

UVM_Subscriber- Subscribes to activities of other components

What is UVM_object,UVM_Component,UVM_sequence_item,UVM_sequence?

A. UVM_object : UVM Object

uvm_object is the base class in UVM from which all other UVM components and objects
are derived. Uvm_object itself is derived from uvm_void.

Define methods for common operations like copy, compare and print,
Clone,Record,Pack,Unpack,Convert2String. Typically used to build testbench and
testcase configurations.

UVM_Component: All testbench components like driver, monitor, scoreboards, etc are
indirectly derived from this class

UVM_sequence_item: All sequence items that need to be sent to a driver to be

driven onto the bus are extended from this class

UVM_Sequence: All sequences that define the stimulus or testcase are extended from
this class

What is UVC?(UVM verification component)

A. It is verification IP

When we buy UVC from IP vendor they will also provide stimulus

UVM virtual sequence: it is not but sequence of sequences

Using Task inside function?
A. module tb;

initial

repeat(2)

begin

fork

functio_n;

join

end

function functio_n;

$display($time, "\t function");

tas_k;

endfunction

task tas_k;

$display($time, "\t task");

endtask

endmodule

23. Handshake between driver and sequencer in UVM?

In UVM, the handshake between a driver and a sequencer is established through the
`get_next_item` and `item_done` methods.

24.What is the difference between == and === in SV?

The main difference between the two operators is how they compare values. The ==
operator compares the values of two variables after performing type conversion if
necessary. On the other hand, the === operator compares the values of two variables
without performing type conversion.

25. Different types of code coverage.

Block coverage – To check how many lines of code have been covered.
Expression coverage – To check whether all combinations of inputs have been driven
to cover expression completely.
FSM coverage – To check whether all state transitions are covered.
Toggle coverage – To check whether all bits in variables have changed their states.

26.Difference between fork-join, fork-join_any, and fork-join_none

In fork-join, all processes start simultaneously and join will wait for all
processes to be completed.

In fork-join_any, all processes start simultaneously and join_any will wait for any
one process to be completed.

In fork-join_none, all processes start simultaneously and join_none will not wait
for any process to be completed.

So, we can say that fork-join and fork-join_any is blocked due to process execution
time, whereas fork-join_none is not blocked due to any process

27. Difference between structure and class

Structure
Class
A structure can contain different members of different data types.
Classes allow objects to create and delete dynamically.
Does not supports inheritance, polymorphism
Supports inheritance, polymorphism
Data members of structure are visible to everyone
Data members of class can be protected and will not be visible outside of class.
Supports data abstraction
Supports only grouping of data.
28.Difference between new[ ] and new()

new[ ] – To create a memory. It can also be used to resize or copy a dynamic array.

new() – To create an object for the class, commonly known as ‘class constructor’.

29.Difference between reg and logic?

difference between structure and union in systemverilog?
A. In SystemVerilog, structures and unions are both used to store multiple data
types, but they differ in how they allocate memory and organize data:

Stores multiple data types of different sizes in an ordered group. Each data object
in a structure is a field or member, and all members can be accessed at any
time. Structures are declared using the struct keyword.

Stores multiple data types of the same size in the same location in
memory. However, only one member of a union can be accessed at a time. Unions are
declared using the union keyword, and only space is allocated for the largest
member.

Who to disable randomization?

A. rand_mode() to disable we use 0. To resume we use 1

32. UVM factory override?

A. 1 set_type_override_by_type

2. set_type_override_by_name

What is UVM call backs?

A. The callbacks are used to alter the behavior of the component or object without
modifying its code

Allows plug-and-play mechanism to establish a reusable verification environment.

Methods:

Add
Add_by_name
Delete
delete_by_name
What is difference between Config_db and TLM ports?
A.

1.Share interface: we use Config_db

2.Transaction data: We use TLM ports

Why run phase is task?

A.The run_phase is the phase where the sequence items are generated and processed.
This requires time. Only tasks can consume time. All the other phases are used to
construct, connect the components or to evaluate results (report_phase)

What is score board?

A. Uvm scoreboard is a verification component that contains checkers and verifies
the functionality of a design. It usually receives transaction level objects
captured from the interfaces of a DUT

Steps to create a UVM Scoreboard:

Create a custom class inherited from Uvm_scoreboard,register with factory and call
function new
Add necessary TLM exports to receive transactions from other components and
instantiat them in build phase
Define the action to be taken when data is received from the analysis port
Perform checks : It is not required to perform checks in the check_phase.Real
checkers can also actively check during the run_phase
Connect analysis ports of scoreboard with other components in the environment

After a scoreboard has been defined, you also need to instantiate it in the
environment and connect it with the appropriate analysis port.

What is difference between New and create?

A. New is the classic way used in system verilog for creating object instance.

Create is addition on used in UVM which is used to return object type which we
want.

What is a TLM Fifo?

A.when two components at different clocks need to operating independently, you
have to insert a TLM fifo in between. Where you can send data at a faster rate
while the other component can receive at a slower rate

39.How does sequence start?

A. Using start() method (or) by using the Marco ‘uvm_do.

What is difference between virtual sequence and virtual sequencers?

A. A virtual sequence is a container which is used to hold and execute other
smaller sequences.

A virtual sequencer is a container used to hold the handles of other sequencers in

a environment so that each sequence in a virtual sequence can be executed on
appropriate sequencer.

41.what is difference between ‘uvm_do and ‘uvm_send?

A.’uvm_do: Marco will automatically creates a new object randomize and sends it to
sequencers

‘uvm_send: when object is already created and randomised and need to be executed on
sequencer
Is it possible to have a user defined phase in UVM?
A. Yes,You can define your own phase and insert it in between the existing phases
which is inherited from Uvm_task_phase and implement the Exc_phase.

What is the difference between UVm_transaction and UVm-sequence_item?

A. Uvm_transaction class is the root base class for all transaction which used
timing and record

uvm_sequence_item is primarly used to defined data objects and related methods.

What are the different TB components in UVM?

A.Some of the major components are driver ,monitor, scoreboard, sequencer, agent,
environment

How do you connect driver and sequencer?

A. Driver has a TLM port called seq_item_port that can be connected with the
sequencer seq_item_export in an agent connect method.

What is UVM_config_db and uvm_resource_db?

A. UVm_config_db class provides convenice interface on top of the uvn_resource_db
to simplify the basic interface that is used for for configuring uvm_component
instance.