by J. G.

Ryan
The evolution of R. M. Geffken
N. R. Poulin
interconnection J. R. Paraszczak

teciinoiogy
at IBIVI

Advances in interconnection technology circuit density has increased by a factor of approximately

have played a icey role In allowing continued 10*, while cost has constantly decreased [e.g., the
improvements in integrated circuit density, historical 27% per year decline in price per bit for
performance, and cost. IBIUI contributions to dynamic random access memories (DRAMs)]. Innovation
interconnection technology over approximately in BEOL technology has been required in each technology
the last ten generations of semiconductor generation, since only part of the density increase could be
products are reviewed. The development of a achieved with improvements in lithography. For example,
planar, back-end-of-line (BEOL) technology, cell areas for the last five IBM DRAM generations [1-5]
used in IBIUI DRAIVI, bipolar, and CMOS are shown in Figure 1. Only a 2x decrease in cell area per
logic products since 1988, has led to a generation would have been possible through lithography
threefold increase in the number of wiring alone, whereas a 3x decrease has been required. The
levels, aggressive wiring pitches at all additional 1.5 x decrease has come from innovation.
Interconnection levels, and high-leverage Additional innovation will most likely be required in the
design options such as stacked contacts and future to continue this trend.
vias. Possible future BEOL technologies are The key competitive metrics for a multilevel-metal
also discussed, with emphasis on the use of interconnection technology are contacted metal pitch,
higher-conductivity wiring and lower-dlelectric- number of levels of wiring, and maximum number of wired
constant Insulators. It is expected that their circuits per chip. Contacted pitch is the minimum metal
use will result in higher performance and line width and spacing plus additions for via or contact
reliability. Applications include future, lower- covers or landing pads. Usually DRAM chips use fewer
power devices as well as more cost-effective, levels of metallization than logic chips of the same
higher-performance versions of present-day lithographic generation, but often exhibit tighter first-
designs. wiring-level contacted pitch because of array wiring
requirements. For static random access memory (SRAM)
and logic chips, multiple levels of metallization at an
Introduction aggressive contacted pitch are key to achieving high circuit
Evolutionary and revolutionary advances in density.
interconnection technology have played a key role in The interconnection technology currently used by IBM
allowing continued improvements in integrated circuit reflects a balancing of chip design requirements with
density, performance, and cost. Over the last 20 years. manufacturing process options available for metallization.
Copyright 1995 by International Business Machines Corporation. Copying in printed foim for private use is permitted without payment of royalty provided that (1) each
reproduction is done without afteration and (2) the Jounml reference and IBM copyright notice are included on thefirsrpage. The title and abstract, but no other portions, of
this paper may be copied or distributed royalty free without further permission by computer-based and other information-service systems. Permission to republish any other
portion of this paper must be obtained from the Editor. 371
Wia4646/95/$3.00 O t99S IBM

IBM J. RES. DEVELOP. VOL. 39 NO. 4 JULY 1995 J. G. RYAN ET AL.

 BEOL evolution
1998
Figure 2 shows the evolution of minimum flrst-wiring-level-
contacted pitch for IBM logic and memory semiconductor
products as a function of year of introduction into
manufacturing. Several notable sections of the curves
highlight technology changes. The 1975-1978 reduction in
pitch for logic products was a result of the change from
wet-etched Al-based wiring to the use of the lift-off
patterning method [9]. The prevailing metal patterning
technology in the early 1970s was wet subtractive etching,
but this technique limited the ability to achieve tighter
pitch because etching bias and tolerance were high
for Al, and even worse for the AI(Cu) alloys used for
0.1
1Mb 1Mb 16 Mb 64 Mb 256Mb electromigration resistance. Furthermore, wet etching
Generation undercut structures and formed holes in the metal at any
recursive topography on the wafer surface. These factors
drove IBM toward the use of a lift-off approach for metal
patterning, introduced into manufacturing in 1975, for
1>K\\1 .,-'1 I I 111 p SAMOS metal-gated DRAMs.
j v i r . lull The lift-off approach allowed significant improvements in
contacted metal pitch compared to that achievable with
wet etching [9], and continues to be used in some bipolar
and CMOS logic chip products. However, as metal pitch
was tightened with successive lithography generations,
insulators, planarization, and patterning. Chip topography and reflectivity issues reduced the acceptable
interconnections, or "interconnects," serve as local and hft-off process window. The migration from lift-off to metal
global wiring, connecting circuit elements and distributing reactive ion etching (RIE) occurred in 1986, during 1Mb
power [6]. To perform these functions, electrical properties DRAM production.
(e.g., resistivity) must be optimized, but interconnects In 1988, a planar BEOL technology was used in
also fimction as the interface between chip and package, the fabrication of the 4Mb DRAM product [7]. The
thereby also requiring stringent control of mechanical
properties. High electrical and mechanical reliability
must also be ensured for a successful interconnection
technology. A planar multilevel metallization architecture
• Metal-gated DRAM
[7] (introduced into IBM manufacturing in 1988) was the
« Si-gated DRAM
key innovation that improved interconnect structural
•# Logic products
integrity. Planarity was achieved by extensive use of
chemical-mechanical polishing (CMP) [8] and chemical
vapor deposition (CVD) of conformal metals (e.g.,
tungsten) [7]. Improving planarity provided improved
electrical and mechanical properties for BEOL films, s
thereby enhancing reliability. Additionally, improved IC

planarity facilitated continuous improvements in wiring

pitch, number of metal levels, and design features
0
such as stacked vias and local interconnects. 1975 1980 1985 19W W95 2(X)0

In this paper, we review contributions by IBM to Year

interconnection technology over approximately the last

ten generations of semiconductor products and discuss
future interconnection technology requirements and
opportunities. In addition, this paper serves as an M1 I •- I . I 1.1
11- II,\1 111 "i
introduction to the other papers presented in this
372 issue.

J. G. RYAN BT AL. IBM J. RES. DEVELOP, VOL. 39 NO. 4 JULY 1»5

combination of planarity and the use of W studs allowed
further reductions in ground rules by allowing minimum 10,0(MK
lithographic dimensions to be used in interconnect
fabrication. Improved planarity also allowed pitch
a lOOOK
reductions at upper wiring levels. For example, in 1978
the pitch of the second level of wiring (M2) for IBM
logic products was 20 fim, whereas in 1994 upper-level 4 lOOK
wiring pitches were 1.8 fjxn [10,11].
Metal polishing at via levels was the first :: lOK F
microelectronics use of the metal patterning technique
known as "damascene" (now in wide use in both DRAM
and logic chip manufacturing). This technique involves
etching trenches or vias in an insulating layer which is s
a I. J I I I I I I i..., I I I ' I
then filled with metal. CMP is then used to remove the
•77 '79 '81 '83 '85 '87 *89 '91 *93 '95 '97 '99
extraneous material until only the metal in the trenches Year

Maximum number of wirable logic circuits per chip vs. year of

i introduction
introduction into
mto IBM manufacturing.
IBM manutactuni
ID /joal ID iimJ
2.7 JUKI 2.2 ^m

• •• •
1.2 Mm/ 12 ion/
•
QM/iml
D • • • • • •
0 3 (tm/
2.4 jum 3.3 jU.m 1,4 ftm OSSixm
or vias remains. The damascene technique has been
• •
I2fua/
• M
0.1 fim/
• 05 •fum/• • DPP
0.33 jum/
E2 1^ ! S SS ^

Ol/jtm/
E3
principally used for tight-pitch tungsten wiring and via
levels, but is also extendable to other materials [12-14]. Its
3.0 jam 1.9 jum lAixm Q.85 jam 05.5 ^m
advantages include easier metal patterning (less sensitive
1Mb 4Mb 16Mb 64Mb 256Mb
to metal composition), easier lithographic alignment,
(a)
improved planarity, better tool clustering logistics, and
fewer process steps [15].
Figure 3{a) is a schematic of wiring levels over the last
five generations of IBM DRAM products. The number of
wiring levels for IBM n-MOS and CMOS logic circuit
products is shown in Figure 3(b). The available number of
metal wiring levels has tripled over the last ten years for
both logic and memory products. When the approaches
used by IBM are compared with industry trends [16], it is
I apparent that tighter metal pitches have been used ahead
of most of the industry. This advantage combined with a
planar architecture has made it possible to produce chips
halving high circuit densities, as depicted in Figure 4. The
•75 '77 "79 '81 '83 '85 '87 '89 '91 '93 '95 maximum number of wirable logic circuits per chip vs.
Year year of introduction into manufacturing is sho'wn for
(b)
various IBM chip technology generations, demonstrating
that the number has increased by an order of magnitude
every 5.5 years since 1977. In addition to considerable
improvements in contacted metal pitch and planarity,
(a) Schematic of wiring levels of tMb-256Mb IBM DRAM increased circuit count for both DRAM and logic
products. Levels depicted in black represent Al(Cu)-based wiring;
those depicted in grey represent W-based wiring. "Values of wire technologies has been made possible by increasing the
thickness/minimum pitch are shown for each level, (b) Number of number of metal levels, making use of stacked contacts
wiring levels vs. date of manufacturing introduction of IBM and vias, and increasing chip size. More than one million
n-MOS and CMOS logic circuit products.
wired circuits can now be contained on a single logic chip,
in contrast to thirteen thousand just ten years ago. This is 373

IBM J. RES. DEVELOP. VOL. 39 NO. 4 JULY 1995 J. G. RYAN ET AL.

 r- 1995
• Borderless contacts

•• 5 LM CMOS logic BEOL •• 6 LM BEOL

• Laser-deleted metal fuses • Dual-damascene
1990 - stud & wire
• CVD W studs
» CVD W wires • High-reliability layered
• CVD WSij polycide winng
• Oxide CMP
• WCMP • High Cu% Al RIE - 1985
• Ti salicide strap, • Laser-deleted polycide fuses
diffusions & gate
• Ti contacts/redundant • 4 LM bipolar BEOL
conductor - 1980
• Lift-off metal patterning
• Polyimide ILD
• AlCuSi wiring
- 1975

• Al-Cu alloy

1970 - • 3 LM bipolar BEOL

• RF sputtered SiOj - 1965

• Flip-chip solder bumps (C4)-
• Al-Si alloy

- 1960
Year

Chronology of key IBM interconnection technology introductions into manufacturing. Years of introduction are indicated, 'LM" denotes
levels of metallization.

consistent with even the most optimistic predictions of In many cases, innovations have more than one driving
nearly a decade ago [17]. force. Cost reductions can result from either process step
reduction/simplification or final yield enhancement. Al(Si)
Enabling technologies metallurgy [18], fuse technology advances, Ti contacts
Over the years, IBM has pioneered a number of key [19], and dual damascene structures [15] (see Figure 5)
interconnection technology advances. Many are now part were all instituted to enhance yield, although each had
of the mainstream processes of most semiconductor the side benefit of widening process windows as well.
manufacturers. A chronology of the associated technology Al{Cu) alloy wiring is an example of an innovation
introductions is shown in Figure 5. Technology directed at enhancing reliability. Al(Cu) alloys have been
introductions are usually linked to product programs, as used since the late 1960s to alleviate electromigration
can be understood from the timing shown in the figure. In concerns associated with Al(Si) metallurgy [20]. To further
most cases, several introductions occurred within a year enhance reliability, IBM pioneered the use of thin layers of
because they were part of the same product program. For refractory metals, including the use of Ti, above and below
example, CVD W wiring, CMP of metals and oxides, and the AI(Cu) alloy layers. The refractory metals reduce
titanium-salicided gates and diffusions were all introduced contact resistance and provide an immobile redundant
as part of the IBM 4Mb DRAM technology. It can also be layer capable of shunting currents over small voids, thus
discerned from Figure 5 that the rate of new technology improving electromigration and stress-migration resistance
introductions appears to be increasing. [21]. It is believed that multilayered, Al(Cu)-based
The introductions occur for several reasons, including interconnects will persist as the chip wiring material into the
cost reductions, reliability enhancements, design late 1990s because of their pervasiveness and acceptance in
374 requirements, or extendability to future products. the semiconductor industry. A multilayered conductor

J. G. RYAN ET A L . IBM J. RES. DEVELOP. VOL. 39 N O . 4 JULY 1995

•mi;
Scanning electron micrograph cross sections of structures fabricated using planar BEOL process: (a) BEOL portion of a QS-ftm CMOS logic
chip currently in production; note that a local interconnect level and five global interconnect levels are used, (h) Stacked contacts and vias.
From [1IJ, reproduced with permission.

approach is also used for tungsten-based wiring. Titanium manufacturing. Processes that can be common to several
is used in combination with titanium nitride as a liner product types or generations are needed for low-cost
beneath CVD W studs. The Ti contact material dramatically manufacturing. For example, the IBM lead-tin solder
reduces contact resistance, while the TiN barrier layer bumpflip-chiptechnology for off-chip connection was
improves contact stability, reliability, and Wfilmadhesion [22]. developed in the 1960s and provides significant advantages
Many innovations are driven by design requirements which reduce chip wiring costs. Its key advantage occurs
such as additional wiring levels [10, 11, 23], new materials where power is delivered to a large chip and redistributed.
(e.g., silicides [24]), or new structures (planar wiring [7], Where edge connection (such as wire bonding) is used,
borderless contacts [3, 4, 12], solder bump "flip-chip" long, wide, and thick buses must be used to deliver power
structures for off-chip connection [25]). Many unit process to the correct point on the chip. By using the solder bump
innovations are needed to successfully produce new approach, these large buses can be fabricated in the
design-driven, integrated structures. For example, package, thus allowing power to be delivered with low
Ti/TiN/CVD W [22], oxide CMP, and metal CMP were all inductance. This technology is still viable today and
developed in order to achieve planar BEOL structures. is pivotal in reducing the cost of large, high-speed processors.
Often, revolutionary approaches are required to meet
design needs, even though evolutionary change Current technologies
from the current manufacturing process is more easily Planar BEOL technology has been used in IBM DRAM,
accommodated. It is logistically undesirable to maintain bipolar, and CMOS logic programs since its introduction
multiple processes intended to produce similar structures into manufacturing in 1988. A cross-sectional scanning
for different products or generations of products. Therefore electron micrograph of the BEOL portion of a 0.5-/nm
the extendability of a process innovation is a key criterion CMOS logic chip currently in production is shown in
in ascertaining whether it is suitable for introduction into Figure 6(a). A local interconnect level and five 375

IBM J. RES. DEVELOP. VOL. 39 NO. 4 JULY WM J. G. RYAN ET AL.

 CMP process yields better global planarization than the
^AIR = 0.5 calculated -O-AIR = 0.5 calculated reflow process, as well as a wider lithographic process
7 - i-A/ff = 1.0 calculated S-AIR = 1.0 calculated window for the critical first wiring layer. Finally, CMP
^AJR = 2.0 calculated -is-A/R = 2.0 calculated
* A/R from 1.6 to 1 measured oxide planarization is a prerequisite for utilizing W CMP
i from 2.1 to 1.1 measured for forming local interconnect or stud structures.
Ti/Al(Cu)/Ti The first global wiring layer [Ti/Al(Cu)/Ti/TiN] is
deposited, and photoresist is applied and patterned. This
metal layer is then reactive-ion-etched using a chlorine-
based plasma. A gap-filling oxidefilmis then deposited and
subsequently planarized using CMP. A second oxide film
is then deposited on the polished oxide to provide a dual
0.4 0.6
Linewidth (/Am) interlevel dielectric. The apphcation of the first via mask
on this oxide surface is the initial step of the next wiring
layer process. This set of process steps can be repeated as
needed in order to form the total number of wiring levels
required. The planar structure faciUtates the use of stacked
Comparison of effective resistivity vs. linewidth for damascene Cu wires
having Ta liners and Ti/Al(Cu)/Ti wires patterned by RIE. From [29], contacts and vias [Figure 6(b)]. The modular nature of the
reproduced with permission. process also allows defect and reliability learning to be
applied to all metal levels.
At the option of the device designer, the final level of
wiring can be specified to be at the same tight pitch as the
global interconnect levels are used. To improve prior levels, or at a more relaxed pitch, using a thicker,
manufacturability, a repetitive modular process flow is lower-resistance conducting layer. A tapered via rather
used in which the materials and sequence of steps are than a stud may be used with this latter option to reduce
identical for each interconnect level. Only horizontal and manufacturing costs. Planarization is not performed
vertical dimensions distinguish the different metal process after the last wiring level. Thefinalpassivation layers
modules. (SiOj/SiN^/polyimide) are formed and patterned. The final
via level also opens the fuse areas if redundant elements
The initial steps in the process flow to form the structure
are used in the design. Connections to packages can then
shown in Figure 6 are deposition and CMP planarization
be made by means offlip-chip,tape-automated-bonding, or
of the phosphosilicate glass (PSG) used to passivate the wire-bonding methods, depending on product requirements.
front-end-of-line (FEOL) portion of the structure. After
Some additional unique features of this modular process
polishing, a contact/local interconnect [11] mask is formed,
should be noted. The Al(Cu)filmsutilize an overlying and
and openings are etched in the PSG film to the titanium
underlying, redundant TiAlj refractory layer, which has
salicided gates and diffusions. After stripping the
been shown to be relatively immune to reliabihty failures
photoresist used for etching, Tifilmsare directionally from either electromigration or stress-migration
deposited using collimated sputtering [13]. TiNfilmsare mechanisms. The lithographic process window at both
then sputtered onto the Ti to act as a barrier and adhesion metal and contact/via levels is relatively wide because of
layer for CVD W, which is deposited next. CMP is used the superior global planarization obtained by using CMP
to remove excess metal, making the tops of the W studs and the incorporation of a TiN antireflective coating (ARC)
and/or local wires thus formed coplanar with the PSG. as the uppermost layer of the interconnect stack. The
If a local interconnect level is used (as in thefigure),the interconnect deposition window is relatively wide because
process sequence is repeated to form W contact studs of the planarity of the surface between oxide and tungsten
prior to formation of the first global interconnect level. stud regions (i.e., step coverage is not an issue).
The process sequence described above is a significant The key unit process choice for this technology was the
departure from the reflowed boron-phosphosilicate glass extensive use of CMP planarization for both metals and
(BPSG) sequence used by most device manufacturers. oxide. Although the planarizing capability of CMP is
Utilization of PSG retains the ionic gettering properties excellent, it was also chosen for its ability to remove prior
required of this layer while simplifying chemical aspects level defects [8] and to be part of a robust interlevel
and avoiding various crystalline defects associated with metal-insulator process. Dual-insulator schemes have
BPSG. The thermal processing requirements for this proven to be relatively immune to interlevel metal shorting
process sequence are less stringent than the requirements defects [9]. A process flow consisting of gap-filling oxide
for BPSG reflow and are less likely to cause siUcide deposition/oxide polishing/cap oxide deposition is an
376 agglomeration or other harmful device degradation. The extremely effective embodiment of this concept.

J. G. RYAN ET AL. IBM J. RES. DEVELOP. VOL. 39 NO. 4 JULY 1995

 The tight metal pitches needed on multiple wiring levels
require near-vertical, zero-overlap via studs. An alternative
to forming W studs by means of CMP is to make use of
reactive ion etchback; however, its use results in an
extremely tight manufacturing process window and a
process that is prone to yield and reliability defects. Any
number of processes such as insulator deposition, via
etching, photoresist removal, liner deposition, and W
deposition can deposit particulates on the insulator
surface. Chemically-vapor-deposited W is very conformal
and uniformly coats these particles, effectively enlarging
them. A significant amount of over-etching must be 3 4 5 6
carried out to remove the W from these particulates during Number of wiring levels required
the etchback process. Any residual W or remaining
particulates can cause shorting at subsequent interconnect
levels. Over-etching also causes the studs to become
Calculated CPU cycle time as a function of the number of wiring
recessed, building in steep topography that can cause
levels for several combinations of conductors and insulators. From
reliability problems for traversing interconnect levels. In [27], reproduced with permission.
contrast, W removal by CMP is more desirable because
all particulates from prior-level processes are thereby
mechanically abraded from the insulator surface. Polishing
times can be extended until all residual tungsten and liner
materials are removed without recessing the stud. of the effective resistivity, as a function of line width, of
damascene copper wires having a 20-nm-thick Ta liner and
Ti/Al(Cu)/Ti wires patterned by RIE and having 20-nm-
Future BEOL technologies
thick Ti layers. The indicated aspect ratios (A/R) denote
Inevitably, devices will continue to diminish in size, and
thickness-to-width ratios. The apparent discrepancy
chip sizes will increase to provide ever greater function
between the measured and calculated effective resistivity
and cost benefits. If scaling is accomplished according to
values of the Ti/Al(Cu)/Ti wires is due to compound
"ideal" rules [26], the supply voltage decreases by a factor
5 at a constant gate field, and the width of the metal lines formation during heat treatments, increasing their effective
connecting the devices decreases by the same factor. If resistivity. Note the better agreement between the
the aspect ratio of the lines is maintained and insulator observed and calculated effective Cu (including Ta liner)
thickness is scaled as S, the capacitance per unit length resistivities. For a Ti/Al(l% Cu)/Ti wire having 20-nm-
does not change, but the resistance increases as 5^ and the thick Ti layers, the calculated effective resistivity at the
current density increases as S. The cell area decreases as indicated ^/7? levels rises from 3.3 (iTl-cm at l-/im
S~^, as does the power dissipation. Thus, the power linewidths to about 5 /iXl-cm at 0.1-fim linewidths. To
dissipation per unit area is independent of scaling. avoid this, lower-resistivity metals such as copper must
be utilized. Although silver has a lower resistivity than
Most high-performance systems are likely to be designed
for general logic applications for which parallelism cannot copper, copper-based conductors appear to be optimal,
be invoked to reduce the requirements of processor speed. providing low resistivity and low cost with enhanced
These include ASICS and microprocessors which may reliability. Silver is generally considered to be less useful
be connected in various arrangements. In such small, for wiring because of its susceptibility to corrosion in the
higher-power systems, in which neither device voltages presence of weak oxidizing agents such as sulphur. The
nor clock frequencies are reduced, the interconnection reduction in resistivity is not significant enough to warrant
issues become even more critical. In such systems, the its use. Cu-based structures should not only improve
interconnections must accommodate increased current performance, but are also expected to limit the rising costs
density, decreased wire width, larger chip size, increased associated with increasing the number of wiring levels in
tolerance to noise, and minimization of power variations each generation. Figure 8 shows that the use of lower-
across the chip, requiring reduced resistance and resistance conductors and lower-capacitance insulators
capacitance interconnections to maintain chip should reduce the number of wiring layers required [27].
performance. Table 1 shows that microprocessor chips have been
Scaling requirements are expected to cause wiring increasing in size while providing more functionality.
technology to evolve from Al-based conductors to Improved cost and performance continue to be required,
Cu-based conductors. Figure 7 shows a comparison driving the need for new interconnection structures. For 377

IBM J. RES. DEVELOP. VOL. 39 NO. 4 JULY 1995 J. G. RYAN ET AL.

 accomplished by use of a lower supply voltage and lower
operating frequency. If the supply voltage (currently 5 V)
were to be reduced to 1.1 V, the resulting power should
be reduced by a factor of approximately 250. Note that as
the voltage is reduced by a factor of 5, the device area
decreases by a factor of 25 according to ideal scaling.
The reduction in the operating frequency can be partially
compensated for if parallelism can be used to implement
the required functions—e.g., linear transformations of
multiple data sets, such as are used in discrete cosine
functions, which are at the heart of video codecs and other
video processing functions. For such applications, although
low-resistivity wiring is a key attribute, it is likely that
capacitance of the wiring (unchanged with ideal scaling)
will become a serious issue, especially for long nets which
traverse the chip. Therefore, for such appUcations, there
should be considerable benefit in reducing the dielectric
Scanning electron micrograph cross section of a test structure constant of the BEOL insulators, since this reduces
containing four levels of dual-damascene Cu-based wires integrated the drive current the devices must supply.
into a polymeric dielectric. From [14], reproduced with permission.
Insulator materials and layered structures have changed
radically as new equipment and materials have become
available. Sputtered quartz was used for several
generations, but has been largely replaced by PECVD
Table 1 Comparison of microprocessors from several oxides and nitrides [28]. Combinations of hard insulators
manufacturers. and polyimide have also been used [9, 14]. Figure 9
shows a cross section of a test structure containing dual-
Microprocessor Chip size MHz damascene Cu-based wires integrated into a polymeric
(mm) (MIH) dielectric [14], Use is made of a layered insulator structure
80486 11.9 X 6.9 100 0.8
of polyimide and PECVD silicon nitride. The damascene
Intel!
Intel® Pentium 13.3 X 12.3 100 0.8 pattern is etched in the polyimide, and Ta and Cufilmsare
IBM® PowerPC 601™ 8.6 X 9.5 100 0.5 then deposited. CMP is used to remove the metal, leaving
Digital™ Alpha 12.8 X 12.8 275 0.5 Ta/Cu in the damascene pattern, PECVD silicon nitride is
then deposited. The nitride prevents oxygen contamination
of the Cu during subsequent processing and acts as a stop
Table 2 Potentially useful polymer insulators. during the next polyimide etching step. The sequence is
then repeated as needed to produce the required multilevel
Material Dielectric structure.
constant Future insulator structures will need to exhibit low
-[O-SiMej^- 2.3 dielectric constants (<3.0), be thermally and mechanically
stable, adhere well, and integrate with other BEOL
-[-SlPhjCHjCHjCH^-]- 3.2
processes. Insulators having lower dielectric constants
Siloxane polyimides -3.7 reduce crosstalk for a given conductor separation. Table 2
-[-SiPhMe-1-^ 7.7 contains a list of potentially useful low-dielectric-constant
-[0-SiMej-Ph-SiMe2-0-SiMe^O]XH=CH^ 3.5 insulators which span the range of chemical composition
from organosilicon to organic materials. As such, they
-[-SlMejCHj-]- 2.8
represent a large range of mechanical, physical, and
Poly(trimethyl silylnorborane) 2.3 electrical properties. These insulators are unexplored as
PMDA-ODA/polydimethylsiloxane 2.8 commercially useful microelectronic intermetal dielectrics,
copolymer yet demonstrate some of the lowest dielectric constants
of thermally stable polymers. Possible methods of
incorporating them into wiring structures are described
example, in cases where the density of circuits is to be in Reference [29].
increased markedly (e.g., in future low-power circuit Although the phenyl- and silicon-containing polymers
378 chips), the reduction in power will probably be shown in Table 2 are more thermally stable than their

J. O. RYAN ET AL. IBM J. RBS. DEVELOP. VOL. 39 NO. 4 JULY 1995

aliphatic counterparts, the inclusion of aromatic moieties presented as a general introduction to the areas of
into polymers (in this case phenyl groups) increases wiring, insulators, planarization, and reUability described
their dielectric constants. Poly(trimethyl silylnorborane) more completely in the other papers in this issue. The
contains no phenyl groups; rather, it is an aliphatic development of a planar BEOL technology is perhaps the
material with ethylenic bonds in the backbone with key advance that has led to interconnection improvements
a pendant trimethyl-silyl group. Although most of over the last few generations. The availability of new
these materials exhibit property degradation at wiring and insulator materials signals the advent of a new
elevated temperatures, materials such as poly(methyl- BEOL technology generation in the near future.
silylphenylenevinylsiloxane) are stable to around 300°C.
To integrate insulators having low dielectric constants
into a BEOL structure, they must be mechanically stable Acknowledgments
and must adhere to the other insulators as well as the The authors wish to thank our IBM colleagues, past and
metals used, and must withstand the polishing operations present, for their hard work, dedication, and innovation.
and thermal cycling associated with BEOL processing. Their many contributions over the years have caused the
Also, subsequently deposited films must adhere to them. interconnection technology developed at IBM to be a
Possible candidates include layered dielectrics that provide standard of excellence in the industry. Special thanks
both etching control and a dual dielectric structure for are due to Dale Critchlow and Gary Bronner for the
yield and reliability. The ability to obtain etching information on previous DRAM technologies, and Paul
selectivity during the patterning of organic and Totta for his helpful comments on the manuscript and
organosilicon polymers by using various plasmas, for information on bipolar technologies. We also thank all
example, is very attractive for process integration. If an the authors who allowed us liberal use of their data.
organosilicon polymer with sufficient silicon content is
coated with an organic polymer, the etching-rate ratio Intel and Pentium are registered trademarks of Intel Corporation.
between the organic material and the organosilicon
material in an oxygen plasma can easily approach 20:1 PowerPC 601 is a trademark of International Business
under conditions under which vertical polymer sidewalls Machines Corporation.
are required [29]. Thus, the material used as an etching Digital is a trademark of Digital Equipment Corporation.
stop can be relatively thin, permitting stresses to be
transferred through it.
Much of the current emphasis on process cost reduction References
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J a m e s G. Ryan IBM Microelectronics Division, East Jurij R. ParaSZCZak IBM Research Division, Thomas J.
Fishkillfacility, Route 52, HopewellJunction, New York 12533 Watson Research Center, P. O. Box 218, Yorktown
(JRYAN at FSHVMl). Dr. Ryan is a senior engineer and Heights, New York 10598 (PARRY at YKTVMV,
project manager of BEOL Engineering at the IBM Advanced [email protected]). Dr. Paraszczak is currently manager
Semiconductor Technology Center. He joined IBM in 1979 at of the Integrated Systems group at the IBM Thomas J. Watson
East Fishkill, New York, where he worked in plasma etching Research Center. Previously, he was manager of the PowerPC
process development. In 1981, he transferred to the Essex 630™ design group. Additionally, since joining IBM in 1979,
Junction facility, where he worked in the the areas of physical he has managed groups in silicon fabrication technology and
vapor deposition and multilevel wiring development. In 1992, packaging technology, and has worked in the fields of
he moved to East Fishkill to work as manager of Thin Film lithography and plasma processing. Dr. Paraszczak's work
and CMP development for the IBM-Siemens-Toshiba has included electron beam lithography, semiconductor
256Mb DRAM program. Currently, his work focuses on etching, and the design and use of microwave plasmas in
interconnection technology and equipment development. He semiconductor processing, with particular application to
received a B.S. in chemistry in 1977, an M.S. in chemistry in multilayer resist systems. He received his Ph.D. from the
1978, an M.S. in biomedical engineering in 1980, and a Ph.D. University of Sheffield, UK, and is a member of the IEEE.
in chemistry in 1988, all from the Rensselaer Polytechnic
Institute, Troy, New York. Dr. Ryan is the author of 18 U.S. PowerPC 630 is a trademark of International Business Machines Corporation.
patents and about 50 papers and technical disclosures. He is a
member of the American Chemical Society, the American
Vacuum Society, and the Electrochemical Society.

Robert M. Geff ken IBM Microelectronics Division,

Burlington facility, Essex Junction, Vermont 05452
(RGEFFKEN at BTWMOFS; [email protected]}.
Dr. Gefiken is a senior technical staff member working in
multilevel metal interconnect development for advanced
CMOS logic circuit chips. He joined IBM in 1968 at the
development laboratory in Essex Junction, Vermont. During
his career at IBM, he has worked in and managed groups in
the areas of metal and insulator deposition and multilevel
metal process integration. Dr. Geflken received a B.S. degree
and an M.S. degree from New York University, New York, in
1963 and 1966, respectively. He received a Ph.D. in metallurgy
and materials sciences in 1969 from the same university.
Dr. Geffken is currently the IBM representative on the
SEMATECH Multilevel Metal Technical Advisory Board;
he is also a member of the Interconnect Committee for
the Semiconductor National Roadmap.

Neil R. Poulin IBM Microelectronics Division, Burlington

facility, Essex Junction, Vermont 05452 (NPOULIN at
BTWMOFS). Mr. Poulin is a senior engineer and project
manager responsible for interconnect manufacturing
engineering for 0.5-Aim CMOS chips. He joined IBM in 1974
after receiving a B.A. degree in mechanical engineering from
Worcester Polytechnic Institute. He subsequently earned an
M.S. degree in physics from the University of Vermont in
1977. While at IBM, Mr. Poulin has worked extensively in
metal interconnect technology for n-MOS and CMOS chips.
He managed the group that implemented the IBM 4Mb DRAM
planar BEOL process in manufacturing, which included the
first chip manufacturing use of CVD tungsten and CMP. In
1989, Mr. Poulin formed the team that implemented BEOL
technology at the newly constructed IBM Advanced
Semiconductor Technology Center in Hopewell Junction, New
York, the fabricator which has piloted the IBM-Siemens 64Mb
DRAM chip development effort. In this position, he supervised
two SEMATECH beta site programs on new BEOL process
equipment.

381

IBM J. RES. DEVELOP. VOL. 39 NO. 4 JULY 1995 J. G. RYAN ET AL.