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VFTF09 An108

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0% found this document useful (0 votes)
182 views53 pages

VFTF09 An108

Freescale(tm) and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.

Uploaded by

Deepak Kurup
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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You are on page 1/ 53

July, 2009

DDR Basics, Register Configurations & Pitfalls


Mazyar Razzaz,
Applications Engineer
TM

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Agenda
Basic

DDR SDRAM

Memory Organization & Operation Read and write timing


Power

QUICC DDR Controllers QUICC DDR Controllers QUICC DDR Controllers

Features & Capabilities

Power

Initialization & Register Configurations

Power

Pitfalls / Debug Tips

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TM

Basic DDR SDRAM Memory Organization & Operation

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TM

Single Transistor Memory Cell

Column (bit) line Row (word) line S

G D precharged to Vcc/2 Cbit Vcc/2 Ccol

1 => Vcc 0 => Gnd

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TM

Single Transistor Memory Cell

Column (bit) line Row (word) line S

G D precharged to Vcc/2 Cbit Ccol

1 => Vcc 0 => Gnd

Storage Capacitor

Vcc/2

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TM

Single Transistor Memory Cell


Access Transistor

Column (bit) line

Row (word) line S

G D precharged to Vcc/2 Cbit Ccol

1 => Vcc 0 => Gnd

Storage Capacitor

Vcc/2

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TM

Single Transistor Memory Cell


Access Transistor

Column (bit) line

Row (word) line S

G D precharged to Vcc/2 Cbit Ccol


Parasitic Line Capacitance

1 => Vcc 0 => Gnd

Storage Capacitor

Vcc/2

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TM

Memory Arrays

B0 W0

B1

B2

B3

B4

B5

B6

B7

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ROW ADDRESS DECODER

W1

W2

SENSE AMPS & WRITE DRIVERS COLUMN ADDRESS DECODER

TM

Memory Arrays
B0 ROW ADDRESS DECODER W0 B1 B2 B3 B4 B5 B6 B7

W1

W2

SENSE AMPS & WRITE DRIVERS COLUMN ADDRESS DECODER

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TM

Memory Arrays
B0 ROW ADDRESS DECODER W0 B1 B2 B3 B4 B5 B6 B7

W1

W2

SENSE AMPS & WRITE DRIVERS COLUMN ADDRESS DECODER

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TM

10

Internal Memory Banks


Multiple Multiple

arrays organized into banks banks per memory device

DDR1 4 banks, 2 bank address (BA) bits DDR2 & DDR3 4 or 8 banks, 2 or 3 bank address (BA) bits Can have one active row in each bank at any given time Can be opening or precharging a row in one bank while accessing another bank

Concurrency May

be referred to as internal, logical or sub- banks


Bank 0 Bank 1 Bank 2 Bank 3

Row 0 Row 1 Row 2 Row 3 Row Row Buffers

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TM

11

Memory Access
Bank 0 Bank 1 Bank 2 Bank 3

requested row is ACTIVATED and made accessible through the banks row buffer.

Row Row Row Row Row

0 1 2 3

Row Buffers

READs

and/or WRITE are issued to the active row.

Row Row Row Row Row

0 1 2 3

Row Buffers

The

row is PRECHARGED and is no longer accessible through the banks row buffer.

Row Row Row Row Row

0 1 2 3

Row Buffers

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TM

12

Example DDR2 SDRAM


Infineon

HYB18T256800AF or Micron MT47H32M8

32M

x 8 (8M x 8 x 4 banks) 256 Mb total


13-bit row address 8K rows 10-bit column address 1K bits/row (8K total when you take into account the x8 width) 2-bit bank address

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TM

13

Example DDR2 DIMM


Infineon

HYS72T3200HU or Micron MT9HTF3272A

/CSn

ODTn

32M x 8
A[12:0] BA[1:0] /RAS /CAS /WE DQ[7:0] DQS /DQS DM MDQ[16:23], MDQS2, MDM2 MDQ[24:31 MDQS3, MDM3 CKE CK /CK MDQ[32:39], MDQS4, MDM4 MDQ[40:47], MDQS5, MDM5 MDQ[48:55], MDQS6, MDM6 MDQ[56:31], MDQS7, MDM7 MDQ[0:7], MDQS0, MDM0 MDQ[8:15], MDQS1, MDM1

each 32M x 8 memory devices 32M x 72 overall 256 MB total Single rank 9 byte lanes

ODT /CS

32M x 8
A[12:0] BA[1:0] /RAS /CAS /WE CKE CK /CK DQ[7:0] DQS /DQS DM ECC[0:7], MDQS8, MDM8

ODT /CS

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TM

14

DDR1/DDR2/DDR3 Basic Command Summary

Command NOP NOP ACTIVE READ WRITE PRECHARGE PRECHARGE ALL REFRESH LOAD MODE REGISTER

/CS H L L L L L L L L

/RAS X H L H H L L L L

/CAS X H H L L H H L L

/WE X H H H L L L H L

ADDR
X X BA, Row BA, Col BA, Col BA A[10] X Bank, OpCode

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TM

15

DDR2-533 Read Timing Example


Mem Clk
Tck = 3.75 ns

ACTIVE
Trcd (ACTTORW ) = 4 clk

READ
Tccd = 2 clk

READ

PRECHARGE
Trp (PRETOACT) = 4 clk

Trtp (RD_TO_PRE) = 2 clk

/CS /RAS /CAS /WE Address


BA, ROW BA, COL BA, COL BA

CASLAT = 4 clk

DQS DQ
D0 D1 D2 D3 D0 D1 D2 D3

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TM

16

DDR2-533 Write Timing Example


Mem Clk
Tck = 3.75 ns

ACTIVE
Trcd (ACTTORW ) = 4 clk

WRITE

PRECHARGE

/CS /RAS /CAS /WE Address


BA, ROW BA, COL BA

WR_LAT = CASL + AL -1 = 3 clk

Twr (WRREC) = 4 clk

DQS DQ DM
D0 D1 D2 D3

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TM

17

DDR1/DDR2/DDR3 Comparison
Feature
Package Voltages Densities Internal Banks Prefetch (min WRITE burst) Data Rate CAS / READ Latency WRITE Latency I/O Signaling

DDR1
TSOP 2.5V Core, 2.5V I/O 64Mb-1Gb 4 2 266-400 Mbps 2, 2.5, 3 Clk 1 SSTL_2

DDR2
BGA only 1.8V Core, 1.8V I/O 256Mb-4Gb 4 or 8 4 400800 Mbps 3, 4, 5 + AL Clk READ Latency - 1 SSTL_18 On-die for data group. VTT termination for address, command, and control Single or Differential

DDR3
BGA only 1.5V Core, 1.5V I/O 256Mb-8Gb 8 8 8001600 Mbps 5, 6, 7+ AL Clk CAS write Latancy SSTL_15 On-die termination for data, address, command, and control Differential

Termination

Parallel termination to VTT for all signals

Data Strobes

Single Ended

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TM

18

PowerQUICC DDR Controllers Features & Capabilities

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TM

19

DDR1/DDR2/DDR3 Controller Features & Capabilities


Supports

most JEDEC standard x8, x16, x32 DDR1 & 2 & 3 devices Memory device densities from 64Mb through 4Gb Data rates up to: 333 Mb/s for DDR1, 800 Mb/s for DDR2 and DDR3 Devices with 12-16 row address bits, 8-11 column address bits, 2-3 logical bank address bits Data mask signals for sub-doubleword writes Up to four physical banks (chip selects) Physical bank sizes up to 4GB, total memory up to 16GB per controller Physical bank interleaving between 2 or 4 chip selects Memory controller interleaving when more than 2 controllers are available Unbuffered or registered DIMMs

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TM

20

DDR1/DDR2/DDR3 Controller Features & Capabilities (cont.)


Up

to 32 open pages globally or by chip select

Open row table Amount of time rows stay open is programmable


Auto-precharge, Self-refresh Up

to 8 posted refreshes Automatic or software controlled memory device initialization ECC: 1-bit error correction, 2-bit error detection, detection of all errors within a nibble ECC error injection Read-modify-write for sub-doubleword writes when using ECC Automatic data initialization for ECC Dynamic power management

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TM

21

DDR2/DDR3 Controller additional Features & Capabilities


Partial

array self refresh Address & command parity for Registered DIMM Independent driver impedance setting for data, address/command, and clock Mirrored DIMM supported Automatic CPO (operational) Write-leveling for DDR3 Automatic ZQ calibration for DDR3 Fixed or On-the-fly Burst chop mode for DDR3 Asynchronous RESET for DDR3

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TM

22

Fly By Routing Topology


Introduction

of Fly-by architecture

Address, command, control & clocks Improved signal integrityenabling higher speeds On module termination
Matched tree routing of clk command and ctrl

DDR2 DIMM Controller


Fly by routing of clk, command and ctrl VTT

DDR3 DIMM

Controller

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23

Fly By Routing Improved SI

DDR2 Matched tree routing

DDR3 Fly by routing

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TM

24

What is write leveling


During a write cycle, the skew between the clock and strobes are increased with the fly-by topology. The write leveling will delay the strobe (and the corresponding data lane) for each byte lane to reduce/compensate for this delay.

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TM

25

Read Adjustment
Automatic CAS to preamble calibration Data strobe to data skew adjustment
Address, Command & Clock Bus

Freescale Chip

Data Lanes

Instead of JEDECs MPR method, Freescale controllers use a proprietary method of read adjust method. Auto CPO will provide the expected arrival time of preamble for each strobe line of each byte lane during the read cycle to adjust for the delays cased by the fly-by topology.

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TM

26

Write Adjustment
Write leveling used to add delay to each strobe/data line.

Freescale Chip

Address, Command & Clock Bus

Data Lanes

Write leveling sequence during the initialization process will determine the appropriate delays to each strobe/data byte lane and add this delay for every write cycle.

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TM

27

PowerQUICC DDR Controllers Initialization and Register Configurations

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TM

28

DDR3 Initialization Flow


Power-up
Asserted at least 200us

DRAMs Initialized ZQ Calibration

Mode Register Commands Issued

DDR Reset
Need at least 500us from reset deassertion to the controller being enabled. Timed loop may be needed.

DDR3s Conduct Precharge Chip selects enabled and DDR clocks begin

ZQCL Issued (512 clocks) Also DLL lock time is occurring

DDR CTRL INIT Stable CLKS Controller Started

Write Leveling Read Adjust Init Complete

Automatically handled By the controller

CKE = HIGH

Automatic CAS-to-Preamble (aka Read Leveling). Plus Data-to-Strobe adjustment

MEM_EN =1

Ready for User accesses

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TM

29

DDR2 Initialization Flow


Power-up Precharge All
Chip selects enabled and DDR clocks begin Issued by controller

DDR CTRL INIT Stable CLKS

DRAMs Initialized Read DQS Adjust Wait tDLL Adjust Read Init DQS Calibration Complete Adjust

Mode Registers Programmed Issued by controller

CKE = HIGH

tDLL = 512 clocks

200 us

Ready for User accesses

Controller Started

MEM_EN =1

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TM

30

Register configuration
Two

general type of registers to be configured in the memory controller First register type are set to the DRAM related parameter values, that are provided via SPD or DRAM datasheet Second register type are the Non-SPD values that are set based on customers application. For example:

On-die-termination (ODT) settings for DRAM and controller Driver impedance setting for DRAM and controller Clock adjust, write data delay, Cast to Preamble Override (CPO) 2T or 3T timing Burst type selection (fixed or on-fly burst chop mode) Write-leveling start value (WRLVL_START)

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TM

31

What Can We Adjust to Optimize the Timing?


1)

CLK_ADJUST 2) WR_DATA_DELAY 3) CPO 4) 2T_EN, 3T_EN 5) WRLVL_EN 6) Burst chop mode

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TM

32

CLK_ADJUST & WR_DATA_DELAY


Internal Clock

MemClk (CLK_ADJUST = 0)
CLK_ADJUST = 1/2

MemClk (CLK_ADJUST = 1/2)

Cmd/Addr Bus

WRITE

WR_LAT = (CASL + AL -1 ) = 3

DQS (WR_DATA_DELAY = 0) DQ (WR_DATA_DELAY = 0)


Tdqss = 1/4 cycle
WR_DATA_DELAY = 1/2

DQS (WR_DATA_DELAY = 1/2) DQ (WR_DATA_DELAY = 1/2)

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TM

33

Pitfalls / Debug Tips - Clock Adjust


Addr/Cmd

are always launched from the same location, memory clock is shifted with DDR_SDRAM_CLK_CNTL[CLK_ADJUST]
Used to meet setup/hold for Addr/Cmd

Use

eye.

a scope to verify that clock is centered inside of the Addr/Cmd valid

Look at heavily loaded signal (/RAS, /CAS, /WE, Addr, BA) Look at lightly loaded signal (/CS, ODT, CKE)

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34

Eye Diagrams

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35

Eye Diagrams

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36

Eye Diagrams

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37

Eye Diagrams

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38

Eye Diagrams

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TM

39

Pitfalls / Debug Tips Write Data Delay


Controlled Used

via TIMING_CFG_2[WR_DATA_DELAY]

In addition to compensating for CLK_ADJUST setting

to meet tDQSS timing requirements using a scope

Verify

Must be measured after DDR_SDRAM_CLK_CNTL[CLK_ADJUST] has been optimized

Erroneous

values may cause failures on writes to DRAM

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TM

40

Pitfalls / Debug Tips - CAS to Preamble


Set Use

via TIMING_CFG_2[CPO] application note AN2583 section 4.2 to calculate

Must

be calculated after DDR_SDRAM_CLK_CNTL[CLK_ADJUST] has been optimized Use the center value if more than one valid CPO available.

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41

2T/3T Timing
Puts

Addr/Cmd signals on the bus for 2 or 3 clock cycles instead of 1 Does not affect Control signals
When

to use?

Two dual-rank unbuffered DIMMs 36 loads on Addr/Cmd lines


Typically

not required for:

One dual-rank unbuffered DIMM 18 loads on Addr/Cmd lines


When

not to use?

Registered DIMMs

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TM

42

PowerQUICC DDR Controllers Pitfalls / Debug Tips

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TM

43

Pitfalls / Debug Tips - DDR Type POR Configuration

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44

Pitfalls / Debug Tips - ECC and DDR Error Registers


ECC

should be enabled if possible

DDR_SDRAM_CFG[ECC_EN] enables ECC DDR_SDRAM_CFG_2[D_INIT] initializes data and ECC in DRAM If ECC cannot be enabled, it may be more difficult to detect DDR generated errors
ERR_DETECT

register should be checked for DDR errors

ACE Automatic calibration error MBE Multi-bit ECC error SBE Single-bit ECC error MSE Memory select error

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45

Pitfalls / Debug Tips - CAS Latency / Write Latency / Additive Latency


Program

write latency based on DRAM type

DDR1 -> Write latency = 1 DRAM cycle DDR2 -> Write latency = (Read latency 1) DRAM cycles DDR3 -> Write latency = CWL
Programming

CAS latency too high can degrade performance

Check DRAM datasheet based on frequency used and specific DRAM device

When

ODT is used, other rules must be followed to allow ODT to assert early enough
DDR2: Write latency + additive latency >= 3 cycles DDR3: TIMING_CFG_5 [WODT_ON], [WODT_OFF] = WL-1 cycles for fixed or fly-by burst chop

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46

Pitfalls / Debug Tips - DDR Mode Registers


Values

programmed into DDR mode registers must match DDR controller configuration registers
CAS latency Burst length Write recovery
Not a straight decode in Mode Register

Active powerdown exit time Additive latency Differential DQS enable

DLL

reset and OCD calibration fields are controlled automatically by the DDR controller

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47

*Pitfalls / Debug Tips - Programming twtr, trrd, and trtp


Use

caution when calculating:

TIMING_CFG_1[WRTORD] (twtr) TIMING_CFG_1[ACTTOACT] (trrd) TIMING_CFG_2[RD_TO_PRE] (trtp)

DDR2: Minimum value for each parameter is 2 DRAM clocks DDR3: Minimum value for each parameter is 4 DRAM clocks

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48

Pitfalls / Debug Tips - 200 us Delay


200

s for DDR2 and 512 us for DDR3 must pass between stable clocks and CKE assertion are stable after DDR_SDRAM_CLK_CNTL[CLK_ADJUST] is programmed and any chip select has been enabled via CSn_CONFIG[CS_n_EN] is asserted after DDR_SDRAM_CFG[MEM_EN] is set must provide delay between these 2 steps

Clocks

CKE

Software

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49

References

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TM

50

Useful References
Books: DRAM Circuit Design: A Tutorial, Brent Keeth and R. Jacob Baker, IEEE Press, 2001 Freescale AppNotes: AN2582 Hardware and Layout Design Considerations for DDR Memory Interfaces AN2910 Hardware and Layout Design Considerations for DDR2 Memory Interfaces AN2583 Programming the PowerQUICC III / PowerQUICC II Pro DDR SDRAM Controller AN3369 PowerQUICC DDR2 SDRAM Controller Register Setting Considerations Micron AppNotes: TN-46-05 General DDR SDRAM Functionality TN-47-02 DDR2 Offers New Features and Functionality TN-41-02 DDR3 ZQ calibration
JEDEC

Specs:

JESD79E Double Data Rate (DDR) SDRAM Specification JESD79-2B DDR2 SDRAM Specification JESD79-3A DDR3 SDRAM Specification

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51

Q&A
Thank

you for attending this presentation. Well now take a few moments for the audiences questions and then well begin the question and answer session.

Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009.

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