VFTF09 An108
VFTF09 An108
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Agenda
Basic
DDR SDRAM
Power
Power
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Storage Capacitor
Vcc/2
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Storage Capacitor
Vcc/2
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Storage Capacitor
Vcc/2
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Memory Arrays
B0 W0
B1
B2
B3
B4
B5
B6
B7
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W1
W2
TM
Memory Arrays
B0 ROW ADDRESS DECODER W0 B1 B2 B3 B4 B5 B6 B7
W1
W2
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Memory Arrays
B0 ROW ADDRESS DECODER W0 B1 B2 B3 B4 B5 B6 B7
W1
W2
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DDR1 4 banks, 2 bank address (BA) bits DDR2 & DDR3 4 or 8 banks, 2 or 3 bank address (BA) bits Can have one active row in each bank at any given time Can be opening or precharging a row in one bank while accessing another bank
Concurrency May
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Memory Access
Bank 0 Bank 1 Bank 2 Bank 3
requested row is ACTIVATED and made accessible through the banks row buffer.
0 1 2 3
Row Buffers
READs
0 1 2 3
Row Buffers
The
row is PRECHARGED and is no longer accessible through the banks row buffer.
0 1 2 3
Row Buffers
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32M
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/CSn
ODTn
32M x 8
A[12:0] BA[1:0] /RAS /CAS /WE DQ[7:0] DQS /DQS DM MDQ[16:23], MDQS2, MDM2 MDQ[24:31 MDQS3, MDM3 CKE CK /CK MDQ[32:39], MDQS4, MDM4 MDQ[40:47], MDQS5, MDM5 MDQ[48:55], MDQS6, MDM6 MDQ[56:31], MDQS7, MDM7 MDQ[0:7], MDQS0, MDM0 MDQ[8:15], MDQS1, MDM1
each 32M x 8 memory devices 32M x 72 overall 256 MB total Single rank 9 byte lanes
ODT /CS
32M x 8
A[12:0] BA[1:0] /RAS /CAS /WE CKE CK /CK DQ[7:0] DQS /DQS DM ECC[0:7], MDQS8, MDM8
ODT /CS
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Command NOP NOP ACTIVE READ WRITE PRECHARGE PRECHARGE ALL REFRESH LOAD MODE REGISTER
/CS H L L L L L L L L
/RAS X H L H H L L L L
/CAS X H H L L H H L L
/WE X H H H L L L H L
ADDR
X X BA, Row BA, Col BA, Col BA A[10] X Bank, OpCode
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ACTIVE
Trcd (ACTTORW ) = 4 clk
READ
Tccd = 2 clk
READ
PRECHARGE
Trp (PRETOACT) = 4 clk
CASLAT = 4 clk
DQS DQ
D0 D1 D2 D3 D0 D1 D2 D3
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ACTIVE
Trcd (ACTTORW ) = 4 clk
WRITE
PRECHARGE
DQS DQ DM
D0 D1 D2 D3
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DDR1/DDR2/DDR3 Comparison
Feature
Package Voltages Densities Internal Banks Prefetch (min WRITE burst) Data Rate CAS / READ Latency WRITE Latency I/O Signaling
DDR1
TSOP 2.5V Core, 2.5V I/O 64Mb-1Gb 4 2 266-400 Mbps 2, 2.5, 3 Clk 1 SSTL_2
DDR2
BGA only 1.8V Core, 1.8V I/O 256Mb-4Gb 4 or 8 4 400800 Mbps 3, 4, 5 + AL Clk READ Latency - 1 SSTL_18 On-die for data group. VTT termination for address, command, and control Single or Differential
DDR3
BGA only 1.5V Core, 1.5V I/O 256Mb-8Gb 8 8 8001600 Mbps 5, 6, 7+ AL Clk CAS write Latancy SSTL_15 On-die termination for data, address, command, and control Differential
Termination
Data Strobes
Single Ended
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most JEDEC standard x8, x16, x32 DDR1 & 2 & 3 devices Memory device densities from 64Mb through 4Gb Data rates up to: 333 Mb/s for DDR1, 800 Mb/s for DDR2 and DDR3 Devices with 12-16 row address bits, 8-11 column address bits, 2-3 logical bank address bits Data mask signals for sub-doubleword writes Up to four physical banks (chip selects) Physical bank sizes up to 4GB, total memory up to 16GB per controller Physical bank interleaving between 2 or 4 chip selects Memory controller interleaving when more than 2 controllers are available Unbuffered or registered DIMMs
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to 8 posted refreshes Automatic or software controlled memory device initialization ECC: 1-bit error correction, 2-bit error detection, detection of all errors within a nibble ECC error injection Read-modify-write for sub-doubleword writes when using ECC Automatic data initialization for ECC Dynamic power management
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array self refresh Address & command parity for Registered DIMM Independent driver impedance setting for data, address/command, and clock Mirrored DIMM supported Automatic CPO (operational) Write-leveling for DDR3 Automatic ZQ calibration for DDR3 Fixed or On-the-fly Burst chop mode for DDR3 Asynchronous RESET for DDR3
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of Fly-by architecture
Address, command, control & clocks Improved signal integrityenabling higher speeds On module termination
Matched tree routing of clk command and ctrl
DDR3 DIMM
Controller
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Read Adjustment
Automatic CAS to preamble calibration Data strobe to data skew adjustment
Address, Command & Clock Bus
Freescale Chip
Data Lanes
Instead of JEDECs MPR method, Freescale controllers use a proprietary method of read adjust method. Auto CPO will provide the expected arrival time of preamble for each strobe line of each byte lane during the read cycle to adjust for the delays cased by the fly-by topology.
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Write Adjustment
Write leveling used to add delay to each strobe/data line.
Freescale Chip
Data Lanes
Write leveling sequence during the initialization process will determine the appropriate delays to each strobe/data byte lane and add this delay for every write cycle.
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DDR Reset
Need at least 500us from reset deassertion to the controller being enabled. Timed loop may be needed.
DDR3s Conduct Precharge Chip selects enabled and DDR clocks begin
CKE = HIGH
MEM_EN =1
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DRAMs Initialized Read DQS Adjust Wait tDLL Adjust Read Init DQS Calibration Complete Adjust
CKE = HIGH
200 us
Controller Started
MEM_EN =1
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Register configuration
Two
general type of registers to be configured in the memory controller First register type are set to the DRAM related parameter values, that are provided via SPD or DRAM datasheet Second register type are the Non-SPD values that are set based on customers application. For example:
On-die-termination (ODT) settings for DRAM and controller Driver impedance setting for DRAM and controller Clock adjust, write data delay, Cast to Preamble Override (CPO) 2T or 3T timing Burst type selection (fixed or on-fly burst chop mode) Write-leveling start value (WRLVL_START)
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MemClk (CLK_ADJUST = 0)
CLK_ADJUST = 1/2
Cmd/Addr Bus
WRITE
WR_LAT = (CASL + AL -1 ) = 3
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are always launched from the same location, memory clock is shifted with DDR_SDRAM_CLK_CNTL[CLK_ADJUST]
Used to meet setup/hold for Addr/Cmd
Use
eye.
Look at heavily loaded signal (/RAS, /CAS, /WE, Addr, BA) Look at lightly loaded signal (/CS, ODT, CKE)
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Eye Diagrams
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Eye Diagrams
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Eye Diagrams
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Eye Diagrams
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Eye Diagrams
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via TIMING_CFG_2[WR_DATA_DELAY]
Verify
Erroneous
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Must
be calculated after DDR_SDRAM_CLK_CNTL[CLK_ADJUST] has been optimized Use the center value if more than one valid CPO available.
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2T/3T Timing
Puts
Addr/Cmd signals on the bus for 2 or 3 clock cycles instead of 1 Does not affect Control signals
When
to use?
not to use?
Registered DIMMs
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DDR_SDRAM_CFG[ECC_EN] enables ECC DDR_SDRAM_CFG_2[D_INIT] initializes data and ECC in DRAM If ECC cannot be enabled, it may be more difficult to detect DDR generated errors
ERR_DETECT
ACE Automatic calibration error MBE Multi-bit ECC error SBE Single-bit ECC error MSE Memory select error
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DDR1 -> Write latency = 1 DRAM cycle DDR2 -> Write latency = (Read latency 1) DRAM cycles DDR3 -> Write latency = CWL
Programming
Check DRAM datasheet based on frequency used and specific DRAM device
When
ODT is used, other rules must be followed to allow ODT to assert early enough
DDR2: Write latency + additive latency >= 3 cycles DDR3: TIMING_CFG_5 [WODT_ON], [WODT_OFF] = WL-1 cycles for fixed or fly-by burst chop
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programmed into DDR mode registers must match DDR controller configuration registers
CAS latency Burst length Write recovery
Not a straight decode in Mode Register
DLL
reset and OCD calibration fields are controlled automatically by the DDR controller
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DDR2: Minimum value for each parameter is 2 DRAM clocks DDR3: Minimum value for each parameter is 4 DRAM clocks
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s for DDR2 and 512 us for DDR3 must pass between stable clocks and CKE assertion are stable after DDR_SDRAM_CLK_CNTL[CLK_ADJUST] is programmed and any chip select has been enabled via CSn_CONFIG[CS_n_EN] is asserted after DDR_SDRAM_CFG[MEM_EN] is set must provide delay between these 2 steps
Clocks
CKE
Software
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References
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Useful References
Books: DRAM Circuit Design: A Tutorial, Brent Keeth and R. Jacob Baker, IEEE Press, 2001 Freescale AppNotes: AN2582 Hardware and Layout Design Considerations for DDR Memory Interfaces AN2910 Hardware and Layout Design Considerations for DDR2 Memory Interfaces AN2583 Programming the PowerQUICC III / PowerQUICC II Pro DDR SDRAM Controller AN3369 PowerQUICC DDR2 SDRAM Controller Register Setting Considerations Micron AppNotes: TN-46-05 General DDR SDRAM Functionality TN-47-02 DDR2 Offers New Features and Functionality TN-41-02 DDR3 ZQ calibration
JEDEC
Specs:
JESD79E Double Data Rate (DDR) SDRAM Specification JESD79-2B DDR2 SDRAM Specification JESD79-3A DDR3 SDRAM Specification
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Q&A
Thank
you for attending this presentation. Well now take a few moments for the audiences questions and then well begin the question and answer session.
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