Chapter 5

Synchronous Sequential Logic

Sequential Circuits Definitions
Latches
Flip-flops
Analysis of Clocked Circuits
State Reduction and Assignment
Design Procedure
Sequential Circuits

• A sequential circuit consists of combinational circuits

to which storage elements are connected to form a
feedback path.
– Storage elements store binary information.
– Outputs of a sequential circuit are a function of the
inputs and the internal state of the storage elements.
• State refers to the currently known condition of the
circuit including what data is stored in the storage
elements.
• A sequential circuit is specified by a time sequence of
inputs, outputs, and internal states.
Sequential Circuit- Block Diagram
Sequential Circuit Types
• There are two types of sequential circuits Synchronous
and Asynchronous :
– A synchronous sequential circuit is a system whose
behavior can be defined from the knowledge of its signals
at discrete instants of time
» All storage elements in synchronous circuits are
affected at discrete instants of time
– asynchronous sequential circuit depends on the input
signals at any instant of time and the order in which the
inputs change
» Storage elements in asynchronous circuits are usually time-
delay devices
» The storage capability of time-delay devices is due to the time
it takes for the signal to propagate through the device
» It is also regarded as combinational circuit with feedback
 Synchronous Sequential Circuit
• Synchronization in synchronous sequential circuits is
achieved by timing device called a clock generator
• A clock generator generates a periodic train of clock pulses
• The clock pulses are distributed throughout the system in
such a way that storage elements are affected only with the
arrival of each pulse
• Clock pulses are employed with other circuitry that
indicates the changes to the storage elements.
• Synchronous sequential circuits that use clock pulses in
the inputs of storage elements are called clocked
sequential circuits.
• These are most commonly used having no instability
problems
• The memory elements used in these circuits are flip-flops
Synchronous Sequential Circuit
Flip Flop

• The storage element used in clocked sequential

circuits are called flip flops.
– A flip flop is a binary storage device capable of storing one bit
of information.
– It has two outputs, one for the normal value and one for the
complement value
– Multiple flip flops can be used to store multiple bits.
– Flip flops receive their inputs from a combinational circuit and
a clock signal.
– A Flip flop maintains a binary state indefinitely until directed
by an input signal to switch states. The state of a flip flop can
change only during a clock pulse.
 Latches

• A flip flop circuit can maintain a binary state

indefinitely until directed by an input signal to switch
states.
– Flip flops are categorized by the number of inputs they
possess and the manner in which the inputs affect the binary
state.
• Latches are the most basic flip flop and they operate
with signal levels.
• Latches are the building blocks for all flip flops.
SR Latch

• The SR latch is a circuit with two cross-coupled NOR

gates or two cross-coupled NAND gates.
– There are two inputs:
» S is for set
» R is for reset Q

– There are two outputs Q and Q’

Q’
SR Latch Logic (NOR Gates)

• The SR latch with NOR Gates has two useful states

– When Q = 1 and Q’ = 0 the latch is said to be in a set state.
– When Q = 0 and Q’ = 1 the latch is said to be in a reset state.
– Q and Q’ are normally complement of each other
– When both inputs are equal to 1 at the same time, an undefined state
with both outputs equal to 0 occurs
 SR Latch (NOR) Logic
• Normally the two inputs to the SR latch (NOR) are left at 0.
• If the state needs to be changed then the application of a
momentary 1 to the S input causes the latch to go to the set
state.
– The S input must go back to 0 before any other changes to avoid the
occurrence of the undefined state. The circuit remains in set state.
• A momentary 1 to the R input causes the latch to go to the
reset state.
– The R input must go back to 0 before any other changes to avoid
the occurrence of the undefined state. The circuit remains in reset
state.
• If a 1 is applied to both S and R then both outputs go to 0,
the undefined state.
SR Latch Logic (NAND Gates)
• The SR latch with NAND Gates has two useful states
– When Q = 1 and Q’ = 0 the latch is said to be in a set state.
– When Q = 0 and Q’ = 1 the latch is said to be in a reset state.
– Q and Q’ are normally complement of each other. When both
inputs are equal to 0 at the same time, an undefined state with
both outputs equal to 1 occurs
SR Latch (NAND) Logic
• Normally the two inputs to the SR latch (NAND) are
left at 1.
• If the state needs to be changed then the application
of a momentary 0 to the S input causes the latch to go
to the set state.
– The S input must go back to 1 before any other changes to avoid the
occurrence of the undefined state. The circuit remains in set state.
• A momentary 0 to the R input causes the latch to go to
the reset state.
– The R input must go back to 1 before any other changes to avoid the
occurrence of the undefined state. The circuit remains in reset state.
• If a 0 is applied to both S and R then both outputs go
to 1, the undefined state.
NAND vs. NOR Implementations

• The input signals for

the NAND latch
requires the
complement of those
values used for the
NOR latch

• Because the NAND

latch requires a 0
signal it is sometimes
called a S’- R’ latch.
SR Latch Modification
• The basic SR latch can be modified by providing an
additional control input that determines when the state of
the latch can be changed.
– The following example uses the C enable input with 1 allowing
inputs S and R to flow through and 0 disallowing the flow of the
inputs S and R. In other words S and R are allowed to change the
flip-flop only when C = 1 and If C=0, S and R can’t change output
– It consists of basic SR latch and two additional NAND gates
– The control input C acts as an enable input for the other two
inputs
– The output of the NAND gates stay at the logic 1 level as long as
the control input remains at 0. This is quiescent (inactive) state.
– When the control input goes to 1, the information for S or R is
allowed to effect the SR latch (active state)
– The set state is reached with S=1, R=0 and C=1. To change to the
reset state, the inputs must be S=0, R=1 and C=1. In either cases
when C returns to 0, the circuit remains in its current state
SR Latch With Control Input
D Latch
• A ‘D’ latch modifies the SR latch to avoid the
undesirable condition of the indeterminate state by
ensuring that S and R are never equal to 1 at the same
time.
– There are only two inputs:
» D is the data input
» En is the Control input
– The D input goes directly to the S input and its complement
goes to the R input.
– When control input En is left at 0 the state of the latch
remains constant (regardless of value of D).
– If En = 1 and D = 1 the output Q goes to 1, placing the circuit
in the set state.
– If En = 1 and D = 0 the output Q goes to 0, placing the circuit
in the reset state.
D Latch With Enable Input (En)

• D Latch
–When En=1, it latches/stores the data
Notes on D Latches

• The D Latch has the ability to hold data in its internal

storage.
• The data input of the D latch is transferred to the Q
output when the control input is enabled.
– The output follows changes in the data input as long as the
control input is enabled.
– For this reason, the latch is also called the transparent latch.
• When the control input is disabled, the output of the
latch remains in the state it was in just prior to the
control input being disabled.
Graphic Symbols for Latches

__
S R : NAND gate Latch
Graphic Symbols for Latches
Problems With Latches

• The problem with the latch is that it responds to a

change in the level of a clock pulse.
– A positive level response in the control input allows changes
in the output when the D input changes while the clock pulse
stays at logic-1.
• The key to solving the latch problem in flip flops is to
ensure that changes are only allowed to occur during
a signal transition (at the point in value change).
– A positive transition is called a positive-edge response.
– A negative transition is called a negative-edge response.
 Summary
Latches D Q

EN
Determine the Q output for
the D latch, given the inputs Q

shown.
D

EN

Notice that the Enable is not active during these

times, so the output is latched.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights
Reserved
 Flip Flop
• The state of a latch or a flip flop is switched by a
change in the control input.
• The momentary change in the control input, called a
trigger, causes a transition in the flip flop.
– As long as the control input is enabled, the data in and data out
can be changed.
• Typically the output of a flip flop is used as an input of
the combinational circuit which in turn provides input
back to the flip flop (next slide).
– If a latch is used, we run the risk of unpredictable results
because the latch changes output for as long as the control
input is enabled. If the input changes while the clock pulse
(control input) is still in logic 1 level, the output will change as
per the new input
– Therefore, the output of a latch cannot be applied directly or
through combinational logic to the input of the same or another
latch.
• Flip flop circuits are constructed in such a way as to
make them operate properly when they are part of a
sequential circuit that employs a common clock.
Synchronous Clocked Sequential Circuit
Clock Responses
Clock Responses
Modifying Latches

• There are two ways that a latch can be modified to

form a flip-flop.
– One way is to employ two latches in a special configuration that
isolates the output of the flip-flop from being affected while its input
is changing.
– Another way is to produce a flip-flop that triggers only during a
signal transition (from 0 to 1 or from 1 to 0), and is disabled during
the rest of the clock pulse duration.
Edge-Triggered D Flip-Flop
• An edge-triggered D flip flop is constructed with two
D latches and an inverter.
– The first latch is called the master and second the slave.
– The circuit samples the D input and changes its output Q only at the
negative-edge of the controlling clock.
– When the clock is 0, the output of the inverter is 1, the slave latch is
enabled and its output Q is equal to the master output Y.
» The master latch is disabled because the clock is 0.
– When the input pulse changes to the logic 1 level, the data from the
external D input is transferred to the master.
» The slave is disabled as long as the clock remains in the 1 level
because its C input is equal to 0.
» Any change in the input changes the master output at Y, but
cannot affect the slave output.
» When the pulse returns to 0 the master is disabled and the slave
is enabled causing the value of Y to be transferred to output Q.
Master Slave D Flip Flop
Master Slave D Flip Flop

C 0 0 1 0 0 1 1 0 1

D 0 1 1 0 1 1 0 0 1

Y 0 0 1 1 1 1 0 0 1

Q 0 0 0 1 1 1 1 0 0 1
Edge Transition

• The previous implementation uses a negative edge

transition.
– The output only changes during the negative edge of the
clock.
• A positive edge transition implementation can be
constructed by placing an inverter on the CLK input
prior to any other gate or inverter. i.e. between the
CLK terminal and the junction between the other
inverter and input C of the master latch.
• Such flip flop is triggered with a negative pulse, so
that negative edge of the clock affects the master and
the positive edge affects the slave and the output
terminal
Edge-Triggered D Flip Flop Graphic
Symbols
Alternative Positive Edge Flip Flop

• A more efficient construction of an edge-triggered D

flip flop uses three SR latches.
– Two latches respond to the external D (data) and CLK (clock)
inputs.
– The third latch provides the outputs for the flip flop.
– The S and R inputs of the output latch are maintained at logic
1 level when CLK = 0 causing the output to remain in its
present state.
– If D = 0 when CLK = 1, R changes to 0 causing a reset state
and making Q = 0.
– If there is a change in D while CLK = 1, terminal R remains at
0, thus locking out the flip flop (unresponsive to further
changes in the input).
– If D = 1 when CLK = 1, S changes to 0 causing the circuit to go
to the set state making Q = 1.
3 – SR Latch Flip Flop (D-Type Positive
Edge Triggered)
D-Type Positive Edge Triggered Flip Flop
– Summary

• When the input clock makes the positive transition,

the value of D is transferred to Q

• A negative transition from 1 to 0 (or steady CLK state:

logic 1 or logic 0 ) doesn’t affect the output
• This flip flop respond to transition from 0 to 1 only
 3 – SR Latch Flip Flop

1/1/1/0/0/0 0/0/0/1/1/1

1/1/1/1/0/1 x/0/0/0/1/1

0/1/0/0/1/0
1/0/1/1/1/1
x/1/1/1/0/0

0/0/0/1/1/1
1/1/1/0/0/0
Flip Flop Characteristics

• The timing of the response of a flip flop to input data

and clock must be taken into consideration when
using edge-triggered flip flops.
• There is a minimum time, called setup time, for which
the D input must be maintained at a constant value
prior to the occurrence of the clock transition.
• There is a minimum time, called hold time, for which
the D input must not change after the application of
the positive transition of the clock.
• The propagation delay time of the flip flop is defined
as the time interval between the trigger edge and the
stabilization of the output to a new state.
 Flip Flop Characteristic

• Set-up time and hold time are times required before and
after the clock transition that data must be present to be
reliably clocked into the flip-flop.

Setup time ts is the D

minimum time for the CLK
data to be present
before the clock.
Set-up time, ts

D
Hold time tH is the
minimum time for the
CLK
data to remain after the
clock.
Hold time, tH
 Flip Flop Characteristic
• Propagation delay time is specified for the rising and falling
outputs. It is measured between the 50% level of the clock to
the 50% level of the output transition.

50% point on triggering edge 50% point on triggering edge

CLK CLK

Q
50% point on High to
50% point on Low to Low transition of Q
High transition of Q
tPLH tPHL
Other Flip Flops

• Other types of flip flops can be constructed by using

the D flip flop and external logic. The two most
commonly used are:
– JK flip flops
– T flip flops
Characteristic Tables

• Characteristic tables define the logical properties of a

flip flop by describing its operations in tabular form.
– They define the next state as a function of the inputs and the
present state
– Q(t) refers to the present state prior to the application of a
clock edge
– Q(t + 1) refers to the next state one clock period later
– Clock edge input is not listed as inputs but is implied to occur
by the transition from t to t + 1
• An equation that expresses the next state of a latch or Flip-
Flop in terms of its present state and inputs is referred to as a
next-state equation, or characteristics equation
Master Slave D Flip Flop Characteristic
Table

Q(t + 1) = D
 JK Flip Flop

• The JK flip flop performs three operations:

– set it to 1
– reset it to 0
– complement the output
• The J input sets the flip flop to 1.
• The K input resets the flip flop to 0.
• When both J and K are enabled, the output is
complemented.
• When both J & K inputs are 0, the flip flop does not
change its state
JK Characteristic Table
JK Flip Flop
Q(t) J K Q(t+1) Remarks D
0 0 0 Q(t) No Change 0
1 0 0 Q(t) No Change 1
0 0 1 0 Reset 0
1 0 1 0 Reset 0
0 1 0 1 Set 1
1 1 0 1 Set 1
0 1 1 Q’(t) Complement 1
1 1 1 Q’(t) Complement 0

J’K’ J’K JK JK’

Q’(t) 0 0 1 1
Q (t) 1 0 0 1

Q(t+1) = JQ’(t) + K’Q(t)

JK Flip Flop Logic
 Analysis of the JK Circuit

• The circuit applied to the D input is

D = JQ’ + K’Q
– If J = 1 and K = 0, D = Q + Q’ = 1, set to 1

– If J = 0 and K = 1, D = 0, reset to 0

– If J = K = 1, D = Q’, complements the output

– If J = K = 0, D = Q, leaving the output unchanged

T Flip Flop

• The T (Toggle) flip flop is a complementing flip flop

and can be obtained from a JK flip flop when inputs J
and K are tied together.
• The T flip flop can be obtained from a D flip flop by
using an XOR as the input for D.
– The expression for D input is D = T  Q = TQ’ + T’Q
– When T = 0, ( j = k = 0 ) then D = Q and there is no change in
the output
– When T = 1, ( j = k = 1 ) then D = Q’ and the output
complements
T Flip Flop Logic
Characteristic Tables

• Characteristic tables define the logical properties of a

flip flop by describing its operations in tabular form.
– They define the next state as a function of the inputs and the
present state.
– Q(t) refers to the present state prior to the application of a
clock edge.
– Q(t + 1) refers to the next state one clock period later.
– Clock edges are not listed as inputs but are implied by the
transition from t to t + 1.
T Flip Flop Characteristic Table
 Toggle Mode using D Flip Flop
• A D flip flop does not have a toggle mode like the J-K flip-
flop, but you can hardwire a toggle mode by connecting
Q’ back to D as shown. This is useful in some counters as
you will see in Chapter 6
• For example, if Q is LOW, Q’ is HIGH and the flip flop will
toggle on the next clock edge. Because the flip-flop only
changes on the active edge, the output will only change
once for each clock pulse.

D Q
CLK
CLK

Q’

D flip-flop hardwired for

a toggle mode
Characteristic Equations

• The D flip flop can be expressed as:

– Q(t + 1) = D

• The JK flip flop can be expressed as:

– Q(t + 1) = JQ’ + K’Q

• The T flip flop can be expressed as:

– Q(t + 1) = TQ’ + T’Q
 Analysis With D Flip Flops

• We start analysis with a given input equation:

– DA = A  x  y
• This implies a D flip flop with output A.
• x and y are inputs to the circuit
• No outputs are given so the output is implied to come
from the output of the flip flop.
Example Analysis
DA = A  x  y
 Analysis Notes

• With D type flip flops, the state equation is the same

as the input equation.
• With JK and T flip flops, it is necessary to refer to the
corresponding characteristic table or characteristic
equation to obtain the next state values.
Example Sequential Circuit

• Since the D input determines the next state:

– A(t + 1) = A(t)x(t) + B(t)x(t) = Ax + Bx
– B(t + 1) = A’(t)x(t) = A’x
– y(t) = [A(t) + B(t)]x’(t) = (A + B)x’
State Table

• The time sequence of inputs, outputs, and flip flop states

can be enumerated in a state table (transition table)
– The table consists of four sections
» Present state shows the states of the flip flops at
time t
» Input gives input values for each possible present
state
» Next state shows the states of the flip flops one
cycle later at t + 1
» Output gives the value of other outputs at time t for
each present state and input condition
Our Example

• The derivation of a state table requires listing all

possible binary combinations of present state and
inputs.
– In our example, we have eight combinations from
000 to 111
• The next state values are then determined from the
logic diagram or from the state equations
Example State Table

• A(t + 1) = Ax + Bx
• B(t + 1) = A’x
• y(t) = (A + B)x’
Generic Procedure

• A sequential circuit with m flip flops and n inputs

needs 2m + n rows in the state table
• The numbers 0 through 2m + n – 1 are listed under the
present state and input columns
• The next state section has m columns, one for each
flip flop
– Next state values are derived from the state equations
• The output section has many columns as there are
output values
– Output values are derived from the circuit or the Boolean
function in the same matter as a truth table
Alternative Table
State Diagram

• Information in a state table can be represented

graphically in the form of a state diagram.
• In a state diagram:
– a state is represented by a circle
– transitions between states are indicated by directed lines
connecting the circles
– Binary numbers inside the circles represent state of the flip
flops
– Directed lines are labeled with two binary numbers separated
by a slash
» The input value during the present state is labeled first
» The second number gives the output after the present
state with the given input
Example State Diagram
 Flip Flop Input Equations
• The part of the circuit that generates the inputs to flip
flops is described algebraically by a set of Boolean
functions called flip flop input equations (excitation
equations).
• The notation of an input equation consists of the flip
flop input symbol with a subscript to denote the name
of the flip flop output
– DQ = x + y
• In our example the following input equations would be
used:
– DA = Ax + Bx
– DB = A’x
– Y = (A + B)x’
 Direct Inputs

• Some flip flops have asynchronous inputs that are

used to force the flip flop to a particular state
independent of the clock
– The input that sets the flip flop to 1 is called preset
or direct set
– The input that clears the flip flop to 0 is called clear
or direct reset
• Direct inputs are useful for setting all flip flops to a
known starting state prior to clocked operation
D Flip Flop with Asynchronous Reset

Reset
D Flip Flop with Asynchronous Preset

Preset
 Propagation Delay

• Another propagation delay time specification is the time

required for an asynchronous input to cause a change in the
output. Again it is measured from the 50% levels. The 74AHC
family has specified delay times under 5 ns.

50% point 50% point

PRE RST

Q
Q

tPHL tPLH
Analysis of Clocked Sequential Circuits

• The behavior of a clocked sequential circuit is

determined from the inputs, the outputs, and the state
of its flip flops.
– The outputs and the next state are both a function of the
inputs and the present state.
• Analysis consists of obtaining a table or a diagram for
the time sequence of inputs, outputs, and internal
states.
• It is also possible to write Boolean expressions that
describe the behavior.
 State Equations

• A state equation (transition equation) specifies the next

state as a function of the present state and inputs
– It is an algebraic equation that specifies the
condition for a flip flop state transition
JK and T Flip Flop Analysis

• The next-state values of a sequential circuit that uses

flip flops such as JK or T type can be derived using
the following procedure:
– Determine the flip flop input equations in terms of
the present state and input variables
– List the binary values of each input equation
– Use the corresponding flip flop characteristic table
to determine the next state values in the state table
 JK Analysis Example

• JA = B
• JB = x’
• KA = Bx’
• KB = A’x + Ax’ = A  x
 JK Analysis State Table

• JA = B
• JB = x’
• KA = Bx’
• KB = A’x + Ax’ = A  x
JK Analysis State Diagram
T Flip Flop Analysis

• Analysis of a sequential circuit with T flip flops

follows the same procedure outlined for JK flip flops.
• The next state values in the state table can be
obtained wither by using the characteristic table or
the characteristic equation
– Q(t + 1) = T  Q = T’Q + TQ’
T Flip Flop Analysis Example
A
x
T
y

• TA = Bx
T
B • TB = x
• Y = AB
R

CLK Reset
T Flip Flop Analysis State Table

• TA = Bx
• TB = x
• Y = AB

A(t + 1) = TA  A = Bx  A
B(t + 1) = TB  B = x  B
Mealy and Moore Models

• The Mealy and Moore models differ in the way the

output is generated.
– In the Mealy model, the output is a function of both
the present state and input, referred to as a Mealy
finite state machine (FSM) or Mealy machine.
– In the Moore model, the output is a function of the
present state only, referred to as a Moore FSM or
Moore machine.
Example Mealy Model

• Output y is a function of both input x and the present

state of A and B.
 Specifying outputs for a Mealy machine

• Output is function of state and inputs

–specify output on transition arc between states

0/0 current next

reset input state state output
B 1 – – A 0
0 0 A B 0
0/0
0 1 A C 0
reset/0 0 0 B B 0
A 0/1 1/1
0 1 B C 1
0 0 C B 1
1/0
0 1 C C 0
C

1/0

FSMs 88
 Example Moore Model
x A
T
y

R
0 0

1
00/0 11/1
T
B
1 1

R
01/0 10/0
1

CLK Reset 0 0

• The output is a function of the present state only.

 Specifying Outputs For A Moore Machine

• Output is only function of state

–specify in state bubble in state diagram
current next
reset input state state output
0
1 – – A
1 0 0 A B 0
B/0 D/1
0 1 A C 0
0 0 0 B B 0
0
reset 0 1 B D 0
A/0 1 0
0 0 C E 0
1 0 1 C C 0
1
0 0 D E 1
C/0 E/1 0 1 D C 1
0
0 0 E B 1
1 0 1 E D 1
FSMs 90
Comparison of Mealy and Moore machines
• Mealy machines tend to have fewer states
– different outputs on arcs (i*n) rather than states (n)
• Mealy machines react faster to inputs
– react in same cycle – don't need to wait for clock
– delay to output depends on arrival of input
• Moore machines are generally safer to use
– outputs change at clock edge (always one cycle later)
– in Mealy machines, input change can cause output change
as soon as logic is done – a big problem when two
machines are interconnected – asynchronous feedback
logic for
inputs inputs outputs
combinational outputs
logic for
next state logic for combinational
reg outputs logic for reg
outputs
next state

state feedback state feedback

Notes on Mealy and Moore
• In the Moore model, the outputs of the sequential
circuit are synchronized with the clock because they
depend on only flip flop outputs that are synchronized
with the clock.
• In the Mealy model, the outputs may change if the
inputs change during the clock cycle and the outputs
may have momentary false values because of the
delay encountered from the time that the inputs
change and the time that the flip flop outputs change.
– To synchronize a Mealy type circuit, the inputs of
the sequential circuit must be synchronized with
the clock and the outputs must be sampled only
during the clock edge.
 State Reduction and Assignment

• The analysis of sequential circuits starts from a circuit

diagram and culminates in a state table or diagram.
• The design of a sequential circuit starts from a set of
specifications and culminates in a logic diagram.
• One of the things we need to do is look at properties
of sequential circuits that may be used to reduce the
number of gates and flip flops during design.
– Two techniques we can use are state reduction and
state assignment.
State Reduction

• The reduction of the number of flip flops is referred to

as the state reduction problem.
– Algorithms are aimed at reducing the number of states
in the state diagram, while keeping the external input-
output requirements unchanged.
– Since m flip flops produce 2m states, a reduction in the
number of states may or may not result in a reduction in
the number of flip flops.
– An unpredictable effect in reducing the number of flip
flops is that sometimes the equivalent circuit with fewer
flip flops may require more combinational gates.
Example FSM
Example Sequence

• Given an input of 01010110100…

Notes on State Reduction

• What we would like to find with our example is a FSM

with fewer states that still generates the same output
sequences for identical input sequences.
• The problem of state reduction is to find ways of
reducing the number of states in a sequential circuit
without altering the input-output relationships.
State Table for Example
State Reduction Algorithm

• Two states are said to be equivalent if, for each

member of the set of inputs, they give exactly the
same output and send the circuit either to the same
state or to an equivalent state.
– When two states are equivalent, one of them can be
removed without altering the input-output
relationships.
• In our example, we look for two present states that go
to the same next state and have the same output for
both input combinations.
– States g and e are examples
State Reduction
Reduced FSM
State Assignment
• In order to design a sequential circuit with physical
components, it is necessary to assign coded binary
values to the states.
– For a circuit with m states, the codes must contain n bits
where 2n >= m
– In our example,
» The unreduced table requires assignment of 7 states
» The reduced table requires assignment of 5 states

• Unused states of a combination of binary values

become our don’t care conditions which normally
leads to a reduction in the number of gates used for
implementation
State Assignment

• The simplest way to code small state sets is to use the

first five integers in binary counting order
• Another similar assignment is to use the Gray code
• Another possible assignment is the one-hot
Reduced State Table With Assignment

• The binary form of the state table is used to derive the

combinational circuit part of the sequential circuit.
Design Procedure

• Design starts from a specification and results in a

logic diagram or a list of Boolean functions.
• The steps to be followed are:
– Derive a state diagram
– Reduce the number of states
– Assign binary values
– Obtain the binary coded state table
– Choose the type of flip flops to be used
– Derive the simplified flip flop input equations and output
equations
– Draw the logic diagram
A Sequence Detector

• The following FSM detects a sequence of three ones.

Synthesizing Using D Flip Flops

• The next step is to create a state table and then select

two D flip flops to represent the four states, labeling
their outputs as A and B.
• There is one input, x, and one output, y, representing
the input sequence and the output value respectively.
• Remember that the characteristic equation of the D
flip flop is
– Q(t + 1) = DQ
– This means that the next-state values in the state table
specify the D input condition for the flip flop.
State Table for Sequence Detector

• Input equations can be obtained directly from

the table using minterms:
– A(t + 1) = DA(A, B, x) = ∑(3, 5, 7)
– B(t + 1) = DB(A, B, x) = ∑(1, 5, 7)
– y(A, B, x) = ∑(6, 7)
Boolean Minimization

• K-Maps can be used to minimize the input equations,

resulting in
– DA = Ax + Bx
– DB = Ax + B’x
– Y = AB
Logic Diagram
Excitation Table

• The design of sequential circuits other than D type flip

flops is complicated by the fact that input equations
must be derived indirectly from the state table.
– It is necessary to derive a functional relationship between the
state table and the input equations.
• During the design, we usually know the transition
from present to next state but we need to find the flip
flop input conditions that will cause the required
transition.
– We need a table that lists the required inputs for a given
change of state, called an excitation table.
Excitation Tables
Synthesis Using JK Flip Flops

• Synthesis of circuits with JK flip flops is the same as

with D flip flops except that the input equations must
be evaluated from the present-state to the next-state
transition derived from the excitation table.
Example JK Synthesis
Example JK Synthesis
• By using K-maps we can minimize the flip flop input equations.
JK Synthesis Logic
 Synthesis Using T Flip Flops
The procedure for synthesizing circuits using T flip-flops
will be demonstrated by designing a binary counter
• An n-bit binary counter consists of n
flip-flops that can count in binary from
0 to 2n – 1
• The state diagram of a three-bit counter
is shown opposite
• The binary states are indicated inside
the circles
• The Flip-flop outputs repeat the binary
count sequence with a return to 000
after 111
• The directed lines between circles are
not marked with input and output
values as in other state diagrams
 Synthesis Using T Flip Flops
• Remember that state transitions in clocked sequential
circuits occur during a clock edge; the flip-flop remain in
their present states if no clock is applied
• For that reason the clock does not appear explicitly as an
input variable in a state diagram or state table
• From this point of view the state diagram of a counter
does not have to show input and output values along the
directed lines
• The only input to the circuit is the
clock and the outputs are specified by
the present state of the Flip-flops
• The next state of a counter depends
entirely on its present state, and the
state transition occurs every time the
clock goes through a transition
 Synthesis Using T Flip Flops
• Table 5.14 is the state table for the three-bit binary counter
• The three flip-flops are symbolized by A2, A1 and A0
• Binary counters are constructed most efficiently with T flip-flops
because of their complement property
• The flip-flop excitation for the T inputs is derived from the excitation
table of the T flip-flop and by inspection of the state transition of the
present state to the next state
 Synthesis Using T Flip Flops
• As an illustration, consider the flip-flop input entries for row 001
• The present state here is 001 and the next state is 010, which is
the next count in the sequence
• Comparing these two counts, we note that A2 goes from 0 to 0, so
TA2 is marked with 0 because flip-flop A2 must not change when a
clock occurs
• Also, A1 goes from 0 to 1, so TA1 is marked with a 1 because this
flip-flop must be complemented in the next clock edge
• Similarly, A0 goes from 1 to 0, indicating that it must be
complemented, so TA0 is marked with a 1
• The last row with
present state 111, is
compared with the first
count 000, which is its
next state
• Going from all 1s to all
0's requires that all
three flip-flops be
complemented
 Synthesis Using T Flip Flops
• The flip-flop input equations are simplified in the maps of Fig.
5.33
• Note thai TAO has 1s in all eight minterms because the least
significant bit of the counter is complemented with each count
• A Boolean function that includes all minterms defines a
constant value of 1
• The input equations listed under each map specify the
combinational part of the counter
 Synthesis Using T Flip Flops
• Including these functions with the three flip-flops, we obtain
the logic diagram of the counter, as shown in Fig. 5.34
• For simplicity, the reset signal is not shown, but be aware
that every design should include a reset signal
 State Reduction - Implication Chart
Filling in the Implication Chart
• Entry Xij — Row is Si, Column is Sj
• Si is equivalent to Sj if outputs are the same and next
states are equivalent
• Xij contains the next states of Si, Sj which must be
equivalent if Si and Sj are equivalent
• If Si, Sj have different output behavior, then Xij is crossed
out
Example:
• S0 transitions to S1 on 0, S2 on 1;
• S1 transitions to S3 on 0, S4 on 1;
• S0 square X<0,1> contains entries S1-S3 (transition on zero)
S2-S4 (transition on one) S -S
1 3
S0 S2-S4
S1
 Implication Chart Method
S0 (a)

S1 (b)

S2 (c)

S3 (d)

S4 (e)

S5 (f)

S6 (g)

S7 (h)

S0 (a) S1 (b) S2 (c) S3 (d) S4 (e) S5 (f) S6 (g) S7 (h)

State Reduction - Implication Chart

S1 (b)

S2 (c) S3 – S3
S0 – S2
S3 (d) S0 – S1
S3 – S4
S4 (e) S0 – S2 S1 – S2
S1 – S4 S1 – S3
S0 (a) S1 (b) S2 (c) S3 (d)
Implication Chart Method
S2 = S0
S1 (b) S4 = S1

S2 (c) S3 – S3
S0 – S2

S3 (d) S0 – S1
S3 – S4

S4 (e) S0 – S2 S1 – S2
S1 – S4 S1 – S3

S0 (a) S1 (b) S2 (c) S3 (d)

Current Next State Output (Z)

State A=0 A=1 A=0 A=1
S0 S3 S0 1 1
S1 S0 S1 0 0
S3 S1 S3 0 0
Implication Chart Method
Implication Chart Method
Implication Chart Method