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EE 140/240A Linear Integrated Circuits

Spring 2020 Homework 5

1. MOSFET Small Signal Transconductances and Impedances

At low frequencies, single-transistor amplifiers’ small signal model can be abstracted into the following
form:
iout
vin vout

Rin Gm vin Ro

Figure 1: Generic amplifier

where, because our input does not depend in any way on our output (i.e. no feedback)

iout vout
Gm = |v =0VAC Ro = |v =0VAC
vin out iout in

vout
= −Gm Ro
vin
It helps to have some things written out ahead of time (e.g. on your cheat sheet) to use as a reference.
This might seem tedious, but you only have to do it once! Your final answer should have both the full,
unsimplified expression as as well a single simplified answer which uses the assumptions gm ro  1 and
RD ≈ RS ≈ ro

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VDD

RD

vd
id
vg

vs
is
RS

Figure 2: Various configurations of a single-transistor amplifier. Typical configurations are gate-to-drain,

gate-to-source, and source-to-drain. Note that RD and RS can be replaced with complex impedances ZD and
ZS , and your answers will still hold.

id
(a) vg given vd = 0VAC . This is the Gm of a degenerated common source.
Solution:

id gm ro
=
vg ro + RS + gm ro Rs

Rubric: (2 Points)
• +1: Correct sign
• +1: Correct expression (without the sign)
vd
(b) idgiven vg = 0VAC . This is the Ro of a source-degenerated common source.
Solution:

id
= RD ||(ro + RS + gm ro RS )
vd

Rubric: (2 Points)
• +1: Correct sign
• +1: Correct expression (without the sign)
vd
(c) vg assuming RD = ∞Ω. This is the voltage gain of a degenerated common source amplifier.
Solution: Here you can use the answers from parts ?? and ??. For the latter, because RD is infinite,
Ro = ro + RS + gm ro RS

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vd
= −gm ro
vg

Rubric: (2 Points)
• +1: Correct sign
• +1: Correct expression (without the sign)
is
(d) vg given vs = 0VAC . This is the Gm of a source follower.
Solution:

is gm ro
=−
vg ro + RD

Rubric: (2 Points)
• +1: Correct sign
• +1: Correct expression (without the sign)
vs
(e) isgiven vg = 0VAC . This is the Ro of a source follower.
Solution:

is ro + R D
= RS ||
vs 1 + gm ro

Rubric: (2 Points)
• +1: Correct sign
• +1: Correct expression (without the sign)
vs
(f) vg assuming RS = ∞Ω. This is the voltage gain of a source follower.
Solution:

vs gm ro
=
vg 1 + gm ro

Rubric: (2 Points)
• +1: Correct sign
• +1: Correct expression (without the sign)
id
(g) vsgiven vd = 0VAC and vg = 0VAC . This is the Gm of a common gate amplifier.
Solution:

id 1 + gm ro
=−
vs ro

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Rubric: (2 Points)
• +1: Correct sign
• +1: Correct expression (without the sign)
vd
(h) idgiven vs = 0VAC and vg = 0VAC . This is the Ro of a common gate amplifier.
Solution:

id
= ro ||RD
vd

Rubric: (2 Points)
• +1: Correct sign
• +1: Correct expression (without the sign)
vd
(i) vsgiven vg = 0VAC and assuming RD = ∞Ω. This is the gain of a common gate amplifier.
Solution:

vd
= 1 + gm ro
vs

Rubric: (2 Points)
• +1: Correct sign
• +1: Correct expression (without the sign)
vs
(j) isgiven vg = 0VAC and RS = ∞Ω. This is the Rin of a common gate amplifier.
Solution: Note that even in low frequencies, it’s finite!

ro + RD
1 + gm ro

Rubric: (2 Points)
• +1: Correct sign
• +1: Correct expression (without the sign)

2. Cascode Analysis
For the circuit below, assume that µnCox (W /L)n = µ pCox (W /L) p and λn = λ p for all devices. You may
assume that all devices are biased in saturation and that the quadratic model is appropriate. You may assume
that gm ro  1 for all combinations.

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VDD

Vin M1
VS2

VBP M2
Vout
VBN2 M3
VS3
VBN1 M4

(a) Why must all devices have the same overdrive voltage?
Solution:

All devices have the same current running through them, and their µCox (W /L) and λ are all the
same, so their overdrive voltages must all be the same as well.

Rubric: (1 Points)
• +1: Correct explanation
(b) Assuming Vtn = −Vt p = Vt , what are the DC bias voltages on the gates of M1 and M4?
Solution: First, we’ll define k ≡ µn/pCox WL n/p for convenience.

r
2ID
Vov =
k
Because we know the source voltage of both of these devices, we can quickly find the gate bias with

VGSn/SGp = Vt +Vov

s
2ID
VG4 = VDD −Vt −
µCox WL

s
2ID
VG1 = Vt +
µCox WL

Rubric: (2 Points)
• +1: Correct M1 gate bias. Full credit if you just used Vov rather than the full expression with ID ,
etc.

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• +1: Correct M4 gate bias. Full credit if you just used Vov rather than the full expression with ID ,
etc.
(c) What is the minimum voltage for the gate of M3 such that M4 stays in saturation? You may leave your
answer in terms of the supply voltage VDD , the threshold voltage Vt , and overdrive voltage Vov .
Solution: To ensure M4 stays in saturation, VDS4 ≥ Vov . In other words, VS3 ≥ Vov

VDS4 ≥ Vov
VS3 ≥ Vov
−VGS3 +VG3 ≥ Vov
−(Vt +Vov ) +VG3 ≥ Vov
VG3 ≥ Vt + 2Vov

VG3 ≥ Vt + 2Vov

Rubric: (2 Points)
• +1: Correct minimum gate voltage
(d) What is the maximum voltage for the gate of M2 such that M1 stays in saturation? You may leave your
answer in terms of the supply voltage VDD , the threshold voltage Vt , and overdrive voltage Vov .
Solution: Following a similar process as ??

VG2 ≤ VDD − 2Vov −Vt

Rubric: (1 Points)
• +1: Correct M2 maximum gate voltage
(e) If the gates of M2 and M3 are biased according to your answers above, what is the output swing
(minimum to maximum voltage for both M2 and M3 to remain in saturation)? You may leave your
answer in terms of the supply voltage VDD , the threshold voltage Vt , and overdrive voltage Vov .
Solution: With all the source voltages set appropriately, the output can swing down to 2Vov or up to
VDD − 2Vov

VOUT ∈ [2Vov ,VDD − 2Vov ]

Rubric: (2 Points)
• +1: Correct upper bound
• +1: Correct lower bound
(f) What is the impedance seen “looking up” and “looking down” at the output, and the total impedance?
Solution: From the previous parts, we know gm = 2I 1
Vov and ro = λ ID as the same for all devices, but
D

for completeness we’ll include the full expression.

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Looking up, we see:

Rout,up = ro2 + gm2 ro2 ro1 + ro1

= gm ro2 + 2ro

And looking down, the computation is identical:

Rout,down = ro3 + gm3 ro3 ro4 + ro4

= gm ro2 + 2ro

The total impedance is simply the parallel combination of the two

Rout = Rout,up ||Rout,down

gm ro2 + 2ro
=
2

Rout,up = Rout,down = gm ro2 + 2ro

gm ro2 +2ro
Rout = 2

Rubric: (3 Points)
• +1: Correct looking up impedance
• +1: Correct looking down impedance
• +1: Correct output impedance
(g) What is the impedance looking up and down at the source of M3, and the total impedance?
Solution: Looking up from the source of M3, we see:
ro3 + Rout,up
RS3,up =
1 + gm3 ro3
gm ro2 + 3ro
=
1 + gm ro
And looking down, we simply see

RS3,down = ro4
= ro

Once again, the total impedance is the parallel combination of the two:

gm ro2 + 3ro
RS3 = ro ||
1 + gm ro
 −1
1 1 + gm ro
= +
ro gm ro2 + 3ro
 −1
gm ro + 3 + 1 + gm ro
=
gm ro2 + 3ro
ro (gm ro + 3)
=
2gm ro + 4

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2
m ro +3ro
RS3,up = g1+g m ro
RS3,down = ro
ro (gm ro +3)
RS3 = 2gm ro +4

Rubric: (3 Points)
• +1: Correct looking up impedance
• +1: Correct looking down impedance
• +1: Correct output impedance
(h) Is the total impedance seen at the source of M2 different from the source of M3? If not, why?
Solution:

The two impedances are the same! The same current flows through all devices which have the
same µCox WL .

(i) What is the DC gain from the input to the output?

Solution:

Av0 = −Gm Rout

= −gm1 Rout
g2m ro2 + 2gm ro
=−
2

g2m ro2 + 2gm ro

Av0 = −
2

Rubric: (1 Points)
• +1: Correct expression
(j) What is the DC gain from the input to the source of M2?
Solution:
vS2
= −gm1 RS2
vin
= −gm RS2
gm ro (gm ro + 3)
=−
2gm ro + 4

gm ro (gm ro + 3)
Av0,S2 = −
2gm ro + 4

Rubric: (1 Points)

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• +1: Correct expression

(k) What is the input capacitance? Express any device-specific capacitances (e.g. Cgs , Cds , etc.) in terms
of known quantities
Solution: Notice that the Millerization term is only Av0,S2 , and not the full Av0 !

Cin ≈ Cgs1 + (1 − Av0,S2Cgd1 )

= Cgs1 + (1 − Av0,S2 )Cgd
   
2 gm ro (gm ro + 3)
= W LCox +WCol + 1 + WCol
3 2gm ro + 4

   
2 gm ro (gm ro + 3)
Cin ≈ W LCox +WCol + 1 + WCol
3 2gm ro + 4

Rubric: (2 Points)
• +1: Correct Cin equation
• +1: Correct value
(l) Given the total output capacitance of the amplifier is Cout , what are the pole and unity gain frequencies?
Solution: The unity gain frequency:
gm1
ωu =
Cout
The output pole:
1
ωp =
RoutCout
2
=
Cout (gm ro2 + 2ro )

gm1
ωu =
Cout
2
ωp =
Cout (gm ro2 + 2ro )

Rubric: (3 Points)
• +1: Correct pole expression
• +1: Correct unity gain expression
(m) If you double the overdrive voltages on all devices without changing the sizing of the devices, how
does that affect the swing, DC gain, pole frequency, and unity gain frequency?
Solution:
• Swing: Given the new overdrive 2Vov , the output swing is now limited to [4Vov ,VDD − 4Vov ]
• DC Gain: gm = 2I 1
Vov , so gm ↑ 2×. ro = λ ID , so ro ↓ 4×, meaning the overall |Av0 | ↓ 4× (roughly)
D

• Pole Frequency: Rout decreases by roughly 8×, so Cout constant, ω p ↑ 8×

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• Unity Gain Frequency: gm doubles while Cout stays roughly constant, so ωu doubles as well.

Swing [4Vov ,VDD − 4Vov ]

DC Gain ↓ 4×
Pole Frequency ↑ 8×
Unity Gain Frequency ↑ 2×

Rubric: (4 Points)
• +1: Correct explanation for swing
• +1: Correct explanation for DC gain
• +1: Correct explanation for pole frequency
• +1: Correct explanation for unity gain frequency

3. Gain Error
A0
Given a feedback-only system, we usually approximate the closed loop gain 1+A0 f ≈ 1f .

sin + serror sout

A0
−

sfb

How good or bad an estimate is that? Show that the fractional gain error (gain error)/gain is − A10 f
Solution: Finding the gain error:
A0 1 A0 f − 1 − A0 f
− =
1 + A0 f f f (1 + A0 f )
1
=−
f (1 + A0 f )

And now the fraction of the ideal:

1 1
− · f =−
f (1 + A0 f ) 1 + A0 f

Consider a system in unity gain feedback with A0 = 1—this means the fractional gain error is − 21 ! That is,
the output is half of what you estimated.

1
Fractional gain error: − 1+A 0f

This is only a good estimate when A0 f  1; when A0 is low, this can lead to fairly significant
systematic error!

Rubric: (5 Points)

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• +2: Gain Error

• +2: Fraction of ideal
• +1: Comment on estimate

4. Gain Error in a Single-Pole Amplifier

In a single pole op-amp with A0 = 105 V/V, ω p = 1krad/s, a feedback factor of f = 0.01 is used. Find:
A0
(a) the exact low-frequency closed loop gain 1+A0 f . Use a calculator if necessary.
Solution:
A0 105
=
1 + A0 f 1 + 105 · 10−2
105
=
1 + 103
≈ 99.9001

V
Aclosed-loop ≈ 99.90
V

(b) the approximate low-frequency closed-loop gain, 1f .

Solution:

1
= 100
f

(c) the fractional gain error − A10 f . Does it agree with your results from parts ?? and ???
Solution:

1
− A10 f = − 1000 by definition agrees

(d) Above the pole frequency, amplifier gain decreases and gain error increases. What is the fractional
gain error at 10ω p ? 100ω p ?
Solution: At 10× and 100× ω p , the amplifier gain decreases by a factor of 10 and 100, respectively.
As such, the fractional gain error − A10 f increases by a factor of 10 and 100 respectively from the DC
error.

1
@10MHz : −
100
1
@100MHz : −
10

Rubric: (5 Points)

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• +1 each for parts a-c.

• +2: For part d), 1 pt each for 10 and 100MHz

5. LM324
Check out the datasheet for the LM324 quad op-amp: http://www.ti.com/lit/ds/symlink/
lm324.pdf.

(a) Circle and label the following in the diagram:

i. input differential pair (Darlington)
ii. current mirror active load
iii. emitter-follower level shifter(s)
iv. compensation capacitor
v. common emitter amplifier (Darlington)
vi. output stage
Solution:

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Rubric: (6 Points)
• +1 Per correct label.
(b)

Assuming the same process parameters (e.g. VA , β ), how will the performance of the LM324 design
compare to the amplifier above with a bias current of 1mA in the following areas
i. Input impedance. How does bias current and Darlington affect this?
Solution:

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The LM324 has much higher input impedance. Not only is the bias current significantly lower
(which reduces the input base current and increases input impedance), the input Darlington
pair greatly reduces the base current as well, which further increases input impedance.

ii. Impedance at the output of the first stage? How does the emitter-follower affect this? Rubric: (6
Points)
• +2 per part, a-c.
Solution:

The common-emitter Darlington pair alleviates the loading effect of the second stage on the
first. The level shifter provides an additional factor of β multiplying the impedance looking
into the base of the Darlington pair.

iii. Output impedance of the amplifier. How does output stage affect this?
Solution:

The output impedance of the LM324 is given by teh output impedance of the Darlington
pair, which is very small. In addition, the PMOS emitter follower has much lower output
impedance.

(c) Given a diode-connected NPN transistor Q1 which has a 6µA reference current flowing through it,
design a bipolar circuit to generate all four of the current supplies shown in the LM324 schematic. The
50µAand 100µA currents don’t need to be exactly right, but should be close. Label your transistors as
multiples of each other as appropriate, e.g. Q2 = 5Q1. You may assume infinite β .
Solution:

VDD

Q3 Q4=Q3 Q5=Q3 Q6=17×Q3

6µA 6µA 102µA ≈ 100µA

6µA

54µA ≈ 50µA

Q1 Q2=Q1 Q7=9×Q1

Rubric: (4 Points)
• +1 per correct sizing of 6, 50, and 100uA current sources (3 total).
• +1 for a working mirror schematic (npn vs pnp etc).

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(d) (EE240A) For the current supplies that you designed for the LM324 in part ??, estimate the actual
current assuming a transistor β of 100. Use a beta helper to alleviate this problem. How much did the
accuracy improve? Rubric: (2 Points)
• +2 For effort.

6. Differential Pair Drills

You may assume all transistors have λ = 0.

VDD

RD

Vo
V+ M1a M1b V−
VTAIL

RTAIL

(a) For the circuit above, estimate the change in VTAIL , ITAIL , ID1a , ID1b , and Vo due to:
i. An increase of ∆V in both V+ and V−
Solution: This is an increase in the common mode signal, so we consider the common mode
characteristics of our amplifier (and in the process assume a linear model).

Because the gain from the inputs to VTAIL is ≈ 1, VTAIL increases by roughly ∆V .

VTAIL ∆V
ITAIL = RTAIL , so ITAIL increases by roughly RTAIL .

ITAIL ∆V
ID1a ≈ ID1b ≈ 2 , and so they increase by roughly 2RTAIL

Vo = VDD − ID1b RD , so Vo moves by −∆V 2RRTAIL

D

VTAIL +∆V
ITAIL + R∆V
TAIL
ID1a + 2R∆V
TAIL
ID1b + 2R∆V
TAIL
Vo −∆V 2RRTAIL
D

Rubric: (5 Points)
• +1 Per correct item.

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ii. An increase of ∆V ∆V
2 in V+ and − 2 in V−
Solution: This is functionally introducing a differential signal to the amplifier.

Because the gm of the two devices is the same, there’s no net change in current, meaning VTAILL
and ITAIL don’t change.

However, ID1a will increase by ∆V ∆V

2 gm1a , and ID1b will change by − 2 gm1b .
∆V
That said, Vo = VDD − ID1b RD will increase by 2 gm RD .

VTAIL No change
ITAIL No change
ID1a + ∆V
2 gm1a
ID1b − ∆V
2 gm1b
∆V
Vo + 2 gm1b RD

Rubric: (5 Points)
• +1 Per correct item.
iii. An increase of ∆V in just V+
Solution: This is essentially the same as introducing a DC bias of + ∆V
2 on top of a differential
signal, so we can use our answers to parts ?? and ??.

VTAIL will shift by + ∆V

2 due to the common mode shift, and the differential signal will not affect it.

ITAIL will shift by + 2R∆V

TAIL
due to the common mode shift, and the differential signal will not affect
it.

Between the left and right branches, the change in ITAIL will be split evenly for + 4R∆V
TAIL
for both
ID1a and ID1b .

Purely from the differential signal, however, ID1a will increase by +gm1a ∆V
2 and ID1b will shift by
−gm1b ∆V2 .
Finally, Vo will shift by the change in −ID1b RD .

VTAIL + ∆V
2
ITAIL + 2R∆V
TAIL
ID1a + 4R∆V
TAIL
+ gm1a ∆V
2
ID1b + 4R∆V − g ∆V
m1b 2
 TAIL 
Vo −RD + 4RTAIL − gm1b ∆V
∆V
2

Rubric: (5 Points)
• +1 Per correct item.
(b) What is the common mode rejection ratio of this amplifier?

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Solution: Using our answers from parts ?? and ??,

Adiff
CMRR =
ACM
gm1b RD 2RTAIL
= ·
2 RD
= gm1b RTAIL

CMRR = gm1b RTAIL

Rubric: (2 Points)
• +1 Correct definition of CMRR.
• +1 Correct algebra.
(c) What is the common mode input range in terms of Vtn and Vov ?
Solution: We know the input has to be at least one threshold voltage above VTAIL in order for the
devices to be turned on, and if you’re given an overdrive Vov we know the gate voltage has to be another
overdrive above the threshold addition:

VG,min = 2ID1b RTAIL +Vtn +Vov

Vin,CM −Vov −Vtn
= · RTAIL +Vtn +Vov
RTAIL
= Vov +Vtn

On the upper bound, it’s important to note that VTAIL will track the input common mode as a source
follower! on the other hand, as the input common mode increases, Vo decreases by a factor of vtail 2RRTAIL
D

(this refers to the small signal change in Vtail , not the actual DC bias).

This continues until Vo −VTAIL = Vov , after which point one of the devices will fall out of saturation.

We start by finding how high VTAIL can get

VDD = VTAIL +Vov + ID1b RD

 
VTAIL
= VTAIL +Vov + RD
2RTAIL
 
RD
VTAIL 1 + = VDD −Vov
2RTAIL
2RTAIL (VDD −Vov )
VTAIL,max =
2RTAIL + RD
and from here we know VG can be Vtn greater than VD , so

VG,max = VTAIL,max +Vov +Vtn

2(VDD −Vov )RTAIL
= +Vov +Vtn
RD + 2RTAIL

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2(VDD −Vov )RTAIL

Vin,CM ∈ [Vov +Vtn , +Vov +Vtn ]
RD + 2RTAIL

Rubric: (4 Points)
• +2 For correct upper bound.
• +2 For correct lower bound.
(d) Sketch Vov vs. VCM over the input range from part ??
Solution: √
Vov ∝ VCM
Vov

2(VDD −Vov )RTAIL

Vov +Vtn RD +Vov +Vtn
0
0
VCM

Rubric: (2 Points)
• +1 For correct proportionality.
• +1 For correct plot.
(e) Sketch the bounds of the output swing over the input range from part ??
Solution:

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VDD

Vov

2(VDD −Vov )RTAIL

2RTAIL +RD +Vov
2(VDD −Vov )RTAIL
Vov +Vtn 2RTAIL +RD +Vov +Vtn
0
0
VCM

The outline has been marked in green for greater visibility. Rubric: (4 Points)
• +2 For correct region of output swing.
• +2 For rest of the plot.

VDD

M2a M2b

Vo
V+ M1a M1b V−

VBIAS Mtail

(f) For the circuit above, estimate the change in VTAIL , ITAIL , ID1a , ID1b , and Vo due to an increase of ∆V in
both V+ and V− . Do not assume λ = 0.
Solution: It helps to consider the (sort of) equivalent half circuit:

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1
gm2a

V+

2ro3

Once again, VTAIL roughly tracks the input, so it shifts by +∆V .

Looking to the half circuit, ITAIL changes by + ∆V

ro3 (mind your factors of 2!)

∆V
ID1a and ID1b change together by half the change in the tail current, + 2ro3
.

1
And lastly, we know the common mode gain ACM = 2ro gm2 , so Vo changes by − 2r∆V
o gm2

VTAIL +∆V
ITAIL + ∆V
ro3
∆V
ID1a + 2r o3
∆V
ID1b + 2r o3
Vo − 2r∆V
o gm2

Rubric: (5 Points)
• +1 Per correct item.
(g) What is the common mode input range in terms of Vtn and Vov ?
Solution: On the low side,
VCM,min = Vov3 +Vov1 +Vtn

And on the high side (going down the left branch):

VCM,max = VDD − (Vov2 + |Vt p | −Vtn )

VCM ∈ [Vov3 +Vov1 +Vtn ,VDD − (Vov2 + |Vt p | −Vtn )]

Rubric: (4 Points)
• +2 Correct Low side.
• +2 Correct High Side.

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(h) Sketch Vov vs. VCM over the input range from part ??
Solution:

stays pretty flat

Vov

Vov3 +Vov1 +Vtn VDD − (Vov2 + |Vt p | −Vtn )

0
0
VCM

Rubric: (2 Points)
• +2 correct plot.
(i) Skech the bounds of the output swing over the input range from part ??
Solution:

VDD −Vov2
Vov

Vov3

Vov3 +Vov1 +Vtn VDD − (Vov2 + |Vt p | −Vtn )

0
0
VCM

Rubric: (4 Points)

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• +2 For correct region of output swing.

• +2 For rest of the plot.

7. Two-Stage Amplifier

(a) Design a 2-stage NMOS input CMOS op-amp with the following specs:
• 80µA tail current
• Able to sink 200µA from the load
• Output swing to within 200mV of the rails
• Input common mode range to within 200mV of the top rail
• Up to one resistor in the design
Your process technology has the following specs:

• µnCox = 2µ pCox = 200 µA

V2
• Vtn = −Vt p = 0.5V fF
• Col = 0.5 µm
• Lmin = 0.5µm • VDD = 2V
1 fF
• λ= 5V
• Cox = 5 µm 2

Draw the schematic and label the device sizes.

Solution: [20 pts] 1 for each W and L of the 8 transistors, 1 for labeling each of the for current. There
aren’t many things that you get to pick in this problem. You can pick L5, and then L3 and L6 should
be the same. You can pick L2A, and then L2B and L4 should be the same. You can pick L1A, and
then L1B should be the same. (W/L) for M3, M4, and M5 are all fixed by the specs. You have some
flexibility in the overdrive voltage for M1, but Vov2 must be the same as Vov4 (which is set by spec)
to get the right bias.
Some things to remember: (W /L)1a + (W /L)1b = (W /L)3 if their overdrives are the same. (W /L)4 =
(W /L)5 (µnCox )/(µ pCox ) if their overdrives are the same. (W /L)2a + (W /L)2b = (W /L)4 (ID3 /ID5 ).

From design specs, ID3 = 80µA, ID4 = ID5 = 200µA (You can leave some margin here for ID4 andID5 ).
|Vov4 | = Vov5 = 200mV
Vov3 = Vov5 = Vov6 = 200mV (You can also leave some margin for Vov’s)
For input common-mode voltage, max value is
Vcm,max = VDD −Vt p − |Vov2 | +Vtn = VDD − 200mV
so, Vov2 = 200mV
To increase gm of input pair, we choose Vov1 = 100mV (You can choose other values)

Then, we can calculate the size of all transistors (we choose L = 1µm for current mirrors, for a larger
output impedance
2 and minimum length for other transistors).
1 W
2 µnC V = 80µA

ox L 3 ov
so, WL 3 = 20um1um . Similarly,
W 50um W 50um W 10um W 20um





L 5 = 1um L 4 = 0.5um L 2 = 0.5um L 1 = 0.5um
We choose reference branch being 40µA,
W 10um


L 6 = 1um
And resistor is R,
R = VDD −VIreov6f −Vtn = 32.5KΩ
The device sizes are

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(b) [35pts] For your amplifier in part ??:

i. Calculate and tabulate ID , Vov , gm , ro , Cgs , and Cgd for all devices
Solution: [18pts âĂŞ 1âA˛Ď2 pt for each entry in the table above]
Note: Your size in previous question will affect all the following answers. So you might get
different results depending on the size you use.
Q1 Q2 Q3 Q4 Q5 Q6
ID (A) 40µ 40µ 80µ 200µ 200µ 40µ
Vov (V) 100m 200m 200m 200m 200m 200m
gm = 2I Vov (S)
D
0.8m 0.4m 0.8m 2m 2m 0.4m
1
ro = λ ID (Ω) 125K 125K 125K 25K 50K 250K
Cgs = 23 W LCox +WCol (F) 43f 22f 77f 108f 192f 38f
Cgd = WCol (F) 10f 5f 10f 25f 25f 5f
ii. Calculate the first and second stage gain, and the overall gain for both differential and common
mode signals.
Solution: [5 pts. 2 each for 1st and 2nd, 1 for overall]
Av1,di f f = −gm1 (ro1 ||ro2 ) = −50
Av2,di f f = −gm4 (ro4 ||ro5 ) = −34
Av,di f f = Av1,di f f Av2,di f f = 1700
2gm1 1
Av1,cm = − 1+2g m1 ro3 2gm2
= −0.01
Av,cm = Av1,cm Av2,di f f = 0.34
iii. Calculate the common mode input range, and the variation in tail current over that range.
Solution: [2 pts]
Vcm,max = VDD −Vov2 − |Vt p | +Vtn = 1.8V
Vcm,min = Vov3 +Vov1 +Vtn = 0.8V
1
∆IDS3 = ID3 λ ∆VDS3 = 80µ 10 · 1 = 8µA
iv. Calculate the gain across Cgd1a .
Solution: [2 pts]
This question is not meant to be a tough problem, but it is if you want to do it right.
The simplest answer is − ggm2a m1a
= −2 .
A better answer would take into account the source degeneration effect on Vtail, and come up
gm1a
with − 1+gm1a /gm1b gm2 a = −1.
||ro2 +ro1
The best answer would be Rtail = ro11+g m1 ro1
||ro3 ≈ 2g3m1b , and Av = − 1+ggm1a
m1a
Rtail gm2a = −4/5
Any of those answers is fine. Bottom line: there is not much gain across that node, so not much
Millerized input capacitance.
v. Calculate the output pole frequency with a 100fF load capacitance.

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Last Updated: 2020-03-09 12:53 24

Solution: [2 pts]
Rout = ro4 ||ro5 = 17KΩ
Cout ≈ Cl +Cgd4 +Cgd5 = 150 f F
ω p,out = Rout1Cout = 392Mrad/s
vi. Calculate the input capacitance of the second stage for frequencies below the output pole.
Solution: [2 pts]
Av2 = gm4 ro4 = −34
With Miller effect, Cin2 = Cgd4 (1 − Av2 ) +Cgs4 = 983 f F
vii. Calculate the first stage output pole frequency, assuming that it is lower than the output pole.
Solution: [2 pts]
Rout1 = ro1 ||ro2 = 62.5KΩ
Cout1 = Cin2 +Cgd1 +Cgd2 = 998 f F
ω p,out1 = Rout11Cout1 = 16Mrad/s
viii. Calculate the input capacitance of the second stage above the second stage unity gain frequency.
Solution: [2 pts]
Above second stage unity gain frequency, there’s neglectabe Miller effect, as gain becoming too
small.
Cin2 = Cgd4 +Cgs4 = 133 f F
(c) (EE240A) If the same amplifier were run at Vov = 0V, how would that affect the gains and pole
frequency?
Solution: [10 pts]
When Vov drops, transistor gm will increase. With same current, the gain will also increase. This trend
will go on even when the transistor goes to subthreshold region. We also say that the effeciency of the
transistor is the highest in this region.
But, in subthreshold region, transistor size will become huge to support the same current, the capaci-
tance from the transistors will be very large, the pole frequency will drop dramastically. The speed of
the transistor will be lowest in the region.
You can actually find a Vov that with highest effeciency and pole frequecy product, they will be covered
in EE240A.

UCB EE 140/240A, Spring 2020, Homework 5 24