STSPIN948

Datasheet

Scalable 4.5 A dual full-bridge driver for brushed DC motors

Features
• Operating voltage up to 58 V
• Maximum output current up to 4.5 Arms
• Five driving methods with full-bridge and dual half-bridge parallel mode
• RDS(ON) HS + LS = 0.36 Ω typ.
• Adjustable power MOS slew rate
• Integrated amplifiers with two different embedded current control techniques
• Adjustable OFF-time with slow or mixed decay
• Low consumption standby
• Protections
– UVLO
– Overcurrent protection
– Thermal shutdown

Application
• Stage lighting
• Factory automation
• ATM and money handling machines
• Textile machines
• Home appliances
Product status link
• Robotics
STSPIN948 • Antenna control
• Vending machines
Product label
Description
The STSPIN948 is a 4.5 A dual full-bridge driver for brushed DC motors or bipolar
stepper motors.
The power stage is designed with high dynamic performance, allowing to achieve
high frequency PWM control with precise duty-cycle.
Each full-bridge is totally independent with a current limiter with adjustable threshold
and OFF-time with slow or mixed decay selection. Two amplifiers with fixed
amplification factor are available for current sensing (using an external shunt
resistor).
The adjustable slew-rate guarantees the best trade-off between performances and
EMI.
Versatile power stage offers several ways of operation for a high level of flexibility.
The device offers a complete set of protection features including overcurrent,
overtemperature, and low bus voltage detection.

DS14271 - Rev 2 - October 2023 www.st.com

For further information contact your local STMicroelectronics sales office.
 STSPIN948
Block diagram

1 Block diagram

Figure 1. Block diagram

VBOOT VSPUMP VDD REFA VA

CP2 CHARGE UVLO VS

CP1 PUMP
VS
nSTBY OVT

EN/nFAULTA OC\SC OUT1A

LSS1A
EN/nFAULTB

OC\SC OUT2A
VDD

MODE1 LSS2A
VDD
CONTROL +
x10 SENSEA
MODE2 LOGIC -
VDD OFFSETA
VS
MODE3
PWM1A

PWM1B OC\SC OUT1B

PHA

PHB LSS1B

Monostable
(fixed tOFF)
TOFFA Digital buffer OC\SC OUTB2B
(PWM trimming)
Monostable
(fixed tOFF) LSS2B
TOFFB Digital buffer
(PWM trimming)
+
x10 SENSEB
-

SR OFFSETB

GND REFB VB

DS14271 - Rev 2 page 2/36

 STSPIN948
Electrical data

2 Electrical data

2.1 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 1 may cause permanent damage to the device.
Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 1. Absolute maximum ratings

Symbol Parameter Test condition Value Unit

VDD Control logic supply voltage -0.3 to 4 V

VS Power stage supply voltage -0.3 to 62 V

dVS/dt Supply voltage gradient 0.5 V/µs

VSPUMP Charge pump input voltage VS +/- 0.1 V V

VBOOT Bootstrap voltage -0.3 to 62 V

VS < 61.4 V VS + 0.6

VOUT Output voltage V
VS ≥ 61.4 V 62

IOUT DC output current Each output Up to 4.5 Arms

IOUT,peak Peak output current Limited by OC protection A

VLSS Low-side source voltage (LSSxx pins) -0.6 to +2 V

Voltage range at pins REFA and

VREFA, VREFB VDD = 4 V -0.3 to VDD V
REFB
VSR Voltage range at pin SR VDD = 4 V -0.3 to VDD V

VTOFFx Voltage range at pins TOFFx VDD = 4 V -0.3 to VDD V

All digital inputs

excluded
-0.3 to 5.5 V
MODE1, MODE2,
VIN Logic input voltage MODE3, OFFSETA and
OFFSETB
MODE1, MODE2,
MODE3, OFFSETA and -0.3 to VDD V
OFFSETB
IOD Open drain outputs sink current nFAULTA, nFAULTB Up to 8 mA

Tstg Storage temperature -55 to 150 °C

Tj Junction temperature -40 to 150 °C

DS14271 - Rev 2 page 3/36

 STSPIN948
Recommended operating conditions

2.2 Recommended operating conditions

Table 2. Recommended operating conditions

Symbol Parameter Test condition Min. Typ. Max. Unit

Control logic supply

VDD 2.8(1) 3.3 3.6 V
voltage
Power stage supply
VS(2) 5.2 58(3) V
voltage
Charge pump input
VSPUMP VS V
voltage
Bootstrap overdrive
VBO VBOOT – VS 3 V
voltage
Voltage range at pins
VREFA, VREFB 0.1 VDD V
REFA and REFB
VLSS1x, VLSS2x Low-side source voltage -0.6 +1 V

VOUT Output voltage -0.6 VS V

MODE1,
MODE2,
MODE3, 0 VDD V
VIN(4) Logic input voltage
OFFSETA and
OFFSETB
All others 0 5 V
Current limiter time Enabled fixed OFF-time current
RTOFF 10 120 kΩ
setting resistor limiter mode (see Section 5.6.1)
Current limiter time Enabled fixed OFF-time current
CTOFF 0.1 5.6 nF
setting capacitor limiter mode (see Section 5.6.1)
Slew rate selection
RSR See Section 5 Table 7
resistor
Minimum PWM pulse
tpulse 280 ns
width

Charge pump capacitor CCP = 100 nF

tBOOT 170 µs
charging time CBOOT = 1 µF

fPWM Switching frequency 0 500(5) kHz

CBOOT Bootstrap capacitor 1 µF

CCP Charge pump capacitor 100 nF

Tamb Ambient temperature -40 85(2) °C

1. Actual operative range can be limited by UVLO protections

2. Actual operative range according to heat dissipation performance of the application
3. In specific conditions (Tj ≥ 75 °C and RH ≥ 60%), the maximum VS voltage is sustainable for a limited period
4. All digital inputs (excluding MODE1,MODE2,MODE3,OFFSETA and OFFSETB) are 5 V tolerant
5. Actual operative range can be limited by the selected slew rate

DS14271 - Rev 2 page 4/36

 STSPIN948
ESD protection ratings

2.3 ESD protection ratings

Table 3. ESD protection ratings

Symbol Parameter Condition Class Value Unit

HBM Human body model Conforming to ANSI/ESDA/JEDEC JS-001-2014 H2 2 kV

All pins
C2a 500 V
Conforming to ANSI/ESDA/JEDEC JS-002-2014
CDM Charge device model
Corner pins only
C2 750 V
Conforming to ANSI/ESDA/JEDEC JS-002-2014
MM Machine model Conforming to EIA/JESD22-A115-C NC 200 V

2.4 Thermal data

Table 4. Thermal data

Symbol Parameter Condition Value Unit

RthJA Junction to ambient thermal resistance Natural convection, according to JESD51-2a(1) 27.6 °C/W

Cold plate on package top, according to

RthJCtop Junction to case thermal resistance (top side) 13.4 °C/W
JESD51-12.01(1)

Junction to case thermal resistance (bottom Cold plate on exposed pad, according to
RthJCbot 2.4 °C/W
side) JESD51-12.01(1)
RthJB Junction to board thermal resistance According to JESD51-8(1) 11.9 °C/W

ΨJT Junction to top characterization According to JESD51-12.01(1) 0.1 °C/W

ΨJB Junction to board characterization According to JESD51-12.01(1) 11.7 °C/W

1. Simulated as per standard JEDEC (JESD51-7) in natural convection

DS14271 - Rev 2 page 5/36

 STSPIN948
Electrical characteristics

3 Electrical characteristics

Testing conditions: VS = 58 V, VBOOT = 61 V, VDD = 3.3 V, unless otherwise specified.

Typical values are tested at Tj = 25 °C, minimum and maximum values are guaranteed by thermal
characterization in the temperature range of -40 to 125 °C, unless otherwise specified.

Table 5. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

Supply
VDDth(ON) VDD power-on reset VDD rising 2.7 V

VDD falling
VDDth(Hyst) VDD power-on reset hysteresis 100 300 mV
(VDDth(ON) - VDDth(OFF))

VSth(ON) VS turn-on threshold VS rising 5.2 V

VS falling
VSth(Hyst) VS turn-on threshold hysteresis 100 300 mV
(VSth(ON) - VSth(OFF))

VBOth(ON) VBO turn-on threshold VBO rising 2 V

IDD,STBY VDD consumption in standby Standby 3 μA

IS,STBY VS consumption in standby Standby 1 μA

tSTBY Standby time 600 μs

tWAKE Wake-up time 10 μs

Power stage
RDS(ON),LS Low-side turn-on resistance Tj = 25 °C 180 mΩ

RDS(ON),HS High-side turn-on resistance Tj = 25 °C 180 mΩ

Input high to high-side turn-on propagation

tdIN(H) Maximum slew rate 300 ns
delay
Input low to low-side turn-on propagation
tdIN(L) Maximum slew rate 300 ns
delay

Delay matching Maximum slew rate

MT 50 ns
HS and LS turn-on/off MT = |tdH - tdL|

RSR = 1 kΩ 2
RSR = 2.2 kΩ 1.2
SRrise Rising slew rate V/ns
RSR = 5.6 kΩ 0.6
RSR = 10 kΩ 0.3

RSR = 1 kΩ 2
RSR = 2.2 kΩ 1.2
SRfall Falling slew rate V/ns
RSR = 5.6 kΩ 0.6
RSR = 10 kΩ 0.3

Logic input and outputs

VIL Low logic input voltage 0.8 V

VIH High logic input voltage 2 V

VIL(EN) Enable low logic input voltage 0.4 V

VIH(EN) Enable high logic input voltage 2.55 V

DS14271 - Rev 2 page 6/36

 STSPIN948
Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

VOL(nFAULT) Low logic level output voltage (EN/nFAULTx) ISINK = 4 mA 0.4 V

VFAULT FAULT open drain release threshold 0.4 0.6 V

EN/nFAULTA and EN/nFAULTB pull-down

IPD 5 μA
current
RPDin Input pull-down resistor 570 kΩ

Input pull-up resistor

RPUin 570 kΩ
(MODE1, MODE2, and MODE3)
Current limiter
ROFF = 10 kΩ
1 μs
Current limiter off-time COFF = 0.1 nF
tOFF
See Section 5 Figure 10 ROFF = 120 kΩ
500 μs
COFF = 5.6 nF

Integrated amplifier
ACL Gain Full temp range 9.5 10 10.5 V/V

Vin 150 mV step

tsettling Output voltage settling time 200 ns
CL= 100 pF

Protections
IOC Overcurrent threshold See Figure 13 7 14 A

TSD Thermal shutdown threshold 150 °C

TSD(Hyst) Thermal shutdown hysteresis 30 °C

DS14271 - Rev 2 page 7/36

 STSPIN948
Pin description

4 Pin description

Figure 2. Pin connection

OUT2A

OUT2A

OUT1A

OUT1A

OUT1B

OUT1B

OUT2B

OUT2B
VS

VS

VS

VS
48 47 46 45 44 43 42 41 40 39 38 37
LSS1A 1 36 LSS1B

LSS1A 2 35 LSS1B

LSS2A 3 34 LSS2B

LSS2A 4 33 LSS2B

GND 5 32 GND

VSPUMP 6 31 SR

CP1 7 30 MODE1

CP2 8 29 MODE2

VBOOT 9 28 MODE3
EPAD
SENSEA 10 27 SENSEB

VA 11 26 VB

OFFSETA 12 25 OFFSETB
13 14 15 16 17 18 19 20 21 22 23 24
PWM1B

VDD

REFB

TOFFB
EN/nFAULTB
PHB
nSTBY

PWM1A

REFA

TOFFA
EN/nFAULTA
PHA

Table 6. Pad list

N. Name Type Function

1 LSS1A Power Low-side source half-bridge 1A

2 LSS1A Power Low-side source half-bridge 1A
3 LSS2A Power Low-side source half-bridge 2A
4 LSS2A Power Low-side source half-bridge 2A
5 GND Ground Device ground
Supply charge pump circuitry (internally connected to VS).
6 VSPUMP Supply In application must be connected to the CBOOT. It can be shorted to VS
supply
7 CP1 Analog output Charge pump oscillator output1
8 CP2 Analog output Charge pump oscillator output2
9 VBOOT Supply Bootstrap voltage needed to drive the high-side MOSFETs
10 SENSEA Analog input Amplifier A input signal

DS14271 - Rev 2 page 8/36

 STSPIN948
Pin description

N. Name Type Function

11 VA Analog output Amplifier A output signal

12 OFFSETA Digital input Voltage level shift (amplifier A)
Active low standby input. When forced low the device enters in low
13 nSTBY Digital input
consumption mode
14 PWM1A Digital input Half-bridge 1A PWM input
15 PHA Digital input Phase A input
16 PWM1B Digital input Half-bridge 1B PWM input
17 PHB Digital input Phase B input
18 VDD Supply Supply digital logic
Logic input with open drain output.
Logic input/open drain
19 EN/nFAULTA Full-bridge A enable (when low, the power stage is turned off); it is forced
output
low by the integrated open drain MOSFET when a failure occurs.
Logic input with open drain output.
Logic input/open drain
20 EN/nFAULTB Full-bridge B enable (when low, the power stage is turned off); it is forced
output
low by the integrated open drain MOSFET when a failure occurs.
21 REFA Analog input Reference voltage for PWM current limiter circuitry (half-bridge 1A-2A)
22 REFB Analog input Reference voltage for PWM current limiter circuitry (half-bridge 1B-2B)
PWM current limiter off-time adjustment (full-bridge 1A-2A) in fixed off-
Analog input
23 TOFFA time mode
Digital output
Decay output signal in PWM trimming mode
PWM current limiter off-time adjustment (full-bridge 1B-2B) in fixed off-
Analog input
24 TOFFB time mode
Digital output
Decay output signal in PWM trimming mode
25 OFFSETB Digital input Voltage level shift (amplifier A)
26 VB Analog output Amplifier B output signal
27 SENSEB Analog output Amplifier B input signal
28 MODE3 Digital input Mode selector pin 3
29 MODE2 Digital input Mode selector pin 2
30 MODE1 Digital input Mode selector pin 1
31 SR Analog input Slew rate value selection
32 GND Ground Device ground
33 LSS2B Power Low-side source half-bridge 2B
34 LSS2B Power Low-side source half-bridge 2B
35 LSS1B Power Low-side source half-bridge 1B
36 LSS1B Power Low-side source half-bridge 1B
37 OUT2B Power Power output half-bridge 2B
38 OUT2B Power Power output half-bridge 2B
39 OUT1B Power Power output half-bridge 1B
40 OUT1B Power Power output half-bridge 1B
41 VS Supply Supply output power stages
42 VS Supply Supply output power stages
43 VS Supply Supply output power stages
44 VS Supply Supply output power stages

DS14271 - Rev 2 page 9/36

 STSPIN948
Pin description

N. Name Type Function

45 OUT1A Power Power output half-bridge 1A

46 OUT1A Power Power output half-bridge 1A
47 OUT2A Power Power output half-bridge 2A
48 OUT2A Power Power output half-bridge 2A

DS14271 - Rev 2 page 10/36

 STSPIN948
Description

5 Description

The is a protected dual full-bridge with low RDS(ON) and high current capability.
The power stages are designed with high dynamic performance allowing to achieve high frequency PWM control
with precise duty-cycle.
It integrates a full set of protections, PWM current limiter circuitry and amplifiers for the current sensing through an
external shunt resistor.

5.1 Power supply

The device has three supply pins:
• VDD is the control logic supply voltage
• VS is the supply voltage for all the power stage
• VBOOT is the supply voltage for high-side gate drivers
During the power-up, the device is in Under Voltage Lock Out condition (UVLO) until the VS supply voltage rises
above the VSth(ON) threshold and the VBOOT supply voltage rises above the VBOth(ON) threshold.
If during the operation the VS supply falls below VSth(ON) – VSth(Hyst), the device returns in UVLO status until the
turn-on threshold is exceeded again by Vs.
If during the operation the VDD supply falls below VDDth(ON) – VDDth(Hyst), the device is powered down, power
stages are disabled, and all the circuitry (charge pump included) is switched off. When VDD supply rises above
VDDth(ON) the device is in UVLO condition and the charge pump is switched on; the device returns operative as
soon as VBOOT rises above the VBOth(ON) threshold.
If during the operation the VBOOT supply falls below VBOth(ON) – VBOth(Hyst), the device returns in UVLO status
until the turn-on threshold is exceeded again.
In UVLO condition, all the MOSFETs are off and the nFAULT is low.

Figure 3. Power-up and power-down sequences

VS

VSth(Hyst)
VSth(ON)
VDD

VDDth(Hyst)
VDDth(ON)

Power power-down power-down

Operative Operative UVLO Operative
up UVLO (CP discharge) (CP discharge)

UVLO
while VBOOT < VBOth(ON)

DS14271 - Rev 2 page 11/36

 STSPIN948
Power stages and charge pump circuitry

5.2 Power stages and charge pump circuitry

The STSPIN948 integrates power NMOS half-bridges. The input PWM signal drives a corresponding half-bridge
according to the driving mode selected (see Section 5.4 Driving logic). In order to achieve a precise duty-cycle
and low jitter between different half-bridge activation, the propagation delay of PWM signals is optimized. Cross
conduction is prevented thanks to a deadtime between high-side and low-side MOSFET status change.
A blanking circuitry filters the internally generated noise at each commutation of the power stages.
Each gate driving circuit for the high-side MOSFETs is supplied through a charge pump circuitry. The voltage
VBOOT is obtained through an internal oscillator with integrated switches and external capacitors implementing a
charge pump circuit as shown in Figure 4.
The slew rate of the power bridges output is set according to the value of the resistor connected to the SR pin as
reported in Table 7.

Table 7. Slew rate selection

RSR (± 5%) Output slew rate (typ) [V/ns]

1 kΩ 2
2.2 kΩ 1.2
5.6 kΩ 0.6
10 kΩ 0.3

Figure 4. Charge pump circuitry

VS + 3.3V

CBOOT

CFLY
External optional
connection
VS + 3.3V
VBOOT CP1 CP2 VSPUMP

VS

VS
VS

to high side
gate drivers VS

fCP

VS - 3.3V
CHARGE PUMP OSCILLATOR

5.3 Integrated operational amplifiers

The device integrates two operational amplifiers with fixed ACL amplification factor. The amplifier inputs are
connected to the pins SENSEA and SENSEB.
The output is made externally available through a dedicated pin (VA and VB).
Two pins are also available (OFFSETA and OFFSETB) to allow a voltage level shift. When forced high, the
corresponding amplifier output is shifted by VDD/2.

5.4 Driving logic

The device supports five different driving modes according to the status of three input pins as listed in Table 8:
1. Dual independent full-bridge – fixed OFF-time
2. Dual half-bridge (parallel mode) – fixed OFF-time
3. Dual full-bridge (mixed decay operation) – fixed OFF-time
4. Dual independent full-bridge – PWM trimming
5. Dual half-bridge (parallel mode) – PWM trimming

DS14271 - Rev 2 page 12/36

 STSPIN948
Driving logic

Table 8. Driving mode selection

MODE1 MODE2 MODE3 Mode Current limiter mode

LOW LOW LOW Reserved Reserved

LOW HIGH LOW Dual independent full-bridge Fixed OFF-time
HIGH LOW LOW Dual half-bridge (parallel mode) Fixed OFF-time
HIGH HIGH LOW Dual full-bridge (mixed decay) Fixed OFF-time with mixed decay
LOW LOW HIGH Reserved Reserved
LOW HIGH HIGH Dual independent full- bridge PWM trimming
HIGH LOW HIGH Dual half-bridge (parallel mode) PWM trimming
HIGH HIGH HIGH Reserved Reserved

Important: It is not allowed to switch from one driving mode to another one during operation. In application, the MODE1,
MODE2, and MODE3 inputs should be shorted to ground, left floating, or shorted to VDD.

MODE1, MODE2 and MODE3 inputs integrate an internal pull-up resistor.

PWM1A, PHA, PWM1B, PHB, OFFSETA, OFFSETB, and nSTDBY inputs have internal pull-down resistors.
EN/nFAULTA and EN/nFAULTB inputs have an internal pull-down current.

5.4.1 Dual independent full-bridge mode

In dual independent full-bridge mode:
• The outputs of each full-bridge are controlled by the respective PWM1x and PHx inputs
• The status of the power bridge is determined by the corresponding current limiter (A or B). When triggered,
low-side MOS is turned on and slow decay is performed (see Section 5.6.1.1)
• If a fault condition occurs on full-bridge A, the EN/nFAULTA pin is forced low and both the half-bridges (1A
and 2A) are disabled
• If a fault condition occurs on full-bridge B, the EN/nFAULTB pin is forced low and both the half-bridges (1B
and 2B) are disabled

Table 9. Truth table – dual independent full-bridge mode

ENx PWM1x PHx OUT1x OUT2x

0 X(1) X(1) High-Z(2) High-Z(2)

1 0 X LS on LS on
1 1 1 HS on LS on
1 1 0 LS on HS on

1. X: don’t care.
2. High-Z: high impedance.

DS14271 - Rev 2 page 13/36

 STSPIN948
Driving logic

Figure 5. Driver time diagram - dual independent full-bridge mode

PWM1x

PHx

tdIN(H) tdIN(H)
VS
90 %

OUT1x

10 %

tdIN(H) tdIN(L)
VS
90 %

OUT2x

10 %

5.4.2 Dual half-bridge mode - parallel operation

In this mode, two half-bridges are driven in parallel (1A with 2A and 1B with 2B) to obtain two high-current and
low-resistance paths:
• PWM1A, PWM1B, PHA, and PHB drive the half-bridges as reported in Table 10.
• Current limit circuitry connected to Vx and REFx operates for both the half-bridges. when triggered slow
decay is performed and the decay mode is selected through PHx (see Section 5.6.1.2 and Section 5.6.2.2):
– if PHx is low, low-side MOS is turned on
– if PHx is high, output is in high-Z
• If a fault condition occurs on full-bridge A, the EN/nFAULTA pin is forced low and both the half-bridges (1A
and 2A) are disabled
• If a fault condition occurs on full-bridge B, the EN/nFAULTB pin is forced low and both the half-bridges (1B
and 2B) are disabled
This operation mode requires short-circuiting the following pins:
• OUT1A and OUT2A
• LSS1A and LSS2A
• OUT1B and OUT2B
• LSS1B and LSS2B

DS14271 - Rev 2 page 14/36

 STSPIN948
Standby

Table 10. Truth table – dual half-bridge mode (parallel operation)

ENx PWM1x PHx OUT1x/2x

0 X(1) X(1) High-Z(2)

1 0 See Section 5.6.1.2 and Section 5.6.2.2 LS on
1 1 See Section 5.6.1.2 and Section 5.6.2.2 HS on

1. X: don’t care.
2. High Z: high impedance.

Figure 6. Driver time diagram - dual half-bridge mode (parallel operation)

PWM1x

tdIN(H) tdIN(L)
VS
90 %

OUT1x

10 %

tdIN(H) tdIN(L)
VS
90 %

OUT2x

10 %

5.4.3 Dual full-bridge mode – mixed decay operation

This mode is available only with the current limiter set in fixed OFF-time. The device is driven similarly to “Dual
independent full-bridge mode” (see Section 5.4.1); however, when current limiter is triggered, a mixed decay is
performed as described in Section 5.6.1.3.

5.5 Standby
The device provides a low consumption mode. In this condition, the charge pump circuitry is turned off.
The device enters the standby mode by forcing low the nSTBY input for at least tSTBY. As soon as the input is
high, the device returns operative after tWAKE + tBOOT.
In low consumption mode, the EN/nFAULT pin should not be left floating at any times.
During the wake-up, the device is in Under Voltage Lock Out condition (UVLO) until the VBOOT supply voltage
rises above the VBOth(ON) threshold. After tBOOT, the charge-pump circuitry charges the bootstrap capacitor and
the device becomes operative.

DS14271 - Rev 2 page 15/36

 STSPIN948
PWM current control

5.6 PWM current control

The device integrates two independent current limiters internally connected to the V1A and V1B pins.
The input voltage of the amplifier (VSENSEx), the voltage drop of an external shunt resistor connected between
LSS1x and ground, is amplified by ACL and output at V1A or V1B. These voltages are compared with the
respective reference voltage (VREFA or VREFB). When V1x > VREFx the comparator triggers and the device
operates according to the selected decay strategy. The reference voltage value, VREFx, must be selected
according to the load current target value (peak value), the gain of the embedded amplifier (ACL) and the sense
resistors value.
Equation 1
VREFx = RSENSE × ACL + VAMPoffset + VAMPoffset (1)
where VAMPoffset is equal to 0 (OFFSETx is low) or VDD/2 (OFFSETx is high).
Two current limiter modes are available:
1. Fixed OFF-time
2. PWM trimming

5.6.1 Fixed OFF-time mode

When V1x exceeds VREFx the control circuitry sets the device in limiting status to reduce the current. During the
tOFF time, the commutation of the PWMx inputs are ignored.
The device returns to normal operation after a toff time set according to the values of the ROFF resistor and the
COFF capacitor connected to TOFFx pin as shown in Figure 7.

Figure 7. OFF-time regulation circuit

TOFFx

COFF ROFF

The recommended values for ROFF and COFF are shown in Figure 8.
Short-circuiting TOFFx to ground disables the current limiter.

DS14271 - Rev 2 page 16/36

 STSPIN948
PWM current control

Figure 8. tOFF vs. ROFF and COFF

140
120
100

nF
nF
pF

pF
ROFF [kΩ]

.6
=1
00

70
80

=5
=1

=4

FF
CO

FF
FF

FF

CO
60

CO

CO
40
20
0
1 10 100
t OFF [µs]

5.6.1.1 Full-bridge operation mode (fixed OFF-time)

In full-bridge operation mode, the current is limited turning on both the low-side MOS of the full-bridge (slow
decay). As soon as the OFF-time expires the bridges return in the ON state (see Figure 9).

Figure 9. Current control in full-bridge mode (fixed OFF-time)

VS VS VS VS VS

VS VS VS VS VS

OUTX1 OUTX2 OUTX1 OUTX2 OUTX1 OUTX2 OUTX1 OUTX2 OUTX1 OUTX2

SENSEX SENSEX SENSEX SE

SENSEX NSEX
SENSEX

RSENSE RSENSE RSENSE RSENSE RSENSE

t OFF
VREFx
RSENSE x ACL

dead time
ISENSE
dead time

VREFx / ACL

VSENSEx

5.6.1.2 Half-bridge parallel operation mode (fixed OFF-time)

In half-bridge parallel operation mode, the decay strategy is determined by the status of PHx:
• PHx is low: the low-side MOS is switched on
• PHx is high: the output is in high impedance (current recirculates in the body diode)
As soon as the OFF-time expires the bridges return in the ON state (see Figure 10).

DS14271 - Rev 2 page 17/36

 STSPIN948
PWM current control

Figure 10. Current control in half-bridge parallel mode (fixed OFF-time)

PHx = 0 PHx = 1
VS VS VS VS VS VS

VS VS VS VS
VS VS

OUTX OUTX OUTX OUTX

OUTX OUTX

SENSEX SENSEX SENSEX SENSEX

SENSEX SENSEX

NSEX NSEX NSEX

RSENSE RSENSE RSENSE RSENSE RSENSE RSENSE

tOFF
VREFx
RSENSE x ACL

dead time
ISENSE
dead time

VREFx / ACL

VSENSEx

5.6.1.3 Mixed decay operation mode (fixed OFF-time)

In mixed decay operation mode, the current is limited turning on both the low-side MOS of the full-bridge (slow
decay), the system switches from slow decay to quasi-synchronous fast decay (the sinking side of the bridge is
put in high impedance) when the counter reaches a fixed threshold corresponding to a 5/8th of the total decay
time (tOFF).
As soon as the OFF-time expires the bridges return in the ON state (see Figure 11).

Figure 11. Current control in mixed decay mode (fixed OFF-time)

VS VS VS VS VS

VS VS VS VS VS

OUTX1 OUTX2 OUTX1 OUTX2 OUTX1 OUTX2 OUTX1 OUTX2 OUTX1 OUTX2

SENSEX SENSEX SENSEX SENSEX SENSEX

RSENSE RSENSE RSENSE RSENSE RSENSE

t OFF
VREFx
RSENSE x ACL dead time
dead time
ISENSE

5/8 x tOFF 3/8 x tOFF

VREFx / ACL

VSENSEx

DS14271 - Rev 2 page 18/36

 STSPIN948
PWM current control

5.6.2 PWM trimming mode

When V1x exceeds VREFx the control circuitry sets the device in limiting status to reduce the current. The decay
strategy and the return to normal operation depends on the selected driving mode: full-bridge or parallel operation
mode (mixed decay is not available with this current limiter mode).
In PWM trimming mode the TOFFx pin is a digital output and it is forced low during the current decay time.

DS14271 - Rev 2 page 19/36

 STSPIN948
PWM current control

5.6.2.1 Full-bridge operation mode (PWM trimming)

In full-bridge operation mode, the current is limited turning on both the low-side MOS of the full-bridge (slow
decay, see Figure 12). The device returns to normal operation if one of the following conditions occurs:
• nSTDBY is set low
• EN/nFAULTx is set low
• PWM1x is set low

Figure 12. Current control in full-bridge mode (PWM trimming)

ON TIME DEAD TIME OFF TIME
VS VS VS

VS VS VS

OUTX1 OUTX2 OUTX1 OUTX2 OUTX1 OUTX2

SENSEX SENSEX
SE SENSEX
SE

RSENSE RSENSE RSENSE

DEAD TIME

DEAD TIME
DEAD TIME
DEAD TIME

DEAD TIME

OFF TIME

OFF TIME
OFF TIME
ON TIME

ON TIME
ON TIME

VREFx
RSENSE x ACL

ISENSE

PWM1x
(PHx = 1)

VREFx / ACL

VSENSEx

TOFFx

DS14271 - Rev 2 page 20/36

 STSPIN948
PWM current control

5.6.2.2 Half-bridge parallel operation mode (PWM trimming)

In half-bridge parallel operation mode, the decay strategy is determined by the status of PHx (see Figure 13):
• PHx is low: the low-side MOS is switched on
• PHx is high: the output is in high impedance (current recirculates in the body diode)
The device returns to normal operation if one of the following conditions occurs:
• nSTDBY is set low
• EN/nFAULTx is set low
• PWM1x is set low, if PHx = 0
• PWM1x is set high, if PHx = 1

Figure 13. Current control in half-bridge parallel mode (PWM trimming)

PHx = 0 PHx = 1

VS VS VS VS VS VS VS VS VS

VS VS VS VS VS VS VS VS VS

OUTX OUTX OUTX OUTX OUTX OUTX OUTX OUTX OUTX

SENSEX SENSEX SENSEX SENSEX SENSEX SENSEX SENSEX SENSEX SENSEX

RSENSE RSENSE RSENSE RSENSE RSENSE RSENSE RSENSE RSENSE RSENSE

PWM1x PWM1x

VREFx VREFx
RSENSE x ACL RSENSE x ACL
dead time dead time
dead time dead time
ISENSE ISENSE

VREFx / ACL VREFx / ACL

VSENSEx VSENSEx

TOFFx TOFFx

5.6.3 Blanking
In order to avoid spurious triggering of the current limiter’s comparator due to both internal and external noise
(ringing, diode’s recovery currents, etc.), the device integrates a blanking circuitry.
Each full-bridge (A and B) has an independent blanking signal (no cross-blanking). The blanking signal is
generated at each commutation of the full-bridge A or B.
When the bridge is in high impedance, blanking condition is always imposed.

DS14271 - Rev 2 page 21/36

 STSPIN948
Overcurrent protection

5.7 Overcurrent protection

An integrated circuitry, independent from the current limiter, protects the power stage from overcurrent condition.
If the current flowing into one of the integrated MOSFETs exceeds the IOC threshold, the OC protection turns off
all the MOSFETs and forces low the EN/nFAULTx open drain output.
The device holds this condition until the nFAULT input voltage falls below the VIL_EN threshold.
In order to avoid spurious triggering due to noise, a deglitch filter with tOCSD (OC protection) period is
implemented.

Figure 14. Overcurrent protection timings

MCU DEVICE
FAULT_MCU
ENx
EN_MCU EN\FAULTx
REN CEN R
Q OCx
S THSD
FAULTx

The rmal
shu tdown

TjSD
TjSD,hyst

Tj

VENx
VIH

VIL_EN

All power
ENABLED DISABLED DISABLED ENABLED
stages

t SD
FAULTx

The total disable time after an overcurrent event can be set properly sizing the external network connected to the
EN\nFAULT pin.

DS14271 - Rev 2 page 22/36

 STSPIN948
Thermal shutdown

5.8 Thermal shutdown

The device integrates a thermal shutdown protection. When the internal temperature exceeds the TSD
temperature, the power stage is disabled until the temperature returns below TSD - TSD(Hyst).
When the device is in thermal shutdown, the nFAULTA and nFAULTB outputs are forced low (see Figure 15).

Figure 15. Thermal shutdown sequence

MCU DEVICE
FAULT_MCU
ENx
EN_MCU EN\FAULTx
REN CEN R
Q OCx
S THSD
FAULTx

The rmal
shu tdown

TjSD
TjSD,hyst

Tj

VENx
VIH

VIL_EN

All power
ENABLED DISABLED DISABLED ENABLED
stages

t SD
FAULTx

DS14271 - Rev 2 page 23/36

 STSPIN948
Characterization graphs

6 Characterization graphs

Figure 16. Output slew rate vs. temperature (VS = 58 V, normalized at TJ = 25 °C)

1.4
Normalized slew rate

1.2

0.8

0.6
-40 -10 20 50 80 110 140
Temperature [°C]

Figure 17. Output slew rate derating vs. supply voltage (TJ = 25 °C)

100%

80%
Slew rate derating

60%

40%

20%

0%
0 10 20 30 40 50 60
VS [V]

DS14271 - Rev 2 page 24/36

 STSPIN948
Characterization graphs

Figure 18. Overcurrent threshold vs. temperature (VS = 58 V, normalized at TJ = 25 °C)

1.4
Normalized OCD threshold
1.2

0.8

0.6
-40 -10 20 50 80 110 140
Temperature [°C]

Figure 19. Overcurrent threshold vs. supply voltage (TJ = 25 °C, normalized at VS = 58 V)

100%
Normalized OCD threshold

95%

90%

85%

80%
0 10 20 30 40 50 60
VS [V]

DS14271 - Rev 2 page 25/36

 STSPIN948
Characterization graphs

Figure 20. PWM input to output propagation delay vs. temperature (referenced to Tj = 25 °C) T

50
40
30
20
Delay variation [ns]

10
0
-10 -40 -10 20 50 80 110 140

-20 2V/ns
-30 1.2V/ns
-40 0.6V/ns

-50 0.3V/ns
Temperature [°C]

DS14271 - Rev 2 page 26/36

 STSPIN948
Typical application

7 Typical application

Table 11. Typical application value

Name Value

CS 470 nF

CBULK 220 µF

CDD 220 nF

CCP 100 nF

CBOOT 1 µF

RSNSA, RSNSB 50 mΩ / 3W

CENA, CENB 10 nF

RENA,RENB 39 kΩ

CSTBY 1 nF

RSTBY 18 kΩ

ROFF, COFF 22 kΩ, 1 nF (tOFF = 18 µs)

CFBK 100 pF

RFBK 100 Ω

RSR 5.6 kΩ (SR = 0.6 V/ns)

Figure 21. Typical application schematic

VDD VS
CBOOT

VDD CDD CCP

VDD CS CS CSPOL
RSTBY
VDD VBOOT CP1 CP2 VSPUMP VS
nSTBY
RENB RENA Brush DC A
CSTBY
OUT1A
EN\FAULTA
CENA
OUT2A
EN\FAULTB
CENB PWM1A LSS1A

PHA LSS2A RSNSA

SENSEA
PWM1B Brush DC B
PHB OUT1B
MODE1 STSPIN948
VDD
MODE2 OUT2B

MODE3 LSS1B

LSS2B
RSNSB
REFA
PWM
VA SENSEB
CFBK RFBK
REFB
PWM
VB
CFBK RFBK

SR
RSR TOFFA TOFFB OFFSETA OFFSETB GND

COFF ROFF COFF ROFF

DS14271 - Rev 2 page 27/36

 STSPIN948
Layout guidelines

8 Layout guidelines

Two 470 nF bypass capacitors must be connected between the VS supply voltage pins and ground and one 220
nF bypass capacitor must be connected between the VDD supply pin and ground.
These capacitors must be low-ESR ceramic technology and placed as close to the pins as possible (VS and VDD
pins) with a thick ground plane connection to the device GND pin.
A bulk capacitor is required to bypass the high current path. One or more capacitors should be placed as to
minimize the length of high current paths between VS and GND. The connecting metal traces should be as wide
as possible, with numerous vias connecting PCB layers.
In application requiring the device switching at high slew rates or with high output currents, ground layers should
be designed to separate digital and power ground. In this case, the exposed PAD must be connected to the power
ground and the VDD bypass capacitor to the digital ground. The path between the ground of the shunt resistors
and the ceramic bypass capacitor of the device is critical; for this reason it must be as short as possible
minimizing parasitic inductances that can cause voltage spikes on the SENSE and OUT pins.
The current sense resistors should be placed as close as possible to the device pins to minimize trace inductance
between the device pin and resistors avoiding, where possible, to place them on a different board layer.
A low-ESR ceramic capacitor must be placed between the CP1 and CP2 pins (100 nF, rated for 16V) and
between the VBOOT and VSPUMP pins (1 µF, rated for 16 V).
A layout example is shown in Figure 22. Layout example.

Figure 22. Layout example

470 nF

470 nF
OUT2A

OUT2A

OUT1A

OUT1A

OUT1B

OUT1B

OUT2B

OUT2B
VS

VS

VS

VS

48 47 46 45 44 43 42 41 40 39 38 37
LSS1A 1 36 LSS1B

LSS1A 2 35 LSS1B

LSS2A 3 34 LSS2B

LSS2A 4 33 LSS2B

GND 5 32 GND

VSPUMP 6 31 SR
0.1 μF
CP1 7 30 MODE1

CP2 8 29 MODE2
1 μF
VBOOT 9 28 MODE3
EPAD
SENSEA 10 27 SENSEB

VA 11 26 VB

OFFSETA 12 25 OFFSETB
13 14 15 16 17 18 19 20 21 22 23 24
PWM1B

VDD

REFB

TOFFB
EN/nFAULTB
PHB
nSTBY

PWM1A

EN/nFAULTA

REFA

TOFFA
PHA

220 nF

DS14271 - Rev 2 page 28/36

 STSPIN948
Package information

9 Package information

In order to meet environmental requirements, STMicroelectronics offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade
definitions, and product status are available at www.st.com. ECOPACK is an STMicroelectronics trademark.
A customized VFQFPN48 7 x 7 package is proposed. A smaller EPAD, internally connected to the ground pin, is
desired to place through holes on the bottom of the package. Lead plating is Nickel/Palladium/Gold (Ni/Pd/Au).

9.1 VFQFPN48 7 x 7 package information

Figure 23. VFQFPN48 (7 x 7 x 1.0 mm) package outline

BOTTOM VIEW TOP VIEW

SIDE VIEW

DS14271 - Rev 2 page 29/36

 STSPIN948
VFQFPN48 7 x 7 package information

Table 12. VFQFPN48 (7 x 7 x 1.0 mm) package mechanical data

(mm)
Dim.
Min. Typ. Max.

A 0.80 0.9 1.00

A1 0.02 0.05
A2 0.75
A3 0.20
b 0.20 0.25 0.30
D 6.90 7.00 7.10
D2 5.05 5.15 5.25
E 6.85 7.00 7.15
E2 4.95 5.15 5.25
e 0.50
L 0.30 0.40 0.50
ddd 0.08

Figure 24. VFQFPN48 (7 x 7 x 1.0 mm) recommended footprint

DS14271 - Rev 2 page 30/36

 STSPIN948
Ordering information

10 Ordering information

Table 13. Device summary

Order code Package Packaging

STSPIN948TR VFQFPN 7 x 7 x 1 – 48 L Tape and reel

STSPIN948 VFQFPN 7 x 7 x 1 – 48 L Tray

DS14271 - Rev 2 page 31/36

 STSPIN948

Revision history
Table 14. Document revision history

Date Version Changes

07-Jul-2023 1 Initial release.

25-Oct-2023 2 Added P/N in Table 13

DS14271 - Rev 2 page 32/36

 STSPIN948
Contents

Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 ESD protection ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 Power stages and charge pump circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3 Integrated operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4 Driving logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4.1 Dual independent full-bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4.2 Dual half-bridge mode - parallel operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4.3 Dual full-bridge mode – mixed decay operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.6 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6.1 Fixed OFF-time mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6.2 PWM trimming mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.6.3 Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.8 Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6 Characterization graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
7 Typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
8 Layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
9 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
9.1 VFQFPN48 7 x 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

DS14271 - Rev 2 page 33/36

 STSPIN948
List of tables

List of tables
Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. Recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. ESD protection ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 6. Pad list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Slew rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. Driving mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9. Truth table – dual independent full-bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 10. Truth table – dual half-bridge mode (parallel operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 11. Typical application value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. VFQFPN48 (7 x 7 x 1.0 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 14. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DS14271 - Rev 2 page 34/36

 STSPIN948
List of figures

List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Charge pump circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Driver time diagram - dual independent full-bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Driver time diagram - dual half-bridge mode (parallel operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. OFF-time regulation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. tOFF vs. ROFF and COFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Current control in full-bridge mode (fixed OFF-time). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Current control in half-bridge parallel mode (fixed OFF-time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Current control in mixed decay mode (fixed OFF-time). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Current control in full-bridge mode (PWM trimming). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. Current control in half-bridge parallel mode (PWM trimming). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. Overcurrent protection timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Thermal shutdown sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16. Output slew rate vs. temperature (VS = 58 V, normalized at TJ = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. Output slew rate derating vs. supply voltage (TJ = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18. Overcurrent threshold vs. temperature (VS = 58 V, normalized at TJ = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19. Overcurrent threshold vs. supply voltage (TJ = 25 °C, normalized at VS = 58 V) . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. PWM input to output propagation delay vs. temperature (referenced to Tj = 25 °C) T . . . . . . . . . . . . . . . . . . . 26
Figure 21. Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 22. Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 23. VFQFPN48 (7 x 7 x 1.0 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 24. VFQFPN48 (7 x 7 x 1.0 mm) recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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 STSPIN948

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