XM25QH32C

3V 32M-BIT
SERIAL FLASH MEMORY WITH
DUAL/QUAD SPI & QPI

This Data Sheet may be revised by subsequent versions 1 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
Table of Contents

FEATURES ................................................................................................................................................................................................. 4
GENERAL DESCRIPTIONS .................................................................................................................................................................... 4
1. ORDERING INFORMATION ...................................................................................................................................................... 5
2. BLOCK DIAGRAM ......................................................................................................................................................................... 6
3. CONNECTION DIAGRAMS ........................................................................................................................................................ 7
4. SIGNAL DESCRIPTIONS ............................................................................................................................................................. 8
4.1 Chip Select (/CS) ................................................................................................................................................................ 8
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ................................................................ 8
4.3 Write Protect (/WP) .......................................................................................................................................................... 8
4.4 HOLD (/HOLD) ................................................................................................................................................................... 8
4.5 Serial Clock (CLK) ............................................................................................................................................................... 8
4.6 Reset (/RESET)..................................................................................................................................................................... 8
5. FUNCTIONAL DESCRIPTIONS ................................................................................................................................................. 9
5.1 SPI / QPI Operations ........................................................................................................................................................ 9
5.1.1 Standard SPI Instructions ................................................................................................................................................................. 9
5.1.2 Dual SPI Instructions .......................................................................................................................................................................... 9
5.1.3 Quad SPI Instructions ...................................................................................................................................................................... 10
5.1.4 QPI Instructions.................................................................................................................................................................................. 10
5.1.5 Hold Function ..................................................................................................................................................................................... 10
5.1.6 Software Reset & Hardware /RESET pin ................................................................................................................................... 11
5.2 Write Protection .............................................................................................................................................................. 12
5.2.1 Write Protect Features..................................................................................................................................................................... 12
6. STATUS AND CONFIGURATION REGISTERS.................................................................................................................... 13
6.1 Status Registers ............................................................................................................................................................... 13
6.1.14 XM25QH32C Status Register Memory Protection (CMP = 0)..................................................................................... 17
6.1.15 XM25QH32C Status Register Memory Protection (CMP = 1)..................................................................................... 18
7. INSTRUCTIONS.......................................................................................................................................................................... 19
7.1 Device ID and Instruction Set Tables ....................................................................................................................... 19
7.1.1 Manufacturer and Device Identification ................................................................................................................................... 19
7.1.2 Instruction Set Table 1 (Standard/Dual/Quad SPI Instructions)(1).................................................................................. 20
7.1.3 Instruction Set Table 2 (Standard/Dual/Quad SPI Instructions)(1).................................................................................. 21
7.1.4 Instruction Set Table 3 (QPI Instructions)(14) ......................................................................................................................... 22
7.2 Instruction Descriptions ............................................................................................................................................... 24
7.2.1 Write Enable (06h) ............................................................................................................................................................................ 24
7.2.2 Write Enable for Volatile Status Register (50h) ...................................................................................................................... 24
7.2.3 Write Disable (04h) ........................................................................................................................................................................... 25
7.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) ................................................... 25
7.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h)................................................... 26
7.2.6 Read Data (03h) ................................................................................................................................................................................. 29
7.2.7 Fast Read (0Bh) .................................................................................................................................................................................. 30
7.2.8 Fast Read Dual Output (3Bh) ........................................................................................................................................................ 32
7.2.9 Fast Read Quad Output (6Bh) ...................................................................................................................................................... 33
7.2.10 Fast Read Dual I/O (BBh) .......................................................................................................................................................... 34
7.2.11 Fast Read Quad I/O (EBh) ........................................................................................................................................................ 36
7.2.12 Word Read Quad I/O (E7h) ..................................................................................................................................................... 39
7.2.13 Set Burst with Wrap (77h) ........................................................................................................................................................ 41
7.2.14 Page Program (02h) ................................................................................................................................................................... 42

This Data Sheet may be revised by subsequent versions 2 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.15 Quad Input Page Program (32h) ........................................................................................................................................... 44

7.2.16 Quad Page Program (33h) ....................................................................................................................................................... 45
7.2.17 Sector Erase (20h) ....................................................................................................................................................................... 46
7.2.18 32KB Block Erase (52h) ............................................................................................................................................................. 47
7.2.19 64KB Block Erase (D8h)............................................................................................................................................................. 48
7.2.20 Chip Erase (C7h / 60h)............................................................................................................................................................... 49
7.2.21 Erase / Program Suspend (75h) ............................................................................................................................................. 50
7.2.22 Erase / Program Resume (7Ah) .............................................................................................................................................. 52
7.2.23 Power-down (B9h) ...................................................................................................................................................................... 53
7.2.24 Release Power-down / Device ID (ABh) ............................................................................................................................. 54
7.2.25 Read Manufacturer / Device ID (90h) .................................................................................................................................. 56
7.2.26 Read Manufacturer / Device ID Dual I/O (92h) ................................................................................................................ 57
7.2.27 Read Manufacturer / Device ID Quad I/O (94h) .............................................................................................................. 58
7.2.28 Read Unique ID Number (4Bh) .............................................................................................................................................. 59
7.2.29 Read JEDEC ID (9Fh)................................................................................................................................................................... 60
7.2.30 Read SFDP Register (5Ah) ........................................................................................................................................................ 61
7.2.31 Erase Security Registers (44h) ................................................................................................................................................. 74
7.2.32 Program Security Registers (42h) .......................................................................................................................................... 75
7.2.33 Read Security Registers (48h) ................................................................................................................................................. 76
7.2.34 Set Read Parameters (C0h) ...................................................................................................................................................... 77
7.2.35 Burst Read with Wrap (0Ch) .................................................................................................................................................... 78
7.2.36 Enter QPI Mode (38h) ................................................................................................................................................................ 79
7.2.37 Exit QPI Mode (FFh) .................................................................................................................................................................... 80
7.2.38 Enable Reset (66h) and Reset Device (99h) ....................................................................................................................... 81
7.2.39 Ultra-Deep Power-Down(79H) .............................................................................................................................................. 82
7.2.40 Exit Ultra-Deep Power-Down................................................................................................................................................. 83
8. ELECTRICAL CHARACTERISTICS .......................................................................................................................................... 84
8.1 Absolute Maximum Ratings (1)(2) ............................................................................................................................. 84
8.2 Operating Ranges .......................................................................................................................................................... 84
8.3 Power-Up Power-Down Timing and Requirements(1) .................................................................................... 85
8.4 DC Electrical Characteristics........................................................................................................................................ 87
8.5 AC Measurement Conditions(1) ................................................................................................................................ 89
8.6 AC Electrical Characteristics(5) ................................................................................................................................... 90
8.7 Serial Output Timing ..................................................................................................................................................... 94
8.8 Serial Input Timing ......................................................................................................................................................... 94
8.9 /HOLD Timing ................................................................................................................................................................. 94
8.10 /WP Timing ....................................................................................................................................................................... 94
9. PACKAGE SPECIFICATIONS ................................................................................................................................................... 95
9.1 SOP 208mil 8L (Package Code H) ............................................................................................................................ 95
9.2 SOP 150mil 8L (Package Code J) .............................................................................................................................. 96
9.3 USON 4x3 8L (Package Code U2)............................................................................................................................. 97
9.4 WSON 5x6 8L (Package Code W) ............................................................................................................................. 98
REVISIONS LIST......................................................................................................................................................................................... 99
IMPORTANT NOTICE .............................................................................................................................................................................. 101

This Data Sheet may be revised by subsequent versions 3 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

FEATURES
 New Family of SpiFlash Memories Range
– XM25QH32C: 32M-bit / 4M-byte – Full voltage range: 2.3V-3.6V
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold – 18mA maximum active read current
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold – 2 A maximum ultra-deep power down current
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 – -40°C to +85°C operating range
– QPI: CLK, /CS, IO0, IO1, IO2, IO3 – -40°C to +105°C operating range
 Flexible Architecture with 4KB sectors
 Highest Performance Serial Flash
– Uniform Sector/Block Erase (4K/32K/64K-Byte)
– 108MHz Single, Dual/Quad SPI clocks
– Program 1 to 256 byte per programmable page
– 216M/432Mhz equivalent Dual/Quad SPI
– Erase/Program Suspend & Resume
– More than 100,000 erase/program cycles
– More than 20 years data retention time  Advanced Security Features
– Software and Hardware Write-Protect
 Efficient “Continuous Read” and QPI Mode – Power Supply Lock-Down and OTP protection
– Continuous Read with 8/16/32/64-Byte Wrap – Top/Bottom, Complement array protection
– Quad Peripheral Interface (QPI) reduces – 64-Bit Unique ID for each device
instruction overhead – Support Serial Flash Discoverable Parameters
– Allows true XIP (execute in place) operation (SFDP) signature
 High performance program/erase speed – 3 sets of OTP lockable 256 byte security pages
– Page program time: 0.5ms typical – Volatile & Non-volatile Status Register Bits
– Sector erase time: 50ms typical  Space Efficient Packaging
– 32KB Block erase time 150ms typical – SOP 208/150-mil 8L
– 64KB Block erase time 300ms typical – USON 4x3 8L
– Chip erase time: 20 seconds typical – WSON 5x6 8L
 Wide Power Range, Wide Temperature – Contact XMC for KGD and other options
GENERAL DESCRIPTIONS
The XM25QH32C (32M-bit) Serial Flash memory provides a storage solution for systems with limited
space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial
Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI
(XIP) and storing voice, text and data. The device operates on a single 2.3V to 3.6V power supply with
current consumption as low as 1µA for ultra-deep power-down. All devices are offered in space-
saving packages.
The XM25QH32C array is organized into 16,384 programmable pages of 256-bytes each. Up to 256
bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of
128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The
XM25QH32C has 1,024 erasable sectors and 64 erasable blocks respectively. The small 4KB sectors
allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.)
The XM25QH32C support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as
2-clocks instruction cycle Quad Peripheral Interface (QPI): Serial Clock, Chip Select, Serial Data I/O0
(DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 108MHz are supported
allowing equivalent clock rates of 216MHz for Dual I/O and 432Mhz for Quad I/O when using the
Fast Read Dual/Quad I/O and QPI instructions. These transfer rates can outperform standard
Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient
memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true
XIP (execute in place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control,
provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and
device ID and SFDP Register, a 64-bit Unique Serial Number and three 256-bytes Security Registers.

This Data Sheet may be revised by subsequent versions 4 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

1. ORDERING INFORMATION
The ordering part number is formed by a valid combination of the following:
XM 25 QH 32 C X X X X XX X–xx x xx

Special Options [1]

xx = Reserve for special request, default 00

Special Options [1]

x= Reserve for special request, default 0
Special Options [1]
xx: for UID, default 00；

Special Option (Default Driving Strength) [1]

F: 100% S: 75%
H: 50% Q: 25%(default)

Speed Option[1]
10: 108MHz

Packing Options [1]

U: Tube
T: Tape and Reel
R: Tray

QE Code
G: Green Package with QE=0(default)
Q: Green Package with QE=1 fix

Temperature Range
I: Industrial (-40°C to +85°C)
P: Industrial (-40°C to +105°C)

Package Code
H: SOP 208mil 8L; J: SOP 150mil 8L
W: WSON 5x6 8L; U2: USON 4x3 8L

Version
C: C version

Device Density
32: 32Mbit

Series
QH: 2.3~3.6V, 4KB uniform-sector, Quad Mode

Product Family
25: SPI Interface Flash

Company Prefix
Wuhan Xinxin Semiconductor Manufacturing. Corp.

Note1: This option code is not included on the part marking.

This Data Sheet may be revised by subsequent versions 5 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

2. BLOCK DIAGRAM
SFDP Register Security Register 1-3
000000h 0000FFh
003000h 0030FFh
002000h 0020FFh
001000h 0010FFh

Block Segmentation 4FFF00h 4FFFFFh

· Block 63 (64KB) ·
xxFF00h xxFFFFh 4F0000h 4F00FFh
· Sector 15 (4KB) ·
xxF000h xxF0FFh
xxEF00h xxEFFFh
· Sector 14 (4KB) ·
xxE000h xxE0FFh .
xxDF00h xxDFFFh
· Sector 13 (4KB) · .

Write Protect Logic and Row Decode

xxD000h xxD0FFh
. .
.
.
xx2F00h xx2FFFh
· Sector 2 (4KB) ·
xx2000h xx20FFh
xx1F00h xx1FFFh 20FF00h 20FFFFh
· Sector 1 (4KB) · · Block 32 (64KB) ·
xx1000h xx10FFh 200000h 2000FFh
xx0F00h xx0FFFh
· Sector 0 (4KB) · 1FFF00h 1FFFFFh
xx0000h xx00FFh · Block 31 (64KB) ·
1F0000h 1F00FFh
.
.
Write Control .
/WP(IO2) Logic
10FF00h 10FFFFh
· Block 16 (64KB) ·
100000h 1000FFh
Status 0FFF00h 0FFFFFh
· Block 15 (64KB) ·
Register 0F0000h 0F00FFh

.
.
.
High Voltage
/HOLD(IO3) or 00FF00h 00FFFFh
Generators · Block 0 (64KB) ·
/RESET(IO3) 000000h 0000FFh

Beginning Page Ending Page

CLK SPI Page Address Address Address

Command & Latch/Counter

/CS Control
Logic Column Decode and
256-Byte Page Buffer
DI(IO 0)
Byte Address
DI(IO1) Latch/Counter

Figure 1. XM25QH32C Serial Flash Memory Block Diagram

This Data Sheet may be revised by subsequent versions 6 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

3. CONNECTION DIAGRAMS

Top View
/CS 1 8 VCC

DO (IO1) 2 7 /HOLD or /RESET (IO3)

/WP (IO2) 3 6 CLK

GND 4 5 DI (IO0)

Figure 2a. 8-pin SOP 150/ 208-mil (Package Code J, H)

Top View

/CS 1 8 VCC

DO (IO1) 2 7 /HOLD or /RESET (IO3)

/WP (IO2) 3 6 CLK

GND 4 5 DI (IO0)

Figure 2b. 8-pad WSON 5x6-mm (Package Code W)/8-pad USON 4x3-mm (Package Code U2)

PIN NO. PIN NAME I/O FUNCTION

1 /CS I Chip Select Input
2 DO (IO1) I/O Data Output (Data Input Output 1)(1)
3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)(2)
4 GND Ground
5 DI (IO0) I/O Data Input (Data Input Output 0)(1)
6 CLK I Serial Clock Input

7 /HOLD or /RESET (IO3) I/O Hold or Reset Input (Data Input Output 3)(2)

8 VCC Power Supply

Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.

This Data Sheet may be revised by subsequent versions 7 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

4. SIGNAL DESCRIPTIONS
4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program
or write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the
device. After power-up, /CS must transition from high to low before a new instruction will be accepted.
The /CS input must track the VCC supply level at power-up and power-down (see “Write Protection” and
Figure 45). If needed a pull-up resister on the /CS pin can be used to accomplish this.
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The XM25QH32C supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be
set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.
4.3 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and
Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can
be hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad
I/O, the /WP pin function is not available since this pin is used for IO2. See Figure 1a-c for the pin
configuration of Quad I/O operation.
4.4 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,
while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be
ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function
can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low.
When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since
this pin is used for IO3. See Figure 1a-c for the pin configuration of Quad I/O operation.
4.5 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Operations")

4.6 Reset (/RESET)

The /RESET pin allows the device to be reset by the controller. For 8-pin packages, when QE=0, the
IO3 pin can be configured either as a /HOLD pin or as a /RESET pin depending on Status Register
setting. When QE=1, the /HOLD or /RESET function is not available for 8-pin configuration.

This Data Sheet may be revised by subsequent versions 8 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

5. FUNCTIONAL DESCRIPTIONS

5.1 SPI / QPI Operations

Power up

Device Initialization
&Status Register Refresh
(Non-Volatile Cells)

Standard SPI
Hardware SPI Reset
Dual SPI
Reset (66h+99h)
Quad SPI

Enable QPI(38H) Disable QPI(FFH)

QPI Reset
QPI
(66h+99h)

Figure 3. XM25QH32C Serial Flash Memory Operation Diagram

5.1.1 Standard SPI Instructions

The XM25QH32C is accessed through an SPI compatible bus consisting of four signals: Serial
Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI
instructions use the DI input pin to serially write instructions, addresses or data to the device on the
rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge
of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is
not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and
rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.

5.1.2 Dual SPI Instructions

The XM25QH32C supports Dual SPI operation when using instructions such as “Fast Read Dual Output
(3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the
device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions
are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-
speed-critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO
pins become bidirectional I/O pins: IO0 and IO1.

-
This Data Sheet may be revised by subsequent versions 9 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

5.1.3 Quad SPI Instructions

The XM25QH32C supports Quad SPI operation when using instructions such as “Fast Read Quad
Output (6Bh)”, “Fast Read Quad I/O (EBh)”, and“Word Read Quad I/O (E7h)”. These instructions allow
data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad
Read instructions offer a significant improvement in continuous and random access transfer rates
allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad
SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins
become IO2 and IO3 respectively. Quad SPI instructions require the non- volatile Quad Enable bit (QE)
in Status Register-2 to be set.

5.1.4 QPI Instructions

The XM25QH32C supports Quad Peripheral Interface (QPI) operations only when the device is switched
from Standard/Dual/Quad SPI mode to QPI mode using the “Enter QPI (38h)” instruction. The typical
SPI protocol requires that the byte-long instruction code being shifted into the device only via DI pin in
eight serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two
serial clocks are required. This can significantly reduce the SPI instruction overhead and improve
system performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are
exclusive. Only one mode can be active at any given time. “Enter QPI (38h)” and “Exit QPI (FFh)”
instructions are used to switch between these two modes. Upon power-up or after a software reset
using “Reset (99h)” instruction, the default state of the device is Standard/Dual/Quad SPI mode. To
enable QPI mode, the non-volatile Quad Enable bit (QE) in Status Register-2 is required to be set.
When using QPI instructions, the DI and DO pins become bidirectional IO0 and IO1, and the /WP and
/HOLD pins become IO2 and IO3 respectively. See Figure 3 for the device operation modes.

5.1.5 Hold Function

For Standard SPI and Dual SPI operations, the /HOLD signal allows the XM25QH32C operation to
be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases
where the SPI data and clock signals are shared with other devices. For example, consider if the page
buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the
/HOLD function can save the state of the instruction and the data in the buffer so programming can
resume where it left off once the bus is available again. The /HOLD function is only available for
standard SPI and Dual SPI operation, not during Quad SPI or QPI. The Quad Enable Bit QE in Status
Register-2 is used to determine if the pin is used as /HOLD pin or data I/O pin. When QE=0 (factory
default), the pin is /HOLD, when QE=1, the pin will become an I/O pin, /HOLD function is no longer
available.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate
on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the
/HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on
the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the
/HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial
Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored.
The Chip Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to
avoid resetting the internal logic state of the device.

This Data Sheet may be revised by subsequent versions 10 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

5.1.6 Software Reset & Hardware /RESET pin

The XM25QH32C can be reset to the initial power-on state by a software Reset sequence, either in
SPI mode or QPI mode. This sequence must include two consecutive commands: Enable Reset
(66h) & Reset (99h). If the command sequence is successfully accepted, the device will take
approximately 28uS (tSR) to reset. No command will be accepted during the reset period.
For the WSON-8 package types, XM25QH32C can also be configured to utilize a hardware
/RESET pin. The HOLD/RST bit in the Status Register-3 is the configuration bit for /HOLD pin function
or RESET pin function. When HOLD/RST=0 (factory default), the pin acts as a /HOLD pin as described
above; when HOLD/RST=1, the pin acts as a /RESET pin. Drive the /RESET pin low for a minimum
period of ~1us (tRESET*) will reset the device to its initial power-on state. Any on-going Program/Erase
operation will be interrupted and data corruption may happen. While /RESET is low, the device will not
accept any command input.
If QE bit is set to 1, the /HOLD or /RESET function will be disabled, the pin will become one of the four
data I/O pins.

Hardware /RESET pin has the highest priority among all the input signals. Drive /RESET low for a
minimum period of ~1us (tRESET*) will interrupt any on-going external/internal operations, regardless
the status of other SPI signals (/CS, CLK, IOs, /WP and/or /HOLD).

Note:
1. While a faster /RESET pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum is
recommended to ensure reliable operation.
2. There is an internal pull-up resistor for the dedicated /RESET pin on the SOIC-16 package. If the reset function is not needed,
this pin can be left floating in the system.

This Data Sheet may be revised by subsequent versions 11 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

5.2 Write Protection

Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the
XM25QH32C provides several means to protect the data from inadvertent writes.

5.2.1 Write Protect Features

 Device resets when VCC is below threshold
 Time delay write disable after Power-up
 Write enable/disable instructions and automatic write disable after erase or program
 Software and Hardware (/WP pin) write protection using Status Registers
 Write Protection using Power-down instruction
 Lock Down write protection for Status Register until the next power-up
 One Time Program (OTP) write protection for array and Security Registers using Status Register*
* Note: This feature is available upon special order. Please contact XMC for details.

Upon power-up or at power-down, the XM25QH32C will maintain a reset condition while VCC is below
the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 45a). While reset,
all operations are disabled and no instructions are recognized. During power-up and after the VCC
voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay
of tPU. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and
the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC
supply level at power-up until the VCC-min level and tVSL time delay is reached, and it must also track
the VCC supply level at power-down to prevent adverse command sequence. If needed a pull-up
resister on /CS can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program,
Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After
completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared
to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting
the Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC, TB, BP[2:0]) bits. These
settings allow a portion or the entire memory array to be configured as read only. Used in conjunction
with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under
hardware control. See Status Register section for further information. Additionally, the Power-down
instruction offers an extra level of write protection as all instructions are ignored except for the Release
Power-down instruction.

This Data Sheet may be revised by subsequent versions 12 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

6. STATUS AND CONFIGURATION REGISTERS

Three Status and Configuration Registers are provided for XM25QH32C. The Read Status Register-
1/2/3 instructions can be used to provide status on the availability of the flash memory array, whether
the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register
lock status, Erase/Program Suspend status, output driver strength. The Write Status Register
instruction can be used to configure the device write protection features, Quad SPI setting, Security
Register OTP locks, Hold/Reset functions, output driver strength. Write access to the Status Register is
controlled by the state of the non-volatile Status Register Protect bits (SRP0, SRP1), the Write Enable
instruction, and during Standard/Dual SPI operations, the /WP pin.
6.1 Status Registers

S7 S6 S5 S4 S3 S2 S1 S0

SRP0 SEC TB BP2 BP1 BP0 WEL BUSY

Status Register Protect 0

(Volatile/Non-Volatile Writable)

Sector Protect Bit

(Volatile/Non-Volatile Writable)

Top/Bottom Protect Bit

(Volatile/Non-Volatile Writable)

Block Protect Bits

(Volatile/Non-Volatile Writable)

Write Enable Latch

(Status-Only)

Erase/Write In Progress
(Status-Only)

Figure 4a. Status Register-1

6.1.1 Erase/Write In Progress (BUSY) – Status Only

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a
Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or
Erase/Program Security Register instruction. During this time the device will ignore further instructions
except for the Read Status Register and Erase/Program Suspend instruction (see tW , tPP, tSE, tBE, and
tCE in AC Characteristics). When the program, erase or write status/security register instruction has
completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.
6.1.2 Write Enable Latch (WEL) – Status Only
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase
Security Register and Program Security Register.
6.1.3 Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3,
and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write
Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can

This Data Sheet may be revised by subsequent versions 13 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

be protected from Program and Erase instructions (see Status Register Memory Protection table). The
factory default setting for the Block Protection Bits is 0, none of the array protected.
6.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the
Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.
The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction
depending on the state of the SRP0, SRP1 and WEL bits.
6.1.5 Sector/Block Protect Bit (SEC) – Volatile/Non-Volatile Writable
The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0)
protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of
the array as shown in the Status Register Memory Protection table. The default setting is SEC=0.
6.1.6 Complement Protect (CMP) – Volatile/Non-Volatile Writable
The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used
in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection.
Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed.
For instance, when CMP=0, a top 64KB block can be protected while the rest of the array is not; when
CMP=1, the top 64KB block will become unprotected while the rest of the array become read-only.
Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0.

6.1.7 Status Register Protect (SRP1, SRP0) – Volatile/Non-Volatile Writable

The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register
(S8 and S7). The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable (OTP) protection.

Status
SRP1 SRP0 /WP Description
Register

/WP pin has no control. The Status register can be

Software
0 0 X written to after a Write Enable instruction, WEL=1.
Protection
[Factory Default]

Hardware When /WP pin is low the Status Register locked and
0 1 0
Protected cannot be written to.

When /WP pin is high the Status register is unlocked

Hardware
0 1 1 and can be written to after a Write Enable instruction,
Unprotected
WEL=1.

Power Supply
Status Register is protected and cannot be written to
1 0 X Lock-Down
again until the next power-down, power-up cycle.(1)

One Time Status Register is permanently protected and cannot be

1 1 X
Program(2) written to.
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available upon special order. Please contact XMC for details.

This Data Sheet may be revised by subsequent versions 14 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

S15 S14 S13 S12 S11 S10 S9 S8

SUS CMP LB3 LB2 LB1 (R) QE SRP1

Suspend Status
(Status-Only)

Complement Protect
(Volatile/Non-Volatile Writable)

Security Register Lock Bits

(Volatile/Non-Volatile OTP Writable)

Reserved

Quad Enable
(Volatile/Non-Volatile Writable)

Status Register Protect 1

(Volatile/Non-Volatile Writable)

Figure 4b. Status Register-2

6.1.8 Erase/Program Suspend Status (SUS) – Status Only

The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a
Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program
Resume (7Ah) instruction as well as a power-down, power-up cycle.

6.1.9 Security Register Lock Bits (LB3, LB2, LB1) – Volatile/Non-Volatile OTP Writable
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in
Status Register (S13, S12, S11) that provide the write protect control and status to the Security
Registers. The default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1
individually using the Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once
it’s set to 1, the corresponding 256-Byte Security Register will become read-only permanently.

6.1.10 Quad Enable (QE) – Volatile/Non-Volatile Writable

The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI
and QPI operation. When the QE bit is set to a 0 state (factory default for part number with ordering
options “IG”,”IP” and “IF”), the /WP pin and /HOLD are enabled. When the QE bit is set to a 1(factory
default for Quad Enabled part numbers with ordering option “IQ”), the Quad IO2 and IO3 pins are
enabled, and /WP and /HOLD functions are disabled.

QE bit is required to be set to a 1 before issuing an “Enter QPI (38h)” to switch the device from
Standard/Dual/Quad SPI to QPI, otherwise the command will be ignored. When the device is in QPI
mode, QE bit will remain to be 1. A “Write Status Register” command in QPI mode cannot change QE
bit from a “1” to a “0”.

WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during
standard SPI or Dual SPI operation, the QE bit should never be set to a 1.

This Data Sheet may be revised by subsequent versions 15 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

S23 S22 S21 S20 S19 S18 S17 S16

HOLD
DRV1 DRV0 (R) (R) (R)
WPS (R) (R)
/RST
/HOLD or /RESET Function
(Volatile/Non-Volatile Writable)

Output Driver Strength

(Volatile/Non-Volatile Writable)

Reserved

Reserved

Reserved

Figure 4c. Status Register-3

6.1.11 Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable

The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1, DRV0 Driver Strength
0, 0 100%
0, 1 75%
1, 0 50%
1, 1 25% (default)

6.1.12 /HOLD or /RESET Pin Function (HOLD/RST) – Volatile/Non-Volatile Writable

The HOLD/RST bit is used to determine whether /HOLD or /RESET function should be implemented on
the hardware pin for 8-pin packages. When HOLD/RST=0 (factory default), the pin acts as /HOLD;
when HOLD/RST=1, the pin acts as /RESET. However, /HOLD or /RESET functions are only available
when QE=0. If QE is set to 1, the /HOLD and /RESET functions are disabled, the pin acts as a
dedicated data I/O pin.

6.1.13 Reserved Bits – Non Functional

There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to
ignore the values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be
written as “0”, but there will not be any effects.

This Data Sheet may be revised by subsequent versions 16 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

6.1.14 XM25QH32C Status Register Memory Protection (CMP = 0)

STATUS REGISTER(1) XM25QH32C (32M-BIT) MEMORY PROTECTION(3)

PROTECTED PROTECTED PROTECTED PROTECTED
SEC TB BP2 BP1 BP0
BLOCK(S) ADDRESSES DENSITY PORTION(2)

X X 0 0 0 NONE NONE NONE NONE

0 0 0 0 1 63 3F0000h – 3FFFFFh 64KB Upper 1/64

0 0 0 1 0 62 thru 63 3E0000h – 3FFFFFh 128KB Upper 1/32

0 0 0 1 1 60 thru 63 3C0000h – 3FFFFFh 256KB Upper 1/16

0 0 1 0 0 56 thru 63 380000h – 3FFFFFh 512KB Upper 1/8

0 0 1 0 1 48 thru 63 300000h – 3FFFFFh 1MB Upper 1/4

0 0 1 1 0 32 thru 63 200000h – 3FFFFFh 2MB Upper 1/2

0 1 0 0 1 0 000000h – 00FFFFh 64KB Lower 1/64

0 1 0 1 0 0 thru 1 000000h – 01FFFFh 128KB Lower 1/32

0 1 0 1 1 0 thru 3 000000h – 03FFFFh 256KB Lower 1/16

0 1 1 0 0 0 thru 7 000000h – 07FFFFh 512KB Lower 1/8

0 1 1 0 1 0 thru 15 000000h – 0FFFFFh 1MB Lower 1/4

0 1 1 1 0 0 thru 31 000000h – 1FFFFFh 2MB Lower 1/2

X X 1 1 1 0 thru 63 000000h – 3FFFFFh 4MB ALL

1 0 0 0 1 63 3FF000h – 3FFFFFh 4KB U - 1/1024

1 0 0 1 0 63 3FE000h – 3FFFFFh 8KB U - 1/512

1 0 0 1 1 63 3FC000h – 3FFFFFh 16KB U - 1/256

1 0 1 0 X 63 3F8000h – 3FFFFFh 32KB U - 1/128

1 1 0 0 1 0 000000h – 000FFFh 4KB L - 1/1024

1 1 0 1 0 0 000000h – 001FFFh 8KB L - 1/512

1 1 0 1 1 0 000000h – 003FFFh 16KB L - 1/256

1 1 1 0 X 0 000000h – 007FFFh 32KB L - 1/128

Notes:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program command specifies a memory region that contains protected data portion, this
command will be ignored

This Data Sheet may be revised by subsequent versions 17 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

6.1.15 XM25QH32C Status Register Memory Protection (CMP = 1)

STATUS REGISTER(1) XM25QH32C (32M-BIT) MEMORY PROTECTION(3)

PROTECTED PROTECTED PROTECTED PROTECTED
SEC TB BP2 BP1 BP0
BLOCK(S) ADDRESSES DENSITY PORTION(2)

X X 0 0 0 0 thru 63 000000h – 3FFFFFh 4MB ALL

0 0 0 0 1 0 thru 62 000000h – 3EFFFFh 4,032KB Lower 63/64

0 0 0 1 0 0 thru 61 000000h – 3DFFFFh 3,968KB Lower 31/32

0 0 0 1 1 0 thru 59 000000h – 3BFFFFh 3,840KB Lower 15/16

0 0 1 0 0 0 thru 55 000000h – 37FFFFh 3,584KB Lower 7/8

0 0 1 0 1 0 thru 47 000000h – 2FFFFFh 3MB Lower 3/4

0 0 1 1 0 0 thru 31 000000h – 1FFFFFh 2MB Lower 1/2

0 1 0 0 1 1 thru 63 010000h – 3FFFFFh 4,032KB Upper 63/64

0 1 0 1 0 2 thru 63 020000h – 3FFFFFh 3,968KB Upper 31/32

0 1 0 1 1 4 thru 63 040000h – 3FFFFFh 3,840KB Upper 15/16

0 1 1 0 0 8 thru 63 080000h – 3FFFFFh 3,584KB Upper 7/8

0 1 1 0 1 16 thru 63 100000h – 3FFFFFh 3MB Upper 3/4

0 1 1 1 0 32 thru 63 200000h – 3FFFFFh 2MB Upper 1/2

X X 1 1 1 NONE NONE NONE NONE

1 0 0 0 1 0 thru 63 000000h – 3FEFFFh 4,092KB L - 1023/1024

1 0 0 1 0 0 thru 63 000000h – 3FDFFFh 4,088KB L - 511/512

1 0 0 1 1 0 thru 63 000000h – 3FBFFFh 4,080KB L - 255/256

1 0 1 0 X 0 thru 63 000000h – 3F7FFFh 4,064KB L - 127/128

1 1 0 0 1 0 thru 63 001000h – 3FFFFFh 4,092KB U - 1023/1024

1 1 0 1 0 0 thru 63 002000h – 3FFFFFh 4,088KB U - 511/512

1 1 0 1 1 0 thru 63 004000h – 3FFFFFh 4,080KB U - 255/256

1 1 1 0 X 0 thru 63 008000h – 3FFFFFh 4,064KB U - 127/128

Notes:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program command specifies a memory region that contains protected data portion, this
command will be ignored

This Data Sheet may be revised by subsequent versions 18 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7. INSTRUCTIONS
The Standard/Dual/Quad SPI instruction set of the XM25QH32C consists of 43 basic instructions that
are fully controlled through the SPI bus (see Instruction Set Table1-2). Instructions are initiated with the
falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction
code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.

The QPI instruction set of the XM25QH32C consists of 27 basic instructions that are fully controlled
through the SPI bus (see Instruction Set Table 3). Instructions are initiated with the falling edge of Chip
Select (/CS). The first byte of data clocked through IO[3:0] pins provides the instruction code. Data on
all four IO pins are sampled on the rising edge of clock with most significant bit (MSB) first. All QPI
instructions, addresses, data and dummy bytes are using all four IO pins to transfer every byte of data
with every two serial clocks (CLK).

Instructions vary in length from a single byte to several bytes and may be followed by address bytes,
data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed
with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in
Figures 5 through 44. All read instructions can be completed after any clocked bit. However, all
instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a full
8-bits have been clocked) otherwise the instruction will be ignored. This feature further protects the
device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when
the Status Register is being written, all instructions except for Read Status Register will be ignored until
the program or erase cycle has completed.

7.1 Device ID and Instruction Set Tables

7.1.1 Manufacturer and Device Identification

MANUFACTURER ID (MF7 - MF0)

XMC Serial Flash 20h

Device ID (ID7 - ID0) (ID15 - ID0)

Instruction ABh, 90h, 92h, 94h 9Fh
XM25QH32C 15h 4016h

This Data Sheet may be revised by subsequent versions 19 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.1.2 Instruction Set Table 1 (Standard/Dual/Quad SPI Instructions)(1)

Data Input Output Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7

Clock Number (0 – 7) (8 – 15) (16 – 23) (24 – 31) (32 – 39) (40 – 47) (48 – 55)
Write Enable 06h
Volatile SR Write Enable 50h
Write Disable 04h
Read Status Register-1 05h (S7-S0)(2)
(4)
Write Status Register-1 01h (S7-S0)(4)
Read Status Register-2 35h (S15-S8)(2)
Write Status Register-2 31h (S15-S8)
Read Status Register-3 15h (S23-S16)(2)
Write Status Register-3 11h (S23-S16)
Chip Erase C7h/60h

Erase / Program Suspend 75h

Erase / Program Resume 7Ah
Power-down B9h
Ultra-Deep Power-down 79h
Release Power-down / ID ABh Dummy Dummy Dummy (ID7-ID0)(2)
Manufacturer/Device ID 90h Dummy Dummy 00h (MF7-MF0) (ID7-ID0)
JEDEC ID 9Fh (MF7-MF0) (ID15-ID8) (ID7-ID0)
Enter QPI Mode 38h
Enable Reset 66h
Reset Device 99h

This Data Sheet may be revised by subsequent versions 20 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.1.3 Instruction Set Table 2 (Standard/Dual/Quad SPI Instructions)(1)

Data Input Output Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6

Clock Number (0 – 7) (8 – 15) (16 – 23) (24 – 31) (32 – 39) (40 – 47)
Read Unique ID 4Bh Dummy Dummy Dummy Dummy (UID63-UID0)
Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0(3)
Quad Input Page Program 32h A23-A16 A15-A8 A7-A0 D7-D0, … (9)
D7-D0, …(3)
Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0
Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0
Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0
Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0)
Fast Read 0Bh A23-A16 A15-A8 A7-A0 Dummy (D7-D0)
Fast Read Dual Output 3Bh A23-A16 A15-A8 A7-A0 Dummy (D7-D0, …)(7)
Fast Read Quad Output 6Bh A23-A16 A15-A8 A7-A0 Dummy (D7-D0, …)(9)
Read SFDP Register 5Ah A23-A16 A15-A8 A7-A0 Dummy (D7-D0)
Erase Security Register(5) 44h A23-A16 A15-A8 A7-A0
Program Security Register(5) 42h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0(3)
(5)
Read Security Register 48h A23-A16 A15-A8 A7-A0 Dummy (D7-D0)
Data Input Output Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7
Clock Number (0 – 7) (8 – 11) (12 – 15) (16 – 19) (20 – 23) (24 – 27) (28 – 31)
Fast Read Dual I/O BBh A23-A16 A15-A8 A7-A0 Dummy (D7-D0)
Mftr./Device ID Dual I/O 92h A23-A16 A15-A8 A7-A0 Dummy (MF7-MF0) (ID7-ID0)
Data Input Output Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Byte 8 Byte 9
(18,
Clock Number (0 – 7) (8, 9) (10, 11) (12, 13) (14, 15) (16, 17) (20, 21) (22, 23)
19)
Set Burst with Wrap 77h Dummy Dummy Dummy W8-W0
Fast Read Quad I/O EBh A23-A16 A15-A8 A7-A0 M7-M0 Dummy Dummy (D7-D0) (D7-D0)
Word Read Quad I/O(12) E7h A23-A16 A15-A8 A7-A0 M7-M0 Dummy (D7-D0) (D7-D0) (D7-D0)
Mftr./Device ID Quad I/O 94h A23-A16 A15-A8 A7-A0 M7-M0 Dummy Dummy (MF7-MF0) (ID7-ID0)
Quad Page Program 33h A23-A16 A15-A8 A7-A0 D7-D0, …(9) D7-D0 D7-D0 D7-D0 D7-D0

This Data Sheet may be revised by subsequent versions 21 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.1.4 Instruction Set Table 3 (QPI Instructions)(14)

Data Input Output Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6

Clock Number (0, 1) (2, 3) (4, 5) (6, 7) (8, 9) (10, 11)

Write Enable 06h
Volatile SR Write Enable 50h
Write Disable 04h
Read Status Register-1 05h (S7-S0)(2)
(4)
Write Status Register-1 01h (S7-S0)(4)
Read Status Register-2 35h (S15-S8)(2)
Write Status Register-2 31h (S15-S8)
Read Status Register-3 15h (S23-S16)(2)
Write Status Register-3 11h (S23-S16)
Chip Erase C7h/60h
Erase / Program Suspend 75h
Erase / Program Resume 7Ah
Power-down B9h
Set Read Parameters C0h P7-P0
Release Powerdown / ID ABh Dummy Dummy Dummy (ID7-ID0)(2)
Manufacturer/Device ID 90h Dummy Dummy 00h (MF7-MF0) (ID7-ID0)
JEDEC ID 9Fh (MF7-MF0) (ID15-ID8) (ID7-ID0)
Exit QPI Mode FFh
Enable Reset 66h
Reset Device 99h
Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0(9) D7-D0(3)
Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0
Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0
Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0
Fast Read 0Bh A23-A16 A15-A8 A7-A0 Dummy(13) (D7-D0)
(14)
Burst Read with Wrap 0Ch A23-A16 A15-A8 A7-A0 Dummy(13) (D7-D0)
Fast Read Quad I/O EBh A23-A16 A15-A8 A7-A0 M7-M0(13) (D7-D0)

This Data Sheet may be revised by subsequent versions 22 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data
output from the device on either 1, 2 or 4 IO pins.
2. The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction.
3. At least one byte of data input is required for Page Program, Quad Page Program and Program Security
Registers, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the addressing will
wrap to the beginning of the page and overwrite previously sent data.
4. Write Status Register-1 (01h) can also be used to program Status Register-1&2, see section 7.2.5.
5. Security Register Address:
Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address
Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address
Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address
6. Dual SPI address input format:
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
7. Dual SPI data output format:
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
8. Quad SPI address input format: Set Burst with Wrap input format:
IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO0 = x, x, x, x, x, x, W4, x
IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO1 = x, x, x, x, x, x, W5, x
IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO2 = x, x, x, x, x, x, W6, x
IO3 = A23, A19, A15, A11, A7, A3, M7, M3 IO3 = x, x, x, x, x, x, x, x
9. Quad SPI data input/output format:
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
10. Fast Read Quad I/O data output format:
IO0 = (x, x, x, x, D4, D0, D4, D0)
IO1 = (x, x, x, x, D5, D1, D5, D1)
IO2 = (x, x, x, x, D6, D2, D6, D2)
IO3 = (x, x, x, x, D7, D3, D7, D3)
11. Word Read Quad I/O data output format:
IO0 = (x, x, D4, D0, D4, D0, D4, D0)
IO1 = (x, x, D5, D1, D5, D1, D5, D1)
IO2 = (x, x, D6, D2, D6, D2, D6, D2)
IO3 = (x, x, D7, D3, D7, D3, D7, D3)
12. QPI Command, Address, Data input/output format:
CLK # 0 1 2 3 4 5 6 7 8 9 10 11
IO0 = C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0
IO1 = C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1
IO2 = C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2
IO3 = C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3
13. The number of dummy clocks for QPI Fast Read, QPI Fast Read Quad I/O & QPI Burst Read with Wrap is
controlled by read parameter P7 – P4.
14. The wrap around length for QPI Burst Read with Wrap is controlled by read parameter P3 – P0.

This Data Sheet may be revised by subsequent versions 23 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2 Instruction Descriptions

7.2.1 Write Enable (06h)

The Write Enable instruction (Figure 5) sets the Write Enable Latch (WEL) bit in the Status Register to
a 1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block
Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write
Enable instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data Input
(DI) pin on the rising edge of CLK, and then driving /CS high.
/CS
/CS Mode 3
Mode 3 0 1
Mode 3 0 1 2 3 4 5 6 7 Mode 3 CLK Mode 0 Mode 0
CLK Inst ructi on
Mode 0 Mode 0 06h

Instruction (06h)
IO0
DI
(IO0)
IO1
DO
High Impedance
(IO1)
IO2

IO3

Figure 5. Write Enable Instruction for SPI Mode (left) or QPI Mode (right)

7.2.2 Write Enable for Volatile Status Register (50h)

The non-volatile Status Register bits described in section 6.1 can also be written to as volatile bits. This
gives more flexibility to change the system configuration and memory protection schemes quickly
without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status
Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for
Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h)
instruction. Write Enable for Volatile Status Register instruction (Figure 6) will not set the Write Enable
Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the volatile Status
Register bit values.

/CS
/CS
Mode 3 0 1 Mode 3
Mode 3 0 1 2 3 4 5 6 7 Mode 3 Mode 0
CLK Mode 0
CLK Mode 0 Mode 0 Inst ructi on
50h
Instruction(50h)
IO0
DI
(IO0)

IO1
DO High Impedance
(IO1)

IO2

IO 3

Figure 6. Write Enable for Volatile Status Register Instruction for SPI Mode (left) or QPI Mode (right)

This Data Sheet may be revised by subsequent versions 24 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.3 Write Disable (04h)

The Write Disable instruction (Figure 7) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h”
into the DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-
up and upon completion of the Write Status Register, Erase/Program Security Registers, Page
Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase and Reset instructions.

/CS

Mode 3 0 1 Mode 3

CLK Mode 0 Mode 0

/CS
Inst ructi on
04h
Mode 3 0 1 2 3 4 5 6 7 Mode 3

CLK Mode 0 Mode 0

IO0
Instruction(04h)

DI
(IO0) IO1

DO High Impedance
(IO1)
IO2

IO3

Figure 7. Write Disable Instruction for SPI Mode (left) or QPI Mode (right)

7.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction
is entered by driving /CS low and shifting the instruction code “05h” for Status Register-1, “35h” for
Status Register-2 or “15h” for Status Register-3 into the DI pin on the rising edge of CLK. The status
register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB)
first as shown in Figure 8. Refer to section 6.1 for Status Register descriptions.

The Read Status Register instruction may be used at any time, even while a Program, Erase or
Write Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine
when the cycle is complete and if the device can accept another instruction. The Status Register can
be read continuously, as shown in Figure 8. The instruction is completed by driving /CS high.

This Data Sheet may be revised by subsequent versions 25 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK Mode 0

Instruction(05h/35h/15h)
DI
(IO0)

Status Register-1/2/3 out Status Register-1/2/3 out

High Impedance
DO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
(IO1)
* *
* =MSB

Figure 8a. Read Status Register Instruction (SPI Mode)

/CS

Mode 3 0 1 2 3 4 5
CLK Mode 0
Inst ructi on
05h/35h/15h

IO0 4 0 4 0 4

IO1 5 1 5 1 5

IO2 6 2 6 2 6

IO3 7 3 7 3 7

SR-1/2/3 SR-1/2/3
out out

Figure 8b. Read Status Register Instruction (QPI Mode)

7.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h)
The Write Status Register instruction allows the Status Registers to be written. The writable Status
Register bits include: SRP0, SEC, TB, BP[2:0] in Status Register-1; CMP, LB[3:1], QE, SRP1 in Status
Register-2; HOLD/RST, DRV1, DRV0 in Status Register-3. All other Status Register bit locations are
read-only and will not be affected by the Write Status Register instruction. LB[3:1] are non- volatile OTP
bits, once it is set to 1, it cannot be cleared to 0.

To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously
have been executed for the device to accept the Write Status Register instruction (Status Register bit
WEL must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the
instruction code “01h/31h/11h”, and then writing the status register data byte as illustrated in Figure 9a
& 9b.

This Data Sheet may be revised by subsequent versions 26 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must
have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0).
However, SRP1 and LB[3:1] cannot be changed from “1” to “0” because of the OTP protection for these
bits. Upon power off or the execution of a Software/Hardware Reset, the volatile Status Register bit
values will be lost, and the non-volatile Status Register bit values will be restored.

During non-volatile Status Register write operation (06h combined with 01h/31h/11h), after /CS is driven
high, the self-timed Write Status Register cycle will commence for a time duration of tW (See AC
Characteristics). While the Write Status Register cycle is in progress, the Read Status Register
instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the
Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions
again. After the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status
Register will be cleared to 0.

During volatile Status Register write operation (50h combined with 01h/31h/11h), after /CS is driven
high, the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See
AC Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.

The Write Status Register instruction can be used in both SPI mode and QPI mode. However, the QE
bit cannot be written to when the device is in the QPI mode, because QE=1 is required for the device to
enter and operate in the QPI mode.

Refer to section 6.1 for Status Register descriptions.

/CS
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 3
CLK Mode 0 Mode 0
Instruction Register-1/2/3 in
(01h/31h/11h)
DI
7 6 5 4 3 2 1 0
(IO0)
*
High Impedance
DO
(IO1)
*=MSB

Figure 9a. Write Status Register-1/2/3 Instruction (SPI Mode)

/CS
Mode 3 0 1 2 3 Mode 3

CLK Mode 0 Mode 0

Inst ructi on S R 1/2/3
01/31/11h in

IO0 4 0

IO1 5 1

IO2 6 2

IO3 7 3

Figure 9b. Write Status Register-1/2/3 Instruction (QPI Mode)

This Data Sheet may be revised by subsequent versions 27 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

The XM25QH32C is also backward compatible to XMC’s previous generations of serial flash memories,
in which the Status Register-1&2 can be written using a single “Write Status Register-1 (01h)”
command. To complete the Write Status Register-1&2 instruction, the /CS pin must be driven high
after the sixteenth bit of data that is clocked in as shown in Figure 9c & 9d. If /CS is driven high after
the eighth clock, the Write Status Register-1 (01h) instruction will only program the Status Register-1,
the Status Register-2 will not be affected (Previous generations will clear CMP and QE bits).

/CS
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 3
CLK Mode 0 Mode 0
Instruction (01h) Status Register 1 in Status Regist er 2 in
DI
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
(IO0) *
*
High Impedance
DO
(IO1)
* =MSB

Figure 9c. Write Status Register-1/2 Instruction (SPI Mode)

/CS
Mode 3 0 1 2 3 4 5 Mode 3

CLK Mode 0 Mode 0

Inst ructi on
S R1 in S R2 in
01h

IO0 4 0 12 8

IO1 5 1 13 9

IO2 6 2 14 10

IO3 7 3 15 11

Figure 9d. Write Status Register-1/2 Instruction (QPI Mode)

This Data Sheet may be revised by subsequent versions 28 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.6 Read Data (03h)

The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by a
24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the rising edge of the
CLK pin. After the address is received, the data byte of the addressed memory location will be shifted
out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is
automatically incremented to the next higher address after each byte of data is shifted out allowing for a
continuous stream of data. This means that the entire memory can be accessed with a single instruction
as long as the clock continues. The instruction is completed by driving /CS high.

The Read Data instruction sequence is shown in Figure 10. If a Read Data instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of f R
(see AC Electrical Characteristics).

The Read Data (03h) instruction is only supported in Standard SPI mode.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
CLK
Mode 0
Instruction (03h) 24-Bit Address
DI
(IO0) 23 22 21 3 2 1 0
* Data out 1
DI High Impedance
7 6 5 4 3 2 1 0 7
(IO1)
*=MSB *

Figure 10. Read Data Instruction (SPI Mode only)

This Data Sheet may be revised by subsequent versions 29 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.7 Fast Read (0Bh)

The Fast Read instruction is similar to the Read Data instruction except that it can operate at the
highest possible frequency of fc (see AC Electrical Characteristics). This is accomplished by adding
eight “dummy” clocks after the 24-bit address as shown in Figure 11. The dummy clocks allow the
devices internal circuits additional time for setting up the initial address. During the dummy clocks the
data value on the DO pin is a “don’t care”.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK Mode 0
Instruction (0Bh) 24-Bit Address
DI
23 22 21 3 2 1 0
(IO0)
*

DO High Impedance

(IO1)
* =MSB

/CS

CLK 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Dummy Clocks

DI
0
(IO0)
Data Out 1 Data Out 2
DO High Impedance
(IO1) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
* *

Figure 11a. Fast Read Instruction (SPI Mode)

This Data Sheet may be revised by subsequent versions 30 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

Fast Read (0Bh) in QPI Mode

The Fast Read instruction is also supported in QPI mode. When QPI mode is enabled, the number of
dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a wide
range of applications with different needs for either maximum Fast Read frequency or minimum data
access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can
be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a
Reset instruction is 2.

/CS
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13
CLK Mode 0
Int ruct ion IOs switch from
0B h
A23-16 A15-8 A7-0 Dummy* Input to Output

IO0 20 16 12 8 4 0 4 0 4 0 4 0 4

IO1 21 17 13 9 5 1 5 1 5 1 5 1 5

IO2 22 18 14 10 6 2 6 2 6 2 6 2 6

IO3 23 19 15 11 7 3 7 3 7 3 7 3 7

Byt e 1 Byte 2
*＂Set Read Parameters＂instruction (C0h) can set the number of dummy clocks.

Figure 11b. Fast Read Instruction (QPI Mode)

This Data Sheet may be revised by subsequent versions 31 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.8 Fast Read Dual Output (3Bh)

The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction
except that data is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of
standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from
Flash to RAM upon power-up or for applications that cache code-segments to RAM for execution.

Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of fc (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in Figure 12. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy clocks
is “don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data
out clock.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK Mode 0
Instruction(3Bh) 24-Bit Address
DI
23 22 21 3 2 1 0
(IO 0)
*
DO High Impedance

(IO1)
* =MSB
/CS

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK

Dummy Clocks IO0 switch from

Input to Output

DI
0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
(IO 0)

DO High Impedance
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
(IO 1)
* * * *
Date out 1 Date out 2 Date out 3 Date out 4

Figure 12. Fast Read Dual Output Instruction (SPI Mode only)

This Data Sheet may be revised by subsequent versions 32 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.9 Fast Read Quad Output (6Bh)

The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO 0, IO1, IO2, and IO3. The Quad Enable (QE) bit in Status
Register-2 must be set to 1 before the device will accept the Fast Read Quad Output Instruction. The
Fast Read Quad Output Instruction allows data to be transferred at four times the rate of standard SPI
devices.

The Fast Read Quad Output instruction can operate at the highest possible frequency of fc (see AC
Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit
address as shown in Figure 13. The dummy clocks allow the device's internal circuits additional time for
setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO
pins should be high-impedance prior to the falling edge of the first data out clock.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK
Mode 0

Instruction (6Bh) 24-Bit Address

IO 0 3 1
23 22 21 2 0

*
High Impedance
IO 1

High Impedance
IO2

High Impedance
IO3

* =MSB
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
CLK

Dummy Clocks IO0 switches from

Input to Output

IO0 0 4 0 4 0 4 0 4 0 4

High Impedance
IO1 5 1 5 1 5 1 5 1 5

High Impedance
IO2 6 2 6 2 6 2 6 2 6

High Impedance
IO 3 7 3 7 3 7 3 7 3 7
Byte1 Byt e2 Byt e3 Byte4

Figure 13. Fast Read Quad Output Instruction (SPI Mode only)

This Data Sheet may be revised by subsequent versions 33 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.10 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to
input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 14a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS
is raised and then lowered) does not require the BBh instruction code, as shown in Figure 14b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately
entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the
next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus
returning to normal operation. It is recommended to input FFFFh on IO0 for the next instruction (16
clocks), to ensure M4 = 1 and return the device to normal operation.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
Mode 0

Instruction (BBh) A23-16 A15-8 A7-0 M7-0

DI
( IO0） 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0

DO
23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1
( IO1）
* *
* =MSB

/CS

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
CLK

IO s switch from
Input to Output
DI
0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
(IO0)

DO 1 5 7 5 3 1 7 3 7 3 7
7 3 1 5 1 5 1
(IO1)
* Byte1
* Byt e2
* Byte3
* Byte4

Figure 14a. Fast Read Dual I/O Instruction (Initial instruction or previous M5-4 10, SPI Mode only)

This Data Sheet may be revised by subsequent versions 34 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK
Mode 0

A23-16 A15-8 A7-0 M7-0

DI
22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0
( IO 0）

DO 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1
( IO1）
* *
=MSB
*
/CS

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CLK

IO s switch from
Input to Output
DI
0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
(IO0 )

DO 1 5 7 5 3 1 7 3 7 3 7
7 3 1 5 1 5 1
(IO1)
* * * *
Byt e1 Byte2 Byte3 Byte4

Figure 14b. Fast Read Dual I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only)

This Data Sheet may be revised by subsequent versions 35 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.11 Fast Read Quad I/O (EBh)

The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO 0, IO1, IO2 and IO3 and four Dummy
clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction
overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad
Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.

Fast Read Quad I/O with “Continuous Read Mode”

The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 15a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after
/CS is raised and then lowered) does not require the EBh instruction code, as shown in Figure 15b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately
entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the
next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus
returning to normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks),
to ensure M4 = 1 and return the device to normal operation.
/CS

CLK Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode 0
IOs switch from
Instruction（EBh） A23-16 A15-8 A7-0 M7-0 Dummy Dummy
Input to Output

20 16 12 8 4 0 4 0 4 0 4 0 4
IO0

IO1
21 17 13 9 5 1 5 1 5 1 5 1 5

IO 2 22 18 14 10 6 2 6 2 6 2 6 2 6

IO3 23 19 15 11 7 3 7 3 7 3 7 3 7

Byte 1 Byte 2 Byte 3

Figure 15a. Fast Read Quad I/O Instruction (Initial instruction or previous M5-410, SPI Mode)

This Data Sheet may be revised by subsequent versions 36 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK
Mode 0
IOs switch from
A23-16 A15-8 A7-0 M7-0 Dummy Dummy Input to Output

IO0 20 16 12 8 4 0 4 0 4 0 4 0 4

IO1
21 17 13 9 5 1 5 1 5 1 5 1 5

IO2 22 18 14 10 6 2 6 2 6 2 6 2 6

IO3 23 19 15 11 7 3 7 3 7 3 7 3 7

Byte 1 Byt e 2 Byte 3

Figure 15b. Fast Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode)

Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode

The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by
issuing a “Set Burst with Wrap” (77h) command prior to EBh. The “Set Burst with Wrap” (77h)
command can either enable or disable the “Wrap Around” feature for the following EBh commands.
When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-
byte section of a 256-byte page. The output data starts at the initial address specified in the instruction,
once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the
beginning boundary automatically until /CS is pulled high to terminate the command.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and
then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
commands.

The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap
around section within a page. Refer to section 7.2.13 for detail descriptions.

This Data Sheet may be revised by subsequent versions 37 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

Fast Read Quad I/O (EBh) in QPI Mode

The Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 15c. When QPI
mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)”
instruction to accommodate a wide range of applications with different needs for either maximum Fast
Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting,
the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy
clocks upon power up or after a Reset instruction is 2. In QPI mode, the “Continuous Read Mode” bits
M7-0 are also considered as dummy clocks. In the default setting, the data output will follow the
Continuous Read Mode bits immediately.

“Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction.
Please refer to the description on previous pages.

“Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a read
operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0Ch)
instruction must be used. Please refer to 7.2.35 for details.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
CLK
Mode 0
Instruction
EBh A23-16 A15-8 A7-0 M7-0 IOs switch from
*
Input to Output

20 16 12 8 4 0 4 0 4 0 4 0 4
IO0

IO1 21 17 13 9 5 1 5 1 5 1 5 1 5

22 18 14 10 6 2 6 2 6 2 6 2 6
IO2

IO3 23 19 15 11 7 3 7 3 7 3 7 3 7

Byte 1 Byte 2 Byte 3

*＂Set Read Parameters＂ instruction (C0h) can

set the number of dummy clocks

Figure 15c. Fast Read Quad I/O Instruction (Initial instruction or previous M5-410, QPI Mode)

This Data Sheet may be revised by subsequent versions 38 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.12 Word Read Quad I/O (E7h)

The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction
except that the lowest Address bit (A0) must equal 0 and only two Dummy clocks are required prior to
the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access
for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2
must be set to enable the Word Read Quad I/O Instruction.

Word Read Quad I/O with “Continuous Read Mode”

The Word Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 16a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after
/CS is raised and then lowered) does not require the E7h instruction code, as shown in Figure 16b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately
entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the
next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus
returning to normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks),
to ensure M4 = 1 and return the device to normal operation.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
CLK
Mode 0
IOs switch from
Instruction (E7h) A23-16 A15-8 A7-0 M7-0 Dummy input to Output
IO0 4 4
20 16 12 8 0 0 4 0 4 0 4

IO1 21 17 13 9 5 1 5 1 5 1 5 1 5

IO2 22 18 14 10 6 2 6 2 6 2 6 2 6

IO3 23 19 15 11 7 3 7 3 7 3 7 3 7

Byte 1 Byte 2 Byte 3

Figure 16a. Word Read Quad I/O Instruction (Initial instruction or previous M5-4 10, SPI Mode only)

This Data Sheet may be revised by subsequent versions 39 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13
CLK
Mode 0
IOs switch from
A23-16 A15-8 A7-0 M7-0 Dummy input to Output
IO0 4 4
20 16 12 8 0 0 4 0 4 0 4

IO1 21 17 13 9 5 1 5 1 5 1 5 1 5

IO2 22 18 14 10 6 2 6 2 6 2 6 2 6

IO3 23 19 15 11 7 3 7 3 7 3 7 3 7

Byt e 1 Byt e 2 Byte 3

Figure16b. Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only)

Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Word Read Quad I/O instruction can also be used to access a specific portion within a page by
issuing a “Set Burst with Wrap” (77h) command prior to E7h. The “Set Burst with Wrap” (77h)
command can either enable or disable the “Wrap Around” feature for the following E7h commands.
When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-
byte section of a 256-byte page. The output data starts at the initial address specified in the instruction,
once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the
beginning boundary automatically until /CS is pulled high to terminate the command.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and
then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
commands.

The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap
around section within a page. See 7.2.13 for detail descriptions.

This Data Sheet may be revised by subsequent versions 40 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.13 Set Burst with Wrap (77h)

In Standard SPI mode, the Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read
Quad I/O” and “Word Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section
within a 256-byte page. Certain applications can benefit from this feature and improve the overall
system code execution performance.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin
low and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0.
The instruction sequence is shown in Figure 17. Wrap bit W7 and the lower nibble W3-0 are not used.

W4 = 0 W4 =1 (DEFAULT)
W6, W5 Wrap Wrap
Wrap Around Wrap Length
Around Length
0 0 Yes 8-byte No N/A
0 1 Yes 16-byte No N/A
1 0 Yes 32-byte No N/A
1 1 Yes 64-byte No N/A

Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and
“Word Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte section
within any page. To exit the “Wrap Around” function and return to normal read operation, another Set
Burst with Wrap instruction should be issued to set W4 = 1. The default value of W4 upon power on or
after a software/hardware reset is 1.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 3
CLK
Mode 0 Mode 0
don,t don,t don,t Wrap Bit
Instruction (77h)
care care care
IO0 x
x x x x x w4 x

IO 1 x x x x x x w5 x

x x x x x x w6 x
IO2

IO3 x x x x x x x x

Figure 17. Set Burst with Wrap Instruction (SPI Mode only)

This Data Sheet may be revised by subsequent versions 41 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.14 Page Program (02h)

The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at
previously erased (FFh) memory locations. A Write Enable instruction must be executed before the
device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by
driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at
least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction
while data is being sent to the device. The Page Program instruction sequence is shown in Figure 18.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits)
should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page
length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial
page) can be programmed without having any effect on other bytes within the same page. One condition to
perform a partial page program is that the number of clocks cannot exceed the remaining page length. If
more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and
overwrite previously sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte
has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven
high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC
Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may still
be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle
and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again.
After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is
cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the
Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits.

/CS
Mode 3 0 1 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
CLK Mode 0

Instruction (02h) 24-Bit Address Data Byte 1

DI
23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
(IO0)
*=MSB * *
/CS
2072
2073
2074
2075
2076
2077
2078
2079

39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Mode 3
CLK Mode 0

Data Byte 2 Data Byte 3 Data Byte 256

DI 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
(IO0)
* * *
Figure 18a. Page Program Instruction (SPI Mode)

This Data Sheet may be revised by subsequent versions 42 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

/CS

516

519
518
517
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Mode 3

CLK Mode 0 Mode 0

Inst ructi on
A23-16 A15-8 A7-0 B yt e 1 B yt e 2 B yt e 3 B yt e 255 B yt e 255
02h .l
IO0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 0

IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1

IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2

IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 3

Figure 18b. Page Program Instruction (QPI Mode)

This Data Sheet may be revised by subsequent versions 43 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.15 Quad Input Page Program (32h)

The Quad Input Page Program instruction allows up to 256 bytes of data to be programmed at
previously erased (FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Input
Page Program can improve performance for PROM Programmer and applications that have slow clock
speeds <5MHz. Systems with faster clock speed will not realize much benefit for the Quad Input
Page Program instruction since the inherent page program time is much greater than the time it take to
clock-in the data.
To use Quad Input Page Program the Quad Enable (QE) bit in Status Register-2 must be set to 1. A
Write Enable instruction must be executed before the device will accept the Quad Input Page Program
instruction (Status Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then
shifting the instruction code “32h” followed by a 24-bit address (A23-A0) and at least one data byte, into
the IO pins. The /CS pin must be held low for the entire length of the instruction while data is being
sent to the device. All other functions of Quad Input Page Program are identical to standard Page
Program. The Quad Input Page Program instruction sequence is shown in Figure 19.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
/CLK
Mode 0
Instruction (32h) 24-Bite Address

IO 0 23 22 21 3 2 1 0
*

IO1
IO2

IO 3
* =MSB
/CS

Mode 3
537

539

541

543
536

538

540

542

31 32 33 34 35 36 37
CLK Mode 0
Byte Byt e Byt e Byte
Byte 1 Byte 2 Byte 3 253 254 255 256

IO0 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0

IO1 5 1 5 1 5 1 5 1 5 1 5 1 5 1

IO 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2

IO3 7 3 7 3 7 3 7 3 7 3 7 3 7 3
* * * * * * *

Figure 19. Quad Input Page Program Instruction (SPI Mode only)

This Data Sheet may be revised by subsequent versions 44 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.16 Quad Page Program (33h)

The Quad Page Program (33h) instruction is similar to the Quad Input Page Program (32h) instruction
except that address and data bits are both input and output through four pins IO0, IO1, IO2 and IO3. The
Quad Page Program can improve performance for PROM Programmer and applications that have slow
clock speeds <5MHz. Systems with faster clock speed will not realize much benefit for the Quad
Page Program instruction since the inherent page program time is much greater than the time it take to
clock-in the data. To use Quad Page Program the Quad Enable (QE) bit in Status Register-2 must be
set to 1. The Quad Page Program instruction sequence is shown in Figure 20.

/CS

Mode 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13

Mode 0
CLK
Instruction (33h)
A23-16 A15-8 A7-0
IO 0 20 16 12 8 4 0

IO1 21 17 13 9 5 1

IO 2 22 17 14 10 6 2

IO3 23 18 15 11 7 3
* * *
/CS
13 14 15 16 17 18 19 518 519 520 521 522 523 524 525
CLK
Byte Byte Byte Byte
Byte 1 Byte 2 Byte 3
253 254 255 256
IO0 4 0 4 0 4 0 4 0 4 0 4 0 4 0

IO1 5 1 5 1 5 1 5 1 5 1 5 1 5 1

IO2 6 2 6 2 6 2 6 2 6 2 6 2 6 2

IO 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3

* * * * * * *

Figure 20. Quad Page Program Instruction (SPI Mode only)

This Data Sheet may be revised by subsequent versions 45 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.17 Sector Erase (20h)

The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of
all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0). The Sector Erase
instruction sequence is shown in Figure 21a & 21b.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done
the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase
instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Sector Erase cycle has
finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase
instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB,
BP2, BP1, and BP0) bits.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 Mode 3
Mode 0 Mode 0
CLK
Instruction (20h) 24-Bit Address

DI 23 22 2 1 0
(IO0)
High Impedance *
DO
(IO1)
*=MSB
Figure 21a. Sector Erase Instruction (SPI Mode)
/CS

Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Inst ructi on
A23-16 A15-8 A7-0
20h

IO0 20 16 12 8 4 0

21 17 13 9 5 1
IO1

22 18 14 10 6 2
IO2

23 19 15 11 7 3
IO3

Figure 21b. Sector Erase Instruction (QPI Mode)

This Data Sheet may be revised by subsequent versions 46 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.18 32KB Block Erase (52h)

The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of
all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “52h” followed a 24-bit block address (A23-A0). The Block Erase
instruction sequence is shown in Figure 22a & 22b.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done
the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase
instruction will commence for a time duration of tBE1 (See AC Characteristics). While the Block Erase
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Block Erase cycle has
finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase
instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB,
BP2, BP1, and BP0) bits.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 Mode 3
Mode 0 Mode 0
CLK
Instruction (52h) 24-Bit Address

DI
23 22 2 1 0
(IO0)

High Impedance
*
DI
(IO1)
* = MSB
Figure 22a. 32KB Block Erase Instruction (SPI Mode)

/CS

Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Inst ructi on
A23-16 A15-8 A7-0
52h
IO0
20 16 12 8 4 0

IO1 21 17 13 9 5 1

IO2 22 18 14 10 6 2

IO3 23 19 15 11 7 3

Figure 22b. 32KB Block Erase Instruction (QPI Mode)

This Data Sheet may be revised by subsequent versions 47 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
7.2.19 64KB Block Erase (D8h)
The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of
all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0). The Block Erase
instruction sequence is shown in Figure 23a & 23b.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done
the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase
instruction will commence for a time duration of tBE (See AC Characteristics). While the Block Erase
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Block Erase cycle has
finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase
instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB,
BP2, BP1, and BP0) bits.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 Mode 3
CLK Mode 0 Mode 0
Inst ructi on (D8h) 24-B it Addres s

DI 23 22 2 1 0
(IO0)
*
DO High I mpedanc e

(IO1)
* =MSB

Figure 23a. 64KB Block Erase Instruction (SPI Mode)

/CS

Mode 3 0 1 2 3 4 5 6 7 Mode 3

CLK Mode 0 Mode 0

Ins t ruc ti on
A23-16 A15-8 A7-0
D8h

IO0 20 16 12 8 4 0

IO1 21 17 13 9 5 1

IO2 22 18 14 10 6 2

IO3 23 19 15 11 7 3

Figure 23b. 64KB Block Erase Instruction (QPI Mode)

This Data Sheet may be revised by subsequent versions 48 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.20 Chip Erase (C7h / 60h)

The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 24.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will
commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY
bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is
ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any
memory region is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits.

/CS

Mode 3 0 1 Mode 3
/CS CLK Mode 0 Mode 0
Inst ructi on
(C7h/60h)
Mode 3 0 1 2 3 4 5 6 7 Mode 3
IO0
CLK Mode 0 Mode 0

Instruction (C7h/60h)
IO 1
DI
(IO0)
IO2
DO High Impedance
(IO1)
IO3

Figure 24. Chip Erase Instruction for SPI Mode (left) or QPI Mode (right)

This Data Sheet may be revised by subsequent versions 49 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.21 Erase / Program Suspend (75h)

The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase
operation or a Page Program operation and then read from any other sectors or blocks. The
Erase/Program Suspend instruction sequence is shown in Figure 25a & 25b.

The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h,42h)
are not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block
erase operation. If written during the Chip Erase operation, the Erase Suspend instruction is
ignored. The Write Status Register instructions (01h, 31h, 11h) and Erase instructions(20h, 52h, D8h,
C7h, 60h, 44h) and Program instructions (02h, 32h, 42h) are not allowed during Program Suspend.
Program Suspend is valid only during the Page Program or Quad Page Program operation.

The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in the
Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page
Program operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend
instruction will be ignored by the device. A maximum of time of “tSUS” (See AC Characteristics) is
required to suspend the erase or program operation. The BUSY bit in the Status Register will be cleared
from 1 to 0 within “tSUS” and the SUS bit in the Status Register will be set from 0 to 1 immediately after
Erase/Program Suspend. For a previously resumed Erase/Program operation, it is also required that the
Suspend instruction “75h” is not issued earlier than a minimum of time of “tSUS” following the preceding
Resume instruction “7Ah”.

Unexpected power off during the Erase/Program suspend state will reset the device and release the
suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or
block that was being suspended may become corrupted. It is recommended for the user to implement
system design techniques against the accidental power interruption and preserve data integrity during
erase/program suspend state.

/CS

tSUS
Mode 3 0 1 4 5 6 Mode 3
2 3 7
CLK Mode 0 Mode 0

Instruction (75h)

DO
(IO0)

DO High Impedance
(IO1) Accept
instructions

Figure 25a. Erase/Program Suspend Instruction (SPI Mode)

This Data Sheet may be revised by subsequent versions 50 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

/CS
tSUS
Mode 3 0 1 Mode 3
CLK Mode 0 Mode 0
Instruction
75h
IO0

IO1

IO2

IO3
Accept
instructions

Figure 25b. Erase/Program Suspend Instruction (QPI Mode)

This Data Sheet may be revised by subsequent versions 51 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.22 Erase / Program Resume (7Ah)

The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase
operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction
“7Ah” will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY
bit equals to 0. After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set
from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will
complete the program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume
instruction “7Ah” will be ignored by the device. The Erase/Program Resume instruction sequence is
shown in Figure 26a & 26b.

Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by
unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to
be issued within a minimum of time of “tERS” following a previous Resume instruction.

/CS

Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Instruction (7Ah)
DI
(IO0)

Resume previously
suspended Program or
Erase

Figure 26a. Erase/Program Resume Instruction (SPI Mode)

/CS

Mode 3 0 1 Mode 3
CLK Mode 0 Mode 0
Instruction
7Ah
IO0

IO1

IO 2

IO3

Resume previously
suspended Program or
Erase

Figure 26b. Erase/Program Resume Instruction (QPI Mode)

This Data Sheet may be revised by subsequent versions 52 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.23 Power-down (B9h)

Although the standby current during normal operation is relatively low, standby current can be further
reduced with the Power-down instruction. The lower power consumption makes the Power-down
instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC
Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code
“B9h” as shown in Figure 27a & 27b.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down
instruction will not be executed. After /CS is driven high, the power-down state will entered within the
time duration of tDP (See AC Characteristics). While in the power-down state only the Release Power-
down / Device ID (ABh) instruction, which restores the device to normal operation, will be recognized. All
other instructions are forbidden. This includes the Read Status Register instruction, which is
always available during normal operation. Forbid all but one instruction makes the Power Down state a
useful condition for securing maximum write protection. The device always powers-up in the normal
operation with the standby current of ICC1.

/CS
tDP
Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Instruction (B9h)
DI
(IO0)

Stand-by Mode Power-down Mode

Figure 27a. Deep Power-down Instruction (SPI Mode)

/CS

tDP
Mode 3 0 1 Mode 3
CLK Mode 0 Mode 0
Instruction
B9h
IO 0

IO1

IO2

IO 3

Stand-by Mode Power-down Mode

Figure 27b. Deep Power-down Instruction (QPI Mode)

This Data Sheet may be revised by subsequent versions 53 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.24 Release Power-down / Device ID (ABh)

The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to
release the device from the power-down state, or obtain the devices electronic identification (ID)
number.
To release the device from the power-down state, the instruction is issued by driving the /CS pin low,
shifting the instruction code “ABh” and driving /CS high as shown in Figure 28a & 28b. Release from
power-down will take the time duration of tRES1 (See AC Characteristics) before the device will resume
normal operation and other instructions are accepted. The /CS pin must remain high during the tRES1
time duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by
driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device
ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first. The Device ID
value for the XM25QH32C is listed in Manufacturer and Device Identification table. The Device ID
can be read continuously. The instruction is completed by driving /CS high.
When used to release the device from the power-down state and obtain the Device ID, the instruction is
the same as previously described, and shown in Figure 28c & 28d, except that after /CS is driven high it
must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the
device will resume normal operation and other instructions will be accepted. If the Release from Power-
down / Device ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY
equals 1) the instruction is ignored and will not have any effects on the current cycle.

/CS
tRES1
Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Instruction (ABh)
DI
(IO0)

Power-down Mode Stand-by Mode

Figure 28a. Release Power-down Instruction (SPI Mode)

This Data Sheet may be revised by subsequent versions 54 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

/CS
tRES1
Mode 3 0 1 Mode 3
CLK Mode 0 Mode 0
Instruction
ABh
IO0

IO1

IO2

IO3

Power-down Mode Stand-by Mode

Figure 28b. Release Power-down Instruction (QPI Mode)

/CS
Mode 3 Mode 3
0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38
CLK Mode 0 Mode 0
Instruction (ABh) 3 Dummy Bytes tRES2
DI
23 22 2 1 0
(IO 0)
* Device ID
DO High Impedance
7 6 5 4 3 2 1 0
(IO 1)
*

* = MSB Power-down Mode Stand-by Mode

Figure 28c. Release Power-down / Device ID Instruction (SPI Mode)

/CS
tRES2
Mode 3 0 1 2 3 4 5 6 7 8 Mode 3
CLK Mode 0 Mode 0
Instruction IOs switch from
3 Dummy Bytes
ABh Input to Output
IO0
4 0

IO1
5 1

IO2 6 2

IO3 7 3
Device ID

Power-down Mode Stand-by Mode

Figure 28d. Release Power-down / Device ID Instruction (QPI Mode)

This Data Sheet may be revised by subsequent versions 55 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
7.2.25 Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID.

The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device
ID instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code
“90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for XMC
(20h) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as
shown in Figure 29. The Device ID values for the XM25QH32C are listed in Manufacturer and Device
Identification table. The instruction is completed by driving /CS high.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK Mode 0
Instruction（90h） Address （000000h)
DI
23 22 21 3 2 1 0
(IO0)
*
High Impedance
DO
(IO1)
* =MSB

/CS

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Mode 3

CLK Mode 0

DI
(IO0) 0

Capacity ID7-0
DO
(IO1) 7 6 5 4 3 2 1 0
*
Manufacturer ID(20h) Device ID

Figure 29. Read Manufacturer / Device ID Instruction (SPI Mode)

This Data Sheet may be revised by subsequent versions 56 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.26 Read Manufacturer / Device ID Dual I/O (92h)

The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID
at 2x speed.
The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “92h” followed by a
24-bit address (A23-A0) of 000000h, but with the capability to input the Address bits two bits per clock.
After which, the Manufacturer ID for XMC (20h) and the Device ID are shifted out 2 bits per clock on the
falling edge of CLK with most significant bits (MSB) first as shown in Figure 30. The Device ID values for
the XM25QH32C are listed in Manufacturer and Device Identification table. The Manufacturer and
Device IDs can be read continuously, alternating from one to the other. The instruction is completed by
driving /CS high.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
Mode 0
Instruction (92h) A23-16 A15-8 A7-0(00h) M7-0

DI
( IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

DI High Impedance
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
( IO1)

=MSB * * * *
*

/CS
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Mode 3
CLK Mode 0
IOs switch from
Input to Output
DI
0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
( IO0)

DI 1 5 3 1 7 5 3 1 7 3 7 3
7 5 1 5 1
( IO1)
* MFR ID
* Device ID
* MFR * Device
ID(repeat) ID(repeat)

Figure 30. Read Manufacturer / Device ID Dual I/O Instruction (SPI Mode only)

Note:
The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Dual I/O instruction.

This Data Sheet may be revised by subsequent versions 57 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.27 Read Manufacturer / Device ID Quad I/O (94h)

The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer
/ Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device
ID at 4x speed.

The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O
instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code “94h”
followed by a four clock dummy cycles and then a 24-bit address (A23-A0) of 000000h, but with
the capability to input the Address bits four bits per clock. After which, the Manufacturer ID for XMC
(20h) and the Device ID are shifted out four bits per clock on the falling edge of CLK with most
significant bit (MSB) first as shown in Figure 31. The Device ID values for the XM25QH32C are listed
in Manufacturer and Device Identification table. The Manufacturer and Device IDs can be read
continuously, alternating from one to the other. The instruction is completed by driving /CS high.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
Mode 0
IOs switch from
A7-0 Input to Output
Instruction (94h) A23-16 A15-8 M7-0 Dummy Dummy
(00h)

IO 0 4 0 4 0 4 0 4 0 4 0 4 0

High Impedance 5 1 5 1 5 1 5 1 5 1 5 1
IO 1

High Impedance 6 2 6 2 6 2 6 2 6 2 6 2
IO 2

High Impedance 7 3 7 3 7 3 7 3 7 3 7 3
IO 3

MFR ID Device ID

/CS

23 24 25 26 27 28 29 30 Mode 3
CLK
Mode 0

IO0 0 4 0 4 0 4 0 4 0

IO1 1 5 1 5 1 5 1 5 1

IO2 2 6 2 6 2 6 2 6 2

IO3 3 7 3 7 3 7 3 7 3
MF R I D Devi ce ID MF R I D Devi ce ID
(repeat) (repeat) (repeat) (repeat)

Figure 31. Read Manufacturer / Device ID Quad I/O Instruction (SPI Mode only)

Note:
The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Quad I/O instruction.

This Data Sheet may be revised by subsequent versions 58 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.28 Read Unique ID Number (4Bh)

The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique
to each XM25QH32C device. The ID number can be used in conjunction with user software methods to
help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the
/CS pin low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks. After
which, the 64-bit ID is shifted out on the falling edge of CLK as shown in Figure 32. (the data will always
be FFh when read after the 64-bit ID).
/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
Mode 0

Instruction (4Bh) Dummy Byte 1 Dummy Byte 2

DI
(IO0)

High Impedance
DI
(IO1)

/CS

101
102
100
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Mode 3
CLK
Mode 0

Dummy Byte 3 Dummy Byte 4

DI
(IO 0)

High Impedance
DI 63 62 61 2 1 0
(IO1)
* 64-bit Unique
*=MSB Serial Number

Figure 32. Read Unique ID Number Instruction (SPI Mode only)

This Data Sheet may be revised by subsequent versions 59 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.29 Read JEDEC ID (9Fh)

For compatibility reasons, the XM25QH32C provides several instructions to electronically determine the
identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI
compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin
low and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID byte for XMC
(20h) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on
the falling edge of CLK with most significant bit (MSB) first as shown in Figure 33a & 33b. For memory
type and capacity values refer to Manufacturer and Device Identification table.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK
Mode 0

Instruction (9Fh)
DI(IO0)

Manufacturer ID
(20h)
High Impedance
DO(IO1)

*=MSB
/CS

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Mode 3
CLK
Mode 0

DI(IO0)
Memory Type
Capacity I D7-0
ID15-8

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
DI(IO1)
* *

Figure 33a. Read JEDEC ID Instruction (SPI Mode)

/CS

Mode 3 0 1 2 3 4 5 6 Mode 3
CLK
Mode 0 Mode 0
Instruction IO switch from
(9Fh) Input to output
IO0 12 8 4 0

IO1 13 9 5 1

IO2 14 10 6 2

IO3 15 11 7 3

(20h) ID15-8 ID7-0

Figure 33b. Read JEDEC ID Instruction (QPI Mode)

This Data Sheet may be revised by subsequent versions 60 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.30 Read SFDP Register (5Ah)

The XM25QH32C features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that
contains information about device configurations, available instructions and other features. The SFDP
parameters are stored in one or more Parameter Identification (PID) tables. Currently only one PID
table is specified, but more may be added in the future. The Read SFDP Register instruction is
compatible with the SFDP standard initially established in 2010 for PC and other applications, as well as
the JEDEC standard JESD216 that is published in 2011.

The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction code
“5Ah” followed by a 24-bit address (A23-A0)(1) into the DI pin. Eight “dummy” clocks are also required
before the SFDP register contents are shifted out on the falling edge of the 40th CLK with most
significant bit (MSB) first as shown in Figure 34. The byte address is automatically incremented to
the next byte address after each byte of data is shifted out. The last byte address of the register is
FFh (the data will always be FFh when read after the last address), For SFDP register values and
descriptions, please refer to please refer to the following SFDP Definition Table.

Note 1: A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP Register.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK
Mode 0

Instruction（5Ah） 24-Bit Address

DI
(IO0) 23 22 21 3 2 1 0

DI High Impedance *
(IO1)

/CS

CLK 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Dummy Byte
DI
(IO0) 0 7 6 5 4 3 2 1 0
Date Out 1 Date Out 2
DI High Impedance
(IO1) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

* =MSB * *

Figure 34. Read SFDP Register Instruction Sequence Diagram (Only SPI Mode)

This Data Sheet may be revised by subsequent versions 61 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
Serial Flash Discoverable Parameters (SFDP) Signature and Parameter Identification Data Value
(Advanced Information)
Add (h) DW Add
Description Data Comment
(Byte) (Bit)

00h 07 : 00 53h
01h 15 : 08 46h
SFDP Signature Fixed: 50444653h
02h 23 : 16 44h
03h 31 : 24 50h
SFDP Minor Revision Number 04h 07 : 00 06h Star from 0x00
SFDP Major Revision Number 05h 15 : 08 01h Star from 0x01
This number is 0-based.Therefore,0
Number of Parameter Headers (NPH) 06h 23 : 16 02h
indicates 1 parameter header.
Unused 07h 31 : 24 FFh Reserved
ID Number(JEDEC) 08h 07 : 00 00h 00h:it indicates a JEDEC specified header.
Parameter Table Minor Revision Number 09h 15 : 08 06h Star from 0x00
Parameter Table Major Revision Number 0Ah 23 : 16 01h Star from 0x01
How many DWORDs in the parameter
Parameter Table Length (in double word) 0Bh 31 : 24 10h
table
0Ch 07 : 00 30h
First address of JEDEC Flash Parameter
Parameter Table Pointer (PTP) 0Dh 15 : 08 00h
table
0Eh 23 : 16 00h
Unused 0Fh 31 : 24 FFh
ID number(Manufacturer ID) 10h 07 : 00 20h It indicates manufacture ID
Parameter Table Minor Revision Number 11h 15 : 08 00h Start from 00h
Parameter Table Major Revision Number 12h 23 : 16 01h Start from 01h
How many DWORDs in the parameter
Parameter Table Length(in double word) 13h 31 : 24 04h
table
14h 07 : 00 D0h
First address of VENDOR Flash Parameter
Parameter Table Pointer(PTP) 15h 15 : 08 00h
table
16h 23 : 16 00h
Unused 17h 31 : 24 FFh
ID number (4-byte Address Instruction) 4-byte Address Instruction parameter
18h 07 : 00 84h
ID
Parameter Table Minor Revision Number 19h 15 : 08 00h Start from 00h
Parameter Table Major Revision Number 1Ah 23 : 16 01h Start from 01h
How many DWORDs in the Parameter
Parameter Table Length (in double word) 1Bh 31 : 24 02h
table
1Ch 07 : 00 C0h
First address of 4-byte Address
Parameter Table Pointer (PTP) 1Dh 15 : 08 00h
Instruction table
1Eh 23 : 16 00h
Unused 1Fh 31 : 24 FFh

This Data Sheet may be revised by subsequent versions 62 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

Parameter ID (0) JEDEC Flash Parameter Tables 1/10

Add (h) DW Add
Description Data Comment
(Byte) (Bit)
00:Reserved, 01:4KB erase,
Block / Sector Erase sizes 01 : 00 01b 10:Reserved, 11:not supported 4KB
erase
Write Granularity 02 1b 0:1Byte,1:64Byte or larger
0: Block Protect bits in device's status
register are solely non-volatile or may
be
programmed either as volatile using
Volatile Status Register Block Protect
30h 03 0b the 50h instruction for write enable
bits
or non-volatile using the 06h
instruction for write enable.
1: Block Protect bits in device's status
register are solely volatile.
Write Enable Instruction Select for 0:use 50h instruction
04 0b
Writing to Volatile Status Registers 1:use 06h instruction
Contains 111b and can never be
Unused 07 : 05 111b
changed
4KB Erase Instruction 31h 15 : 08 20h
0 = not supported
(1-1-2) Fast Read(1) 16 1b
1 = supported
Address Bytes Number used in 00:3Byte only, 01:3 or 4Byte
18 : 17 00b
addressing flash array 10:4Byte only, 11:Reserved
0 = not supported
Double Transfer Rate(DTR) clocking 19 0b
1 = supported
32h 0 = not supported
(1-2-2) Fast Read 20 1b
1 = supported
0 = not supported
(1-4-4) Fast Read 21 1b
1 = supported
0 = not supported
(1-1-4) Fast Read 22 1b
1 = supported
Unused 23 1b
Unused 33h 31 : 24 FFh

This Data Sheet may be revised by subsequent versions 63 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

Parameter ID (0) JEDEC Flash Parameter Tables 2/10

Add (h) DW Add
Description Data Comment
(Byte) (Bit)
For densities 2 gigabits or less,
bit-31 is set to 0b. The field 30:0
defines the size in bits.
Example: 00FFFFFFh = 16
megabits
For densities 4 gigabits and
Flash Memory Density 37h : 34h 31 : 00 01FFFFFFh
above, bit-31 is set to 1b. The
field 30:0 defines ‘N’ where the
density is computed as 2^N bits
(N must be >= 32).
Example: 80000021h = 2^33 = 8
gigabits

Parameter ID (0) JEDEC Flash Parameter Tables 3/10

Add (h) DW Add
Description Data Comment
(Byte) (Bit)
(1-4-4)Fast Read number of Wait 00000b:Not supported;00100b:4
04 : 00 00100b
states(2) 00110b:6 01000b:8
38h Mode clocks:
(1-4-4)Fast Read number of Mode
07 : 05 010b 000b:Not supported;010: 2
Clocks(3)
clocks
(1-4-4)Fast Read instruction 39h 15 : 08 EBh
00000b:Not suppoted;00100b:4
(1-1-4)Fast Read Number of Wait states 20 : 16 01000b
00100b:6; 01000b:8
3Ah Mode clocks:
(1-1-4)Fast Read Number of Mode Clocks 23 : 21 000b 000b:Not supported;010b:2
clocks
(1-1-4)Fast Read Instruction 3Bh 31 : 24 6Bh

Parameter ID (0) JEDEC Flash Parameter Tables 4/10

Add (h) DW Add
Description Data Comment
(Byte) (Bit)
00000b:Not supported;00100b:4
(1-1-2)Fast Read Number of Wait states 04 : 00 01000b
00110b:6;01000b:8
3Ch
Mode clocks:
(1-1-2)Fast Read Number of Mode Clocks 07 : 05 000b
000b:Not supported;100:4 clocks
(1-1-2)Fast Read Instruction 3Dh 15 : 08 3Bh

00000b:Not supported;00100b:4
(1-2-2)Fast Read Number of Wait states 20 : 16 00010b
0 0110b:6;01000b:8
3Eh
Mode clocks:
(1-2-2)Fast Read Number of Mode Clocks 23 : 21 010b
000b:Not supported;010:2 clocks
(1-2-2)Fast Read Instruction 3Fh 31 : 24 BBh

This Data Sheet may be revised by subsequent versions 64 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

Parameter ID (0) JEDEC Flash Parameter Tables 5/10

Add (h) DW Add
Description Data Comment
(Byte) (Bit)
0 = not supported
(2-2-2)Fast Read 00 0b
1 = supported
Unused 03 : 01 111b
40h
0 = not supported
(4-4-4)Fast Read 04 1b
1 = supported
Unused 07 : 05 111b
Unused 43h : 41h 31 : 08 FFFFFFh

Parameter ID (0) JEDEC Flash Parameter Tables 6/10

Add (h) DW Add
Description Data Comment
(Byte) (Bit)
Unused 45h : 44h 15 : 00 FFFFh
00000b:Not supported;00100b:4
(2-2-2)Fast Read Number of Wait states 20 : 16 00000b
00110b:6;01000b:8
46h
(2-2-2) Fast Read Number of Mode Mode Clocks:
23 : 21 000b
Clocks 000b:Not supported;010:2 clocks
(2-2-2)Fast Read Instruction 47h 31 : 24 FFh

Parameter ID (0) JEDEC Flash Parameter Tables 7/10

Add (h) DW Add
Description Data Comment
(Byte) (Bit)
Unused 49h : 48h 15 : 00 FFFFh
00000b:Not supported;00100b:4
(4-4-4)Fast Read Number of Wait states 20 : 16 00000b
00110b:6;01000b:8
4Ah
(4-4-4) Fast Read Number of Mode Mode Clocks:
23 : 21 010b
Clocks 000b:Not supported;010:2 clocks
(4-4-4)Fast Read Instruction 4Bh 31 : 24 EBh

Parameter ID (0) JEDEC Flash Parameter Tables 8/10

Add (h) DW Add
Description Data Comment
(Byte) (Bit)
Sector/block size=2N bytes(4)
Erase Type 1 Size 4Ch 07 : 00 0Ch
0Ch:4KB;0Fh:32KB;10h:64KB
Erase Type 1 Erase Instruction 4Dh 15 : 08 20h
Sector/block size=2N bytes
Erase Type 2 Size 4Eh 23 : 16 0Fh
00h:NA;0Fh:32KB;10h:64KB
Erase Type 2 Erase Instruction 4Fh 31 : 24 52h

Parameter ID (0) JEDEC Flash Parameter Tables 9/10

Add (h) DW Add
Description Data Comment
(Byte) (Bit)

This Data Sheet may be revised by subsequent versions 65 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
Sector/block size=2N bytes
Erase Type 3 Size 50h 07 : 00 10h
00h:NA;0Fh:32KB;10h:64KB
Erase Type 3 Erase Instruction 51h 15 : 08 D8h
Sector/block size=2N bytes
Erase Type 4 Size 52h 23 : 16 00h
00h:NA;0Fh:32KB;10h:64KB
Erase Type 4 Erase Instruction 53h 31 : 24 FFh Not support

Parameter ID (0) JEDEC Flash Parameter Tables 9/10

Add (h) DW Add
Description Data Comment
(Byte) (Bit)
Multiplier value: 0h~Fh (0~15)
Multiplier from typical erase time to 03 : 00 0100b
Max. time = 2 * (Multiplier + 1) *
maximum erase time Typical Time
54h 07 : 04
00010b Count value: 00h~1Fh (0~31)
08 Typical Time = (Count + 1) * Units
Erase Type 1 Erase Time
(Typical) Units
10 : 09 01b 00: 1ms, 01: 16ms
55h
10b: 128ms, 11b: 1s
Count value: 00h~1Fh (0~31)
15 : 11 01001b
Typical Time = (Count + 1) * Units
EraseType 2 Erase Time
Units
(Typical)
17 : 16 01b 00: 1ms, 01: 16ms
10b: 128ms, 11b: 1s
56h Count value: 00h~1Fh (0~31)
22 : 18 10010b
Typical Time = (Count + 1) * Units
Erase Type 3 Erase Time
Units
(Typical)
24 : 23 01b 00: 1 ms, 01: 16 ms
10b: 128ms, 11b: 1s
Count value: 00h~1Fh (0~31)
29 : 25 00000b
57h Typical Time = (Count + 1) * Units
Erase Type 4 Erase Time
(Typical) Units
31 : 30 00b 00: 1ms, 01: 16ms
10b: 128 ms, 11b: 1 s

Multiplier value: 0h~Fh (0~15)

Multiplier from typical time to max
03 : 00 0010b Max. time = 2 * (Multiplier + 1)
time for Page or byte program *Typical Time
58h

Page size = 2^N bytes

Page Program Size 07 : 04 1000b
2^8 = 256 bytes, 8h = 1000b
Count value: 00h~1Fh (0~31)
12 : 08 00111b
Typical Time = (Count + 1) * Units
Page Program Time (Typical)
59h Units
13 1b
0: 8us, 1: 64us
15 : 14 Count value: 0h~Fh (0~15)
1110b
Byte Program Time, First Byte 17 : 16 Typical Time = (Count + 1) * Units
(Typical) 5Ah Units
18 0b
0: 1us, 1: 8us
This Data Sheet may be revised by subsequent versions 66 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
Count value: 0h~Fh (0~15)
22 : 19 0001b
Byte Program Time, Additional Byte Typical Time = (Count + 1) * Units
(Typical) Units
23 0b
0: 1us, 1: 8us
Count value: 00h~1Fh (0~31)
28 : 24 00100b
Typical Time = (Count + 1) * Units
Chip Erase Time
(Typical) 5Bh Units
30 : 29 10b 00: 16ms, 01: 256ms
10: 4s, 11: 64s
Reserved 31 1b Reserved
xxx0b: May not initiate a new
erase anywhere (erase nesting not
permitted)
xxx1b: May not initiate a new
erase in the program suspended
page size
xx0xb: May not initiate a new page
program anywhere (program
nesting not permitted)
Prohibited Operations During Program xx1xb: May not initiate a new page
03 : 00 1100b program in the program suspended
Suspend page size
x0xxb: Refer to vendor datasheet
for read restrictions
x1xxb: May not initiate a read in
the program suspended page size
0xxxb: Additional erase or
program restrictions apply
1xxxb: The erase and program
restrictions in bits 1:0 are sufficient

5Ch
xxx0b: May not initiate a new
erase anywhere (erase nesting not
permitted)
xxx1b: May not initiate a new
erase in the erase suspended
erase type size
xx0xb: May not initiate a page
program anywhere
xx1xb: May not initiate a page
Prohibited Operations During Erase program in the erase suspended
07 : 04 1100b
Suspend erase type size
x0xxb: Refer to vendor datasheet
for read restrictions
x1xxb: May not initiate a read in
the erase suspended erase type
size
0xxxb: Additional erase or
program restrictions apply
1xxxb: The erase and program
restrictions in bits 5:4 are sufficient

This Data Sheet may be revised by subsequent versions 67 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
Reserved 08 1b Reserved
Program Resume to Suspend Interval Count value: 0h~Fh (0~15)
5Dh 12 : 09 0000b
(Typical) Typical Time = (Count + 1) * 64us
15: 13 Count value: 00h~1Fh (0~31)
10101b Maximum Time = (Count + 1) *
17 : 16 Units
Program Suspend Latency (Max.)
Units
5Eh 19 : 18 01b 00: 128ns, 01: 1us
10: 8us, 11: 64us
Erase Resume to Suspend Interval Count value: 0h~Fh (0~15)
23 : 20 1111b
(Typical) Typical Time = (Count + 1) * 64us
Count value: 00h~1Fh (0~31)
28 : 24 10101b Maximum Time = (Count + 1) *
Erase Suspend Latency (Max.) Units
5Fh Units
30 : 29 01b 00: 128ns, 01: 1us
10: 8us, 11: 64us
Suspend / Resume supported 31 0b 0= Support 1= Not supported
Program Resume Instruction 60h 07 : 00 7Ah Instruction to Resume a Program
Program Suspend Instruction 61h 15 : 08 75h Instruction to Suspend a Program
Erase Resume Instruction 62h 23 : 16 7Ah Instruction to Resume Write/Erase
Erase Suspend Instruction 63h 31 : 24 75h Instruction to Suspend Write/Erase
Reserved 01 : 00 11b Reserved: 11b

Bit 2: Read WIP bit [0] by 05h

Read instruction
64h Bit 3: Read bit 7 of Status Register
Status Register Polling Device Busy 07 : 02 111101b
by 70h Read instruction (0=not
supported 1=support)
Bit 07:04,Reserved: 1111b

Count value: 00h~1Fh (0~31)

12 : 08 00010b Maximum Time = (Count + 1) *
Units
Release from Deep Power-down (RDP)
Delay (Max.) 65h Units
14 : 13 01b 00: 128ns, 01: 1us
10: 8us, 11: 64us

15 Instruction to Exit Deep Power

Release from Deep Power-down (RDP)
10101011b Down
Instruction 22 : 16 FFh: Don't need command
66h
23
Instruction to Enter Deep Power
Enter Deep Power Down Instruction 10111001b
Down
30 : 24
67h
Deep Power Down Supported 31 0b 0: Supported 1: Not supported

This Data Sheet may be revised by subsequent versions 68 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
Methods to exit 4-4-4 mode
xxx1b: issue FFh instruction
xx1xb: issue F5h instruction
4-4-4 Mode Disable Sequences 03 : 00 1001b x1xxb: device uses a read-modify-
68h
write sequence of operations
1xxxb: issue the Soft Reset 66/99
sequence
07 : 04 Methods to enter 4-4-4 mode
x_xxx1b: set QE per QER
description above, then issue
4-4-4 Mode Enable Sequences 00001b
08 instruction 38h
x_xx1xb: issue instruction 38h
x_x1xxb: issue instruction 35h
Performance Enhance Mode,
0-4-4 Mode Supported 09 1b Continuous Read, Execute in Place
0: Not supported 1: Supported
xx_xxx1b: Mode Bits[7:0] = 00h
will terminate this mode at the end
69h of the current read operation.
xx_xx1xb: If 3-Byte address
active, input Fh on DQ0-DQ3 for 8
clocks. If 4-Byte address active,
input Fh on DQ0-DQ3 for 10
0-4-4 Mode Exit Method 15 : 10 111101b
clocks.
xx_x1xxb: Reserved
xx_1xxxb: Input Fh (mode bit
reset) on DQ0-DQ3 for 8 clocks.
x1_xxxxb: Mode Bit[7:0]≠Axh
1x_xxxxb: Reserved

xxx1b: Mode Bits[7:0] = A5h Note:

QE must be set prior to using this
0-4-4 Mode Entry Method 19 : 16 1101h mode
x1xxb: Mode Bit[7:0]=Axh
1xxxb: Reserved

000b: No QE bit. Detects 1-1-4/1-

6Ah 4- 4 reads based on instruction
001b: QE is bit 1 of status register 2.
Quad Enable (QE) bit Requirements 22 : 20 100b 010b: QE is bit 6 of Status
Register. where 1=Quad Enable or
0=not Quad Enable
111b: Not Supported

HOLD and RESET Disable by bit 4 of Ext. 0: Not supported

23 0b
Configuration Register

Reserved 6Bh 31 : 24 FFh Reserved

This Data Sheet may be revised by subsequent versions 69 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

xxx_xxx1b: Non-Volatile Status

Register 1, powers-up to last
written value, use instruction 06h to
enable write
xxx_1xxxb: Non-Volatile/Volatile
status register 1 powers-up to last
written value in the nonvolatile
status register, use instruction 06h
to enable write to non-volatile
status register. Volatile status
Volatile or Non-Volatile Register and register may be activated after
Write Enable Instruction for Status 06 : 00 1101001b power-up to override the
Register 1 non-volatile status register, use
instruction 50h to enable write and
activate the
volatile status register.
6Ch xx1_xxxxb: Status Register 1
contains a mix of volatile and non-
volatile bits. The 06h
instruction is used to enable writing
of the register.
x1x_xxxxb: Reserved
1xx_xxxxb: Reserved

Reserved 07 1b Reserved

Return the device to its default

power-on state
Soft Reset and Rescue Sequence
13 : 08 010000b Exit 4-Byte Addressing
Support
6Dh issue reset enable instruction 66h,
then issue reset instruction 99h.

xx_xxxx_xxx1b: issue instruction

Exit 4-Byte Addressing 15 : 14 00b
E9h to exit 4-Byte address mode

This Data Sheet may be revised by subsequent versions 70 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
(write enable instruction 06h is not
required)
xx_xxxx_x1xxb: 8-bit volatile
extended address register used to
define A[31:A24] bits. Read with
instruction C8h. Write instruction is
C5h, data length is 1 byte. Return
to lowest memory segment by
setting A[31:24] to 00h and use 3-
6Eh 23 : 16 11000000b
Byte addressing.
xx_xx1x_xxxxb: Hardware reset
xx_x1xx_xxxxb: Software reset
(see bits 13:8 in this DWORD)
xx_1xxx_xxxxb: Power cycle
x1_xxxx_xxxxb: Reserved
1x_xxxx_xxxxb: Reserved

xxxx_xxx1b: issue instruction B7h

(preceding write enable not
required)
xxxx_x1xxb: 8-bit volatile
extended address register used to
define A[31:24] bits. Read with
instruction C8h. Write instruction is
C5h with 1 byte of data. Select the
Enter 4-Byte Addressing 6Fh 31 : 24 10000000b active 128 Mbit memory segment
by setting the appropriate A[31:24]
bits and use 3-Byte addressing.
xx1x_xxxxb: Supports dedicated
4-Byte address instruction set.
Consult vendor data sheet for the
instruction set definition.
1xxx_xxxxb: Reserved

Parameter ID (1) 4-Byte Instruction Tables

Add (h) DW Add
Description Data Comment
(Byte) (Bit)
Support for (1-1-1) READ Command, 0=not supported 1=supported
00 0b
Instruction=13h
Support for (1-1-1) FAST_READ 0=not supported 1=supported
01 0b
Command, Instruction=0Ch
Support for (1-1-2) FAST_READ 0=not supported 1=supported
02 0b
Command, Instruction=3Ch
Support for (1-2-2) FAST_READ C0h 0=not supported 1=supported
03 0b
Command, Instruction=BCh
Support for (1-1-4) FAST_READ 0=not supported 1=supported
04 0b
Command, Instruction=6Ch
Support for (1-4-4) FAST_READ 0=not supported 1=supported
05 0b
Command, Instruction=ECh
Support for (1-1-1) Page Program 0=not supported 1=supported
06 0b
Command, Instruction=12h

This Data Sheet may be revised by subsequent versions 71 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
Support for (1-1-4) Page Program 0=not supported 1=supported
07 0b
Command, Instruction=34h
Support for (1-4-4) Page Program 0=not supported 1=supported
08 0b
Command, Instruction=3Eh
Support for Erase Command – Type 1 0=not supported 1=supported
09 0b
size, Instruction lookup in next Dword
Support for Erase Command – Type 2 0=not supported 1=supported
10 0b
size, Instruction lookup in next Dword
Support for Erase Command – Type 3 0=not supported 1=supported
11 0b
size, Instruction lookup in next Dword
Support for Erase Command – Type 4 0=not supported 1=supported
C1h 12 0b
size, Instruction lookup in next Dword
Support for (1-1-1) DTR_Read 0=not supported 1=supported
13 0b
Command, Instruction=0Eh
Support for (1-2-2) DTR_Read 0=not supported 1=supported
14 0b
Command, Instruction=BEh

Support for (1-4-4) DTR_Read 0=not supported 1=supported

15 0b
Command, Instruction=EEh

Support for volatile individual sector lock 0=not supported 1=supported

16 0b
Read command, Instruction=E0h
Support for volatile individual sector lock 0=not supported 1=supported
17 0b
Write command, Instruction=E1h
Support for non-volatile individual sector C2h 0=not supported 1=supported
18 0b
lock read command, Instruction=E2h
Support for non-volatile individual sector 0=not supported 1=supported
19 0b
lock write command, Instruction=E3h
Reserved 23 : 20 1111b Reserved
Reserved C3h 31 : 24 FFh Reserved
Instruction for Erase Type 1 C4h 07 : 00 FFh FFh=not supported
Instruction for Erase Type 2 C5h 15 : 08 FFh FFh=not supported
Instruction for Erase Type 3 C6h 23 : 16 FFh FFh=not supported
Instruction for Erase Type 4 C7h 31 : 24 FFh FFh=not supported

Parameter ID (2) Flash Parameter Tables

Add (h) DW Add
Description Data Comment
(Byte) (Bit)
07:00 00h 2000h=2.000V
Vcc supply maximum voltage D1h:D0h 2700h=2.700V
15:08 36h
3600h=3.600V
1650h=1.65V
23:16 00h 1750h=1.75V
2250h=2.25V
Vcc supply minimum voltage D3h:D2h 2300h=2.3V
2350h=2.35V
31:24 23h
2650h=2.65V
2700h=2.7V
0 = not supported
H/W Reset# pin D5h:D4h 0 F99Fh
1 = supported
This Data Sheet may be revised by subsequent versions 72 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
0 = not supported
H/W Hold# pin 1
1 = supported
0 = not supported
Deep Power Down Mode 2
1 = supported
0 = not supported
S/W Reset 3
1 = supported
Reset Enable(66h)should be issued
S/W Reset Instruction 11:04
before Reset instruction
0 = not supported
Program suspend/resume 12
1 = supported
0 = not supported
Erase suspend/resume 13
1 = supported
Unused 14
0 = not supported
Wrap-Around Read mode 15
1 = supported
Wrap-Around Read mode instruction D6h 23:16 77h
08h:support 8B wrap-around read
16h:8B&16B
Wrap-Around Read data length D7h 31:24 64h
32h:8B&16B&32B
64h:8B&16B&32B&64B
0 = not supported
Individual block lock 0
1 = supported
Individual block lock
1 0:Volatile 1:Nonvolatile
bit(Volatile/Nonvolatile)
Individual block lock Instruction 09:02
Individual block lock Volatile protect bit
10 0:Protect 1:Unprotect
default protect status
E800h 0 = not supported
Secured OTP DBh:D8h 11
1 = supported
0 = not supported
Read Lock 12
1 = supported
0 = not supported
Permanent Lock 13
1 = supported
Unused 15:14
Unused 31:16 FFFFh
Unused DFh:DCh 31:00 FFFFFFFFh

Note 1: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the
instruction (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-
2),and (4-4-4)
Note 2: Wait States is required dummy clock cycles after the address bits or optional mode clocks.
Note 3: Mode clocks is optional control bits that follow the address bits. These bits are driven by the system
controller
if they are specified. (eg,read performance enhance toggling bits)
Note 4: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 5: All unused and undefined area data is blank FFh.

This Data Sheet may be revised by subsequent versions 73 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.31 Erase Security Registers (44h)

The XM25QH32C offers three 256-byte Security Registers which can be erased and programmed
individually. These registers may be used by the system manufacturers to store security and other
important information separately from the main memory array.
The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable
instruction must be executed before the device will accept the Erase Security Register Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and
shifting the instruction code “44h” followed by a 24-bit address (A23-A0) to erase one of the three
security registers.

ADDRESS A23-16 A15-12 A11-8 A7-0

Security Register #1 00h 0001 0000 Don’t Care
Security Register #2 00h 0010 0000 Don’t Care
Security Register #3 00h 0011 0000 Don’t Care

The Erase Security Register instruction sequence is shown in Figure 35. The /CS pin must be driven
high after the eighth bit of the last byte has been latched. If this is not done the instruction will not be
executed. After /CS is driven high, the self-timed Erase Security Register operation will commence for a
time duration of tSE (See AC Characteristics). While the Erase Security Register cycle is in progress,
the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The
BUSY bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is
ready to accept other instructions again. After the Erase Security Register cycle has finished the Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Security Register Lock Bits (LB3-1) in
the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the
corresponding security register will be permanently locked, Erase Security Register instruction to that
register will be ignored (Refer to section 6.1.9 for detail descriptions).

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 Mode 3
CLK Mode 0 Mode 0
Instruction（44h） 24-Bit Address
DI
23 22 2 1 0
(IO0)
*
DI High Impedance
(IO1)
* =MSB

Figure 35. Erase Security Registers Instruction (SPI Mode only)

This Data Sheet may be revised by subsequent versions 74 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.32 Program Security Registers (42h)

The Program Security Register instruction is similar to the Page Program instruction. It allows from one
byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory
locations. A Write Enable instruction must be executed before the device will accept the Program
Security Register Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS
pin low then shifting the instruction code “42h” followed by a 24-bit address (A23-A0) and at least one
data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while data
is being sent to the device.

ADDRESS A23-16 A15-12 A11-8 A7-0

Security Register #1 00h 0001 0000 Byte Address
Security Register #2 00h 0010 0000 Byte Address
Security Register #3 00h 0011 0000 Byte Address

The Program Security Register instruction sequence is shown in Figure 36. The Security Register Lock
Bits (LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit
is set to 1, the corresponding security register will be permanently locked, Program Security Register
instruction to that register will be ignored (See 6.1.9 for detail descriptions).

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
CLK Mode 0
Instruction (42h) 24-Bit Address Data Byt e 1
DI
23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
(IO0)
* *
* =MSB

/CS
2073

2075
2076

2078
2079
2072

2074

2077

39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Mode 3
CLK Mode 0
Data Byte 2 Data Byte 3 Data Byte 256

DI
0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
(IO0)
* * *
Figure 36. Program Security Registers Instruction (SPI Mode only)

This Data Sheet may be revised by subsequent versions 75 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.33 Read Security Registers (48h)

The Read Security Register instruction is similar to the Fast Read instruction and allows one or more
data bytes to be sequentially read from one of the three security registers. The instruction is initiated by
driving the /CS pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0)
and eight “dummy” clocks into the DI pin. The code and address bits are latched on the rising edge of
the CLK pin. After the address is received, the data byte of the addressed memory location will be
shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte
address is automatically incremented to the next byte address after each byte of data is shifted out.
Once the byte address reaches the last byte of the register (byte address FFh), it will reset to address
00h, the first byte of the register, and continue to increment. The instruction is completed by driving /CS
high. The Read Security Register instruction sequence is shown in Figure 37. If a Read Security
Register instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the
instruction is ignored and will not have any effects on the current cycle. The Read Security Register
instruction allows clock rates from D.C. to a maximum of FR (see AC Electrical Characteristics).

ADDRESS A23-16 A15-12 A11-8 A7-0

Security Register #1 00h 0001 0000 Byte Address
Security Register #2 00h 0010 0000 Byte Address
Security Register #3 00h 0011 0000 Byte Address

Note: If the 24-bit address (A23-A0) out of the table, the data of the addressed memory location will always
be FFh.
/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK Mode 0
Instruction (48h) 24-Bit Address
DI
23 22 21 3 2 1 0
(IO0)
*
DO High Impedance
(IO1)
* =MSB

/CS

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
Dummy Byte
DI 0 7 6 5 4 3 2 1 0
(IO0)
Data Out 1 Data Out 2
DO High Impedance
(IO1) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
* *

Figure 37. Read Security Registers Instruction (SPI Mode only)

This Data Sheet may be revised by subsequent versions 76 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.34 Set Read Parameters (C0h)

In QPI mode, to accommodate a wide range of applications with different needs for either maximum read
frequency or minimum data access latency, “Set Read Parameters (C0h)” instruction can be used to
configure the number of dummy clocks for “Fast Read (0Bh)”, “Fast Read Quad I/O (EBh)” & “Burst Read
with Wrap (0Ch)” instructions, and to configure the number of bytes of “Wrap Length” for the “Burst Read
with Wrap (0Ch)” instruction.
In Standard SPI mode, the “Set Read Parameters (C0h)” instruction is not accepted. The dummy clocks
for various Fast Read instructions in Standard/Dual/Quad SPI mode are fixed, please refer to the
Instruction Table 1-2 for details. The “Wrap Length” is set by W5-4 bit in the “Set Burst with Wrap (77h)”
instruction. This setting will remain unchanged when the device is switched from Standard SPI mode to
QPI mode.
The default “Wrap Length” after a power up or a Reset instruction is 8 bytes, the default number of
dummy clocks is 2. The number of dummy clocks is only programmable for “Fast Read (0Bh)”, “Fast
Read Quad I/O (EBh)” & “Burst Read with Wrap (0Ch)” instructions in the QPI mode. Whenever the
device is switched from SPI mode to QPI mode, the number of dummy clocks should be set again, prior to
any 0Bh, EBh or 0Ch instructions.

DUMMY MAXIMUM WRAP LENGTH

P5 – P4 P1 – P0
CLOCKS READ FREQ.

0 0 2 40MHz 00 8-byte
0 1 4 80MHz 01 16-byte
1 0 6 108MHz 10 32-byte
1 1 8 108MHz 11 64-byte

/CS
Mode 3 0 1 2 3 Mode 3
CLK Mode 0 Mode 0

Inst ructi on
C0h Read
P aram ents

IO0 P4 P0

IO1 P5 P1

IO2 P6 P2

IO3 P7 P3

Figure 38. Set Read Parameters Instruction (QPI Mode only)

This Data Sheet may be revised by subsequent versions 77 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.35 Burst Read with Wrap (0Ch)

The “Burst Read with Wrap (0Ch)” instruction provides an alternative way to perform the read operation
with “Wrap Around” in QPI mode. The instruction is similar to the “Fast Read (0Bh)” instruction in QPI
mode, except the addressing of the read operation will “Wrap Around” to the beginning boundary of the
“Wrap Length” once the ending boundary is reached.
The “Wrap Length” and the number of dummy clocks can be configured by the “Set Read Parameters
(C0h)” instruction.

/CS

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
CLK Mode 0

Inst ructi on IOs switch from

0Ch A23-16 A15-8 A7-0 Dummy*
Input to Output

IO0 20 16 12 8 4 0 4 0 4 0 4

IO 1 21 17 13 9 5 1 5 1 5 1 5

IO2 22 18 14 10 6 2 6 2 6 2 6

IO3 23 19 15 11 7 3 7 3 7 3 7
B yt e 1 B yt e 2 B yt e 3

*＂Set Read Parameters＂instruction (C0h) can

set the number of dummy clocks.

Figure 39. Burst Read with Wrap Instruction (QPI Mode only)

This Data Sheet may be revised by subsequent versions 78 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.36 Enter QPI Mode (38h)

The XM25QH32C support both Standard/Dual/Quad Serial Peripheral Interface (SPI) and Quad
Peripheral Interface (QPI). However, SPI mode and QPI mode cannot be used at the same time. “Enter
QPI (38h)” instruction is the only way to switch the device from SPI mode to QPI mode.

Upon power-up, the default state of the device upon is Standard/Dual/Quad SPI mode. This provides full
backward compatibility with earlier generations of XMC serial flash memories. See Instruction Set Table
1-3 for all supported SPI commands. In order to switch the device to QPI mode, the Quad Enable (QE)
bit in Status Register-2 must be set to 1 first, and an “Enter QPI (38h)” instruction must be issued. If the
Quad Enable (QE) bit is 0, the “Enter QPI (38h)” instruction will be ignored and the device will remain in
SPI mode.

See Instruction Set Table 3 for all the commands supported in QPI mode.

When the device is switched from SPI mode to QPI mode, the existing Write Enable and Program/Erase
Suspend status will remain unchanged, but the Wrap Length setting will reset to default.

/CS

Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Instruction (38h)
DI
(IO0)

DO High Impedance
(IO1)

Figure 40. Enter QPI Instruction (SPI Mode only)

This Data Sheet may be revised by subsequent versions 79 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.37 Exit QPI Mode (FFh)

In order to exit the QPI mode and return to the Standard/Dual/Quad SPI mode, an “Exit QPI (FFh)”
instruction must be issued.

When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch (WEL) and
Program/Erase Suspend status, and the Wrap Length setting will remain unchanged.

/CS

Mode 3 0 1 Mode 3
CLK
Mode 0 Mode 0
Instruction
FFh
IO0

IO1

IO2

IO3

Figure 41. Exit QPI Instruction (QPI Mode only)

This Data Sheet may be revised by subsequent versions 80 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.38 Enable Reset (66h) and Reset Device (99h)

Because of the small package and the limitation on the number of pins, the XM25QH32C provide a
software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted,
any on-going internal operations will be terminated and the device will return to its default power-on
state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch
(WEL) status, Program/Erase Suspend status, Read parameter setting (P7-P0) and Wrap Bit setting
(W6-W4).

“Enable Reset (66h)” and “Reset (99h)” instructions can be issued in either SPI mode or QPI mode. To
avoid accidental reset, both instructions must be issued in sequence. Any other commands other than
“Reset (99h)” after the “Enable Reset (66h)” command will disable the “Reset Enable” state. A new
sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the device. Once the Reset
command is accepted by the device, the device will take approximately tSR=28us to reset. During this
period, no command will be accepted.

Data corruption may happen if there is an on-going or suspended internal Erase or Program operation
when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit
and the SUS bit in Status Register before issuing the Reset command sequence.

/CS

Mode 3 0 1 2 3 4 5 6 7 Mode 3 0 1 2 3 4 5 6 7 Mode 3

CLK Mode 0 Mode 0
Mode 0
Instruction (66h) Instruction (99h)
DI
(IO0)

DO High Impedance
(IO1)

Figure 42a. Enable Reset and Reset Instruction Sequence (SPI Mode)

/CS

Mode 3 0 1 Mode 3 0 1 Mode 3

CLK Mode 0 Mode 0
Mode 0
Instruction Instruction
66h 99h
IO0

IO1

IO2

IO3

Figure 42b. Enable Reset and Reset Instruction Sequence (QPI Mode)

This Data Sheet may be revised by subsequent versions 81 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.39 Ultra-Deep Power-Down(79H)

The Ultra-Deep Power-Down mode allows the device to consume far less power compared to the
standby and Deep Power-Down modes by shutting down additional internal circuitry.
When the device is in the Ultra-Deep Power-Down mode, all commands including the Status Register
Read and Resume from Deep Power-Down commands will be ignored. Since all commands will be
ignored, the mode can be used as an extra protection mechanism against program and erase
operations.
Entering the Ultra-Deep Power-Down mode is accomplished by simply driving /CS low in Deep Power-
Down mode, shifting the instruction code “79h” into the Data Input (DI) pin on the rising edge of CLK,
and then driving /CS high. Any additional data clocked into the device after the instruction will be
ignored. When the /CS pin is high, the device will enter the Ultra-Deep Power-Down mode within the
maximum time of tEUDPD(See AC Characteristics).
The complete instruction code must be clocked in before the /CS pin is driving high, and the /CS pin
must be driving high on an even byte boundary (multiples of eight bits); otherwise, the device will abort
the operation and return to the standby mode once the /CS pin is driving high. In addition, the device
will default to the standby mode after a power cycle.
The Ultra-Deep Power-Down command will be ignored if an internally self-timed operation such as a
program or erase cycle is in progress. The Ultra-Deep Power-Down command must be reissued after
the internally self-timed operation has been completed in order for the device to enter the Ultra-Deep
Power-Down mode.

CS
tEUDPD

0 1 2 3 4 5 6 7

SCK

Instruction

SI 0 1 1 1 1 0 0 1
MS B

SO High-impedance
Active Current

ICC

Deep Power-Down Mode Ultra-Deep Power Down Mode Current

Figure 43. Ultra-Deep Power-Down

This Data Sheet may be revised by subsequent versions 82 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

7.2.40 Exit Ultra-Deep Power-Down

To exit from the Ultra-Deep Power-Down mode, the /CS pin must simply be driving low, waiting the
minimum necessary tCSLU(See AC Characteristics) time, and then driving /CS high. To facilitate
simple software development, a dummy byte can also be entered while the /CS pin is being pulsed just
as in a normal operation like the Program Suspend operation; the dummy byte is simply ignored by the
device in this case. After the /CS pin has been driving high, the device will exit from the Ultra-Deep
Power-Down mode and return to the standby mode within a maximum time of tXUDPD(See AC
Characteristics). If the /CS pin is driving low again before the tXUDPD(See AC Characteristics) time
has elapsed in an attempt to start a new operation, then that operation will be ignored and nothing will
be performed. The system must wait for the device to return to the standby mode before normal
command operations such as Continuous Array Read can be resumed.

CS tCSLU
tXUDPD

High-impedance
SO
Act ive Current

ICC

Ultra-Deep Power Down Mode Current Standby Mode Current

Figure 44. Exit Ultra-Deep Power-Down

This Data Sheet may be revised by subsequent versions 83 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

8. ELECTRICAL CHARACTERISTICS

8.1 Absolute Maximum Ratings (1)(2)

PARAMETERS SYMBOL CONDITIONS RANGE UNIT
Supply Voltage VCC –0.6 to 4.6V V
Voltage Applied to Any Pin VIO Relative to Ground –0.6 to VCC+0.4 V
<20nS Transient –2.0V to
Transient Voltage on any Pin VIOT V
Relative to Ground VCC+2.0
V
Storage Temperature TSTG –65 to +150 °C
Lead Temperature TLEAD (3) See Note (3) °C
Electrostatic Discharge Human Body
VESD(2) –2000 to +2000 V
Voltage Model
Notes:
1.This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not
guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings
may cause permanent damage.
2.JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms).
3.Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on
restrictions on hazardous substances (RoHS) 2002/95/EU.

8.2 Operating Ranges

SPEC
SYMB
PARAMETER CONDITIONS UNIT
OL MIN MAX

Supply Voltage VCC (1) FR = 108MHz, fR = 66MHz 2.3 3.6 V

Industrial –40 +85 °C

Ambient
Temperature,
TA
Operating
Industrial plus –40 +105 °C

Note:
1.VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programming
(erase/write) voltage.

This Data Sheet may be revised by subsequent versions 84 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

8.3 Power-Up Power-Down Timing and Requirements(1)

SPEC
PARAMETER SYMBOL UNIT
MIN MAX
VCC (min) to /CS Low tVSL 1 ms
Write Inhibit Threshold Voltage VWI 1.0 2.1 V
Note:
1. These parameters are characterized only.

VCC(max)

Chip Selection is not allowed

VCC(min)

tVSL Device is fully

accessible

VWI

Time

Figure 45a. Power-up Timing and Voltage Levels

/CS must track VCC

During VCC Ramp Up/Down

VCC

/CS

Time

Figure 45b. Power-up, Power-Down Requirement

This Data Sheet may be revised by subsequent versions 85 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
SPEC
PARAMETER SYMBOL UNIT
MIN MAX
The minimum duration for ensuring tPWD 100 us
initialization will occur
VCC voltage needed to below VPWD for VPWD 0.9 V
ensuring initialization will occur

VCC
Chip select is not acceptable
VCC(max)

VCC(min)

tVSL Device is fully accessible

VPWD(max)

tPWD

Time

Figure 45C. Power-Down Requirement

This Data Sheet may be revised by subsequent versions 86 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

8.4 DC Electrical Characteristics

(-40~85℃)
SPEC
PARAMETER SYMBOL CONDITIONS UNIT
MIN TYP MAX
Input Leakage ILI ±2 µA
I/O Leakage ILO ±2 µA
/CS = VCC,
Standby Current ICC1 15 35 µA
VIN = GND or VCC
/CS = VCC,
Power-down Current ICC2 6 26 µA
VIN = GND or VCC
Ultra Deep /CS = VCC, VIN = VSS or µA
1 2
Power-down VCC
ICC3
Current
CLK = 0.1 VCC / 0.9 VCC mA
at 108MHz, DQ =
7 18
open(1,2,4 I/O)
CLK = 0.1 VCC / 0.9 VCC mA
Operating at 80MHz, DQ =
6 16
Current (Read) (1) ICC4
open(1,2,4 I/O)
CLK = 0.1 VCC / 0.9 VCC mA
4 6
at 33MHz, DQ =
open(1,2,4 I/O)
Operating Current /CS = VCC 6 20 mA
(PP) ICC5

Operating /CS = VCC 2 12 mA

Current (WRSR) ICC6

Operating Current /CS = VCC 4 20 mA

(SE,BE) ICC7

Operating Current /CS = VCC 4 20 mA

(CE) ICC7

Input Low Voltage VIL –0.5 VCC x 0.3 V

Input High Voltage VIH VCC x 0.7 VCC + 0.4 V
Output Low Voltage VOL IOL = 100 µA 0.2 V

Output High Voltage VOH IOH = –100 µA VCC – 0.2 V

Notes:
(1) 0XFF Pattern.

This Data Sheet may be revised by subsequent versions 87 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
(-40~105℃)
SPEC
PARAMETER SYMBOL CONDITIONS UNIT
MIN TYP MAX
Input Leakage ILI ±2 µA
I/O Leakage ILO ±2 µA
/CS = VCC,
Standby Current ICC1 15 35 µA
VIN = GND or VCC
/CS = VCC,
Power-down Current ICC2 6 26 µA
VIN = GND or VCC
Ultra Deep /CS = VCC, VIN = VSS or µA
1 2
Power-down ICC3 VCC
Current
CLK = 0.1 VCC / 0.9 VCC mA
7 18
at 108MHz, DQ =
open(1,2,4 I/O)
CLK = 0.1 VCC / 0.9 VCC mA
Operating at 80MHz, DQ =
6 16
ICC4
Current (Read) (1) open(1,2,4 I/O)
CLK = 0.1 VCC / 0.9 VCC mA
4 6
at 33MHz, DQ =
open(1,2,4 I/O)
Operating Current /CS = VCC 6 20 mA
(PP) ICC5

Operating /CS = VCC 2 12 mA

Current (WRSR) ICC6

Operating Current /CS = VCC 4 20 mA

ICC7
(SE,BE)
Operating Current /CS = VCC 4 20 mA
(CE) ICC7

Input Low Voltage VIL –0.5 VCC x 0.3 V

Input High Voltage VIH VCC x 0.7 VCC + 0.4 V
Output Low Voltage VOL IOL = 100 µA 0.2 V

Output High Voltage VOH IOH = –100 µA VCC – 0.2 V

Notes:
(1) 0XFF Pattern.

This Data Sheet may be revised by subsequent versions 88 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

8.5 AC Measurement Conditions(1)

SPEC
PARAMETER SYMBOL UNIT
MIN MAX
Load Capacitance CL 30 pF
Input Rise and Fall Times TR, TF 5 ns
Input Pulse Voltages VIN 0.1 VCC to 0.9 VCC V
Input Timing Reference Voltages IN 0.2 VCC to 0.8 VCC V
Output Timing Reference Voltages OUT 0.5 VCC to 0.5 VCC V
Note:
1. Output Hi-Z is defined as the point where data out is no longer driven.

Input and Output

Input Levels Timing Reference Levels

0.9 VCC

0.5 VCC

0.1 VCC

Figure 46. AC Measurement I/O Waveform

This Data Sheet may be revised by subsequent versions 89 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

8.6 AC Electrical Characteristics(5)

(-40~85℃)
SPEC
DESCRIPTION SYMBOL ALT UNIT
MIN TYP MAX
Serial Clock Frequency for:
FAST_READ, QPP, PP, SE, HBE, BE, DP, RES,
fc fC1 D.C. 108 MHz
WREN, WRDI, WRSR, RDSR, RDID, Dual Output Fast
Read, Dual I/O Fast Read
Serial Clock Frequency for:
Quad Output, Quad I/O Fast Read, Quad I/O Word fc fC2 D.C. 108 MHz
Read and Burst Read

Clock frequency for Read fR D.C. 66 MHz

Clock High, Low Time tCLH, tCLL(1)

4 ns

Serial Clock Rise Time (Slew Rate) tCLCH(2) 0.1 V/ns

Serial Clock Fall Time (Slew Rate) tCHCL(2) 0.1 V/ns

/CS Active Setup Time relative to CLK tSLCH tCSS 5 ns

/CS Not Active Hold Time relative to CLK tCHSL 5 ns

Data In Setup Time tDVCH tDSU 2 ns

Data In Hold Time tCHDX tDH 3 ns

/CS Active Hold Time relative to CLK tCHSH 5 ns

/CS Not Active Setup Time relative to CLK tSHCH 5 ns

/CS Deselect Time (for Read) tSHSL1 tCSH 7 ns

/CS Deselect Time (for Erase or Program or write) tSHSL2 tCSH 30 ns

Output Disable Time tSHQZ(2) tDIS 6 ns

Clock Low to Output Valid for 30pF tCLQV tV 7 ns

Clock Low to Output Valid for 15pF tCLQV tV 6 ns

Output Hold Time tCLQX tHO 1 ns

/HOLD Active Setup Time relative to CLK tHLCH 5 ns

/HOLD Active Hold Time relative to CLK tCHHH 5 ns

/HOLD Not Active Setup Time relative to CLK tHHCH 5 ns

/HOLD Not Active Hold Time relative to CLK tCHHL 5 ns

Continued – next page AC Electrical Characteristics (cont’d)

This Data Sheet may be revised by subsequent versions 90 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

AC Electrical Characteristics (cont’d)

SPEC
DESCRIPTION SYMBOL ALT UNIT
MIN TYP MAX

/HOLD to Output Low-Z tHHQX(2) tLZ 6 ns

/HOLD to Output High-Z tHLQZ(2) tHZ 6 ns

Write Protect Setup Time Before /CS Low tWHSL(3) 20 ns

Write Protect Hold Time After /CS High tSHWL(3) 100 ns

/CS High to Power-down Mode tDP(2) 3 µs

/CS High to Standby Mode without ID Read tRES1(2) 3 µs

/CS High to Standby Mode with ID Read tRES2(2) 1.8 µs

/CS High to next Instruction after Suspend tSUS(2) 22 µs

Latency Between Resume And Next Suspend tERS(2) 1000 µs

/RESET pin Low period to reset the device tRESET(2)(4) 1 µs

Write Status Register Time tW 1 50 ms

Page Program Time tPP 0.5 3 ms

Sector Erase Time (4KB)

tSE 50 500(2) ms

Block Erase Time (32KB) tBE1 0.15 1.4(2) s

Block Erase Time (64KB) tBE2 0.3 1.8(2) s

Chip Erase Time tCE 20 60(2) s

Software Reset Latency(WIP = write operation) tSR 28 µs

Software Reset Latency(WIP = not in write tSR 0.3 µs
operation)
the maximum time to enter the Ultra-Deep tEUDPD 2 µs
Power-Down mode
/CS low to /CS high time(Exit Ultra-Deep Power- tCSLU 100 ns
Down mode)
/CS high to exit(Exit Ultra-Deep Power-Down tXUDPD 1 ms
mode)
Notes:
1.Clock high + Clock low must be less than or equal to 1/fC.
2.Value guaranteed by design and/or characterization, not 100% tested in production.
3.Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1).
4.It’s possible to reset the device with shorter tRESET (as short as a few hundred ns), a 1us minimum is recommended to ensure
reliable operation.
5.4-bytes address alignment for QPI/Quad Read

This Data Sheet may be revised by subsequent versions 91 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
(-40~105℃)
SPEC
DESCRIPTION SYMBOL ALT UNIT
MIN TYP MAX
Serial Clock Frequency for:
FAST_READ, QPP, PP, SE, HBE, BE, DP, RES,
fc fC1 D.C. 108 MHz
WREN, WRDI, WRSR, RDSR, RDID, Dual Output Fast
Read, Dual I/O Fast Read
Serial Clock Frequency for:
Quad Output, Quad I/O Fast Read, Quad I/O Word fc fC2 D.C. 108 MHz
Read and Burst Read

Clock frequency for Read fR D.C. 66 MHz

Clock High, Low Time tCLH, tCLL(1)

4 ns

Serial Clock Rise Time (Slew Rate) tCLCH(2) 0.1 V/ns

Serial Clock Fall Time (Slew Rate) tCHCL(2) 0.1 V/ns

/CS Active Setup Time relative to CLK tSLCH tCSS 5 ns

/CS Not Active Hold Time relative to CLK tCHSL 5 ns

Data In Setup Time tDVCH tDSU 2 ns

Data In Hold Time tCHDX tDH 3 ns

/CS Active Hold Time relative to CLK tCHSH 5 ns

/CS Not Active Setup Time relative to CLK tSHCH 5 ns

/CS Deselect Time (for Read) tSHSL1 tCSH 7 ns

/CS Deselect Time (for Erase or Program or write) tSHSL2 tCSH 30 ns

Output Disable Time tSHQZ(2) tDIS 6 ns

Clock Low to Output Valid for 30pF tCLQV tV 7 ns

Clock Low to Output Valid for 15pF tCLQV tV 6 ns

Output Hold Time tCLQX tHO 1 ns

/HOLD Active Setup Time relative to CLK tHLCH 5 ns

/HOLD Active Hold Time relative to CLK tCHHH 5 ns

/HOLD Not Active Setup Time relative to CLK tHHCH 5 ns

/HOLD Not Active Hold Time relative to CLK tCHHL 5 ns

Continued – next page AC Electrical Characteristics (cont’d)

This Data Sheet may be revised by subsequent versions 92 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

AC Electrical Characteristics (cont’d)

SPEC
DESCRIPTION SYMBOL ALT UNIT
MIN TYP MAX

/HOLD to Output Low-Z tHHQX(2) tLZ 6 ns

/HOLD to Output High-Z tHLQZ(2) tHZ 6 ns

Write Protect Setup Time Before /CS Low tWHSL(3) 20 ns

Write Protect Hold Time After /CS High tSHWL(3) 100 ns

/CS High to Power-down Mode tDP(2) 3 µs

/CS High to Standby Mode without ID Read tRES1(2) 3 µs

/CS High to Standby Mode with ID Read tRES2(2) 1.8 µs

/CS High to next Instruction after Suspend tSUS(2) 22 µs

Latency Between Resume And Next Suspend tERS(2) 1000 µs

/RESET pin Low period to reset the device tRESET(2)(4) 1 µs

Write Status Register Time tW 1 50 ms

Page Program Time tPP 0.5 5 ms

Sector Erase Time (4KB)

tSE 50 500(2) ms

Block Erase Time (32KB) tBE1 0.15 1.4(2) s

Block Erase Time (64KB) tBE2 0.3 1.8(2) s

Chip Erase Time tCE 20 60(2) s

Software Reset Latency(WIP = write operation) tSR 28 µs

Software Reset Latency(WIP = not in write tSR 0.3 µs
operation)
the maximum time to enter the Ultra-Deep tEUDPD 2 µs
Power-Down mode
/CS low to /CS high time(Exit Ultra-Deep Power- tCSLU 100 ns
Down mode)
/CS high to exit(Exit Ultra-Deep Power-Down tXUDPD 1 ms
mode)
Notes:
1. Clock high + Clock low must be less than or equal to 1/fC.
2.Value guaranteed by design and/or characterization, not 100% tested in production.
3.Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1).
4.It’s possible to reset the device with shorter tRESET (as short as a few hundred ns), a 1us minimum is recommended to ensure
reliable operation.
5.4-bytes address alignment for QPI/Quad Read

This Data Sheet may be revised by subsequent versions 93 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
8.7 Serial Output Timing

/CS

tCLH
CLK

tCLQV tCLQV tCLL tSHQZ

tCLQX tCLQX
IO
output
MSB OUT LSB OUT

8.8 Serial Input Timing

/CS

tSHSL
tCHSL tSLCH tCHS
tSHCH
H
CLK
tCLCH tCHCL
tDVCH tCHDX
IO
input MSB IN LSB IN

8.9 /HOLD Timing

/CS

tCHHL tHLCH tHHCH

CLK

tCHHH
/HOLD

tHLQZ
tHHOX
IO
Output

IO
input

8.10 /WP Timing

/CS

tWHSL tSHWL

/WP

CLK

IO
input
Write Status Register is allowed Write Status Register is not allowed

This Data Sheet may be revised by subsequent versions 94 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

9. PACKAGE SPECIFICATIONS

9.1 SOP 208mil 8L (Package Code H)

R0.006

PIN 1
INDEX R0.007
R0.012
H
PLANE
GAGE

DETAIL A L
θ

0.010
b
D1
E1 DETAIL A
10°(4×)
A2

e
A1
y
E
D C

Note: Both the package length and width do not include the mold flash.

Millimeters Inches
Symbol
Min Nom Max Min Nom Max
A 1.75 1.95 2.16 0.069 0.077 0.085
A1 0.05 0.15 0.25 0.002 0.006 0.010
A2 1.70 1.80 1.91 0.067 0.071 0.075
b 0.33 0.42 0.51 0.013 0.017 0.020
C 0.17 0.21 0.25 0.007 0.008 0.010
D 5.13 5.25 5.38 0.202 0.207 0.212
D1 5.07 5.25 5.38 0.200 0.206 0.212
E 5.13 5.25 5.38 0.202 0.207 0.212
E1 5.12 5.25 5.38 0.202 0.207 0.212
e 1.27 BSC 0.050 BSC
H 7.70 7.90 8.10 0.303 0.311 0.319
L 0.50 0.65 0.80 0.020 0.026 0.031
y --- --- 0.10 --- --- 0.004
θ 0° --- 8° 0° --- 8°

This Data Sheet may be revised by subsequent versions 95 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

9.2 SOP 150mil 8L (Package Code J)

A2 A

PIN 1
INDEX e
A1
E1 E CP

b θ C
L
D

Millimeters Inches
Symbol
Min Nom Max Min Nom Max
A 1.35 1.55 1.75 0.053 0.061 0.069
A1 0.10 0.15 0.25 0.004 0.006 0.010
A2 1.25 1.40 1.55 0.049 0.055 0.061
b 0.31 --- 0.51 0.012 --- 0.020
C 0.17 --- 0.25 0.007 --- 0.010
D 4.80 4.90 5.00 0.189 0.193 0.197
E 6.00 BSC 0.236 BSC
E1 3.80 3.90 4.00 0.150 0.154 0.157
e 1.27 BSC 0.050 BSC
L 0.40 0.82 1.25 0.016 0.032 0.049
CP --- --- 0.10 --- --- 0.004
θ 0° --- 8° 0° --- 8°

Note : Both the package length and width do not include the mold flash.

This Data Sheet may be revised by subsequent versions 96 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

9.3 USON 4x3 8L (Package Code U2)

D D2 0.8 REF

PIN 1
INDEX
E E2

e
b

A3
eee C
A1

Millimeters Inches
Symbol
Min Nom Max Min Nom Max
A 0.50 0.55 0.60 0.020 0.022 0.024
A1 0.00 0.02 0.05 0.000 0.001 0.002
b 0.25 0.30 0.35 0.010 0.012 0.014
A3 --- 0.15 REF --- --- 0.006REF ---
D 4.00 BSC 0.157 BSC
D2 0.70 0.80 0.90 0.028 0.031 0.035
E 3.00 BSC 0.118 BSC
E2 0.10 0.20 0.30 0.004 0.008 0.012
e 0.80BSC 0.031BSC
L 0.55 0.60 0.65 0.022 0.024 0.026
eee 0.00 --- 0.08 0.000 --- 0.003

This Data Sheet may be revised by subsequent versions 97 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

9.4 WSON 5x6 8L (Package Code W)

D D2

PIN 1
INDEX
E E2

e
b

A
A3
eee C
A1

Millimeters Inches
Symbol
Min Nom Max Min Nom Max
A 0.70 0.75 0.80 0.028 0.030 0.031
A1 0.00 0.02 0.05 0.000 0.001 0.002
b 0.35 0.40 0.45 0.014 0.016 0.018
A3 --- 0.203 REF --- --- 0.008 REF ---
D 4.90 5.00 5.10 0.193 0.197 0.201
D2 4.20 4.30 4.40 0.165 0.169 0.173
E 5.90 6.00 6.10 0.232 0.236 0.240
E2 3.30 3.40 3.50 0.130 0.134 0.138
e 1.27 BSC 0.050 BSC
L 0.50 0.60 0.70 0.020 0.024 0.028
eee 0.00 --- 0.08 0.000 --- 0.003

This Data Sheet may be revised by subsequent versions 98 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
Revisions List

Revision NO DESCRIPTION Date

1.0 preliminary version 05/06/2019

1.Modify Page program typical time from 0.7ms to 0.5ms in P5 and P79
2. Modify 32KB Block erase typical time from 120ms to 150ms in P5 and P79
3. Modify 64KB Block erase typical time from 250ms to 300ms in P5 and P79
4. Modify Sector erase max time from 400ms to 700ms in P5 and P79
5. Modify write status register typical time from 10ms to 1ms in P79
6. Modify chip erase typical time from 15s to 20s in P5 and P79
7. Modify the typical value of ICC1 (from 18uA to 15uA) in Table 8.4 DC
Characteristics in P76
8. Modify the typical value of ICC2 (from 10uA to 4.5uA) in Table 8.4 DC
Characteristics in P76
9. Modify the typical value of ICC3 (from 1uA to 0.3uA) in Table 8.4 DC
1.1 Characteristics in P76 07/25/2019
10. Modify the typical value of ICC4 (from 13mA to 7mA(108Mhz))、(from
11mA to 6mA(80Mhz)) in Table 8.4 DC Characteristics in P76
11. Modify the typical value of ICC5 (from 16mA to 6mA) in Table 8.4 DC
Characteristics in P76
12. Modify the typical value of ICC6 (from 8mA to 2mA) in Table 8.4 DC
Characteristics in P76
13. Modify the typical value of ICC7 (from 16mA to 4mA) in Table 8.4 DC
Characteristics in P76
14. Modify Table 8.3 and Figure 45a
15. Modify Operating Temperature from 105°to 85°

1. Modify tSR Max time from 0us to 0.3us in P92

2. Update ORDERING INFORMATION in P6
3. Modify tSUS Max time from 20us to 22us in P92
4.Add SFDP Table in P64
5. Add Operating Temperature 105°
6. Add DC Electrical Characteristics(-40°~105°)
7. Add AC Electrical Characteristics(-40°~105°)
1.2 09/24/2019
8. Modify the max(from 50uA to 35uA) value of ICC1 in Table 8.4 DC
Characteristics in P88
8. Modify the typical(from 4.5uA to 6uA) and max(from 30uA to 26uA) value
of ICC2 in Table 8.4 DC Characteristics in P88
9. Modify the typical(from 0.3uA to 1uA) and max(from 5uA to 2uA) value of
ICC3 in Table 8.4 DC Characteristics in P88
10. Modify chip erase max time from 50s to 60s in P92

1. Modify tSE Max time from 700ms to 500ms in P93&P95.

2. Correct SFDP Table in P64.
1.3 3. Correct Package Specifications from P97 to P100 05/22/2020
4.Add tPWD/ VPWD in P87 and Figure 45C. Power-up, Power-Down
Requirement inP88

1.4 Correct Input Timing Reference Voltages Value in P91 09/25/2020

1.5 Change Tclqx Value From 0ns to 1ns in P92 & P94 03/25/2021

correct the 33h Quad Page Program typo error in Instruction Set Table 2
1.6 01/17/2022
In P23

1.Correct arrow Direction Figure3 in P11

2.Correct SOP150mil 8L POD E1 Distance markers in P98
1.7 02/18/2022
3.Correct SOP150 L max value 0.89->0.90 in P98
4.Correct SOP208 L max value 0.80->0.85 in P97

This Data Sheet may be revised by subsequent versions 99 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C
1.Delete Tpu in Table 8.3 in P87
1.8 2.Update Figure 45a. Power-up Timing and Voltage Levels in P87 06/13/2022
3.Change VPWD from 0.6v to 0.9v in P88

1.Add Only in SPI mode in figure 34 in P63

2.Correct the Erase/Program suspend description in P52
3.Add but the Wrap Length setting will reset to default in P81
1.9 07/27/2022
4.Delete Continuous Read Mode bit setting (M7-M0) in P83
5. Correct some typo error in P32, P34, P35, P78
6.Correct the figure 29 in P58 and figure 33 a&b in P62 and figure 3 in P11

2.0 1. Update tERS in SFDP in P69 and AC&DC table in P92&P94 04/25/2023

1. Delete TFBGA Package.

2.1 2. Modify the Package Mechanical Value 12/15/2023
3. Modify VIL From 0.2*VCC to 0.3*VCC, VIH From 0.8VCC to 0.7VCC in
P87&P88

This Data Sheet may be revised by subsequent versions 100 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15
 XM25QH32C

Important Notice
XMC products are not designed, intended, authorized or warranted for use as components in
systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, or for other applications intended to support or sustain life. Furthermore, XMC products are
not intended for applications wherein failure of XMC products could result or lead to a situation where in
personal injury, death or severe property or environmental damage could occur. XMC customers using
or selling these products for use in such applications do so at their own risk and agree to fully indemnify
XMC for any damages resulting from such improper use or sales.

Information in this document is provided solely in connection with XMC products. XMC
reserves the right to make changes, corrections, modifications or improvements to this
document and the products and services described herein at any time, without notice.

This Data Sheet may be revised by subsequent versions 101 Wuhan Xinxin Semiconductor Manufacturing Corp.
or modifications due to changes in technical specifications.
Rev.2.1, Issue Date: 2023/12/15