ABSTRACT

Low power architectures are more pronounced for different applications that
extend from Internet of Things to Quantum computing. Primitive
combinational logic circuits induce from bit deletion due to information loss
during the processing of input information which results in energy loss. The
computations involving reversibility cancel the loss of information by
sustaining the input bits from output. In the basic arithmetic and logic units,
the combinational circuits play a significant role in determining the
performance of the processor. The principals involved in the design of
reversibility is an upcoming technology for ultra-low power applications. The
reversible logic circuits furnish a thoroughly new way to progress in Quantum
computing. In this article, we propose an energy tolerant low power reversible
multiplexer with optimum energy loss. The proposed multiplexer also reduces
the ancillae, garbage outputs and quantum cost considerably.
 CHAPTER – 1

INTRODUCTION
1.1 Introduction to VLSI:

Very-large-scale integration (VLSI) is the process of creating an integrated

circuit (IC) by combining thousands of transistors into a single chip.

VLSI began in the 1970s

when complex semiconductor and communication technologies were being

developed. The microprocessor is a VLSI device.

Before the introduction of VLSI technology, most ICs had a limited set of
functions they could perform. An electronic circuit might consist of a CPU,
ROM, RAM and other glue logic. VLSI lets IC designers add all of these into
one chip.

The electronics industry has achieved a phenomenal growth over the last few
decades, mainly due to the rapid advances in large scale integration
technologies and system design applications. With the advent of very large
scale integration (VLSI) designs, the number of applications of integrated
circuits (ICs) in high-performance computing, controls, telecommunications,
image and video processing, and consumer electronics has been rising at a very
fast pace.
The current cutting-edge technologies such as high resolution and low bit-rate
video and cellular communications provide the end-users a marvelous amount
of applications, processing power and portability. This trend is expected to
grow rapidly, with very important implications on VLSI design and systems
design.

The Design Process of a VLSI IC

Overall, VLSI IC design incorporates two primary stages or parts:

1. Front-End Design: This includes digital design using a hardware

description language, for example, Verilog, System Verilog, and VHDL.
Furthermore, this stage encompasses design verification via simulation and
other verification techniques. The entire process also incorporates designing,
which starts with the gates and continues through to design for testability.

2. Back-End Design: This consists of characterization and CMOS library

design. Additionally, it involves fault simulation and physical design.

The entire design process follows a step-by-step approach, and the following
are the front-end design steps:

Problem Specification: This is a high-level interpretation of a system. We

address the key parameters, such as design techniques, functionality,
performance, fabrication technology, and physical dimensions. The final
specifications include the power, functionality, speed, and size of the VLSI
system.

Architecture Definition: This includes fundamental specifications such as

floating-point units and which system to use, such as RISC or CISC and
ALU's cache size.

Functional Design: This recognizes the vital functional units of a system

and, thus, enables identification of each unit's physical and electrical
specifications and interconnect requirements.

Logic Design: This step involves control flow, Boolean expressions, word
width, and register allocation.

Circuit Design: This step performs the realization of the circuit in the form
of a netlist. Since this is a software step, it utilizes simulation to check the
outcome.

Physical Design: In this step, we create the layout by converting the netlist
into a geometrical depiction. This step also follows some preconceived static
rules, such as the lambda rules, which afford precise details of the ratio,
spacing between components, and size.

The following are the back-end design steps for hardware development:
Wafer Processing: This step utilizes pure silicon melted in a pot at 1400º C.
Then, a small seed comprising the required crystal orientation is injected into
liquefied silicon and gradually pulled out, 1mm per minute. We manufacture
the silicon crystal as a cylindrical ingot and cut it into discs or wafers before
polishing and crystal orientation.

Lithography: This process (photolithography) includes masking with photo

etching and a photographic mask. Next, we apply a photoresist film on the
wafer. A photo aligner then aligns the wafer to a mask. Finally, we expose
the wafer to ultraviolet light, thus highlighting the tracks through the mask.

Etching: Here, we selectively remove material from the surface of the wafer
to produce patterns. With an etching mask to protect the essential parts of the
material, we use additional plasma or chemicals to remove the remaining
photoresist.

Ion Implantation: Here, we utilize a method to achieve a desired electrical

characteristic in the semiconductor, i.e., a process of adding dopants. The
process uses a beam of high-energy dopant ions to target precise areas of the
wafer. The beam's energy level determines the depth of wafer penetration.

Metallization: In this step, we apply a thin layer of aluminum over the entire
wafer.
Assembly and Packaging: Every one of the wafers contains hundreds of
chips. Therefore, we use a diamond saw to cut the wafers into single chips.
Afterward, they receive electrical testing, and we discard the failures. In
contrast, those that pass receive a thorough visual inspection utilizing a
microscope. Finally, we package the chips that pass the visual inspection as
well as recheck them.

VLSI technology is ideally suited to the demands of today's electronic

devices and systems. With the ever-increasing demand for miniaturization,
portability, performance, reliability, and functionality, VLSI technology will
continue to drive electronics advancement.

1.2 Introduction to Multiplexers

What is a Multiplexer?
A multiplexer (sometimes spelled multiplexor and also known as a MUX) is
defined as a combinational circuit that selects one of several data inputs and
forwards it to the output. The inputs to a multiplexer can be analog or digital.
Multiplexers are also known as data selectors.
A multiplexer efficiently transmits large data volumes over a network within
limited time and bandwidth.
Multiplexers that are built from transistors and relays are termed as analog
multiplexers which are used in analog applications and Multiplexers that are
built from logic gate termed as digital multiplexers which are used in digital
applications. The inverse of a multiplexer is known as a demultiplexer.

What Does a Multiplexer Do?

In digital systems, many times it is necessary to select a single data line from
several data-input lines and the data from the selected data input line should be
available on the output line. The digital circuit which does this task is a
multiplexer.

A multiplexer is a digital circuit that selects one of the n data inputs and
forwards it to the output. The selection of one of the n inputs is done by the
select inputs. To select one of several inputs, we need m select lines such that
2m=n.

Depending on the digital code applied at the select inputs, one of the n data
inputs is selected and transmitted to the single output. Hence, a multiplexer has
maximum 2n data input lines, ‘m’ selects lines, and one output line.
The block diagram of an n-to-1 multiplexer and its equivalent circuit is shown
in the figure below.

How Does a Multiplexer Work?

The multiplexer works like a multiple-input and single-output switch. The

output gets connected to only one of the n data inputs at a given instant of time.
Therefore, the multiplexer is ‘many into one’ and it works as the digital
equivalent of an analog selector switch.

Multiplexer Circuit

There are many types of multiplexers – like 2-to-1, 4-to-1, and 8-to-1
multiplexers. Each one has a different circuit, truth table, boolean expression,
and working principle. Let’s discuss each type of multiplexer one by one.
2 to 1 Multiplexer

2 to 1 Multiplexer Circuit

A 2-to-1 multiplexer is the digital multiplexer circuit that has two data inputs
D0 and D1, one selects line S and one output Y. To implement a 2-to-1
multiplexer circuit we need 2 AND gates, an OR gate, and a NOT gate.

The block diagram, logic symbol and switching circuit analogy of 2-to-1
multiplexer is shown in the figure below.
As shown, D0 is an applied input to one of the AND gate and D1 is an
applied input to the other AND gate. Select input S is applied to the second
AND gate as a second input and an inverted input S is applied to the first
AND gate as a second input. The output of both the AND gates is applied as
inputs to the OR gate.2 to 1 Multiplexer Circuit.
2 to 1 Multiplexer Working Principle

When S=0, it directly enters the second AND gate, while inverted S (1) enters
the first AND gate. For AND gates, an output of zero occurs if any input is
zero, resulting in zero from the second AND gate. Meanwhile, the first AND
gate outputs Y = D0 since its second input is 1.

When S=1, Exactly the reverse happens. In this case, the second AND gate
output is equal to its first input, that is Y = D1 and the first AND gate output
is 0.

So, by applying either a logic ‘0’ or a logic ‘1’ at the select input S, we can
select the appropriate input, D0 or D1 with the circuit act like a single pole
double throw (SPDT) switch.

The below table shows the truth table for the 2-to-1 multiplexer.
 2 to 1 Multiplexer Truth Table

Here, the 2-input multiplexer connects one of two 1-bit sources to a common
output, hence it produces a 2-to-1 multiplexer.

1.3 Introduction to Reversible Computing

Reversible Computing is a model of computing where
the computational process to some extent is reversible, i.e., time-invertible. In
a model of computation that uses deterministic transitions from one state of the
abstract machine to another, a necessary condition for reversibility is that the
relation of the mapping from (nonzero-probability) states to their successors
must be one-to-one. Reversible computing is a form of unconventional
computing.

There are two major, closely related types of reversibility that are of
particular interest for this purpose: physical reversibility and logical
reversibility.

A process is said to be physically reversible if it results in no increase in

physical entropy, it is isentropic . There is a style of circuit design ideally
exhibiting this property that is referred to as charge recovery logic, adiabatic
circuits, or adiabatic computing. Although in practice no nonstationary
physical process can be exactly physically reversible or isentropic, there is no
known limit to the closeness with which we can approach perfect reversibility,
in systems that are sufficiently well isolated from interactions with unknown
external environments, when the laws of physics describing the system's
evolution are precisely known.

Energy dissipation is one of the major issues in present day technology.

Energy dissipation due to information loss in high technology circuits and
systems constructed using irreversible hardware was demonstrated by R.
Landauer in the year 1960. According to Landauer’s principle, the loss of one
bit of information lost, will dissipate kT*ln (2) joules of energy where, k is the
Boltzmann’s constant and k=1.38x10 -23 J/K, T is the absolute temperature in
Kelvin[1]. The primitive combinational logic circuits dissipate heat energy for
every bit of information that is lost during the operation. This is because
according to second law of thermodynamics, information once lost cannot be
recovered by any methods.
In 1973, Bennett, showed that in order to avoid kTln2 joules of energy
dissipation in a circuit it must be built from reversible circuits [2].
According to Moore’s law the numbers of transistors will double every
18 months. Thus energy conservative devices are the need of the day. The
amount of energy dissipated in a system bears a direct relationship to the
number of bits erased during computation. Reversible circuits are those circuits
that do not lose information.

The most prominent application of reversible logic lies in quantum

computers [3]. A quantum computer will be viewed as a quantum network (or
a family of quantum networks) composed of quantum logic gates; It has
applications in various research areas such as Low Power CMOS design,
quantum computing, nanotechnology and DNA computing.
Quantum networks composed of quantum logic gates; each gate
performing an elementary unitary operation on one, two or more two–state
quantum systems called qubits. Each qubit represents an elementary unit of
information; corresponding to the classical bit values 0 and 1. Any unitary
operation is reversible and hence quantum networks effecting elementary
arithmetic operations such as addition, multiplication and exponentiation
cannot be directly deduced from their classical Boolean counterparts (classical
logic gates such as AND or OR are clearly irreversible).
 Thus, quantum arithmetic must be built from reversible logical
components [3]. Reversible computation in a system can be performed only
when the system comprises of reversible gates. A circuit/gate is said to be
reversible if the input vector can be uniquely recovered from the output vector
and there is a one-to-one correspondence between its input and output
assignments [4-6].
An N*N reversible gate can be represented as
Iv=(I1,I2,I3,I4,……………………IN)
Ov=(O1,O2,O3,………………….ON).
Where Iv and Ov represent the input and output vectors respectively.

There are many number of reversible logic gates that exist at present.
The quantum cost of each reversible logic gate is an important optimization
parameter.

Irreversible gates are used as design units in the conventional techniques for
creating a digital circuit. Due to bit loss in each operation, these gates cause
information loss. The major source of heat produced by digital systems is the
bit loss phenomenon in digital circuits.

Although it is true that computers consume a maximum energy, the

question is why computers consume the maximum level energy? In 1961[1],
Mr. Rolf Landauer developed a novel solution from thermodynamics for this
problem that he named the Landauer principle. The principle demonstrates that
irreversible information loss of every bit will result in the generation of the
ln2kT Joules of heat energy, where ln is a logarithm of 2, T is a temperature,
and k is the Boltzmann constant. In 1973, Bennett demonstrated that using
reversible computing as opposed to irreversible calculation prevents the
expenditure of ln2kT Joules of energy.

In typical computers, the calculation is irreversible, meaning that once

the output is produced, the input data may be lost and cannot be recovered,
resulting in increased power usage. Reversible logic circuits, however, are an
exception to this rule since they allow for the generation of input from output.
There will be a distinct input combination for each output logic. Because they
are all multiple level input, single input to output logic gates, gates like AND,
OR, and XOR cannot be reversed.

If the vectors of the input bits and output bits are equal and the inputs
and outputs are assigned to each individual input in a one-to-one relationship,
then a logic gate is said to be reversible. As a result, the outputs of a reversible
gate may potentially be used to identify it individually. Input bits may still be
recovered from the logic gates even after the creation of the output. Reversible
logic gates' inputs and outputs can only be recovered from one another in a
certain way. Information cannot be deleted using reversible logical processes,
and no heat is produced.
 In order to reproduce the inputs from the outputs, the reversible circuit
works backward, which results in zero power usage. Reversible logic gates are
used to create reversible circuits, which carry out difficult logical and
arithmetic operations.
 CHAPTER – 2

LITERATURE SURVEY
The Proposed Multiplexer Architecture performs multiplexing
operation. Multiplexers of various designs have already addressed and worked
on by numerous authors in a literature of reversible designs with the aim of
creating the large optimal and better performance circuits.

“Approach to design a compact reversible low power binary

comparator”--Reversible logic has captured significant attention in recent time
as reducing power consumption is the main concern of digital logic design. It
consumes less power by recovering bit loss from its unique input–output
mapping. In this study, the authors propose a reversible low power n-bit binary
comparator. An algorithm is presented for constructing a compact reversible n-
bit binary comparator circuit. The authors also propose two new reversible
gates, namely, Babu-Jamal-Saleheen (BJS) and Hasan-Lafifa-Nazir (HLN)
gates, to optimise the comparator. In addition, several theorems on the numbers
of gates, garbage outputs, quantum cost, ancilla input, power, delay and area
of the reversible n-bit comparator have been presented. The simulation results
of the proposed comparator show that the circuit works correctly and gives
significantly better performance than the existing ones. The comparative study
shows that, as an example, for a 64-bit comparator, the proposed design
achieves the improvement of 24.4% in terms of number of gates, 19.9% in
terms of garbage outputs, 7.7% in terms of quantum cost, 25.77% in terms of
area and 3.43% in terms of power over the existing best one. Area and power
analysis also show that the proposed design is the most compact as well as a
low power circuit.

“Performance evaluation of reversible logic gates” -- It has been realized

that quantum computing is one of the latest technologies using reversible logic.
It is observed that increasing growth of transistor density, power consumption
will reach their limits in conventional technologies. In conventional Circuits
during the logic operations bits of information is erased resulting dissipation
of energy in significant amount. Thus, if Circuits are designed so that
information bits can be preserved, the power use can be reduced. In case of
reversible logic computation, the information bits are not lost. We can use
reversible logic technology for minimizing the power consumption, heat
dissipation, increasing speed etc. This paper describes various logic gates
based on reversible logic like Toffoli, Peres, Fredkin, and Feynman etc. A
comparative between classical and quantum logic gates is also given on various
parameters along with limitations of conventional computing.

“Design of reversible circuits with high testability” -- A new method of

designing reversible logic circuits which can be adopted by any synthesis
technique to produce parity preserving reversible circuits based on Multiple
Controlled Tofolli gates is proposed. The designed circuit using proposed
methodology is easily testable by checking the input and output parity. A set of
benchmark circuits and corresponding testable designs are implemented. The
results under testable designs show an average reduction of 32% in operating
cost as compared to prior work.

“Design of fault tolearnt full adder/subtractor using reversible gates,” --

Reversible logic gates are in demand for the upcoming future computing
technologies. Reversible logic is emerging as an important research area
having its application in diverse fields such as low power CMOS design. The
paper proposes the design of full Adder/Subtractor circuit using fault tolerant
reversible logic gates. The design can work singly as a reversible Full
Adder/Subtractor unit. It is a parity preserving reversible adder cell, that is, the
parity of the inputs matches the parity of the outputs. The proposed parity
preserving reversible adder can be used to synthesize any arbitrary Boolean
function. It allows any fault that affects no more than a single signal readily
detectable at the circuit's primary outputs. The proposed design offers less
hardware complexity and is efficient in terms of gate count, garbage outputs
and constant inputs than the existing counterparts.
 CHAPTER – 3

EXISTING SYSTEM
4x1 Multiplexer

4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 &
s0 and one output Y. The block diagram of 4x1 Multiplexer is shown in the
following figure.

4x1 Multiplexer

One of these 4 inputs will be connected to the output based on the

combination of inputs present at these two selection lines. Truth table of 4x1
Multiplexer is shown below.
From Truth table, we can directly write the Boolean function for output, Y as

Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3

We can implement this Boolean function using Inverters, AND gates & OR
gate. The circuit diagram of 4x1 multiplexer is shown in the following figure.
4 to 1 Multiplexer Circuit Diagram

We can easily understand the operation of the above circuit. Similarly, you
can implement 8x1 Multiplexer and 16x1 multiplexer by following the same
procedure.

Implementation of Higher-order Multiplexers.

Now, let us implement the following two higher-order Multiplexers using
lower-order Multiplexers.

8x1 Multiplexer

16x1 Multiplexer

8x1 Multiplexer

In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and
2x1 Multiplexer. We know that 4x1 Multiplexer has 4 data inputs, 2 selection
lines and one output. Whereas, 8x1 Multiplexer has 8 data inputs, 3 selection
lines and one output.

So, we require two 4x1 Multiplexers in first stage in order to get the 8 data
inputs. Since, each 4x1 Multiplexer produces one output, we require a 2x1
Multiplexer in second stage by considering the outputs of first stage as inputs
and to produce the final output.

Let the 8x1 Multiplexer has eight data inputs I7 to I0, three selection lines s2,
s1 & s0 and one output Y. The Truth table of 8x1 Multiplexer is shown
below.
We can implement 8x1 Multiplexer using lower order Multiplexers easily by
considering the above Truth table. The block diagram of 8x1 Multiplexer is
shown in the following figure.
 8 to 1 Multiplexer

The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The
data inputs of upper 4x1 Multiplexer are I7 to I4 and the data inputs of lower
4x1 Multiplexer are I3 to I0. Therefore, each 4x1 Multiplexer produces an
output based on the values of selection lines, s1 & s0.

The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1
Multiplexer that is present in second stage. The other selection line, s2 is
applied to 2x1 Multiplexer.
If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I3
to I0 based on the values of selection lines s1 & s0.

If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I7
to I4 based on the values of selection lines s1 & s0.

Therefore, the overall combination of two 4x1 Multiplexers and one 2x1
Multiplexer performs as one 8x1 Multiplexer.
 CHAPTER – 4

METHODOLOGY
The Reversible logic gates methodology is used in the proposed design.

A. Reversible Logic Gates A device with a one point to one other point
mapping between input and output vectors is a reversible logical gates. The
vector of outputs may always be used to reconstruct the vector of inputs. Each
output vectors have a unique functionalities compared to the other output
vectors. A reversible circuit gate has a at least four logic gates with low
complexity level. The Reversible logic circuits have different parameters like
constant given inputs, trash outputs, Quantum rate or cost and number of gates
used in the circuit designing.

1. Number of gates (CG): gates needed to construct reversible circuits.

2. Number of constant inputs given (CI): the proportion of inputs in a

function that represents the number of unchangeable inputs.

3. Garbage or trash output (GO): The reversible logic gate's output

lines are maintained by the amount of unused or undesirable output

bits, allowing reversible circuits to be created.

4. Quantum cost (QC): It is calculated by counting the number of

reversible gates wanted to realising a circuits, which have one input

 output and two inputoutputs. The realisation of one input-output and

two input-output QC is 1.

B. SOME BASIC REVERSIBLE LOGIC GATES To implement the

combinational circuits, the following basic reversible gates are used. Not,
Toffoli, Peres, CNOT, DKG and TR gates are used in this proposed design. Not
gate [6] is a 1x1 gate and functional block is illustrated in figure.1. M(a) is the
input vectored, while K is the output vectored (p). p=a' is the definition of the
not gate's output. The not gate's quantum rate is 1.

Fig.1. NOT gate

Figure.2 shows the functional block for the Toffoli gate [6], that is a 3x3 gate.
Toff, gate's input and output vectors are M(a,b,c) and K(p,q,r). Toffoli gate's
output will specified as p=a, q=b, r =ab xor c. The Toffoli gate's quantum rate
is 5.

Fig.2. Toffoli gate

Figure.3 shows the functional block for the Peres gate , a 3x3 gate. The gate's
input and output vectors are M(a,b,c) and K(p,q,r). The peres gate's output is
denoted as p=a, q= a xor b, and r =ab xor c. The Peres Gate has a quantum rate
of 4.

Fig.3. Peres gate.

Figure.4 shows the functional block and the CNOT gate , which is a 2x2 gate.
M(a,b) and K represent the input and output vectors (p,q). The CNOT gate's
output is denoted as p=a, q=a xor b. The CNOT gate has a quantum rate of 1.

Fig.4: CNOT gate

Figure.5 shows the functional block for the DKG gate, a 4x4 gate. DKG gate's
input and output vectors are M(a,b,c,d) and K(p,q,r,s). p=b, q=a xor c, r=(a xor
b)(c xor d) xor cd, and s=b xor c xor d are the output parameters of the DKG.
The DKG gate's quantum rate is 17.
 Fig.5. DKG gate

Figure 6 shows the functional block for the TR gate , a 3x3 gate. The input
vectors for the TR gate are M(a,b,c) and Output Vector of the gate is K(p,q,r),
respectively. The definition of the TR gate's output is p=a, q=a xor b, and r =b'
xor c. Quantum rate of the TR gate is 4.

Fig.6. TR gate

Cog gate

Figure.7 shows the functional block and the Cog gate .Cog gate is also known
as New Fredkin gate. The Cog gate is formed by cascading of Feynman gate
and Fredkin gate. The Operation of cog gate is almost similar to that of Fredkin
gate. In case of Fredkin gate, it generates only one Swapping operation of the
control inputs. Whereas in Cog gate, it generates the two Swap operation of all
the control inputs. In case of all 3 input 3 output reversible gates, the minimum
quantum cost is attained by cog gate.

Other than this, some basic reversible gates also available like Feynmann(2x2
gate), Double Feynmenn(3x3 gate), HNG gate, Fredkin gate, TSG, NFT,
RMUX1, TKS, BVF. These gates also used for implement the combinational
circuit.
 CHAPTER – 5

PROPOSED METHOD
The design of proposed multiplexer is done in three stages. Initially the most
significant bit of selection lines is considered with least significant two input
bits to generate the partial output expression. The desired output in first stage
is used as selection line in the second stage. In second stage the most significant
two input bits are considered. Finally, the output is generated in the third stage
where the least significant bit of the selection line is considered and generated
the output. The proposed 4 X 1 Multiplexer uses COG reversible gate. It uses
3 COG gates and has 5 garbage outputs. The quantum cost of each COG gates
is 4. The effective quantum cost of proposed multiplexer is 16 which is very
low when compared with existing architectures. A single COG gate can be used
as a 2 X 1 multiplexer. In order to design a 4 X 1 multiplexer, in general we
require three 2 X 1 multiplexers. Therefore, in proposed design three 2 X 1
multiplexers are used. Similarly, the proposed design can be extended for
higher order multiplexers. In order to design 8 X 1 multiplexers, we need two
4 X 1 multiplexers and one 2 X 1 multiplexer. Higher order multiplexers are
obtained by cascading smaller order multiplexers. In general, to design a 2n X
1 multiplexer, (2n -1) COG gates are required with the required quantum cost
of 4(2n-1). It also generates (2n+n-1) garbage outputs. An open source
software Revkit is used for simulating the proposed multiplexer. The output
expression for the proposed multiplexer is
 Fig. Design of 4x1 Multiplexer
For implementing an 8x1 Reversible Multiplexer, two 4x1 Reversible
Multiplexer and one 2x1 Reversible Multiplexer are required which is as
shown in below fig. This design quantum cost is twenty eight and produces
12 garbage outputs. The Reversible 8x1 Multiplexer is implemented based on
the following equation.
 Fig: Proposed 8:1 Reversible multiplexer

Y = S2’S1’S0’I0 + S2’S1’S0I1 + S2’S1S0’I2 + S2’ S1S0I3 + S2S1’S0’I4+

S2S1’S0I5+ S2S1S0’I6+ S2S1S0I7
Here we are using S2 as most significant bit (MSB) among the three selection
lines are used and S0 as least significant bit (LSB).
 CHAPTER – 6
IMPLEMENTATION

Digital Circuit Design Using Xilinx ISE Tools

Introduction

Xilinx Tools is a suite of software tools used for the design of digital
circuits implemented using Xilinx Field Programmable Gate Array
(FPGA) or Complex Programmable Logic Device (CPLD). The design
procedure consists of (a) design entry, (b) synthesis and implementation of
the design, (c) functional simulation and (d) testing and verification. Digital
designs can be entered in various ways using the above CAD tools: using a
schematic entry tool, using a hardware description language (HDL) –
Verilog or VHDL or a combination of both. In this lab we will only use the
design flow that involves the use of Verilog HDL.

The CAD tools enable you to design combinational and sequential circuits
starting with Verilog HDL design specifications. The steps of this design
procedure are listed below:

1. Create Verilog design input file(s) using template driven editor.

2. Compile and implement the Verilog design file(s).
 3. Create the test-vectors and simulate the design (functional
simulation) without using a PLD (FPGA or CPLD).
4. Assign input/output pins to implement the design on a target device.
5. Download bitstream to an FPGA or CPLD device.
6. Test design on FPGA/CPLD device

A Verilog input file in the Xilinx software environment consists of the

following segments:

Header: module name, list of input and output ports.

Declarations: input and output ports, registers and wires.

Logic Descriptions: equations, state machines and logic functions.

End: endmodule

All your designs for this lab must be specified in the above Verilog input
format. Note that the
state diagram segment does not exist for combinational logic designs.

1. Programmable Logic Device: FPGA

In this lab digital designs will be implemented in the Basys2 board which
has a Xilinx Spartan3E –XC3S250E FPGA with CP132 package. This
FPGA part belongs to the Spartan family of FPGAs. These devices come
in a variety of packages. We will be using devices that are packaged in
132 pin package with the following part number: XC3S250E-CP132. This
FPGA is a device with about 50K gates. Detailed information on this
device is available at the Xilinx website.

2. Creating a New Project

Xilinx Tools can be started by clicking on the Project Navigator Icon on

the Windows desktop. This should open up the Project Navigator window
on your screen. This window shows (see Figure 1) the last accessed
project.

Clicking on NEXT on the above window brings up the following window:

 Figure 4: Create New source window (snapshot from Xilinx
ISE software)

If creating a new source file, Click on the NEW SOURCE.

2.1 Creating a Verilog HDL input file for a combinational logic

design

In this lab we will enter a design using a structural or RTL description using
the Verilog HDL. You can create a Verilog HDL input file (.v file) using
the HDL Editor available in the Xilinx ISE Tools (or any text editor).

In the previous window, click on the NEW SOURCE

A window pops up as shown in Figure 4. (Note: “Add to project” option

is selected by default. If you do not select it then you will have to add the
new source file to the project manually.)

Figure 5: Creating Verilog-HDL source file (snapshot from Xilinx ISE

software)
Select Verilog Module and in the “File Name:” area, enter the name of the
Verilog source file you are going to create. Also make sure that the option
Add to project is selected so that the source need not be added to the
project again. Then click on Next to accept the entries. This pops up the
following window (Figure 5).

Figure 6: Define Verilog Source window (snapshot from Xilinx

ISE software)

In the Port Name column, enter the names of all input and output pins and
specify the Direction accordingly. A Vector/Bus can be defined by
entering appropriate bit numbers in the MSB/LSB columns. Then click on
Next> to get a window showing all the new source information (Figure 6).
If any changes are to be made, just click on <Back to go back and make
changes. If everything is acceptable, click on Finish > Next > Next >
Finish to continue.

Figure 7: New Project Information window(snapshot from

Xilinx ISE software)
Once you click on Finish, the source file will be displayed in the sources
window in the Project Navigator (Figure 1).

If a source has to be removed, just right click on the source file in the
Sources in Project window in the Project Navigator and select Remove
in that. Then select Project -> Delete Implementation Data from the
Project Navigator menu bar to remove any related files.

2.2 Editing the Verilog source file

The source file will now be displayed in the Project Navigator window
(Figure 8). The source file window can be used as a text editor to make
any necessary changes to the source file. All the input/output pins will be
displayed. Save your Verilog program periodically by selecting the File-
>Save from the menu. You can also edit Verilog programs in any text editor
and add them to the project directory using “Add Copy Source”.
 Figure 8: Verilog Source code editor window in the Project
Navigator (from Xilinx ISE software)

Adding Logic in the generated Verilog Source code template:

A brief Verilog Tutorial is available in Appendix-A. Hence, the

language syntax and construction of logic equations can be referred
to Appendix-A
 The Verilog source code template generated shows the module name,
the list of ports and also the declarations (input/output) for each port.
Combinational logic code can be added to the verilog code after the
declarations and before the endmodule line.

For example, an output z in an OR gate with inputs a and b can

be described as, assign z = a | b;
Remember that the names are case sensitive.

Other constructs for modeling the logic function:

A given logic function can be modeled in many ways in verilog.
Here is another example in which the logic function, is implemented
as a truth table using a case statement:

module cog_mux41_db(
input A,B,C,D,
input S0,S1,
output Y
);

coggate cog1(S1,A,B,C1,C2,G1);
coggate cog2(C1,C,D,G2,C3,G3);
coggate cog3(S0,C2,C3,G4,Y,G5);
endmodule
module coggate(a,b,c,x,y,z);
input a,b,c;
output reg x,y,z;
always@(a,b,c)
begin
case({a,b,c})
0 : begin x=0;y=0;z=1; end
1: begin x=0;y=0;z=0; end
2: begin x=0;y=1;z=0; end
3: begin x=0;y=1;z=1; end
4: begin x=1;y=0;z=1; end
5: begin x=1;y=1;z=0; end
6: begin x=1;y=0;z=0; end
7: begin x=1;y=1;z=1; end
endcase
end
endmodule
Suppose we want to describe an OR gate. It can be done using the logic
equation as shown in Figure 9a or using the case statement (describing the
truth table) as shown in Figure 9b. These are just two example constructs
to design a logic function. Verilog offers numerous such constructs to
efficiently model designs. A brief tutorial of Verilog is available in
Appendix-A.
 3. Synthesis and Implementation of the Design

The design has to be synthesized and implemented before it can be checked

for correctness, by running functional simulation or downloaded onto the
prototyping board. With the top-level Verilog file opened (can be done by
double-clicking that file) in the HDL editor window in the right half of the
Project Navigator, and the view of the project being in the Module view ,
the implement design option can be seen in the process view. Design
entry utilities and Generate Programming File options can also be seen
in the process view. The former can be used to include user constraints, if
any and the latter will be discussed later.

To synthesize the design, double click on the Synthesize Design option in

the Processes window.

To implement the design, double click the Implement design option in the
Processes window. It will go through steps like Translate, Map and Place
& Route. If any of these steps could not be done or done with errors, it will
place a X mark in front of that, otherwise a tick mark will be placed after
each of them to indicate the successful completion. If everything is done
successfully, a tick mark will be placed before the Implement Design
option. If there are warnings, one can see mark in front of the option
indicating that there are some warnings.
One can look at the warnings or errors in the Console window present at
the bottom of the Navigator window. Every time the design file is saved;
all these marks disappear asking for a fresh compilation.

Figure 11: Implementing the Design (snapshot from Xilinx ISE

software)

The schematic diagram of the synthesized verilog code can be viewed by

double clicking View RTL Schematic under Synthesize-XST menu in the
Process Window. This would be a handy way to debug the code if the output
is not meeting our specifications in the proto type board.

By double clicking it opens the top level module showing only input(s) and
output(s) as shown below.

Figure 12: Top Level Hierarchy of the design

By double clicking the rectangle, it opens the

realized internal logic as shown below.
 Figure 13: Realized logic by the XilinxISE for the verilog code

4. Functional Simulation of Combinational Designs

4.1 Adding the test vectors

To check the functionality of a design, we have to apply test vectors and

simulate the circuit. In order to apply test vectors, a test bench file is
written. Essentially it will supply all the inputs to the module designed
and will check the outputs of the module. Example: For the 2 input OR
Gate, the steps to generate the test bench is as follows:

In the Sources window (top left corner) right click on the file that you
want to generate the test bench for and select ‘New Source’

Provide a name for the test bench in the file name text box and select
‘Verilog test fixture’ among the file types in the list on the right side as
shown in figure 11.

Figure 14: Adding test vectors to the design (snapshot from

Xilinx ISE software)

Click on ‘Next’ to proceed. In the next window select the source file with
which you want to associate the test bench.
Figure 15: Associating a module to a testbench (snapshot from
Xilinx ISE software)
Click on Next to proceed. In the next window click on Finish. You will
now be provided with a template for your test bench. If it does not open
automatically click the radio button next to Simulation .

You should now be able to view your test bench template. The code
generated would be something like this:

module cog_mux41;

// Inputs
reg A;
reg B;
reg C;
reg D;
reg S0;
reg S1;

// Outputs
wire Y;

// Instantiate the Unit Under Test (UUT)

cog_mux41_db uut (
.A(A),
.B(B),
.C(C),
.D(D),
.S0(S0),
.S1(S1),
.Y(Y)
);

initial begin
// Initialize Inputs
A = 1;B = 0;C = 1;D = 0;S0 = 0;S1 = 0;
#10 A = 1;B = 0;C = 1;D = 0;S0 = 0;S1 = 1;
#10 A = 1;B = 0;C = 1;D = 0;S0 = 1;S1 = 0;
 #10 A = 1;B = 0;C = 1;D = 0;S0 = 1;S1 = 1;
#10 $finish;

// Wait 100 ns for global reset to finish

#100;
// Add stimulus here
end
endmodule
assigns them initial values. In order to test the gate completely we shall
provide all the different input combinations. ‘#100’ is the time delay for
which the input has to maintain the current value. After 100 units of time
have elapsed the next set of values can be assign to the inputs.
Complete the test bench as shown below:
module cog_mux41;
// Inputs
reg A;
reg B;
reg C;
reg D;
reg S0;
reg S1;

// Outputs
wire Y;

// Instantiate the Unit Under Test (UUT)

cog_mux41_db uut (
.A(A),
.B(B),
.C(C),
.D(D),
.S0(S0),
.S1(S1),
.Y(Y)
);
initial begin
// Initialize Inputs
A = 1;B = 0;C = 1;D = 0;S0 = 0;S1 = 0;
#10 A = 1;B = 0;C = 1;D = 0;S0 = 0;S1 = 1;
#10 A = 1;B = 0;C = 1;D = 0;S0 = 1;S1 = 0;
#10 A = 1;B = 0;C = 1;D = 0;S0 = 1;S1 = 1;
#10 $finish;

// Wait 100 ns for global reset to finish

#100;
#10; {S1, S0, A, B, C, D} = 6'b000000; #10;
#10; {S1, S0, A, B, C, D} = 6'b000001; #10;
#10; {S1, S0, A, B, C, D} = 6'b000010; #10;
#10; {S1, S0, A, B, C, D} = 6'b000011; #10;
#10; {S1, S0, A, B, C, D} = 6'b000100; #10;
#10; {S1, S0, A, B, C, D} = 6'b000101; #10;
#10; {S1, S0, A, B, C, D} = 6'b000110; #10;
#10; {S1, S0, A, B, C, D} = 6'b000111; #10;

#10; {S1, S0, A, B, C, D} = 6'b001000; #10;

#10; {S1, S0, A, B, C, D} = 6'b001001; #10;
#10; {S1, S0, A, B, C, D} = 6'b001010; #10;
#10; {S1, S0, A, B, C, D} = 6'b001011; #10;
 #10; {S1, S0, A, B, C, D} = 6'b001100; #10;
#10; {S1, S0, A, B, C, D} = 6'b001101; #10;
#10; {S1, S0, A, B, C, D} = 6'b001110; #10;
#10; {S1, S0, A, B, C, D} = 6'b001111; #10;

#10; {S1, S0, A, B, C, D} = 6'b111000; #10;

#10; {S1, S0, A, B, C, D} = 6'b111001; #10;
#10; {S1, S0, A, B, C, D} = 6'b111010; #10;
#10; {S1, S0, A, B, C, D} = 6'b111011; #10;
#10; {S1, S0, A, B, C, D} = 6'b111100; #10;
#10; {S1, S0, A, B, C, D} = 6'b111101; #10;
#10; {S1, S0, A, B, C, D} = 6'b111110; #10;
#10; {S1, S0, A, B, C, D} = 6'b111111; #10;
// Add stimulus here

end

endmodule
Save your test bench file using the File menu.
4.2 Simulating and Viewing the Output Waveforms
Now under the Processes window (making sure that the testbench file in
the Sources window is selected) expand the ModelSim simulator Tab
by clicking on the add sign next to it. Double Click on Simulate
Behavioral Model. You will probably receive a complier error. This is
nothing to worry about – answer “No” when asked if you wish to abort
simulation. This should cause ModelSim to open. Wait for it to complete
execution. If you wish to not receive the compiler error, right click on
Simulate Behavioral Model and select process properties. Mark the
checkbox next to “Ignore Pre-Complied Library Warning Check”.

Figure 16: Simulating the design (snapshot from Xilinx ISE

software)
 CHAPTER – 7

RESULTS

Figure 18: Behavioral Simulation output Waveform

 CHAPTER – 8
CONCLUSION
An efficient design of multiplexer is proposed in this article for ultra-low
quantum cost and ultra-low power applications. As the primitive logic gates
dissipate heat energy, the reversible gates form the basic need for modern
computing. The multiplexers are very widely used in VLSI and communication
environment. Thus a new design of multiplexer is proposed where the main
parameters of focus is quantum cost. There is a reduction of 25% of quantum
cost of proposed multiplexer than the existing multiplexer architectures. Thus
the proposed multiplexer is much pronounced to quantum cost.
 CHAPTER - 9
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