ANALOG CIRCUIT DESIGN

Dr. Pramod R. Bokde

December 4, 2020
 Analog Circuit Design

PBCOE, Nagpur 2 Dr. P.R. Bokde

Contents

1 OPERATIONAL AMPLIFIER FUNDAMENTALS 9

1.1 Definition of Operational Amplifier (OP-AMP) . . . . . . . . . . . 9
1.2 OP-AMP symbol and Pin Diagram . . . . . . . . . . . . . . . . . . 9
1.3 Block Diagram of OP-AMP . . . . . . . . . . . . . . . . . . . . . . 11
1.4 Ideal Characteristics of an OP-AMP . . . . . . . . . . . . . . . . . 12
1.5 Modes of Operation of OP-AMP . . . . . . . . . . . . . . . . . . . 13
1.5.1 Inverting Mode . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.2 Non-Inverting Mode . . . . . . . . . . . . . . . . . . . . . . 13
1.5.3 Differential Mode . . . . . . . . . . . . . . . . . . . . . . . . 13
1.6 Basic Operational Amplifier Circuit . . . . . . . . . . . . . . . . . . 13
1.7 OP-AMP Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.7.1 Common Mode Rejection . . . . . . . . . . . . . . . . . . . 15
1.7.2 Power Supply Rejection Ratio (PSRR) . . . . . . . . . . . . 16
1.7.3 Offset in OP-AMP . . . . . . . . . . . . . . . . . . . . . . . 17
1.7.4 Input and Output Impedances . . . . . . . . . . . . . . . . . 18
1.7.5 Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.7.6 Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . 19
1.8 Basic OP-AMP Configuration . . . . . . . . . . . . . . . . . . . . . 19
1.8.1 Inverting Amplifier . . . . . . . . . . . . . . . . . . . . . . . 19
1.8.2 Non-inverting Amplifier . . . . . . . . . . . . . . . . . . . . 20
1.8.3 Voltage Follower . . . . . . . . . . . . . . . . . . . . . . . . 21
1.9 Equivalent Circuit of OP-AMP . . . . . . . . . . . . . . . . . . . . 22
1.10 Concept of Virtual Short and Virtual Ground . . . . . . . . . . . . 22

2 OP-AMP Linear Applications 25

2.1 Voltage Follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2 Summer or Adder Circuit . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.1 Inverting Summer . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.2 Noninverting Summing Amplifier . . . . . . . . . . . . . . . 27
2.2.3 Averaging Circuit . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3 Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.1 Ideal Integrator . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.2 Practical Integrator . . . . . . . . . . . . . . . . . . . . . . . 30
2.3.3 Applications of Practical Integrator . . . . . . . . . . . . . . 31
2.3.4 Summing Integrator . . . . . . . . . . . . . . . . . . . . . . 31
2.4 Differentiaor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.4.1 Ideal Differentiator . . . . . . . . . . . . . . . . . . . . . . . 33
2.4.2 Practical Differentiator . . . . . . . . . . . . . . . . . . . . . 33

3
CONTENTS Analog Circuit Design

2.4.3 Applications of Practical Differentiator . . . . . . . . . . . . 35

2.4.4 Summing Differentiator . . . . . . . . . . . . . . . . . . . . . 35
2.5 Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6 Logarithmic Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.6.1 Basic Log Amplifier using Transistor . . . . . . . . . . . . . 38
2.7 Antilog Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.7.1 Basic Antilog Amplifier using Diode . . . . . . . . . . . . . . 39
2.7.2 Basic Antilog Amplifier using Transistor . . . . . . . . . . . 40
2.8 Analog Voltage Multiplier . . . . . . . . . . . . . . . . . . . . . . . 41
2.9 Current to Voltage Converter . . . . . . . . . . . . . . . . . . . . . 42
2.10 Voltage to Current Converter . . . . . . . . . . . . . . . . . . . . . 42
2.10.1 V-I Converter with Floating Load . . . . . . . . . . . . . . . 43
2.10.2 V-I Converter with Grounded Load . . . . . . . . . . . . . . 43
2.11 Difference Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.11.1 Difference Amplifier with Single OP-AMP . . . . . . . . . . 44
2.11.2 Difference Amplifier with two OP-AMP . . . . . . . . . . . . 45
2.12 Instrumentation Amplifier . . . . . . . . . . . . . . . . . . . . . . . 46
2.12.1 Instrumentation Amplifier with two OP-AMPs . . . . . . . . 46
2.12.2 Instrumentation Amplifier using Three OP-AMPs . . . . . . 48

3 OP-AMP Non-Linear Applications 51

3.1 Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.1.1 Inverting Schmitt Trigger . . . . . . . . . . . . . . . . . . . 51
3.1.2 Non-inverting Schmitt Trigger . . . . . . . . . . . . . . . . . 54
3.2 Clipper Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.2.1 Positive Clipper . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.2.2 Negative Clipper . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3 Clamper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.3.1 Positive Clamper . . . . . . . . . . . . . . . . . . . . . . . . 59
3.3.2 Negative Clamper . . . . . . . . . . . . . . . . . . . . . . . 61
3.4 Precision Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.4.1 Precision Half Wave Rectifiers . . . . . . . . . . . . . . . . . 62
3.4.2 Precision Full Wave Rectifier . . . . . . . . . . . . . . . . . . 66
3.5 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.6 Sample and Hold Circuit . . . . . . . . . . . . . . . . . . . . . . . . 69
3.7 IC 555 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.8 Data Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.9 Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . 75
3.10 Astable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.10.1 Types of Data Converters . . . . . . . . . . . . . . . . . . . 82
3.10.2 Specifications of Data Converters . . . . . . . . . . . . . . . 82
3.11 Digital to Analog Converters . . . . . . . . . . . . . . . . . . . . . . 84
3.11.1 Weighted Resistor DAC . . . . . . . . . . . . . . . . . . . . 84
3.11.2 R-2R Ladder DAC . . . . . . . . . . . . . . . . . . . . . . . 86
3.12 Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . 88
3.12.1 Counter Type ADC . . . . . . . . . . . . . . . . . . . . . . . 88
3.12.2 Successive Approximation ADC . . . . . . . . . . . . . . . . 90
3.12.3 Flash Type ADC . . . . . . . . . . . . . . . . . . . . . . . . 91

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CONTENTS Analog Circuit Design

3.12.4 Dual Slope ADC . . . . . . . . . . . . . . . . . . . . . . . . 93

4 Voltage Regulators 97
4.1 Series OP-AMP Regulator . . . . . . . . . . . . . . . . . . . . . . . 97
4.2 IC Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.2.1 Fixed Voltage Series Regulator . . . . . . . . . . . . . . . . 98
4.2.2 Characteristics of IC Regulators . . . . . . . . . . . . . . . . 99
4.2.3 Limitations of IC Voltage Regulator . . . . . . . . . . . . . . 99
4.2.4 Advantages of IC Voltage Regulator . . . . . . . . . . . . . . 100
4.2.5 Important Performance Parameter . . . . . . . . . . . . . . 100
4.2.6 IC Regulator as a Current Source . . . . . . . . . . . . . . . 100
4.2.7 Boosting IC Regulator Output Current . . . . . . . . . . . . 101
4.2.8 Fixed Regulator used as Adjustable Regulator . . . . . . . . 104
4.2.9 Dual Voltage Supply . . . . . . . . . . . . . . . . . . . . . . 106
4.2.10 Demerits of 3-terminal IC regulators . . . . . . . . . . . . . 106
4.3 723- General Purpose Regulator . . . . . . . . . . . . . . . . . . . . 106
4.3.1 IC-723 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . 107
4.3.2 Salient Features of IC 723 Regulator . . . . . . . . . . . . . 107
4.3.3 Low Voltage Regulator using 723-IC . . . . . . . . . . . . . 108
4.3.4 IC 723 as High Voltage Regulator (Vo > 7V ) . . . . . . . . . 110
4.3.5 Current Limit Protection . . . . . . . . . . . . . . . . . . . . 112
4.3.6 Current Foldback . . . . . . . . . . . . . . . . . . . . . . . . 113
4.3.7 Current Boosting in 723 IC . . . . . . . . . . . . . . . . . . 114
4.4 Limitations of Linear Voltage Regulators . . . . . . . . . . . . . . . 114
4.5 Switching Regulator or Switched Mode Power Supply . . . . . . . . 114
4.5.1 Advantages of SMPS . . . . . . . . . . . . . . . . . . . . . . 116
4.5.2 Disadvantages of SMPS . . . . . . . . . . . . . . . . . . . . 116
4.5.3 Comparison of Linear regulators and Switching regulators . 117

5 Design of Sinusoidal Oscillators and Function Generator 119

5.1 RC Phase Shift Oscillator . . . . . . . . . . . . . . . . . . . . . . . 119
5.2 Wien Bridge Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 122

6 Filters 127
6.1 Advantages of Active Filters over Passive Filters . . . . . . . . . . . 127
6.2 First Order Low Pass Active Filter . . . . . . . . . . . . . . . . . . 128
6.2.1 Design Steps : First Order Active Low Pass Filter . . . . . . 129
6.3 Second Order Active Low Pass Filter . . . . . . . . . . . . . . . . . 130
6.3.1 Design Steps of Second Order Active Low Pass Filter . . . . 131
6.4 First Order Active High Pass Filter . . . . . . . . . . . . . . . . . . 134
6.4.1 Design Steps for First Order High Pass Filter . . . . . . . . 134
6.5 Second Order Active High Pass Filter . . . . . . . . . . . . . . . . 135
6.5.1 Design Steps of Second Order High Pass Filter . . . . . . . . 136

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CONTENTS Analog Circuit Design

PBCOE, Nagpur 6 Dr. P.R. Bokde

List of Figures

1.1 Symbol and Pin diagram of Operational Amplifier . . . . . . . . . . 10

1.2 Basic Circuit of an operational amplifier has a differential amplifier
input stage and an emitter follower output. . . . . . . . . . . . . . . 13
1.3 Basic Circuit of an OP-AMP with the two inputs short circuited
and a common input votlage Vi applied to them . . . . . . . . . . . 15

3.1 Inverting Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . 52

3.2 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.3 Input and Output waveforms . . . . . . . . . . . . . . . . . . . . . 54
3.4 Non-inverting Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . 54
3.5 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.6 Input and output waveforms . . . . . . . . . . . . . . . . . . . . . . 55
3.7 Positive Clipper Circuit . . . . . . . . . . . . . . . . . . . . . . . . 56
3.8 Waveforms of Positive Clipper Circuit . . . . . . . . . . . . . . . . . 57
3.9 Negative Clipper Circuit . . . . . . . . . . . . . . . . . . . . . . . . 58
3.10 Waveforms of Negative Clipper . . . . . . . . . . . . . . . . . . . . 59
3.11 Positive Clamper Circuit . . . . . . . . . . . . . . . . . . . . . . . . 60
3.12 Waveforms of Positive Clamper Circuit . . . . . . . . . . . . . . . . 60
3.13 Negative Clamper Circuit . . . . . . . . . . . . . . . . . . . . . . . 61
3.14 Waveforms of Negative Clamper Circuit . . . . . . . . . . . . . . . 62
3.15 Precision Non-inverting Half Wave Rectifier . . . . . . . . . . . . . 63
3.16 Half Wave rectivier equivalent circuit for Vi > 0 . . . . . . . . . . . 63
3.17 Half wave circuit equivalent when Vi < 0V . . . . . . . . . . . . . . 64
3.18 Input and Output waveforms for non-inverting Half Wave Rectifiers 64
3.19 Inverting Half Wave Rectifier . . . . . . . . . . . . . . . . . . . . . 65
3.20 Input and Output waveforms of inverting Half Wave Rectifier. . . . 66
3.21 Block Diagram of Phase Locked Loop . . . . . . . . . . . . . . . . . 68
3.22 Sample and Hold Circuit . . . . . . . . . . . . . . . . . . . . . . . . 69
3.23 Sample and Hold Circuit . . . . . . . . . . . . . . . . . . . . . . . . 70
3.24 Sample and Hold Circuit . . . . . . . . . . . . . . . . . . . . . . . . 71
3.25 Sample and Hold Circuit . . . . . . . . . . . . . . . . . . . . . . . . 71
3.26 Pin Diagram of IC 555 Timer . . . . . . . . . . . . . . . . . . . . . 72
3.27 Functional Diagram of IC 555 Timer . . . . . . . . . . . . . . . . . 73
3.28 Monostable operation of IC555 . . . . . . . . . . . . . . . . . . . . 75
3.29 Waveforms of Monostable operation . . . . . . . . . . . . . . . . . . 76
3.30 555 timer as monostable multivibrator . . . . . . . . . . . . . . . . 77
3.31 Astable operation of IC555 . . . . . . . . . . . . . . . . . . . . . . . 78
3.32 Waveforms of Astable Operation . . . . . . . . . . . . . . . . . . . . 80

7
LIST OF FIGURES Analog Circuit Design

3.33 555 timer as Astable multivibrator . . . . . . . . . . . . . . . . . . 81

3.34 Digital to Analog Converter . . . . . . . . . . . . . . . . . . . . . . 84
3.35 Weighted Resistor DAC . . . . . . . . . . . . . . . . . . . . . . . . 85
3.36 R - 2R Ladder Digital to Analog Converter . . . . . . . . . . . . . . 87
3.37 Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . 88
3.38 Counter Type ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.39 Successive Approximation Analog to Digital Converter . . . . . . . 90
3.40 Flash Type Analog to Digital Converter . . . . . . . . . . . . . . . 92
3.41 Dual Slope Analog to Digital Converter . . . . . . . . . . . . . . . . 94

4.1 Pin diagram of IC-723 . . . . . . . . . . . . . . . . . . . . . . . . . 107

5.1 RC network and its phasor diagram . . . . . . . . . . . . . . . . . . 119

5.2 Feedback newtork of RC Phase Shift Oscillator . . . . . . . . . . . 121
5.3 RC Phase Shift Oscillator using OP-AMP . . . . . . . . . . . . . . 121
5.4 Basic Circuit of Wien Bridge Oscillator . . . . . . . . . . . . . . . . 123
5.5 Wien Bridge Oscillator using OP-AMP . . . . . . . . . . . . . . . . 124

PBCOE, Nagpur 8 Dr. P.R. Bokde

Chapter 1

OPERATIONAL AMPLIFIER
FUNDAMENTALS

1.1 Definition of Operational Amplifier (OP-AMP)

OP-AMP is a directly coupled high gain IC amplifier with two high
impedance input terminals and one low output impedance. The OP-
AMP consists of a differential amplifier input stage and an emitter
follower output stage. It is a differential amplifier that amplifies the
difference between two input terminals. It amplifies a.c. as well
as d.c. It is called operational amplifier because with its help, we
can perform mathematical operations such as addition, subtraction,
differentiation, integration etc.

1.2 OP-AMP symbol and Pin Diagram

The OP-AMP is a two input terminal and one output terminal de-
vice. We can apply input signal to any one of these terminals by
grounding other or we can apply it differently.
When we apply signal to non-inverting input, the output obtained
is in phase with input. When we apply signal to inverting input,
output is 180o out of phase.
The letter prefix code on IC identifies the manufacturer as shown
in table below :
OP-AMP Terminals :
OP-AMPs have five basic terminals i.e. two input terminal, one
output terminal and two power supply terminal.

1. Power Supply Terminals : The positive and negative pwoer

supply terminals are connected to two d.c. voltage source.

9
1.2. OP-AMP SYMBOL AND PIN DIAGRAM Analog Circuit Design

Figure 1.1: Symbol and Pin diagram of Operational Amplifier

Table 1.1: OP-AMP IC Manufacturers

Letter Prefix Manufacturer
AD Analog Devices
CA RCA
LM National Semiconductor Coorporation
MC Motorola
SN Texas instruments
µA Fair Child corporation

+VCC connected to +ve terminal of one source and −VEE con-

nected to negative terminal of other source. The power supply
voltage may range from ±5 to ±22 V. Usually +15 V supply is
used.

2. Output Terminal : OP-AMP has one output terminal. Load

RL is connected to this terminal. There is a limit to the current
that can be drawn from output terminal of OP-AMP, usually
of the order of 5 to 10 mA. there are also limits on the output
terminals voltage level. These limits are set by the supply volt-
ages. The upper limit of Vo is called positive saturation voltage
+Vsat and the lower limit is called the negative saturation volt-
age −Vsat e.g. for supply voltage of ±15V , +Vsat = 13V and
−Vsat = −13V .

3. Input Terminal : There are two input terminal of OP-AMP

labelled as - and + . They are called differential input termi-

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 Analog Circuit Design
CHAPTER 1. OPERATIONAL AMPLIFIER FUNDAMENTALS

nal. The (+) input is non-inverting input. An a.c. signal or

d.c. voltage applied to this input produces an inphase or same
polarity signal at the output. On the other hand (–) input is the
inverting input because an ac signal or d.c. voltage applied to
this terminal produces an 180o out of phase or opposite polarity
signal at the output.

1.3 Block Diagram of OP-AMP

An OP-AMP is basically a differernce amplifier having very high
gain, directly coupled amplifier with high input impedance and low
output impedance.
Figure ?? shows the block diagram of IC OP-AMP. The OP-AMP
basically consists of 4-stages as shown in figure ??.

1. Input Stage :
The input stage requires two input terminals with high input
impedance and low output impedance. These requirements are
achieved by using dual input, balanced output differential am-
plifier.
The function of a differential amplifier is to amplify the differ-
ence between the two input signals. This stage provides a major
part of the voltage gain.

2. Intermediate Stage :
The output of the input stage is directly fed to the intermediate
stage. This is anohter differential amplifier with dual input,
unbalanced output (i.e. single ended output). the input stage
alone cannot provide such a high gain.
The main function of the intermediate stage is to provide an
additional voltage gain required. Practically, the intermediate
stage is a chain of cascaded amplifiers called Multi-stage ampli-
fiers.

3. Level Shifting Stage :

Since the input stage amplifier and the intermediate stage am-
plifiers are directly coupled, the d.c. voltage at the output of
the intermediate stage tends to rise above the ground, which is
not desirable.

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1.4. IDEAL CHARACTERISTICS OF AN OP-AMP Analog Circuit Design

To bring down this d.c. voltage to zero, a level shifter is em-

ployed. this is usually an emitter follower, which also acts as
a buffer with very large input resistance and low output resis-
tance.

4. Output Stage :
The output stage consists of a complementary push-pull ampli-
fier, which helps to increase the output voltage swing and the
current supplying capacity of the OP-AMP.

1.4 Ideal Characteristics of an OP-AMP

An ideal OP-AMP shoud have following characteristics :

1. It should have infinite gain. In closed loop application, if the

gain of OP-AMP is infinity, the closed loop gain of circuit de-
pends on external component to OP-AMP. It makes easy to
design amplifier with differential gain.

2. It shoud have infinite input resistance so that amplifier draws

little current from input source. Therefore any source can drive
it. Also if it is connected in intermediate stage, there will be no
loading on previous stage.

3. It should have zero output resistance so that the entire ampli-

fied voltage AVd appears at output terminal. As the output
resistance is zero, it can source large output current. So it can
drive many other devices without loading the OP-AMP.

4. It should provide zero output voltage when applied input is zero

i.e. it should have zero output offset voltage.

5. The bandwidth should be infinite so that any signal ranging

from 0 to ∞ can be amplified with constant gain..

6. Infinite slew rate so that the output changes occur simultane-

ously with input changes.

7. Infinite CMRR so that it can amplify only difference input and

reject common mode signal.

With Rd = ∞ and Ro = 0, the circuit of idea OP-AMP becomes –

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 Analog Circuit Design
CHAPTER 1. OPERATIONAL AMPLIFIER FUNDAMENTALS

1.5 Modes of Operation of OP-AMP

1.5.1 Inverting Mode
In inverting mode, the input voltage Vi is applied to the INV input
terminal and the NON-INv input terminal is grounded. The output
signal of the inverting amplifier is 180o out of phase with the applied
input signal.
Thus, output votlage Vo = −Av Vi

1.5.2 Non-Inverting Mode

In Non-Inverting mode, the input voltage is applied to the NON-INV
input terminal and the INV input terminal is grounded. The output
signal of the Non-Inverting amplifier is in-phase with the applied
input signal.
Thus output voltage Vo = Av Vi

1.5.3 Differential Mode

In differential mode, the voltages V1 and V2 are applied to the in-
verting and non-inverting input terminals respectively.
The output voltage is proportional to the difference between V2
and V1 and hence the name differential mode.

1.6 Basic Operational Amplifier Circuit

The basic circuit of an OP-AMP is shown in figure 1.2.

Figure 1.2: Basic Circuit of an operational amplifier has a differential amplifier

input stage and an emitter follower output.

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1.6. BASIC OPERATIONAL AMPLIFIER CIRCUIT Analog Circuit Design

It is provided with +VCC and −VEE supply voltages and the two
input terminals are grounded. Transistors Q1 and Q2 forms a differ-
ential amplifier.
When a difference input votlage is applied to the bases of Q1 and
Q2 , it produces a voltage change at the collector of Q2 . Transistor
Q3 acts as an emitter follower to provide a low output impedance.
The d.c. output voltage at pin 6 is (applying KVL from VCC , RC , Q3
base and output, we get),

VCC − IC2 RC − VBE3 − VO = 0 (1.1)

VO = VCC − IC2 RC − VBE3 (1.2)

Assuming that Q1 and Q2 are matched (identical) transistors,

which provides equal VBE levels and current gains.
With both transistors bases at ground level, the emitter currents
IE1 and IE2 are equal and flow through common emitter resistor RE .
∴ The total emitter current is given by –
VRE
IE1 + IE2 = (1.3)
RE
Applying KVL from base of Q2 to −VEE supply,

−VBE − (IE1 + IE2 )RE + VEE = 0 (1.4)

(IE1 + IE2 )RE = VEE − VBE (1.5)
VEE − VBE
(IE1 + IE2 ) = (1.6)
RE
The collector votlage of Q2 is given by –

VC = VCC − IC RC (1.7)

We know that,

VCE = VC − VE (1.8)
and VBE = VB − VE (1.9)
∴ VBE = −VE ∵ VB = 0 (1.10)
∴ VE = −VBE (1.11)

VCE = VC − VE (1.12)
∴ VCE = VCC − IC RC − (−VB E) (1.13)
∴ VCE = VCC + VBE − IC RC (1.14)

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 Analog Circuit Design
CHAPTER 1. OPERATIONAL AMPLIFIER FUNDAMENTALS

1.7 OP-AMP Parameters

1.7.1 Common Mode Rejection

Figure 1.3: Basic Circuit of an OP-AMP with the two inputs short circuited and
a common input votlage Vi applied to them

The two input terminals are shorted together and a d.c. voltage of
1 V is applied to it. This is known as a common mode input. Since
there is no differential input, and both input terminals are at the
same potential. So ideally the output should be zero.
Since base votlages of Q1 and Q2 are raised by 1 V, the votlage
drop across RE also increases by 1 V. This increases IC1 and IC2 .
Thus voltage drop across RC also increases, which results in a change
in the output.
Similarly, if a -1 V common mode input is applied, IC2 falls and
again a change is produced at output.
Thus common mode votlage gain Acm is defined as the ratio of
change in output voltage to change in common mode input voltage.
VO(cm)
i.e. Acm = (1.15)
Vi(cm)

The ability of the OP-AMP in injecting common mode inputs is

defined as common mode rejection ratio (CMRR).
CMRR is defined as the ratio of the open-loop gain M to the
common mode gain Acm .
M
i.e. CM RR = (1.16)
Acm
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1.7. OP-AMP PARAMETERS Analog Circuit Design

The CMRR is usually expressed in decibels.

 
M
i.e. (CM RR)dB = 20log10 dB (1.17)
Acm
Typical value of CMRR for 741 IC is 90 dB.
The effect of common mode gain can be modified with feedback.
Consider the non-inverting amplifier as shown in figure ??.
We know that,
VO(cm)
Acm = (1.18)
Vi(cm)
∴ VO(cm) = Acm Vi(cm) (1.19)
The differential input voltage required to cancel VO(cm) is –
VO(cm)
Vd = (1.20)
M
Substituting equation (1.19) in equation (1.20), we get,
Acm × Vi(cm)
Vd = (1.21)
M
From figure ??, the feedback voltage V2 across R2 is –
Vd = IR2 (1.22)
VO(cm)
∴ Vd = × R2 (1.23)
R1 + R 2
Equating equation (1.21) and (1.22)
VO(cm) Acm × Vi(cm)
× R2 = (1.24)
R1 + R2 M
Ac mVi(cm) R1 + R2
∴ VO(cm) = × (1.25)
M R2
Acm Vi(cm)
∴ VO(cm) = × Av (1.26)
M
R1 + R2
where, Av =
R2

1.7.2 Power Supply Rejection Ratio (PSRR)

In basic OP-AMP circuit, a variation in −VEE have the same effect
as an input voltage change. Thus variations in VC C and VEE do
produces some changes at output.

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 Analog Circuit Design
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The PSRR is the ability of the OP-AMP to reject variations in

the power supply voltages.
Ideally, the output voltage should not vary with variations in the
power supply voltage.

VO (ripple)
P SRR = (1.27)
VS (ripple)

If a variation of 1 V in VCC or VEE causes the output to change by

1 V, then PSRR is 1 V per volt i.e. (1 V/V).
If the output changes by 10 mV when one of the supply voltage
changes by 1 V, then PSRR is 10 mV/V.
For µA − 741, the PSRR is typically 30µV /V . For the LM-708,
the PSRR is expressed in decibels.

1.7.3 Offset in OP-AMP

When the two transistors of the input stage are not perfectly matched
then the two base currents are different i.e. IB1 6= IB2 and there is
some difference between their base-emitter voltages VBE1 6= VBE2 .
Due to this, there is presence of unwanted voltages and currents
which are called offset voltages and currents.

Input Offset Voltage

The differential voltage that must be applied between the two input
terminals of an OP-AMP, to make the output voltage zero is called
input offset voltage and denoted as Vios .

Input Offset Current

The algebraic difference between the current flowing into the two
terminals of the OP-AMP is called input offset current and denoted
as IiOS .
IiOS = |IB1 − IB2 | (1.28)

Output Offset Voltage

The presence of d.c. voltage at the output terminals when both the
input terminals are grounded is called output offset voltage.

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1.7. OP-AMP PARAMETERS Analog Circuit Design

1.7.4 Input and Output Impedances

Input Impedance

?? In most OP-AMP applications, some form of negative feedback

is normally provided by the externally connected components.
From negative feedback, the input impedance of the OP-AMP
input terminals becomes,
Zin = (1 + M β)Zi (1.29)
where,
Zi = The OP-AMP input impedance without negative feedback.
M = OP-AMP open loop gain.
β = Feedback factor = 1 for a voltage follower.
The impedance of signal sources connected at the input of an
OP-AMP Circuited should be very much smaller than the amplifier
input impedance to avoid a loss of signal across Rs.

Output Impedance

The typical output resistance specified for the 741 OP-AMP is 75Ω.
Any stray capacitance in parallel with this is certain to have larger
reactance than 75Ω.
The output impedance of the OP-AMP is affected by negative
feedback.
ZO
Zout = (1.30)
1 + Mβ
where,
ZO = OP-AMP output impedance without negative feedback.
M = OP-AMP open loop gain
β = Feedback factor.
Load impedance connected at the output of an OP-AMP should
be much larger than the circuit output impedance. This is to avoid
any significant loss of output as a voltage drop across Zout .

1.7.5 Slew Rate

The slew rate ’S’ of an OP-AMP is the maximum rate at which the
output voltage can change.
When the slew rate is too slow for the input, distortion results.
To understand the concept of slew rate, let us consider an OP-
AMP voltage follower circuit as shown in figure ??.

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 Analog Circuit Design
CHAPTER 1. OPERATIONAL AMPLIFIER FUNDAMENTALS

Figure ?? illustrates a sine wave input to a voltage follower pro-

ducing a triangular output waveform.
The triangular wave results because the OP-AMP simply cannot
move fast enough to follow the sine wave input.
△V
Slew Rate = (1.31)
△t

The typical slew rate of the 741 OP-AMP is 0.5 V/µSec.

If ’S’ represents the slew rate and △VO is the change in the output
voltage, then the minimum time required for satisfactory operation
of OP-AMP is given by –
△VO
△t = (1.32)
S

1.7.6 Input Bias Current

It is defined as the average value of the individual currents flowing
into the INV (–) and NON-INV (+) input terminals of the OP-AMP.

IB + IB2
∴ IB = (1.33)
2
For 741, typical value is 80nA and Maximum value is 500nA.

1.8 Basic OP-AMP Configuration

By connecting external components around an OP-AMP, we obtain
various configuration. The three basic configurations are :

1. Inverting Amplifier

2. Non-inverting Amplifier

3. Voltage Follower

1.8.1 Inverting Amplifier

Input signal applied to the inverting input terminal. Therefore the
output of inverting amplifiers will be inverted i.e. 180o out of phase
with input signal.

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1.8. BASIC OP-AMP CONFIGURATION Analog Circuit Design

Applying KCL at V2 is,

I1 = Ii + If (1.34)
but, Ii =0 (1.35)
∴ I1 = If (1.36)
Vin − V2 V2 − Vo
∴ = (1.37)
R1 Rf

By virtual ground concept, V1 = V2 = 0,

Vin Vo
=− (1.38)
R1 Rf
Vo Rf
∴ = Af = − (1.39)
Vi n R1

1.8.2 Non-inverting Amplifier

In non-inverting amplifier, input is applied at non-inverting terminal

of OP-AMP. Therefore the ouput of non-inverting amplifier is in
phase with the input signal.
Appying KCL at V2 we get,

I1 + Ii = If (1.40)
but Ii = 0 since input impedance is very large (1.41)
∴ I1 = If (1.42)
V2 Vo − V2
∴ = (1.43)
R1 Rf

Since V1 = Vin and A is very large,

Vo
Vd = ≅0 (1.44)
A
∴ V1 − V2 = 0 (1.45)

But, V1 = Vin , therefore V1 = V2 = Vin

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 Analog Circuit Design
CHAPTER 1. OPERATIONAL AMPLIFIER FUNDAMENTALS

∴ equation 1.43 becomes,

Vin Vo − Vin
= (1.46)
R Rf
  1
1 1 Vo
∴ + Vin = (1.47)
R Rf Rf
 1 
R1 + Rf Vo
∴ Vin = (1.48)
R1 Rf Rf
Vo R1 + R f
∴ = Af = (1.49)
Vi n R1
Vo Rf
∴ = Af = 1 + (1.50)
Vi n R1

1.8.3 Voltage Follower

Here Vf = Vo (1.51)
Vf
∴β= =1 (1.52)
Vo
Thus it is non-inverting amplifier with β = 1. This circuit is called
as voltage follower circuit.
∵ it is non-inverting amplifier,
A
Af = (1.53)
1 + Aβ
A 1
∴ Af = = =1 (1.54)
Aβ β
Vo
∴ Af = =1 (1.55)
Vin
∴ Vo = Vin (1.56)
i.e. output is same as that of input. So it is called as voltage follower.
The input resistance of non-inverting amplifier is –
Rif = Ri (1 + Aβ) (1.57)
∴ Rif = Ri (1 + A) (1.58)
It has very high input impedance.
Output resistance,
Ro
Rof = (1.59)
1 + Aβ
Ro
∴ Rof = (1.60)
1 + Aβ

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1.9. EQUIVALENT CIRCUIT OF OP-AMP Analog Circuit Design

The circuit is used as buffer and isolator. It gives better performance

as compared to emitter follower but because it has very high input
resistance and very low output resistance as compared to emitter
follower.

1.9 Equivalent Circuit of OP-AMP

The equivalent circuit of OP-AMP is as shown in figure ??. It in-
cludes differential input resistance Ri , the differential voltage gain
A and output resistance Ro . The Ri , A, Ro are referred to a open
loop parameter and are symbolized by lower case letters. The output
voltage Vo is proportional to the differential input voltage Vd .

∴ Vo = AVd (1.61)
∴ Vo = A(V1 − V2 ) (1.62)
Vo
where A = is called the open loop gain of OP-AMP and it is very
Vd
high for OP-AMP.

1.10 Concept of Virtual Short and Virtual Ground

While analyzing different OP-AMP applications two important con-
cepts have to be considered. They are virtual short and virtual
ground.
Virtual Short :
According to virtual short concept, the potential difference between
two input terminals of an OP-AMP is almost zero. In other words,
both input terminals are approximately at same potential. This
concept can be explained as follows :
The input impedance Ri of an ideal OP-AMP is infinite. So no
current flows from one input terminal to other as shown in figure
??(a). Thus voltage drop across Ri will be zero and both the input
terminals will be set at same potential.
Virtual Ground :
In figure ??(b), the voltage Vid = 0 implies that terminal 1 has
same potential as terminal 2. Since terminal 2 is grounded, terminal
1 is also virtually grounded. The term ’Virtual’ is used to imply
that since Vid = 0, no current flows from terminal 1 to termina 2.
Thus virtual ground point has zero voltage and draws no current.

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 Analog Circuit Design
CHAPTER 1. OPERATIONAL AMPLIFIER FUNDAMENTALS

The inverting input terminal acts like ground as far as voltage is

concerned. So the virtual ground has zero voltage and zero current
unlike the usual ground which has zero voltage but can sink infinite
current.
In virtual ground, for closed loop OP-AMP we can write,

Vo = AVid (1.63)
Vo
i.e A= (1.64)
Vid
where, A is open loop gain of OP-AMP and it is very large.
Vo
∴ Vid = ≅ 0 = negligibly small (1.65)
A
i.e. V1 − V2 = 0 (1.66)
∴ V1 = 0 (1.67)
∴ V1 = V2 = 0 (1.68)

∵ V1 is at ground potential, V2 is also virtually at ground potential

i.e. for voltage purpose input appears as short circuit and for current
purpose, it appears as open circuit.

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1.10. CONCEPT OF VIRTUAL SHORT AND VIRTUALAnalog
GROUNDCircuit Design

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Chapter 2

OP-AMP Linear Applications

2.1 Voltage Follower

A circuit in which the output voltage follows the input voltage is
called voltage follower circuit. The output waveform is exactly same
as the input waveform. The circuit diagram of voltage follower circuit
is as shown in figure ??.
The node B is at potential Vin . Now node A is also at the same
potential as B i.e. Vin .
∴ VA = VB = Vin (2.1)
Node A is directly connected to the output. Hence we can write,
VO = VA (2.2)
Equating equations (2.1) and (2.2),
VO = Vin (2.3)
For this circuit, the voltage gain is unity.
Thus the output voltage VO is equal to the input voltage Vin . If
Vin increases, VO also increases and vice versa.
It can be observed that the output follows the input hence the
circuit is called voltage follower circuit. It is also called as ’Source
follower, unity gain amplifier, buffer amplifier or isolation
amplifier’.
Advantages of Voltage Follower :
1. Very large input resistance of the order of MΩ.
2. Low output impedance, almost zero. Hence it can be used to
connect high impedance source to a low impedance load as a
buffer.

25
2.2. SUMMER OR ADDER CIRCUIT Analog Circuit Design

3. It has large bandwidth.

4. The output follows the input exactly without phase shift.

2.2 Summer or Adder Circuit

As the input impedance of an OP-AMP is extremely large, more
than one input signal can be applied to the inverting amplifier. Such
circuit gives the addition of the applied signals at the output. Hence
it is called Summer or Adder circuit. Depending upon the sign of
the output, the summer circuits are classified as inverting summer
and non-inverting summer.

2.2.1 Inverting Summer

In this circuit, all the input signals to be added are applied to the
inverting input terminal of the OP-AMP. the circuit with two input
signals is shown in figure ??.
As point B is grounded, due to virtual ground concept the node
A is also at virtual ground potential i.e. VA = 0.
Now from the input side,
V1 − VA V1
I1 = = (2.4)
R1 R1
V2 − VA V2
I2 = = (2.5)
R2 R2
Applying KCL at node A and as input OP-AMP current is zero,
I = I1 + I2 (2.6)
From the output side,
VA − VO VO
I= =− (2.7)
Rf Rf
Substituting (2.6), (2.4) and (2.5) in (2.6),
VO V1 V2
− = + (2.8)
Rf R1 R2
 
Rf Rf
∴ VO = − V1 + V2 (2.9)
R1 R2
If the three resistances are equal, R1 = R2 = Rf , then
VO = −(V1 + V2 ) (2.10)

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CHAPTER 2. OP-AMP LINEAR APPLICATIONS Analog Circuit Design

By properly selecting Rf , R1 and R2 , we can have weighted addition

of the input signals line aV1 + bV2 .
Thus the magnitude of the output voltage is the sum of the input
voltages and hence the circuit is called summer or adder circuit.

2.2.2 Noninverting Summing Amplifier

A summer that gives noninverted sum of the input signals is called

non-inverting summing amplifier. The circuit of non-inverting sum-
ming amplifier is as shown in figure ??.
Let the voltage of node B is VB . The node A is at the same
potential as that of node B (due to virtual short concept). Therefore
VA = VB .
From the input side,

V1 − VB
I1 = (2.11)
R1
V2 − VB
I2 = (2.12)
R2
(2.13)

But as the input current of OP-AMP is zero,

I1 + I2 = 0 (2.14)
V1 − VB V2 − VB
∴ + =0 (2.15)
R1 R2  
V1 V2 1 1
∴ + = VB + (2.16)
R1 R2 R1 R2
(R2 V1 + R1 V2 )
∴ VB = (2.17)
(R1 + R2 )

Now at node A,

VA VB
I= = asVB = VA (2.18)
R R
Vo − VA Vo − VB
and I= = (2.19)
Rf Rf

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2.2. SUMMER OR ADDER CIRCUIT Analog Circuit Design

Equating the two equations, we get,

VB Vo − VB
= (2.20)
R Rf
 
Vo 1 1
∴ = VB + (2.21)
Rf R Rf
[R + Rf ]
∴ Vo = VB (2.22)
R
Substituting equation 2.17 in equation 2.22, we get,
(R2 V1 + R1 V2 )[R + Rf ]
Vo = (2.23)
R(R1 + R2 )
R2 (R + Rf ) R1 (R + Rf )
∴ Vo = V1 + V2 (2.24)
R(R1 + R2 ) R(R1 + R2 )
The above equation shows that the output is the weighted sum of
the inputs. If we select R1 = R2 = R = Rf , we get,

Vo = V1 + V2 (2.25)

As there is no phase difference between input and output, this is

called non-inverting summer amplifier.

2.2.3 Averaging Circuit

If in the inverting summer circuit, the values of resistances are se-
R
lected such that, R1 = R2 = R and Rf = then from equation 2.9,
2
we get,
 
R/2 R/2
Vo = − V1 + V2 (2.26)
R R
(V1 + V2 )
∴ Vo = − (2.27)
2
The above equation 2.27 shows that the output voltage is the average
of two input voltages, hence the circuit is called averaging circuit.
Similiarly, if we have n number of inputs, then the average of
these n inputs when R1 = R2 = R3 = ...... = Rn and Rf = Rn is given
by –
(V1 + V2 + V3 + ...... + Vn )
Vo = − (2.28)
n
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CHAPTER 2. OP-AMP LINEAR APPLICATIONS Analog Circuit Design

2.3 Integrator
When the output voltage is the integration of the input voltage,
then the circuit is called Integrator. The integrator can be imple-
mented without using active devices like transistors and OP-AMPs,
such integrators are called passive integrators. But if the integra-
tor circuit uses active components like OP-AMp, it is called active
integrator.

2.3.1 Ideal Integrator

The ideal integrator circuit can be shown as in figure ??.
The non-inverting terminal is grounded i.e. node B is grounded,
hence due to the concept of virtual ground, node A is also grounded.
∴ VA = VB = 0 (2.29)
As the input impedance of ideal OP-AMP is infinity, the cur-
rent flowing into the input terminals of OP-AMP is zero, hence the
current I flowing through R1 also flows through Cf .
From the circuit, we can write,
Vin − VA Vin
I= = (2.30)
R1 R1
Also, we can write,
d(VA − Vo )
I = Cf (2.31)
dt
dVo
∴ I = −Cf (2.32)
dt
Equating equations (2.30) and (2.32), we get,
Vin dVo
= −Cf (2.33)
R1 dt
Integrating both sides of above equation,
Z t Z t
Vin dVo
dt = −Cf dt (2.34)
0 R1 0 dt
Z t
Vin
i.e. dt = −Cf Vo (2.35)
0 R 1
Z t
1
∴ Vo = − Vin dt + Vo (0) (2.36)
R1 C f o

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2.3. INTEGRATOR Analog Circuit Design

where, Vo (0) is the constant of integration which indicates the initial

output voltage and R1 Cf is called time constant of the integrator.
The negative sign in the output indicates that there is a phase shift
of 180o between the input and output.
Sometimes a resistance Rcomp = R1 is connected in the non-
inverting terminal to provide bias compensation as shown in figure
??.
As the input current of of OP-AMP is zero, the node B is still at
ground potential. Hence the above analysis is also applicable to the
integrator circuit with bias compensation.

2.3.2 Practical Integrator

The practical integrator circuit uses Rf in parallel with the capacitor

Cf . The practical integrator circuit is shown in figure ??. The
resistance Rcomp is used to overcome the errors due to bias current.
The resistance Rf reduces the low frequency gain of the OP-AMP.
As current entering into the input terminals of OP-AMP is zero,
the node B is still at ground potential. So node A is also at ground
potential due to virtual ground concept. Therefore VA = 0.
From Figure ??, we can write,

Vin − VA Vin
I= = (2.37)
R1 R1

Again,

d(VA − Vo ) dVo
I 1 = Cf = −Cf (2.38)
dt dt
VA − Vo Vo
also I2 = =− (2.39)
Rf Rf

Applying KCL at node A,

I = I1 + I2 (2.40)
Vin dVo Vo
∴ = −Cf − (2.41)
R1 dt Rf

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CHAPTER 2. OP-AMP LINEAR APPLICATIONS Analog Circuit Design

Taking Laplace of above equation, we get,

Vin (s) Vo (s)

= −sCf Vo (s) − (2.42)
R1 Rf
 
Vin (s) 1
∴ = −Vo (s) sCf + (2.43)
R1 Rf
Vin (s) −Vo (s)[1 + sCf Rf ]
∴ = (2.44)
R1 Rf
Rf
∴ Vo (s) = − Vin (s) (2.45)
R1 (1 + sCf Rf )
1
∴ Vo (s) = −   Vin (s) (2.46)
R1
sR1 Cf + Rf

AS Rf is very large then R1 /Rf can be neglected.

1
Vo (s) = − Vin (s) (2.47)
sR1 Cf
1
Z
∴ Vo (t) = − Vin (t)dt (2.48)
R1 C f

Hence the circuit behaves like ideal integrator.

2.3.3 Applications of Practical Integrator

1. In analog and digital converters.

2. Various signal wave shaping circuits

3. In analog computers

4. In solving differential equations

5. In ramp Generators.

2.3.4 Summing Integrator

The summing integrator can be formed by applying more than one
input to the basic integrator circuit as shown in figure ??.
The node B is grounded, hence due to virtual ground concept the
node A is also grounded. Therefore VA = VB = 0.

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2.4. DIFFERENTIAOR Analog Circuit Design

From figure ??, we can write,

V1 − VA V1
I1 = = (2.49)
R1 R1
V2 − VA V2
I2 = = (2.50)
R2 R2
V3 − VA V3
I3 = = (2.51)
R3 R3
d(VA − Vo ) dVo
and I = Cf = −Cf (2.52)
dt dt
dVo I
∴ =− (2.53)
dt Cf
Integrating both sides,
1
Z
Vo = − Idt (2.54)
Cf
Applying KCL at node A,

I = I1 + I2 + I3 (2.55)
V1 V2 V3
∴I= + + (2.56)
R1 R3 R3
Therefore from equation (2.54), we can write,
Z t
1 V1 V2 V3
Vo (t) = − + + dt (2.57)
C f 0 R1 R2 R3
The above equation shows that the output of the integrator is the
integration of the sum of input voltages. Hence the circuit is called
summing integrator.
If R1 = R2 = R3 = 100K and Cf = 10µF , then we can write,
Z t
Vo (t) = − (V1 + V2 + V3 )dt (2.58)
0

2.4 Differentiaor
In differentiator the output voltage is the differentiation of the input
voltage. The differentiator which does not use any active device
such as transistors, OP-AMP etc are called passive differentiator,
while the differentiator which uses active devices such as OP-AMP
is called active differentiator.

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CHAPTER 2. OP-AMP LINEAR APPLICATIONS Analog Circuit Design

2.4.1 Ideal Differentiator

The differentiator circuit is as shown in figure ??. It is obtained by
exchanging the positions of R and C in the integrator circuit.
The node B is grounded, hence node A is also grounded due to
virtual ground concept. Therefore VA = VB = 0. As the input cur-
rent of OP-AMP is zero, the current I1 flowing through the capacitor
C also flows through resistance Rf .
From figure ??, we can write,
d(Vin − VA ) dVin
I 1 = C1 = C1 (2.59)
dt dt
Also, we can write,
(VA − Vo ) Vo
I= =− (2.60)
Rf Rf
Here, I = I1 , therefore equating two equations,
dVin Vo
C1 = =− (2.61)
dt Rf
dVin
∴ Vo = −C1 Rf (2.62)
dt
The above equation shows that the output is C1 Rf times the dif-
ferentiation of the input voltage. The product term C1 Rf is called
the time constant of the differentiator. The negative sign in the
output indicates that there is a phase shift of 180o between the input
and output voltages.
In practice, a resistance Rcomp = Rf is connected to the non-
inverting terminal to provide the bias compensation as shown in
figure ??.

2.4.2 Practical Differentiator

The noise and stability at high frequencies can be corrected in the
practical differentiator circuit using the resistance R1 in series with
C1 and the capacitor Cf in parallel with resistance Rf . The circuit
of practical differentiator is as shown in figure ??.
AS the input current of OP-AMP is zero, there is no current input
at node B. Hence, it is at the ground potential. From the concept of
the virtual ground, node A is also at the ground potential and hence
VA = VB = 0V .

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2.4. DIFFERENTIAOR Analog Circuit Design

From figure we can write,

Vin − VA Vin
I= = (2.63)
Z1 Z1
where, Z1 = R1 in series with C1 . So in laplace domain we can write,
1 1 + sR1 C1
Z1 = R 1 + = (2.64)
sC1 sC1
sC1 Vin (s)
∴I= (2.65)
(1 + sR1 C1 )
Now, the current I1 is,
VA − Vo Vo
I1 = =− (2.66)
Rf Rf
Vo (s)
In Laplace, I1 = − (2.67)
Rf
d(VA − Vo ) dVo
and I2 = Cf = −C (2.68)
dt dt
Taking laplace transform we get,
I2 = −sCf Vo (s) (2.69)
Applying at node A,
I = I1 + I2 (2.70)
sC1 Vin (s) Vo (s)
∴ =− − sCf Vo (s) (2.71)
(1 + sR1 C1 ) Rf
 
sC1 Vin (s) 1 + sRf Cf
∴ = −Vo (s) (2.72)
(1 + sR1 C1 ) Rf
−sRf C1 Vin (s)
∴ Vo (s) = (2.73)
(1 + sRf C1 )(1 + sR1 C1 )
If Rf Cf = R1 C1 then,
−sRf C1 Vin (s)
Vo (s) = (2.74)
(1 + sR1 C1 )2
The time constant Rf C1 is much greater than R1 C1 or Rf Cf and
hence the equation reduces to,
Vo (s) = −sRf C1 Vin (s) (2.75)
dVin (t)
∴ Vo (t) = −Rf C1 in time domain (2.76)
dt
Thus the output voltage is the Rf C1 times the differentiation of the
input.

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CHAPTER 2. OP-AMP LINEAR APPLICATIONS Analog Circuit Design

2.4.3 Applications of Practical Differentiator

1. In the wave shaping circuits to detect the high frequency com-
ponents in the input signal.
2. As a rate-of-change detector in the FM demodulators.

2.4.4 Summing Differentiator

Summing differentiator can be obtained by applying more than one
input to the basic differentiator as shown in figure ??.
The node B is grounded, hence the potential at A is also zero. So
VA = 0V . Hence we can write the expressions for current as,
V1 − VA V1
I1 = = (2.77)
Z1 Z1
V2 − VA V2
I2 = = (2.78)
Z2 Z2
VA − Vo Vo
and I = =− (2.79)
Rf Rf
Applying KCL at node A,
I = I1 + I2 (2.80)
Vo V1 V2
∴− = + (2.81)
Rf Z1 Z2
Taking Laplace of the equation,
−Vo (s) V1 (s) V2 (s)
∴ = + (2.82)
Rf Z1 Z2
where,
1 1 + sR1 C1
Z1 = R 1 + = (2.83)
sC1 sC1
1 1 + sR2 C2
and Z2 = R2 + = (2.84)
sC2 sC2
−Vo (s) sC1 V1 (s) sC2 V2 (s)
∴ = + (2.85)
Rf 1 + sR1 C1 1 + sR2 C2
−sRf C1 V1 (s) sRf C2 V2 (s)
∴ Vo (s) = − (2.86)
1 + sR1 C1 1 + sR2 C2
As Rf C1 is very much higher than R1 C1 and R2 C2 , we get,
Vo (s) = −sRf C1 V1 (s) − sRf C2 V2 (s) (2.87)

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2.5. PEAK DETECTOR Analog Circuit Design

d
Replacing s by dt ,
 
dV1 (t) dV2 (d)
Vo (t) = −Rf C1 + C2 (2.88)
dt dt
For C1 = C2 , we get,
 
dV1 dV2
Vo (t) = −Rf C1 + (2.89)
dt dt
The above expression shows that the output is the sum of the differ-
entiations of the two inputs. Hence the circuit is called as summing
differentiator.

2.5 Peak Detector

A peak detector is a circuit which notes and remember the peak
positive or negative value of an input signal for an infinite period of
time until it is reset.
Such a peak detector circuit follows the peak of an input signal
and stores the highest value, in terms of a voltage on a capacitor. If
more than one peak occurs in an input signal, new peak value gets
stored, for infinite time until the capacitor is discharged.
Figure ?? shows the basic peak detector circuit.
The circuit is basic positive peak detector. The input signal
charges the capacitor C through diode D. The capacitor gets charged
equal to the highest input voltage, neglecting the small voltage drop.
The capacitor remains charged to the peak value of input unless and
until discharged with the help of MOSFET reset switch.
The OP-AMP is connected as voltage follower and its output
voltage will be equal to the drop across capacitor which is positive
peak of value of the applied voltage and will remain that way for
long periods until next more higher peak occurs at the input. For
negative cycles of input the diode is reverse biased and the capacitor
C retains its voltage.
More sophisticated peak detector that buffers the signal source
from the capacitor is shown in figure ??.
The OP-AMP A1 offers a high impedance load to the source. The
OP-AMP A2 acts as a buffer between the capacitor and the load.
The output voltage Vo at any given time is equal to the voltage
on the capacitor, which is nothing but the peak of the input voltage
occurred upto that time.

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CHAPTER 2. OP-AMP LINEAR APPLICATIONS Analog Circuit Design

Whenever the input signal has more higher peak than the current
one, the capacitor charges upto the new higher input level. But if
the input level gets dropped then the capacitor retains the peak of
input voltage as diode D1 gets reverse biased and diode D2 prevents
the output of A1 from going into the negative saturation. This then
serves to improve the recovery time of A1 when the input attains
more positive value. Resistance R2 provides the path for input bias
current to A1 . The resistance R1 is selected equal to R2 so as to min-
imize the effect of offset voltage. To provide the stability against the
oscillations, the required frequency compensation must be provided
to the OP-AMP A1 .
The figure ?? shows the waveforms for the positive peak detector.
The peak at T1 cannnot be recognized as it is less than the pre-
viously occurred peak in the input signal.
The circuit can be modified to hold the negative peak of the input
signal by reversing the diode connections.
Peak detectors are used for amplitude modulation in communica-
tion and in test and measurement instrumentation applications.

2.6 Logarithmic Amplifier

The circuit which provides the output proportional to the logarithm
of the input voltage is called Logarithmic amplifier. The circuit
diagram of basic log amplifier using diode is shown in figure ??.
Here, in the circuit diode D is used in the feedback path. Since
the node A is grounded, the node B is also at virtual ground. Hence
VB = 0.
Vin − VB Vin
∴I= = (2.90)
R R
As no current flows into the input terminals of OP-AMP, I = If
= Diode Current.
The voltage drop across diode is VB − Vo i.e. −Vo .
The voltage drop across the diode can be written as ,
 
If
−Vo = ηVT ln (2.91)
Io
Vin
Substituting If = I = R ,
 
Vin
Vo = −ηVT ln (2.92)
RIo
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2.6. LOGARITHMIC AMPLIFIER Analog Circuit Design

Since RIo is constant d.c. voltage, it can be represented as Vref .

 
Vin
∴ Vo = −ηVT ln (2.93)
Vref
Thus the output voltage is a function of logarithm of the input
voltage. The circuit gives the logarithm to base e i.e. natural loga-
rithm. But the same circuit can be used to find out logarithm values
to base 10 by proper scaling as,

log10 X = 0.4343 ln(X) (2.94)

2.6.1 Basic Log Amplifier using Transistor

The basic log amplifier is obtained by using transistor in place of
diode in feedback path of OP-AMP as shown in figure ??.
The node B is at virtual ground hence, VB = 0.
Vin − VB Vin
∴I= = (2.95)
R R
As the OP-AMP input current is zero I = IC = collector Current.
The voltage VCB = 0 as the collector is at virtual ground and base
is grounded. Hence the equation of IC can be modified as,
 
IC
VBE = VT ln (2.96)
Is
Applying to the output side, we getm

∴ Vo + VBE = 0 (2.97)
∴ VBE = −Vo (2.98)
Vin
and IC = I = (2.99)
R
Substituting in equation 2.96,
 
Vin
−Vo = VT ln (2.100)
RIs
Let Vref = RIs (2.101)
 
Vin
∴ Vo = −VT ln (2.102)
Vref
From equation 2.102, it is clear that, the output is proportional to
the logarithm of the input voltage.

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CHAPTER 2. OP-AMP LINEAR APPLICATIONS Analog Circuit Design

Disadvantage of Basic Circuit :

The reverse saturation current Io for the diode changes with temper-
ature. It doubles for every 10o C rise in temperature. Similarly the
emitter saturation current varies significantly from one transistor to
other and also with the temperature. Hence it is very difficult to set
the term Vref for the circuit.
The term VT which is kT also changes with temperature, which
appears in both the equations.
Thus temperature affects the performance and accuracy of the
basic logarithmic amplifier circuit. Hence it is must to provide some
sort of temperature compensation to reduce the errors.

2.7 Antilog Amplifier

The log amplifier can be be easily modified to form antilog or expo-
nential function which is called antilog amplifier. The basic antilog
amplifier can be obtained by using a diode or a transistor.

2.7.1 Basic Antilog Amplifier using Diode

The circuit of basic antilog amplifier using diode is shown in figure
??.
The positions of diode and resistance are exchanged as compared
to log amplifier circuit. The node A is grounded and hence node B
is at virtual ground. Hence VB = 0.
Now the current flowing through the diode is If and the voltage
across diode is Vin itself, as B is at virtual ground. Hence from the
diode current equation can be written as,
If = Io evin /ηVT (2.103)
As OP-AMP input current is zero, the current I must be same as If .
VB − Vo −Vo
I = If = = (2.104)
Rf Rf
−Vo
∴ = Io eVin /ηVT (2.105)
Rf
∴ Vo = −(Io Rf )eVin /ηVT (2.106)
The product Io Rf can be assumed to be Vref , so we get,
∴ Vo = −Vref eVin /ηVT (2.107)

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2.7. ANTILOG AMPLIFIER Analog Circuit Design

Thus the output voltage is proportional to the exponential function

of Vin . The exponential function is nothing but the antilog and thus
circuit works as an antilog amplifier.

2.7.2 Basic Antilog Amplifier using Transistor

The basic antilog amplifier using transistor is as shown in figure ??.
The node B i at virtual ground hence VB = 0. Thus both collector
and base of the transistor are at ground potential and hence VCB = 0.
Hence the voltage across the transistor is VBE and we can write the
expression for its collector current as,

IC = Is eVBE /VT (2.108)

But as seen from figure ??, VBE = Vin ,

IC = Is eVin /VT (2.109)

Now the current IC and current I are same as OP-AMP input current
is zero.
VB − Vo −Vo
I = Ic = = (2.110)
Rf Rf
−Vo
∴ = Is eVin /VT (2.111)
Rf
∴ Vo = −Is Rf eVin /VT (2.112)

Assuming Is Rf as Vref , we can write,

∴ Vo = −Vref eVin /ηVT (2.113)

Thus the output voltage is proportional to the exponential of Vin

i.e. antilog of Vin . Thus the circuit works as basic antilog amplifier.
In both the above circuits, it can be seen that the terms Io , Is
and VT are present in the output equation. All these are function of
temperature. Hence as temperature changes, these parameters also
change and cause serious errors at the output. So the basic antilog
circuits also face the same limitations as that of basic log amplifier
circuits and hence the temperature compensation is must for the
antilog amplifier circuits.

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CHAPTER 2. OP-AMP LINEAR APPLICATIONS Analog Circuit Design

2.8 Analog Voltage Multiplier

The circuit can be built to obtain the output which is proportional
to the product of the two input voltages by using log and antilog
amplifiers. This circuit is called analog voltage multiplier which is
shown in figure ??.
The output of log amplifier circuits A1 , A2 is Vo1 andVo2 expressed
as –
Vo1 = +K1 ln K2 V1 (2.114)
and, Vo2 = +K1 ln K2 V2 (2.115)
−VT (R2 + RT ) 1
where, K1 = and K2 =
RT Vref
Now OP-AMP A3 is non-inverting amplifier with unity gain.
∴ Vo3 = Vo1 + Vo2 (2.116)
∴ Vo3 = K1 ln K2 V1 + K1 ln K2 V2 (2.117)
∴ Vo3 = K1 ln(K22 V1 V2 ) (2.118)
Now, Vo3 is applied as input to antilog amplifier A4 .
1 −1 +K1 ln(K22 V1 V2 )
 
∴ Vo = + ln (2.119)
K2 K1
1  2 
∴ Vo = K2 V 1 V 2 (2.120)
K2
∴ V o = K2 V 1 V 2 (2.121)
Thus the output is proportional to the product of two analog inputs
V1 and V2 .
Applications of Multiplier :
1. In communication, it is used in amplitude modulation, phase
modulation, frequency modulation, phase detection, suppressed
carrier modulation, etc.
2. In instrumentation and control used to measure velocity, accel-
eration, instantaneous power, automatic gain control etc.
3. For voltage controlled attenuators and for voltage controlled
amplification.
4. It is used for voltage divider, true r.m.s. calculation, rectifier
phase shift detection etc.

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2.9. CURRENT TO VOLTAGE CONVERTER Analog Circuit Design

5. It is used for frequency converters, frequency doubling and fre-

quency shifting.

6. It is used for squaring and square root calculation.

7. It is used to solve non-linear equations.

8. It is used in oscillators to generate the waveforms and also used

for square wave generation etc.

2.9 Current to Voltage Converter

The photocell, photodiode and photovoltaic cel gives an output cur-
rent that is proportional to an incident radiant energy or light. The
current through these devices can be converted to voltage by using
a current to voltage converter and thereby the amount of light or
radiant energy incident on the photo device can be measured.
Here (–) input terminal is at virtual ground, no current flows
through Rs , thus Is independent of Rs . Is flows through Rf and
produce drop across it with polarity as shown in figure ??.

Vo = −Is Rf (2.122)

From this equation, output voltage Vo becomes proportional to the

input current or source current Is , thus the input source current gets
converted into output voltage.
Vo
The gain is = −Rf (2.123)
Io
This is called sensitivity of converter because it gives the amount of
output voltage change for a given input current change. Feedback
element need not be limited to resistive, it may be impedance Z(s).
∴ Vo (s) = −Z(s)Is (s) and the circuit is called trans-impedance am-
plifier. It may be noted that the lowest current that this circuit can
measure will depend upon the bias current IB of the OP-AMP. This
means that µA 741 (IB = 3nA) can be used to detect lower current.

2.10 Voltage to Current Converter

A voltage to current converter accepts an input voltage Vs and pro-
duces an output current Io which is proportional to the input voltage

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CHAPTER 2. OP-AMP LINEAR APPLICATIONS Analog Circuit Design

 
1  
i.e. Io = Vs where gain R11 has dimensions of conductance.
R1
So the voltage to current converter is also called as trans-conductance
amplifier. There are two configurations of V–I converter depending
upon how the load is connected.
The load can be connected as floating and grounded.
A floating load is a load whose both terminals are not connected
to ground or some reference point. Whereas, a grounded load is a
load whose one of terminal is connected to ground or some reference
point.

2.10.1 V-I Converter with Floating Load

At node a,

V i = iL R 1 (2.124)
Vi
∴ iL = (2.125)
R1
Vi
Thus the input voltage Vi gets converted to current iL =
R1

2.10.2 V-I Converter with Grounded Load

Writing KVL at a,

∴ i 1 + i 2 = iL (2.126)
Vi − V1 Vo − V1
∴ + = iL (2.127)
R R
∴ Vi + Vo − 2V1 = iL R (2.128)
V i + V o − iL R
∴ V1 = (2.129)
2
Here, OP-AMP is used in non-inverting mode.
Vo R
∴ Gain = =1+ =2 (2.130)
V1 R
∴ Vo = 2Vi = Vi + Vo − iL R (2.131)
∴ V i = iL R (2.132)
Vi
∴ iL = (2.133)
R
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2.11. DIFFERENCE AMPLIFIER Analog Circuit Design

2.11 Difference Amplifier

The difference amplifier amplifies the difference between two input
signals. This amplifier has application in instrumentation amplifier
because –
1. They have better capability to reject common mode signals such
as noise than inverting and non-inverting amplifier.
2. Also they present a balanced input impedance.
The difference amplifier can be built using one, two or three OP-
AMPs.

2.11.1 Difference Amplifier with Single OP-AMP

Since the circuit has two input signals, we apply superposition the-
orem.
1. Let Vs2 = 0
RF
∴ Vo′ = − Vs1 (2.134)
R1
2. Let Vs1 = 0
 
R3
V1 = Vs1 (2.135)
R3 + R2
  
R F R 3
∴ Vo′′ = 1 + Vs2 (2.136)
R1 R1 + R2
If R1 = R2 and RF = R3 then,
  
′′ R1 + RF RF
∴ Vo = Vs2 (2.137)
R1 R1 + RF
RF
∴ Vo′′ = Vs2 (2.138)
R1

∴ Vo = Vo′ + Vo′′ (2.139)

RF RF
∴ Vo = − Vs1 + Vs2 (2.140)
R1 R2
RF
∴ Vo = − (Vs1 − Vs2 ) (2.141)
R1

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CHAPTER 2. OP-AMP LINEAR APPLICATIONS Analog Circuit Design

Thus the  circuit 

amplifies the difference in input, i.e. Vs1 − Vs2 with
−RF
a gain of .
R1
The drawback of difference amplifier using one OP-AMP is that
input resistance of difference amplifier is the resistance looking into
any one input terminal with other grounded.
If V1 is grounded, circuit is inverting amplifier and its input resis-
tance is Rif = R1 . If V2 is grounded, circuit is non-inverting amplifier
and its input resistance is Rif = Ri (1 + Aβ). So drawback of dif-
ference amplifier using one OP-AMP is that it has unequal input
resistance.

2.11.2 Difference Amplifier with two OP-AMP

By use of two OP-AMP difference amplifier there is a improvement
in gain and input impedance
 also.

R 3
For first stage, Vo′ = 1 + Vs2 . So now the second stage has
R2
inputs Vs1 and Vo′ . So applying superposition we have,
1. with Vs1 = 0
 
RF RF R3
Vo1 = − Vo′ = − 1+ Vs2 (2.142)
R1 R1 R2
2. with Vo′ = 0  
RF
Vo2 = 1+ Vs1 (2.143)
R1
∴ The final output is –
Vo = Vo1 + Vo2 (2.144)
   
RF R3 RF
∴ Vo = − 1+ Vs2 + 1 + Vs1 (2.145)
R1 R2 R1
(2.146)
If RF = R2 and R1 = R3 then,
   
RF RF
∴ Vo = − 1 + Vs2 + 1 + Vs1 (2.147)
R1 R1
 
RF
∴ Vo = 1 + (Vs1 − Vs2 ) (2.148)
R1
So here the
 difference
 of the input signal (Vs1 − Vs2 ) is amplified by
RF
a gain of 1 + .
R1
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2.12. INSTRUMENTATION AMPLIFIER Analog Circuit Design

2.12 Instrumentation Amplifier

In many industrial and consumer applications, the measurement and
control of physical conditions is very important. Generally, these
measurements are done using transducer. The transducer is a device
that converts one form of energy into another.
The instrumentation system is used to measure the output signal
produced by a transducer and often to control the physical signal
producing it.
The following figure shows a block diagram of instrumentation
system :
The input stage is a transducer and a pre-amplifier. The output
stage may consists of devices like oscilloscope, magnetic recorders,
display etc. The signal input to instrumentation amplifier is the out-
put of transducer. Many transducers produce output which do not
have sufficient strength. To amplify the low-level output, produced
by transducer so that it can drive the display or indicator is the main
function of instrumentation amplifier.
Requirements of Instrumentation Amplifier :
An instrumentation amplifier must satisfy following requirements :
1. Precise low level signal amplification.
2. Low noise
3. Low thermal drift
4. High input resistance
5. Accurate closed loop gain and easy gain adjustments.
6. Low power dissipation
7. High CMRR
8. High Slew Rate

2.12.1 Instrumentation Amplifier with two OP-AMPs

The dual OP-AMP instrumentation amplifier is shown in figure ??.
The OA1 is a non-inverting amplifier. So its output is given by –
 
R3
V3 = 1 + V1 (2.149)
R4
For OA2 applying superposition theorem.

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CHAPTER 2. OP-AMP LINEAR APPLICATIONS Analog Circuit Design

1. Consider V3 acting aline

R2
∴ Vo′ = − V3 (2.150)
R1  
′ R2 R3
∴ Vo = − 1+ V1 (2.151)
R1 R4
For true operation of circuit, R3 = R1 and R2 = R4
 
′ R2 R2 + R1
Vo = − V1 (2.152)
R1 R2
 
R 2
∴ Vo′ = − 1 + V1 (2.153)
R1
2. Consider V2 acting alone
 
R2
Vo ” = 1+ V2 (2.154)
R1
∴ For getting final output we add Vo′ and Vo ”.
∴ Vo = Vo′ + Vo ” (2.155)
 
R2
∴ Vo = 1 + (V2 − V1 ) (2.156)
R1
 
R2
∴ Vo = 1 + (V2 − V1 ) (2.157)
R1
We can also get an dual OP-AMP instrumentation amplifier by
adding resistor RG as shown in figure ??.
The gain of the circuit becomes –
R2 R2
A=1+ + (2.158)
R1 2RG
So by varying RG we can vary the gain.
Advantages :
This instrumentation amplifier requires fewer components. The in-
put resistance is very high and the output resistance is low.
Drawbacks :
In this instrumentation amplifier, the inputs are asymmetrical be-
cause V1 has to propagate through OA1 before being applied to
OA2 . This delay leads to degradation of CMRR with frequency.
So three OP-AMP instrumentation amplifier is designed such that it
has symmetric inputs and high CMRR is maintained over a broader
frequency range.

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2.12. INSTRUMENTATION AMPLIFIER Analog Circuit Design

2.12.2 Instrumentation Amplifier using Three OP-AMPs

The difference amplifier with 3- OP AMPs is as shown in figure ??.

OA1 and OA2 is often referred input or first stage and OA3 forms
the output or second stage. The OA1 and OA2 are connected in non-
inverting mode and OA3 act as difference amplifier. The drawback
of difference amplifier using one OP-AMP is that of unequal input
impedance. This is overcome by connecting OA1 and OA2 to input
of OA3 as shown in figure ??. The output voltage can be calculated
as follows :
Consider OP-AMP OA1 . To find output voltage of OA1 , we apply
superposition theorem.

1. Consider V1 acting alone.

 
R3
∴ Vx = 1+ V1 (2.159)
RG

2. Consider V2 acting alone.

−R3
Vy = V2 (2.160)
RG

∴ The total output of OA1 is –

V3 = Vx + Vy (2.161)
 
R3 R3
∴ V3 = 1 + V1 − V2 (2.162)
RG RG

Similarly for OA2 we can write,

 
R3 R3
V4 = 1+ V2 − V1 (2.163)
RG RG

The V3 and V4 act as input to OA3 . For OA3 we have to apply

superposition theorem again.

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CHAPTER 2. OP-AMP LINEAR APPLICATIONS Analog Circuit Design

∴ The output becomes,

R2
Vo = (V4 − V3 ) (2.164)
R1     
R2 R3 R3 R3 R3
∴ Vo = 1+ V2 − V1 − 1 + V1 + V2
R1 RG RG RG RG
(2.165)
   
R2 2R3 2R3
∴ Vo = 1+ V2 − 1 + V1 (2.166)
R1 RG RG
 
R2 2R3
∴ Vo = 1+ (V2 − V1 ) (2.167)
R1 RG
By varying RG we can adjust gain of instrumentation amplifier.

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2.12. INSTRUMENTATION AMPLIFIER Analog Circuit Design

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Chapter 3

OP-AMP Non-Linear
Applications

3.1 Schmitt Trigger

Schmitt Trigger was invented by Otto Schmitt early 1930’s. It is an

electronic circuit that adds hysteresis to the input-output transition
threshold with the help of positive feedback. Hysteresis here means
it provides two different threshold voltage levels for rising and falling
edge.
Essentially, a Schmitt Trigger is a Bi-stable Multivibrator and its
output remains in either of the stable states indefinitely. For the
output to change from one stable state to other, the input signal
must change (or trigger) appropriately.
This Bistable operation of the Schmitt Trigger requires an ampli-
fier with positive feedback (or regenerative feedback) with a loop gin
greater than one. Hence, Schmitt Trigger is also known as Regener-
ative Comparator.
The Schmitt Trigger is a logic input type that provides hysteresis
or two different threshold voltage levels for rising and falling edge.
This is useful because it can avoid the errors when we have noisy
input signals from which we want to get square wave signals.

3.1.1 Inverting Schmitt Trigger

Figure 3.1 shows the basic circuit diagram of Schmitt trigger. As the
input is applied to the inverting terminal, it is also called inverting
schmitt trigger circuit.

51
3.1. SCHMITT TRIGGER Analog Circuit Design

Figure 3.1: Inverting Schmitt Trigger

When Vin is slightly positive than Vref , the output gets driven
into negative saturation at −Vsat level.
When Vin becomes more negative than −Vref , then output gets
driven into positive saturation at +Vsat level.
Thus the output voltage is always at +Vsat or −Vsat , but the volt-
age at which it changes its state can be controlled by the resistance
R1 and R2 . Thus Vref can be obtained as per requirement.
The values of VREF and -VREF can be formulated as follows:
Vo +Vsat
+Vref = × R2 = × R2 Positive Saturation
R1 + R 2 R 1 + R2
(3.1)
Vo −Vsat
−Vref = × R2 = × R2 Negative Saturation
R1 + R 2 R 1 + R2
(3.2)
(3.3)

+Vref is for positive saturation when Vo = +Vsat and is called

upper threshold voltage denoted as VU T . −Vref is for negative
saturation when Vo = −Vsat and is called lower threshold voltage
denoted as VLT . The values of these threshold voltage levels can be
determined and adjusted by selecting proper values of R1 and R2 .
+Vsat R2
VU T = (3.4)
(R1 + R2 )
−Vsat R2
and VLT = (3.5)
(R1 + R2 )
The output voltage remains in the given state until the input
voltage exceeds the threshold voltage level either positive or negative.
The figure 3.2 shows the graph of output voltage against input
voltage. This is called transfer characteristics of Schmitt trigger.

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CHAPTER 3. OP-AMP NON-LINEAR APPLICATIONSAnalog Circuit Design

Figure 3.2: Hysteresis

The graph indicates that once the output changes its state, it
remains there indefinitely until the input voltage crosses any of the
threshold voltage levels. This is called hysteresis of schmitt trigger.
The hysteresis is also called dead band or dead zone.
The difference between VU T and VLT is called width of the hys-
teresis denoted as H.

 
+Vsat R2 −Vsat R2
H = VU T − VLT = − (3.6)
R1 + R2 R 1 + R2
2Vsat R2
∴H= (3.7)
R1 + R2

The schmitt trigger eliminates the effect of noise voltage present

the noise voltages less than the hysteresis H, cannot cause triggering.
As for positive Vin greater than VU T , the output becomes −Vsat and
for negative Vin less than VLT , the output becomes +Vsat this is called
inverting schmitt trigger.
In short,

Vi < VLT , Vo = +Vsat (3.8)

Vi > VU T , Vo = −Vsat (3.9)

VLT < Vi < VU T , Vo = previous state achieved.

For a pure sinusoidal input signal, the output of an Inverting
Schmitt Trigger Circuit is shown in the following figure 3.3

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3.1. SCHMITT TRIGGER Analog Circuit Design

Figure 3.3: Input and Output waveforms

3.1.2 Non-inverting Schmitt Trigger

The figure 3.4 shows the noninverting schmitt trigger circuit. The
input is applied to the non-inverting input terminal of the OP-AMP.

Figure 3.4: Non-inverting Schmitt Trigger

Let us assume that the output is positively saturated i.e. at +Vsat .

This is feedback to the noninverting input through R1 . This is pos-
itive feedback.
Now though Vin is decreased, the output continues its positive
saturation level unless and until the input becomes more negative
than VLT . At lower threshold, the output changes its states from
positive saturation +Vsat to negative saturation −Vsat . It remains in
the negative saturation till Vin increases beyond its upper threshold
level VU T . The transfer characteristics is shown in figure 3.5.

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Figure 3.5: Hysteresis

Now, VA = voltage at point A = Iin R2 = VU T .

As OP-AMP input current is zero, Iin entirely passes through R1 .
Vo +Vsat
Iin = = (3.10)
R1 R1
R2 R2
∴ VU T = Iin R2 = (+Vsat ) = Vsat (3.11)
R1 R1
R2 R2
and VLT = (−Vsat ) = −Vsat (3.12)
R1 R1
R2
∴ H = VU T − VLT = 2Vsat (3.13)
R1
If a pure sinusoidal signal is applied as input, then the output
signals looks something that given in the figure 3.6.

Figure 3.6: Input and output waveforms

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3.2. CLIPPER CIRCUITS Analog Circuit Design

3.2 Clipper Circuits

A clipper is an electronic circuit that produces an output by remov-
ing a part of the input above or below a reference value. That means,
the output of a clipper will be same as that of the input for other
than the clipped part. Due to this, the peak to peak amplitude of
the output of a clipper will be always less than that of the input.
The main advantage of clippers is that they eliminate the un-
wanted noise present in the amplitude of an ac signal.
Clippers can be classified into the following two types based on
the clipping portion of the input.
1. Positive Clipper
2. Negative Clipper

3.2.1 Positive Clipper

A positive clipper is a clipper that clips only the positive portion(s)
of the input signal.
The circuit diagram of positive clipper is shown in the following
figure –

Figure 3.7: Positive Clipper Circuit

In the circuit shown above, a sinusoidal voltage signal Vi is ap-

plied to the non-inverting terminal of the op-amp. The value of the
reference voltage Vref can be chosen by varying the resistor R2 .
The operation of the circuit shown above is explained below –
If the value of the input voltage Vi is less than the value of the
reference voltage Vref , then the diode D1 conducts. Then, the circuit

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given above behaves as a voltage follower. Therefore, the output

voltage V0 of the above circuit will be same as that of the input
voltage Vi , for Vi ¡ Vref .
If the value of the input voltage Vi is greater than the value of
reference voltage Vref , then the diode D1 will be off. Now, the op-
amp operates in an open loop since the feedback path was open.
Therefore, the output voltage V0 of the above circuit will be equal
to the value of the reference voltage Vref , for Vi ¿ Vref .
The input wave form and the corresponding output wave form of
a positive clipper for a positive reference voltage Vref , are shown in
the following figure –

Figure 3.8: Waveforms of Positive Clipper Circuit

3.2.2 Negative Clipper

A negative clipper is a clipper that clips only the negative portion(s)

of the input signal. You can obtain the circuit of the negative clipper
just by reversing the diode and taking the reverse polarity of the
reference voltage, in the circuit that you have seen for a positive
clipper.
The circuit diagram of a negative clipper is shown in the following
figure 3.9–

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3.2. CLIPPER CIRCUITS Analog Circuit Design

Figure 3.9: Negative Clipper Circuit

In the above circuit, a sinusoidal voltage signal Vi is applied to

the non-inverting terminal of the op-amp. The value of the reference
voltage Vref can be chosen by varying the resistor R2 .

The operation of a negative clipper circuit is explained below –

If the value of the input voltage Vt is greater than the value of

reference voltage Vref , then the diode D1 conducts. Then, the above
circuit behaves as a voltage follower. Therefore, the output voltage
V0 of the above circuit will be same as that of the input voltage Vi
for Vi ¿ Vref .

If the value of the input voltage Vi is less than the value of ref-
erence voltage , then the diode D1 will be off. Now, the op-amp
operates in an open loop since the feedback path is open. Therefore,
the output voltage V0 of the above circuit will be equal to the value
of reference voltage ,Vref for Vi ¡ Vref .

The input wave form and the corresponding output wave form of
a negative clipper, for a negative reference voltage Vref , are shown
in the following figure –

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CHAPTER 3. OP-AMP NON-LINEAR APPLICATIONSAnalog Circuit Design

Figure 3.10: Waveforms of Negative Clipper

3.3 Clamper

A clamper is an electronic circuit that produces an output, which is

similar to the input but with a shift in the DC level. In other words,
the output of a clamper is an exact replica of the input. Hence, the
peak to peak amplitude of the output of a clamper will be always
equal to that of the input.
Clampers are used to introduce or restore the DC level of input
signal at the output. There are two types of op-amp based clampers
based on the DC shift of the input.

1. Positive Clamper

2. Negative Clamper

3.3.1 Positive Clamper

A positive clamper is a clamper circuit that produces an output in

such a way that the input signal gets shifted vertically by a positive
DC value.
The circuit diagram of a positive clamper is shown in the following
figure –

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3.3. CLAMPER Analog Circuit Design

Figure 3.11: Positive Clamper Circuit

In the above circuit, a sinusoidal voltage signal, Vi is applied to

the inverting terminal of op-amp through a network that consists of
a capacitor C1 and a resistor R1 . That means, AC voltage signal is
applied to the inverting terminal of the op-amp.
The DC reference voltage Vref is applied to the non-inverting
terminal of the op-amp. The value of reference voltage Vref can be
chosen by varying the resistor R2 . In this case, we will get a reference
voltage Vref of a positive value.
The above circuit produces an output, which is the combination
(resultant sum) of the sinusoidal voltage signal Vi and the reference
voltage Vref . That means, the clamper circuit produces an output in
such a way that the sinusoidal voltage signal Vi gets shifted vertically
upwards by the value of reference voltage Vref .
The input waveform and the corresponding output wave form of
positive clamper are shown in above figure –

Figure 3.12: Waveforms of Positive Clamper Circuit

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CHAPTER 3. OP-AMP NON-LINEAR APPLICATIONSAnalog Circuit Design

From the figure above, you can observe that the positive clamper
shifts the applied input waveform vertically upward at the output.
The amount of shift will depend on the value of the DC reference
voltage.

3.3.2 Negative Clamper

A negative clamper is a clamper circuit that produces an output in
such a way that the input signal gets shifted vertically by a negative
DC value.
The circuit diagram of negative clamper is shown in the following
figure –

Figure 3.13: Negative Clamper Circuit

In the above circuit, a sinusoidal voltage signal Vi is applied to

the inverting terminal of the op-amp through a network that consists
of a capacitor C1 and resistor R1 . That means, AC voltage signal is
applied to the inverting terminal of the op-amp.
The DC reference voltage Vref is applied to the non-inverting
terminal of the op-amp.The value of reference voltage Vref can be
chosen by varying the resistor R2 . In this case,we will get reference
voltage Vref of a negative value.
The above circuit produces an output, which is the combination
(resultant sum) of sinusoidal voltage signal Vi and reference voltage
Vref . That means, the clamper circuit produces an output in such
a way that the sinusoidal voltage signal Vi gets shifted vertically
downwards by the value of reference voltage Vref .
The input wave form and the corresponding output wave form of
a negative clamper are shown in the following figure –

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3.4. PRECISION RECTIFIER Analog Circuit Design

Figure 3.14: Waveforms of Negative Clamper Circuit

We can observe from the output that the negative clamper shifts
the applied input waveform vertically downward at the output. The
amount of shifting will depend on the value of DC reference voltage.

3.4 Precision Rectifier

Rectifier circuits can be implemented with a diode/diodes (half wave
rectifier or full wave rectifier). The major limitations of these Pre-
cision Rectifiers circuits is that they cannot rectify voltages below
VD(0N ) = 0.7 V, the cut-in voltage of the diode. In these circuits V,
has to rise to a threshold of the order of VD(ON ) before any appre-
ciable change can be seen at the output.
Therefore, above this threshold we have Vo = Vi –VD(ON ) = Vi –0.7V
and below threshold Vo = OV i.e.

Vo = Vi − VD(ON ) f orVi ≥ VD(ON ) (3.14)

Vo = 0V f orVi ≤ VD(ON ) (3.15)

Due to this, output of the conventional rectifier is distorted.

To achieve Precision Rectifiers we need a circuit that keeps Vo
equal to Vi for Vi > OV . This can be achieved by using op-amp along
with the diodes and these circuits are called Precision Rectifiers.
These are used to precisely rectify voltages having amplitudes less
than 0.7 V.

3.4.1 Precision Half Wave Rectifiers

There are two types of precision half wave rectifiers available,

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1. Noninverting half wave rectifier

2. Inverting half wave rectifier

Noninverting half wave rectifier

Figure 3.15: Precision Non-inverting Half Wave Rectifier

Fig. 3.15 shows precision half wave rectifier. It consists of nonin-

verting amplifier with diode D1 in the feedback loop of an op-amp.
The analysis of this circuit can be done considering two distinct
case Vi > 0V and Vi < 0V .
1. Case - 1 : When Vi > 0V :
For closed loop op-amp Vp = Vn , due to virtual ground.

Figure 3.16: Half Wave rectivier equivalent circuit for Vi > 0

When Vi > 0, op-amp tries to keep Vo = Vn = Vp = Vi and it

does this because forward biasing diode provides closed loop
feedback path. The voltage drop across forward bias diode
VD(ON ) = 0.7V .
To accomodate the voltage drop across diode the OP-AMP
swings about 0.7V higher than Vo, as shown in the figure 3.16.

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3.4. PRECISION RECTIFIER Analog Circuit Design

2. Case - 2 : When Vi < 0V

When Vi < OV , diode D1 is reverse biased and the OP-AMP is
working in the open loop, as shown in the figure 3.17.
Therefore, op-amp is no longer capable of keeping Vn = Vp .

Figure 3.17: Half wave circuit equivalent when Vi < 0V

With no current through resistance R we have Vo = 0. Since

Vn = Vo = 0V and Vp = Vi < 0. The OP-AMP output VoA is
saturated at Vsat .
The input and output waveforms are shown in figure 3.18.

Figure 3.18: Input and Output waveforms for non-inverting Half Wave Rectifiers

Inverting Half Wave Rectifiers

Figure ?? shows another popular circuit, inverting half-wave rectifier.

It consists of two diodes and two resistors and op-amp is connected
in the inverting configuration.
1. CASE 1: Vi > 0 : Recalling virtual ground concept we can say
that Vp = Vn = OV . For Vi > 0, Vi is positive with respect to

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CHAPTER 3. OP-AMP NON-LINEAR APPLICATIONSAnalog Circuit Design

Figure 3.19: Inverting Half Wave Rectifier

Vn and hence current through R1 flows from left to right. Only

one path for this current to flow is through diode D1 . Hence
diode D1 is forward biased and diode D2 is reverse biased. As
current flow through R2 is zero, Vo = Vn = OV .

2. CASE 2 : Vi < 0 : For Vi < 0, Vi is negative with respect

to Vn and hence current through R1 flows from right to left.
Only one path for this current to flow is through diode D2 and
resistor R2 , indicating that VoA > Vn . Hence diode D1 is OFF,
and diode D2 is ON. With these diode states, circuit acts like
an inverting amplifier and output voltage is given as,

R2
Vo = − Vi f or Vi < 0V (3.16)
R1

If R1 and R2 are made equal, then we can write Vo = −Vi

The input and output waveforms are shown in figure ??

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3.4. PRECISION RECTIFIER Analog Circuit Design

Figure 3.20: Input and Output waveforms of inverting Half Wave Rectifier.

3.4.2 Precision Full Wave Rectifier

The full wave rectifier circuit accepts an a.c. signal at the input,
inverts either the negative or the positive half and delivers both the
inverted and non-inverted halves at the output as shown in figure
??.
The operation of the positive full wave rectifier is expressed as –
Vo = |Vi | (3.17)
and that of the negative rectifier as,
Vo = −|Vi | (3.18)
Figure ?? shows the full wave rectifier or absolute value circuit.
1. CASE 1 : Vi > 0 : When Vi > 0, inverting side of A1 will
force its output to swing negative, thus forward biasing D1 and
reverse biasing D2 . Since no current flows through resistance
R connected betweeen Vn1 and Vp2 , both are equipotential i.e.
Vn1 = Vp2 = 0V .
The figure ?? shows equivalent circuit. The output voltage can
be given as –
   
−R R
Vo = − Vi = Vi (3.19)
R R
2. CASE 2 : Vi < 0 : When Vi < 0, negative, the output voltage
of A1 swings to positive, making diode D1 reverse biased and
diode D2 forward biased.

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CHAPTER 3. OP-AMP NON-LINEAR APPLICATIONSAnalog Circuit Design

The figure ?? shows the equivalent circuit.

Let the output voltage of OP-AMP A1 be V. Since the differ-
ential input to A2 is zero, the inverting input terminal is also
at voltage V, as shown in figure ??.
Applying KCL at node ’a’, we have,
Vi V V
+ + =0 (3.20)
R 2R R
3V −Vi
∴ = (3.21)
2R R
−2
∴V = Vi (3.22)
3
To find Vo in terms of V, consider the equivalent circuit of A2
as shown in figure ??.
   
R 2R + R 3
∴ Vo = 1 + V = V = V (3.23)
2R 2R 2

Substituting the expression of V in above equation, we get,

 
3 −2
Vo = Vi = −Vi (3.24)
2 3

Hence for Vi < 0, the output is positive. This is shown in figure

??.

3.5 PLL
Phase Locked Loop (PLL) is one of the vital blocks in linear systems.
It is useful in communication systems such as radars, satellites, FMs,
etc.
A Phase Locked Loop (PLL) mainly consists of the following three
blocks –

1. Phase Detector

2. Active Low Pass Filter

3. Voltage Controlled Oscillator (VCO)

The block diagram of PLL is shown in the following figure –

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3.5. PLL Analog Circuit Design

Figure 3.21: Block Diagram of Phase Locked Loop

The output of a phase detector is applied as an input of active low

pass filter. Similarly, the output of active low pass filter is applied
as an input of VCO.
The working of a PLL is as follows –
1. Phase detector produces a DC voltage, which is proportional
to the phase difference between the input signal having fre-
quency of fin and feedback (output) signal having frequency of
fout .
2. A Phase detector is a multiplier and it produces two fre-
quency components at its output – sum of the frequencies fin
and fout and difference of frequencies fin and fout .
3. An active low pass filter produces a DC voltage at its out-
put, after eliminating high frequency component present in the
output of the phase detector. It also amplifies the signal.
4. A VCO produces a signal having a certain frequency, when
there is no input applied to it. This frequency can be shifted
to either side by applying a DC voltage to it. Therefore, the
frequency deviation is directly proportional to the DC voltage
present at the output of a low pass filter.
The above operations take place until the VCO frequency equals
to the input signal frequency. Based on the type of application, we
can use either the output of active low pass filter or output of a
VCO. PLLs are used in many applications such as FM demodulator,
clock generator etc.
PLL operates in one of the following three modes –
1. Free running mode
2. Capture mode

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CHAPTER 3. OP-AMP NON-LINEAR APPLICATIONSAnalog Circuit Design

3. Lock mode
Initially, PLL operates in free running mode when no input is
applied to it. When an input signal having some frequency is applied
to PLL, then the output signal frequency of VCO will start change.
At this stage, the PLL is said to be operating in the capture mode.
The output signal frequency of VCO will change continuously until
it is equal to the input signal frequency. Now, it is said to be PLL
is operating in the lock mode.

3.6 Sample and Hold Circuit

Four basic sample and hold circuit are shown in following figures. In
these circuits a JFET is used as switch. During the sampling time
the JFET switch is turned on, and the holding capacitor charges up
to the level of the analog input voltage. At the end of this short
sampling period, the JFET switch is turned off. This isolates the
holding capacitor. CH from the input signal. As a result, the volt-
age across capacitor CH and hence the output voltage will remain
essentially constant at the value of the input voltage at the end of
the sampling time. However, there will be a small drop-off or drop
of the capacitor voltage during the hold period due to the various
leakage currents. To avoid this, input and output buffers (voltage
follower) circuits are used.

Figure 3.22: Sample and Hold Circuit

Figure 3.22shows the open loop architecture of the sample and

hold circuit. Remaining Figs show the closed loop architecture of the
sample and hold circuit. Open loop type sample and hold circuits are
faster than closed loop types which have delayed output fedback to
the input buffer. However, closed loop architectures provide higher

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3.6. SAMPLE AND HOLD CIRCUIT Analog Circuit Design

dc accuracy because of this feedback, cancelling the output amplifier

offset errors.
The acquisition time of a S/H circuit is the time required for the
holding capacitor CH to charge up to a level close to the input voltage
during sampling. The acquisition time for S/H circuit should be as
low as possible. In the circuit of figure 3.22 there are three principle
factors that will control the acquisition time.
These factors are :

1. RC time constant where R is the rds (ON ), i.e. on resistance of

JFET and C is the holding capacitance CH .

2. Maximum output current, which can be source or sunk by the

operational amplifier.

3. Slew rate of the op-amp.

Figure 3.23: Sample and Hold Circuit

The circuit shown in figure 3.23 offers some advantage over that of
Fig. 14.141 (a) in terms of the acquisition time since the rds (ON ) of
the JFET switch is inside the feedback loop of A1 and A2 . Therefore
the acquisition time for this circuit is limited by maximum output
current and slew rate of the op-amp, rather than the RC time con-
stant.

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CHAPTER 3. OP-AMP NON-LINEAR APPLICATIONSAnalog Circuit Design

Figure 3.24: Sample and Hold Circuit

The S/H circuit of figure 3.24 performs in a fashion similar to

that of figure 3.23 but it offers the additional feature of providing
voltage gain. The voltage gain of this circuit can be given as A =
1 + (RF /R1 ). Therefore, the sampled output
Advantage over that of figure 3.22 in terms of the acquisition time
since the rds (ON ) of the JFET switch is inside the feedback loop of
A1 and A2 . Therefore the acquisition time for this circuit is limited
by maximum output current and slew rate of the op-amp, rather
than the RC time constant. voltage is equal to the sampled input
voltage multiplied by the voltage gain factor of 1 + (RF /R1 ).

Figure 3.25: Sample and Hold Circuit

The S/H circuit of figure 3.25 offers two advantages. The faster
capacitor charging rate provides shorter acquisition time. This is
because the voltage at the inverting input terminal of A2 is equal
to the capacitor voltage divided by the open loop gain of A2 . In
this circuit, the summing input of A2 remains at virtual ground.
Due to this, the charge removed from the summing junction via
Cgd is constant regardless of the input and output signal levels. This

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3.7. IC 555 TIMER Analog Circuit Design

removed charge appears as a constant offset at the output. However,

as it is constant, it can be nulled by any standard offset trimming
technique.
Advantages of Sample and Hold Circuit :
1. The primary use of the sample and hold circuit to hold the
sampled analog input voltage constant during conversion time
of A/D converter.
2. In case of multichannel ADCs, synchronization can be achieved
by sampling signals from all channels at the same time.
3. It also reduces the crosstalk in the multiplexer.

3.7 IC 555 Timer

The 555 Timer IC got its name from the three 5KΩ resistors that are
used in its voltage divider network. This IC is useful for generating
accurate time delays and oscillations.
The 555 Timer IC is an 8 pin mini Dual-Inline Package (DIP).
The pin diagram of a 555 Timer IC is shown in the following figure
–

Figure 3.26: Pin Diagram of IC 555 Timer

The significance of each pin is self-explanatory from the above

diagram. This 555 Timer IC can be operated with a DC supply of
+5V to +18V. It is mainly useful for generating non-sinusoidal wave
forms like square, ramp, pulse etc.
The pictorial representation showing the internal details of a 555
Timer is known as functional diagram.

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CHAPTER 3. OP-AMP NON-LINEAR APPLICATIONSAnalog Circuit Design

The functional diagram of 555 Timer IC is shown in the following

figure –

Figure 3.27: Functional Diagram of IC 555 Timer

Observe that the functional diagram of 555 Timer contains a volt-

age divider network, two comparators, one SR flip-flop, two transis-
tors and an inverter.
1. Voltage Divider Network :
(a) The voltage divider network consists of a three 5KΩ resis-
tors that are connected in series between the supply voltage
Vcc and ground.
(b) This network provides a voltage of V3cc between a point and
ground, if there exists only one 5KΩ resistor. Similarly, it
provides a voltage of 2V3cc between a point and ground, if
there exists only two 5KΩ resistors.
2. Comparator :
(a) The functional diagram of a 555 Timer IC consists of two
comparators: an Upper Comparator (UC) and a Lower
Comparator (LC).
(b) Recall that a comparator compares the two inputs that are
applied to it and produces an output.

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3.7. IC 555 TIMER Analog Circuit Design

(c) If the voltage present at the non-inverting terminal of an

op-amp is greater than the voltage present at its inverting
terminal, then the output of comparator will be +Vsat . This
can be considered as Logic High (’1’) in digital representa-
tion.
(d) If the voltage present at the non-inverting terminal of op-
amp is less than or equal to the voltage at its inverting ter-
minal, then the output of comparator will be −Vsat . This
can be considered as Logic Low (’0’) in digital representa-
tion.

3. SR Flip-Flop :

(a) Recall that a SR flip-flop operates with either positive clock

transitions or negative clock transitions. It has two inputs:
S and R, and two outputs: Q(t) and Q(t)’. The outputs,
Q(t) & Q(t)’ are complement to each other.
(b) The following table shows the state table of a SR flip-flop
S R Q (t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 –
(c) Here, Q(t) & Q(t+1) are present state & next state respec-
tively. So, SR flip-flop can be used for one of these three
functions such as Hold, Reset & Set based on the input con-
ditions, when positive (negative) transition of clock signal
is applied.
(d) The outputs of Lower Comparator (LC) and Upper Com-
parator (UC) are applied as inputs of SR flip-flop as shown
in the functional diagram of 555 Timer IC.

4. Transistors and Inverters :

(a) The functional diagram of a 555 Timer IC consists of one

npn transistor Q1 and one pnp transistor Q2 . The npn
transistor Q1 will be turned ON if its base to emitter voltage
is positive and greater than cut-in voltage. Otherwise, it
will be turned-OFF.

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(b) The pnp transistor Q2 is used as buffer in order to isolate

the reset input from SR flip-flop and npn transistor Q1 .
(c) The inverter used in the functional diagram of a 555 Timer
IC not only performs the inverting action but also amplifies
the power level.
he 555 Timer IC can be used in mono stable operation in order to
produce a pulse at the output. Similarly, it can be used in astable
operation in order to produce a square wave at the output.

3.8 Data Converters

All the real world quantities are analog in nature. We can represent
these quantities electrically as analog signals. An analog signal is a
time varying signal that has any number of values (variations) for a
given time slot.
In contrast to this, a digital signal varies suddenly from one level
to another level and will have only finite number of values (varia-
tions) for a given time slot.

3.9 Monostable Multivibrator

The IC 555 timer can be operated as a Monostable Multivibrator
Using IC 555 by connecting an external resistor and a capacitor as
shown in the figure 3.28.

Figure 3.28: Monostable operation of IC555

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3.9. MONOSTABLE MULTIVIBRATOR Analog Circuit Design

The circuit has only one stable state. When trigger is applied, it
produces a pulse at the output and returns back to its stable state.
The duration of the pulse depends on the values of R and C. As it
has only one stable state, it is called one shot multivibrator.
Operation :
The flip-flop is initially set i.e. Q is high. This drives the transistor
Qd in saturation. The capacitor discharges completely and voltage
across it is nearly zero. the output at pin 3 is low.
When a trigger input, a low going pulse is applied, then circuit
state remains unchanged till trigger voltage is greater than 1/3Vcc .
When it becomes less than 1/3Vcc , then comparator 2 output goes
high. This resets the flip-flop so Q goes low and Q goes high. Low Q
makes the transistor Qd off. Hence capacitor starts charging through
resistance R, as shown by dark arrows in the figure 3.28.
The voltage across capacitor increases exponentially. This voltage
is nothing but the threshold voltage at pin 6. When this voltage
becomes more than 2/3Vcc , then comparator 1 output goes high.
This sets the flip-flop i.e. Q becomes high and low. This high Q
drives the transistor Qd in saturation. Thus capacitor C quickly
discharges through Qd as shown by dotted arrows in the figure ??.

Figure 3.29: Waveforms of Monostable operation

So it can be noted that Vout at pin 3 is low at start, when trigger

is less than 1/3Vcc it becomes high and when threshold is greater
than 2/3Vcc again becomes low, till next trigger pulse occurs. So
a rectangular wave is produced at the output. The pulse width of
this rectangular pulse is controlled by the charging time of capacitor.
This depends on the time constant RC. Thus RC controls the pulse

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width. The waveforms are shown in the figure 3.29.

Derivation of Pulse Width :
The voltage across capacitor increases exponentially and is given by
–

VC = V (1 − e−t/CR ) (3.25)
2
If, VC = Vcc (3.26)
3
2
then, Vcc = Vcc (1 − e−t/CR ) (3.27)
3
2
− 1 = −e−t/CR (3.28)
3
1
= e−t/CR (3.29)
3
−t
∴ = −1.0986 (3.30)
CR
∴ t = +1.0986CR (3.31)
∴ t ≈ 1.1CR (3.32)

where, C in farads, R in ohms and t in seconds.

Thus we say that voltage across capacitor will reach 23 Vcc is ap-
proximately 1.1 times, time constant i.e. 1.1 RC
Thus the pulse width denoted as W is given by,

W = 1.1RC (3.33)

Schematic Diagram

Figure 3.30: 555 timer as monostable multivibrator

Generally a schematic diagram of the Monostable Multivibrator

Using IC 555 circuits is shown which does not include comparators,

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3.10. ASTABLE MULTIVIBRATOR Analog Circuit Design

flip-flop etc. It only shows the external components to be connected

to the 8 pins of Monostable Multivibrator Using IC 555. Thus,
the schematic diagram of Monostable Multivibrator Using IC 555 is
shown in the figure 3.30.
The external components R and C are shown. To avoid accidental
reset, pin 4 is connected to pin 8 which is supply +Vcc . To have the
noise filtering of control voltage, the pin 5 is grounded through a
small capacitor of 0.01 µF .
Applications of Monostable Multivibrator :
1. Frequency divider
2. Pulse width modulation
3. Linear ramp generator
4. Pulse position modulation
5. Missing pulse detector
6. Timer in relay

3.10 Astable Multivibrator

The figure ?? shows the Astable Multivibrator Using IC 555. The
threshold input is connected to the trigger input. Two external
resistances RA , RB and a capacitor C is used in the circuit.

Figure 3.31: Astable operation of IC555

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This circuit has no stable state. The circuits changes its state
alternately. Hence the operation is also called free running nonsinu-
soidal oscillator.

Operation :
When the flip-flop is set, Q is high which drives the transistor Qd
in saturation and the capacitor gets discharged. Now the capacitor
voltage is nothing but the trigger voltage. So while discharging,
when it becomes less than 1/3Vcc , comparator 2 output goes high.
This resets the flip-flop hence Q goes low and Q goes high.

The low Q makes the transistor off. Thus capacitor starts charg-
ing through the resistances RA , RB and Vcc . The charging path
is shown by thick arrows in the figure 3.31. As total resistance
in the charging path is (RA + RB ), the charging time constant is
(RA + RB )C.

Now the capacitor voltage is also a threshold voltage. While

charging, capacitor voltage increases i.e. the threshold voltage in-
creases. When it exceeds 2/3Vcc , then the comparator 1 output goes
high which sets the flip-flop. The flip-flop output Q becomes high
and output at pin 3 i.e. Q becomes low. High Q drives transistor Qd
in saturation and capacitor starts discharging through resistance RB
and transistor Qd . This path is shown by dotted arrows in the figure
3.31. Thus the discharging time constant is RB C. When capacitor
voltage becomes less than 1/3Vcc , comparator 2 output goes high,
resetting the flip-flop. This cycle repeats.

Thus. when capacitor is charging, output is high while when it is

discharging the output is low. The output is a rectangular wave. The
capacitor voltage is exponentially rising and falling. The waveforms
are shown in the ??

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3.10. ASTABLE MULTIVIBRATOR Analog Circuit Design

Figure 3.32: Waveforms of Astable Operation

Duty Cycle :
Generally the charging time constant is greater than the discharging
time constant. Hence at the output, the waveform is not symmetric.
The high output remains for longer period than low output. The
ratio of high output period and low output period is given by a
mathematical parameter called duty cycle. It is defined as the ratio
of ON time i.e. high output to the total time of one cycle. As shown
in the figure ??.
Let W =time for output is high, T = time of one cycle.
Therefore, duty cycle (D) is given as –

W
D= (3.34)
T
W
∴ %D = × 100% (3.35)
T

The charging time of capacitor is given by,

Tc = Charging time = 0.693(RA + RB )C (3.36)

While the discharging time is given by –

Td = Discharging time = 0.693RB C (3.37)

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Hence the time for one cycle is,

T = Tc + Td = 0.693(RA + RB )C + 0.693RB C (3.38)
∴ T = 0.693(RA + 2RB )C (3.39)
while, W = Tc = 0.693(RA + RB )C (3.40)
W 0.693(RA + RB )C
∴ %D = × 100 = × 100 (3.41)
T 0.693(RA + 2RB )C
(RA + RB )
∴ %D = × 100 (3.42)
(RA + 2RB )
While the frequency of oscillation is given by,
1 1
f= = (3.43)
T 0.693(RA + 2RB )C
1.44
∴f = Hz (3.44)
(RA + 2RB )C
If RA is much smaller than RB, duty cycle approaches to 50% and
output waveform approaches to square wave.
Schematic Diagram :

Figure 3.33: 555 timer as Astable multivibrator

The figure 3.33 shows the schematic diagram of astable timer

circuit. It shows only the external components RA , RB and C. The
pin 4 is tied to pin 8 and pin 5 is grounded through a small capacitor.
The important application of astable multivibrator is voltage con-
trolled oscillator (VCO).
Applications of Astable Multivibrator :
1. Square wave generation
2. FSK generator
3. Voltage controlled oscillator (VCO)

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3.10. ASTABLE MULTIVIBRATOR Analog Circuit Design

3.10.1 Types of Data Converters

The electronic circuits, which can be operated with analog signals
are called as analog circuits. Similarly, the electronic circuits, which
can be operated with digital signals are called as digital circuits. A
data converter is an electronic circuit that converts data of one form
to another.
There are two types of data converters –

1. Analog to Digital Converter

2. Digital to Analog Converter

If we want to connect the output of an analog circuit as an input of

a digital circuit, then we have to place an interfacing circuit between
them. This interfacing circuit that converts the analog signal into
digital signal is called as Analog to Digital Converter.
Similarly, if we want to connect the output of a digital circuit
as an input of an analog circuit, then we have to place an inter-
facing circuit between them. This interfacing circuit that converts
the digital signal into an analog signal is called as Digital to Analog
Converter.
Note that some Analog to Digital Converters may require Digital
to Analog Converter as an internal block for their operation.

3.10.2 Specifications of Data Converters

The following are the specifications that are related to data conver-
sions –

1. Resolution

2. Conversion Time

Resolution

Resolution is the minimum amount of change needed in an analog

input voltage for it to be represented in binary (digital) output. It
depends on the number of bits that are used in the digital output.
Mathematically, resolution can be represented as

1
Resolution =
2N
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where, ‘N’ is the number of bits that are present in the digital
output.
From the above formula, we can observe that there exists an in-
verse relationship between the resolution and number of bits. There-
fore, resolution decreases as the number of bits increases and vice-
versa.
Resolution can also be defined as the ratio of maximum analog
input voltage that can be represented in binary and the equivalent
binary number.
Mathematically, resolution can be represented as

VF S
Resolution =
2N − 1
where,
VF S is the full scale input voltage or maximum analog input volt-
age,
‘N’ is the number of bits that are present in the digital output.

Conversion Time

The amount of time required for a data converter in order to convert

the data (information) of one form into its equivalent data in other
form is called as conversion time. Since we have two types of data
converters, there are two types of conversion times as follows :

1. Analog to Digital Conversion time

2. Digital to Analog Conversion time

The amount of time required for an Analog to Digital Converter

(ADC) to convert the analog input voltage into its equivalent binary
(digital) output is called as Analog to Digital conversion time. It
depends on the number of bits that are used in the digital output.
The amount of time required for a Digital to Analog Converter
(DAC) to convert the binary (digital) input into its equivalent analog
output voltage is called as Digital to Analog conversion time. It
depends on the number of bits that are present in the binary (digital)
input.

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3.11. DIGITAL TO ANALOG CONVERTERS Analog Circuit Design

3.11 Digital to Analog Converters

A Digital to Analog Converter (DAC) converts a digital input signal

into an analog output signal. The digital signal is represented with
a binary code, which is a combination of bits 0 and 1.
The block diagram of DAC is shown in the following figure –

Figure 3.34: Digital to Analog Converter

A Digital to Analog Converter (DAC) consists of a number of

binary inputs and a single output. In general, the number of binary
inputs of a DAC will be a power of two.
There are two types of DACs :

1. Weighted Resistor DAC

2. R-2R Ladder DAC

3.11.1 Weighted Resistor DAC

A weighted resistor DAC produces an analog output, which is almost

equal to the digital (binary) input by using binary weighted resistors
in the inverting adder circuit. In short, a binary weighted resistor
DAC is called as weighted resistor DAC.
The circuit diagram of a 3-bit binary weighted resistor DAC is
shown in the following figure –

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Figure 3.35: Weighted Resistor DAC

The bits of a binary number can have only one of the two values.
i.e., either 0 or 1. Let the 3-bit binary input is b2 b1 b0 . Here, the
bits b2 and b0 denote the Most Significant Bit (MSB) and Least
Significant Bit (LSB) respectively.
The digital switches shown in the above figure will be connected to
ground, when the corresponding input bits are equal to ‘0’. Similarly,
the digital switches shown in the above figure will be connected to
the negative reference voltage, −VR when the corresponding input
bits are equal to ‘1’.
In the above circuit, the non-inverting input terminal of an op-
amp is connected to ground. That means zero volts is applied at the
non-inverting input terminal of op-amp.
According to the virtual short concept, the voltage at the invert-
ing input terminal of opamp is same as that of the voltage present
at its non-inverting input terminal. So, the voltage at the inverting
input terminal’s node will be zero volts.
The nodal equation at the inverting input terminal’s node is:

0 + V R b2 0 + V R b1 0 + V R b0 0 − V 0
+ + + =0
20 R 21 R 22 R Rf
V0 V R b 2 V R b1 V R b 0
=> = 0 + 1 + 2
Rf 2R 2R 2R
 
V R R f b2 b1 b 0
=> V0 = + +
R 20 21 22
Substituting, R = 2Rf in above equation.

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3.11. DIGITAL TO ANALOG CONVERTERS Analog Circuit Design

 
V R Rf b2 b1 b 0
=> V0 = + +
2Rf 20 21 22

 
VR b2 b1 b0
=> V0 = + +
2 20 21 22

The above equation represents the output voltage equation of a

3-bit binary weighted resistor DAC. Since the number of bits are
three in the binary (digital) input, we will get seven possible values
of output voltage by varying the binary input from 000 to 111 for a
fixed reference voltage, VR .
We can write the generalized output voltage equation of an N-bit
binary weighted resistor DAC as shown below based on the output
voltage equation of a 3-bit binary weighted resistor DAC.
 
VR bN −1 bN −2 b0
=> V0 = 0
+ 1 + .... + N −1
2 2 2 2

The disadvantages of a binary weighted resistor DAC are as fol-

lows –

1. The difference between the resistance values corresponding to

LSB & MSB will increase as the number of bits present in the
digital input increases.

2. It is difficult to design more accurate resistors as the number of

bits present in the digital input increases.

3.11.2 R-2R Ladder DAC

The R-2R Ladder DAC overcomes the disadvantages of a binary

weighted resistor DAC. As the name suggests, R-2R Ladder DAC
produces an analog output, which is almost equal to the digital (bi-
nary) input by using a R-2R ladder network in the inverting adder
circuit.
The circuit diagram of a 3-bit R-2R Ladder DAC is shown in the
following figure –

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Figure 3.36: R - 2R Ladder Digital to Analog Converter

The bits of a binary number can have only one of the two values.
i.e., either 0 or 1. Let the 3-bit binary input is b2 b1 b0 . Here, the
bits b2 and b0 denote the Most Significant Bit (MSB) and Least
Significant Bit (LSB) respectively.
The digital switches shown in the above figure will be connected to
ground, when the corresponding input bits are equal to ‘0’. Similarly,
the digital switches shown in above figure will be connected to the
negative reference voltage, −VR when the corresponding input bits
are equal to ‘1’.
It is difficult to get the generalized output voltage equation of a R-
2R Ladder DAC. But, we can find the analog output voltage values
of R-2R Ladder DAC for individual binary input combinations easily.
The advantages of a R-2R Ladder DAC are as follows –

1. R-2R Ladder DAC contains only two values of resistor: R and

2R. So, it is easy to select and design more accurate resistors.

2. If more number of bits are present in the digital input, then we

have to include required number of R-2R sections additionally.

Due to the above advantages, R-2R Ladder DAC is preferable

over binary weighted resistor DAC.

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3.12. ANALOG TO DIGITAL CONVERTER Analog Circuit Design

3.12 Analog to Digital Converter

An Analog to Digital Converter (ADC) converts an analog signal
into a digital signal. The digital signal is represented with a binary
code, which is a combination of bits 0 and 1.
The block diagram of an ADC is shown in the following figure –

Figure 3.37: Analog to Digital Converter

Observe that in the figure shown above, an Analog to Digital

Converter (ADC) consists of a single analog input and many binary
outputs. In general, the number of binary outputs of ADC will be a
power of two.
There are two types of ADCs: Direct type ADCs and Indirect
type ADC. This chapter discusses about the Direct type ADCs in
detail.
If the ADC performs the analog to digital conversion directly by
utilizing the internally generated equivalent digital (binary) code for
comparing with the analog input, then it is called as Direct type
ADC.
The following are the examples of Direct type ADCs –
1. Counter type ADC
2. Successive Approximation ADC
3. Flash type ADC

3.12.1 Counter Type ADC

A counter type ADC produces a digital output, which is approxi-
mately equal to the analog input by using counter operation inter-
nally.
The block diagram of a counter type ADC is shown in the follow-
ing figure –

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Figure 3.38: Counter Type ADC

The counter type ADC mainly consists of 5 blocks: Clock signal

generator, Counter, DAC, Comparator and Control logic.
The working of a counter type ADC is as follows –
1. The control logic resets the counter and enables the clock
signal generator in order to send the clock pulses to the counter,
when it received the start commanding signal.
2. The counter gets incremented by one for every clock pulse and
its value will be in binary (digital) format. This output of the
counter is applied as an input of DAC.
3. DAC converts the received binary (digital) input, which is the
output of counter, into an analog output. Comparator compares
this analog value,Va with the external analog input value Vi .
4. The output of comparator will be ’1’ as long as Vi is greater
than. The operations mentioned in above two steps will be
continued as long as the control logic receives ’1’ from the output
of comparator.
5. The output of comparator will be ‘0’ when Vi is less than or
equal to Va . So, the control logic receives ‘0’ from the output
of comparator. Then, the control logic disables the clock signal
generator so that it doesn’t send any clock pulse to the counter.

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3.12. ANALOG TO DIGITAL CONVERTER Analog Circuit Design

6. At this instant, the output of the counter will be displayed as the

digital output. It is almost equivalent to the corresponding
external analog input value Vi .

3.12.2 Successive Approximation ADC

A successive approximation type ADC produces a digital output,
which is approximately equal to the analog input by using successive
approximation technique internally.
The block diagram of a successive approximation ADC is shown
in the following figure –

Figure 3.39: Successive Approximation Analog to Digital Converter

The successive approximation ADC mainly consists of 5 blocks–

Clock signal generator, Successive Approximation Register (SAR),
DAC, comparator and Control logic.
The working of a successive approximation ADC is as follows –

1. The control logic resets all the bits of SAR and enables the
clock signal generator in order to send the clock pulses to SAR,
when it received the start commanding signal.

2. The binary (digital) data present in SAR will be updated for

every clock pulse based on the output of comparator. The out-
put of SAR is applied as an input of DAC.

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3. DAC converts the received digital input, which is the output

of SAR, into an analog output. The comparator compares this
analog value Va with the external analog input value Vi .

4. The output of a comparator will be ‘1’ as long as Vi is greater

than Va . Similarly, the output of comparator will be ‘0’, when
Vi is less than or equal to Va .

5. The operations mentioned in above steps will be continued until

the digital output is a valid one.

The digital output will be a valid one, when it is almost equivalent

to the corresponding external analog input value Vi .

3.12.3 Flash Type ADC

A flash type ADC produces an equivalent digital output for a cor-

responding analog input in no time. Hence, flash type ADC is the
fastest ADC.

The circuit diagram of a 3-bit flash type ADC is shown in the

following figure –

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3.12. ANALOG TO DIGITAL CONVERTER Analog Circuit Design

Figure 3.40: Flash Type Analog to Digital Converter

The 3-bit flash type ADC consists of a voltage divider network, 7

comparators and a priority encoder.
The working of a 3-bit flash type ADC is as follows.
1. The voltage divider network contains 8 equal resistors. A
reference voltage VR is applied across that entire network with
respect to the ground. The voltage drop across each resistor
from bottom to top with respect to ground will be the integer
multiples (from 1 to 8) of V8R .
2. The external input voltage Vi is applied to the non-inverting
terminal of all comparators. The voltage drop across each re-
sistor from bottom to top with respect to ground is applied to
the inverting terminal of comparators from bottom to top.

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CHAPTER 3. OP-AMP NON-LINEAR APPLICATIONSAnalog Circuit Design

3. At a time, all the comparators compare the external input volt-

age with the voltage drops present at the respective other input
terminal. That means, the comparison operations take place by
each comparator parallelly.

4. The output of the comparator will be ‘1’ as long as Vi is

greater than the voltage drop present at the respective other
input terminal. Similarly, the output of comparator will be ‘0’,
when, Vi is less than or equal to the voltage drop present at the
respective other input terminal.

5. All the outputs of comparators are connected as the inputs of

priority encoder. This priority encoder produces a binary
code (digital output), which is corresponding to the high prior-
ity input that has ‘1’.

6. Therefore, the output of priority encoder is nothing but the

binary equivalent (digital output) of external analog input
voltage, Vi .

The flash type ADC is used in the applications where the conver-
sion speed of analog input into digital data should be very high.

3.12.4 Dual Slope ADC

As the name suggests, a dual slope ADC produces an equivalent

digital output for a corresponding analog input by using two (dual)
slope technique.
The block diagram of a dual slope ADC is shown in the following
figure –

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3.12. ANALOG TO DIGITAL CONVERTER Analog Circuit Design

Figure 3.41: Dual Slope Analog to Digital Converter

The dual slope ADC mainly consists of 5 blocks: Integrator, Com-

parator, Clock signal generator, Control logic and Counter.
The working of a dual slope ADC is as follows –
1. The control logic resets the counter and enables the clock
signal generator in order to send the clock pulses to the counter,
when it is received the start commanding signal.
2. Control logic pushes the switch sw to connect to the external
analog input voltage Vi , when it is received the start com-
manding signal. This input voltage is applied to an integrator.
3. The output of the integrator is connected to one of the two
inputs of the comparator and the other input of comparator is
connected to ground.
4. Comparator compares the output of the integrator with zero
volts (ground) and produces an output, which is applied to the
control logic.
5. The counter gets incremented by one for every clock pulse
and its value will be in binary (digital) format. It produces an
overflow signal to the control logic, when it is incremented after

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reaching the maximum count value. At this instant, all the bits
of counter will be having zeros only.
6. Now, the control logic pushes the switch sw to connect to the
negative reference voltage −Vref . This negative reference
voltage is applied to an integrator. It removes the charge stored
in the capacitor until it becomes zero.
7. At this instant, both the inputs of a comparator are having zero
volts. So, comparator sends a signal to the control logic. Now,
the control logic disables the clock signal generator and retains
(holds) the counter value. The counter value is proportional
to the external analog input voltage.
8. At this instant, the output of the counter will be displayed as
the digital output. It is almost equivalent to the corresponding
external analog input value Vi .
The dual slope ADC is used in the applications, where accuracy
is more important while converting analog input into its equivalent
digital (binary) data.

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Chapter 4

Voltage Regulators

A voltage regulator is an electronic circuit that provides a constant

d.c. output voltage independent of the change in load current, tem-
perature and a.c. line voltage variations.
Voltage regulators are classified as :

1. Series Regulator

2. Switching Regulator

4.1 Series OP-AMP Regulator

1. A voltage regulator is an electronic circuit that provides a con-
stant d.c. output votlage independent of the change in the load
current, temperature and a.c. line voltage variations.
Figure ?? shows a regulated power supply. The circuit consists
of four major components.

(a) Reference Voltage Vref [Zener diode]

(b) Error amplifier [Difference amplifier]
(c) Series pass transistor Q1
(d) Feedback network [R1 and R2 ]

2. The power transistor Q1 is in series with the unregulated d.c.

voltage Vin and the regulated output voltage Vo . Any variation
in output voltage is absorbed by this transistor.

3. The transistor Q1 connected as an emitter follower and therefore

provide sufficient current gain to drive the load.

97
4.2. IC VOLTAGE REGULATOR Analog Circuit Design

4. The output voltage is sampled by potential divider R1 and R2

(feedback newtork) and fed back to the INV input terminal of
the OP-AMP error amplifier.

5. The sampled voltage is compared with the reference voltage

Vref . The output Vo′ of the error amplifier drives the series
transistor Q1 .
When the output voltage tends to increase, then the feedback
R2
voltage βVo also increases, where β = .
R1 + R2
6. The votlage at INV input terminal of OP-AMP increases and
as a result the output voltage Vo′ of the OP-AMP decreases.
Since Q acts as emitter follower, the output votlage Vo which
follows Vo′ , thus the Vo also reduces. Thus the output voltage
Vo remains constant.

4.2 IC Voltage Regulator

IC voltage regulator replaces discrete component circuits OP-AMP
regulator with IC, which gives low cost, high reliability, reduction in
size and excellent performance.
E.g.

1. 78XX — 79XX – Fixed voltage series regulators

2. 723 – General purpose regulators

4.2.1 Fixed Voltage Series Regulator

78XX series are three terminal positive fixed voltage regulators.
In 78XX, the last two numbers ’XX’ indicate the output voltage.

Table 4.1: Series of fixed voltage series regulator

Series Output Voltage
7805 +5V
7806 +6V
7808 +8V
7812 + 12 V
7815 + 15 V
7818 + 18 V
7824 + 24 V

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CHAPTER 4. VOLTAGE REGULATORS Analog Circuit Design

79XX series are three terminals negative fixed voltage regu-

lators. In 79XX, the last two numbers ’XX’ indicate the output
voltage. In 79XX series two extra voltage options of -2 V and - 5.2
V available.
The regulators are available in two types of package :

1. Metal Package

2. Plastic Package

Figure ?? shows the standard representation of IC voltage regula-

tor. The capacitor Ci is usually connected between input and ground
terminal to cancel the inductive effect due to long leads. The output
capacitor Co improves the transient response.

4.2.2 Characteristics of IC Regulators

There are four characteristics of three terminal IC regulators :

1. Vo (Regulated output voltage) : The regulated output volt-

age is fixed at a value as specified by the manufacturer. There
are various models available with different output voltages.
E.g. 78XX series has output voltage at 5,6,8,12,15,18 V etc.

2. |Vin | ≥ |Vo | + 2volts : The unregulated input voltage must be

atleast 2 V more than the regulated output voltage.
For example, if Vo = 5V , then Vin = 7V .

3. Maximum Output Current Io(max) : The load current may

vary from 0 to rated maximum output current. The IC is usually
provided with a heat sink, ohterwise it may not provide the
rated maximum output current.

4. Thermal Shutdown : The IC has a built-in termperature

sensor which turn-off the IC when it becomes too hot. the
output current will drop and remains there until the IC has
cooled significantly

4.2.3 Limitations of IC Voltage Regulator

1. No Short circuit protection.

2. Output voltage is fixed.

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4.2. IC VOLTAGE REGULATOR Analog Circuit Design

4.2.4 Advantages of IC Voltage Regulator

1. Easy to use.
2. Simplifies power supply design.
3. Low Cost.
4. Conveniently used for local regulations.
5. Over-current protection.
6. Thermal Overload protection.

4.2.5 Important Performance Parameter

The important performance parameters of a 3-terminal IC regulators
are :
1. Line/Input Regulation
2. Load Regulation
3. Ripple Rejection
Line Regulation :
It is defined as the percentage change in the output voltage for a
change in the input voltage. It is usually expressed in milli-volt or
as percentage of the output voltage. Typical value of line regulation
from the data sheet of 7805 is 3 mV.
Load Regulation :
It is defined as the change in output voltage for a change in load
current and is also expressed in milli-volts or as percentage of Vo .
For 7805 regulator, the load regulation is 15 mV for a load current
variation for 5 mA to 1.5 amp.
Ripple Rejection :
The IC regulator not only keeps the Output voltage constant but
also reduces the amount of ripple voltage. It is usually expressed in
dB. For 7805, it is 78 dB.

4.2.6 IC Regulator as a Current Source

The three terminal fixed voltage regulator can be used as a current
source as shown in figure ??. From the circuit, it is clear that,
IL = IR + IQ (4.1)

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CHAPTER 4. VOLTAGE REGULATORS Analog Circuit Design

where, IQ is the quiscent current.

For 7805, IQ = 4.2 mA.
The IR is given by –
VR
IR = (4.2)
R
Substituting equation 4.2 in 4.1, we get,
VR
IL = + IQ (4.3)
R
In equation 4.3, VR , IQ are constant, R can be selected to provide a
sufficient current. Thus 78XX can be used as current source.

4.2.7 Boosting IC Regulator Output Current

It is possible to boost the output current of a three terminal regulator
simply by connecting an external pass transistor in parallel with the
regulator as shown in figure ??.
For low load currents, the voltage drop across R1 is insufficient
(i.e. VBE < 0.7V ) to turn ON transistor Q1 and the regulator itself
is able to supply the load current. However when IL increases, the
voltage drop across R1 increases. When this voltage drop (i.e. VBE =
0.7V ) the transistor Q1 turn ON and transistor Q1 supplies the extra
current needed to drive low resistance load.
Applying KCL at node B, we get,

IC + Io − IL = 0 (4.4)
IL = Io + IC (4.5)

We know that, IC = βIB

For regulator (for 7805)

Ii = IQ + Io (4.6)

Since, IQ is very small, we can neglect it,

∴ Ii = Io (4.7)

Applying KCL at node A, we get,

IR1 + IB − Ii = 0 (4.8)
IB = Ii − IR1 (4.9)

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4.2. IC VOLTAGE REGULATOR Analog Circuit Design

We know that,
VEB(ON )
IR1 = (4.10)
R1
Substituting equation 4.3 and IR1 value in equation in equation 4.9,
we get,
VEB(ON )
IB = Io − (4.11)
R1
We know that, IC = βIB .
Substituting IB value we get,
 
VON
IC = β Io − (4.12)
R1
VEB(ON )
∴ IC = βIo − β (4.13)
R1
Substituting equation 4.13 in equation 4.5, we get,
VEB(ON )
IL = Io + βIo − β (4.14)
R1
VEB(ON )
∴ IL = Io (1 + β) − β (4.15)
R1
Example 4.1 Using 7805, design a current source to deliver 0.2 A
curret to a 22 Ω, 10 W load. Take quiscent current as 4.2 mA.

Ans : Given : IL = 0.2A, RL = 22Ω

For 7805 : Vo = VR = 5V and IQ = 4.2 mA
From Figure,
VR
IL = + IQ
R
VR
∴R=
IL − IQ
5
∴R=
0.2 − 4.2 × 10−3
∴ R = 25.53Ω

Vo = VR + VL
∴ Vo = 5 + I L RL
∴ Vo = 5 + 0.2 × 22
∴ Vo = 9.4V

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CHAPTER 4. VOLTAGE REGULATORS Analog Circuit Design

Example 4.2 For the current booster circuit using 7805, calculate
the output current coming from 7805 IC and coming from transistor
Q1 for loads 100 Ω, 5 Ω, 1 Ω. Assume VBE(ON ) = 1V, β = 15, R1 =
7Ω

Ans : Given : VBE(ON ) = 1V , β = 15, R1 = 7Ω

For 7805 : Vo = 5V

1. RL = 100Ω
Vo 5
IL = =
RL 100
∴ IL = 50mA
Now VEB = IL × R1
∴ VEB = 50 × 10−3 × 7
∴ VEB = 0.35V
Since, VEB < 0.7V , Hence Q1 is OFF. So Io = IL = Ii = 50mA.
2. RL = 5Ω
Vo 5
IL = =
RL 5
∴ IL = 1A
Now VEB = IL × R1
∴ VEB = 1 × 7
∴ VEB = 7V
Since, VEB > 0.7V , ∴ Q1 is ON.
Now,
VEB(ON )
IL = (1 + β)Io − β
R1
VEB(ON )
IL + β R1
∴ Io =
(1 + β)
1 + 15 × 17
∴ Io =
1 + 15
∴ Io = 196mA

IC = IL − Io = 1 − 196 × 10−3
∴ IC = 804mA

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4.2. IC VOLTAGE REGULATOR Analog Circuit Design

3. RL = 1Ω
Vo 5
IL = =
RL 1
∴ IL = 5A
Now VEB = IL × R1
∴ VEB = 5 × 7
∴ VEB = 35V

Since, VEB > 0.7V , ∴ Q1 is ON.

Now,
VEB(ON )
IL = (1 + β)Io − β
R1
VEB(ON )
IL + β R1
∴ Io =
(1 + β)
5 + 15 × 17
∴ Io =
1 + 15
∴ Io = 446mA

IC = IL − Io = 5 − 446 × 10−3
∴ IC = 4.55A

4.2.8 Fixed Regulator used as Adjustable Regulator

Fixed regulator can be made use as a variable regulated voltage
regulator. The circuit is shown in figure ??.
The output voltage of the circuit is,

Vo = VR + VP OT (4.16)
∴ Vo = VR + (IQ + IR1 )R2 (4.17)
∴ Vo = VR + IQ R2 + IR1 R2 (4.18)
VR
∴ V o = V R + I Q R2 + R2 (4.19)
  R 1
R2
∴ Vo = VR 1 + + I Q R2 (4.20)
R1
where, VR is the regulated voltage difference between the OUT and
GND terminals.

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CHAPTER 4. VOLTAGE REGULATORS Analog Circuit Design

The effect of IQ is minimized by choosing R2 as small as possible

(i.e. neglecting IQ R2 ). The minimum output voltage of the ad-
justable regulator is the value of the fixed voltage available from the
regulator. Hence neglecting IQ R2 , it is possible to get an adjustable
regulated voltage of any value.

Example 4.3 Specify suitable component values to get Vo = 7.5V

using a 7805 regulator.

Ans : Given Data : Vo = 7.5V

For 7805, output voltage is 5 V, i.e. VR = 5V and IQ = 4.2mA.
Assume, IR1 = 25 mA

VP OT = Vo − VR = 7.5 − 5
∴ VP OT = 2.5V

VR 5
R1 = = = 200Ω
IR1 25 × 10−3

VP OT 2.5
R2 = = = 85.6Ω
IQ + IR1 (4.2 + 25) × 10−3
Choose R2 = 86Ω

Example 4.4 Design a 7805 regulator to get the output Vo = 6.5V .

Ans : Given Vo = 6.5 V

For 7805, output voltage is 5 V i.e. VR = 5V and IQ = 4.2mA
Assume, IR1 = 25 mA

VP OT = Vo − VR = 6.5 − 5
∴ VP OT = 1.5V

VR 5
R1 = = = 200Ω
IR1 25 × 10−3

VP OT 1.5
R2 = = = 51.37Ω
IQ + IR1 (4.2 + 25) × 10−3
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4.3. 723- GENERAL PURPOSE REGULATOR Analog Circuit Design

4.2.9 Dual Voltage Supply

Three terminal fixed voltage regulators can be used to provide dual
power supply required for OP-AMP. The circuit ?? shows a bipolar
±15V supply provided by two fixed voltage regulators LM340-15 and
LM-320-15.
The LM 340-15 is a +15 V regulator and LM 320-15 is a -15 V
regulator. The pin configuration of LM340 and LM320 is different.
The diodes D1 and D2 in the circuit protect the regulator against
short circuit occuring at its input terminals. Diodes D3 and D4
provide protection against the situation when both the regulators
may not turn ON simultaneously.
If there is a load between two outputs, the faster one will reverse
the polarity of other and cause it to latch up unless it is properly
clamped and this clamping is done by the diodes.
Once the regulator starts operating properly, diodes are reverse
biased and have no effect on circuit.

4.2.10 Demerits of 3-terminal IC regulators

The three terminal IC regulators have the following limitations :
1. No short circuit protection.
2. Output voltage is fixed (either Positive or negative).

4.3 723- General Purpose Regulator

1. IC 723 is a general purpose regulator, which can be adjusted
over a wide range of both +ve and -ve regulated output voltage.
2. IC 723 has a limitation that it has no inbuilt thermal protection.
It also has no short circuit limits.
3. The functional diagram of IC 723 is as shown in figure ?? below
:
4. IC 723 has two sections. The section-1 has zener diode, a con-
stant current source and reference amplifier produces a fixed
voltage of 7 V at Vref terminal.
5. The constant current source forces the zener to operate at fixed
point so that the zener outputs a fixed voltage.

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CHAPTER 4. VOLTAGE REGULATORS Analog Circuit Design

6. The section-2 consists of an error amplifier, a series pass tran-

sistor Q1 and a current limit transistor Q2 . The error amplifier
compares a sample of the output voltage applied at the INV
terminal with that of reference voltage (Vref ) applied at the
Non-INV terminal.

7. The error signal controls the conduction of Q1 . These two sec-

tions are internally not connected but are available or 723 IC
regulator.

4.3.1 IC-723 Pin Diagram

IC-723 regulator is available in a 14 pin Dual-in-line package and 10
pin metal-can package as shown in figure 4.1.

Figure 4.1: Pin diagram of IC-723

4.3.2 Salient Features of IC 723 Regulator

The salient features of a 723 regulator are :

1. It works as voltage regulator at output voltage ranging from 2

V to 37 V at currents upto 150 mA.

2. Input and output short circuit protection is provided.

3. It has good line and load regulation.

4. Low temperature drift and high ripple rejection.

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4.3. 723- GENERAL PURPOSE REGULATOR Analog Circuit Design

5. Low standby current drain.

6. Small size, lower cost.

7. It can be used at load currents greater than 150 mA with ex-

ternal pass transistor.

4.3.3 Low Voltage Regulator using 723-IC

The simple positive low voltage (2 V to 7 V) regulator can be made
using 723 as shown in figure ??.
The voltage at the Non-INV terminal of the error amplifier due
to R1 and R2 is –
R2
VN I = Vref × (4.21)
R1 + R2
The difference between the voltage at NON-INV terminal and
output voltage Vo (directly fed back) at INV terminal are the inputs
to the error amplifier.
The output of the error amplifier drives the pass transistor Q1 .
Since Q1 is operating as emitter follower

R2
Vo = Vref × (4.22)
R1 + R 2

If output voltage becomes low i.e. voltage at INV terminal goes

down, this makes the output of the error amplifier to be more pos-
itive, thereby increasing the conduction of pass transistor Q1 and
thus output voltage across load increases. Thus initial drop in volt-
age is compensated. Similarly any increase in load voltage or change
in input voltage gets regulated.
The reference voltage is typically 7.15 V, so output voltage is –

R2
Vo = 7.15 × (4.23)
R1 + R2
So output voltage will always less than 7.15 V. Thus figure ?? is
used as low voltage regulator.

Example 4.5 Design a voltage regulator using IC723 to get a volt-

age output of 3 V.

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CHAPTER 4. VOLTAGE REGULATORS Analog Circuit Design

Ans : Vo = 3V We know that, Vref = 7V

We know that,
R2
Vo = Vref times
R1 + R2
R2
∴3=7×
R1 + R2
∴ 3R1 + 3R2 = 7R2
∴ 4R2 = 3R1
3
∴ R2 = R1
4
Assume R1 = 10kΩ
3
∴ R2 = × 10kΩ
4
∴ R2 = 7.5kΩ

R3 = R1 ||R2
R1 × R2
∴ R3 =
R1 + R2
10 × 103 × 7.5 × 103
∴ R3 =
10 × 103 + 7.5 × 103
∴ R3 = 4.2kΩ
Example 4.6 Design a voltage regulator using IC 723 to get a volt-
age output of 5 V.
Ans : Vo = 5V We know that, Vref = 7V
We know that,
R2
Vo = Vref times
R1 + R2
R2
∴5=7×
R1 + R2
∴ 5R1 + 5R2 = 7R2
∴ 5R1 = 2R2
5
∴ R2 = R1
2
Assume R1 = 10kΩ
5
∴ R2 = × 10kΩ
2
∴ R2 = 25kΩ

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4.3. 723- GENERAL PURPOSE REGULATOR Analog Circuit Design

R3 = R1 ||R2
R1 × R2
∴ R3 =
R1 + R2
10 × 103 × 25 × 103
∴ R3 =
10 × 103 + 25 × 103
∴ R3 = 7.14kΩ

4.3.4 IC 723 as High Voltage Regulator (Vo > 7V )

Figure ?? show the basic high voltage 723 voltage to get output
voltage greater than 7 V.
The NON-INV terminal is directly connected to Vref through R3 .
Hence voltage at NON-INV terminal is –

VN I = Vref = 7.15V (4.24)

The error amplifier acts as NON-INV amplifier with a voltage

gain of –
R1
Av = 1 + (4.25)
R2

The output voltage of the circuit is –

 
R1
Vo = 7.15 1 + (4.26)
R2

Thus regulated output voltage is greater than 7.15 V.

Example 4.7 Design a high voltage regulator using IC 723 so as to

get an output votlage of 25 V.

Ans : Vo = 25V
Assume, Vref = 7V

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CHAPTER 4. VOLTAGE REGULATORS Analog Circuit Design

We know that,

 
R1
Vo = Vref 1 +
R2
 
R1
∴ 25 = 7 1 +
R2
 
25 R1
∴ = 1+
7 R2
 
R1
∴ 3.57 = 1 +
R2
R1
∴ = 2.57
R2
∴ R1 = 2.57R2
Assume R2 = 10kΩ
∴ R1 = 2.57 × 10kΩ
∴ R1 = 25.7kΩ

R3 = R1 R2
∴ R3 = 25.7 × 103 × 10 × 103
∴ R3 = 257.14M Ω

Example 4.8 Design a high voltage regulator to get a output voltage

of 28 volts.

Ans : Vo = 28V
Assume, Vref = 7V

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4.3. 723- GENERAL PURPOSE REGULATOR Analog Circuit Design

We know that,
 
R1
Vo = Vref 1 +
R2
 
R1
∴ 28 = 7 1 +
R2
 
28 R1
∴ = 1+
7 R2
 
R1
∴4= 1+
R2
R1
∴ =3
R2
∴ R1 = 3R2
Assume R2 = 1kΩ
∴ R1 = 3 × 1kΩ
∴ R1 = 3kΩ

R3 = R 1 R2
∴ R3 = 3 × 103 × 1 × 103
∴ R3 = 3M Ω

4.3.5 Current Limit Protection

The low and high voltage regulators using 723 IC have no short cir-
cuit protection. If the IC tries to drive very large current at constant
output voltage then the IC gets hotter and may burn out.
The IC is therefore, provided with a current limit facility. The
ability of the regulator to prevent the load current from increasing
beyond certain limit is called ’Current limiting’ and is denoted by
Ilimit .
The output voltage remains constant for load current below Ilimit .
As the current approaches to the limit, the output voltage drops to
zero, as shown in figure ??. The current limit Ilimit is set by con-
necting an external resistor RSC between the terminals CL and CS
terminals as shown in figure ??. The CL terminal is also connected
to the output terminal Vo and CS terminal to the load.
The load current produces a small voltage drop Vsense across RSC ,
when Vsense ≈ 0.5V , the transistor Q2 begins to turn ON (since
Vsense = VBE2 ). Now current IC2 starts flowing into the collector

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CHAPTER 4. VOLTAGE REGULATORS Analog Circuit Design

of Q2 and the base current to Q1 reduces. As a result, the emitter

current of Q1 also decreases i.e. load current is decreased. So any
increase in the load current will get nullified and vice versa.
We know that,

Vsense = VBE2 = 0.5V (4.27)

Vsense
Ilimit = (4.28)
RSC
Vsense
RSC = (4.29)
Ilimit

Example 4.9 Design a current limit circuit for a 723 regulator to

limit the current of 60 mA.

Ans : ISC = 60mA, Assume Vsense = 0.5V

we know that,

Vsense 0.5
RSC = =
Ilimit 60 × 10−3
∴ RSC = 8.33Ω

4.3.6 Current Foldback

If the load is short circuited, the voltage Vo becomes zero and a

large current flows through the regulator. To protect the regulator,
current foldback method is used.
Figure ?? shows the current foldback characteristics curve. When
load goes on increasing, the output voltage Vo is held constant till a
value Iknee . Once the load current tries to increase beyond this, the
current foldback circuit decreases both output voltage and output
current.
Figure ?? shows the current foldback circuit. The voltage oat
base of Q2 is divided by R3 − R4 network. Q2 conducts only when
VBE2 = 0.5V i.e. the voltage drops across RSC .
As Q2 conducts, IC2 flows more and thereby decreasing IB1 . Thus
Q1 turns off and IC decreases. This decreases V1 , thus voltage at base
VR4
of Q2 also drops i.e. . This process continues till Vo = 0V
R4 + R3
and V1 is equal to 0.5 V.

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 Analog Circuit Design
4.4. LIMITATIONS OF LINEAR VOLTAGE REGULATORS

4.3.7 Current Boosting in 723 IC

The maximum current that 723 IC regulator can provide is 140 mA.
For many applications this current is not sufficient. It is possible to
boost the current level by adding a boost transistor Q1 to the voltage
regulator as shown in figure ??.
The unregulated d.c. supply Vin supplies the collector current
to Q1 . The output current from pin-10 is connected to the base of
pass transistor Q1 . This base current gets multiplied by β of pass
transistor Q1 .
IL = β × Io(723) (4.30)
Note :
1. β varies from 15 to 50.
2. Io(723) = 140 mA

4.4 Limitations of Linear Voltage Regulators

1. The regulated input step down transformer is bulky and expen-
sive.
2. Due to low line frequency (50 Hz), large values of filter capaci-
tors are required.
3. The efficiency is very low.
4. Input must be greater than the output voltage.
5. As large is the difference between input and output voltage,
more is the power dissipation in the series pass transistor.
6. For higher input voltages, efficiency decreases.
7. The need for dual supply is not economical and flexible to
achieve with the help of linear regulators.

4.5 Switching Regulator or Switched Mode Power

Supply
In switching regulator, the pass transistor is used as a ’Controlled
Switch’ and is operated at either cut-off or saturated state. Hence
power transmitted across the transistor is in discrete pulses.

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CHAPTER 4. VOLTAGE REGULATORS Analog Circuit Design

When the transistor is in cut-off region, there is no current and

dissipates no power. When the transistor is in saturation region, a
negligible voltage drop appears across it and thus power dissipation is
very less. Hence power transmitted increases and also the efficiency
(70 % to 90 %).
Switching regulator uses concept of pulse width modulation to
control the average value of output voltage.
If the duty cycle varied as shown in figure ??, the average value
of the voltage changes with respect to duty cycle.
tON
∴ Duty Cycle = (4.31)
tON + tOF F
Figure ?? shows the switching power supply. The bridge rectifier
and capacitor filters are connected directly to the a.c. line to give
unregulated d.c. input. The thermistor Rt limits the high initial
capacitor charge current.
Transistors Q1 and Q2 are alternatively switched OFF and ON
at 20 kHz. These transistors are either fully ON or cut-off, so they
dissipate very little power. The transistors Q1 and Q2 drives the
primary of the main transformer. The secondary is centre tapped
and full wave rectification is achieved by diodes D1 and D2 . This
unidirectional square wave is next filtered through a two stage LC
filter to produce output voltage Vo .
The regulation of Vo is achieved by the feedback circuit consisting
of a pulse width modulation and steering logic circuit.
R2
The fraction of the output i.e. Vo is feedback to the INV
R1 + R2
input of the comparator 1 and is compared with a fixed reference
voltage Vref in comparator–1.
The output of comparator–1 is called Vcontrol and is applied to the
negative input terminal of comparator–2 and a triangular waveform
of frequency 40 kHz is applied at the +ve input terminal. (It may
be noted that a high frequency triangular waveform is being used to
reduce the ripple).
The comparator–2 functions as a pulse width modulator and its
output is a square wave VA of period T.
TON
The duty cycle of the square wave is and varies with
TON + TOF F
Vcontrol which in turn varies with the variation of output Vo . The
output VA drives a steering logic circuit shown in shaded blocks.

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 Analog
4.5. SWITCHING REGULATOR OR SWITCHED MODE POWERCircuit Design
SUPPLY

The output VA1 and VA2 of AND gates A1 and A2 are shown in
figure ??. These waveforms are applied at the base of transistor Q1
and Q2 . Depending upon whether Q1 or Q2 is ON, the waveform at
the input of the transformer will be a square wave as shown in figure
??. The rectified output VB is shown in figure ??.
by using switch (transistor) with low losses and a filter with high
quality factor, the conversion efficiency can easily exceed 90 %.
If there is a rise in d.c. output voltage Vo , the voltage control
Vcontrol of the comparator–1 also rises. Now time period T1 decreases.
This inturn decreases the pulse width of the waveform driving the
main power transformer.
Reduction in pulse width lowers the average value of the d.c.
output voltage Vo . Thus the initial rise in the d.c. output votlage Vo
has been nullified.

4.5.1 Advantages of SMPS

1. Efficiency is high (70 % to 90 %).

2. Decrease in size and cost.

3. The high operating frequency used for the switching transistor

allows the use of smaller transformer.

4. The power dissipation of pass transistor is very small.

5. Small output filters.

4.5.2 Disadvantages of SMPS

1. Design is complex.

2. Ripple voltage is higher compared to linear regulator.

3. The response to load variations is not fast as compared to linear

regulators.

4. Electromagnetic and radio frequency interference occurs..

5. A switch mode power supply requires external components like

inductors and transformers.

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CHAPTER 4. VOLTAGE REGULATORS Analog Circuit Design

4.5.3 Comparison of Linear regulators and Switching

regulators
S.N. Linear Regulator Switching Regulator
(SMPS)
1 Efficiency is low. Efficiency is high.
2 Cost is low. Cost is high.
3 Design is simple. Design is complex.
4 Ripples are less at output. Ripples are more at output.
5 Power handling capacity is Power handling capacity is
low. high.
6 No switching losses. Switching losses are high.
7 Response to load variation Response to load variation
is fast. is slow.
8 Weight is high. It is light in weight.
9 Due to low line frequency High switching frequency
large filter capacitors are re- allows small values of choke
quired. and capacitor.
10 Power transmitted across a Power transmitted across a
transistor is in linear fash- transistor is in the form of
ion. discrete pulse.
11 Series pass transistor does Series pass transistor acts as
not act as a switch. a switch.

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 Analog
4.5. SWITCHING REGULATOR OR SWITCHED MODE POWERCircuit Design
SUPPLY

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Chapter 5

Design of Sinusoidal Oscillators

and Function Generator

5.1 RC Phase Shift Oscillator

RC Phase Shift Oscillator basically consists of an amplifier and a
feedback network consisting of resistors and capacitors arranged in
ladder fashion. Hence such an oscillator is also called ladder type
RC Phase Shift Oscillator.
To understand the operation of this oscillator let us study RC
circuit first, which is used in the feedback network of this oscillator.
The figure 5.1 shows the basic RC circuit.

Figure 5.1: RC network and its phasor diagram

The capacitor C and resistance R are in series. Now Xc is the

capacitive reactance in ohms given by,
1
XC = Ω (5.1)
2πf C
The total impedance of the circuit is,
 
1
Z = R − jXC = R − j Ω = |Z|∠0o Ω (5.2)
2πf C
119
5.1. RC PHASE SHIFT OSCILLATOR Analog Circuit Design

The r.m.s. value of the input voltage applied is say Vi volts. Hence
the current is given by,

Vi ∠0o Vi ∠0o
I= = (5.3)
Z |Z|∠ − φ
Vi
∴I = ∠+φ (5.4)
Z
q
where, |Z| = R2 + XC2 (5.5)
 
−1 XC
and, φ = tan (5.6)
R

From expression of current it can be seen that current I leads

input voltage Vi by angle φ
The output voltage V is the drop across resistance R given by,

Vo = VR = IR (5.7)

The voltage across the capacitor is,

VC = IXC (5.8)

The drop VR is in phase with current I while the drop Vc lags current
I by 90o i.e. I leads Vc by 90o . The phasor diagram is shown in the
figure 5.1(b).
By using proper values of R and C, the angle is adjusted in prac-
tice equal to 60o
RC Feedback Section :
As stated earlier, RC network is used in feedback path. In oscillator,
feedback network must introduce a phase shift of 1800o to obtain
total phase shift around a loop as 360o . Thus if one RC network
produces phase shift of 4) = 60o then to produce phase shift of 180o
such three RC networks must be connected in cascade.
Hence in RC phase shift oscillator, the feedback network consists
of three RC sections each producing a phase shift of 60o , thus total
phase shift due to feedback is 180o (3x 60o ). Such a feedback network
is shown in the Fig. 5.2

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CHAPTER 5. DESIGN OF SINUSOIDAL OSCILLATORS AND FUNCTION
GENERATOR Analog Circuit Design

Figure 5.2: Feedback newtork of RC Phase Shift Oscillator

The network is also called the ladder network. All the resistance
values and all the capacitance values are same, so that for a par-
ticular frequency, each section of R and C produces a phase shift
of60o .
RC Phase Shift Oscillator using OP-AMP :
R-C phase shift oscillator using op-amp uses op-amp in inverting
amplifier mode. Thus it introduces the phase shift of 180o between
input and output. The feedback network consists of 3 RC sections
each producing 60o phase shift. Such a RC phase shift oscillator
using op-amp is shown in the Fig. 5.3.

Figure 5.3: RC Phase Shift Oscillator using OP-AMP

The output of amplifier is given to feedback network. The Out-

put of feedback network drives the amplifier. The total phase shift
around a loop is 180o of amplifier and 180o due to 3 RC section, thus
360o . This satisfies the required condition for positive feedback and
circuit works as an oscillator.

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5.2. WIEN BRIDGE OSCILLATOR Analog Circuit Design

The frequency of sustained oscillations generated depends on the

values of R and C and is given by,
1
f= √ (5.9)
2π 6RC
At this frequency the gain of the op-amp must be at least 29 to
satisfy Aβ = 1. Now gain of the op-amp inverting amplifier is given
by,
Rf
|A| ≥ ≥ 29for oscillations (5.10)
R1
Rf ≥ 29R1 (5.11)

Thus circuit will work as an oscillator which will produce a si-

nusoidal waveform if gain is 29 and total phase shift around a loop
is 360o . This satisfies the Barkhausen criterion for the oscillator.
These oscillators are used over the audio frequency range i.e. about
20 Hz upto 100 kHz.
Advantages :
1. The circuit is simple to design.
2. Can produce output over audio frequency range.
3. Produces sinusoidal output waveform.
4. It is a fixed frequency oscillator.
Disadvantages :
By changing the values of R and C, the frequency of the oscillator
can be changed. But the values of R and C of all three sections must
be changed simultaneously to satisfy the oscillating conditions. But
this is practically impossible. Hence the phase shift oscillator is
considered as a fixed frequency oscillator, for all practical purposes.
And the frequency stability is poor due to the changes in the
values of various components, due to effect of temperature, aging
etc.

5.2 Wien Bridge Oscillator

This is also RC oscillator which uses RC type of feedback network.
The main difference between phase shift and Wien bridge oscillator is

PBCOE, Nagpur 122 Dr. P.R. Bokde

CHAPTER 5. DESIGN OF SINUSOIDAL OSCILLATORS AND FUNCTION
GENERATOR Analog Circuit Design

that the R-C phase shift oscillator introduces 180o phase shift during
the amplifier stage, while Wien bridge oscillator uses a non-inverting
amplifier. So in Wien bridge type there is no phase shift necessary
through the feedback network. Let us see the basic version of the
Wien bridge oscillator and its analysis.

Figure 5.4: Basic Circuit of Wien Bridge Oscillator

A basic Wien bridge and an amplifier stage is shown in the Fig.

5.4.

The output of the amplifier is applied between the terminals 1 and

3, which is the input to the feedback network. While the amplifier
input is supplied from the diagonal terminals 2 and 4, which is the
output from the feedback network. Thus amplifier supplies its own
input through the Wien bridge as a feedback network.

The two arms of the bridge, namely R1 , C1 in series and R2 , C2

in parallel are called frequency sensitive arms. This is because the
components of these two arms decide the frequency of the oscilla-
tor. Such a feedback network is called lead–lag network. This is
because at very low frequencies it acts like a lead while at very high
frequencies it acts like lag network.

Wien Bridge Oscillator using OP-AMP

The Fig. 5.5 shows the Wien bridge oscillator using an op-amp.

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5.2. WIEN BRIDGE OSCILLATOR Analog Circuit Design

Figure 5.5: Wien Bridge Oscillator using OP-AMP

The resistance R and capacitor C are the components of frequency

sensitive arms of the bridge. The resistance Rf and R1 form the
part of the feedback path. The gain of noninverting op-amp can be
adjusted using the resistance Rf and R1 . The gain of op-amp is,
Rf
A=1+ (5.12)
R1
To satisfy Barkhausen criterion that Aβ = 1 it is necessary that
the gain of the noninverting op-amp amplifier must be minimum 3.
Rf
|A| ≥ 3 i.e.1 + ≥3 (5.13)
R1
Rf
≥2 (5.14)
R1
Thus ratio of Rf and R1 must be greater than or equal to 2.
The frequency of oscillations is given by,
1
f= (5.15)
2πRC
The feedback is given to the noninverting terminal of op-amp
which ensures zero phase shift. It is used popularly in laboratory
signal generators.
If in a Wien bridge feedback network, two resistances are not
equal i.e. they are R1 and R2 while two capacitors are not equal i.e.
they are C1 and C2 then the frequency of oscillations is given by,
1
f= √ (5.16)
2π R1 R2 C1 C2
Advantages :

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CHAPTER 5. DESIGN OF SINUSOIDAL OSCILLATORS AND FUNCTION
GENERATOR Analog Circuit Design

1. By varying the two capacitor values simultaneously, by mount-

ing them on the common shaft, different frequency ranges can
be obtained.
2. The perfect sine wave output is possible.
3. It is useful audio frequency range i.e. 20 Hz to 100 kHz.
Disadvantages :
If instead of OP-AMP, transistorized amplifier is to be used then
more stages are required to obtain 0o phase shift between input and
output. This increases the number of components and cost. The
frequency stability is poor.

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5.2. WIEN BRIDGE OSCILLATOR Analog Circuit Design

PBCOE, Nagpur 126 Dr. P.R. Bokde

Chapter 6

Filters

Filters are circuits that pass only a desired band of frequencies and
attenuates the undesired band of frequencies.
The filters are classified as :
1. Low Pass Filter
2. High Pass Filter
3. Band Pass Filter
4. Band Elimination or Band Reject or Band Stop Filter
Filters can be of passive or active type. Passive filters use only
passive components such as resistors, capacitors and inductors. Ac-
tive filters use transistor or OP-AMPs together with passive com-
ponents. Active filters are further defined in terms of rate at which
output falls off at the edge of the frequency range.
1. If the fall off rate is 20 dB/decade, the filters are called as First
Order Filters.
2. If the fall off rate is 40 dB/decade, the filters are called as
Second Order Filters.
3. If the fall off rate is 60 dB/decade, the filters are called as Third
Order Filters.

6.1 Advantages of Active Filters over Passive

Filters
1. Because of high input impedance and low output impedance of
OP-AMP, the active filter does not cause loading of the source
or load.

127
6.2. FIRST ORDER LOW PASS ACTIVE FILTER Analog Circuit Design

2. Active filters are more economical because of absence of induc-

tors. (Inductors are bulky, costly and dissipate more power)
3. Due to availability of modern ICs, a variety of cheaper OP-
AMPs are available.
4. The OP-AMP gain can be easily controlled in the closed loop
fashion, hence active filter input signal is not attenuated.
5. The active filter is easier to tune or adjust to any frequency
compared to passive filter.
6. Active filters has excellent isolation between source and load.

6.2 First Order Low Pass Active Filter

A passive low pass filter circuit consisting of a resistor and a capacitor
is shown in figure ??. The filter load ZL is connected in parallel with
a capacitor C1 .
Unless ZL ≫ XC1 , the load is likely to affect the filter perfor-
mance.
Connecting a voltage follower to circuit of figure ?? eliminates the
load problem and converts the circuit into an active filter.
The output voltage Vo of the active filter is given by :
From figure ??,

Vo = I × (−jXC1 ) (6.1)
Vi
∴ Vo = × (−jXC1 ) (6.2)
R1 − jXC1
Taking magnitude,
p
2
XC1
Vo = Vi × p 2 2
(6.3)
R1 + XC1
XC1
∴ Vo = Vi × p 2 2
(6.4)
R1 + XC1
Vo XC1
∴ =p 2 (6.5)
Vi 2
R1 + XC1
At low frequencies, XC1 ≫ R1 , so equation 6.5 gives the gain as
approximately 1.
At higher frequencies, XC1 ≈ R1 , the gain decreases.

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CHAPTER 6. FILTERS Analog Circuit Design

The frequency at which the output voltage is down by 3 dB from

its pass frequency is defined as cut-off frequency fc of the filter.
In figure ??, fc is the frequency at which XC1 = R1 , now equation
6.5 becomes –
Vo XC1
=p 2 (6.6)
Vi 2
R1 + XC1
Vo XC1
∴ =p 2 (6.7)
Vi XC1 + XC12

Vo XC1
∴ =p 2 (6.8)
Vi 2XC1
Vo 1
∴ =√ (6.9)
Vi 2
At frequencies hihger than fc , the gain of the circuit falls off at a
rate of 20 dB/decade i.e. a fall of 20 dB each time the frequency is
increased by a factor of 10.

6.2.1 Design Steps : First Order Active Low Pass Filter

0.1VBE
1. R1 =
IB(max)
2. R1 = R2
3. XC1 = R1 at fc .
1
= R1
2πfc C1
1
C1 =
2πfc R1
Example 6.1 Using a 741 OP-AMP, design a first order active low
pass filter to have a cut-off frequency of 1 kHz.

Ans : fc = 1kHz
For OP-AMP 741 : IB(max) = 500nA
Assume VBE = 0.7V

0.1VBE 0.1 × 0.7

R1 = =
IB(max) 500 × 10−9
∴ R1 = 140kΩ
Choose R1 = 120kΩ

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6.3. SECOND ORDER ACTIVE LOW PASS FILTER Analog Circuit Design

R2 = R1 = 120kΩ

1 1
C1 = =
2πfc R1 2π × 1 × 103 × 120 × 103
∴ C1 = 1326 × 10−12
∴ choose C1 = 1300pF

Example 6.2 Design a first order active low pass filter using 715
OP-AMP having a cut-off frequency of 4 kHz [IB(max) = 1.5µA for
715 OP-AMP]

Ans : fc = 4kHz
For OP-AMP 715 : IB(max) = 1.5µA
Assume VBE = 0.7V

0.1VBE 0.1 × 0.7

R1 = =
IB(max) 1.5 × 10−6
∴ R1 = 46.67kΩ
Choose R1 = 47kΩ

R2 = R1 = 12047kΩ

1 1
C1 = =
2πfc R1 2π × 4 × 103 × 47 × 103
∴ C1 = 846.57 × 10−12
∴ choose C1 = 820pF

6.3 Second Order Active Low Pass Filter

In first order low pass filter, after cut-off frequency the voltage gain
decreases at the rate of 20 dB/decade.
In second order low pass filter, after cut-off frequency, the voltage
gain decreases at the rate of 40 dB/decade.
Figure ?? shows a second order low pass filter, which has a fre-
quency response that falls off at the rate of 40 dB per decade above
the upper cut-off frequency.
This steeper roll-off rate is achieved by using the C1 R2 together
with feedback from the output via capacitor C2 to the junction of
R1 and R2 .

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CHAPTER 6. FILTERS Analog Circuit Design

At low frequencies, XC1 and XC2 are much larger than R1 and R2
and they have no effect on the circuit. So output voltage is equal to
the input giving a voltage gain of 1. (∵ Av = Vo /Vi )
At high frequencies, the effect of C1 and R2 causes the output to
fall off at a rate of 20 dB per decade as the frequency increases. The
R2 and C1 introduces a phase lag. The C2 combined with R1 and
R2 introduces a phase lead.
The result of these phase difference is that the feedback via C2
produces a further fall off of 20 dB per decade. Thus second order
low pass filter produces a fall off rate of 40 dB per decade.

6.3.1 Design Steps of Second Order Active Low Pass

Filter
0.1VBE
1. R1 + R2 =
IB(max)

2. R1 = R2
√
3. XC1 = 2R2 atfc
1 √
= 2R2
2πfc C1
1
∴ C1 = √
2πfc 2R2

4. R3 = R1 + R2

5. C2 = 2C1

Note : The resistance R1 satisfies the equation

√
R1 = 2XC2 (6.10)
√
2
R1 = (6.11)
2πfc C2

Example 6.3 Design a second order low pass filter circuit to have
a cut-off frequency of 1 kHz

Ans : Given fc = 1 kHz. Assume VBE = 0.7V .

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6.3. SECOND ORDER ACTIVE LOW PASS FILTER Analog Circuit Design

For 741 OP-AMP: IB(max) = 500nA

0.1VBE 0.1 × 0.7
R1 + R2 = =
IB(max) 500 × 10−9
∴ R1 + R2 = 140 × 103 Ω
140 × 103 Ω
∴ R1 = R2 = = 70kΩ
2
If R1 = R2 = 70kΩ, Choose Standard Value R1 = R2 = 68kΩ.

R3 = R1 + R2 = 68kΩ + 68kΩ
∴ R3 = 136kΩ
Choose R3 = 150kΩ

1 1
C1 = √ = √
2πfc 2R2 2π × 1 × 103 × 2 × 68 × 103
∴ C1 = 1655pF
Choose C1 = 1600pF

C2 = 2C1 = 2 × 1600pF = 3200pF

Choose C2 = 3300pF

Example 6.4 Design a Second Order Low Pass Active filter having
a cut-off frequency of 2.5 kHz. Use 709 OP-AMP. For 709 OP-AMP,
IB(max) = 200nA.

Ans : Given fc = 2.5 kHz. Assume VBE = 0.7V .

For 741 OP-AMP: IB(max) = 200nA
0.1VBE 0.1 × 0.7
R1 + R2 = =
IB(max) 200 × 10−9
∴ R1 + R2 = 350 × 103 Ω
350 × 103 Ω
∴ R1 = R2 = = 175kΩ
2
If R1 = R2 = 175kΩ, Choose Standard Value R1 = R2 = 180kΩ.

R3 = R1 + R2 = 180kΩ + 180kΩ
∴ R3 = 360kΩ
Choose R3 = 390kΩ

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CHAPTER 6. FILTERS Analog Circuit Design

1 1
C1 = √ = √
2πfc 2R2 2π × 2.5 × 103 × 2 × 180 × 103
∴ C1 = 250pF
Choose C1 = 250pF

C2 = 2C1 = 2 × 250pF = 500pF

Choose C2 = 500pF

Example 6.5 Using a 741 OP-AMP, design a Second Order Low

Pass Filter to have a cut-off frequency of 5 kHz.

Ans : Given fc = 5 kHz. Assume VBE = 0.7V .

For 741 OP-AMP: IB(max) = 500nA

0.1VBE 0.1 × 0.7

R1 + R2 = =
IB(max) 500 × 10−9
∴ R1 + R2 = 140 × 103 Ω
140 × 103 Ω
∴ R1 = R2 = = 70kΩ
2
If R1 = R2 = 70kΩ, Choose Standard Value R1 = R2 = 68kΩ.

R3 = R1 + R2 = 68kΩ + 68kΩ
∴ R3 = 136kΩ
Choose R3 = 150kΩ

1 1
C1 = √ = √
2πfc 2R2 2π × 5 × 103 × 2 × 68 × 103
∴ C1 = 330.9pF
Choose C1 = 330pF

C2 = 2C1 = 2 × 330pF = 660pF

Choose C2 = 680pF

Example 6.6 Design a Second Order Low Pass filter circuit to have
a cut-off frequency of 2 kHz. Draw the circuit and indicate the fre-
quency response of the filter.

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6.4. FIRST ORDER ACTIVE HIGH PASS FILTER Analog Circuit Design

Ans : Given fc = 2 kHz. Assume VBE = 0.7V .

For 741 OP-AMP: IB(max) = 500nA
0.1VBE 0.1 × 0.7
R1 + R2 = =
IB(max) 500 × 10−9
∴ R1 + R2 = 140 × 103 Ω
140 × 103 Ω
∴ R1 = R2 = = 70kΩ
2
If R1 = R2 = 70kΩ, Choose Standard Value R1 = R2 = 68kΩ.

R3 = R1 + R2 = 68kΩ + 68kΩ
∴ R3 = 136kΩ
Choose R3 = 150kΩ

1 1
C1 = √ = √
2πfc 2R2 2π × 2 × 103 × 2 × 68 × 103
∴ C1 = 827.4pF
Choose C1 = 820pF

C2 = 2C1 = 2 × 820pF = 1640pF

Choose C2 = 1600pF

6.4 First Order Active High Pass Filter

The first order high pass filter can be obtained by interchanging the
elements R1 and C1 in a first order low pass filter circuit. In figure
??, the voltage follower isolates the load from R1 and C1 .
At high frequencies , XC1 is very much smaller than R1 and volt-
age gain Vo /Vi is almost equal to 1 or 0 dB.
When the frequency decreases to a value such that XC1 = R1 , the
voltage gain drops by 3 dB. As the frequency decreases further, the
voltage gain rolls-off at 20 dB per decade.

6.4.1 Design Steps for First Order High Pass Filter

0.1VBE
1. R1 =
IB(max)
2. R2 = R1

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CHAPTER 6. FILTERS Analog Circuit Design

3. XC1 = R1 atfc
1
= R1
2πfc C1
1
∴ C1 =
2πfc R1

Example 6.7 Design a first order active high pass filter for a cut-off
frequencies of 4.5 kHz. Use 741 OP-AMP.

Ans : fc = 4.5kHz
For 741 OP-AMP : IB(max) = 500nA
Assume VBE = 0.7V
0.1VBE 0.1 × 0.7
R1 = =
IB(max) 500 × 10−9
∴ R1 = 140kΩ
Use Standard Value R1 = 120kΩ
R2 = R1 = 120kΩ

1 1
C1 = =
2πfc R1 2π × 4.5 × 103 × 120 × 103
∴ C1 = 295pF
Use Standard Value : C1 = 300pF

6.5 Second Order Active High Pass Filter

The second order high pass filter circuit is similar to the second order
low pass filter circuit, except that the resistor and capacitor positions
are interchanged.
At higher frequencies, XC1 and XC2 are much smaller than R1
and R2 , consequently C1 , C2 , R1 and R2 have no significant effect on
the circuit. The output voltage is then equal to the input, giving a
voltage gain of 1.
At low frequencies, the effect of C2 and R2 causes the output to
fall off at a rate of 20 dB per decade. A phase lead is produced by
C2 and R2 and a phase lag is generated by R1 combined with C1
and C2 . So, feedback via R1 produces a further roll-off of 20 dB per
decade. Thus the total roll-off rate is 40 dB per decade.

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6.5. SECOND ORDER ACTIVE HIGH PASS FILTER Analog Circuit Design

6.5.1 Design Steps of Second Order High Pass Filter

0.1VBE
1. R2 =
IB(max)
√
2. R2 = 2XC2 at fc
√ 1
R2 = 2×
2πfc C2
√
2 1
C2 = =  
2πfc R2 2πf √R2
c 2

3. C1 = C2
R2
4. R1 =
2
5. R3 = R2
6. The impedance XC1 satisfies the equation
√
XC1 = 2R1 at fc
1
i.e. C1 =  
R1
2πfc √ 2

Example 6.8 Design a Second order high pass active fitler to have
a cut-off frequency of 12 kHz. Use 715 OP-AMP and estimate the
highest signal frequency that will be passed.

Ans : Given fc = 12kHz

For 715 OP-AMP : IB(max) = 1.5µA
0.1VBE 0.1 × 0.7
R2 = =
IB(max) 1.5 × 10−6
∴ R2 = 46.66kΩ
Use Standard Value : R2 = 47kΩ

R2 47kΩ
R1 = = = 23.5kΩ
2 2
Use Standard Value : R1 = 22kΩ
R3 = R2 = 47kΩ

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CHAPTER 6. FILTERS Analog Circuit Design

1 1
C2 =  = 
3

R2 47×10
2πfc √
2
2π × 12 × 103 × √
2
∴ C2 = 398pF
Use Standard Value : C2 = 390pF

C1 = C2 = 390pF

From 715 data sheet, the OP-AMP unity gain cut-off frequency is
fu = 11 MHz.
fu
f2 = = 11MHz
Av
Example 6.9 Using OP-AMP, design a second order high pass filter
to have a cut-off frequency of 7 kHz.

Ans : Given fc = 7kHz

For 715 OP-AMP : IB(max) = 500nA
0.1VBE 0.1 × 0.7
R2 = =
IB(max) 500 × 10−9
∴ R2 = 140kΩ
Use Standard Value : R2 = 120kΩ

R2 120kΩ
R1 = = = 60kΩ
2 2
Use Standard Value : R1 = 56kΩ
R3 = R2 = 120kΩ

1 1
C2 =  = 
3

R2 120×10
2πfc √
2
2π × 7 × 103 × √
2
∴ C2 = 267.9pF
Use Standard Value : C2 = 270pF

C1 = C2 = 270pF

Example 6.10 Using a 741 OP-AMP, design a Second order high

pass filter to have a cut-off frequency of 15 kHz.

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6.5. SECOND ORDER ACTIVE HIGH PASS FILTER Analog Circuit Design

Ans : Given fc = 15kHz

For 715 OP-AMP : IB(max) = 500nA
0.1VBE 0.1 × 0.7
R2 = =
IB(max) 500 × 10−9
∴ R2 = 140kΩ
Use Standard Value : R2 = 120kΩ

R2 120kΩ
R1 = = = 60kΩ
2 2
Use Standard Value : R1 = 56kΩ
R3 = R2 = 120kΩ

1 1
C2 =  = 
3

R2 120×10
2πfc √
2
2π × 15 × 103 × √
2
∴ C2 = 125pF
Use Standard Value : C2 = 100pF

C1 = C2 = 100pF

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