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FDP Assignment Solutions

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Sakshi Tiwari
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9 views

FDP Assignment Solutions

Uploaded by

Sakshi Tiwari
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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1. Serial input with valid pulse, design SIPO to generate 8bit output with valid.

When 12 bytes are received, compare it with the fixed input value. If it
matches, generate a pulse output. Draw timing diagram and design optimized
digital circuit of it.

Serial Input --> Shift Register (8-bit SIPO) --> Storage (96-bit
register)
|
v
Comparator --> Pulse Generator -->
Output

2. Generate the below phase-1, phase-2 and phase-3 output where frequency
of each phase-X (X=1,2,3) CLK/20 of CLK of input CLK.

// Define input and output signals


input clk; // Clock signal
input [2:0] hall; // Hall sensor signals (3 bits)
output reg [2:0] phase; // Motor phase outputs (3 bits for
switching)

// Define states for the state machine


parameter IDLE = 3'b000;
parameter STATE_0 = 3'b001;
parameter STATE_1 = 3'b010;
parameter STATE_2 = 3'b100;
parameter STATE_3 = 3'b101;
parameter STATE_4 = 3'b011;
parameter STATE_5 = 3'b110;

reg [2:0] current_state; // Current state of the state machine

// Function to decode Hall sensor signals into a state


function reg [2:0] decode_hall;
input [2:0] hall_sig;
begin
case (hall_sig)
3'b000: decode_hall = IDLE;
3'b001: decode_hall = STATE_0;
3'b010: decode_hall = STATE_1;
3'b011: decode_hall = STATE_2;
3'b100: decode_hall = STATE_3;
3'b101: decode_hall = STATE_4;
3'b110: decode_hall = STATE_5;
3'b111: decode_hall = IDLE; // Handle invalid hall sensor
states
default: decode_hall = IDLE;
endcase
end
endfunction

// State transition logic


always @(posedge clk) begin
case (current_state)
IDLE: begin
if (decode_hall(hall) != IDLE) begin
current_state = decode_hall(hall);
end
end
STATE_0: current_state = STATE_1;
STATE_1: current_state = STATE_2;
STATE_2: current_state = STATE_3;
STATE_3: current_state = STATE_4;
STATE_4: current_state = STATE_5;
STATE_5: current_state = STATE_0;
default: current_state = IDLE;
endcase
end

// Define phase outputs based on state


always @(posedge clk) begin
case (current_state)
IDLE: phase = 3'b000;
STATE_0: phase = 3'b100; // Phase A high, others low
(example)
STATE_1: phase = 3'b010; // Phase B high, others low
(example)
STATE_2: phase = 3'b001; // Phase C high, others low
(example)
STATE_3: phase = 3'b110; // (Adjust phase assignments based
on motor wiring)
STATE_4: phase = 3'b011; //
STATE_5: phase = 3'b101; //
default: phase = 3'b000;
endcase
end
endmodule

3. Create a calculator which do + and -. Assume two numbers are 9bit wide.
Full Adder:
module full_adder(
input a,
input b,
input cin,
output sum,
output cout
);

assign sum = a ^ b ^ cin;


assign cout = (a & b) | (cin & (a ^ b));

endmodule

9-bit Adder:
module nine_bit_adder(
input [8:0] a,
input [8:0] b,
output [8:0] result,
output carry_out
);

wire [8:0] sum;


wire carry_out_last;

full_adder FA0(.a(a[0]), .b(b[0]), .cin(1'b0), .sum(sum[0]),


.cout(carry_out_last));
full_adder FA1(.a(a[1]), .b(b[1]), .cin(carry_out_last),
.sum(sum[1]), .cout(carry_out_last));
full_adder FA2(.a(a[2]), .b(b[2]), .cin(carry_out_last),
.sum(sum[2]), .cout(carry_out_last));
full_adder FA3(.a(a[3]), .b(b[3]), .cin(carry_out_last),
.sum(sum[3]), .cout(carry_out_last));
full_adder FA4(.a(a[4]), .b(b[4]), .cin(carry_out_last),
.sum(sum[4]), .cout(carry_out_last));
full_adder FA5(.a(a[5]), .b(b[5]), .cin(carry_out_last),
.sum(sum[5]), .cout(carry_out_last));
full_adder FA6(.a(a[6]), .b(b[6]), .cin(carry_out_last),
.sum(sum[6]), .cout(carry_out_last));
full_adder FA7(.a(a[7]), .b(b[7]), .cin(carry_out_last),
.sum(sum[7]), .cout(carry_out_last));
full_adder FA8(.a(a[8]), .b(b[8]), .cin(carry_out_last),
.sum(sum[8]), .cout(carry_out));

assign result = sum;


assign carry_out = carry_out_last;

endmodule

9-bit Subtractor:
module nine_bit_subtractor(
input [8:0] a,
input [8:0] b,
output [8:0] result,
output borrow_out
);

wire [8:0] diff;


wire borrow_out_last;

// Create two's complement of b


assign b_twos_complement = ~b + 1;

// Perform addition with two's complement to achieve


subtraction
nine_bit_adder ADD(.a(a), .b(b_twos_complement),
.result(diff), .carry_out(borrow_out_last));

assign result = diff;


assign borrow_out = borrow_out_last;

endmodule

Calculator:
module calculator(
input [8:0] num1,
input [8:0] num2,
input op, // '0' for addition, '1' for subtraction
output reg [8:0] result,
output reg valid_output
);

reg [8:0] temp_result;


reg valid_result;

always @(*) begin


if (op == 0) begin // Addition
nine_bit_adder ADD(.a(num1), .b(num2),
.result(temp_result), .carry_out());
valid_result = 1;
end
else begin // Subtraction
nine_bit_subtractor SUB(.a(num1), .b(num2),
.result(temp_result), .borrow_out());
valid_result = 1;
end
end

always @(posedge op) begin


result <= temp_result;
valid_output <= valid_result;
end

endmodule

4. Multiply input 10bit data by 6 (without multiplier) .

module multiply_by_6(
input [9:0] data_in,
output reg [15:0] result
);

reg [9:0] mult_by_4;


reg [9:0] mult_by_2;

always @* begin
mult_by_4 = data_in << 2; // Multiply by 4 (left shift
by 2)
mult_by_2 = data_in << 1; // Multiply by 2 (left shift
by 1)
result = mult_by_4 + mult_by_2; // Multiply by 6
end
endmodule

5. There is a 8bit incoming data, and other input are reg_sel, sel and chk which
are one bit input along with data, this data has be captured as below logic.
• If reg_sel is set to 0, data needs to be loaded in register when sel
input is 1, chk is don’t care.
• If reg_sel is set to 1, then data need to be loaded in register when
sel and chk input is 1
Reg, sel and chk can change at any time.

module data_capture(

input wire clk,

input wire [7:0] data,

input wire reg_sel,

input wire sel,

input wire chk,

output reg [7:0] captured_data

);

// Internal registers to hold previous state of inputs

reg prev_reg_sel;

reg prev_sel;

reg prev_chk;

always @(posedge clk) begin

// Store previous state of inputs

prev_reg_sel <= reg_sel;

prev_sel <= sel;


prev_chk <= chk;

// Logic to capture data based on conditions

if (reg_sel == 0 && sel == 1) begin

captured_data <= data;

end else if (reg_sel == 1 && sel == 1 && chk == 1) begin

captured_data <= data;

end

// No action needed if conditions are not met

end

endmodule

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