Building Larger Circuits

VERILOG HDL
1. Counter with period 1000
2. 4-bit shift register and down counter
3. FSM: Sequence 1101 recognizer
4. FSM: Enable shift register
5. FSM: The complete FSM
6. The complete timer
7. FSM: One-hot logic equations

CHANCHAL TIWARI 1
Question :-

Design :-
module top_module (
input clk,
input reset,
output [9:0] q);

always@(posedge clk) begin

if(reset)
q <= 0;
else if(q == 999 )
q <= 0;
else
q <= q+1;
end

endmodule

CHANCHAL TIWARI 2
Question :- Build a four-bit shift register that also acts as a down counter. Data is shifted in
most-significant-bit first when shift_ena is 1. The number currently in the shift register is
decremented when count_ena is 1. Since the full system doesn't ever
use shift_ena and count_ena together, it does not matter what your circuit does if both control
inputs are 1 (This mainly means that it doesn't matter which case gets higher priority).

Design :-
module top_module (
input clk,
input shift_ena,
input count_ena,
input data,
output [3:0] q);

always@(posedge clk) begin

if(shift_ena && ~count_ena) //1110 1 =1101
q <= {q[2:0],data };
else if(~shift_ena && count_ena)
q <= q - 1'b1;
else
q <= q;
end
endmodule

CHANCHAL TIWARI 3
Question :- Build a finite-state machine that searches for the sequence 1101 in an input bit
stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Getting
stuck in the final state is intended to model going to other states in a bigger FSM that is not yet
implemented. We will be extending this FSM in the next few exercises.

Design :-
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting);

parameter s0 = 3'b000 ,
s1 = 3'b001 ,
s2 = 3'b010,
s3 = 3'b011,
s4 = 3'b100;
reg [2:0] ps,ns;

always@(posedge clk ) begin

if(reset)
ps <= s0;
else
ps <= ns ;
end

always@(ps , data) begin

case(ps)
3'b000 : ns = data ? s1 : s0 ;
3'b001 : ns = data ? s2 : s0 ;
3'b010 : ns = data ? s2 : s3 ;
3'b011 : ns = data ? s4 : s0 ;
3'b100 : ns = data ? s4 : s4 ;
default ns = s0;
endcase
end

assign start_shifting = (ps == s4);

endmodule

CHANCHAL TIWARI 4
Question :- As part of the FSM for controlling the shift register, we want the ability to enable
the shift register for exactly 4 clock cycles whenever the proper bit pattern is detected. We
handle sequence detection of previous question, so this portion of the FSM only handles
enabling the shift register for 4 cycles.
Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset).

Design :-
module top_module (
input clk,
input reset, // Synchronous reset
output shift_ena
);

reg [2:0] q = 3'd0;

always@(posedge clk)
begin
if(reset)
begin
shift_ena <= 1'b1;
q <= 3'd0;
end
else

CHANCHAL TIWARI 5
 begin
if(q == 3'd3)
begin
shift_ena <= 1'b0;
end
else if(q < 3'd4)
begin
shift_ena <= 1'b1;
q <= q + 3'd1;
end
end
end

endmodule

Question :-
We want to create a timer that:
1. is started when a particular pattern (1101) is detected,
2. shifts in 4 more bits to determine the duration to delay,
3. waits for the counters to finish counting, and
4. notifies the user and waits for the user to acknowledge the timer.
In this problem, implement just the finite-state machine that controls the timer. The data path
(counters and some comparators) are not included here.
The serial data is available on the data input pin. When the pattern 1101 is received, the state
machine must then assert output shift_ena for exactly 4 clock cycles.
After that, the state machine asserts its counting output to indicate it is waiting for the counters,
and waits until input done_counting is high.
At that point, the state machine must assert done to notify the user the timer has timed out, and
waits until input ack is 1 before being reset to look for the next occurrence of the start sequence
(1101).
The state machine should reset into a state where it begins searching for the input sequence
1101.
Here is an example of the expected inputs and outputs. The 'x' states may be slightly confusing to
read. They indicate that the FSM should not care about that particular input signal in that cycle.
For example, once a 1101 pattern is detected, the FSM no longer looks at the data input until it
resumes searching after everything else is done.

CHANCHAL TIWARI 6
Design :-
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output shift_ena,
output counting,
input done_counting,
output done,
input ack );

parameter s0=4'b0000, s1=4'b0001, s2=4'b0010, s3=4'b0011,

b0=4'b0100, b1=4'b0101, b2=4'b0110, b3=4'b0111,
count=4'b1000, wt=4'b1001;

reg [4:0] ps,ns;

always@(posedge clk) begin

if(reset)
ps <= s0;
else
ps <= ns ;
end

always@(ps, data ,done_counting,ack)begin

case(ps)
4'b0000 : ns = data ? s1 : s0;
4'b0001 : ns = data ? s2 : s0;
4'b0010 : ns = data ? s2 : s3;

CHANCHAL TIWARI 7
 4'b0011 : ns = data ? b0 : s0;
4'b0100 : ns = b1;
4'b0101 : ns = b2;
4'b0110 : ns = b3;
4'b0111 : ns = count;
4'b1000 : ns = done_counting ? wt : count;
4'b1001 : ns = ack ? s0 : wt;
default : ns = s0 ;
endcase
end

assign shift_ena = (ps == b0) || (ps == b1) ||(ps == b2) ||(ps == b3) ;
assign done = (ps == wt);
assign counting = (ps == count) ;

endmodule

Question :-
We want to create a timer with one input that:
1. is started when a particular input pattern (1101) is detected,
2. shifts in 4 more bits to determine the duration to delay,
3. waits for the counters to finish counting, and
4. notifies the user and waits for the user to acknowledge the timer.
The serial data is available on the data input pin. When the pattern 1101 is received, the circuit
must then shift in the next 4 bits, most-significant-bit first. These 4 bits determine the duration
of the timer delay. I'll refer to this as the delay[3:0].
After that, the state machine asserts its counting output to indicate it is counting. The state
machine must count for exactly (delay[3:0] + 1) * 1000 clock cycles. e.g., delay=0 means count
1000 cycles, and delay=5 means count 6000 cycles. Also output the current remaining time. This
should be equal to delay for 1000 cycles, then delay-1 for 1000 cycles, and so on until it is 0 for
1000 cycles. When the circuit isn't counting, the count[3:0] output is don't-care (whatever value
is convenient for you to implement).
At that point, the circuit must assert done to notify the user the timer has timed out, and waits
until input ack is 1 before being reset to look for the next occurrence of the start sequence
(1101).
The circuit should reset into a state where it begins searching for the input sequence 1101.
Here is an example of the expected inputs and outputs. The 'x' states may be slightly confusing to
read. They indicate that the FSM should not care about that particular input signal in that cycle.
For example, once the 1101 and delay[3:0] have been read, the circuit no longer looks at
the data input until it resumes searching after everything else is done. In this example, the circuit
counts for 2000 clock cycles because the delay[3:0] value was 4'b0001. The last few cycles starts
another count with delay[3:0] = 4'b1110, which will count for 15000 cycles.

CHANCHAL TIWARI 8
Design :-
module top_module (
input clk,
input reset,
input data,
output [3:0] count,
output counting,
output done,
input ack
);

wire shift_ena;
wire done_counting;
// Complete FSM
reg [3:0] cs, ns;
parameter S = 4'b0,
S1 = 4'b0001,
S11 = 4'b0010,
S110 = 4'b0011,
B0 = 4'b0100,
B1 = 4'b0101,
B2 = 4'b0110,
B3 = 4'b0111,
C = 4'b1000,
W = 4'b1001;
always @(posedge clk) begin
if (reset)
cs <= S;
else
cs <= ns;
end
always @(*)begin
case (cs)
S: ns = data ? S1 : S;
S1: ns = data ? S11 : S;
S11: ns = data ? S11 : S110;
S110: ns = data ? B0 : S;
B0: ns = B1;
B1: ns = B2;
B2: ns = B3;
B3: ns = C;
C: ns = done_counting ? W : C;
W: ns = ack ? S : W;

CHANCHAL TIWARI 9
 default: ns = S;
endcase
end

// 4-bit shift register and down counter

reg [3:0] delay;
always @(posedge clk) begin
if (shift_ena) delay <= {delay[2:0], data};
else if (cnt_1k == 999) delay <= delay - 1;
else delay <= delay;
end

// Counter 1000
reg [9:0] cnt_1k;
always @(posedge clk) begin
if (~counting) cnt_1k <= 0;
else cnt_1k <= cnt_1k < 999 ? cnt_1k + 1 : 0;
end

assign shift_ena = (cs == B0) || (cs == B1) || (cs ==

B2) || (cs == B3);
assign done_counting = (count == 0 )&& (cnt_1k ==
999);
// Output logic
assign count = delay;
assign counting = (cs == C);
assign done = (cs == W);

endmodule

Question :-
CHANCHAL TIWARI 10
Question :-
Given the following state machine with 3 inputs, 3 outputs, and 10 states:

Derive next-state logic equations and output logic equations by inspection assuming the
following one-hot encoding is used: (S, S1, S11, S110, B0, B1, B2, B3, Count, Wait) =
(10'b0000000001, 10'b0000000010, 10'b0000000100, ... , 10'b1000000000)
Derive state transition and output logic equations by inspection assuming a one-hot encoding.
Implement only the state transition logic and output logic (the combinational logic portion) for
this state machine. (The testbench will test with non-one hot inputs to make sure you're not
trying to do something more complicated. See fsm3onehot for a description of what is meant by
deriving logic equations "by inspection" for one-hot state machines.)
Write code that generates the following equations:
• B3_next -- next-state logic for state B3
• S_next
• S1_next
• Count_next
• Wait_next
• done -- output logic
• counting
• shift_ena

Design :-
module top_module(
input d,
input done_counting,
input ack,
input [9:0] state,
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena

CHANCHAL TIWARI 11
);

parameter S = 0, S1 = 1, S11 = 2, S110 = 3,

B0 = 4, B1 = 5, B2 = 6, B3 = 7, C = 8, W = 9;
// B3_next is described as "next-state logic for state
B1".
// It is obviously a mistake and should be B2.
assign B3_next = state[B2];
assign S_next = (state[S]&~d) | (state[S1]&~d) |
(state[S110]&~d) | (state[W]&ack);
assign S1_next = state[S]&d;
assign Count_next = (state[B3]) |
(state[C]&~done_counting);
assign Wait_next = (state[C]&done_counting) |
(state[W]&~ack);
assign done = state[W];
assign counting = state[C];
assign shift_ena = (state[B0] ) | (state[B1]) |
(state[B2]) | (state[B3]);

endmodule

CHANCHAL TIWARI 12