Lecture 6

Dr. Nabil M. Eldakhly

Faculty of Computers and Information –
Department of CS-
CS-SAMS
&
The French University in Egypt (UFE)
Gate-Level Minimization (Cont.)
 Outline

1. Don't-Care Conditions
2. NAND and NOR Implementation
3. Other Two-level Implementations
4. Exclusive-OR Function
 Gate Level Minimization (Cont.)-
Don’t-Care Conditions

In practice, in some applications the function is not specified for

certain combinations of the variable

Functions that have unspecified outputs for some input combinations

are called incompletely specified functions.

In most applications, we simply don't-care what value is assumed by

the function for the unspecified minterms.

For this reason, it is customary to call the unspecified

minterms of a function don’t-care conditions.

These don't-care conditions can be used on a map to provide further

simplifications of the Boolean expression.
 Gate Level Minimization (Cont.)-
Don’t-Care Conditions (Cont.)

A don‘t-care minterm is a combination of variables whose logical

value is not specified.
̶ Such a minterm cannot be marked with a 1 in the map, because it would
require that the function always be a 1 for such a combination. Likewise,
putting a 0 on the square requires the function to be 0.
To distinguish the don't-care condition from 1’s and 0’s, X is used.
̶ Thus, an X inside a square in the map indicates that we don’t care
whether the of 0 or 1 is assigned to F for the particular minterm.
In a choosing adjacent squares to simplify the function in a map, the
don't-care mintems may be assumed to be either 0 or 1.
When simplifying the function, we can choose to include each don't-
care minterm with either the 1's or the 0’s, depending on which
combination gives the simplest expression.
When using K-map to simplify the Boolean function, each grouping will give either a
literal or one product term. It is known as Prime Implicant.
The prime implicant is said to be Essential Prime Implicant, if at least single ‘1’ is not
covered with any other groupings but only that grouping covers.
 Gate Level Minimization (Cont.)-
Don’t-Care Conditions (Cont.)- Example-1

Simplify F(w, x, y, z) = Σ(1, 3, 7, 11, 15) which has the don't-

care conditions d(w, x, y, z) = Σ(0, 2, 5).
Essential Implicant

F = yz + w'x' = Σ(0, 1, 2, 3, 7, 11, 15); F = yz + w'z = Σ(1, 3, 5, 7, 11, 15)

Either expression is acceptable
 Outline

1. Don't-Care Conditions
2. NAND and NOR Implementation
3. Other Two-level Implementations
4. Exclusive-OR Function
 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NAND Gate

NAND gate is a universal gate

– Can implement any digital system

(xy)’

x’
y’
 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NAND Gate (Cont.)-
Two-Level Implementation-
NAND-NAND = Sum of Product

Example: F = AB+CD Sum of Products

= ((AB)‘ (CD)’ )‘ NAND-NAND
 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NAND Gate (Cont.)-
Two-Level Implementation (Cont.)-
NAND-NAND = Sum of Product- Example

Implement F(x, y, z) = Σ(1, 2, 3, 4, 5, 7)

F ( x, y , z ) = ∑ (1, 2,3, 4,5, 7) F ( x, y , z ) = xy′ + x′y + z
 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NAND Gate (Cont.)-
Two-Level Implementation (Cont.)-
NAND-NAND = Sum of Product- Procedures with Two-Level

1. Simplified in the form of sum of products;

2. A NAND gate for each product term; the inputs to each NAND
gate are the literals of the term (the first level);

3. A single NAND gate for the second sum term (the second level);

4. A term with a single literal requires an inverter in the first level.

 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NAND Gate (Cont.)-
Two-Level Implementation (Cont.)-
Multi-Level NAND Circuits- Boolean Function Implementation

AND-OR logic → NAND-NAND logic

AND: AND + inverter = NAND
OR: inverter + OR = NAND
• For every bubble that is not compensated by another small circle
along the same line, insert an inverter.
 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NOR Gate

NOR function is the dual of the NAND function.

The NOR gate is also universal.
 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NOR Gate (Cont.)-
Two Graphic Symbols Implementation

(A+B)’

(A+B)
(C+D)’
(C+D)
E
E’

= [(A+B)’ + (C+D)’+ E’]’

 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NOR Gate (Cont.)-
Two Graphic Symbols Implementation- Example

AB’

(AB’+ A’B)’ AB’+ A’B

A’B
(C+D’)

(C+D’)’
 Outline

1. Don't-Care Conditions
2. NAND and NOR Implementation
3. Other Two-level Implementations
4. Exclusive-OR Function
 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NAND Gate (Cont.)-
Other Two-Level Implementations
TTL: Transistor-Transistor Logic
Wired logic ECL: Emitter-Coupled Logic
– A wire connection between the outputs of two gates
– Open-collector TTL NAND gates: wired-AND logic
– The NOR output of ECL gates: wired-OR logic
 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NAND Gate (Cont.)-
Other Two-Level Implementations- Degenerate Forms
How Many Two-level Combinations Of Gates Are Possible? We
consider 4 types of gates: AND, OR, NAND, and NOR.
̶ If we assign one type of gate for the first level and one type for the second
level, we find that there are 16 possible combinations of two-level forms.
̶ Eight of them are said to be degenerate forms because they will result in
a single operation effectively.
• Example: This can be seen from a circuit with AND gates in the first level and
an AND gate in the second Level. The output of the circuit is merely the AND
function of all input variables.
• AND-AND, AND-NAND, OR-OR, OR-NOR, NAND-OR, NAND-NOR, NOR-AND,
NOR-NAND.
̶ The first gate listed in each of the forms
constitutes a first level in the
A
implementation. The second gate listed B
C
is a single gate placed in the second level D
 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NAND Gate (Cont.)-
Other Two-Level Implementations- Non-Degenerate Forms

The eight non-degenerate forms

– AND-OR, OR-AND, NAND-NAND, NOR-NOR, NOR-OR, NAND-AND, OR-
NAND, AND-NOR.

Examples of equivalent’s two-level non-degenerate form gates:

– AND-OR and NAND-NAND = sum of products.

– OR-AND and NOR-NOR = product of sums.

– NOR-OR, NAND-AND, OR-NAND, AND-NOR = ?????

 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NAND Gate (Cont.)-
Other Two-Level Implementations-
AND-OR-Invert (AOI) Implementation

AND-NOR = NAND-AND = AOI

AND-OR-Invert
Example: F = (AB+CD+E)' = (AB)’(CD)’E’ = NAND-AND
= AND-NOR
F’ = AB+CD+E = Sum of Products
 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NAND Gate (Cont.)-
Other Two-Level Implementations-
OR-AND-Invert (OAI) Implementation

OR-NAND = NOR-OR = OAI OR-AND-Invert

Example: F = [(A+B)(C+D)E]‘ = (A+B)’+(C+D)’+E’ = NOR-OR
= OR-NAND
F’ = (A+B)(C+D)E = Product of Sums
 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NAND Gate (Cont.)-
Other Two-Level Implementations-
Tabular Summary and Examples
 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NAND Gate (Cont.)-
Other Two-Level Implementations-
Tabular Summary and Examples- Example-1
Implement F = x'y'z'+ xyz' into AOI and OAI Forms
The complement of the function F is:
F' = (x'y'z'+ xyz‘)’
The AOI forms require a simplified expression of the complement of
the function in sum-of-products form by combining the 0’s in the map:

Then, the F’ after simplified into sum-of-products is:

F' = x'y +xy‘ +z
 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NAND Gate (Cont.)-
Other Two-Level Implementations-
Tabular Summary and Examples- Example-1 (Cont.)
Then the normal output of the function F become AND-OR-Invert
F = (x'y +xy‘ + z)‘ (which is the AOI form) = NAND-AND
= AND-NOR
= Sum of Products
AND-NOR = NAND-AND = AOI
 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NAND Gate (Cont.)-
Other Two-Level
F = x'y'z'+Implementations-
xyz'
Tabular Summary and Examples- Example-1 (Cont.)
The OAI forms require a simplified expression of the complement of
the function in product-of-sums form by combining the 1’s in the map:

x+y+z

x’ + y’ + z

Then, the F’ is:

F' = (x'y'z'+ xyz‘)’ = (x’y’z’)’(xyz’)’= (x + y + z)(x’+ y’+ z)
Then the normal output of the function F become
F = [(x + y+ z)(x’+ y’+ z)]’ (which is the OAI form)
 Gate Level Minimization (Cont.)-
NAND & NOR Implementation- NAND Gate (Cont.)-
Other Two-Level Implementations-
Tabular Summary
OR-NAND and Examples-
= NOR-OR = OAI Example-1 (Cont.)
OR-AND-Invert
OR-NAND = NOR-OR = OAI = NOR-OR
= OR-NAND
= Product of Sums
 Outline

1. Don't-Care Conditions
2. NAND and NOR Implementation
3. Other Two-level Implementations
4. Exclusive-OR Function
 Gate Level Minimization (Cont.)-
Exclusive-OR Function

Exclusive-OR (XOR)
x⊕y = xy‘ + x'y
Exclusive-NOR (XNOR)
(x⊕y)' = xy + x'y'
Some identities
x⊕0 = x
x⊕1 = x'
x⊕x = 0
x⊕x' = 1
x⊕y' = (x⊕y)'
x'⊕y = (x⊕y)'
Commutative and associative
A⊕B = B⊕A
(A⊕B) ⊕C = A⊕ (B⊕C) = A⊕B⊕C
 Gate Level Minimization (Cont.)-
Exclusive-OR Function (Cont.)-
Two-Variable Exclusive-OR Implementation

(x'+y')x + (x'+y')y = xy‘ + x'y = x ⊕y

(xy)’

Exclusive-OR Implementations
 Gate Level Minimization (Cont.)-
Exclusive-OR Function (Cont.)-
Two-Variable Exclusive-OR Implementation- Odd Function
– A⊕B⊕C
= (A ⊕ B) ⊕C x ⊕ y = xy‘ + x'y
= (A ⊕ B) C’ + (A ⊕ B)’ C
(x ⊕ y)' = xy + x'y'
= (AB'+A'B)C' +(AB+A'B')C
= AB'C'+A'BC'+ABC+A'B'C
= Σ(1, 2, 4, 7)
– XOR is an odd function →
an odd number of 1's, then F = 1.
– XNOR is an even function →
an even number of 1's, then F = 1.
 Gate Level Minimization (Cont.)-
Exclusive-OR Function (Cont.)-
Two-Variable Exclusive-OR Implementation-
Odd & Even Function

Map for a Three-variable Exclusive-OR Function

 Gate Level Minimization (Cont.)-
Exclusive-OR Function (Cont.)-
Two-Variable Exclusive-OR Implementation-
Odd & Even Function- XOR & XNOR

Logic diagram of odd and even functions

Logic Diagram of Odd and Even Functions

 Gate Level Minimization (Cont.)-
Exclusive-OR Function (Cont.)-
Four-Variable Exclusive-OR Implementation

Four-variable Exclusive-OR function

A⊕B⊕C⊕D = (AB'+A'B)⊕(CD'+C'D)
= (AB'+A'B)(CD+C'D')+(AB+A'B')(CD'+C'D)

Map for a Four-variable Exclusive-OR Function

 Gate Level Minimization (Cont.)-
Exclusive-OR Function (Cont.)-
Four-Variable Exclusive-OR Implementation-
Parity Generation & Checking

• In the context of computing and data storage, "parity" refers

to a method of error checking used to detect and sometimes
correct errors in data.
̶ Parity is a simple and widely used technique to ensure data
integrity, particularly in systems where error detection is
important but not necessarily error correction.
• The basic idea behind parity is to add an extra bit (the parity
bit) to a set of binary data bits.
̶ This parity bit is calculated in a way that ensures the total
number of 1s in the data (including the parity bit) is either
even or odd, depending on the chosen parity scheme.
 Gate Level Minimization (Cont.)-
Exclusive-OR Function (Cont.)-
Four-Variable Exclusive-OR Implementation-
Parity Generation & Checking
• Even Parity: In even parity, the number of 1s (including the parity bit) in
the data should be an even number. If it's not, the parity bit is set to make
it even. So, if the data already has an even number of 1s, the parity bit is
0. If the data has an odd number of 1s, the parity bit is set to 1.
Example:
Data bits: 101100
Parity bit (even parity): 1 (to make the total count of 1s even)= 1011001
• Odd Parity: In odd parity, the number of 1s (including the parity bit) in the
data should be an odd number. If it's not, the parity bit is set to make it
odd. So, if the data already has an odd number of 1s, the parity bit is 0. If
the data has an even number of 1s, the parity bit is set to 1.
Example:
Data bits: 101100
Parity bit (odd parity): 0 (to make the total count of 1s odd)= 1011000
 Gate Level Minimization (Cont.)-
Exclusive-OR Function (Cont.)-
Four-Variable Exclusive-OR Implementation-
Parity Generation & Checking

Parity Generation and Checking

– A parity bit: P = x ⊕ y ⊕ z
– Parity check: C = x ⊕ y ⊕ z ⊕ P
• C=1: one bit error or an odd number of data bit error
• C=0: correct or an even # of data bit error

Logic Diagram of a Parity Generator and Checker

 Gate Level Minimization (Cont.)-
Exclusive-OR Function (Cont.)-
Four-Variable Exclusive-OR Implementation-
Parity Generation & Checking (Cont.)
 Gate Level Minimization (Cont.)-
Exclusive-OR Function (Cont.)-
Four-Variable Exclusive-OR Implementation-
Parity Generation & Checking (Cont.)