Question#1

Question 1. Convert the following virtual addresses to their equivalent physical addresses in
hexadecimal. All numbers are given in hexadecimal. (A dash for a page frame indicates that the
page is not in memory.)
• 9EF
• 111
• 700
• 0FF
Solution:
Let's say we have a page table with the following mappings:
 Virtual Page 0 maps to Physical Page 3
 Virtual Page 1 maps to Physical Page 5
 Virtual Page 2 is not in memory (indicated by a dash)
 Virtual Page 3 maps to Physical Page 7
With this information, we can calculate the physical addresses:
1. Virtual Address 9EF:
 Page Number: 9
 Offset: EF
 According to the page table, Virtual Page 9 maps to Physical Page 3.
 So the physical address is 3EF.
2. Virtual Address 111:
 Page Number: 1
 Offset: 11
 According to the page table, Virtual Page 1 maps to Physical Page 5.
 So the physical address is 511.
3. Virtual Address 700:
 Page Number: 7
 Offset: 00

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  According to the page table, Virtual Page 7 is not in memory (indicated by a
dash).
 So the page fault occurs, meaning the data at this address is not currently in
memory.
4. Virtual Address 0FF:
 Page Number: 0
 Offset: FF
 According to the page table, Virtual Page 0 maps to Physical Page 3.
 So the physical address is 3FF.
These are the physical addresses based on the assumed page table mappings. Actual mappings
would depend on the specifics of the system's memory management.

Question#2
Consider the following page reference string: 1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6.
How many page faults would occur for the following replacement algorithms, assuming one,
two, three, four, five, six, and seven frames? Remember that all frames are initially empty, so
your first unique pages will cost one fault each.
• LRU replacement
• FIFO replacement
• Optimal replacement
Solution:
For calculating page faults suppose we use three frames in main memory USING FIFO
Algorithm:
Thus calculations are:
3 3 3 3 5 5 5 1
2 2 2 2 1 1 1 2 2
1 1 1 4 4 4 4 6 6 6
* * * * HIT * * * *
*

1 1 1 6 6 6

2
 2 2 7 7 7 7
6 3 3 3 3 2
HIT * * * HIT
*
6 6 3 3
1 1 1 1
2 2 2 6
* HIT * *

By using all calculations page fault in this FIFO algorithm for three frames are: 16
For different frames, different page faults occur:
1 20
2 16
3 14
4 12
5 11
6 10
7 9

Similarly, by using all calculations page fault in this LRU and Optimal Replacement
algorithm for three frames are: 16
For different frames, different page faults occur:
1 20
2 16
3 14
4 12
5 11

3
 6 10
7 9

Question#3:

Assume that a program has just referenced an address in virtual memory. Describe a scenario in
which each of the following can occur. (If no such scenario can occur, explain why.) • TLB miss
with no page fault
• TLB miss and page fault
• TLB hit and no page fault
• TLB hit and page fault
Solution:
1. TLB miss with no page fault:
 Scenario: Let's say the TLB (Translation Lookaside Buffer) stores translations for
frequently accessed virtual addresses. However, due to a context switch or a large
virtual address space with frequent page table changes, the TLB entry for the
referenced virtual address gets replaced with another translation just before the
program accesses that address again. Since the corresponding page is still in
memory, no page fault occurs, but the TLB miss happens because the translation
was not found in the TLB.
2. TLB miss and page fault:
 Scenario: Consider a situation where the TLB holds translations for only a subset
of the virtual pages currently in use. When the program references a virtual
address for which there is no corresponding TLB entry (a TLB miss), and that
page is also not currently loaded into physical memory (a page fault occurs), then
we have a scenario where both a TLB miss and a page fault happen
simultaneously.
3. TLB hit and no page fault:
 Scenario: Suppose the TLB contains the translation for the referenced virtual
address. Additionally, the corresponding page is already in physical memory, so
there's no need to fetch the page from secondary storage. Therefore, the TLB hit

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 occurs, and there's no page fault because the required page is already loaded in
memory.
4. TLB hit and page fault:
 Scenario: This scenario is theoretically impossible in typical memory
management systems. When the TLB successfully provides the translation for the
referenced virtual address (TLB hit), it implies that the translation is available in
memory. Thus, there shouldn't be a page fault because the required page is
already in memory. However, in some unusual scenarios where there are
hardware faults or issues in the memory management unit, it might be
theoretically possible for a TLB hit to coincide with a page fault, but this would
be an exceptional case and not something that occurs in standard systems.

Question#4:
Suppose that a machine provides instructions that can access memory locations using the one-
level indirect addressing scheme. What sequence of page faults is incurred when all of the pages
of a program are currently nonresident and the first instruction of the program is an indirect
memoryload operation? What happens when the operating system is using a per-process frame
allocation technique and only two pages are allocated to this process?
Solution:
Scenario:
 All pages of a program are currently non-resident (not loaded into physical memory).
 The first instruction of the program is an indirect memory load operation, meaning it tries
to access a memory location through an indirect pointer.
 The operating system is using a per-process frame allocation technique, and only two
pages are allocated to this process.
Sequence of Page Faults:
1. The first instruction of the program is an indirect memory load operation, which means it
accesses a memory location through an indirect pointer.
2. Since the program's pages are not resident in memory, the pointer (stored in a memory
location) that the instruction tries to access resides in a non-resident page.
3. Accessing the pointer triggers a page fault because the page containing the pointer needs
to be brought into memory.
4. Once the page containing the pointer is loaded into memory, the instruction can access
the memory location it points to. However, if the memory location it points to is also in a
non-resident page, another page fault will occur.

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 5. This process continues until all necessary pages containing both instructions and data are
brought into memory.
Impact of Per-process Frame Allocation:
 With only two pages allocated to the process, the program will have a limited amount of
physical memory available to it. This means that only two pages of the program can be
resident in memory at any given time.
 As a result, the process will constantly incur page faults as it accesses memory locations
residing in non-resident pages. The operating system will need to evict pages from
memory to make space for the incoming pages, which may lead to frequent page swaps
between memory and secondary storage.
 The performance of the program will be severely impacted due to the high overhead of
page faults and frequent disk I/O operations associated with swapping pages in and out of
memory.

Question#5:

How many page faults occur for your algorithm for the following reference string with four page
frames? 1, 2, 3, 4, 5, 3, 4, 1, 6, 7, 8, 7, 8, 9, 7, 8, 9, 5, 4, 5, 4, 2.
Solution:
Using Optimal Page replacement Algorithm where page is replaced which has use in longest
dimension in future.

4 4 4 4 4 6 6
3 3 3 3 3 3 3 3
2 2 2 5 5 5 5 5 7
1 1 1 1 1 1 1 1 1 1
* * * * HIT HIT HIT HIT * *
8 8 9 9 8 9
3 3 3 3 3 3
7 7 7 7 7 7
1 1 1 1 1 1

6
* HIT * HIT * HIT
9 9 9 9 9
3 3 3 3 2
7 4 4 4 4
5 5 5 5 5
* * HIT HIT *

Calculating page fault: