A processor for testing mixed-signal cores in System-on-Chip

Francisco Duarte, J. Machado da Silva, José C. Alves, G. A. Pinho, José S. Matos

Faculdade de Engenharia da Universidade do Porto, INESC Porto
Rua Dr. Roberto Frias, 4200-465 Porto, Portugal
{fduarte, jms, jca, gabriel, jsm}@fe.up.pt

Abstract 1.1. Test processors

This paper describes the design of a processor specific The use of processors to perform different test operations
for testing cores embedded in system-on-chip. This proces- has already been proposed. These include self-testing [3],
sor, which can be implemented within a system’s reconfig- memory tests [10], and the entire test of a SoC [6]. Both
urable area, shall be responsible for scheduling and control hardware and software specific facilities can be provided
test operations and perform preliminary data processing, in these processors, such as boundary-scan controllers [9],
as well as to provide the interface with an external tester. Linear Feedback Shift (LFSR) and Multiple Input Shift
Building these test operations on-chip allows for simplify- (MISR) registers, and programs for local test vector com-
ing external tester interface and to reduce testing time. The pression and decompression [2]. In [1] an embedded AMS
testing procedure and the infrastructure required to test an test controller is proposed which makes use of the IEEE
A/D converter is described as an example. 1149.4 standard [8] and utilizes the embedded memory to
support test operations.
The solution proposed here relies on reusing the logic
reconfigurable block (such as a field-programmable gate ar-
1. Introduction ray – FPGA) existing in a SoC to perform some other mis-
sion function, to implement an application specific instruc-
The progress attained in successive generations of tion set processor (ASIP) to control and schedule on-chip
system-on-chip (SoC), has created a new range of innova- test operations. This processor can be adapted to the specific
tive and affordable consumer products. Blocks such as dig- test needs of each block under test, in order to fully exploit
ital and analogue I/O interfaces, complex communication the reconfigurable resources available within the system and
sub-systems (including optical and radio-frequency cir- minimize the test time. For example, different test mecha-
cuits), power management, and multiple processors with nisms are required for an A/D converter, a RAM block, or
the respective software, can now being integrated onto sin- a bank of digital filters, and the requirements of each test
gle silicon dies. depend whether the test is intended for production or field
Conventional test approaches, fully relying on external maintenance. Furthermore, depending on the architecture of
automatic test equipment (ATE), are unable to cope with the SoC under test, the test processor may also include sup-
the test requirements of tens or even hundreds of such cores port to manage the SoC test infrastructure and configuring
deeply embedded in complex systems. This is particularly the routing of normal mission and test signals. Being an
true for analogue and mixed-signal (AMS) SoCs found in instruction-set processor implemented on a reconfigurable
the markets of wireless and wired communications, along platform, a very flexible architecture can be obtained that is
with consumer electronics products. enhanceable with dedicated instructions tailored to meet ap-
plication specific test needs.
To overcome this drawback specific built-in self test
(BIST) schemes may be used in order to simplify the in- The rest of the paper describes, in section 2, the in-
terface with the external tester, performing parallel tests of frastructure and the test processor main functionalities be-
different cores, and generating specific test stimuli through ing proposed. Section 3 describes the processor’s architec-
on-chip processing. Such approaches shall always be devel- ture and its instruction set. An application example for the
oped having in mind the objective of reducing test time and specific case of an ADC core is presented section 5. Sec-
cost. tion 6 highlights the main conclusions.

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 2. The test processor and test infrastructure
PI M3
The architecture of the test infrastructure and test proces- SI
M1 0
0
PO
0 1

sor to implement and manage analogue and mixed-signal 1

D 1

FF M2
test operations is presented in this section. The test proces- clk
SO

sor is built as a RISC style load-store processor core with

a customizable instruction set, surrounded by modules that
dynamic
handle test-specific tasks supported by custom instructions. TCM inputs

TMX TCM
2.1. Test Infrastructure Control
TMX

The type of interface implemented between the tester and Parallel

ADC
static
inputs
Port
the core under test (CUT) depends on the test resources in-
cluded in the circuit. Increasing the amount of in-circuit FPGA
test resources allows increasing controllability and observ-
ability. On the other hand, one has to distinguish between
mission and test signals. Generally, test signals include dy-
namic and static signals. The former ones are active or
change often during testing, while the seconds are typically dynamic
outputs
those which are only used to configure test modes or do not
PI M2 D1
change often during test [11]. While these signals can be M1 0 0

SI 0 PO
propagated and configured using serial test infrastructures, 1
D 1 1

FF
the dynamic ones need parallel routing. clk
SO

A standard boundary-scan IEEE 1149.1 serial chain, or

a generic scan chain, can be used to propagate static signals
and to switch between mission and test functional modes.
An infrastructure controller resident in the processor pro- Figure 1. Example of interface between the
vides this facility. Furthermore, reconfigurable logic allows CUT and the test processor.
also to implement IEEE 1149.1 boundary-scan (or other
type) scan cells to route signals from cores which are not
provided with test wrappers. All these registers shall be con-
trolled by the test processor.
As an example, figure 1 illustrates the case of the CUT
being an A/D converter and the test processor placed in Similarly, the CUT dynamic outputs require cells capable
the FPGA. This structure represents the generic case of the of directing these signals to mission lines or to the test ones
CUT being a peripheral within the system. The ADC wrap- that connect directly to the test processor. These cells are
per includes the cells required to switch between mission similar to the ones presented in [7] but include both ser-
and test signals (either dynamic or static). In general, mis- ial and parallel test inputs and outputs. The FPGA offers
sion signals are connected to other blocks in the system, and thus also the possibility of implementing the digital part of
test signals are connected to the FPGA. When necessary, test cells, in a more flexible way as it would be easier to de-
additional Test Control Mode (TCM) and Test Multiplexer sign these cells following the requirements of each specific
(TMX) registers provide accessibility for additional test sig- case.
nals, coming from external or internal resources. This can
be the case of the Test Bus Interface Circuit (TBIC) of the Another aspect concerns time control and synchroniza-
IEEE 1149.4 analogue test bus [8], which could be used to tion of analogue and digital events. In analogue test it is
drive analogue test stimuli coming from the external ATE. often required that sampling (for stimulus generation and
Analogue test cells placed in the core’s wrapper allow for, response capture) be performed at a constant rate. In gen-
besides switching between mission and test signals, a sin- eral, the analogue frequencies are smaller than the digital
gle internal analogue test bus to drive stimuli to different clock frequencies used in the test processor, however, it is
cores. critical that during stimuli generation and response capture,
Dynamic input signals require that two input cells be the processor does not introduce fluctuation in sampling fre-
present in the wrapper to switch between system mission quencies. This aspect will be developed further later in the
signals and the test ones generated by the test processor. paper.

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 2.2. Test stimuli generation and response capture to generate the full cycle after this sub-set of the wave-
form. The stimulus frequency is defined by the ratio be-
The variety of test operations to be performed in an in- tween “clkDDS” and “enDDS” clock signals.
tegrated system (interconnects, modules integrity, overall Testing time is a critical issue in production test. Al-
functional performance) requires different test stimuli, ob- though not expected to be a frequent case, aborting a test
servation, time control and response evaluation schemes. operation when catastrophic faults are detected avoids un-
Concerning stimuli generation, besides the possibility of necessary further test operations. For this purpose, capture
choosing among different test stimuli generators, such as instructions include the possibility to generate an interrupt
Pulse Width Modulator (PWM), LFSR, Direct Digital Syn- in case the captured sample presents a definitely erroneous
thesizer (DDS), it is also important to assure a high degree value. For each captured sample, if the variation from the
of inter-operability between the stimulus generator and the previous one is higher than a specified expected value, it
core processor to allow a flexible stimulus waveform am- is assumed that the CUT’s response presents a totally non-
plitude and frequency definition. On the other hand, it is admissible behaviour.
fundamental that the stimulus generation, after being pro- Power consumption in testing can be problematic in
grammed, be functionally autonomous to avoid requiring a SoCs, as usually the system’s power management is de-
permanent interaction with the core processor, freeing it for signed considering only the normal operation mode, and
other operations, for example capture and pre-processing of also because different test operations may be run in par-
the response. A digital sigma-delta modulator implemented allel to reduce test time. To reduce power consumption the
in the FPGA allows to generate analogue signals requiring a processor’s clock frequency can be adjusted to the specific
simple RC network to filter the 1 bit modulated FPGA out- requirements of each test stage. For example, during stim-
put signal. uli generation and response capture the processor may run
with the lowest clock frequency that can guarantee the re-
quired sampling frequency, but to pre-process the acquired
response an higher speed would be convenient to reduce
6 8 8
DDS N processing time.

clk
2.3. Preliminary processing operations
clk*N
reset Performing preliminary test data processing on-chip, al-
lows reducing the volume of data to be transferred to the
Figure 2. Stimuli generation with DDS and in- external tester, as well as the post-processing needed to ob-
terpolation. tain the final test results. This contributes also to reduce
testing time, both on transferring and post-processing time.
Depending on the testing methods being used, different
processing operations may be required. Besides those which
Figure 2 illustrates the block diagram of a stimulus gen- can be performed with the ALU included in the test proces-
erator comprising a DDS and an interpolator. The combina- sor, more specific operations can be carried-out using addi-
tion of these two blocks allows to find a good compromise tional test logic or within auxiliary blocks that can be added,
between the area occupied in the FPGA, and the generated exploring the execution of parallel operations.
stimulus resolution. Using a 8-bit DDS, and a 2 times inter- One of the possible processing operations to be imple-
polation (N=2), allows to obtain an equivalent higher res- mented is the cross-correlation of the captured response
olution, with a shorter look-up table (LUT). The interpo- with in-phase and quadrature forms of the test stimulus,
lator assigns values between consecutive LUT words, and in order to calculate gain, phase, and harmonic distortion.
thus increases the sampling rate of the D/A process, lead- The block ”+PI/2” shown in figure 3 is used to gener-
ing noise (image frequencies) in the output spectrum to ate the quadrature signal. Re-generating the test stimulus
be shifted to higher frequencies. For a certain output filter in processing operations avoids the necessity for storing it
bandwidth, this has the effect of pushing noise out of band, when it is applied to the CUT.
thus reducing the in-band noise and increasing the equiva-
lent resolution. 3. Processor’s architecture
Figure 3 shows a detailed diagram of the DDS. In this
case, to generate a sinusoidal stimulus, only 90o of the To make use of an FPGA area inside a SoC for testing
waveform are stored in the LUT, being the blocks “1’s one part of the SoC, it is necessary to design a custom digi-
compl”, “-1” (2’s comp), and the output multiplexer used tal circuit to execute the appropriate tasks in the correct se-

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 DDS

6 MSB

R
6 6 6 4 0 L 0 0
+ E +PI/2 4
U
8 8 8
6 G 1's
COMPL
1 T -1
1 1

Sine FF
clk DDS
Accumulator
2nd MSB
reset
reset
clk DDS
enDDS
enCOS

Figure 3. DDS block diagram.

quence. This involves four main operations: controlling the The base processor core supports a complete set of con-
test infrastructure to gain access to the part to be tested, gen- ventional instructions, plus all the specific instructions that
erate a set of stimuli and apply them to the part under test, control the test-specific functional blocks placed around the
capture the output values and, finally, process the captured core. In this case we have:
results.
All these operations can be efficiently undertaken by cus- • BSctrl is a boundary-scan controller implementing the
tom designed digital circuits, relying on traditional digi- IEEE 1149.1/.4 standard protocol, meant to control the
tal design techniques. However, using such development 1149.1 test infrastructure;
methodology to design the different circuits required for the
various cores to be tested and test stages is time consuming, • TSctrl is a block dedicated to stimulus generation
error prone, and inflexible.
The approach proposed here resorts on obtaining Ap- • DUVctrl is a module responsible for controlling the
plication Specific Instruction-Set Processors (ASIP), whose operation of the CUT;
set of conventional and dedicated instructions are automat-
ically derived from a software specification of the test op- • TrespAnal is dedicated to evaluate the validity of the
eration to be implemented. Figure 4 shows a block diagram samples being captured;
of the test processor. It includes a programmable processor
core surrounded with several test specific functional blocks, The actual configuration of the test processor is deter-
which may be included or not, depending on the type of test mined by the instructions the designer uses in the test pro-
operations to be performed. gram, and includes only the resources required for that task.
For example, if the processor’s registers and the ALU oper-
ations are not referred in the program to be executed, these
elements do not need to be included in the processor’s data-
path and control path; in the other hand, if a sine waveform
generator is needed to stimulate an analogue block, a spe-
cial instruction must be used that will attach to the processor
core a block that support this function. Section 4 presents
the procedure to create a configuration of the test proces-
sor from the textual specification of a test program.
Although this strategy creates programmable processors
that do not exhibit a high degree of flexibility because they
only include the resources to meet the needs of one partic-
ular program, it is an efficient way to create dedicated con-
trollers area-optimized for each particular test task. Besides,
any test programs that use the same set of instructions can
Figure 4. Test processor architecture.
still be implemented without requiring the re-synthesis of a
different processor.

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 3.1. The instruction set
test program

Besides conventional load/store, arithmetic/logic opera-

tions and loop control, the instruction set comprises applica-
tion specific instructions supported by peripheral blocks, to Processor
handle the IEEE 1149.1/4 port that controls the CUT wrap- template
per, the test stimuli generator, and to handle the CUT spe- Processor Instruction
cific control signals: optimization database

• SRTEST Starts the test procedure by applying appro-

priate control signals to the device under test;
• NSHF TDIdata Load the 1149.4 infrastructure regis-
HDLmodules
ters with a specific bit stream;
• STATE TMSdata Changes the TAP controller state
machine to the specified state, applying the appropri-
ate number of TCK ticks and TMS values;
FPGA synthesis and
• STIMULUS Applies a digital stimuli vector previ- implementation tools
ously stored in a specific memory segment to the TSc-
trl stimuli generator block; 1010111

• EOTEST Signalizes the end of test and resets internal 0111010

1111001

memory pointers to prepare for another test; FPGA configuration

bitstream
The instructions SRTEST and EOTEST are meant to be
used to support particular CUT functions under the con-
trol of the DUVctrl module. The generation of test stimuli Figure 5. Design flow to configure and imple-
is performed with the STIMULUS instruction, which acts ment a custom test processor.
over the TSctrl block. Once that instruction is executed, the
generation of the stimulus signal is functionally indepen-
dent from the core processor.
This set of instructions was designed in order to enable for the control path and additional blocks that may have
the parallel execution among them. For example, while the to be included in the datapath to support the execution of
processor waits a new test response sample, it can evalu- that instruction. The set of registers referenced in the pro-
ate the validity of the previous sample captured. This par- gram configures the processor’s register file, and the group
allelism can also be exploited when the processor waits for of arithmetic and logic operations used in the code select
an external synchronization, to perform some specific oper- the functional blocks to be included within the ALU. Fi-
ation related with the CUT. nally, the finite state machine that implements the control
path is adjusted to minimize the number of states and a pre-
4. Test processor configuration defined state encoding is assigned to the final HDL model.
Although some characteristics of the processor are fixed
To customize the test processor for a specific test pro- (for example the width of internal data buses and the encod-
gram, an application was developed that configures the var- ing of instructions), this configuration procedure leads to
ious parts of the processor in order to include only the re- significant reduction to the occupation of the FPGA, when
sources necessary to run that test program. The output of compared with the complete version of the processor. If the
this process is the complete RTL model of the test proces- target platform is a FPGA area with a large amount of con-
sor, organized as a set of synthezisable HDL modules, that figurable resources that can support the whole processor, it
can enter the specific FPGA synthesis and implementation is not worth the effort to reduce the area of the test proces-
tools (figure 5). sor. In this case, a test procedure composed of various sub
The starting point for this customization is the source tasks (e.g. configure devices, apply stimuli, analyze results)
code of a test program, which may refer any instruction may be implemented by only one instance of the test proces-
available in the full instruction set. The optimization pro- sor. In the other hand, if the reconfigurable area is small
cedure reads the source code and extracts a list of the in- and can only implement subsets of the processor, a test pro-
structions used, as well as the registers and ALU opera- cedure may be split into different stages, each one accom-
tions referenced. For each instruction, its description is ex- plished by a different version of the test processor, reconfig-
tracted from a database that defines the sequence of states uring the FPGA area as many times as necessary. In this sit-

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 wave stimulus, and performing the cross-correlation of the
Processor model 4-input LUTs Flip-flops
captured response with in-phase and quadrature versions
Full processor 1575 749
of the stimulus. Gain, phase, and harmonic distortion can
Cross-correlation 821 540
be obtained after these two correlations [4]. The following
Dithered step wave 418 257
script shows the main processor’s program to perform the
test operation.
Table 1. FPGA occupation for different test
processor configurations. NHARMONICS .EQU 5 ;no. of harmonics to determine
SETDDS ;DDS as stimuli generator
;sinusoidal signal
; Set test infrastructure
STATE 11,447
uation, the test designer will only write the test programs NSHF 39,1048575
for each stage, and a specific processor will be created to STATE 5,7
NSHF 48,4194561
run each one of those programs. STATE 2,3
Table 1 shows the FPGA occupation for three different MOVC CNT2,NHARMONICS
configurations of the test processor. These implementations ;start test execution
STIMULUS
where done with Synopsys FPGA Express for a XC4013 TEST_CS5330A ;schedules DUVctrl CUT block
FPGA. First row refers to the full version that supports the L: XCORR RAD ;performs cross-correlation
whole instruction set, peripheral blocks and ALU opera- XCORR LAD ;performs cross-correlation
STIMULUS
tions. The second configuration was obtained for the spe- DJNZ CNT2,L ;go to next harmonic
cific case described in next section. The last version cor- STATE 6,3F ;go to Test-Logic-Reset state
responds to a different specific architecture that applies as EOTEST
HLT
stimuli a dithered step wave, captures a set of samples and .END
computes the average of responses in each step [5]. As one
can see, there is a significant variation of the FPGA occu- The first instruction specifies the DDS block for stimuli
pation when the processor is configured to include only the generation. The next 5 instructions interact with the “BSc-
resources required for the specified operations. If an FPGA trl” module to control the test infrastructure. The configura-
block is reconfigured twice to implement the two test proce- tion of the infrastructure test mode is done by selecting the
dures referred in table 1 it will require only 52% of the logic appropriate number of test clock (TCK) ticks and the test
resources that would be necessary for the complete proces- mode select (TMS) value to apply, and the bitstream to pro-
sor. gram the test infrastructure registers. These instructions per-
form the appropriate sequence to up-load the infrastructures
registers with the required content [8].
5. Application example After the test infrastructure has been configured the num-
ber of harmonics to be calculated is specified. The STIM-
The principles and design philosophy presented before ULUS instruction controls the “TSctrl” module to generate
has been developed and used to develop a test strategy the test stimulus previously specified. This stimulus is gen-
for an electronic energy meter system. Besides the central erated with the DDS block described before followed by a
processing unit this system comprises in the signal acquisi- Σ∆ modulator and low-pass filter which provide the digital
tion front-end an FPGA dedicated to control and capture the to analogue conversion. With the stimulus signal being ap-
digitised signals from the A/D converter. The system spec- plied to the CUT, the TEST-CS5330A instruction starts the
ifications require that the system performs a monthly test ADC clock and the time delay required for the ADC ini-
to check accuracy of captured data. Figure 6 shows the di- tialization. This instruction is similar to SRTEST but spe-
agram of the prototype built to evaluate the test processor cific for the ADC under test. The end of this initialization
and test strategy of the data acquisition front-end. In this is signaled by the “DUVctrl” block. This time is also used
case a 1149.4 test bus is used to drive analogue signals from to let the CUT transient response to settle-down. Data cap-
the stimulus generator output to the ADC input, as well as ture is also performed within the TEST-CS5330A instruc-
to the input impedance adapter (not shown in the picture) tion. The number of samples to be captured has been previ-
placed before the ADC. The analogue test cells are imple- ously stored in the “DUVctrl” module.
mented with a commercial IC that implements the 1149.4 The XCORR instruction activates the cross-correlator
infrastructure. (The use of the this standard infrastructure is auxiliary block to perform this operation (the two XCORR
not mandatory and a simpler bus could be used, however it instructions refer to right and left ADC channels). The ALU
was decided to implement it here as a demonstration proto- can also be involved in this operation under the control of
type.) the cross-correlation block. Upon the test completion the
The test to be carried-out consists on applying a sine TAP state machine is brought to the reset state (STATE in-

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 Test processor 3
Dynamic control signals

T
1149.1 A
P
controller

signatures
Interface
TDI A
Analogue

ATE

Test
mission input
B
M
Ain ADC

Test stimulus T Analog

1
B test bus
modulator AT 1,2 2
I
C
TDO

Static control signals

Serial data

Figure 6. ADC test example.

struction) and the HLT instruction is executed to signal that

Hn /H1 amplitude (dB)
the operation is concluded.
h2 -52
Figure 7 shows the stimulus spectrum at the ADC input. h3 -55
It is a 50 Hz sinusoidal wave with 4 Vpp amplitude. It can be h4 -60
seen that some harmonic content is present at low frequen- h5 -70
cies. Although their relative amplitudes are small, these can
affect test results if very low total harmonic distortions are Table 2. Amplitude of harmonics obtained in
being measured. It was found that their presence is due to the test operation.
fluctuations in the amplitude of Σ∆ bit stream at the output
of the FPGA. Table 2 shows average values of the harmon-
ics obtained after performing the test operation. These val- 6. Conclusions
ues reflect both the distortion introduced by the data acqui-
sition front-end, as well as the residual one from the stimu- A processor specific for testing embedded cores in a SoC
lus. This might lead to the necessity of inserting a buffer to is described in this paper. It provides on-chip stimuli gen-
adapt the FPGA output to the load being driven. eration, test control and scheduling, the control of a com-
pliant IEEE 1149.1/4 test infrastructure, and data process-
ing. These facilities allow reducing the number of signals
to be sourced by the external tester, the amount of data to
be transported between the tester and the CUT, as well as
test time by performing on-chip pre-processing operations.
The solution proposed here relies on reusing an FPGA-like
block that may exist within the SoC to implement an appli-
cation specific instruction set processor, that can be scaled
according the test needs and the space available for imple-
mentation.
Having a programmable processor dedicated to
this task and implemented in a digital reconfigurable
FPGA-like block has several advantages, when com-
pared to test-specific controllers with fixed functionality.
First, there is no significant silicon area overhead, be-
cause the reconfigurable platform where the test processor
is implemented already exists in the SoC. Second, de-
Figure 7. Stimulus spectrum. pending on the size of the FPGA block available in a
particular system, an adequate version of a test proces-
sor may be chosen, in order to offer a convenient trade-off
between processing power and FPGA occupation.

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 Acknowledgment
The work presented herein has been partly supported by
the Portuguese government - Agência de Inovação under
the framework of projects ASSOCIATE (A503 - MEDEA+)
and NanoTEST (2A702 - MEDEA+, phase 2).

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Proceedings of the 2005 8th Euromicro conference on Digital System Design (DSD’05)
© 2005 IEEE
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