Jour of Adv Research in Dynamical & Control Systems, Vol.

10, 14-Special Issue, 2018

A Comparative Study on Different

Multipliers-Survey
S. Nagaraj, Research Scholar, Department of ECE, JNTUA Anantapuramu, AP. E-mail:[email protected]
Dr.G.M. Sreerama Reddy, Principal, CBIT Kolar, KA. E-mail:[email protected]
Dr.S. Aruna Mastani, Assistant Professor, Department of ECE, JNTUA Anantapuramu, AP. E-mail:aruna [email protected]
Abstract--- Multiplication operation is the second most used arithmetic operation after addition. There are many
researches carried out to develop and increase the performance of Multipliers. In this paper different types of
multipliers like Array Multiplier, Carry Save Array Multiplier, Wallace Tree Multiplier, Dadda Multiplier, Booth’s
Multiplier, Booth Encoded Wallace Tree and Vedic Multiplier are surveyed and analyzed. Their speed, area, power
consumption and circuit complexity is analyzed.
Index Terms--- Array Multiplier, Carry Save Array Multiplier, Wallace Tree Multiplier, Dadda Multiplier, Booth’s
Multiplier, Booth Encoded Wallace Tree, Vedic Multiplier.

I. Introduction
Multipliers play important and significant role in Signal Processing according to A. V. Oppenheim and R. W.
Schafer [1] and other variouus applications. Multiplication is mathematical operation in which the number is added
to itself for the specified number of times.
Multipliers take more time and area than other arithmetic operations. Multipliers are used in Digital Signal
Processing applications such as convolution, filtering, Fast Fourier Transform(FFT) and in Arithmetic Logic
Unit(ALU) in microprocessors. 8.72 % of all the instructions in scientific program are multiplication as per A.V.
Oppenheim and R. W. Schafer [1]. Researchers have been carried by Poras T. Balsara et al. [7], R.Gnanasekaran
[8], Gensuke Goto, Tomio Sato et al. [9], H. I. Saleh, A. H. Khalil et al. [10] to develop new techniques and
algorithms for high speed and optimized area.
An efficient multiplier has the following characteristics Speed: The Multiplier should perform the operations at
high speed.
Accuracy: The results of Multiplier should be correct.
Area: Multiplier should occupy less area that is it should be with minimum no of transistors.
Power: Power consumption of Multiplier should be low.

II. Multipliers
Multiplication operation generally comprises of two steps. Partial Products are generated in the first step and
then it is added with the previous partial products. Every bit of multiplicand is multiplied by every multiplier bit to
get partial products. So to multiply two N-bit numbers N partial product rows of N bit each has to be generated. So
we need AND gate to generate every bit of partial product.

The general process can be broken down into three steps as per H. A. Al-Twaijry [2] as shown in Figure 1.

1. Partial products are generated in the first step. The partial Products are generated in parallel and there are
several ways for partial products generation.
2. Reduction of Partial Products are reduced from N rows to two rows which are called as sum and carry rows.
Special adder architectures are used to produce the final two rows. The delay of this step can be reduced
upto 30 % as per Earl E. Swartzlander, Jr. [5].
3. The two rows sum and carry rows are added using Adder to get the final product of the input operands.

ISSN 1943-023X 739

Received: 20 October 2018/Accepted: 15 November 2018
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 14-Special Issue, 2018

Fig. 1: Multiplication Steps

Multipliers are classified into following
1. Serial Multipliers
2. Parallel Multipliers
Parallel Multipliers feeds operands in parallel and Serial Multipliers feeds operands in serial N number of partial
products are formed for each cycle. Parallel Multipliers are faster than Serial Multipliers since the delay is reduced
by simultaneous processing. Serial Multipliers are preferred when area and power are of greater importance than the

Fig. 2: Multiplication Steps

delay. Serial-Parallel multipliers are good in area and power consumption but not in speed Rabaey J.,
Chandrakasan A et al. [30]
The Figure 3 shows general block diagram of a Serial Multiplier. The Figure 4 shows general block diagram of a
Parallel Multiplier.

ISSN 1943-023X 740

Received: 20 October 2018/Accepted: 15 November 2018
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 14-Special Issue, 2018

Fig. 3: Serial Multiplier

The following Multiplier are studied in the survey
1. Array Multiplier
2. Carry Save Array Multiplier
3. Wallace Tree Multiplier
4. Dadda Multiplier
5. Booth’s Multiplier
6. Booth Encoded Wallace Tree
7. Vedic Multiplier

Fig. 4: Parallel Multiplier

III. Array Multiplier

Array method of partial products accumulation was proposed by C.R. Baugh, and B.A. Wooley [18], P.E.
Blankenship [19]. Array multipliers are suited best for faster computations in digital signal processing applications
since it has simple interconnections. An array multiplier to perform multiplication of nxn bits requires n2 no of AND

ISSN 1943-023X 741

Received: 20 October 2018/Accepted: 15 November 2018
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 14-Special Issue, 2018

gates and n(n-1) adders. The Figure 5 shows 4x4 Array Multiplier. Array Multiplier is easy to design and it is very
slow due to large critical path. The performance issues of Array Multiplier was discussed in Qi Wang and Yousef R
et al. [24]. Bajaj et al. [50] has low power parallel array multiplier for unsigned and 2’s complement signed
multiplication the authors used NOR gates instead of AND gates and reduced delay and power dissipation.
Chua-Chin Wang et al. [51] proposed low power digital signed array multiplier based on 2D by passing
technique and acheived power savings compared with array of array and bough wooley multiplier.
Das et al. [52] proposed new architecture for signed multiplier which is 25% faster , 54% more area than Bough
wooley multiplier.
Pieper et al. [53] proposed efficient 2’s complement array multiplier by combining radix 2 m dedicated multiplier
blocks and adder compressors. The design has shown more efficient in terms of delay and power consumption.

IV. Carry Save Array Multiplier

Carry Save Array Multiplier uses Carry Save Adders to reduce the critical path delay. Carry Propagation Adder
is used in the final stage for generation the final product. The Figure 6 shows 4x4 Carry Save Array Multiplier.

Fig. 5: Array Multiplier

Fig. 6: Carry Save Array Multiplier

ISSN 1943-023X 742

Received: 20 October 2018/Accepted: 15 November 2018
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 14-Special Issue, 2018

N.Ravi,Y.Subbaiah et al. [42] has implemented low power low area array multiplier with carry save adder. The
proposed multiplier has shown 13.91% of less power, 34.09% of more speed and 59.91% of less energy
consumption.
Singh et al. [56] implemented array multiplier using Carry Look ahead Adder and Carry Save Adder. Carry Save
adder shows improvement in speed by 78%, 42% reduction in area and 1.4% decrease in power consumption.
Jia, Song, et al. [57] presented array multiplier using simplified carry save adders. The work has shown 5.3%
reduce in transistor count, 9.7% improvement in speed and 3.1% increase in power for a 4x4 multiplier.
Fonseca, et al. [58] implemented radix 2m hybrid array multiplier using carry save adder (CSA) has shown 25%
power savings.
Paul et al. [59] has presented (VT-Sub-CMOS) variable threshold sub threshold CMOS implementation of Carry
Save Array Multiplier and has shown Power Dissipation Product reduction by 5 times better than normal
subthreshold CMOS.
Preet et al. [60] implemented 32-bit unsigned array multiplier using carry look ahead adder, carry save adder.
Multiplier using CSA has shown improvement of 78.3% in speed, power consumption 1.4% and reduction of area
by 4.2%.
Zhan Yu et al. [61] implemented Booth encoded carry save array multiplier and the results has shown 18%
reduction in power when used in multiplexed FIR filter.

V. Wallace Tree Multiplier

Wallace Tree Multiplier was proposed in the year 1964 by C.S.Wallace [3]. It is fast method of performing
multiplication. The performance of Wallace Tree Multiplier is faster for larger operands. The partial product matrix
of an Array Multiplier is rearranged to form a tree like structure as shown in the figure. This reduces the number of
adders and the critical path.
Wallace Tree Multiplier uses column compression technique. Wallace tree has complexity in design. There are
(2:2),(3:2),(4:2) and (5:2) compressors. The Figure 7 shows 8 bit Wallace Tree Multiplier using 3:2 compressor.
Wallace tree was implemented using modified full adders using XOR gate and Multiplexer by Kokila Bharti
Jaiswal, Nithish Kumar V et al. [34] showed reduction of delay of about 17.65% , area of about 45.75% and average
power of about 37.45%.
Wallace tree Multiplier was designed using Carry Selected Adder and Binary to Excess-1 Converter by R. Bala
Sai Kesava, B. Lingeswara rao et al. [35] which showed reduced area and power consumption. Ramanathan P,
Kowsalya P et al. [36] used 8-T,10-T,14-T,Gate Diffussion Input(GDI) for designing adders in 8:2 compressors and
the proposed Wallacw Tree structure consumes less power and area.
A. 2:2 Compressors
A Half adder is (2:2) compressor it takes two bits from a column of partial product matrix and produces two bits
of output , one bit to the next column and one bit to the same column. The Figure 8 shows (2:2) compressor.
B. 3:2 Compressors
Wallace Tree can use 3:2 Compressors proposed in Ahmed M. Shams, Tarek K. Darwish et al. [20] , Hung Tine
Bui, Yuke Wang et al. [21]. A Full adder is (3:2) compressor it takes three bits from a column of partial product
matrix and produces two bits of output , one bit to the next column and one bit to the same column. The Figure 9
shows (3:2) compressor.
C. 4:2 Compressors
Wallace Tree can use 4:2 Compressors proposed in Hiroshi Makino,Yasunobu Nakase et al. [22] , D. T. Shen
and A. Weinberger [23], K. Prasad and K.K. Parhi [25].
A (4:2) compressor it takes four bits from a column of partial product matrix and produces two bits of output,
one bit to the next column and one bit to the same column. Multiplier using (4:2) compressor has shown improved
performance in speed and regularity in structure as per Au L.S. and Burgess N [32]. The Figure 10 shows (4:2)
compressor which uses two (3:2) compressor (Full adders).

ISSN 1943-023X 743

Received: 20 October 2018/Accepted: 15 November 2018
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 14-Special Issue, 2018

Fig. 7: Wallace Tree Multiplier using 3:2 Compressor

Fig. 8: 2:2 Compressor

D. 5:2 Compressors
Wallace Tree can use 5:2 Compressors proposed in K. Prasad and K.K. Parhi [25]. A (5:2) compressor it takes
five bits from a column of partial product matrix and produces two bits of output , one bit to the next column and
one bit to the same column. The Figure 11 shows (5:2) compressor which uses (3:2) compressor.

Fig. 9: 3:2 Compressor

ISSN 1943-023X 744

Received: 20 October 2018/Accepted: 15 November 2018
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 14-Special Issue, 2018

Fig. 10: 4:2 Compressor

VI. Dadda Multiplier

Dadda multiplier is high speed multiplier as per L. Dadda Dadda multiplier is similar to Wallace tree multiplier.
Dadda Multiplier uses minimum number of full and half adders to meet predefined heights at each stage. The stage
height is increased by 1.5 times at the subsequent stage. The stage height limit starts with 2. The different stage
heights are 2,3,4,6,9,13,19,28,42 and so on. Dadda multiplier architecture proposed in Chittibabu A., Sola V.K. [33]
et. al can perform signed multiplication it supports operands in two’s complement form and signed form. This
architecture has shown better performance in terms of area and speed.
Townsend et al. [62] implemented Dadda multiplier and Wallace tree multiplier the results has shown that Dadda
multiplier is slightly faster than Wallace tree multiplier.
Jeevan, B., et al. [63] has presented high speed binary floating multiplier based on Dadda algorithm. The speed
improvement is acheived by using Dadda multiplier instead of carry save multiplier for mantissa.
Crawley, D. G., and G. A. J. Amaratunga. [64] presented 8x8 time optimal multilier using Dadda Algorithm with
7-stage linear pipeline.
Riaz, Muhammad Hussnain, et al. [65] implemented 4-bit multiplier using Dadda algorithm with optimized Full
Adder. Hybrid Full Adder is designed using CMOS and Pass Transistor Logic. This has shown low latency and high
speed. Hybrid Full adder has shown high throughput and low propagation delay.

Fig. 11: 5:2 Compressor

ISSN 1943-023X 745

Received: 20 October 2018/Accepted: 15 November 2018
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 14-Special Issue, 2018

VII. Booth’s Multiplier

If the partial products can be reduced by N/2 or less the hardware required and as well as the time will be
reduced. A.D. Booth [11] in the year 1951 proposed algorithm that reduces the number of partial products. This was
later mod-ified by L. P. Rubinfield [12] by Rubinfield and named it as Modified Booth’s Encoding(MBE) algorithm.
Using this algorithm the number of partail product rows is reduced by half. Booth’s Multiplier is high speed
multiplier. It can perform signed multiplication and reduces the number of multiplicand multiples. The researchers
K. Choi and M. Song [13], K-Y. Khoo, Z. Yu et al. [14], D. Villeger and V. G. Oklobdzija has developed efficient
circuits based on Booth’s encoding algorithm. The partial products rows can be further reduced by using extension
of Booth’s algorithm for higher radix encoding H. Sam and A. Gupta [16], D. E. Atkin [17]. But high radix
encoding involves complex circuits for partial products generation and its time consuming process. Booth’s
algorithm A.D. Booth [11], Madrid P.E., Millar B. [31] is a powerful algorithm for signed multiplication it considers
negative and positive numbers uniformly.
Booth encoder encodes multiplier bits using Radix 2, Radix 4 or Radix 8 algorithm.
A. Radix 2
The Table I shows truth table for Radix 2 Booth Encoding. Radix 2 Booth’s Multiplier has the following
disadvantages
1. The Algorithm becomes inefficient when there are isolated 1’s.
2. This is inconvenient for designing parallel multipliers since the number of add/subtract operations is
variable.
Table I: Radix 2 Encoding
Bj Bj 1 CODE
0 0 0
0 1 +A
1 0 +A
1 1 +2A
Table II: Radix 4 Encoding
B
j+1 Bj Bj 1 CODE
0 0 0 0
0 0 1 +A
0 1 0 +A
0 1 1 +2A
1 0 0 -2A
1 0 1 -A
1 1 0 -A
1 1 1 0
B. Radix 4
Radix 4 Booth’s Multiplier reduces the number of products by n/2. It overcomes the drawbacks of Radix 2
Booth’s Multiplier. Radix 4 is Modified Booth Encoding(MBE) since the number of partial products is reduced the
hardware and time is reduced. The Table II shows truth table for Radix 4 Modified Booth Encoding(MBE). If A is
multiplicand then partial products will take a value of 0,+A,-A,+2A,-2A. Depending on the coded value of each
group 0 and +A is obtained by selecting zero or A,+2A is obtained by shifting A by one bit position,-A and -2A is
obtained complementing each bit and by adding code polarity Cp=1 at the Least Significant Bit(LSB). Shen et al.
[43] proposed low power 2’s complement multiplier which reduces switching activities of partial products using
radix-4 booth multiplier. The proposed 16x16 bit multiplier was implemented based on Yu, Goldovsky and Mahant
Shetti’s low power approaches and has shown more than 14%, 30% and 31% of power respectively.
C. Radix 8
Radix 8 encoding is extension of Radix 4 encoding. In Radix 8 encoding groups of four bits are taken for coding.
Radix 8 encoding reduces the number of partial products by n/3. The Table III shows truth table for Radix 8 Booth
Encoding. If A is multiplicand then partial products will take a value of 0,+A,+2A,+3A,+4A,-A,-2A,-3A,-4A. The
partial products will take a value of 0,+A,+2A,+4A-A,-2A,-4A are obtained by selecting zero , A, shifting A or by

ISSN 1943-023X 746

Received: 20 October 2018/Accepted: 15 November 2018
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 14-Special Issue, 2018

taking two’s complement of A and by adding one at Least Significant Bit(LSB). Carry propagate addition is to be
done to get 3A and thus increases the complexity of the circuit and the time delay also increases. Hence Booth
encoding is limited to Radix 4 because of increase in complexity and time.
High speed Booth encoded parallel multiplier was proposed by Yeh et al. [70] in this modified booth encoding

Table III: Radix 8 Encoding

B
j+1 Bj Bj 1 Bj 2 CODE
0 0 0 0 0
0 0 0 1 +A
0 0 1 0 +A
0 0 1 1 +2A
0 1 0 0 +2A
0 1 0 1 +3A
0 1 1 0 +3A
0 1 1 1 +4A
1 0 0 0 -4A
1 0 0 1 -3A
1 0 1 0 -3A
1 0 1 1 -2A
1 1 0 0 -2A
1 1 0 1 -A
1 1 1 0 -A
1 1 1 1 0
(MBE) is used for partial products generation and the final addition is performed by multi level conditional sum
adder (MLCSMA).The performance has been increased by 25% and total delay is decreased by 8%.
Low power 2’s complement multiplier was praposed by Chen, Oscal T. C., et al. [71] which minimizes the
switching activities of partial products of radix-4 Booth multiplier. To reduce power concumption column based
adder tree is used. The results has shown more than 31.2%, 19.1% and 33.0% of power consumption compared to
ordinary multiplier. The authors has also presented multiplier with row based hybrid adder trees and results has
shown an reduction of power consumption by 35.3%, 25.3% and 39.6%,24.9% and 36.9% respectively.
Lee, Hanho. [72] implemented Low power poweraware scaled pipelined booth multiplier that use sharing of
common functional unit and the results has shown reduction of 29% and 58% of power consumption over non
scalable booth multiplier for 8-bit and 4-bit multipliers. Thus the proposed method is 20% more power efficient than
non scalable pipelined booth multiplier and speed is also increased due to pipelining.
Power efficient configurable Booth multiplier was proposed by Kuang et al. [73] and the results have shown that
the proposed multiplier is more complex than non configurable Booth multiplier but it has savings in power and
energy. This also gives good accuracy when truncation is applied.
El-Guibaly et al. [75] implemented dependence graph to implement Multiplier and Accumulator Unit (MAC)
based on modified booth multiplier(MBE). The results has shown three times faster than other parallel MAC
schemes that are based on Modified booth algorithm.
Signed and unsigned modified booth encoding (MBE) multiplier is designed by Rajput et al. [74] this reduces
the hardware and area of the chip this in turn reduces the power dissipation and system cost.

VIII. Booth Encoded Wallace Tree Multiplier

Booth Array in combination with Wallace tree structure is fastest with normal area delay product and area power
product. Jagadeshwar Rao M, Sanjay Dubey [37] has designed fast area efficient Booth encoded Wallace Tree
Multiplier and has shown 67% faster than the Wallace Tree Multiplier , 22% and 18% faster than Radix-8 and
Radix-16 Booth Multiplier respectively with efficient use fo area.
Jalil et al. [66] praposed design method for M-bit x N-bit Booth Encoded parallel multiplier. A new algorithm
was praposed by reducing delay inside the branches of Wallace Tree section. The final stage of adding is done by
using optimal carry select adder stage. Booth encoded Wallace Tree Multiplier was implemented by Liao, M. J., et

ISSN 1943-023X 747

Received: 20 October 2018/Accepted: 15 November 2018
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 14-Special Issue, 2018

al. [68] using carry select adder partitioning algorithm. The results has shown 9.12% reduction in delay and 1% less
area overhead.
Rahul D et al. [67] presented Booth Encoded parallel multiplier with four stage pipelining it is implemented at
intermediate nodes. This has increased the speed.
Wallace Tree Multiplier with modified booth algorithm was implemented by Jagadeshwar Rao M, Sanjay Dubey
using Radix-8 booth encoder and the results has shown 67% increase in speed compared to ordinary Wallace Tree
Multiplier.

IX. Vedic Multiplier

Vedic Mathematics is ancient Indian Vedic system of Mathematics. Vedic Multiplier is based on vedic sutras to
improve the speed of multiplier. This ancient system is based on 16 Vedic Sutras which describe natural ways of
solving mathematical problems. Chidgupkar P.D and Karad M.T [28] has praposed vedic algorithms usage in
multiplication process of 8085 and 8086 microprocessors and there was aprreciable time saving in the process. An
NxN bit parallel overlay multiplier architecture was praposed Thapliyal H and Srinivas M.B [29] for high speed
DSP applications. Vedic Multiplier can be used for low power and high speed applications Rabaey J., Chandrakasan
A et al. [30]. It has less complexity compared to booth multiplier. Vedic multiplier requires less hardware. Thus
Vedic multiplier gives numerous advantages in terms of area, power, delay and complexity. Urdhva -Tiryagbhyam
Sutra multiplication technique is applied here. Ramesh Pushpan-gadana, Vineeth Sukumarana et al. [39] has
implemented 8x8 and 16x16 vedic multiplier and Booth wallace tree multilier and vedic multilier has shown that
vedic multiplier is faster than Booth wallace tree multiplier. The vedic multiplier was implemented using reversible
gates by Gowthami. P and R.V.S. Satyanarayana [6] and had got an optimized structure for 2x2 multiplier. M. Akila,
C. Gowribala et al. [40] implemented vedic multiplier using modified Carry Select Adder has shown an increase in
speed. Sheetal N. Gadakh, Amitkumar Khade has implemented vedic multiplier using modified Carry Save Adder
has shown 33.26% redution in delay compared to Ripple Carry Adder and Carry Select Adder.

Fig. 12: 2x2 Vedic Multiplier

Fig. 13: 4x4 Vedic Multiplier

The Figure 12 shows 2 X 2 Vedic Multiplier. The Figure 13 shows 4 X 4 Vedic Multiplier.

ISSN 1943-023X 748

Received: 20 October 2018/Accepted: 15 November 2018
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 14-Special Issue, 2018

X. Conclusion
Array multiplier is simple circuit with small area, low speed and more power consumption. Carry save array
multiplier is also a simple circuit with improvement in speed compared to Array Multiplier and has more power
consumption. Wal-lace Tree Multiplier circuit complexity is more than Array Multiplier but has high speed and
more power consumption with large in area. Dadda Multiplier complexity is high with large area, high seed and less
power consumption. Booth’s Multiplier complexity is high with optimum area, high seed and less power
consumption. Booth Encoded Wallace Tree Multiplier is more complex with large area, high seed and less power
consumption. Vedic Multiplier complexity is medium with optimum area, high seed and less power consumption.

Acknowledgement
I am thankful to my guides Dr. G.M.Sreerama Reddy and Dr. S.Aruna Mastani for their constant support and
valuable suggestions in doing this work.

References
[1] A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing. 2nd edition, Prentice Hall, 1999.
[2] H. A. Al-Twaijry, Area and performance optimized CMOS multipliers, Ph.D. dissertation, Stanford
University, Aug. 1997.
[3] C. S. Wallace, A Suggestion for a Fast Multiplier, IEEE Transactions on Electronic Computers, vol. 13,
pp. 14-17, 1964
[4] L. Dadda, Some Schemes for Parallel Multipliers, Alta Frequenza, vol. 34, pp. 349-356, 1965.
[5] Earl E. Swartzlander, Jr., High-Speed Computer Arithmetic, Chapter 22 in 2ed. Computer Science
Handbook, Boca Raton, FL: Chapman and Hall/CRC, 2004.
[6] Gowthami. P and R.V.S. Satyanarayana, ”Design of an Efficient Multiplier Using Vedic Mathematics and
Reversible Logic”, 2016 IEEE International Conference on Computational Intelligence and Computing
Research.
[7] Poras T. Balsara and David T. Harper, Understanding VLSI bit serial multiplier, IEEE Trans. on Education,
Vol. 39, No. 1, Feb.1996.
[8] R.Gnanasekaran, A fast serial-parallel binary multiplier, IEEE Trans. Computer, Vol. C-34, No. 8,
pp. 741-744, Aug. 1985.
[9] Gensuke Goto, Tomio Sato, Masao Nakajima, and Takao Sukemura, A 54X54 regular structured tree
multiplier, IEEE J. Of Solid State Circuits, Vol.27, No.9, pp. 1229-1236, Sept. 1992.
[10] H. I. Saleh, A. H. Khalil, M. A. Ashour, and A. E. Salama, Novel serial parallel multipliers, IEE Proc-
circuits Devices System, Vol.148, No.4, pp. 183-189, Aug. 2001.
[11] A.D. Booth, A signed binary multiplication technique, Quarterly J.Mech. Appl. Math, Vol. 4, Part 2,
pp. 236-240, 1951.
[12] L. P. Rubinfield, A proof of the modified booth’s algorithm for multiplication, IEEE Trans. on Computers,
Vol. 24, No. 10, pp.1014-1015, Oct. 1975.
[13] K. Choi and M. Song, Design of a high performance 32*32-bit multiplier with a novel sign select Booth
encoder, in Proc. 2001 IEEE Int. Symp. Circuits and Systems, Vol.2, pp.701-704, May 2001.
[14] K-Y. Khoo, Z. Yu, and A.N. Willson, Improved-Booth encoding for low-power multipliers, in Proc. 1999
IEEE Int. Symp. Circuits and Systems, Vol.1, pp.62-65, May 1999.
[15] D. Villeger and V. G. Oklobdzija, ”Analysis of Booth encoding efficiency in parallel multipliers using
compressors for reduction of partial products, Proceedings of the 27th Asilomar Conference on Signals,
Systems and Computers, pp. 781-784, 1993.
[16] H. Sam and A. Gupta, A generalized multibit recoding of twos com-plement binary numbers and its proof
with application in multiplier implementations, IEEE Trans. Computer, Vol.39, No.8, pp.1006-1015, Aug.
1990.
[17] D. E. Atkin, Design Of arithmetic UNITS OF Illiac III: Use of redundancy and higher radix method, IEEE
Trans. on Computer, Vol. C-19, No. 8, pp. 720-733, Aug. 1970.
[18] C.R. Baugh, and B.A. Wooley, A two’s complement parallel array multiplication algorithm, IEEE Trans.
Computers, Vol. 22, No. 12,pp. 1045-1047, Dec. 1973.
[19] P.E. Blankenship, Comments on a two’s complement parallel array multiplication algorithm, IEEE Trans.
Computers, Vol. 23, pp.1327, 1974.

ISSN 1943-023X 749

Received: 20 October 2018/Accepted: 15 November 2018
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 14-Special Issue, 2018

[20] Ahmed M. Shams, Tarek K. Darwish and Magdy A. Bay-oumi, Performance analysis of low-power 1-bit
CMOS full adder cells, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 10, No.
1, pp. 20-29, Feb. 2002.
[21] Hung Tine Bui, Yuke Wang, and Yingtao Jiang, Design and analysis of low power 10-transistor full adder
using novel XOR XNOR gates, IEEE Trans. On Circuits And Systems-II: Analog And Digital Signal
Processing, Vol.49, No.1, pp. 25-30, Jan. 2002.
[22] Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, and
Koichiro Mashiko, An 8.8-ns 54 x 54-Bit multiplier with high speed redundant binary architecture, IEEE J.
of Solid State Circuits, Vol.31, No.6, pp. 773-783, June 1996.
[23] D. T. Shen and A. Weinberger, 4-2 carry-save adder implementation using send circuits, In IBM Technical
Disclosure Bulletin, pp. 3594-3597, February 1978.
[24] Qi Wang and Yousef R. Shayan, A versatile signed array multiplier suitable for VLSI implementation, in
proc. IEEE CCECE 2003, Vol. 1, pp 199-202, May 2003.
[25] K. Prasad and K.K. Parhi, Low-power 4-2 and 5-2 compressors, Proc. of 2001 Asilomar Conf. on Signals,
Systems and Computers,Pacific Grove, CA, USA, Vol. 1. pp 129-133, Nov. 2001.
[26] P.J. Song and G. De Micheli, Circuit and architecture trade-of for high-speed multiplication, IEEE J. Solid-
State Circuits, Vol.26, pp.1184-1198, Sept. 1991.
[27] Shen-Fu Hsiao, Ming-Roun Jiang, and Jia-Sien Yeh, Design of high-speed low-power 3-2 counter and 4-2
compressor for fast multipliers, IEE Electronics Letters, Vol. 34, No. 4, pp. 341-343, Febr. 1998.
[28] Chidgupkar P.D. and Karad M.T. (2004), The Implementation of Vedic Algorithms in Digital Signal
Processing, Global Journal of Engg Education, Vol. 8, No.2, Australia.
[29] Thapliyal H. and Srinivas M.B. (2004), High Speed Efficient N x N Bit Parallel Hierarchical Overlay
Multiplier Architecture Based on Ancient Indian Vedic Mathematics, Transactions on Engineering,
Computing and Technology, Vol.2.
[30] Rabaey J., Chandrakasan A. and Nikolic B. (2002), Digital Integrated Circuits: A Design Perspective, 2nd
edition, Prentice Hall.
[31] Madrid P.E., Millar B. and Swartzlander Jr E.E. (1993), Modified Booth Algorithm for High Radix Fixed-
Point Multiplication, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1(2):
pp.164-167.
[32] Au L.S. and Burgess N. (2002), A (4:2) adder for unified GF(p) and GF(2n) Galois field Multipliers,
Proceedings of 36th IEEE Asilomar Conference on Signals, Systems, and Computers, vol. 2,
pp. 1619-1623.
[33] Chittibabu A., Sola V.K. and Raj C.P. (2006), ASIC Implementation of New Architecture for constant
coefficient Dadda multiplier for High-Speed DSP applications, Proceedings of the National Conference on
Recent trends in Electrical, Electronics and Computer Engineering, JCECON, pp. 299 304.
[34] Kokila Bharti Jaiswal, Nithish Kumar V, Pavithra Seshadri and Laksh-minarayanan G, ”Low Power
Wallace Tree Multiplier Using Modified Full Adder”, 2015 3rd International Conference on Signal
Processing, Communication and Networking (ICSCN).
[35] R. Bala Sai Kesava,B. Lingeswara rao, K. Bala Sindhuri,N. Udaya Kumar, ”Low Power And Area Efficient
Wallace Tree Multiplier Using Carry Select Adder With Binary To Excess-1 Converter”,2016 Confer-ence
on Advances in Signal Processing (CASP) Cummins College of Engineering for Women, Pune. Jun 9-11,
2016.
[36] Ramanathan P, Kowsalya P & Anitha P, ”Modified Low Power Wal-lace Tree Multiplier Using Higher
Order Compressors”, Taylor & Francis: International Journal of Electronics Letters, Jan 2016, DOI:
10.1080/21681724.2016.1138509.
[37] Jagadeshwar Rao M, Sanjay Dubey ”A high speed and area efficient Booth recoded Wallace tree multiplier
for fast arithmetic circuits”, 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics &
Electronics (PRIMEASIA),5th - 7th December 2012, pp 220-223.
[38] Sandeep Kakde, Shahebaj Khan, Pravin Dakhole, Shailendra Bad-waik,”Design of Area and Power Aware
Reduced Complexity Wallace Tree Multiplier”,2015 International Conference on Pervasive Computing
(ICPC).
[39] Ramesh Pushpangadana, Vineeth Sukumarana, Rino Innocenta, Dinesh Sasikumara & Vaisak Sundara,
”High Speed Vedic Multiplier for Digital Signal Processors”, IETE JOURNAL OF RESEARCH , Vol 55,
ISSUE 6 , NOV-DEC 2009

ISSN 1943-023X 750

Received: 20 October 2018/Accepted: 15 November 2018
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 14-Special Issue, 2018

[40] M. Akila, C. Gowribala, S. Maflin Shaby, “Implementation of High Speed Vedic Multiplier using Modified
Adder”, International Conference on Communication and Signal Processing, April 6-8, 2016,
India,PP.2244-2248.
[41] Sheetal N. Gadakh, Amitkumar Khade, ”Design and Optimization of 1616 Bit Multiplier Using Vedic
Mathematics”,2016 International Conference on Automatic Control and Dynamic Optimization Techniques
(ICAC-DOT) International Institute of Information Technology (IIIT),pp,460-464.
[42] N.Ravi, Y.Subbaiah, Dr.T.Jayachandra Prasad and Dr.T.Subba Rao ”A Novel Low Power, Low Area Array
Multiplier Design for DSP Ap-plications”, Proceedings of 2011 International Conference on Signal
[43] Processing, Communication, Computing and Networking Technologies (ICSCCN 2011), pp. 254-257.
[44] Shen, NY, Chen & Oscal, TC 2002 ,’Low-power multipliers by min-imizing switching activities of partial
products’, IEEE International Symposium on Circuits and Systems, ISCAS, vol. 4, pp. 93-96.
[45] More, TV & Kshirsagar, R V 2011,’Design of low power column bypass multiplier using FPGA’ , 3rd
International Conference on Electronics Computer Technology (ICECT), vol. 3, pp. 431-435.
[46] Economakos, G, Bekiaris, D, & Pekmestzi, K 2010,’A mixed style architecture for low power multipliers
based on a bypass technique’ ,5th International Conference on Design and Technology of Integrated
Systems in Nano scale Era (DTIS), pp. 1-6.
[47] Rashidi, Bahram; Rashidi, Bahman; Pourormazd, Majid 2011, ’Design and implementation of low power
digital FIR filter based on low power multipliers and adders on xilinx FPGA’, Institute of Electrical and
Electronics Engineers conf.
[48] Rao, PV, Raj, PCP & Ravi, S 2009,’VLSI Design and Analysis of Multipliers for Low Power’, IEEE
Conference Publications, Fifth Inter-national Conference on Intelligent Information Hiding and Multimedia
Signal Processing, pp. 1354-1357.
[49] Wen, MC, Wang, SJ & Lin, YN 2005,’Low power parallel multiplier with column bypassing’ , IEEE
Conference Publications, IEEE International Symposium on Circuits and Systems, vol. 2,pp. 1638-1641.
[50] Hwang, YZ, Lin, JF, Sheu, M & Sheu, CJ 2007, ’Low Power Multipliers Using Enhenced Row Bypassing
Schemes’ , IEEE Workshop on Signal Processing Systems, pp. 136-141.
[51] Bajaj, Ronak; Chhabra, Saransh; Veeramachaneni, Sreehari; Srinivas, M B,’A novel, low-power array
multiplier architecture’, IEEE 2009 9th International Symposium on Communications and Information
Technology (ISCIT), pp:119-123.
[52] Chua-Chin Wang; Chia-Hao Hsu; Gang-Neng Sung; Yu-Cheng Lu,’A Signed Array Multiplier with
Bypassing Logic’, Springer-Verlag Journal of Signal Processing Systems,Feb 2012,Volume:66, Issue:2, pp.
87-92.
[53] Das, Debaprasad; Rahaman, Hafizur,’ A Novel Signed Array Multi-plier’, IEEE 2010 International
Conference on Advances in Computer Engineering (ACE),2010 , pp. 19-23.
[54] Pieper, Leandro Zafalon; da Costa, Eduardo A. C.; Monteiro, Jose C,’ Combination of radix-2m multiplier
blocks and adder compressors for the design of efficient 2’s complement 64-bit array multipliers’, IEEE
2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), pp. 1-6.
[55] Debaprasad Das and Hafizur Rahaman, ’A Novel Signed Array Multiplier’, IEEE Computer Society,2010
International Conference on Ad-vances in Computer Engineering,978-0-7695-4058-0/10 2010 IEEE DOI
10.1109/ACE.2010.29.
[56] Leandro Zafalon Pieper, Eduaro A.C.da Costa, Jose C. Monteiro,’ Combinatiomn of Radix- 2m Multiplier
Blocks and Adder Compressors for the Design of Efficient 2’s Complement 64-bit Array Multipliers’,
978-1-4799-1132-5/13/ 2013 IEEE.
[57] Singh, Raminder & Kumar, Parveen & Lakha, Balwinder. (2018). Performance Analysis of 32Bit Array
Multiplier with a Carry Save Adder and with a Carry-Look-Ahead Adder. International Journal of Recent
Trends in Engineering.
[58] Jia, Song, Shigong Lyu, Xiayu Li, Yandong He, Simplified Carry Save Adder-Based Array Multiplier
Scheme and Circuits Design. International Journal of Circuit Theory and Applications, vol. 43, no. 9, 2015,
pp. 1226-1234.
[59] Fonseca, M., E.da Costa, S. Bampi, J. Monteiro, Design of a Radix-2m Hybrid Array Multiplier Using
Carry Save Adder. 2005 18th Symposium on Integrated Circuits and Systems Design, 2005, pp. 172-177.
[60] Paul, B. C., H. Soeleman, K.Roy. An 8x8 Sub-Threshold Digital CMOS Carry Save Array Multiplier.
Proceedings of the 27th European Solid-State Circuits Conference, 2001, pp. 377-380.
[61] Preet, Raminder, Pal Singh, Parveen Kumar, Balwinder Singh, ’Performance Analysis of 32-Bit Array
Multiplier with a Carry Save Adder and with a Carry Look Ahead Adder’. 2009.

ISSN 1943-023X 751

Received: 20 October 2018/Accepted: 15 November 2018
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 14-Special Issue, 2018

[62] Zhan Yu, L. Wasserman and A. N. Willson, ”A painless way to reduce power dissipation by over 18% in
Booth-encoded carry-save array multi-pliers for DSP,” 2000 IEEE Workshop on SiGNAL PROCESSING
SYS-TEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528), Lafayette, LA, 2000,
pp. 571-580. doi: 10.1109/SIPS.2000.886-755.
[63] Townsend, Whitney J. Swartzlander, Earl E., Jr., Abraham, Jacob A. A Comparison of Dadda and Wallace
Multiplier Delays. Advanced Signal Processing Algorithms, Architectures, and Implementations.
Conference, vol. 5205, 2003, pp. 552-561.
[64] Jeevan, B. ; Narender, S. ; Reddy, C.V.K. ; Sivani, , A High Speed Binary Floating Point Multiplier Using
Dadda Algorithm. 2013 Inter-national Mutli-Conference on Automation, Computing, Communication,
Control and Compressed Sensing (IMac4s), 2013, pp. 455-460.
[65] Crawley, D. G., and G. A. J. Amaratunga, 8*8 Bit Pipelined Dadda Multiplier in CMOS. IEE Proceedings
G (Electronic Circuits and Systems), vol. 135, no. 6, 1988, pp. 231-240.
[66] Muhammad Hussnain Riaz, Syed Adrees Ahmed, Qasim Javaid, Tariq KamalLow Power 44 Bit Multiplier
Design Using Dadda Algorithm and Optimized Full Adder. 2018 15th International Bhurban Conference
on Applied Sciences and Technology (IBCAST), 2018.
[67] Fadavi-Ardekani, Jalil. M*N Booth Encoded Multiplier Generator Using Optimized Wallace Trees. IEEE
Transactions on Very Large Scale Integration Systems, vol. 1, no. 2, 1993, pp. 120-125.
[68] Rahul D Kshirsagar, Aishwarya.E.V., Ahire Shashank Vishwanath, P Jayakrishnan, Implementation of
Pipelined Booth Encoded Wallace Tree Multiplier Architecture. 2013 International Conference on Green
Computing, Communication and Conservation of Energy (ICGCE), 2013, pp. 199-204.
[69] M.-J. Liao, C.-F. Su, C.-Y. Chang and Allen C.-H. Wu, A Carry-Select-Adder Optimization Technique for
High-Performance Booth-Encoded Wallace-Tree Multipliers. 2002 IEEE International Symposium on
Circuits and Systems. Proceedings (Cat. No.02CH37353), vol. 1, 2002, pp. 81-84.
[70] Jagadeshwar Rao M, Sanjay Dubey, “A High Speed Wallace Tree Multiplier Using Modified Booth
Algorithm for Fast Arithmetic Cir-cuits”, IOSR Journal of Electronics and Communication Engineering
(IOSRJECE) ISSN: 2278-2834, ISBN No: 2278-8735 Volume 3, Issue 1 (Sep-Oct 2012), PP 07-11.
www.iosrjournals.org.
[71] Yeh, Wen-Chang, and Chein-Wei Jen. High-Speed Booth Encoded Parallel Multiplier Design. IEEE
Transactions on Computers, vol. 49, no. 7, 2000, pp. 692-701.
[72] Oscal T.-C. Chen, Sandy Wang, and Yi-Wen Wu, Minimization of Switching Activities of Partial Products
for Designing Low-Power Multipliers. IEEE Transactions on Very Large Scale Integration Systems, vol.
11, no. 3, 2003, pp. 418-433.
[73] Lee, Hanho. A Power-Aware Scalable Pipelined Booth Multiplier. IEEE International SOC Conference,
2004. Proceedings., 2004, pp. 123-126.
[74] Kuang, Shiann-Rong, and Jiun-Ping Wang. Design of Power-Efficient Configurable Booth Multiplier.
IEEE Transactions on Circuits and Systems, vol. 57, no. 3, 2010, pp. 568-580.
[75] Rajput, Ravindra P., and M. N. Shanmukha Swamy. High Speed Modified Booth Encoder Multiplier for
Signed and Unsigned Numbers. 2012 UKSim 14th International Conference on Computer Modelling and
Simulation, 2012, pp. 649-654.
[76] El-Guibaly, Fayez. A Fast Parallel Multiplier-Accumulator Using the Modified Booth Algorithm. IEEE
Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing, vol. 47, no. 9, 2000,
pp. 902-908.

ISSN 1943-023X 752

Received: 20 October 2018/Accepted: 15 November 2018