CHAPTER 7

CMOS Circuit Design Styles

Chapter 6 described basic CMOS logic gates emphasizing their electronic parameter
characteristics. We now look at CMOS design styles that take different approaches to
making an arbitrary logic function. Each design style has unique advantages in circuit
speed, power, and physical size of the die. No design style is superior in all three charac-
teristics.
CMOS combinational logic has several design style options. The complementary static
design style is dominant in CMOS circuits (Chapter 6). It is a robust, lower power design,
while high-performance circuits may use dynamic logic styles more suitable for high speed
with less concern for power. Dynamic logic design may be used on smaller sections of the
integrated circuit (IC) that requires repetitive high-speed operations, such as an arithmetic
logic unit (ALU). A third logic design style uses pass-transistor or pass-gate elements as
basic switches using fewer transistors to implement a function. We want to understand
these combinational logic design styles and their trade-offs as options for the designer
and for diagnostic knowledge necessary for test engineers, failure analysts, and reliability
engineers.

7.1. Boolean Algebra to Transistor Schematic Transformation

Static, fully complementary CMOS designs can use inverter, NAND, NOR, and trans-
mission gates as building blocks for more complex logic circuits. This chapter extends
these simple designs to build “complex” combinational logic circuits that can be im-
plemented for arbitrary Boolean functions. This complementary design style has good
noise margins and low static power dissipation. CMOS static complementary gates have
two transistor networks (nMOS and pMOS) whose topologies are related (Figure 7-1).
Each nMOS transistor is paired with a pMOS transistor as are the simple gates of
Chapter 6. The pMOS transistor net is connected between the power supply and the

185
186 CMOS Circuit Design Styles

VDD

p-MOS

Inputs Output

n-MOS

GND
FIGURE 7-1.
Standard configuration of a CMOS complementary gate.

logic gate output, while the nMOS transistor topology is connected between the output
and ground.
The nMOS transistor network is referred to as a pull-down network and the pMOS
as a pull-up network (Figure 7-1). The output node pulls up to VDD when the pMOS
transistors are activated, while the pull-down net pulls the output node down to ground
when the nMOS transistors are activated. We will learn an algorithmic technique that
converts arbitrary Boolean algebra to a transistor CMOS schematic.
A Boolean function transforms to a transistor schematic with a straightforward design
procedure:

1. Derive the nMOS transistor topology with the following rules:

• Product terms (AND operations) in the Boolean function are implemented with
series-connected nMOS transistors.
• Sum terms (OR operations) are mapped to nMOS transistors connected in parallel.
2. The pMOS transistor network has a dual or complementary topology with respect to
the nMOS net. This means that serial transistors in the nMOS net convert to parallel
transistors in the pMOS net, and parallel connections within the nMOS block translate
to serial connections in the pMOS block.
3. Add an inverter to the output if the nonnegated (positive) function is needed. An inverter
added to a NAND or NOR function produces the AND and OR function. Some examples
in this chapter require an inverter to fulfill the function.

This procedure is illustrated with three examples.

7.1 Boolean Algebra to Transistor Schematic Transformation 187

EXAMPLE 7-1
Design a complementary static CMOS 2NAND gate at the transistor level.

The previously listed rules define F = AB so the nMOS net has two series connected
transistors, while the pMOS net has the complementary topology, that is, two transistors in
parallel.
Step 1: Draw the nMOS net of two series transistors.
Step 2: Add the pMOS net of two parallel transistors as the complement.

A B

EXAMPLE 7-2
Design a complementary static CMOS XOR gate at the transistor level.
The XOR gate Boolean expression F has four literals and is

F = X ⊕ Y = XY + XY

F is the sum of two product terms. The design steps are as follows:

1. Derive the nMOS transistor topology with four transistors, one per literal in the Boolean
expression. The transistors driven by X and Y are in series as well as the devices
188 CMOS Circuit Design Styles

driven by X and Y . These two transistor groups are in parallel, since they are additive
in the Boolean function. The nMOS transistor net is

Output

X X

Y Y

nMOS net

2. Implement the pMOS net as a dual topology to the nMOS net. The pMOS transistors
driven by X and Y are in parallel, as well as the devices driven by X and Y . These
transistor groups are then in series, since they are parallel in the nMOS net. The out
node is the negated function F.
3. Finally, add an inverter to obtain the function F, so that F = out = X Y + X Y . The
signal inputs have mutual connections that we omit for schematic clarity. Notice that to
simplify the schematic we ignored the inverters needed for x and y.

pMOS net

X Y

X Y
Out
F

X X

Y Y

nMOS net

Steps 1–3 show that any Boolean function, regardless of its complexity, can be implemented
with a CMOS complementary structure and an inverter. A more complicated example is
developed.
7.1 Boolean Algebra to Transistor Schematic Transformation 189

EXAMPLE 7-3
Design the nMOS transistor net for the Boolean function F = X + {Y [Z + T W ]}
The nMOS transistor network is connected between the output and ground terminals.
The higher-level function F is a sum of two terms

F = X + {operation A}

where operation A stands for the logic within the braces of F. The transistor version of this
sum is

Out

y
z
X ⫹ {Operation A} X Operation A t
w

nMOS net
Parallel
connection

Now we design the transistor topology that implements the block operation A whose Y
operation is an AND, that is,

operation A = Y · [operation B]

Hence the design topology is a transistor controlled by input Y in series with a third box
that will implement operation B, that is,

Out
Serial
connection
X y

z
Operation B t Y ⭈ {Operation B}
w

nMOS net

We then design the topology of operation B. This is a transistor controlled by input Z in

parallel with two transistors in series: one controlled by input T , and the other by input W .
The complete nMOS network is shown.
The pMOS block is a dual topological structure and we then connect an inverter to its
output to form the nonnegated function F = X + {Y [Z + T W ]}.
190 CMOS Circuit Design Styles

pMOS net

W T
Y

Out
F
nMOS net

X Y

T
Z
W

Self-Exercise 7-1
(a) Design the transistor schematic for F = ABCD + E.
(b) Discuss the rise and fall time issues.

Self-Exercise 7-2
Design the transistor schematic for F = (A + B) (C + D) + E.

Self-Exercise 7-3
Design the transistor schematic for F = (X + Y )[Z + (W T )(Z + X )].

7.2. Synthesis of DeMorgan Circuits

Thus far, the function F was created from the natural CMOS negated function F by adding
an inverter at the output. There is another approach that uses DeMorgan’s law to convert
a NAND gate to an OR equivalent and a NOR to an AND gate. The technique is similar
7.2 Synthesis of DeMorgan Circuits 191

to that just described with examples, but eliminates the output inverter. The DeMorgan
equivalent NAND gate to OR gate is

F = AB = A + B

The DeMorgan equivalent on the right side of the equation turns our focus to the pMOS
transistor network where F = 1 on any logic-0. Our thinking now asks what logic-0
signals will turn on the pMOS transistors and cause a logic-1 at the output.
Similarly, the NOR expression converts to the DeMorgan AND gate as

F = A+B = AB

The right side of the equation activates the pMOS network F to a logic-1 when A and B
are both logic-0. Our interest lies in a function that is not negated. The AND DeMorgan
equivalent circuit is

F = AB = A + B

The negated function on the right implies a NOR pull-down network with transistor inputs
A and B. The pull-up network has two series pMOS transistors also with inputs A and B.
The schematic is given in Figure 7-2. The circuit performs the function F = AB without
adding an output inverter to a NAND gate. The original AND gate is equivalent to a NOR
gate if the signal polarities are reversed on the NOR gate.
At first it seems that we have created a need for two inverters to negate the inputs A
and B. This may be true, but signal polarities on an input node are not uniformly the
positive literal value. They may be the literal complement. A flip-flop circuit inherently
provides a logic signal and its complement. The assumption that the DeMorgan circuit
requires additional inverters for each literal has no more meaning on an IC than if we

B
F

A B

FIGURE 7-2.

An AND gate function as the equivalent DeMorgan NOR gate.

192 CMOS Circuit Design Styles

said that NAND and NOR gates needed signal polarity correction to get true values of the
literals. Whether one implementation has fewer transistors will depend on the local signal
situation. We are stressing flexible design to optimize local gate designs. These are tools
at the designer’s discretion.

EXAMPLE 7-4
Repeat the XOR using the DeMorgan conversion technique to implement the function
without using an inverter. Verify the operation with a truth table.

F = X ⊕ Y = XY + XY

The DeMorgan equivalent is

F = X Y + X Y = (X + Y ) (X + Y )

X X

Y Y
F

X Y

X Y

The schematic shows the pMOS net activating a logic-1 for F = X Y + X Y when the signal
polarities are inverted. The truth table is consistent with the transistor schematic.

X Y X Y F = XY + XY
0 0 1 1 0
0 1 1 0 1
1 0 0 1 1
1 1 0 0 0

Notice that the nMOS topology of Example 7.2 is the pMOS topology of the DeMorgan
design given in this example. Likewise the pMOS topology is the same as the nMOS
topology of the DeMorgan design. However, the signal polarities are reversed.
7.2 Synthesis of DeMorgan Circuits 193

EXAMPLE 7-5
Redesign the function F = X + {Y [Z + T W ]} without using an inverter. Compare your
solution with Example 7-3.
The DeMorgan equivalent is

F = X [Y + Z (T + W )]

whose circuit is on the right.

X Y

T
Z
W
F
X

W T
Y

Self-Exercise 7-4
Derive the equivalent CMOS transistor circuit for F = A + B without an output inverter.

Self-Exercise 7-5
Design the transistor level schematic for F = (X + Y )[Z + (W T )(Z + X )] without using
an output inverter. Compare your solution with Self-Exercise 7-3.

Self-Exercise 7-6
Design an equivalent DeMorgan logic gate schematic for F = A + (B + C)D E.

Self-Exercise 7-7
Design an equivalent DeMorgan logic gate schematic for F = W X Y + W X Y + W X Y.
What function is performed?
194 CMOS Circuit Design Styles

7.3. Dynamic CMOS Logic

Previous design techniques showed that conventional combinational CMOS circuits do
not use a clock signal. If inputs are held stable, then the circuits retain their output state (all
circuit nodes remain at their valid quiescent logic values) as long as power is maintained.
Dynamic circuits require a clock signal, but they are faster, smaller, and are used for IC
subcircuits that are data processing intensive. We will develop this design style exploring
dynamic CMOS strengths and weaknesses.

7.3.1. Dynamic CMOS Logic Properties

A dynamic CMOS gate implements the logic with a block of transistors (usually nMOS
for its higher carrier mobility). The output node is connected to ground through an nMOS
transistor logic block and a single nMOS evaluation transistor (Figure 7-3). The output
node is connected to the power supply through one precharge pMOS transistor. The logic
gate has two phases: precharge and evaluation. A global clock drives the precharge and
evaluation transistors. During precharge, the global clock goes low turning the pMOS
transistor on and the nMOS off. The gate output goes high (it is being precharged) while
the block of nMOS transistors are driven to the Off-state. All inputs to the nMOS logic
block must have logic-0 during precharge. This disconnects the logic block transistors
from the output precharge.
In the evaluation phase, the clock is driven high turning the pMOS device off and the
nMOS on. The input signals determine if there is either a low or high impedance path
from the output to ground. If the logic does not turn on transistors in the n-logic block
giving a path from the out node to ground, then the out node floats at the precharged logic
high voltage. If the nMOS logic transistors provide a path to GND, then the output node
is logic-0.

Global
clock Precharge
transistor out

CL
Logic
Inputs
block

Evaluate
transistor

FIGURE 7-3.

Basic structure of a dynamic CMOS gate.

7.3 Dynamic CMOS Logic 195

The precharge and evaluation transistors never conduct simultaneously, which elimi-
nates through current with its power loss and speed degradation. The design also reduces
the capacitance at the out-node, since there is only one pMOS transistor. For example, a
static complementary NAND gate has more than one parallel pMOS transistor tied to the
out-node and that extra drain capacitance loads the output node. Conveniently, if the logic
state determined by the inputs is a logic-1 (VDD ) then the rise time is effectively zero. The
lower capacitance, the near zero rise time for a logic-1 output, the reduced through cur-
rent during a transition, and reduced area makes dynamic logic a favorite for high-speed
applications.
Dynamic circuits with an n-input gate use only n + 2 transistors instead of the 2n
devices required for the complementary CMOS static gates. Dynamic CMOS gates have
a drawback. When the out in Figure 7-3 is evaluated high, then the output node is in the
high-Z state, since there is no electrical path to VDD or ground. This exposes the node
to leakage induced drift, noise fluctuations, and possible charge sharing within the logic
block thus degrading its voltage. The output load capacitor will slowly discharge due to
transistor Off-state leakage currents, and may lose its logic value. This limits the low
frequency operation of the circuit. The nMOS transistor gate inputs can only change only
during evaluation since charge redistribution from the output capacitor to internal nodes
of the nMOS logic block may drop the output voltage when it has a logic high. We will
analyze charge sharing in the next section.
Dynamic CMOS logic families have the following properties:

Advantages
− They use fewer transistors and therefore less area than a complementary transistor
design.
− Fewer transistors present smaller input capacitance to previous driving gates and there-
fore provide faster switching speed.
− Gates are designed and transistors sized for fast switching characteristics. High-
performance circuits use these families.
− The logic transition voltage for output low-to-high is not a transition since the output
node is precharged before the event. Therefore, the low-to-high transition is said to
have zero rise time.
− There is no through or short-circuit current so power is reduced and speed is increased.

Disadvantages
− Each gate needs a clock signal that must be routed through the whole circuit. This
requires precise timing control.
− Clock circuitry runs continuously, drawing significant power.
− The circuit loses its state if the clock stops.
− Dynamic circuits are more sensitive to noise.
− Clock and data must be carefully synchronized to avoid erroneous states.
196 CMOS Circuit Design Styles

We will next look at the dynamic circuit property of charge sharing, and then see how
the domino version solves many of these problems.

7.3.2. Charge Sharing in Dynamic Circuits

The generic charge-sharing problem involves switches and charged capacitors and is a
rearrangement of electrons when a switch is closed after a precharge. Switching exposes
a fixed amount of charge to a different capacitive environment causing node voltage
changes. This occurs in dynamic circuits. The circuit is first precharged high followed
by an evaluation mode where the precharge can partially trickle into the n-logic block
when certain nMOS transistors turn on but there is no direct path to ground. This reduces
the voltage at the output node. Analysis uses the principle of charge conservation when
switches isolate a circuit. Charge is Q = C V and Q is constant in a closed system. Q has
the unit of coulombs (C).
Figure 7-4 shows a dynamic circuit design of a 3NAND gate. The precharge phase with
Clk = 0 charges capacitances connected to the output node. During precharge C L accepts
an initial charge Q init = C L VDD . When the clock returns to the logic-high evaluation
mode, then that initial charge will spread into the n-logic block if paths are open. Assume
that only the top transistor is on during evaluation. Then, capacitance C1 accepts charge
from the output node. The total charge in the system in the same as the initial charge so
the final voltage is calculated by

Q init = C L VDD (7-1)

VDD

Vout

CL
M1

Clk M2
C1

M3

FIGURE 7-4.

Dynamic CMOS 3NAND gate.

7.3 Dynamic CMOS Logic 197

When M1 turns on

Q init = Q final = C L VDD = C L Vfinal + C1 Vfinal (7-2)

CL
Vfinal = VDD (7-3)
C L + C1

If the M1 source voltage attempts to rise higher than VDD − Vtn , then transistor M1
turns off. VS1 cannot rise higher than VG1 − Vtn = VDD − Vtn . When the circuit finishes its
charge transfer there is no current in the transistor, so VD = VS . The following example
will illustrate how to deal with this situation.

EXAMPLE 7-6
The 3NAND dynamic gate is precharged, and then the top transistor M1 turns on. Given
VDD = 1.5 V, Vtn = 0.4 V, C L = 150 fF, C1 = 25 fF, and C2 = 50 fF, what is the final
voltage?

Q init = C L VDD = 150 fF × 1.5 V = 225 fC

Q final = Q init = 225 fC = C L Vfinal + C1 Vfinal
225 fC = (150 fF)(Vfinal ) + (25 fF)(Vfinal )

and
225 fC
Vfinal = = 1.286 V
175 fF
1.5 V

Clk

Vout

CL
M1

M2 C1

M3
C2
198 CMOS Circuit Design Styles

But as the source of M1 rises toward 1.286 V, it will stop at VG − Vtn = 1.5 − 0.4 = 1.1 V.
Therefore, Vfinal = 1.286 V is incorrect. When VS1 = 1.1 V, M1 turns off and VD1 = Vfinal .
The charge on the drain is less than Q init by the amount of charge leaked into C1 . That
leaked charge is

Q 1 = 1.1 V(25 fF) = 27.5 fF.

Q final 225 fC − 27.5 fC

Then VD1 = = = 1.317 V
150 fF 150 fF

Self-Exercise 7-8
VDD = 2.0 V and Vtn = 0.5 V. During evaluation, Y and T are activated. What is the final
voltage when the evaluation mode settles? Write the Boolean expression for F.
2V

F
Y
200 fF
Clk X Z 125 fF
T

W
75 fF

Answer: Vfinal = 1 V, which is an invalid logic state.

Self-Exercise 7-9
Calculate C1 so that the final voltage is determined by M1 that is just at cut-off. C L = 175
fF, VDD = 1.5 V, and Vtn = 0.4 V.
7.4 Domino CMOS Logic 199

VDD

Vout

M1 CL

Clk
M2
C1
M3

Answer: C1 = 63.6 fF

7.4. Domino CMOS Logic

Domino CMOS eliminates the charge share problem and has other advantages. It was
proposed in 1982 [1]. Figure 7-5 shows a domino design. The global clock, the precharge
and evaluation transistors, and the n-logic block work as before, but an inverter and a

Global Latch
clock transistor

out out

Logic
Inputs
block

Evaluate
transistor

FIGURE 7-5.
Domino CMOS logic gate with a weak pMOS feedback transistor.
200 CMOS Circuit Design Styles

pull-up transistor are added to the out-node. The inverter drives the domino output to a
strong logic state forcing the circuit output to be 0 V during precharge. That is an advantage
since the signal inputs at the next domino stage must be logic-0 during precharge so there
is no path to GND. The inverter conveniently provides this.
A weak pMOS feedback transistor is added to latch the internal floating node high
when out is high (Figure 7-5). The latch transistor holds out at VDD so that its voltage will
not drop from charge sharing or leakage currents through the logic block transistors during
evaluation. If the nMOS logic block discharges the out-node to GND during evaluation
(Figure 7-5), then the inverter output signal out goes high, turning off the feedback pMOS.
When out is evaluated or precharged high, then the inverter output goes low turning on
the feedback pMOS device providing a low impedance path to VDD . This prevents the
out-node from floating making it less sensitive to node voltage drift, noise, and current
leakage. The latch transistor forms a positive feedback loop with the inverter.
The W/L of the latch transistor must be kept small with respect to the nMOS pull-down
transistors to minimize the influence of contention during a high-to-low transition. The
domino configuration is the most common form of dynamic gate achieving a 20–50%
speed performance increase over static logic. It is a popular subcircuit for fast adders and
arithmetic logic units ALUs.
Figure 7-6 shows domino 2OR and 2AND logic gates. The nMOS pull-down network
is the same as for the complementary CMOS designs earlier in this chapter.
Domino CMOS with its output inverter allows logic gate cascading since all inputs are
naturally set to zero during precharge avoiding erroneous evaluation from different delays
(Figure 7-7). All logic blocks must have zero input signals during precharge to avoid any
paths from out to ground.

2V 2V

F
F
Clk
Clk A

A B
B

(a) (b)

FIGURE 7-6.
Domino circuits for (a) 2OR and (b) 2AND.
7.4 Domino CMOS Logic 201

Clk Clk

n-net n-net

FIGURE 7-7.
Cascaded domino circuits.

Domino logic uses only noninverting gates making it an incomplete logic family. There
are techniques to achieve an inverting domino circuit, but they will not be discussed in
this book.

EXAMPLE 7-7
Draw the domino transistor schematic for F = A + BC.

B
Clk
A
C

Self-Exercise 7-10
Draw the schematic for a domino circuit to perform F = (A + B) C (ED + G).
202 CMOS Circuit Design Styles

Self-Exercise 7-11
A domino circuit performs F = [AC + (BC)(AC)]B.
(a) Draw the transistor circuit.
(b) Minimize the function and redraw the schematic.
Answer: F = ABC

Self-Exercise 7-12
A domino circuit performs F = AB. Draw and implement this function. Can the n-logic
block be converted to a DeMorgan equivalent circuit and fulfill the AND function? Show
your work using truth tables.

7.5. NORA CMOS Logic

A design modification to domino CMOS logic eliminates the output buffer without com-
promising race problems between clock and data that arise when cascading dynamic gates.
NORA CMOS (No Race CMOS) avoids race problems by cascading alternate nMOS and
pMOS blocks for logic evaluation. The cost is routing and controlling two complemented
clock signals. The cascaded NORA gate structure is shown in Figure 7-8. The pMOS logic
block takes its output from the evaluation transistor drain. When the global clock (GC) is
low (GC is high), the nMOS logic block output nodes are precharged high, turning off the
pMOS logic block transistors. The outputs of gates with pMOS logic blocks are precharged
low at the nMOS precharge transistor drain. All logic blocks are in the precharge state
until the clocks reverse their polarity. When the clocks change to the evaluate state, the
first nMOS logic block is driven first, and it starts the logic operation cascade.

GC GC GC

nMOS pMOS nMOS

Logic Logic Logic
block block block

FIGURE 7-8.

NORA CMOS cascaded gates.

7.6 Pass Transistor Logic 203

7.6. Pass Transistor Logic

Pass transistor logic uses either single transistors or transmission gates as switches to
carry logic signals from node to node instead of connecting output nodes directly to VDD
or ground. Figure 7-9 shows a pass transistor logic circuit for F = AB. When A = B = 1,
then F = 1. The pass transistor connecting node-F to ground keeps node-F from floating
when A = 0 or B = 0.
B

F
B

FIGURE 7-9.
Pass transistor logic AND gate.

A pass gate weakness is apparent when the nMOS transistor passes a logic-1 from
node-A to node-F. Node-F suffers a drop in voltage VF = VDD − Vtn . An inverter placed
at the end of the pass transistor restores strong voltages.
Figure 7-10 shows a 3AND whose first stage transistor connects to the gate terminal of
a load transistor forming the function F = ABD. The voltage level at node-C is VDD − Vtn .
While the overall logic function is achieved the logic high voltage at the output node-F
drops by another threshold level. The weak logic-1 voltage at the output is F = VDD −2 Vtn .
Designers must take care in how signals are connected.
AND gates can have many pass transistors in series with each input tied to one of
the transistor gates. Figure 7-11 shows a 4AND logic gate design F = ABCD. The three
parallel transistors pull node F to ground when F = logic-0. Pass transistor logic appears
simple, especially when compared to static complementary CMOS designs. But there

A C

FIGURE 7-10.

Chaining pass transistor source output to gate input of load transistor.

204 CMOS Circuit Design Styles

B C D

B F F

FIGURE 7-11.
Pass transistor logic gate. F = ABCD.

are two weaknesses and both relate to propagation delay. The chain puts significant load
impedance on the signal path, degrading the high-frequency capability. The second weak-
ness also relates to speed in that the driving signals may not be strong rail voltages, but a
weakened logic voltage as in Figure 7-11. Despite these drawbacks, the node capacitances
of smaller pass transistors can allow speed properties to sometimes be competitive with
complementary CMOS logic. Pass transistor design is presented as a design option.

EXAMPLE 7-8
Design a 2OR gate using pass transistors where C = A + B. Include a pull-down network
to account for the floating output logic-0 state.
Two parallel transistors with signals A and B are applied to the transistor gates. VDD
is applied to the drain inputs of both transistors. The pull-down network uses two pass
transistors in series driven by A and B.
A

C
VDD

A
B

B
7.7 CMOS Transmission Gate Logic Design 205

EXAMPLE 7-9
Draw a pass transistor schematic for F = AB + CD. Include the circuitry that protects the
circuit from a floating node and a weak logic state.
A B

VDD C D F

C A

D B

Self-Exercise 7-13
If ABCD = 1.5 V and Vtn = 0.5 V, what is the voltage at node-F in Figure 7-10?
Answer: VF = 0.5. What does this mean?

Self-Exercise 7-14
Implement a pass transistor design for the XOR gate F = X Y + X Y . Don’t let nodes float.

Self-Exercise 7-15
Implement a pass transistor design for F = AX Y Z + W . Don’t let nodes float.

7.7. CMOS Transmission Gate Logic Design

CMOS transmission gates avoid the weak logic voltages of single-pass transistors by using
the two-transistor transmission gate. A typical CMOS transmission logic gate design is the
gate-level multiplexer (MUX) shown in Figure 7-12a for a 2-to-1 MUX. A MUX selects
one from a set of logic inputs to connect with the output. In Figure 7-12a, the logic signal
C selects either A or B to activate the output (out). Figure 7-12b shows a MUX design with
transmission gates. The complementary CMOS gates (Figure 7-12a) require 14 transistors
(4 transistors for each NAND and 2 transistors for the inverter), while the transmission
gate design requires only 6 transistors (4 transistors for T-gates and 2 for a C inverter).
206 CMOS Circuit Design Styles

C
A
A

C Out C Out

B
B

FIGURE 7-12.
(a) Standard 2-to-1 MUX design. (b) Transmission (pass) gate-based version.

Each transmission gate in Figure 7-12b has two transistors plus two more to invert the
control signal. The control signal polarities can be generated by a master circuit that feeds
these control signals to many subcircuits, thus lessening the transistor count.
Another pass gate design example is the XOR gate that produces a logic one output
when only one of the inputs is logic high. If both inputs are logic one or logic zero, then
the output is zero. Figure 7-13 shows an 8-transistor XOR gate having a tristate buffer and
transmission gate with their outputs connected. Both gates are controlled by the same input
through a complementary inverter (Input- A in this case). The XOR standard CMOS design
built from primitive logic gates requires 12 transistors, whereas the design of Figure 7-13
requires only 8.

A B Out
0 0 0
A Out 0 1 1
B 1 0 1
1 1 0

FIGURE 7-13.
Eight-transistor XOR gate and truth table.

7.8. Power and Activity Coefficient

Power dissipation is an issue for virtually all ICs. High-performance ICs with many tran-
sistors can generate 100–200 watts. Most of this power is wasted and has nothing to do with
actual computation. Some low power battery ICs generate microwatts and must operate for
a few years without replacement. The estimated power dissipation for the combinational
logic in this section assumes that all power loss is by the charge and discharge of a load
capacitance. This ignores the through current and leakage current power, but does allow
a look at the primary variables reducing circuit power. This section is intended to deepen
our knowledge and sensitivity to power loss properties. The power loss of an IC to charge
7.8 Power and Activity Coefficient 207

or discharge load capacitance is modeled as

1
PIC = αC L VDD
2
f clk (7-4)
2
where PIC is the power dissipated on the active edge of the clock when load capacitance is
charged or discharged, α is the average IC switching activity coefficient, C L is a lump sum
capacitance for all signal switching nodes in the IC, and f clk is the clock frequency. During
each clock pulse, only a fraction α of the combinational logic gates undergo a transition,
and the load capacitance is either charged or discharged but not both. α is typically on the
order of 5–30% for combinational logic gates in various ICs.
The power required to charge and discharge a logic gate capacitance in a clock network is

PIC = αC L VDD
2
f clk (7-5)

where α = 1 since the clock pulse is deterministic and happens with certainty on each
period. The 1/2 factor disappears for a clock circuit since charge and discharge are involved
in the same clock period. Some clock networks gate the clock for subcircuits that are not
activated during an operation. This allows de-powering of that subcircuit.
We will compute α at the gate level to compare the power efficiency of different logic
gates to better understand power reduction. Products may be high-performance high-power
or low-frequency low-power ICs, but all products must minimize power dissipation.
Assume that the major power dissipation occurs when the clock makes an active tran-
sition. The probability of an output signal transition from zero to one is α0→1 and is

α0→1 = p0 p1 = p0 (1 − p0 ) (7-6)

where p0 is the probability of an output logic-0, and p1 is the probability of an output

logic-1. The probability of an output signal transition from one to zero is α1→0 and is

α1→0 = p1 p0 = p0 p1 = p1 (1 − p1 ) (7-7)

so that

α1→0 = α0→1

If the input logic states are random, then we can determine p0 and p1 . Let N0 be the number
of possible logic-0 states in the output of a logic gate, N1 is the number of possible logic-1
states in the output of the same logic gate, and N is the number of input signals feeding
the logic circuit. The total number of input logic states is 2 N . Then
N0
p0 =
2N
N1
p1 = N
2
208 CMOS Circuit Design Styles

The transition activity coefficient is

N0 N1 N0 N1 N0 (2 N − N0 )
α0→1 = p0 p1 = = = (7-8)
2N 2N 22N 22N
where N0 + N1 = 2 N
We treat the inputs to combinational logic as random. A random input to an inverter
considers that two consecutive zeros or ones could occur that would not cause a logic
transition. If the inputs to an inverter are random then the probability of a 0→1 or a 1→0
transition is
11 11
αInv = α0→1 + α1→0 = p0 p1 + p1 p0 = + = 0.5
22 22
The inverter has a 0.5 probability of changing state for a random input that we also know
from intuition.

EXAMPLE 7-10

(a) Calculate the switching activity coefficient α0→1 for a 2NAND gate using a truth
table to identify the number of states.
(b) If the 2NAND gate is clocked at 1 GHZ, has a power supply of 1.5 V, and a load of
200 fF, what is the expected power dissipation of that gate for the 0 →1 transition?
(c) If an IC has one million such gates each with an activity coefficient of 20%, what is
the operating power of the IC due to the combinational logic gates?

A B C
0 0 1 A
0 1 1 C
B
1 0 1
1 1 0

(a) N0 = 1, N1 = 3, So
N0 N1 1 3
α0→1 = 2N
= 2·2 × 3 = = 0.1875
2 2 16
1 1 3
(b) P = α0−1 C L VDD
2
f clk = × 200 × 10−15 × 1.52 × 109 = 42.2 μW
2 2 16
(c) Each gate can transition 0 → 1 or 1 → 0. Therefore α = 2(0.1875) = 0.375, and
20% 0f the one million gates are switching.

PIC = 0.20 × 42.2 μW × 106 = 8.44 W

Notice how quickly power loss increases when dealing with millions or hundreds of millions
of gates and the moderating effect of a lower activity coefficient.
7.8 Power and Activity Coefficient 209

EXAMPLE 7-11
Let C L = 50 fF for each signal output node, VDD = 2.0 V, and f Clk = 1.5 GHz. Make a
truth table for the circuit and calculate
(a) The switching activity coefficient α0→1 for the circuit including the activity coeffi-
cients for all gate output nodes.

A
B
D
F
E
C

Hint: You must calculate and add the transition probabilities for each of the signal
nodes D, E, and F.
(b) Calculate the expected power dissipation for the 0 →1 transition.

(a)
A B C D E F
0 0 0 1 1 0
0 0 1 1 0 0
0 1 0 1 1 0
0 1 1 1 0 0
1 0 0 1 1 0
1 0 1 1 0 0
1 1 0 0 1 0
1 1 1 0 0 1

  
2 6 12
(α0→1 ) D = ( p0 p1 ) D = = = 0.1875
8 8 64
  
4 4 16
(α0→1 ) E = ( p0 p1 ) E = = = 0.25
8 8 64
  
7 1 7
(α0→1 ) F = ( p0 p1 ) F = = = 0.109
8 8 64
The sum of the α0→1 transition probabilities is

0.1875 + 0.25 + 0.109 = 0.5469

1
(b) PDEF = [0.1875 + 0.25 + 0.109] 50 fF (2)2 (1.5 GHz) = 82.0 μW
2
210 CMOS Circuit Design Styles

EXAMPLE 7-12
Given that F = A(B + C D) and VDD = 1.2 V, C L = 100 fF, and f Clk = 1.5 GHz:
(a) Draw the transistor schematic for a static CMOS gate.
(b) Compute the activity coefficients for both output transitions using a truth table.
(c) Calculate the expected power dissipated.

C D
A

B C

(a) The circuit is to the right.

(b) The truth table is

A B C D F = A(B + CD)
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
7.9 Summary 211

and
     
11 5 5 11
αTotal = αo→1 + α1→0 = p0 p1 + p1 p0 = + = 0.430
16 16 16 16

(c) The power is

1 1
P= α C L VDD
2
f clk = 0.430(100 × 10−15 ) (1.2)2 × (1.5 × 109 ) = 46.4 μW
2 2

Self-Exercise 7-16
Verify that the 2AND and 2NOR have the same activity coefficient α0→1 .

Self-Exercise 7-17
Make a truth table for the circuit and calculate the switching activity coefficient
(a) α0→1 for node-F
(b) α1→0 for node-F
(c) α0→1 for node-D
(d) α0→1 for node-E

A
B
D
F
E
C

Answers:
(a) α0→1 ) F = 0.234
(b) α1→0 ) F = 0.234
(c) α0→1 ) D = 0.1875
(d) α1→0 ) E = 0.25

7.9. Summary
This chapter showed how complex CMOS combinational logic gate designs are constructed
from Boolean algebra equations. More compact circuits with different power dissipation
and speed properties illustrate the popular dynamic logic, and pass transistor logic gate
designs. All versions appear in modern CMOS IC design. Lower power design theory was
illustrated by calculating activity coefficients and subsequent power dissipation.
212 CMOS Circuit Design Styles

Reference
[1] R. H. Krambeck, et al. “High Speed compact circuits with CMOS”, IEEE Journal of Solid State Circuits,
Vol. 17, No. 3, June 1982.

Exercises
Complex Combinational Logic Gates discuss whether the pull-up will be faster
than the pull-down network, or they will
7-1. Given the Boolean function F = Z [X Y Z +
they be the same.
X Z ] draw the static CMOS transistor sche-
matic in reduced form.
7-2. Write the Boolean expression F for the input
signals in the following circuit: A B C D E

B
7-6. Determine the logic function of the circuit
using a truth table.
A B C

A A

A F

A B B

C
B

C
7-3. Draw the static CMOS transistor schematic
that performs the Boolean function F =
(G + F)(M + N )
A B C F F
7-4. Draw the CMOS transistor schematic that ful-
fills the function F = (AB + C)D for a static 0 0 0
CMOS logic gate. 0 0 1
0 1 0
7-5. Given the schematic in the figure.
0 1 1
(a) If it corresponds to the CMOS pull-up net-
1 0 0
work of a static circuit, what is the resul-
1 0 1
tant Boolean expression F?
1 1 0
(b) If the p- and the n-channel transistors are
1 1 1
sized for individual equal drive currents
Exercises 213

7-7. Determine the Boolean function of the circuit. the square root of N1 is greater than or equal
A and B are input signals, and C is the output. to 1 and less than or equal to 2.
(a) Write the truth table.
(b) Draw a CMOS transistor schematic to
implement this function.

A B
A

B F

C C
The truth table shows (fill in)

A B C
A B C
0 0 0
0 0 0 0 1
0 1 0 1 0
1 0 0 1 1
1 1 1 0 0
1 0 1
1 1 0
Synthesis of DeMorgan Circuits 1 1 1
7-8. Use the DeMorgan equivalent circuit to imple-
ment the transistor circuit for F = X Y + Z Sizing Combinational Logic
without an output inverter. 7-14. F = AB + CD + E. Draw the transistor
7-9. Use the DeMorgan equivalent circuit to imple- schematic not using an inverter, and size the
ment F = X Y Z + X YZ without an output transistors with respect to current strengths
inverter. shown for the inverter.

7-10. Use the DeMorgan equivalent expression to VDD

draw the transistor schematic for a CMOS
combinational logic circuit for the function 4W
F = MNO + (P + Q)D.
7-11. Use the DeMorgan equivalent circuit to im-
3W
plement F = (X + Y )Z without an output
inverter.
7-12. Use the DeMorgan equivalent expression to
draw the transistor schematic for a CMOS 7-15. Consider the circuit and
combinational logic circuit for the function: (a) Provide the logic function that is imple-
F = (AB + C)(D + E) without using an in- mented by the circuit.
verter output stage. Hint: You can provide the truth table or
analyze the operation of each transistor.
7-13. A switching network has three inputs as (b) Size the transistors to have the same de-
shown. A and B and C represent the first and lay as a balanced CMOS inverter with
second and third bits of a binary number N1. W p = 3Wn .
The output of the circuit (F) is to be 1 only if
214 CMOS Circuit Design Styles

E
X Y

A B C D
T
Z
F
A W
F
B X
E
C
W T
D Y
Z

7-16. Given the function: F = (C + A)(B + AC) +

AC: 7-18. Size the transistors in the circuit with respect
(a) Reduce and express this function to its to a symmetrical inverter whose pMOS to
minimum Boolean statement. nMOS width-to-length ratio is 3.
(b) Draw the transistor schematic and size
the transistors for worst-case pull-up and B
pull-down with respect to the following
inverter.
A B C
VDD

3W A

F
W A

A B B
7-17. Size the transistors in the circuit with respect
to a symmetrical inverter whose pMOS width
is three times the nMOS width of Wn = 1 μm. C
Exercises 215

7-19. Size the transistors in the circuit with respect 7-21. (a) Draw the pull-up circuit schematic.
to a symmetrical inverter whose pMOS to (b) Label every transistor for minimum size
nMOS width is three times the nMOS width that matches the inverter pull-up and pull-
of Wn = 1 μm. down strengths. Use your new schematic
to label the width of all transistors.
VDD
X Y 4W Pull-up Net

Out
2W A

X Y
B

Out
F
C

X X E G
D
Y Y

Charge Sharing in Dynamic Circuits

7-20. Given a symmetrical inverter on the left. Size 7-22. The dynamic 3NAND gate is precharged and
the transistors in the circuit to the right for then the A and B n-transistors turn on. Vtn =
worst-case pull-up and pull-down that match 0.4 V. What is the final voltage?
the current drive of the inverter.
1.5 V

Clk
B C Vout

A 150 fF
D
A
F
6W
B B 25 fF
D
2W
C C 50 fF

A
216 CMOS Circuit Design Styles

7-23. If the capacitance that absorbs charge after 7-25. Given the dynamic circuit with Vtn = 0.6 V,
the switching occurs is small enough, then the when the input signals ABC go to 010 during
analysis changes. Vtn = 0.4 V. Calculate the the evaluation, what is the final voltage at the
final voltage Vfinal . node feeding the inverter?
1.5 V 2V

Vout
F
150 fF
500 fF
A Clk A B
Clk
B 25 fF C
60 fF

7-26. The dynamic circuit has a vector ABCDE =

10001 and Vtn = 0.5 V. What is the final volt-
age after charge sharing occurs? The drain ca-
7-24. The dynamic circuit has Vtn = 0.5 V. Node-C pacitance is 30 fF per transistor.
is constant at logic-0. What is VO during the
2V
evaluate phase of the circuit.
2V 2V

Nodes-AB 0 V 0V F
100 ns 200 ns 300 ns 400 ns 500 fF

30 fF 30 fF
A B

F
Clk
200 fF
30 fF 30 fF
C D
A

Clk 50 fF
B
E
C 50 fF 30 fF
Exercises 217

7-27. Repeat Problem 7.26 for the vector ABCDE 2V

= 11010.
Domino CMOS Logic M2
M3 M4
7-28. What Boolean function will the circuit per- 0V Vout
form?
M1

Clk 2V 2V

7-35. Determine the node voltages for the circuit

F where Vtn = 0.5 V.
3V 5V
D

X Y
C 3V
Z
3V

A B 1V F

7-36. Write in the voltages at the intermediate and

output nodes. Vtn = 0.5 V.
2V 2V

7-29. Draw the transistor schematic for a CMOS 2V

domino circuit that satisfies F = (X + Y )Z .
7-30. Draw the transistor schematic for a 2V
CMOS domino circuit that satisfies F =
(X + Y )(X + Y ).
2V 2V F
7-31. Draw a domino logic circuit for the function:
F = [(ABC) + (D E)]Z . Power and Activity Coefficient
7-32. Draw the transistor schematic for a CMOS 7-37. The probabilities of transitions are α0→1 =
domino circuitry that has a 2AND output gate 0.25 and α1→0 = 0.25. If VDD = 1.5 V, C L =
driven by a 2AND and a 2OR gate. The 2AND 10 nF, and clock frequency is 1 GHZ, what is
gate has A and B as input signals, and the the power dissipated?
2OR gate has signals C and D. The domino
7-38. Given VDD = 1.2 V and f clk = 500 MHz,
input gates are separate structures. What is the
calculate the activity coefficients and power
need for the inverters?
dissipation at node-D and node-F.
7-33. Draw the domino CMOS transistor schematic A
that fulfills the function F = (AB + C)D for
B
a domino CMOS logic gate. D
10 fF
F
Pass Transistor Logic
7-34. Given Vtn = 0.5 V, Vtp = −0.5 V, and γ = 0, E 10 fF
what is Vout ? A
218 CMOS Circuit Design Styles

A B C D E F A
B
100 fF E
G

F 200 fF
C
D
100 fF

7-42. Given F = (A + B)C, VDD = 2 V, and

f clk = 2 GHz, what is the expected power
dissipation if the inputs are random?
7-39. What is the probability pnt of no transition at
node-F in Problem 7.38. A
A
B D B F

C 500 fF
F

E 7-43. Calculate the probability of a logic-0 to logic-

C
1 transition and logic-1 to logic-0 transition
at node F. Use a truth table. If VDD = 1.2
7-40. Calculate the probability of a logic-0 to logic-1
V, f clk = 500 MHz. C D = 10 fF, and C F =
transition and logic-1 to logic-0 transition at
15 fF, what is the power dissipated at nodes-D
node-G. Use a truth table.
and -F?
A
A
B E D
B
G
F
C F
E
D C

7-41. Estimate the total power consumption at the

three capacitive nodes when VDD = 1.5 V and
f clk = 100 kHz.