8.Decimal-To-BCD Encoder - VHDL
8.Decimal-To-BCD Encoder - VHDL
Encoders 343
(16)
GND
(a) Pin diagram (b) Logic diagram
FIGURE 6–38 The 74HC147 decimal-to-BCD encoder (HPRI means highest value input
has priority.
Programmable Logic Device (PLD) The logic of the decimal-to-BCD encoder shown in
Figure 6–38 can be described in VHDL for implementation in a PLD. The data flow approach
is used in this case.
entity DecBCDencoder is
˛˝¸
port (D1, D2, D3, D4, D5, D6, D7, D8, D9:
Inputs and outputs declared
in bit; A0, A1, A2, A3: out bit);
end entity DecBCDencoder;
architecture LogicFunction of DecBCDencoder is
begin
A0 6= (D1 or D3 or D5 or D7 or D9);
˛˚˚˝˚˚¸
EXAMPLE 6–11
If LOW levels appear on pins, 1, 4, and 13 of the 74HC147 shown in Figure 6–38, indi-
cate the state of the four outputs. All other inputs are HIGH.
Solution
Pin 4 is the highest-order decimal digit input having a LOW level and represents deci-
mal 7. Therefore, the output levels indicate the BCD code for decimal 7 where A0 is the
LSB and A3 is the MSB. Output A0 is LOW, A1 is LOW, A2 is LOW, and A3 is HIGH.
Related Problem
What are the outputs of the 74HC147 if all its inputs are LOW? If all its inputs are HIGH?