Introduction to VHDL and the Program Life Cycle

All programming projects adhere to four basic phases of design. In this section the programming
life cycle will be discussed from the birth of a programming project to the maintenance of a
mature application.

Determine In the design of any digital logic design there are four basic phases.
WHAT
the system is to do.
1. Define what the system is to do.
2. Define how the system is going to accomplish this task.
3. Implement the digital logic system.
Determine 4. Maintaining the digital logic system.
HOW
the system is to do it. Phase 1 WHAT. Before any digital logic system can be developed, we must first
determine what the system is going to do. Unless all of the system requirements
are known, your design is doomed to failure. As development progresses, the
ability to insert a forgotten feature becomes less likely without major redesign.
IMPLEMENT Design considerations are based on what is known. To solve a design
the system. challenge, you must first understand it fully. In this phase, all of the system
requirements and features are identified. This also includes consideration for the
possibility of future expansion. In many cases, a missed requirement means the
failure of a project to reach completion on time. Often to implement a missed
MAINTATINING requirements means a complete system redesign down the road and lost dollars.
the system. Only after all of the system requirements have been addressed can you progress
to the next step.
Four Phases of the
program life cycle

Phase 2 HOW. The type and level of complexity will determine the approach taken in the design
of the digital logic system. In this phase of design, the developer is to determine how the digital
logic system is to accomplish its task. The system may be developed from a low level hardware
approach, a structure approach where individual pieces are developed and connected together
as in a schematic, or if a behavior approach is taken where the digital logic system is defined by
how the system behaves over time. Cost and labor are to be minimized in the creation of any
digital logic system.

Along with knowing how the system is to perform its task, the design needs to know how it is to
be installed. Often, a new system replaces an existing one. In a critical application, you may
have to design into the system, a method of conversion to the new system.

Phase 3 IMPLEMENT. The third phase of development is the implementation phase. In this
phase of design, the requirements have been defined and the method of accomplishing the task
has been determined. The system is ready to be built. As you progress further through the four
phases of design, it becomes more and more costly to implement missed features or to add new
functionality. The system is now installed and tested.

Testing involves three stages, the unit test, the system test, and the acceptance test. First the
digital logic system is tested as an individual unit. Once the digital system has been fully tested
and meets design requirements, the unit is tested in the system environment. Here, the
interaction of the digital logic unit is evaluated by how it performs in the target system
environment as it undergoes exhaustive testing. It is essential that problems are detected and
corrected before acceptance testing. After the system tests have been performed and the results

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documented, it is time for the acceptance test. Acceptance testing concentrates on the overall
operation of the completed system. Does the system as a whole meet the stated requirements.

In the case of a brand new system, implementation is easy. If the new system is replacing an
existing system, you must decide how to convert the old system to the new one. It may be
required that the new system is phased where the new system gradually takes over the tasks of
the existing system. In other cases, the new system is run in parallel with the existing system.

Phase 4 MAINTAIN. In the fourth phase is the maintenance phase. After the system has been
installed, maintenance must be performed during the life of the system. As the system grows and
matures, modifications may be required to ensure that the system meets its requirements. As the
system reaches the point where age or technology has past it by, the cycle starts again.

Introduction to VHDL

VHDL is a programming language for simulation and/or synthesis (design) of digital circuits.
This section provides an introduction to VHDL and the use of a high-level language to describe
and implement digital logic circuits. High-level programming will be used to describe simple logic
gates from a VHDL programmer’s point of view. More complex digital circuits can then be
described in terms of a series of basic logic gates. Using VHDL, the functional description of
combinational logic can be implemented through this high-level description language. A
Complex logic design is converted from this high-level program code to a file that may be
programmed on to a wide variety of logic devices.

In this tutorial, several basic logic gates are introduced. Using basic logic descriptions and
demonstration, the logic of each gate was described followed by an application. In this section,
the process will be described allowing you to represent these gates using VHDL.

After completing this section, you should be able to:

Represent the Inverter, the AND gate, the OR gate, the NAND gate, the NOR gate, the
Exclusive-OR gate, and the Exclusive-NOR Gate in standard VHDL convention.
Implement simple digital functions utilizing VHDL.

VHDL is an acronym often misquoted. As part of a DoD program, the acronym VHDL is an
acronym that contains another acronym. In the early 1980’s, the DoD sponsored the VHSIC
(Very High-Speed Integrated Circuit) program. Because of new semiconductor manufacturing
processes, digital systems could be designed with such great complexity that description and
documentation became unmanageable. A method was needed that would allow for a standard
representation of these digital systems to cope with modern designs utilizing complexities of ever
increasing orders of magnitude. VHSIC in its entirety became the ‘V’ in VHDL which stands for
(VHSIC Hardware Description Language).

First, we will examine and define some basic elements of VHDL and then learn how to apply
them to basic logic gates.

VHDL Design Units

Design units are segments of VHDL code that can be compiled separately and stored in a
common location called a library. There are two required design units in VHDL. These are
entities and architectures, as shown in Figure V-1. Entities and architectures are the only two
units that must be included in any VHDL design description.

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 VHDL Design Units

Entities Architectures

FIGURE V-1 The design units shown in blue are introduced in this section.

Entities The entity describes all of the inputs and outputs to be used in the device model.
Every VHDL design must include at least one entity declaration. The entity is where the interface
to the physical device, such as a gate, that we wish to program is described. It makes sense that
if we wish to describe the behavior of a logic gate, you first need to describe how to get the
signals into and out of the device model. User defined names or identifiers are created to
represent the input and output. Identifiers are names given to signal ports, variables, and used in
other instances where the programmer needs to uniquely identify an object in code. Once
defined, these identifiers may be used to describe the desired behavior of the device model. The
structure and syntax of the VHDL entity section is as follows with the identifiers shown within the
< > and the VHDL keywords are in boldface.

entity <user defined name> is

port (port assignments)
end <user defined name>;

The entity section begins with the keyword entity followed by a user defined identifier for the
entity and the keyword is. Next is the port statement which includes the definitions of the ports,
followed by the keyword end and the user defined name or identifier. The keyword end indicates
the end of the entity section.

A port is how the entity interfaces device input and output signals. The VHDL keyword port is
used to declare the input and output signal assignments. Ports are specified by direction and
identifier. Port directions are specified as in for inputs, out for outputs, and inout for bidirectional
ports.

VHDL supports two different types of identifiers, basic identifiers and extended identifiers.
There are some rules and guidelines for the creation of VHDL basic identifiers.

1. VHDL basic identifiers can consist of a combination of lowercase(a…z), uppercase(A..Z),

numeric digits(0…9), and the underscore.
2. Basic identifiers must not use numeric digits(0…9) or an underscore “_” as the first
symbol in an identifier name.
3. Basic Identifiers must not contain spaces.
4. Basic Identifiers must not use double underscores “_ _” as part of the identifier name.
5. VHDL basic identifiers are “case insensitive”. For example, Input, INput, input, and
INPUT would be seen as four different identifiers.
6. Keywords and identifiers reserved for VHDL may not be used as identifiers.
7. When creating names for things in VHDL, make them meaningful. Try to use names that
remind you what it is that is being represented. For example, you would not name an
input signal “Ouput1” or “George”. Unmeaningful or nonsensical naming make code hard
to read and very difficult to troubleshoot.

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Extended identifiers are placed between two back slashes and allow the use of characters such
as *, !, and # . VHDL extended identifiers are “case sensitive”. For example, /In*put/, /In*put/,
/in*put/, and /IN*PUT/ would be seen as four different and distinct identifiers. In this section only
basic identifiers will be used.

Architectures The architecture section is where the behavior of the digital design model is
specified. Now that the input and output ports have been defined by the entity, you must tell the
system what the output of the modeled device is going to be. First, you need to look at the
structure of the architecture and determine how it will relate to the entity port definitions. Each
architecture section must be associated by name with an entity. The structure and syntax of the
architecture section is as follows. Comment lines are preceded by - - and are not part of the
VHDL code. The VHDL code describing behavior is specifically covered

architecture <architecture name> of <entity name> is

begin
- - VHDL code describing behavior (logic function) goes here
end <architecture name>;

The architecture section begins with the keyword architecture followed by a user defined
identifier for the architecture and the keyword of followed by the entity name and the keyword is.
Next is VHDL keyword begin, followed by the functional or behavioral description of the logic
circuit. Next is the keyword end and the user defined name or identifier. The keyword end
indicates the end of the architectural declaration.

Example - VHDL Modeling of the INVERTER

The basic function of an inverter is described is to invert an input from ‘1’ to ‘0’ or ‘0’ to ‘1’. We will
now see how the inverter in Figure V-2 can be represented in VHDL.

Input1 Output1
Output1 <= not Input1;
Logical not operator ‘not’
FIGURE V-2 Schematic Inverter represented in VHDL

Inverter Source Code The following VHDL code describes the simple inverter. Let’s examine
this simple VHDL code sample and analyze the program code structure. For the purpose of
clarity, VHDL keywords are boldface. As in all programming languages, VHDL has a method for
inserting comments for the purpose of code description and clarification. VHDL comments follow
double dashes “- -“. Comments may be placed anywhere explanation or clarification is needed.
Everything after the double dashes is considered part of the comment and will continue until the
end the line is reached. The comments have no effect on the VHDL code and are strictly for
descriptive purposes.

-- The inverter
-- Inverts a high or low signal
-- The following is the declaration section
library IEEE;
use IEEE.std_logic_1164.all

-- The following is the entity section

entity Inverter1 is
port( Input1: in std_logic; Output1: out std_logic); -- Port identifiers

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 end Inverter;
-- The following is the architecture section.
architecture BehaviorInverter of Inverter1 is
begin
Output1 <= not Input1;
end BehaviorInverter;

NOTE: In VHDL, the ‘<=’ symbol is used as a port assignment statement.

In the case of the inverter, there must exist signal port assignments allowing signals to get in and
the corresponding resulting signal to get out. A port is how the entity interfaces the device input
and output signals. As you know, the VHDL keyword port is used to declare the input and output
signal assignments. In the inverter, the identifier “input1” is programmer defined and is assigned
as type in making this as an input only signal port. In the same statement, the identifier “output1”
is assigned as type out making this as an output only port.

Notice that there are three basic sections to this simple example. These sections are the library
declaration, the entity, and the architecture section. We will start at the top by first describing the
declaration section.

In the declaration section, libraries of predefined functions can be listed and made available for
use in the VHDL program. Functions are program tool sets that perform predefined tasks. In the
VHDL inverter example, the keyword library is used to tell the program that a specified library
has been declared available for use. Different libraries contain different program tools and may
be created by the VHDL programmer or supplied as predefined libraries. In this example, the
standard library named IEEE is made available to the inverter program. The IEEE library is a
standard library used in VHDL that contains a standardized tool set called std_logic_1164 . The
tool set std_logic_1164 is made available by most vendors of VHDL programming applications
and contains a wealth of standardized tools and functions such as the std_logic, and, and the
not command. Using standard libraries is a way to make your program code compatible with
other IC devices. Using standard library functions will allow you to implement your code with sets
of common functions familiar to other VHDL developers. The use of libraries also prevents the
need to rewrite code every time you need to use a common function. The keyword use tells the
VHDL program what functions are be used from the library. In this case, from the IEEE library,
standard logic (std_logic_1164) is selected. From std_logic_1164, all of the functions are to be
made available by the keyword all. Later, it will be shown that your can limit access to specific
functions of your choice from a declared library.

Notice that in the inverter example, the entity is given the identifier name “Inverter1”. Once the
entity has been defined, it may be used as a template for reference in the construction of the
architecture. Having defined one entity, multiple architectures based on this single entity may be
created. In order to complete our VHDL inverter we must have given the architecture section its
own unique identifier name. The architecture identifier is related to the entity identifier.

The Behavior or Function Code The code used to define the actual behavior of a logic circuit
is placed between the VHDL keywords begin and end. Table V-1 and V-3 shows a list of VHDL
assignment and logical operators

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A breakdown of the code used to describe the behavior of the inverter is as follows.
User defined
identifiers

Output1 <= not Input1;

Assignment Logical not operator

Operator

Values are assigned to an output port based on the input signal.

Assignment Operators
Assignment Operators Table V-1 lists and describes the two VHDL assignment operators
used in the text.

Assignment Description Syntax Example and

Operator Comments
Used as a variable assignment TEMP := 23;
operator -- The value 23 is assigned to
:= -- the variable TEMP.

OUT1 <= ‘1’;

Used as the assignment operator -- Assigns a logical 1 to the signal
when assigning a value to a signal port OUT1.
port. Do not confuse it with the
<= OUT1 <= InputA and InputB;
“less than or equal” operator used
in Boolean equations. -- The result of AB is assigned to
-- the variable OUT1.

TABLE V-1

We will now see how the AND gate in Figure V-3(a) and the OR gate in part (b) can be
represented as standard VHDL code listings.

Input1 Input1
Output1 Output1
Input2 Input2
(a) (b)

FIGURE V-3 AND gate and OR gate

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Relational Operators
A relational operator is used to compare the value of one identifier to the value of another. A
relational comparison is a Boolean operation that returns a value of 1or 0. The result of a
relational evaluation is also used to control conditional and loop structures. Table V-2 describes
the VHDL relational operators.

Each of the relational operators returns a Boolean 1 or 0. In the following example, the
assignment operator ‘=’ is used to determine of one value is equivalent to another.

( A = B) -- Returns the value 1 if A is equivalent to B

The ‘/=’ operator is the not equal operator. This operator returns the value 1 if one value is not
equivalent to another.

( A /= B) -- Returns the value 1 if A is not equivalent to B

Less than comparisons are performed using the ‘<’ operator. This operator returns 1 if the
operand of the left is less than the operand on the right.

( A < B) -- Returns the value 1 if A is less than B

The less equal to operator ‘<=’. This operator returns 1 if the operand of the left is less than or
equal the operand on the right.

( A <= B) -- Returns the value 1 if A is less than B

Greater than comparisons are performed using the ‘>’ operator. This operator returns 1 if the
operand of the left is greater than the operand on the right.

( A > B) -- Returns the value 1 if A is greater than B

The greater equal to operator ‘>=’. This operator returns 1 if the operand of the left is greater
than or equal the operand on the right.

( A >= B) -- Returns the value 1 if A is greater than B

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Relational Description Syntax Example and Comments
Operator
Equality operator variable v1: integer := 5;
returning a Boolean 1 if variable v2: integer := 5;
two values are variable v3: integer := 8;
= equivalent otherwise 0.
Result = (v1 = v2) -Has the value 1 equivalent.
Result = (v1 = v3) -Has the value 0 not equivalent.

Inequality operator variable v1: integer := 5;

returning a Boolean 1 if variable v2: integer := 5;
two values are not variable v3: integer := 8;
equivalent otherwise 0.
/= Result = (v1 /= v2) -Has the value 0 not equivalent.
Result = (v1 /= v3) -Has the value 1 not.

Less than operator variable v1: integer := 3;

returning a Boolean 1 if variable v2: integer := 5;
the left hand operand is variable v3: integer := 1;
less than the right hand
< operand otherwise 0. Result = (v1 < v2) -Has the value 1, v1 is less than v2.
Result = (v2 < v3) -Has the value 0, v2 not less than v3.

Less or equal than variable v1: integer := 3;

operator returning a variable v2: integer := 3;
Boolean 1 if the left variable v3: integer := 1;
hand operand is less
<= than or equal to the Result = (v1 <= v2) -Has the value 1, v1 is less or equal to v2.
right hand operand Result = (v2 <= v3) -Has the value 0, v2 not less or equal to v3.
otherwise 0.

Greater than operator variable v1: integer := 8;

returning a Boolean 1 if variable v2: integer := 5;
the left hand operand is variable v3: integer := 1;
greater than the right
> hand operand Result = (v1 > v2) -Has the value 1, v1is greater than v2.
otherwise 0. Result = (v2 > v3) -Has the value 0, v2 not greater than v3.

Greater or equal than variable v1: integer := 3;

operator returning a variable v2: integer := 3;
Boolean 1 if the left variable v3: integer := 6;
hand operand is greater
>= than or equal to the Result = (v1 >= v2) -Has the value 1, v1 is greater or equal to v2.
right hand operand Result = (v2 >= v3) -Has the value 0, v2 not greater or equal to v3.
otherwise 0.

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Logical Operators
The AND gate and OR gate will be modeled using VHDL using Table V-3, which is a list of
logical operators that perform the basic Boolean operations. A logical operator evaluates two or
more Boolean variables. Boolean variables have two possible values 0 or 1. Note that the
inverter could have also been represented in VHDL code using the logical operator NOT.

Logic operators are also used to connect Boolean expressions. For example, we may wish to
test to see of the identifier X is greater than 0 and less than 10. The logical operator allows more
complex Boolean expressions to be built from simpler ones.

A simple application of the logical operator and is demonstrated in the example expression
shown.

BoolOne := ( A > 0 ) and ( A <= 10 );

A more complex application of the logical operator is demonstrated in the example next
expression.

BoolOne := not ((( A > 0 ) and ( A <= 10 )) nor ( C /= 3));

Logical Operator Description Syntax Example and Comments

Returns 1 only when all input OUT := InputA and InputB;

and signals are 1. -- The result of AB is assigned to
-- the variable OUT.
OUT := InputA nand InputB;
Returns 1 when any input
-- The result of AB is assigned to
nand signals are 0.
-- the variable OUT.

Returns 1 when one or the OUT := InputA xor InputB;

other input signals is 1 but -- The result of A xor B is assigned to
xor
not both. -- the variable OUT.

OUT := InputA or InputB;

Returns 1 when any input
-- The result of A+B is assigned to
or signal is 1.
-- the variable OUT.

OUT := not InputA;

Returns 1 if signal is 0, and
-- Assigned the complement of
not 0 if the signal is 1.
-- InputA to the variable OUT.

Table V-3 VHDL Logical Operators

AND Gate Refer to Table V-3 the truth table for a 2-input AND Gate. Recall that two inputs are
required and a single output port. In the following VHDL program, the two input ports are defined
as ‘A’ and ‘B’ and are assigned as type “in”, marking them input only signal ports. The output
port is defined as ‘X’ and is assigned type “out” marking this an output only signal port. It should
be clear that in the entity section, the user may define as many ports as required for the particular
digital design limited only by the physical IC device.

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 -- The AND Gate
-- Output is high when input signals
-- A and B are high else the output is low.
library IEEE;
use IEEE.std_logic_1164.all

entity AND1 is
port( A, B: in std_logic; X: out std_logic);
end AND1;

Now that the device interface to the outside world has been defined and named in the entity, the
architecture section of the AND gate can be specified. The code segment for the architecture is
listed below. This architecture is based on the entity “AND1”. You must provide a unique name
for the architecture and indicate which entity you are referencing. Refer to Table V-2 for a partial
list of logical operators. You want to find a logical operator that will allow you to define the
operation of an AND gate in simplest terms. Notice that we have the keyword AND which may be
used to relate behavior of the output ‘X’ to the input signals from ports ‘A’ and ‘B’.

architecture BehaviorAND1 of AND1 is

begin
X <= A and B;
end BehaviorAND1;

OR Gate The VHDL listing for a 2-input OR gate is as follows.

-- The OR Gate
-- Output is high when input signals
-- A or B or both are high else the output is low.
library IEEE;
use IEEE.std_logic_1164.all

entity OR1 is
port( A, B: in std_logic; X: out std_logic);
end OR1;

architecture BehaviorOR1 of OR1 is

begin
X <= A or B;
end BehaviorOR1;

You can also describe NAND, NOR, XOR, and XNOR gates using VHDL code in a similar way as
you have learned for the inverter, AND, and OR gates.

Data Types
The idea of a data type is important to the design of any high level language application. When
writing a VHDL program, names of variable identifiers, ports, and other entities will have to be
defined. These names or identifiers will have to be given a data type to tell the program what kind
of data that the identifier accepts. In the development of digital logic circuits, the inputs and
outputs as well as internal identifiers are defined by data types.

When you define a variable in VHDL, you can assign an initial value to use as a constant or
default value. For some types of identifier data types, the range of values that may be assigned
is determined by the system on which it is implemented. For example, counting numbers start at
0 and continue through infinity. Because electronic devices are not infinite in size, the
representation of a number set must be limited to fit one the target device. You should limit your
data values to only those values that will physically fit on the target IC device.

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A range assigned to a data type can be used to limit the data that can be assigned to a particular
identifier and determine to set of values that can be assigned to it. In some cases, the range of
values needs to be constrained or limited to a certain set of values. For example, a set of
counting numbers may be constrained to the values 0 through 7. Numbers outside of this range
would not be accepted as valid input. This is important because you do not want to send a value
to an output port that contains more bits that you have physical pins defined on the target device
to represent it. For example, the number seven is represented using three bits. The assignment
of the number 8 may require hardware modifications.

The VHDL programming language supports a rich assortment of data types that may be applied
to program identifiers. To understand how to select the appropriate data type, you must first
understand how each of the data types works. The Table V-4 showsa list of data types supported
by VHDL.

Data Type Description Syntax Example and Comments

An identifier of data type bit variable MyBit: bit;

bit has two possible values, 0 -- Declare a variable of type
and 1. -- bit.
An identifier that is part of variable MyStdBit: std_logic;
the IEEE.std_logic_1164 -- Declare a variable of type
std_logic
standard with nine possible -- std_logic. Added features over bit
values, U,X,0,1,Z,W,L,H,-. -- data type allows added functionality.
An identifier of data type variable MyBitVector: bit_vector;
bit_vector identifies a set of -- Declares a variable
bit_vector
indexed items with the -- of type bit_vector
same name.
An identifier that is part of variable MyStdVector:std_logic_vector(0 to
the IEEE.std_logic_1164 3);
standard. Identifies a set -- Declare a variable of type std_logic_vector
std_logic_vector of indexed items with the -- Added features over bit_vector data type
same name with nine -- allows added functionality.
possible values
U,X,0,1,Z,W,L,H,-
An identifier of data type variable MyInt: integer;
integer can contain positive -- Declares a variable of
integer
and negative whole -- type integer.
numbers.
Natural is a subtype of variable MyNatural: natural;
integer. An identifier of -- Declares a variable of
data type natural can -- type natural
natural
contain positive and
negative whole numbers
starting at 0.
Positive is a subtype of variable MyPositive: positive;
integer. An identifier of -- Declares a variable of
data type natural can -- type positive
positive
contain positive and
negative whole numbers
starting at 1.
An identifier of data type variable MyBool: boolean;
boolean Boolean has two possible -- Declares a variable of
values, true and false. -- type integer.
Table V-4 VHDL Data Types

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bit vs. std_logic
The bit and bit_vector data types accept the assignment of a true or false similar to a wire
passing a single high or low. The bit_vector data type allows the declaration of a series or an
array or bits identified with a single identifier name using an index to select individual members of
the bit_vector.

The bit datatype is limited to two possible values.

1. '0': logic 0 or LOW

2. '1': logic 1 or HIGH

The std_logic datatype is part of the IEEE.std_logic_1164 standard and contains added features
over the bit and bit_vector data types. The .std_logic_1164 standard supports nine possible
assignments to a std_logic signal or variable. These include the traditional logic 0 and logic 1, but
also includes eight other data conditions useful in design and simulation. The following lists
possible std_logic assignments and their definitions.

1. '0': logic 0 or LOW

2. '1': logic 1 or HIGH
3. 'X': unknown. Impossible to determine this value/result.
4. 'U': uninitialized. This signal hasn't been set yet.
5. 'Z': High Impedance
6. 'W': Weak signal, can't tell if it should be 0 or 1.
7. 'L': Weak signal that should probably go to 0
8. 'H': Weak signal that should probably go to 1
9. '-': Don't care.

-- Compliable program demonstrating assignments to bit and std_logic port identifiers.

library ieee;
use ieee.std_logic_1164.all;

entity StdLogicVSBit is
port(A,B,C,D,E,F: out std_logic;
X,Y: out bit );
end entity StdLogicVSBit;

architecture StdBitExample of StdLogicVSBit is

begin
-- Example of assignments to the std_logic datatype
A <= '0'; -- Logic 0
B <= '1'; -- Logic 1
C <= 'X'; -- Unknown
D <= 'U'; -- Uninitialized
E <= '-'; -- Don't Care
-- Assignments to traditional Bit datatype
X <= '0'; --Bit limited to 1 or 0
Y <= '1';
end architecture StdBitExample;

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Arithmetic Operators
Arithmetic operators perform program addition, subtraction, multiplication, and division
operations. These operators manipulate and modify numeric values as defined by their arithmetic
functionality. Table V-5 shows the arithmetic operators used by VHDL.

Operator Description Syntax Example and Comments

variable v1: integer := 5
Addition operator adds the two variable v2: integer := 3
+ values together.
v1 + v2 --Has the value 8.
variable v1: integer := 5
Subtraction operator subtracts the
variable v2: integer := 3
- value on the right side from the
value on the.
v1 - v2 --Has the value 2.
variable v1: integer := 5
Multiplication operator multiplies variable v2: integer := 3
* two values together.
v1 * v2 --Has the value 15.
variable v1: integer := 5
variable v2: integer := 3
Division operator divides the value
/ on the left by the value on the right. v1 / v2 --Has the value 1. 3 goes into
--five 1 time. See mod or rem
--to get the remainder.
variable v1: integer := -5
variable v2: integer := 3

Modulus operator returns the v1 mod v2 -- Has the value positive 2

integer result from an integer -- because three goes into
Mod division keeping the sign of the right -- 5 one time with 2 as the.
hand operand. -- remainder. The mod
-- operator retains the sign of
-- if the right hand operand.

variable v1: integer := 5

variable v2: integer := -3

Remainder operator returns the v1 rem v2 -- Has the value positive 2

rem remainder portion of an integer -- because three goes into
division keeping the sign of the left -- 5 one time with 2 as the.
hand operand. -- remainder. The rem
-- operator retains the sign of
-- if the left hand operand.

Table V-5 VHDL Arithmetic Operators

Each arithmetic operator return a value based on the selected arithmetic operators function. In
the following addition example, the addition operator ‘+’ assigns the result of an addition
operation to the variable Total.

X := 4 + 5; -- The addition operator returns the value 9

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In the subtraction example, the subtraction operator subtracts the right hand value from the left
and assigns the result to an identifier.

X := 4 – 2: --The subtraction operator returns the value 2

The multiplication operator returns the result of two values multiplied together as follows in the
next example.

X := 5 * 3; --The multiplication operator returns the value 15

The division operator returns the result of a division operation. The value on the left is divided
by the value on the right and assigned to an identifier.

X := 6 / 2; -- The division operator returns the value 3

The mod and rem operators work in a similar manner. The modulus operator mod returns the
integer result form an integer division keeping the sign of the right most operand. In an integer
result, what would be the decimal remainder is discarded. In this example the number three goes
into -7 twice and the sign of the right value is keep, therefore the answer positive 2.

X := -7 mod 3; -- The mod operator returns the value +2;

The rem operator works as the mod operator except that the sign of the left most operand is
retained. In this example the number three goes into -7 twice and the sign of the left value is
keep, therefore the answer negative 2.

X := -7 rem 3; -- The rem operator returns the value -2;

Arithmetic operators can be used in simple to complex mathematic applications. Parenthesis can
be applied to complex mathematical expressions to be brake them up into smaller pieces as
shown in the following example. The simplification of expression using parenthesis allows for
better readability, trouble shooting, and maintenance of your VHDL program.

X := (( A * B ) + (C mod D)) / 2;

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 The if statement
In this section, the topic of decisions will be covered. In complex digital logic systems, there
needs to be a method for making choices based on input conditions. The evaluation of a Boolean
expression determines if a VHDL program will execute statements within the if statement block.

The basic syntax for a simple if statement is:

If <Boolean Expression> then

<VHDL statements>
end if;

The VHDL keyword if is followed by a conditional statement in the form of a Boolean expression
that results in a true or false response. The keyword then follows the conditional Boolean
expression. A Boolean true will cause the VHDL program to act on the statements within the if
statement code block. Closing out the if statement code block are the keywords end if. The use
of indentation helps to make your programs readable.

In the VHDL code example, a simple if statement is used to increment a variable v1 if the input A
is equivalent to B. In the design of VHDL code, it is good code practice to select a data type that
best represents the range of values that are to be accepted in the digital logic system. In this
example, three output pins have been defined to return the binary representation of an integer
whose range is 0 to n. Because the designer wants to limit the hardware to three output pins, the
integer data type needs to be given a range from 0 to 7 which corresponds or binary 000 2 to
1112. The data type natural was selected because only positive integer values from 0 to 7 are
valid as defined in table V-4. The use of indentation makes your program more readable.

entity if1 is
port( A, B: on bit; X: out natural range 0 to 7);
end if1; The holding variable v1 has
been defined to the same
architecture BehaviorIf1 of if1 is constraints of the output port.
begin In this way, the variable has
process(A, B) been constrained to only those
variable v1: natural range 0 to 7; values that are valid for the
begin output identifier X.
Use of v1 := 6;
indentations if ( A = B ) then If A and B are
makes code v1 := v1 + 1; equivalent, then
more readable end if; the variable v1 is
X <= v1; incremented by 1.
end process;
end BehaviorIf1;

The else statement

The keyword else is used to provide an alternate path for an if statement. In the event that the
conditional Boolean expression evaluates to false, the VHDL statements following the else
statement are acted upon. The previous code example has been modified to provide an alternate
set of VHDL statements to act upon in the event that the conditional Boolean expression
evaluates False.

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 entity if1 is
port( A, B: on bit; X: out natural range 0 to 7);
end if1;

architecture BehaviorIf1 of if1 is

begin
process(A, B)
variable v1: natural range 0 to 7;
begin
v1 := 6; The else statement
if ( A = B ) then provides an
v1 := v1 + 1; alternate path for the
else if statement when
v1 := 0; the conditional
end if; Boolean expression
X <= v1; evaluates to false.
end process;
end BehaviorIf1;

The elsif statement

System requirements often require that multiple alternatives must be defined based on an input
condition. To satisfy this need in a VHDL program, the keyword elsif (else if), is used. The
process of implementing multiple paths in an if statement block using the elsif command is called
nesting. Often we desire the ability to make multiple selections based on different inputs.

Using nested if statements, define a simple selector that reads a three bit binary value and
selects one of seven output pins

Solution To build our selector, we must first define an input port identifier A that describes the
three input bits. Next, we need to define an output port identifier X that defines a set of 7 bits.
Reading the value from A from 0 to 7, select an output bit from bit 0 to bit 6. The if statement
block should use the optional else statement used to account for any inputs not addressed in the
if or elsif code blocks.

NOTE: The if and nested if blocks do not require that the programmer account for all possible
inputs conditions, therefore it is the responsibility of the programmer to insure that any
unaccounted for conditions are addressed. The following VHDL program demonstrates a simple
selector application.

entity sel1 is
port( A: in bit_vector(0 to 2); X: out bit_vector(0 to 6));
end sel1;

architecture BehaviorSel1 of sel1 is

begin
process(A) In VHDL, you can specify a
begin desired binary bit pattern
if ( A = "001") then enclosed in double quotes. In
X <= "0000001"; this example, the input pattern
elsif ( A = "010") then is matched against the input
X <= "0000010"; variable A and the output X is
elsif ( A = "011") then defined by a binary bit pattern
X <= "0000100";
elsif ( A = "100") then

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 X <= "0001000";
elsif ( A = "101") then
X <= "0010000";
elsif ( A = "110") then
X <= "0100000";
elsif ( A = "111") then The optional trailing else is
X <= "1000000"; used to catch any pattern
else not specified in the nested
X <= "0000000"; if statements.
end if;
end process;
end BehaviorSel1;

The case statement

The VHDL case statement is similar to the nested if statement. Different sets of VHDL
statements are acted upon based on the evaluation of an expression. Unlike the if statement, the
case statement must account for all possible values that may be applied to the case block. The
VHDL keyword “others” is used to specify a response for any inputs not accounted for. If all
inputs are specified, the keyword others is not required. It is good coding practice to always
include the others keyword to account for unexpected or illegal inputs, even if the system appears
to account for all of them and it does not seem possible.

The basic syntax for the case statement is:

case <switch expression> is Multiple when clauses are used

when => <VHDL statements>; to ensure that all possible
when => <VHDL statements>; values. The when others

 clause provides alternate path
 for any cases not covered with a
when => <VHDL statements>; previous when clause.
when others => <VHDL statements>;
end if;

Implement a selector using the case selection statement.

Solution In the case selection implementation, there is no comparison of the input identifier to a
value, the path selection is determined by the input value itself based on the when clause.

NOTE: If all possible cases have been accounted for in a case selection, you do not necessarily
need to include the when others clause. It is generally good coding practice to include the
others clause anyway to handle unexpected inputs.

entity case1 b
port( A: in bit_vector(0 to 2); X: out bit_vector(0 to 6));
end case1;

architecture BehaviorCase1 of case1 is

begin
process(A)
begin
case A is

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 when "001" => X <= "0000001";
when "010" => X <= "0000010"; Multiple when account for
when "011" => X <= "0000100"; possible selector values. The
when "100" => X <= "0001000"; optional when others clause
when "101" => X <= "0010000"; provides an alternate path for
when "110" => X <= "0100000"; any unexpected signals.
when "111" => X <= "1000000";
when others => X <= "0000000";
end case;
end process;
end BehaviorCase1;

The following waveform simulation is generated from inputs variable A values 0 through 7. The
use of a simulation proves the functionality of the VHDL selector using the case statement. The
functionality of the two selector examples provide the exact output waveform.

The loop statements and Sequential Programming

A loop is a statement that repeatedly executes a set of statements
contained within the loop structure. In this section, the for loop and while
loop will be discussed.

Two loops will be covered in this section, the VHDL for loop and the VHDL while loop. Loops
allow you to repeat a section of VHDL statements within a VHDL program.

For loop
The VHDL for loop is used when the programmer knows where the loop is going to start
and when the looping is going to end before entering the loop. For example the loop may start at
the value zero and stop at the tenth iteration. A fixed number of iterations has been determined
and the for loop runs a sequence of statements for the specified number of iterations.

The four stages of the for loop. These are:

1. The Entry Point. The point in which the loop has been entered.
2. The Iteration. The iteration refers to a pass through the body of the loop structure.
3. The Terminal Test. The test of the exit condition to determine when to stop the loop.
4. The Exit Point. The point in which the loop structure is exited

The for loop syntax is Starting value Stopping

User assigned to value of User
Defined User Defined Defined
Identifier Identifier Identifier
for identifier in starting value to stopping value loop

VHDL Statements

end loop;

The VHDL keyword for is followed by a user defined identifier used as an iteration index. The
keyword in precedes the start value for the loop. The keyword to precedes the stopping value of
the for loop. In the case of the for loop, the keyword to is used when the loop is to start at a value

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lower than the terminal value. The keyword downto can be used when the for loop is to start at a
number higher than the terminal value and the loop is to count down to terminal value. The start
and stop values defined in the loop are the starting value assigned to the user defined identifier
and the value of the user defined identifier when the loop is to stop. The keyword loop completes
the for loop declaration. After the keyword loop are the sequential statements that are to be
acted upon by the for loop structure.

EXAMPLE For Loop Example

Write a VHDL program that reads a set of 7 input bits, then counts the number of bits that were
set to ‘1’ and sends the count to an output port .

Solution: In this example, a 7 bit std_logic_vector is used to define the input. An output port X
is declared as type natural to hold the calculated value that can be in the range 0 and 7. A bit
counter variable bit_count keeps track of the number of bit set to 1. The VHDL keyword length
tells the for loop the total number of bits in bit_vector A.

library ieee;
use ieee.std_logic_1164.all;

A is defined as a entity forloop1 is Because this code

set of four bits 0 port( A: in std_logic_vector(0 to 7); determines a number >=
through 7. X: out natural range 0 to 7); 0, X has been defined as
end forloop1; data type natural.

architecture BehaviorFor1 of forloop1 is

begin
process(A)
Variable v1 is variable v1: natural range 0 to 7;
set to 0 prior begin
Loop index interator i is
to the loop v1 := 0;
entry point. used to select individual
for i in 0 to A'length-1 loop
bits within bit_vector A.
if ( A(i) = '1' ) then
The final bit v1 := v1 + 1;
An if statement determines
count is end if;
if the bit is a 1 and
assigned to end loop;
increments variable v1.
the output X <= v1;
port X. end process;
end BehaviorFor1;

The simulation waveform demonstrates how 1’s in input bits A0 through A7 are added together
and the result output to X.

In the previous example problem, for loops is a good choice since the number of loops or
iterations was known. In the case of the I’s counter, the count started at bit_vector position 0 and
continued until the last bit in the bit vector was read. A std_logic_vector defined a group of bits
with the same identifier name that were accessed individually using the loop index. The index
was used to select a particular bi. Because zero is considered the first vector index, to access
the bits in the vector, you needed to access them as A(0), A(1), A(2), … A(7). The index started
at zero and ended at a number one less than the number of bits in the bit vector.

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It is good programming practices to avoid hard coding values when ever possible. In the 1’s
counter, the number of bits within the bit_vector needed to be known. There is a special VHDL
command that will tell the VHDL development tool how many bits is contained within our
bit_vector. The number of bits in a bit_array can be determined by inserting the tic ‘ and
keyword length after the port identifier as follows: A’length. Where A is the port identifier and
‘length tells VHDL that the number of bits contained in the bit_array is to be returned. The
bit_vector A can be modified to contain a different number of bits and the program will
automatically know long the new bit_array is.

While loop
An other VHDL loop structure is the while loop. For the while loop, a Boolean expression is
evaluated to determine when the while loop should stop. The Boolean expression is a pre-test
entry point to the loop structure. The Boolean expression must evaluate true before the loop can
be entered. For this reason, programmers will often write a code statement prior to the while loop
to ensure that the conditions to enter the loop are met.

The three stages of the while loop. These are:

1. The Entry Point. The point in which the loop has been entered.
2. The Terminal Test. The test of the exit condition to determine when to stop the loop.
3. The Exit Point. The point in which the loop structure is exited

The while syntax is:

while Boolean Expression loop

VHDL Statements

end loop;

The VHDL while loop is used when the number of iterations to be accomplished is to be run is not
necessarily known. The while loop continues to loop until a Boolean condition is satisfied
allowing the looping process to stop. It is possible that initial conditions to enter a while loop are
never met. The while loop Boolean expression my evaluate to the end loop condition and the
structure is never entered.

For example, the Boolean expression controlling the while loop may be evaluating a condition
that requires the loop to repeat for a varied number of iterations. Since the total number of
iterations is not known, a while loop can be employed .

Example The While Loop

Digital information is often passed as a byte. When communicating data within a digital system,
the number of bits sent from one location to the next is typically the same size. The number of
bits used to represent a value is labeled a byte. The byte can be divided into two halves, each
half is called a nibble.

A data verification scheme requires that the number of 1’s in the two nibbles of a data byte
determined. The values of the two nibbles is compared to a set of values representing valid data.

20
Write a VHDL program using a while loop to add the number of bits set to 1 in each nibble of an
8-bit byte of data and outputs the cont for the first nibble as X and the second nibble as Y.

Solution: In this example, a 4 bit bit_vector will be used to define the input byte of data. Output
ports X and Y are declared as natural because the result can only a value >=0. Two while loops
are used in this example. A bit counter variable bit_count keeps track of the bit is being accessed
in bit_vector A. The VHDL keyword length is used to find the number of bits in bit_vector A. The
Boolean expression in the first while loop checks to see if all the bits if the first nibble have been
processed. The bits in the first while loop are added together and stored in the variable v1.

When the program enters the second wile loop, bit_count is now holding the index of the first bit
in the second nibble. The 1’s in the second nibble are added and assigned to the variable v2.

entity Whileloop1 is
port( A: in bit_vector(0 to 3);
X,Y: out natural range 0 to 7);
end Whileloop1;

architecture BehaviorWhile1 of Whileloop1 is

begin
process(A)
variable v1, v2, bit_count: natural range 0 to 7;
begin
v1 := 0;
v2 := 0;
bit_count := 0;
while bit_count <= (A'length / 2 ) - 1 loop
if ( A(bit_count) = '1' ) then
v1 := v1 + 1;
end if;
bit_count := bit_count + 1;
end loop;

while bit_count <= (A'length / 2 ) -1 loop

if ( A(bit_count) = '1' ) then
v2 := V2 + 1;
end if;
bit_count := bit_count + 1;
end loop;
X <= v1;
Y <= v2;
end process;
end BehaviorWhile1;

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