B.Tech.

, 5th Semester, Solved papers, Dec 2014 57

MICROPROCESSING & INTERFACING

Dec 2014
Paper Code: EE-309-F
Figures in the bracket indicate full marks.

Note: Attempt five questions in total selecting one question from each of the four Units.
Question No.1 is compulsory.
Q.1.(a) Differentiate vectored and non-vectored interrupt. (4)
Ans. Vectored interrupt : In the vecotored interrupt, the branch address is supplied by
the external device which interrupts the microprocessor.
When a vectored interrupt occurs, CPU calculates internally, the vector address by
multiplying the vector number by 8. For example, if an interrupt in received through RST 5.5 pin
of 8085, CPU internally finds the vector address by multiplying finds the vector address by
multiplying 5.5 × 8 = 002C. The CPU transfer control of 002C (by loading 002C into PC) and
then execute the program located at that address onwards.
Non Vectored interrupt : In the non vectored interrupt, the branch address is assigned
to fixed location.
When CPU receive a non-vectored interrput, it expect some external device to supply
the vector address. For example, if the 8085 CPU is interrupted through INTR pin, then CPU
outputs one INTR for which an external circuit should supply an RST instructions opcode or call
instructions opcode. If CALL instruction opcode is supplied, then two more INTR are generated
during which the complete address is to be supplied.
CPU on receiving the address, branches to that address. If RST instruction is supplied,
CPU branches to the RST instructions vector location.

Q.1.(b) What is pipelining ? How does this occur. (4)

Ans. The process of fetching the next instruction, when the present instruction is being
executed is called as pipelining.
Pipelining has become possible due to the use of queue. BIU fills in the queue, until the
entire queue is full. BIU restarts filling in the queue when atleast two locations of queue are
vaccant. The EU always reads the next instruction byte from the que in BIU. This is much faster
than sending out an address to the memory and wainting for the next instruction byte to come. In
short pipelining eliminates the waiting time of EU and speeds up the procesing .

Q.1.(c) What are the advantages/disadvantages of memory mapped I/O over

I/O mapped I/O ? (4)
Ans. In Memory Mapped I/O Mode, the larger Instruction set of the 8085A pertaining
to memory operations may be used to access I/O devices, in contrast to just two (IN and OUT)
Instructions in the I/O Mapped I/O Mode. Also, in the former, data from any register can be
moved to a part, or data from a can be moved to any register, while in the I/O Mapped I/O Mode,
all data to and from ports have to be routed through the Accumulator. However in Memory
Mapped I/O Mode, where I/O devices are addressed as memory, fewer memory locations are
58 Microprocessing & Interfacing

available than in the case of I/O Mapped I/O Mode. Also, while accessing ports, IN and OUT
instructions can be excauted with a lesser number of clock cycle (that is, they are faster) than
LDA or STA instruction in the Memory Mapped I/O mode because the port address in the case
of I/O Mapping is one byte while it is two bytes in Memory Mapping (more time is spent on
getting the port address during the execution of the Instruction).

Q.1.(d) Explain the difference between segment and FROC directives. (4)
Ans. SEGMENT directive : An assembly program in .EXE format consists of one or
more segments. The art of these segment are defined by SEGMENT directive and the ENDS
statement indicates the end of the segment.
Format : name SEGMENT [options] ; Begin segment
. .
name ENDS ; End segment
Example : CODE SEGMENT End segement
.
.
CODE ENDS

PROC directive : The procedures in the programs can be defined by PROC directive.
The procedure name must be present, must be unique, and must follow naming conventions for
the langauage. After the PROC directive the term, NEAR or FAR are issued to specify the type
of the procedure.
Example : FACT PROC FAR ; Identifies the start of a procedure named FACT and
tells the assmebler that the procedure is far (in a segement with a different name from that
which contains the instruction which calls the procedure).

Q.1.(e) Explain hidden DMA. (4)

Ans. Hidden DMA or transparent DMA : The microprocessor executes some states
during which it floats the address and data busses. e.g., T4, T5 and T6 of 8085 opcode fetch
cycle. During these states, the microprocessor is isolated form the system bus. The DMA controller
transfers data between memory and input/output devices during these states. This operation is
transparent to microprocessor. The 8085 microprocessor executes idle machine cycle for some
instructions (DAD Rp). During this cycle, the DMA controller can transfer data. This is the
slowest DMA transfer. In this mode, the instruction execution speed of microprocessor is not
reduced. But, the transparent DMA requires logic the states when the microprocessor is floating
the buses.
The DMA controller contains four types of registers viz. address. count. control and
status register. The address register is used to hold the starting address of memory. The count
register indictates number of bytes to be transferred. Control register is used to set operating
modes of the DMA controller and status register provides states of DMA cycle.
B.Tech., 5th Semester, Solved papers, Dec 2014 59
Unit-I
Q.2.(a) Describe the Pin diagram of 8085 microprocessor. (10)
Ans. Fig. shows functional pin diagram of 8085 microprocessor. The signals of 8085
can be classified into seven groups according to their functions :
(i) Power supply and frequency signals.
(ii) Data bus and address bus
(iii) Control bus
(iv) Interrupt signals
(v) Serial I/O signals
(vi) DMA signals
(vii) Reset signals

RESET

RST
RST
RST

Fig. : Pin diagram of 8085 microprocessor

(i) Power Supply and Frequency Signals :

(a) VCC : It requires a single +5V power supply.
(b) VSS : Ground reference
60 Microprocessing & Interfacing

(c) X1 and X2 : A tuned circuit like LC, RC or crystal is connected at these two pins. The
internal clock generator divides oscillator frequency by 2, therefore, to operate a system at
3 MHz, the crystal of tuned circuit must have a frequency of 6 MHz.
(d) CLK OUT : This signal is used as a system clock for other devices. Its frequency is
half of the oscillator frequency.
(ii) Data bus and address bus :
(a) AD0 to AD7 : The 8 bit data bus (D0 - D7) is multiplexed with the lower half (A0 - A7)
of the 16 bit address bus. During first part of the machine cycle (T1), lower 8 bits of memory
address or I/O address appear on the bus. During remaining part of the machine cycle (T2 and
T3) these lines are used as a bi-directional data bus.
(b) A8 to A15 : The upper half of the 16 bit address appears on the address lines A8 to A15.
These lines are exclusively used for the most significant 8 bits of the 16 bit address.
(iii) Control and status signals :
(a) ALE (Address Latch Enable) : We know that AD0 to AD7 lines are multiplexed and
the lower half of the address is also necesarry during T2 and T3 of machine cycle to access
specific location in memory or I/O port. This means that the lower half of an address must be
latched in T1 of the machine cycle, so that it is available throughout the machine cycle. The
latching of lower half of an address is done by external latch and ALE signal from 8085.
(b) RD and WR : These signals are basically used to control the direction of the direction
of the data flow between processor and memory or I/O device/port. A low on RD indicates that
the data must be read from the selected memory location or I/O port via data bus. A low on WR
indicates that the data must be written into the selected memory location or I/O port via data bus.
(c) IO/ M , S0 and S1 : IO/ M indicates whether I/O operation or memory operation is
being carried out. S1 and S0 indicate the type of machine cycle in progress.
(d) Ready : It is used by the microprocessor to sense whether a peripheral is ready or
not for data transfer. If not, the processor waits. It is thus used to synchronize slower peripherals
to the microprocessor. If peripherals are fast enough it is tied to VCC. If it is left open, 8085 enters
in the wait state.
(iv) Interrupt signals : The 8085 has five hardware interrupt signals : RST 5.5, RST
6.5, RST 7.5, TRAP and INTR. The microprocessor recognizes interrupt requests on these lines
at the end of the current instruction execution.
The INTA (Interrupt Acknowledge) signal is used to indicate that the processor has
acknowledged an INTR interrupt.
(v) Serial I/O signals :
(a) SID (Serial I/P data) : This input serial is used to accept serial data bit by bit from the
external device.
B.Tech., 5th Semester, Solved papers, Dec 2014 61

(b) SOD (Serial O/P Data) : This is an output signal which enables the transmission of
serial data bit by bit to the external device.
(vi) DMA Signals :
(a) HOLD : This signal indicates that another master is requesting for the use of address
bus, data bus and control bus.
(b) HLDA : This active high signal is used to acknowledge HOLD request.
(vii) Reset signal :
(a) RESET IN : A low on this pin
– Sets the program counter to zero (0000H).
– Resets the interrupt enable and HLDA flip-flops. Before entering any interrupts
service routine we may have to initialize certain passing parameters. Thus it is not desired to
activate interrupts at the RESET time.
– Tri-states the data bus, addres bus and control bus.
– Affects the contents of processor’s internal registers randomly.
On reset, the PC sets to 0000H which causes the 8085 to execute the first instruction
from address 0000H. For proper reset operation reset signal must be held low for at least 3 clock
cycles. The power-on reset circuit can be used to ensure execution of first instruction from
address 0000H.
(b) RESET OUT : This active high signal indicates that processor is being reset. This
signal is synchronized to the processor clock and it can be used to reset other devices connected
in the system.

Q.2.(b) Write an assembly language Program to find the number of negative

number in the array. (10)
Ans. Program statement : Given an arrray of N numbers. Write a program in ALP of
8085 to find the number of negative numbers in the array. Assume the array at memory location
D001 H and memory location D000 H consists of the size of the array. Store the result at
memory location E000 H.
Explanation :
– We have an array of N numbers. For e.g. we intialize the count with 5.
– Also we initialize a pointer to point the elements in the array.
– We will check for the MSB. If the MSB of number is 1, the number is negative.
– Increment count for counting the negative numbers.
– Increment the pointer to point to the next elements. Check if MSB is 1. Repeat process
till all the number are scanned.
– Store the count of negative numbers.
62 Microprocessing & Interfacing

Start
Label Instruction Comment Operation
Initialise pointer
LDA D000 H Load count in accumulator A = 05 H
with source add-
MOV C,A Initialize count C = 05 H ress of array
MVI B, 00 Initialize the negative B = 00 H
Initialise counter
number count = 0
=5
LXI H, Initialize pointer to H = D0H,
D001H array L = 01 H Get the number
BACK: MOV A,M Get the number A  (HL) Add number with
ANI 80 H Check of MSB And with 80 H
80 H
JZ SKIP Check if MSB = 1 If MSB = 1, No Is
MSB = 1
number is ?
negative yes
INR B Increment negative B=B+1 Increment count for
number count negative numbers
SKIP : INX H Increment memory HL = HL + 1
pointer Increment pointer

DCR C Decrement count C=C–1 Decrement

JNC BACK If count 0 repeat counter
MOV A, B Load negative count A=B
in A No Is
count = 1
STA E000H Store the result E000H : No ?
of negative yes
number Result
Store the count
HLT Terminate program Stop of number of
execution negative numbers

Stop
Flow chart
Q.3.(a) What is interrupt ? Explain interrupt structure of 8085 microprocessor
with suitable diagram. (10)
Ans. Interrupt : It is a mechanism by which an I/O device (Hardware interrupt) or an
instruction (Software interrupt) can suspend the normal execution of the processor and get
iteself serviced.
8085 Interrupt structure : 8085 supports two types interrupts. They are :
(1) Hardware Interrputs : Peripheral device activates interrupt by activating the
respective pin. In response to the interrupt request microprocessor completes the current instruction
execution in main program and transfer program control to interrupt service routine.
B.Tech., 5th Semester, Solved papers, Dec 2014 63

In ISR routine, required task is complete. Task may be to read data, to write data to
update the status, to update to counter etc. After completing the task, the program control is
transferred back to the main program. These types of interrupts where the microprocessor pins
are used to receive interrupt requests, are called hardware interrupts. The microprocessor 8085
has five hardware interrupts they are :
(i) TRAP
(ii) RST 7.5
(iii) RST 6.5
(iv) RST 5.5
(v) INTR
The interrupt structure is a 5 level structure. Fig. shows the interrupt structure.

Fig. : 8085 interrupt structure

64 Microprocessing & Interfacing

(i) TRAP : It is a non maskable edge and level triggered interrupt. It is unaffected by any
mask or interrupt enable. The TRAP signal must a LOW to HIGH transition and remain HIGH
until acknowledged. This avoids false triggering due to noise or glitches. It has the highest
priority among all interrupts. This interrupts transfers the microprocessor’s control to location
0024 H. It is used for emergency purpose like power failure, parity, error checker, smoke detector
etc.
(ii) RST 7.5 : It is maskable, edge triggered, interrupt resquest input line. This interrupt is
triggered at the rising edge of the signal. It has highest priority among all maskable interrupts and
second priority among all interrupts. The interrupt vector location for this interrupt is 003C H.
Action taken by microprocessor, when it receives RST 7.5 :
Step I : The peripheral activates RST 7.5 signal to set R7.5 flip-flop.
Step II : When R7.5 flip flop is set and if INTE flip -flop is set and M7.5 mask latch is
reset, the logic activates an internal RST 7.5 resquest signal.
Step III : In response to this signal, the microprocessor completes current instruction
cycle and calculate starting address of ISR. It activates RST 7.5 acknow ledge and any
interrupt acknowledge signals to reset R 7.5 and INTE flip flop respectively.
Step IV : The microprocessor executes two memory write cylces to save contents of
program counter on the stack and then executes corresponding ISR.
Using SIM instruction the M6.5 and M5.5 flip flop can be set or reset and hence enable
or disable RST 6.5 and 5.5. DI clears the interrupt enable flip flop, while EI sets the interrupt
enable flip flop. (EI and DI are instructions). M7.5 and interrupt enable flip flop together decide
whether RST 7.5 is enabled or disabled.
(iii) RST 6.5 and RST 5.5 : These are level triggered, maskable interrupt request input
lines. RST 6.5 transfers microprocessor’s control to location 0034 H while RST 5.5 transfers
microprocessor’s control to location 002C H. Action taken by microprocessor, when it receives
RST 6.5 interrupt :
Step I : The peripheral activates RST 6.5 signal.
Step II : When RST 6.5 pin is at logic 1, INTE flip flop is set and M 6.5 mask latch is
reset, the logic activates an internal RST 6.5 request signal.
Step III : The microprocessor completes current instruction cycle calculate the starting
address of ISR. It activates any interrupt acknowledge cycle to reset INTE flip flops.
Step IV : The microprocessor executes two memory write cycle to save contents of
program counter on the stack and then executes corresponding ISR.
Using SIM instruction the M6.5 and M5.5 flip flop can be set or reset and hence enable
or disable RST 6.5 and 5.5. DI clears the interrupt flip flop, while EI sets the interrupt enable flip
flop (EI and DI are instructions). M7.5 and interrupt enable flip flop together decide whether
RST 7.5 is enabled or disabled.
The above steps are also true for RST 5.5.
(iv) INTR : It is level triggered, maskable interrput request input line. This interrupt
works in conjunction with RST N or CALL instruction. The INTR logic consists of INTE
flip-flop, OR gate and inverter. The INTR pin is logically ANDed with the output of INTE flip
flop. To activate an internal INTR request signal, the INTR pin should be held at logic 1 and
INTE flip flop should be set. This flip flop is set by executing EI instruction. It is reset by executing
DI instruction. It is also reset by RESET IN or any interrrupt acknowledge signal. In response
B.Tech., 5th Semester, Solved papers, Dec 2014 65

to any interrupt the microproessor resets in INTE flip flop that means it disables all maskable
interrupts.
Using SIM instruction the M6.5 and M5.5 flip flop can be set or reset and hence enable
or disable RST 6.5 and RST 5.5. DI clears the interrupt enable flip flop, while EI sets the
interrupt enable flip flop. (EI and DI are instructions). M6.5 and M5.5 and interrupt enable flip
flop together decide whether RST 6.5 and RST 5.5 are enabled or disabled.
Action taken by the microprocessor when it receives an INTR :
Step I : The 8085 microprocessor checks for the status of the INTR signal while it
executes each instruction.
Step II : If the INTR signal is high, then the microprocessor completes the execution of
the current of the current instruction and in response to the INTR signal sends an active low
INTA interrupt acknowledge singal, if the interrupt is enabled.
Step III : In response to the INTA signal, the external logic places on opcode on the
data bus. In case of multibyte instruction, additional interrupt acknowledge cycles are generated
by the microprocessor, in order to transfer additional bytes to the microprocessor.
Step IV : The 8085 then saves the address of the next instruction onto the stack and
execute the received instruction.
Software interrupts : In case of software interrupts the cause of the interrupt is the
execution of the instruction. The microprocessor 8085 has eight instructions. These eight
instructions are RST 0 to RST 7. Such interrupts are called as software interrupts. They allow
the microprocessor to transfer program control from the main program to the subroutine program
(i.e. predefined service routine address).
After completing the subroutine program, the program control returns back to the main
program.
Q.3.(b) Write an assembly language Program to transfer 150 bytes of data from
memory location starting at 21000H to memory addressed by 31000H. (10)
Ans. Let take
 Contents of DS = 2000 H, SI = 1000 H
ES = 2848 H, DI = 2520 H
Physical Address of DS : SI Physical Address of ES : DI
DS = 2 0 0 0 0 H ES = 2 8 4 8 0 H
SI = 1 0 0 0 H DI = 2 5 2 0 H
2 1 0 0 0 H 3 1 0 0 0 H
CLD Clear Directions Flag, DF = 0
MOV AX, 2000 H MOVE the starting address of DS Register into Accumulator.
MOV DS, AX Starting address of DS Register loaded to DS Register.
MOV AX, 2848 H Starting address of ES Register is moved to Accumulator.
MOV ES, AX Loaded to ES Register.
MOV CX, 96 H Hexadecimal equivalent of 150 (= 96 H) loaded to CX as count.
MOV SI, 1000 H Offset address 1000 H moved to Source Index Register
MOV DI, 2520 H Offset address 2520 H moved to Distination Index Register
REP MOV SB Contents starting from 21000 H (150 bytes) transferred to 31000
H.
66 Microprocessing & Interfacing

Unit-II
Q.4.(a) Explain BIU and EU of 8086 microprocessor. (15)
Ans. Bus Interface Unit (BIU) : The Bus Interface unit fetches instructions from
memory, reads data from ports and memory and writes data to ports and memory. It handles all
transfers of data and addresses on the buses for the execution unit. The Bus interface Unit
consists of the following :
(a) Instruction Queue (b) Segment Registers (c) Instruction Pointer
(a) Instruction Queue : The instruction queue is a first-in-first-out group of registers.
To speed up program execution, the Bus Interface Unit fetches as many as six instruction bytes
are held for the Execution Unit in a Instruction Queue. The BIU can be fetching instruction
bytes while the Execution Unit (EU) is decoding the instruction or executing an instruction which
does not require use of the buses. When the Execution Unit is ready for its next instruction, it
simply reads the instruction from the Instruction Queue in the BIU. This scheme is much faster
than sending out an address to memory and then waiting for memory to send sack the next
instruction byte. The prefetch instruction and queue scheme greatly speeds up processing. The
arrangement of fetching the next instruction while the current instruction executes is called pipe
lining.

Fig. : Block diagram of 8086 microprocessor

B.Tech., 5th Semester, Solved papers, Dec 2014 67

(b) Segment Registers : The Big Interface Unit (BIU) contains four 16 bit segment
registers. They are :
– Code Segment Register (CS)
– Stock Segment Register (SS)
– Extra Segment Register (ES)
– Data Segment Register (DS)
(c) Instruction Pointer : The instruction pointer register is a 16 bit register which holds
the address of the next code byte that is to be fetched within the code segment. This register
contains the address value which is an offset, because this value must be added to the segment
base address contained in CS register to produce the required 20 bit physical address.
Execution Unit (EU) : The execution unit of 8086 performs the following major
operations :
– It tells the BIU, from where to fetch instructions or data.
– It decodes and executes instructions.
To perform the above operations, the execution unit consists of the following sections :
(a) Instruction Decoder, ALU and control circuitry.
(b) Flag Register
(c) General Purpose Registers
(d) Stack Pointer Register
(e) Other Pointer and Index Registers
(a) Instruction decoder, ALU and control circuitry : The instruction decoder in the
EU translate instructions fetched from memory into a series of actions which are further carried
out. The Airthmetic and Logic Unit (ALU) of 8086 is of 16 bits which can add, subtract, AND,
OR, XOR, increment, decrement, complement or shift the binary numbers. All internal operations
of EU are controlled by control circuitry.
(b) Flag register : 8086 microprocessor contains one 16 bit flag register (status register).
A flag register is a flip flop which indicates the status of some conditions produced by the
execution of an instruction or controls certain operations of the Execution Unit. In a 16 bit flag
register, there are nine active flags. Six of the nine flag bits are used to indicate some conditions
produced by an instructions. These six flags are called status flag (conditional flags). The remaining
three flag bits in the flag register are used to control certain operations of the processor and are
called control flags.
(c) General purpose registers : The execution unit 8086 contains eight general purpose
registers labelled as AH, AL, BH, BL, CH, CL, DH and DL in the fig. below.

Fig. : 8086 general purpose register

(d) Stack pointer register : The stack pointer register SP is a 16 bit register which
contains the 16 bit offset address from the start of the stack segment to the memory location
where a word was most recently stored on the stack. The stack memory location where a word
was mostrecently stored is called top of the stack.
68 Microprocessing & Interfacing

(e) Other pointer and index registers : In addition to the stack pointer register SP, the
EU of the 8086 also contains a 16 bit base pointer register BR The base pointer register BP
contains the 16 bit offset address relative to the stack segment register SS but it is employed in
the based addressing mode of 8086.
Q.4.(b) What is Pipelining ? (5)
Ans. Pipelining : The process of fetching the next instruction, when the present
instruction is being executed is called as pipelining. Pipelining has become possible due to the use
of queue. BIU fills in the queue, until the entire queue is full. BIU restarts filling in the queue
when atleast two locations of queue are vaccant.
Advantage of Pipelining :
(i) The EU always reads the next instruction byte from the queue in BIU. This is much
faster than sending out an address to the memory and waiting for the next instruction byte to
come.
(ii) In short pipelining eliminates the waiting time of EU and speeds up the processing.
(iii) The 8086 BIU will not initiate a fetch unless and until there are two empty bytes in
its queue. 8086 BIU normally obtains two instruction bytes per fetch.
Q.5.(a) Calculate the Physical address represented by : (10)
(a) 1234 H : 0002H
(b) F2 F2 H : 1234H
Ans. Physical address is obtained in 8086 p by adding the constant of CS (Code
Segement) Register which holds the upper 16 bits of starting address of code segment & the
contents (i.e 16 bit address) of IP (Instruction Pointer) which actually holds the offset.
These contents of CS and IP are added Because 8086 up’s Physical address is of 20
bits.
(a) Physical address of 1234 H : 0002H will be
Additional zero is added
to compare 20 bit address.
1 2 3 4 0 H
Physical address 0 0 0 0 2 H
1 2 3 4 2 H
Physical address  12342 H
(b) CS = F2 F2 H and 1234 H = IP
Additional zero
F 2 F 2 0 H
1 2 3 4 H
F 4 1 5 4 H
Physical Address  F 4 1 5 4 H

Q.5.(b) Describe the 8086 instruction queue. Explain the advantages of Program
relocation in 8086 microprocessor. (10)
Ans. Instruction queue : The execution unit is supposed to decode or execute an
instruction. Decoding does not require the use of buses. When EU is busy in decoding and
B.Tech., 5th Semester, Solved papers, Dec 2014 69

executing an instruction, the BIU fetches upto six instruction bytes for the next instructions.
These bytes are called as the prefetched bytes and they are stored in a first in first out (FIFO)
register set, which is called as a “queue”.
Significance of Queue : To understand the significance of the queue, refer fig.

Fig. : Significance of queue

As shown in fig., while the EU is busy in decoding the instruction corresponding to

memory location 100F0, the BIU fetches the next six instruction bytes for locations 100F1 to
100F6 numbered as 1 to 6. These instruction bytes are stored in the 6 bytes Queue on the first in
first out (FIFO) basis. When EU completes the execution of the existing instruction, and becomes
ready for the next instruction, it simply reads the instruction bytes in the sequence 1, 2,.... from
the Queue. Thus the Queue will always hold the instruction bytes of the next instructions to be
executed by the EU.

Advantages of Program relocation in 8086 microprocessor :

(i) We can address 1 MB memory spare with only 16 bits Registers.
(ii) It allows a program to be put in different areas of memory each time program in
executed.
(iii) Relocatable program is executed without any changes.
(iv) Relocated program can work on seprate data sets.
(v) Can relocate a program by simply changing the contents of code segment.
(vi) Program Relocation is suitable for general purpose computers.
(vii)Without relocation, a program has to be rewritten to be altered if a memory segement
has to be moved.
70 Microprocessing & Interfacing

Unit-III
Q.6.(a) Explain directives and identifiers used in 8086 microprocessor. (10)
Ans. Directives used in assembly language program are as follows :
Directive Action
ALIGN aligns next variable or instruction to byte which is multiple of operand.
ASSUME selects segment register(s) to be the default for all symbol in segment(s)
COMMENT indicates a comment
DB allocates and optionally intializes bytes of storage
DW allocates and optionally intializes doublewords of storage
DD allocates and optionally initializes doublewords of storage
DQ allocates and optionally initializes quadwords of storage
DT allocates and optionally initializes 10-byte long storage units
END terminates assembly; optionally indicates program entry point
ENDM terminates a macro defination
ENDP marks end of procedure definition
ENDS marks end of segment or structure
EQU assigns expression to name
EVEN aligns next variable or instruction to even byte
ESITM terminates macro expansion
EXTRN indicates externally defined symbols
LABEL creates a new label with specified type and current location counter
LOCAL declares local variables in macro definition
MACRO starts macro definition
MODEL specifies mode for asssembling the program
ORG sets location counter to argument
PAGE sets length and width of program listing; generates page break
PROG starts procedure definition
PTR assigns a specific type to a variable or to a label
PUBLIC identifies symbols to be visible outside module
TITLE defines the program listing title
Identifiers : An identifier is basically a name that is applied to an item in the program
for reference purpose.
An identifier is basically a symbole cased for reference is a program.
Basically these are two types of identifiers in 8086 p.
(i) NAME identifer : This type of identifiers identifies the item by name or can say
refers to the address of data item.
e.g. COUNTER (Name identifier) in Counter DBO.
(ii) Label Identifier : Refer to the address of an instruction, procedure or segment
e.g. MAIN PROC FAR MAIN  MAIN is label identifier.
B 30 : ADD BL, 30 B30 is label identifier
Maximum length of an identifier is 31 characters upto MASM 6.0 & 247.
B.Tech., 5th Semester, Solved papers, Dec 2014 71
Following characters can be used as Indentifiess
(i) Alphabetic characters : - A to Z and a -z
(ii) Digit : 0 – 9 (but not as 1st character)
(iii) Special charackes : ? _ $ @. (but not as 1st character)
Q.6.(b) Write a simple assembly language Program to add two memory locations
where each memory location is one byte wide. (10)
Ans.
Program Comments
LDA 2500 H Load Accumulator directly from memory location 2500 H.
MOV B, A MOVE contents of Accumulator (i.e from 2500 H) to Register
B.
MVI C, 00 H Initialize carry by putting value 0 in Resgister C.
LDA 2501 H Load Accumulator directly from 2501 H (i.e. 2nd number.
ADD B Add contents of Register B to Accumulator (i.e 1st number +
2nd number = stored in Accumulator)
JNC Jump to LABEL if no carry generated
INR C Otherwise increment Register C by 1 (i.e. carry generated)
LABEL : STA = 2502 Store Result of addition to memory location 2502 H.
MOV A, C Move contents of Register C (i.e. = 01) to Accumulator.
STA 2503 H Store content of Accumulator to memory location 2503 H.
HLT Program Ended Halt.
Q.7.(a) Explain NOP and HLT instructions with the help of suitable
example. (10)
Ans. NOP instruction :
Mnemonic NOP Flags : It does not affect any flag.
NOP : No operation
Algorithm Do nothing
Addr. Mode Implied addressing mode
Operation The execution of this instruction causes the CPU to do nothing.
(i) This instruction causes the CPU to do nothing.This instruction
uses three clock cycles and increments the instruction pointer to
point to the next instruction.
(ii) It can be used to increase the delay of a delay loop.
Example :
MOV AL, 00011011b
NOT AL ; AL = 11100100b
RET
Flags : all unchanged.
72 Microprocessing & Interfacing

HLT (Halt until interrupt or reset) Instruction :

Mnemonic Halt processing Flags : No flags are affected..
Operation (i) The HLT instruction will cause the 8086 to stop fetching and
executing instructions. The 8086 enters into a half state. To
come out of the halt state, there are 3 ways given below.
(a) Interrupt signal on INTR pin, (b) Interrupt signal on NMI pin
(c) Reset signal on reset pin.
(ii) It may be used as an alternative to an endless software loop in
situations where a program must wait for an interrupt.
Q.7.(b) Explain instruction execution timing with example. (10)
Ans. Instruction Execution timing : The execution time for instruction varies and
depends upon the type of instruction and addressing modes. Basic Instruction time can determined
by multiplying the number of clock needed to execute the instruction by clock’s period.
The total instruction execution time is the sum of Basic time plus time required to calculate
the effective Address if a memory operand is accessed. The Basic instruction time assumes that
the instruction to be executed has already been prefetched and stored in instruction queue. If not
so, then additonal clock cycles must be added to find the total execution time.
Total instruction execution time depends upon :
(i) No. of memory seferences required by instruction : If operand is a single byte
or word with an even address, then only are memory reference is needed, if with an odd address
then two memory references is needed. Each memory reference require 4 clock cycle.
(ii) Addressing nodes : In case of 2 operand instruction, register to register addressing
gives fasters operation than register to memory or vice-versa operation, and between memory
to register and register to memory operation, the memory to register operation is faster.
(iii) Variable Basic Execution Times : Some Instruction are data dependent & Require
Variable Basic Execution Times. These are multiply, divide, shift & Rotate.
(iv) Conditional Branch Instruction : For these, 2 different timings are specific smaller
time should be considered when condition is not met and branch is not taken. Larger time is
considered when condition met. Hence some extra cycle are required to fetch the next instruction.
Let’s take on example of Ready & Wait state : The Ready input causes wait state for
slower memory & I/O Devices to cope with up. A wait state is an extra clocking period inserted
between T2 and T3. Due to this memory access time of 5 MHz with 460 ns is increased by 200
ns to make it (460 ns + 200 ns = 660 ns)
TW = Wait State

T2 TW T3
CLK

30ns
READY 8ns

Fig. : READY input timing in 8086 p.

B.Tech., 5th Semester, Solved papers, Dec 2014 73

If READY is at logic 0 after T2 , then T3 is delayed and Tw is inserted between T2 and T3.
Ready is next sampled at middle of Tw to determine if next state is Tw or T3. It is tested for a logic
0 on 1 to 0. Transition of clock at the end of T2 & for a 1 on 0 to 1 transmition of clock in middle
of T w. Also READY input 8086 p has some stringent tining reguirements. Such timing
requirements are fulfilled by the internal READY synchronization circuitry of 8284 A clock
generator.
Unit-IV
Q.8.(a) Describe the major components of 8279 keyboard/display/CPU interface
with the help of its block diagram. (10)
Ans. Fig. shows a block diagram of 8279 funticonally 8279 is divided into three sections:
(i) CPU Interface and control section.
(ii) Keyboard section.
(iii) Display section.

Fig. : Block diagram of 8279

74 Microprocessing & Interfacing

(i) CPU interface and control section : It consists of data buffers, I/O control, control
and timing registers and timing and control logic.
(a) Data Buffers : These are bidirectional, tristate buffers. It connects external data
bus to the internal bus.
(b) I/O Control : It uses CS , A0, RD and WR lines to control data flow to and from the
various internal registers and buffers.
(c) Control and timing register : This block consists of control and timing registers.
8279 provides 8 control and timing registers which are distinguished by higher three bits of
command word. To access these registers, A0 line should held at logic 1. These registers store
the keyboard and display modes and other operating conditions of chip. These registers are
affected by reset signal.
(d) Timing and control logic : It generates all internal keyboard and display control
signal. It also generates BD signal, provides proper key scan, row scan, display scan and debounce
timings.
(ii) Keyboard section :
(a) FIFO/Sesnor RAM : It is an 8 × 8 bits read only RAM. Its function depends upon
operating modes. In scanned keyboard mode, it functions as a FIFO RAM. In this mode the
position of depressed key (Row no. and function no) along with status control and shift keys is
entered into FIFO RAM location. The data format of FIFO RAM location for scanned keyboard
mode is given below.

The lower three bits (C2, C1, C0) indicate to which return line the depressed key was
connected. R2, R1, R0 bits give the value of coresponding scan count in encoded mode. In decoded
mode, R2 is always zero. The inidicate to which row the depressed key was found. In this mode,
the microprocessor cannot access other entries without accesing first one, in sensor matrix
mode, this block functions as sensor RAM. In this mode, the data on the return sensor RAM is
specified by scan counter (row no of sensor matrix). Therefore each sensor switch position can
be scanned by the CPU. The shift and CNTI inputs are ignored.
The data format of a sensor RAM location for sensor matrix mode is given below.
RL7 R L6 RL5 R L4 R L3 R L2 R L1 R L0
(b) Keyboard debounce and control : In scanned keyboard mode, it debounces, encodes
and stores encoded value into FIFO key closures. It also saves status of shift and control keys
into FIFO. It updates information stored into FIFO/sensor RAM status register. In sensor matrix
mode, the debounce logic is inhibited and the contents of the retrun lines is directly transferred to
the corresponding location of sensor RAM.
(c) Retrun Buffers : The RL0- RL 7 lines are buffered and lateched by this block. It
scans RL 0 – RL 7 lines during each row scan in scanned keyboard or sensor matrix mode.
RL0 – RL7 lines are not scanned in strobed input mode.
B.Tech., 5th Semester, Solved papers, Dec 2014 75

(iii) Display section : It consists of display RAM, display address registers and display
registers.
(a) Display Section : It is 16 × 18 bits display RAM. During initialization, all locations
are loaded with clear code or blank code. The microprocessor can read or write this RAM. The
address of location to be accessed is specified by command word. During each digit time, the
contents of selected location are transferred into display register. In the decoded mode, the 8279
used only first four locations. In the encoded mode, the 8279 uses first 8 locations (8 digits) or all
locations (16 digits).
(b) Display address registers : It constains two types of address registers viz.
microprocessor controlled address registers and timing controlled address registers.
(c) Display registers : These registers holds the codes of character to be displayed.
They are divided into two nibbles viz. nibble A and nibble B.
Nibble A and nibble B can be blanked and inhibited individually.
During each digit scan, the contents of some registers hold blanking code of the display.
Q.8.(b) List the operating modes of 8255 PPI chip. (10)
Ans. Various operating modes of 8255 PPI chip are as follows :
1. BSR Mode : The BSR mode is a port C bit set/reset mode. The individual bit of port
C can be set or reset by writing control word in the control register. The control word format of
BSR mode is shown in fig.

Fig. : BSR control word format

The pin of port C is selected using bit select bits [b b b] and set or reset is decided by bit
S/R. The BSR mode affects only one bit of port C at a time. The bit set using BSR mode remains
set unless and until you change the bit. So to set any bit of port C, bit pattern is loaded in control
register. If a BSR mode is selected it will not affect I/O mode.
2. I/O modes of 8255 PPI chip : I/O modes of 8255 PPI chip are as follows :
(i) Mode-0 operation : In the mode-0, the 8255 can be programmed as simple input or
output. Each of the four ports, port A, port B, port CU (upper) and port CL (Lower) of 8255 can
be programmed to be either an input port or an output port. Data is written into or read from the
specific port. The input/output features of 8255 in the mode-0 are :
– Two 8 bit ports and two bit ports
– Any port can be an input port or an output port.
76 Microprocessing & Interfacing
– Outputs are latched where as inputs are not latched.
– Ports do not have handshake or interrupt capability.
(ii) Mode-1 operation : In the mode-1 operation of 8255, the handshake signals are
exchanges betweeen the microprocessor and peripherals prior to data transfer. The features of
this mode are :
– Two ports, port A and port B can function as 8 bit I/O ports. Port A and port B can be
configured either as input port or output port.
– Each port (port A and port B) uses three lines from port C as handshake signals. The
remaining two lines of port C can be used for simple I/O functions.
– Interrupt logic is supported.
– Both inputs and outputs are latched.
(iii) Mode-2 operation : In this mode, the port A can be used as a bidirectional port and
port B can be used either in mode 0 and 1 operation. Port A uses five signals from port C as
handshake signals for data transfer. The remaining three signals of port C can be used either as
simple I/O function or as handshake signals for port B. The mode-2 operation is generally used
for bidirectional data transfer. Data transfer between two computers can be accomplished using
8255 programmable peripheral interface in mode-2 operation.
Q.9.(a) Explain 8237 DMA controller with help of Pin diagram. (10)
Ans. The fig. shows pin configuration of 8237.

Fig. : Pin configuration of 8237

B.Tech., 5th Semester, Solved papers, Dec 2014 77

Symbol Description
CLK This is a clock input line ignored in slave mode. In master mode,
this signal controls all internal and external DMA operations.
The data transfer rate depends upon the frequency of this signal.

CS In slave mode, this signal is generated by address decoder

to select 8237 chip for communication between CPU and 8237.
In master mode, this signal is ignored.
Reset It is an asynchronous input line. This signal clears the command,
status, request and temporary register and forces 8237 into
slave mode.
READY In master mode, this signal is used to add wait states into a
DMA cycle.
HRQ It is a hold request output line. It is connected to hold input of
the CPU. It is used to request control of the system bus.
HLDA It is a hold acknowledge input line. This signal is generated by
CPU. In response to this signal, the 8237 gains control of the
system bus and enters into master mode.

IOR It is an active low bi-directional tristate line. In slave mode, it

acts as an input line and used to read contents of 8237 registers.
In master mode, it acts as an output line. This signal is generated
during DMA cycle to read data from I/O device.

IOW It is an active low bi-directional line. In slave mode, it acts as an

input line and used by CPU to write contents to 8237 registers.
In master mode, it acts as an output line. This signal is generated
during DMA read cycle to write data into I/O device.
A0 - A3 These are bi-directional, address lines. In slave mode, these
lines act as input lines, used to select one of the registers of
8237. In master mode, the 8237 provides lower bits of memory
address on these lines.
A4 - A7 These are tristate address output lines. These lines are tristated
in slave mode. In master mode, the 8237 transfers bits of
memory address on these lines.

MEMR It is an active low tristate control output line. It is tristated in

slave mode. In master mode, this signal is generated during
DMA read cycle or during memory to memory transfer cycle
to read contents of source memory.
78 Microprocessing & Interfacing

MEMW It is an active low tristate output line. It is tristated in slave

mode. In master mode, this signal is activated during DMA
write or during memory to memory transfer cycle to read
contents of destination memory.
DB0 - DB7 These are bi-directional tristate buffered data lines. In slave
mode, these lines are used to transfer data between CPU and
8237’s registers. In master mode, these lines act as address
output lines. The 8237 places higher byte of address on these
lines during DMA cycles.
AEN This active high output enables the 8 bit latch that drives the
upper 8 bit address bus. The AEN pin is used to disable other
bus drivers during DMA transfers.
ADSTB This output line is used to strobe the upper address byte
generated by 8237 in master mode into an external latch.
DREQ0 - DREQ0 These are asynchronous DMA channel request lines used by
peripheral. The polarity of each signal is programmable i.e. these
lines can be used as either active high or active low input. DREQ
must be maintained until the corresponding DACK is activated.
DACK0 - DACK3 These are DMA acknowledge output lines. The polarity of each
line is programmable. This signal indicates that the requesting
peripheral has been granted fro DMA cycle.
EOP End of Process : It is an active low bi-directional signal. This
line is also used to terminate DMA cycle. The DMA cycle can
be terminated by pulling EOP input low. The 8237 also
generates EOP pulse, when the terminal count for any channel
is reached.
Q.9.(b) Explain :
(i) Mode-2 strobbed bidirection I/O of 8255
(ii) Priority Resolver. (10)
Ans. (i) Mode-2 strobbed bidirection I/O of 8255Working of 8255 : In this mode
group A is used as input and output i.e. for transmitting and receiving data from peripheral
through 8255 as shown in fig.(a).
The transfer of data is achieved by port C handshake signals. The group B can be in
Mode 0 or Mode 1.
The bi-directional data is transferred through port A so it consists of input and output
latch.
The Mode 2 is combination of Mode 1 input and output both at a time to port A.
The interrupt signals of input and output mode are combined to generate common
interrupt signal to CPU. The internal organization of these signals is as shown in fig. (b).
B.Tech., 5th Semester, Solved papers, Dec 2014 79

The different handshake signals used are OBFA , ACK A ,STBA , IBFA and INTERA. 2
handshake signals are used for output operation, 2 are used for input operation and one is common
to both.
Output operation :
– OBF (Output buffer full) : This is an active low output signal generated by 8255.
When CPU writes data to output port 8255 will enable OBF signal to indicate peripheral that
data is available in output buffer.

Fig. (a) : Mode 2 interfacing Fig. (b) : PA, PB and PC in mode 2

– ACK (Acknowledge) : This is an active low input signal for 8255. When the peripheral
detects OBF signal, it reads data from 8255 port and makes ACK = 0 and the ACK signal is
used to acknowledge 8255 that data is read from port so 8255 will remove OBF signal to
indicate output buffer is empty.
Input operation :
– STB (strobe) : This is an active low input signal. When the peripheral writes data to
input buffer, it generates a signal STB to indicate 8255 that it has written data.
– IBF (Input buffer full) : When data is available in input buffer 8255 will enable IBF
signal to indicate that data is available in input buffer.

Ans. (ii) Priority resolver : It determines the priorities of the bit set in the IRR. To
make decision, the priority resolver looks at the ISR. If the higher priority bit in the InSR is set
80 Microprocessing & Interfacing

then it ignores the new request. If the priority resolvers finds that the new interrupt has a higher
priority than the highest priority interrupt currently being serviced and the new interrupt is not in
service, then it will set appropriate bit in the InSR and send the INT signal to the microprocessor
for new interrupt request.