B.Tech.

, 5th Semester, Solved papers, Dec 2010 1

MICROPROCESSING & INTERFACING

Dec 2010
Paper Code: EE-309-E
Figures in the bracket indicate full marks.
Note: Attempt any five questions. All questions carry equal marks.
Q. 1(a) Write the purposer of following signals in 8085.
(i) IO / M (ii) S0, S1
(iii) RD (iv) WR
(v) RESET IN (vi) X1, X2
(vii) CLK OUT (viii) INTA (10)
Ans. (i) IO / M (Input output/ Memory : This is an O/P status signal, used to give status of
operation to be performed with memory or I/O device. When IO/M = 0 the microprocessor is performing
a memory related operation and when IO/M = 1 the microprocessor is performing the I/O device related
operation. This is the signal which seperate memory and I/O device. To implement this IO/M signals is
combined with read write control signals and two sets of singals are generated one for I/O device
namely : IOR,IOW,MEMR and MEMW .
(ii) S0, S1 : (a) These are output status signals used to give information of operation performed by
microprocessor.
(b) When S0 and S1 is combined with IO / M we get status of all the machine cycles (operations)
performed by 8085 as shown in Table.
Status Signals Operation Control signals used
IO / M S1 S0
0 0 0 – –
0 0 1 Memory write WR
0 1 0 Memory read RD
0 1 1 Opcode fetch RD
1 0 0 – –
1 0 1 I/O write WR
1 1 0 I/O read RD
1 1 1 Interrupt acknowledge INTA
Z 0 0 Halt
Z X X Hold –
Z X X Reset

(iii) RD : This is an active low, output control signals used to read data from memory or an I/O
device.
2 Microprocessing & Interfacing

Fig : (a)
To read data from device microprocessor selects a device, make data bus available for data
transfer and then generates signals RD to read data from selected device or memory. This line is tristate
by 8085 for conditions same as A8 to A15.
(iv) WR : This line is an active low control signal used to write data to memory or an I/O device.
To write data to device or memory microprocessor selects a device and transfer data on data lines and
then generates signal WR . The signal WR indicates that the contents of data bus is to be written on the
selected device. This line is tristated by 8085 conditions same as A8 to A15.

Fig : (b)
(v) RESET IN : This is an active low input signal used to clear program counter, i.e., 0000H and
makes address, data and control lines tristated. After reset the states or internal register and flag are
unpredictable. CPU is held in reset condition as long as RESETIN is applied. After reset the microprocessor
start executing instructions from 0000H.
(vi) X1, X2 : (a) These are clock input signals, connected to crystal, LC or RC network. The crystal,
LC or RC is connected between these two pins.
(b) The X1and X2 pins drive the internal clock generator circuit. Hence, externally only one crystal
is enough.
(c) The frequency is divided by 2 and used as operating frequency. Generally the 6.014 MHz
crystal is connected to X1 and X2, this is divided by 2. So the operating frequency of 8085 is 3.07 MHz.
(vii) CLK OUT :
(a) This is an output signal , used as a system clock.
(b) The internal operating frequency is available on CLK OUT pin.
(c) This pin can be used by the peripherals as a system clock input for their operation. Hence,
there will be synchronization between the different peripherals and the microprocessor.
(viii) INTA : (a) it is an output signal.
(b) INTA is used to indicate that the microprocessor has received an INTR interrupt.
B.Tech., 5th Semester, Solved papers, Dec 2010 3

Q.1.(b) Explain the purpose of following in 8085

(i) Serial I/O control
(ii) Interrupt control. (4 + 6 = 10)
Ans. (i) Serial I/O control : (a) The data transferred on to data bus is parallel data,but under
certain condition it is advantageous to use serial data transfer. 8085 implements this by using SID and
SOD signals.
(b) The data on these lines is accepted or transferred under software control by serial I/O control
block.
(c) In 8085 to perform serial data transfer there are two special instructions RIM and SIM.
(ii) Interrupt control : (a) This block accepts different interrupt request inputs such as TRAP,
RST 7.5, RST 6.5, RST 5.5 and INTR.
(b) INTA is an acknowledgement pin for maskable and non-vectored interrupt i.e. INTR.
(c) When a valid interrupt request is present it informs control logic to take action in response to
each signal. In such a case the processor has to be interrupted in order to service the interrupt.
(d) The interrupt control units job is to service the interrupt and after completing the interrupt
service routine return back the control to the main program where it was interrupted.

` Q.2.(a) Write the purpose and working of following instructions in 8085 : RIM, SIM,
RRC, XCHG, DAD Rp. (10)
Ans. SIM : Set Interrupt Mask
(i) This instruction is used to enable/disable the RST 7.5, RST 6.5 and RST 5.5 interrupts.
(ii) This instruction does not affect on the TRAP and INTR inputs.
(iii) It can also be used for serial data transmission.
(iv) It transfers the control word from accumulator to the interrupt control logic, and the serial
control logic. So, it is essential to load the (SIM format) control word into the accumulator before the
execution of SIM instruction.
RIM : Read Interrupt Mask
(i) This instruction is used to check the status of all pending and maskable interrupts.
(ii) It can also transfer serial data bit from the serial input data line (SID) to the D7 bit of the
accuumulator.
(iii) This instruction transfers the contents of the interrupt control logic and serial control logic
to the accumulator. Hence, accumulator is loaded with the status format after execution of the RIM
instruction.
XCHG : This instruction exchanges contents of H reg, with D reg. and L reg. with E reg.
Operation : H  D, L  E
DAD RP : This instruction adds the contents of specified register pair to HL pair and stores the
result in HL pair. The examples of RP are SP, BC, DE and HL. Only carry flag is modified to reflect the result
of operation.
Operation : RP + HL  HL
RRC : This instruction rotates the contents of accumulator right by 1 bit. D7 will be transferred to
D6, D6 to d5 and so on D1 to D0, D0 to D7 as well as to the carry flag.

Fig.
4 Microprocessing & Interfacing

Operation : Accumulator : Dn + 1  Dn (n = 0 to 6)
D0  D7, D0  CY

Q.2.(b) Multiply two 8 bit numbers stored in memory location D000 H and D001 H. Store the
result in memory locations E000 and E001 H. (10)
Ans. Explaination :
(i) Consider that a byte is present at the memory location D000 H and second byte is present at
memory location D001 H.
(ii) We have to multiply the bytes present at the above two memory locations.
(iii) We will multiply the numbers using successive addition method.
(iv) In successive additon method, one number is accepted and other number is taken as a
counter. The first number is added with itself, till the counter decrements to zero.
(v) Result is stored at memory locations E000 H and E001 H.
For example : D000 H = 12 H, D001 H = 10 H
Result = 12 H + 12 H + 12 H + 12 H + 12 H + 12 H + 12 H + 12 H + 12 H + 12 H
Result = 0120 H
E000 H = 20 H
E001 H = 01 H

Fig : Flowchart
Flow Chart : Refer flowchart.
B.Tech., 5th Semester, Solved papers, Dec 2010 5

Program :
Label Instruction Comment Operation
LDA D000H A = First number A = 12 H
MOV E, A E = First number E = 12 H
MVI D, 00 H D = 00 H D = 00 H
LDA D001H A = Second number A = 10 H
MOV C, A Initialize counter C = 10 H
LXI H, 0000H Result = 0 H = 00H,
L = 00H
BACK: DAD D Result = result + first number HIL = HL + DE
DCR C Decrement count C=C–1
JNZ BACK If counter  0 repeat
SHLD E000H Store result E 000 H : 20 H
E 001 H : 01 H Result
HLT Terminate program execution Stop

Q.3.(a) Explain with the help of suitable example, how physical address is computed for the
instruction/ op code lying in code segment in 8086. (6)
Ans. Physical Address Generation :
Step 1: The CS register contains the upper 16 bits of the starting address of the code segment.
 CS Register : 3 4 8 A Segment base

Step 2 : The BIU will automatically insert zeros for the lowest four bits of the segment base
address to get the 20 bit physical address for the starting of code segment.
 Starting address of code segment : 3 4 8 A 0
 BIU adds this zero
Step 3 : The I.P. register contains the offset or distance from this address. The offset here is
4214H.
 I.P. Register : 4 2 1 4

Step 4 : Add the starting address of code segement (20 bit) to the offset to get the physical
address of the location containing the next code byte as follows :
Starting address of code segment  3 4 8 A 0  Hard wired 0
Offset in the I.P. Register + 4 2 1 4
Physical address of the location  3 8 A B 4
containing the next code byte
(ii) This 20 bit physical address is then sent out by the BIU to fetch the next code byte stored at
this location.
Alternative way to represent the physical address :
(i) An alternative way of representing a 20 bit physical address is as follows :
Segment base : Offset
(ii) For example the 20 bit physical address in the above example is 348 A : 4214.

Q.3.(b) Write the purpose of following flags in 8086 – Direction, interrupt, over flow. (6)
Ans. Direction Flag(DF) : This bit is specifically for string instructions. In string instruction we
use SI (source index) and DI (destination index) registers as offset registers to point source area and
destination area respectively. DF flag controls direction of SI and DI pointers.
6 Microprocessing & Interfacing

If DF = 1, the string instruction will automatically decrement the pointer(s), i.e. process string
from high addresses to low addresses, or from right to left.
If DF = 0, the string instruction will automatically increment the pointer(s), i.e. process string from
low addresses to high addresses or from left to right.
It is used with string instructions :
DF = ‘1’ - Up, DF = ‘0’ - Down
Interrupt - flag (IF) : (i) If user sets IF flag, the CPU will recognize external (maskable) interrupt
requests.
(ii) Clearing IF disables these interrupts.
(iii) IF has no effect on either non-maskable external or internally generated interrupt. The interrrupt
flag (IF) is used for allowing or prohibiting the interruption of a program.
IF = ‘1’ - Interrupt enabled, IF = ‘0’ - Interrupt disabled.
Overflow Flag (OF) : It indicates an overflow from the magnitude to the sign bit of result. If OF is
set, an arithmetic overflow has occurred; that is, a significant bit has been lost because the size of the
result exceeded the capacity of its destination location. In 8086 interrupt on overflow instruction is
available that will generate an interrupt in this situation. If result is not out of range, OF remains reset.
OF = ‘1’ - signed overflow occurred, OF = ‘0’ - no overflow.

Q.4.(a) Write the purpose of following in 8086.

(i) BHEand Ao (ii) MN / MX
(iii) LOCK (iv) TEST (2 + 1 + 1 + 1 = 5)
Ans. (i) BHE and A0 : (i) These line carries the BHE signal during T1. BHE and A0 are used
together to access a word/byte from the memory. Status line S7 is reserved for “further development”.

(ii) MN / MX : (i) This is an input signal to 8086 that indicates the processor has to work in
which mode.
(ii) If this signal is HIGH, 8086 is in Minimum mode i.e. Single-processor system.
(iii) If this signal is LOW, 8086 is in Maximum mode i.e. Multi-processor system.
(iii) LOCK : The output indicates that the other system bus master not gain control of the
system bus while LOCK is active low. The lock signal is activated by LOCK instruction and remains
active until the completion of the next instruction.
(iv) TEST : It is an active low input line dedicated for 8087 Co-processor. In minimum mode it is
connected to GND. In Maximum Mode whenever the Co-processor is busy it makes this pin HIGH. TEST
input is examined by the WAIT instruction. If the TEST pin is high, the P enters idle state; till TEST pin
becomes low i.e. 8087 is free.

Q.4.(b) Describe any five addressing modes in 8086. (10)

Ans. The 8086 microprocessor is provided with various addressing techniques called addressing
modes of 8086 are :
(i) Register Addressing
(ii) Immediate Addressing
(iii) Direct Addressing
(iv) Resister Indirect Addressing
(v) Direct Relative Addressing
B.Tech., 5th Semester, Solved papers, Dec 2010 7

(vi) Based Index Address

(vii) Relative Based Index Addressing.
The various modes have been discussed below alongwith examples.
(i) Register Addressing : In this type of addressing, the operand to be accessed is specified as
residing on one of the internal register of 8086.
The contents of CX (16 bit word), the source operand is moved to BX, the destination of operand.
In this instruction, both the source and destination operand have been specified as the consents of
external registers of 8086, i.e., CX and BX respective.
The datum is in the register that is specified by the instruction for a 16 bit operand, a register may
be AX, BX, CX, DX, SI, DI, SP or BP and for an 8 bit operand a register may be AL, AH, BL, BH,CL,CH,DL,
or DH.
Instruction Register
Register  Operand
(ii) Immediate Addressing : In this type of addressing the source operand is the part of the
instruction itself instead of the contents of any internal register or memory location. The immediate
operand can be either a byte or word of data.
Example : MOV BL, 10 H
The source operand is 10H and is an example of byte wide immediate source operand.
MOV BX, 1234 H
The source is 1234H and is an example of word wide immediate source operand.
Instruction
Operand
(iii) Direct Addressing : In this type of addressing the bit effective memory address of the
operand follows the instruction opcode. This effective address (EA) is actually an offset of the storage
location of the operand from the location specified by the current value of the DS register. The EA is
combined with the current content of DS in the 8086 to produce the actual physical address (PA) of the
operand. As an example, in the following instruction. The source operand follows the direct addressing
mode.
MOV CX, [1234]
It means “Move the contents of the memory location which is at an offset 1234 from the current
data segment, into the internal register CX”. When the instruction is executed, the 8086 combines 1234 H
with the current contents of DATA segment to get the physical address of the source operand. Let
DS = 0400H. Then, PA = 04000 + 1234 = 05234 H. So the contents of the physical address 05234 H its copied
into the internal register CX of 8086.
(iv) Register Indirect Addressing : In this mode, the effective address of the operand is not the
direct part of the instruction, but resides in either a base register or an index register within the 8086. The
base register can either be BX or base pointer register BP, and the enclose register can either be SI or DI,
i.e., source index register a destination index register.
Example : MOV. CX [SI] The EA is in the source index register.
“Move the contents of the memory location when is at on offset equal to the contents of source
index register from the current data segment, into the internal response CX”.
Let, DS = 0400H, SI = 1002H
PA = 0400 + 1002 = 05002 H
and then the contents of 05002H memory location is stored into internal register CX of 8086.
(v) Register Relative Addressing : In this type of addressing, the EA of the operand in the sum
of an 8 bit displacement and the contents of either a base register or an index register.
8 Microprocessing & Interfacing

The base register can be either BX or BP and index register can be either SI or DI. As an example,
in the following instruction the EA is the sum of source indirect displacement.
MOV AH, [SI] + DISP
i.e., EA = DI + EA + DISP
PA = DS + EA
Let, [DS] = 0400H
[SI] = 2000H and
DISP = 1234 H
PA = 04000 + 2000 + 1234 = 007234H
04000
2000
+ 1234
07234
Then as a result of the indirect on given above the contents of 07234H is copied in the AH
register, i.e., higher-byte part of register AX of 8086.

Q.4.(c) Explain the purpose of EU and BIU in 8086. (5)

Ans. BUS Interface Unit (BIU) : The BIU interface 8086 to the outside word. It provides a
full 16 bit bidirectional data bus and 20bit address bus. The BIU is responsible for performing all external
bus operations as given below :
(i) It sends address of the memory or I/O.
(ii) It fetches instruction from memory.
(iii) It reads data from port/memory.
(iv) It writes data into port/memory.
(v) It supports instruction queuing.
(vi) It provides the address location facility.
The BIU has a dedicated order. The main function of this order is to produce 20 bit physical
address. The bus control logic of the BIU generates all bus control signals such as READ and WRITE for
memory and I/O.
Execution Unit (EU) : The EU of 8086 tells the BIU from where to fetch instructions or data,
decodes instrcuction and executes instructions. It contains :
(i) Control Circuitary
(ii) Instruction Decoder
(iii) Arithmetic Logic Unit (ALU)
(iv) Flag register
(v) General purpose registers.
(vi) Pointers and Index registers.
The central circuitry in the EU directs the internal operation. A decoder in the EU translates the
instructions fetched from memory into a series of actions which the EU performs. ALU is 6 bit. If can add,
subtract, AND, OR, XOR, increment, decrements complement and shift binary numbers.

Q.5.(i) Prepare a look up table for the square of Hexadecimal digits 0 to F . Write an ALP to
obtain the square of Hexadecimal digit 3. Using XLAT instruction. (10)
Ans. Look up table should be always present in Data memory segment. Let the base address of
data memory segment is 19750 H. Let the starting address of look up table is 19756 H. The square of
hexadecimal digits 0 to F will be stored in sequence from address 19756 H as shown in Fig. is given
below :
B.Tech., 5th Semester, Solved papers, Dec 2010 9

Fig : Look up table for squares.

E. A. = 0006 BX
+ 03 AL
0009 H
So Physical address can be calculated as follows :
DS
B. A. = 1975 0
E. A. = 0009
P. A. = 19759 H
19759 09 H  09 AL
Program :
MOV AX, 1975 H
MOV DS, AX
MOV BX, 0006 H
MOV AL, 3 H
XLAT ;
HLT/INT 3

Q.5.(ii) Write a program to find cut the largest number from a given array of 8-bit numbers,
stored in the locations starting from a known address. (10)
Ans. NAME Largest number
Model small
ASSUME CS : code. DS : Data
Data
10 Microprocessing & Interfacing

LIST DB 20 H, 23 H, 18 H, 40 H1 ....
COUNT EQU OF
LARGEST DB 01 H DUP (?)
DATA ENDS
CODE SEGMENT
START : MOV AX, DATA
MOV DS, AX
MOV SI, OFFSET LIST
MOV CL, Count
MOV AL, [SI]
*** : CMP AL, [SI + 1]
JNC BELOW
MOV AL, [SI + 1]
BELOW : INC SI
DEC CL
JNZ ***
MOV SI, OFFSET LARGEST
MOV (SI), AL
MOV AH, 4CH
INT 21 H
CODE ENDS
END START.
Q.6.(a) Explain the purpose of following instructions in 8086
(i) MOVSB (ii) LOOP (iii) AAD. (6)
Ans. (i) MOVSB : This instruction copies a byte or a word from a location in the data segment to
a location in the extra segment. The offset of the source byte/word in the DS must be SI register. The offset
of the destination in ES must be in DI register. After byte or word is moved, SI and DI are automatically
adjusted to point to the next source and next destination.
(ii) LOOP : This instruction is used to repeat a series of instruction some number of times. The
number of times the instruction sequence is to be repeated is loaded into CX. Each time loop executes CX
is decremented by 1.
(iii) AAD : It converts two unpacked BCD digits in AH and AL to the equivalent binary number
in AL. This adjustment must be made before dividing the two unpacked BCD digits in AX, by an unpacked
BCD byte. After the division,
AL  unpacked BCD quotient
AH  unpacked BCD remainder.

Q.6.(b) Write the purpose of Model directive in 8086 assembly language. (4)
Ans. MODEL : It is available in MASM version 5.0 and above. This directive provides short-cuts
in defining segments. It is initializes memory model before defining any segment. The memory model can
be SMALL, MEDIUM, COMPACT or LARGE. We can choose the memory model based on our requirement
by referring following table.
Model Code segments Data segments
Small One One
Medium Multiple One
Compact One Multiple
Large Multiple Multiple
B.Tech., 5th Semester, Solved papers, Dec 2010 11

Q.6.(c) Explain the working of 8237 DMA controller. (10)

Ans. DMA Controller : DMA controller is used to transfer data. The DMA controlled data
transfer does not require software hence it is faster than microprocessor controlled data transfer. This
techniques used on any system that requires a high speed data transfer rate. e.g., C.R.T. system, Floppy
disk drive system, hard disc derive system, High speed ADC etc. DMA controller is shoen in fig.

Fig. : DMA Controller

Working of 8237 DMA Controller can be explained by following modes:

(i) Autoinitialization mode,
(ii) Priority modes,
(iii) Normal mode,
(iv) Extended write mode,
(v) Compressed timing.
(i) Autoinitialization mode : In this mode, the original values of the current address and current
word count registers are automatically restored from the base address and base word count registers of
that channel following EOP . The mask bit is not set when the channel is in autoinitialization.
(ii) Priority modes : The 8237 provides two priority modes viz. fixed priority mode and rotating
priority mode. These modes are similar to 8257 priority modes.
(iii) Normal mode : In this mode, Read( IOR and MEMR) pulse is activated during S3 and S4 and
write pulse is activated during S4 as shown in fig.(a).

Fig. (a) : Read and write pulses in normal mode. Fig. (b) : Extended write mode
12 Microprocessing & Interfacing

(iv) Extended write mode : In this mode, write( IOW and MEMW ) and read ( IOR and MEMR)
pulses are activated during S3 and S4 as shown in Fig. (b). The minimum length of DMA cycle is 3S. But one
clock cycle (S3) is wasted.

Fig. (c) : Compressed timing

Fig. (b) : Extended write mode

(v) Compressed timing : In order to achieve even greater throughput the 8237 can compress the
transfer time to two clock cycles. In extended write mode, the state S3 is wasted. In compressed time, the
8237 eliminates state S3. Hence 8237 execute only S2 and S4 as shown in fig. (c). The minimum length of
DMA cycle is 2S.

Q.7.(a) Explain the working of 8259 interrupt controller. How it handles multiple interrupts
and assigns priorities to them? (12)
Ans. 8259 A Programmable Interrupt Controller : For application where we require multiple
interrupt sources, we need to use an external device called as a priority interrupt controller (PIC).
By connecting a PIC to the microprocessor we can increase the interrupt handling capacity of
the microprocessor. 8259 A is the commonly used priority interrupt controller.
Cascade PICs System with 8085 : The 8259A can be easily interconnected to obtain multiple
interrupts fig.(b) shows 8259 A connected in cascade mode.
When 8259 A IC’s are connected in cascade, one 8259 A is configured as master while all other
8259 A’s are configured as salve.
In fig. (b) 8259-1 is in master mode and others are in slave mode.
Each slave is recognized by a number that is assigned as a part of its initialization.
The 8085 microprocessor has only one INTR input. Hence only one of 8259 A INT pin is connected
to the 8085 INTR pins.
The INT pins from other 8259s are connected to the IR inputs of the master 8259 A.
These cascaded 8259s are called as slave. The INTA signal is connected to master as well as
slave 8259 A.
The cascade pins CAS0 – CAS2 are connected from master to corresponding slave pins. For
master they function as outputs while for slave these pins function as input.
The SP / EN signal is tied high for the master. However it is grounded for all slaves.
Address for 8259 As.
For 8259 A – 1
A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 0 0 0 × = F0 or F1 H
For 8259 A – 2
A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 0 0 1 × = F2 H or F3 H
B.Tech., 5th Semester, Solved papers, Dec 2010 13

For 8259 A – 3
A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 0 1 0 × = F4 H or F5 H
Upto 8 PICs can be cascade together to act as a slave unit to master PIC. Thus, a total of 64
peripherals can be connected to the microprocessor.

Fig. (b) : 8259 A connected in cascade mode

14 Microprocessing & Interfacing

Master and slave operation : When the slave receives an interrupt signal on one of its IR inputs,
it checks the mask condition and priority of the interrupt request.
If the interrupt is unmasked and its priority is higher than any other interrupt level being serviced
in the slave, then the slave will send an INT signal to the IR input of the master.
If that IR input of the master is unmasked and if that input has higher priority than other IR inputs
currently being serviced, then the maseter will send an INT signal to 8085 INTR input.
If the INTR interrupt is enabled, the 8085 will go through its INTR interrupt procedure and sends
three INTA pulses to both the master and the slave.
In response to the first interrupt acknowledge signal the opcode for CALL instruction is available
on the data bus. The master outputs a 3 bit slave identification number on CAS0 – CAS2 lines. This
enables the slave.
When the slave receives second INTA pulse from the 8085, the slave will send the low-order
address byte of the ISR on the data bus.
Finally, the slave sends the high order byte of the ISR on the data bus on receiving third INTA
pulse.
If the interrupt signal is applied directly to one of the IR inputs of the master, the master will send
the opcode for CALL instruction to 8085 when it receives just INTA pulse from 8085. It then sends low-
order byte and high-order byte in successive interrupt acknowledge cycles.

Q.7.(b) Explain working of 8253 programmable interval timer in mode Mode 2 and
Mode 3. (8)
Ans. Mode 2 : Rate generator : This mode functions like a divide by – N counter.
(a) Normal Operation :
1. The output will be initially high.
2. The output will go low for one clock pulse before the terminal count.
3. The output then goes high, the counter reloads the initial count and the process is repeated.
4. The period from one output pulse to the next equals the number of input counts in the count
register.
(b) Gate Disable :
1. If Gate = 1 it enables a counting otherwise it disables counting (Gate = 0).
2. If Gate goes low during an low output pulse, output is set immediately high. A trigger reloads
the count and the normal sequence is repeated.
(c) New Count : The current counting sequence does not affect when the new count is written.
If a trigger is received after writing a new count but before the end of the current period, the new count will
be loaded with the new count on the text CLK pulse and counting will continue from the new count.
Otherwise, the new count will be loaded at the end of the current counting cycle.
MODE 3 : Square Wave Rate Generator
(a) Normal operation :
1. Initially output is high.
2. For even count, counter is decremented by 2 on the falling edge of each clock pulse. When the
counter reaches terminal count, the state of the output is changed and the counter is reloaded with the full
count and the whole process is repeated.
3. If the count is odd and the output is high the first clock pulse (after the count is loaded)
decrements the count by 1. Subsequent clock pulse decrement the clock by 2. After time-out, the output
goes low and the full count is reloaded. The first clock pulse (following the reload) decrements the count
by 3 and subsequent clock pulse decrement the count by two. Then the whole process is repeated. In this
way, if the count is odd, the output will be high for (n + 1)/2 counts and low for (n – 1)/2 counts.
B.Tech., 5th Semester, Solved papers, Dec 2010 15

Fig. (a) : Mode 2 rate generator.

Fig. (b) : Mode 3 : Square wave rate generator.
(b) Gate Disable : If Gate is 1 counting is enabled otherwise, it is disabled. If Gate goes low while
output is low, output is set high immediately. After this, When Gate goes high, the counter is loaded with
the initial count on the next clock pulse the sequence is repeated.
(c) New Count : The count counting sequence does not affect when the new count is written. If
a trigger is received after writing a new count but before the end of the current half-cycle of the square
wave, the counter will be loaded with the new count on the next CLK pulse and counting will continue
from the new count, otherwise, the new count will be loaded at end of the current half-cycle.
Q.8. Explain the working of 8255 PPI in
(i) BSR mode
(ii) Mode 2
(iii) Explain the setting of control register in setting the various ports as input or
output ports. (20)
Ans. Working of 8255 :
Mode 2 : In this mode group A is used as input and output i.e. for transmitting and receiving data
from peripheral through 8255 as shown in fig.(a).
The transfer of data is achieved by port C handshake signals. The group B can be in Mode 0 or
Mode 1.
The bi-directional data is transferred through port A so it consists of input and output latch.
The Mode 2 is combination of Mode 1 input and output both at a time to port A.
The interrupt signals of input and output mode are combined to generate common interrupt
signal to CPU. The internal organization of these signals is as shown in fig. (b).
The different handshake signals used are OBFA , ACK A ,STBA , IBFA and INTERA. 2 handshake
signals are used for output operation, 2 are used for input operation and one is common to both.
16 Microprocessing & Interfacing

Output operation :
OBF (Output buffer full) : This is an active low output signal generated by 8255. When CPU
writes data to output port 8255 will enable OBF signal to indicate peripheral that data is available in output
buffer.

Fig. (a) : Mode 2 interfacing Fig. (b) : PA, PB and PC in mode 2

ACK (Acknowledge) : This is an active low input signal for 8255. When the peripheral detects
OBF signal, it reads data from 8255 port and makes ACK = 0 and the ACK signal is used to acknowledge
8255 that data is read from port so 8255 will remove OBF signal to indicate output buffer is empty..
Input operation :
STB (strobe) : This is an active low input signal. When the peripheral writes data to input buffer,,
it generates a signal STB to indicate 8255 that it has written data.
IBF (Input buffer full) : When data is available in input buffer 8255 will enable IBF signal to
indicate that data is available in input buffer.
INTR (Interrupt request) : This is an output signal given by 8255 to request CPU service.
The INTR is generated in two different conditions input and output.
The interrupt is generated for input mode when IBF = 1, STB = 1 and INTE1 = 1 and for output
mode when OBF = 1, ACK = 1 and INTE2 = 1. The INTE1 and INTE2 are set/reset using BSR mode, port
C bits used are PC6 and PC4 respectively.
The logical equation will be,
INTRA = INTE1.ACK A .OBFA  INTE 2 .STBA .IBFA
The timing diagram of Mode 2 bi-directional data transfer for data transfer from peripheral to CPU
and CPU to peripheral are as shown in Fig. (c).
The mode 2 also supports both modes of data transfer i.e. Interrupt drive I/O and status driven I/
O. The port C is used as status word and its definitions are as follows :
OBFA INTE1 IBFA INTE2 INTRA x x x
B.Tech., 5th Semester, Solved papers, Dec 2010 17

Fig. ( c) : Timing diagram of mode 2

BSR mode : The BSR is a Port C bit set reset mode. The mode used eight bits of Port C only. The
individual bit of Port C can be set or reset by writing control word in the control register.
The control word format of BSR mode is as shown in Fig.(d)(i) and mode selection formal is in
fig.(d)(ii).
The pin of Port C, i.e., Bit 0 to Bit 7 to set or rest is chosen using Bit select bits b3b2b1, i.e., D3, D2
and D1, of control word register. The bit to set or reset is decided by bit S/R, i.e., D0. The BSR mode affects
only one bit of Port C at a time. The bit set using BSR mode remains set unless and until you change the
bit. The bit to be set/reset is decided by control word. So to set any bit of Port C, bit pattern is loaded in
control register. Even though a BSR mode is selected it will not affect I/O mode.
D7 D6 D5 D4 D3 D2 D1 D0
0 X X X b3 b2 b1 S/R

Mode Mode Port C Port C bit

Bit select
b3 b2 b1 Set/Reset
0 0 0 Bit 0 1 = Set
0 0 1 Bit 1 0 = Reset
0 1 0 Bit 2
0 1 1 Bit 3
1 0 0 Bit 4
1 0 1 Bit 5
1 1 0 Bit 6
1 1 1 Bit 7

Fig : (d)(i )
18 Microprocessing & Interfacing

Control Word :
D7 D6 D5 D4 D3 D2 D1 D0
I/O
I/O Mode

BSR Mode Mode 0 Mode 1 Mode 2

(bit Set Reset) Simple I/O Handshake I/O Bidirectional data
For Port C for ports for ports A and or B bus for port A
No effect on A, B and C Port C bits are used Port B : either in mode
I/O mode for handshake 0 or 1 Port C bits are
used for handshake

Fig : (d)(ii)
I/O Modes : There are three I/O modes of operation :
(1) mode 0 – Basic I/O
(2) Mode 1 – Strobed I/O
(3) Mode 2 – Bi-directional I/O
The I/O modes are programmed using control register. The control word format of I/O modes is as
shown in fig.(e).

Fig. (e) : I/O modes control word format

Function of each bit is as follows :

(i) D7 : When the bit D7 = 1 then I/O mode is selected, if D7 = 0 then BSR mode is
selected . The function of bits D0 to D6 is dependent on mode (I/O mode or
BSR mode).
(ii) D6 and D5 : In I/O mode the bits D6 and D5 specifies the different I/O modes for group
A i.e. Mode 0, Mode 1 and Mode 2 for port A and port C upper.
B.Tech., 5th Semester, Solved papers, Dec 2010 19

(iii) D4 and D3 : In I/O mode the bits D4 and D3 selects the port function for group A. If these
bits = 1 the respective port specified is used as input port. But if bit = 0, the
port is used as output port.
(iv) D2 : In I/O mode the bit D2 specifies the different I/O modes for group B i.e. Mode
0 and Mode 1 for port B and port C lower.
(v) D1 and D0 : In I/O mode the bits D1 and D0 selects the port function for group B. If these
bits = 1 respective port specified is used as input port. But if bit = 0, the
port is used as output port.
From the above explanation you can observe that all the 3 modes i.e. Mode 0, Mode 1 and Mode
2 are only for group A ports, but for group B only 2 modes i.e. Mode 0 and Mode 1 are provided.
When 8255 is reset, it will clear control word register contents and all the ports are set to input
mode. The ports of 8255 can be programmed for other modes by sending appropriate bit pattern to control
register.