60 Microprocessing & Interfacing

MICROPROCESSING & INTERFACING

Dec 2013
Paper Code: EE-309-F
Figures in the bracket indicate full marks.

Note: Attempt five questions in total selecting one question from each of the four Units.
Question No.1 is compulsory.
Q.1.(i) Why AD0 – AD7 lines multiplexed in 8085. (4)
Ans. These are input/output, tristate signals having two set of signals. They are address
and data. The lower order 8 bits, of 16 bit address is multiplexed or time shared with data bus.
They are demultiplexed with the help of ALE signal. During the earlier part it is used as lower
order address and in later part it is used as data bus. The address and data buses are multiplexed
to reduce the number of pins of the chip.

Q.1.(ii) Write a Program to find 1’s complement of the number. (4)

Ans. Statement : Find the 1’s complement of the number stored
at memory location 2200H and store the complemented number at Flowchart
memory location 2300H. Start
Sample Problem :
(2200H) = 55H Get the number
Result = (2300H) = A AH
Program Complicated the number
LDA 2200H  Get the number
CMA  Complement number
Store the result
STA 2300H  STore the result
HLT  Terminate program execution.
End

Q.1.(iii) What is Pipelining ? How does this occur. (4)

Ans. The process of fetching the next instruction, when the present instruction is being
executed is called as pipelining.
Pipelining has become possible due to the use of queue. BIU fills in the queue, until the
entire queue is full. BIU restarts filling in the queue when atleast two locations of queue are
vaccant. The EU always reads the next instruction byte from the que in BIU. This is much faster
than sending out an address to the memory and wainting for the next instruction byte to come. In
short pipelining eliminates the waiting time of EU and speeds up the procesing .
Q.1.(iv) What is wrong with a MOV Instruction ? (4)
Ans. The MOV instruction cannot :
(i) set the value of he CS and IP registers.
(ii) copy value of one segment register to another segment register (should copy to
general register first).
(iii) copy immediate value to segment register (should copy to general register first).
B.Tech., 5th Semester, Solved papers, Dec 2013 61

(iv) any move to or from the flag register

(v) any move where the operands are not the same size
(vi) a move of several objects
Q.1.(v) Explain following instructions with example. (4)
(a) SPHL (b) XTHL (c) RET (d) IN address
Ans. (a) SPHL :
Description : Load stack pointer with HL reg. pair contents.
When this instructon is excuted the contents to high order 8 bits and L register contents
olow order 8 bits. The contents of H and L are not altered.
Operation : HL  SP
Example : SHPL
Suppose HL pair = ABCD, Stack pointer = 1234 and SPHL instruction is executed.
(b) XTHL :
Description : Exchange HL with top of stack.
When this instruction is executed the contents of L register are exchanged with the
stack location pointed by the stack pointer. The contents of H register are exchanged with the
next stack location (SP + 1). The contents of the stack pointer register are not altered.
Operation : L  (SP), H  (SP + 1)
Example : XTHL
Suppose H = 01, L = 20, SP = FFFD and at memory location FFFD = 05 and FFFE = 09
is stored and XTHL instruction is executed.
(c) RET :
Description : Return from subroutine.
When this instruction is executed program sequence is transferred from the subroutine
to the calling program. The return address is taken from stack (where the call instruction has
stored its PC contents i.e., return address) this address is loaded in PC and the program execution
begins at address taken from stack.
Operation : (SP + 1)  PCH
(SP)  PCL, SP + 2  SP
Example : RET
Suppose the CALL C200 instruction is written at C006 and is executed by microprocessor.
The microprocessor will call the subroutine. It will store the return address at C7FE and C7FD,
starts executing instructions from C200 onwards. A C209 RET instruction is present. When
RET instruction is executed by microprocessor, it will take return address from stack (C7FD and
C7FE) and load in program counter. So the next instruction executed will be from C009.
(d) IN address :
Description : Input data to accumulator from a port with 8 bit address.
This instruction takes data from input port and stores in accumulator. The address of
port is 8 bits and is specified along with the instruction. The 8 bit address bits are transferred on
A0–A7 and A8–A15 and a port is accessed. Any one set of address lines used to detect and
enable the port. The range of addresses will be 00 to FF.
Operation : (port address)  A
62 Microprocessing & Interfacing

Example : IN 20 H (20 H is the port address)

When IN 20 instruction is executed, the microprocessor reads data from input port. The
address of input port is given with the instruction i.e., 20 H. The data is read from input port and
copied accumulator.

Section-A
Q.2.(i) Explain Pin diagram of 8085 microprocessor. (10)
Ans. Refer Q.2.(a) of paper Dec 2014.

Q.2.(ii) Write a Program to calculate the sum of the series of even

numbers. (10)
Ans. Program statement : Write a program in the ALP of 8085 to calculate the sum of
series of even numbers. Assume that the length of the series is stored at memory location
D000 H and the series itself begins at memory location D001 H. Store the result at memory
location E000 H. Draw flowchart.
Explanation :
(i) Initialize the sum to zero. Load the count of numbers in register C. Initialize pointer
to start of series.
(ii) To check whether the number is even we will AND the number with 01 H. If the
result of ANDing is zero it indicates that the number is even. We will add this even number to the
initialised sum.
(iii) Decrement count. Increment source pointer to next location. Continue the process
till sum of all even numbers is found. Store the sum at memory location E000 H.
Program :
Label Instruction Comment
LDA D000H
MOV C,A Initialize counter
MVI B,00 H sum = 0
LXI H,D001 H Initialize pointer
Back : MOV A,M Get the number
ANI 01 H Mask Bit 1 to Bit 7
JNZ SKIP Don’t add if number is ODD
MOV A,B Get the sum
ADD M SUM = SUM + data
MOV B, A Store result in B register
SKIP : INX H Increment pointer
DCR C Decrement cointer
JNZ BACK If counter  0 repeat
STA E000H Store sum (Result)
HLT Terminate program execution
B.Tech., 5th Semester, Solved papers, Dec 2013 63

Fig. : Flow chart

Q.3.(i) What is the functioning of timing and control unit in 8085 microprocessor?
Discuss all its signals in detail. (10)
Ans. Timing and Control : This is a control section of 8085 made up of synchronous
sequential ogic circuit. It controls all internal and external circuits in the microprocessor system.
It operates with reference to clock signal. It accepts information from instruction decoder and
generates microsteps to perform it. In addition to this, the block accepts clock inputs, performs
sequencing and synchronising operations. The synchronization is required for communication
between microprocessor and peripheral devices. Fig. shows the control section of microprocessor.
The contents of the instruction register are in the form of 0’s and 1’s. They are converted
to meaningful form by the decoding network called matrices. The control matrix provides internal
signals for controlling operation and data between registers. The control unit also generates
timing signals essential for microprocessor to operate. The microprocessor uses a quartz crystal
64 Microprocessing & Interfacing

(LC or RC circuit) to determine the clock frequency, so that other timing and control signals are
developed. The speed of microprocessor is directly proportional to the speed of the crystal. The
clock speed and access time must be compatible for maximum performance. To implement this
it uses different status and control signals.
Control and status signals :
(a) ALE (Address Latch Enable) : We
know that AD0 to AD7 lines are multiplexed and
the lower half of the address is also necesarry
during T 2 and T3 of machine cycle to access
specific location in memory or I/O port. This
means that the lower half of an address must
be latched in T1 of the machine cycle, so that it
is available throughout the machine cycle. The
latching of lower half of an address is done by
external latch and ALE signal from 8085.
(b) RD and WR : These signals are
basically used to control the direction of the
direction of the data flow between processor Fig. : Control section of microprocessor
and memory or I/O device/port. A low on RD
indicates that the data must be read from the selected memory location or I/O port via data bus.
A low on WR indicates that the data must be written into the selected memory location or I/O
port via data bus.
(c) IO/ M , S0 and S1 : IO/ M indicates whether I/O operation or memory operation is
being carried out. S1 and S0 indicate the type of machine cycle in progress.
(d) Ready : It is used by the microprocessor to sense whether a peripheral is ready or
not for data transfer. If not, the processor waits. It is thus used to synchronize slower peripherals
to the microprocessor. If peripherals are fast enough it is tied to VCC. If it is left open, 8085 enters
in the wait state.

Q.3.(ii) Differentiate between vectored and Non-vectored interrupt. Also explain

interrupt structure with proper diagram. (10)
Ans. Vectored interrupt : In the vecotored interrupt, the branch address is supplied by
the external device which interrupts the microprocessor.
Non Vectored interrupt : In the non vectored interrupt, the branch address is assigned
to fixed location.
Interrupt structure : While executing the main program, the microprocessor can be
interrupted to perform some specific operation. This specific operation can be performed by
calling a subroutine also called interrupt service routine (ISR). Aftering completing this specific
task, microprocessor returns to the main program. The sequence of interrupt operation is explained
with the flow chart as shown in figure.
B.Tech., 5th Semester, Solved papers, Dec 2013 65

Fig. : Interrupt structure

Section-B
Q.4.(i) Explain various addressing modes of 8086 microprocessor. (10)
Ans. Refer Q.4.(a) of paper Dec 2012.
Q.4.(ii) If the first instruction of a program is to be fetched from 12340H. What
should the value of CS register be ? The sixth instruction to be fetched is at memory
location 1234FH. What should be the value of Ip register ? (10)
(Hint : Assume Ip to be 000H for first part)
Ans. Value of code segment (CS) register be 1234 H.
Value of instruction pointer (IP) will be 000F H.
Q.5.(i) Explain the block diagram of 8086 microprocessor. (10)
Ans. Block Diagram of 8086 : The block diagram of 8086 microprocessor is shown in
figure. As shown in block diagram, the 8086 is divided into two independent functional units. The
Bus interface Unit (BIU) and the Execution.
(i) The Bus Interface Unit : The Bus Interface unit fetches instructions from memory,
reads data from ports and memory and writes data to ports and memory. It handles all transfers
of data and addresses on the buses for the execution unit. The Bus interface Unit consists of the
following :
(a) Instruction Queue (b) Segment Registers (c) Instruction Pointer
(a) Instruction Queue : The instruction queue is a first-in-first-out group of registers.
To speed up program execution, the Bus Interface Unit fetches as many as six instruction bytes
66 Microprocessing & Interfacing

are held for the Execution Unit in a Instruction Queue. The BIU can be fetching instruction
bytes while the Execution Unit (EU) is decoding the instruction or executing an instruction which
does not require use of the buses. When the Execution Unit is ready for its next instruction, it
simply reads the instruction from the Instruction Queue in the BIU. This scheme is much faster
than sending out an address to memory and then waiting for memory to send sack the next
instruction byte. The prefetch instruction and queue scheme greatly speeds up processing. The
arrangement of fetching the next instruction while the current instruction executes is called pipe
lining.

Fig. : Block diagram of 8086 microprocessor

(b) Segment Registers : The Big Interface Unit (BIU) contains four 16 bit segment
registers. They are :
– Code Segment Register (CS)
– Stock Segment Register (SS)
– Extra Segment Register (ES)
– Data Segment Register (DS)
(c) Instruction Pointer : The instruction pointer register is a 16 bit register which holds
the address of the next code byte that is to be fetched within the code segment. This register
B.Tech., 5th Semester, Solved papers, Dec 2013 67

contains the address value which is an offset, because this value must be added to the segment
base address contained in CS register to produce the required 20 bit physical address.
(ii) The Execution Unit : The execution unit of 8086 performs the following major
operations :
– It tells the BIU, from where to fetch instructions or data.
– It decodes and executes instructions.
To perform the above operations, the execution unit consists of the following sections :
(a) Instruction Decoder, ALU and control circuitry.
(b) Flag Register
(c) General Purpose Registers
(d) Stack Pointer Register
(e) Other Pointer and Index Registers
(a) Instruction decoder, ALU and control circuitry : The instruction decoder in the
EU translate instructions fetched from memory into a series of actions which are further carried
out. The Airthmetic and Logic Unit (ALU) of 8086 is of 16 bits which can add, subtract, AND,
OR, XOR, increment, decrement, complement or shift the binary numbers. All internal operations
of EU are controlled by control circuitry.
(b) Flag register : 8086 microprocessor contains one 16 bit flag register (status register).
A flag register is a flip flop which indicates the status of some conditions produced by the
execution of an instruction or controls certain operations of the Execution Unit. In a 16 bit flag
register, there are nine active flags. Six of the nine flag bits are used to indicate some conditions
produced by an instructions. These six flags are called status flag (conditional flags). The remaining
three flag bits in the flag register are used to control certain operations of the processor and are
called control flags.
(c) General purpose registers : The execution unit 8086 contains eight general purpose
registers labelled as AH, AL, BH, BL, CH, CL, DH and DL in the fig. below.

Fig. : 8086 general purpose register

(d) Stack pointer register : The stack pointer register SP is a 16 bit register which
contains the 16 bit offset address from the start of the stack segment to the memory location
where a word was most recently stored on the stack. The stack memory location where a word
was mostrecently stored is called top of the stack.
(e) Other pointer and index registers : In addition to the stack pointer register SP, the
EU of the 8086 also contains a 16 bit base pointer register BR The base pointer register BP
contains the 16 bit offset address relative to the stack segment register SS but it is employed in
the based addressing mode of 8086.

Q.5.(ii) How Physical address is computated in 8086 microprocessor ? (10)

Ans. Refer Q.5.(a) of paper Dec 2011.
68 Microprocessing & Interfacing

Section-C
Q.6.(i) Explain directives used in assembly language program ? Why are segment
directives used. (10)
Ans. Directives used in assembly language program are as follows :
Directive Action
ALIGN aligns next variable or instruction to byte which is multiple of operand.
ASSUME selects segment register(s) to be the default for all symbol in segment(s)
COMMENT indicates a comment
DB allocates and optionally intializes bytes of storage
DW allocates and optionally intializes doublewords of storage
DD allocates and optionally initializes doublewords of storage
DQ allocates and optionally initializes quadwords of storage
DT allocates and optionally initializes 10-byte long storage units
END terminates assembly; optionally indicates program entry point
ENDM terminates a macro defination
ENDP marks end of procedure definition
ENDS marks end of segment or structure
EQU assigns expression to name
EVEN aligns next variable or instruction to even byte
ESITM terminates macro expansion
EXTRN indicates externally defined symbols
LABEL creates a new label with specified type and current location counter
LOCAL declares local variables in macro definition
MACRO starts macro definition
MODEL specifies mode for asssembling the program
ORG sets location counter to argument
PAGE sets length and width of program listing; generates page break
PROG starts procedure definition
PTR assigns a specific type to a variable or to a label
PUBLIC identifies symbols to be visible outside module
TITLE defines the program listing title
SEGMENT directive : An assembly program in .EXE format consists of one or more
segments. The art of these segment are defined by SEGMENT directive and the ENDS statement
indicates the end of the segment.
Format : name SEGMENT [options] ; Begin segment
. .
name ENDS ; End segment
Example : CODE SEGMENT End segement
.
.
CODE ENDS
B.Tech., 5th Semester, Solved papers, Dec 2013 69

Q.6.(ii) Write a simply assembly program to subtract two memory locations,

where each memory location is one byte wide. (10)
Ans. Assembly program :
Instruction Comments
LDA 4201 H ; Content of 4201 H loaded into Accumulator
MOV B, A ; Content of A copied to B register
LDA 4200 H ; Get the minuend in A register
MVI C, 00 H ; Clear C register to account for sign
SUB B ; Get the difference in A register
JNC AHEAD ; if CF = 0 then go the AHEAD
CMA ; Complement Accumulator
ADI 01 H ; 2’s complement of difference in A
AHEAD : STA 4202 H ; Store the result in memory
MOV A, C ;
STA 4203 H ; Store the sign bit in memory
HLT ; Halt program
End
Sample data :
Input data : Minuend = 5 EH
Subtrahend = 34H
Output data : Difference = 2AH
Sign Bit = 00H
Memory Address Content
4200 5EH
4201 34H
4202 2AH
4203 00H

Q.7.(i) Explain NOP and HLT instructions (10)

Ans. NOP instruction :
Mnemonic NOP Flags : It does not affect any flag.
NOP : No operation
Algorithm Do nothing
Addr. Mode Implied addressing mode
Operation The execution of this instruction causes the CPU to do nothing.
(i) This instruction causes the CPU to do nothing.This instruction
uses three clock cycles and increments the instruction pointer to
point to the next instruction.
(ii) It can be used to increase the delay of a delay loop.
HLT (Halt until interrupt or reset) Instruction :
Mnemonic Halt processing Flags : No flags are affected.
70 Microprocessing & Interfacing

Operation (i) The HLT instruction will cause the 8086 to stop fetching and
executing instructions. The 8086 enters into a half state. To
come out of the halt state, there are 3 ways given below.
(a) Interrupt signal on INTR pin, (b) Interrupt signal on NMI pin
(c) Reset signal on reset pin.
(ii) It may be used as an alternative to an endless software loop in
situations where a program must wait for an interrupt.

Q.7.(ii) Write a 8086 assembly language program to find largest number in a

data array. (10)
Ans. Program :
0201 BE, 00, 03 MOV SI, 0300H MEMORY ADDRESS IN SI
0204 8B, 0C MOV CX, [SI] COUNT IN CX
0206 B8, 00, 00 MOV AX, 0000 INITIAL VALUE 0000 FOR COMPARISON
0209 46 BCK INC SI INCREMENT SI
020A 46 INC SI INCREMENT SI
020B 3B, 04 CMP, AX, [SI] COMPARE PREVIOUS MAX. WITH
NEXT NUMBER
020D 73, 02 JAE GO JUMP IF NUMBER IN AX IS
GREATER
020F 8B, 04 MOV AX, [SI] SAVE NEW LARGER NUMBER IN AX
0211 E2, F6 GO LOOP BCK JUMP UNTIL CX = 0
0213 A3, 51, 03 MOV [0351], AX STORE LARGEST NUMBER IN
MEMORY
0216 CC INT 3 BREAKPOINT

Section-D
Q.8.(i) Explain Pin diagram of 8237 DMA controller. (10)
Ans. Refer Q.9.(a) of paper Dec 2014.

Q.8.(ii) Explain BSR and I/O modes of 8255 PPI chip. (10)
Ans. BSR Mode : The BSR mode is a port C bit set/reset mode. The individual bit of
port C can be set or reset by writing control word in the control register. The control word format
of BSR mode is shown in fig.
The pin of port C is selected using bit select bits [b b b] and set or reset is decided by bit
S/R. The BSR mode affects only one bit of port C at a time. The bit set using BSR mode remains
set unless and until you change the bit. So to set any bit of port C, bit pattern is loaded in control
register. If a BSR mode is selected it will not affect I/O mode.
B.Tech., 5th Semester, Solved papers, Dec 2013 71

Fig. : BSR control word format

I/O modes of 8255 PPI chip : I/O modes of 8255 PPI chip are as follows :
(i) Mode-0 operation : In the mode-0, the 8255 can be programmed as simple input or
output. Each of the four ports, port A, port B, port CU (upper) and port CL (Lower) of 8255 can
be programmed to be either an input port or an output port. Data is written into or read from the
specific port. The input/output features of 8255 in the mode-0 are :
– Two 8 bit ports and two bit ports
– Any port can be an input port or an output port.
– Outputs are latched where as inputs are not latched.
– Ports do not have handshake or interrupt capability.
(ii) Mode-1 Operation : In the mode-1 operation of 8255, the handshake signals are
exchanges betweeen the microprocessor and peripherals prior to data transfer. The features of
this mode are :
– Two ports, port A and port B can function as 8 bit I/O ports. Port A and port B can be
configured either as input port or output port.
– Each port (port A and port B) uses three lines from port C as handshake signals. The
remaining two lines of port C can be used for simple I/O functions.
– Interrupt logic is supported.
– Both inputs and outputs are latched.
(iii) Mode-2 operation : In this mode, the port A can be used as a bidirectional port and
port B can be used either in mode 0 and 1 operation. Port A uses five signals from port C as
handshake signals for data transfer. The remaining three signals of port C can be used either as
simple I/O function or as handshake signals for port B. The mode-2 operation is generally used
for bidirectional data transfer. Data transfer between two computers can be accomplished using
8255 programmable peripheral interface in mode-2 operation.
72 Microprocessing & Interfacing

Q.9 Explain (Any two) :

(i) Instruction register and Priority Resolver.
(ii) 8259-A Programmable interrupt controller.
(iii) 8253/8254 programmable Interval time. (20)
Ans. (i) Instruction Register : This register is not accessible to the user. The instruction
register holds the opcode of the instruction that is decoded and executed.
The opcode is further sent to the instructoion decoder to select one of the 256 alternavitves
(operations). The contents of the instructoin decoder are in the form of 0’s and 1’s.

Priority resolver : It determines the priorities of the bit set in the IRR. To make
decision, the priority resolver looks at the ISR. If the higher priority bit in the InSR is set then it
ignores the new request. If the priority resolvers finds that the new interrupt has a higher priority
than the highest priority interrupt currently being serviced and the new interrupt is not in service,
then it will set appropriate bit in the InSR and send the INT signal to the microprocessor for new
interrupt request.

Ans. (ii) 8259-A Programmable interrupt controller : Refer Q.2.(a) of paper Dec
2012.

Ans. (iii) 8253/8254 programmable Interval timer : The 8253/8354 is an intelligent

Programmable Interval Timer/Counter (PIT). It is available in 24-pin DIP package using nMOS
technology and operates with +5V power supply. It has three 16-bit presettable down counters.
Each of the 3-counters can operate either in binary or BCD mode. Each counter has 2-inputs :
Clock (CLK) and Gate (GATE) and one Output (OUT). Various functions of the 8253/8254 are
as follows :
(i) As event counter,
(ii) As programmable rate generator,
(iii) As binary rate multiplier,
(iv) As digital mono shot,
(v) As complex motor controller.
Pinout and Block Diagram : The pin outs and its internal details in the form of block
diagram is shown in fig.(a) and fig.(b) respectively. Each one of the 3-counters of the 8253 is
capable of counting from DC to 2 MHz. The input clock is fed to its CLK terminal with the
frequency < 2 MHz. The funcitons of the GATE and OUT terminals depends on the mode and
setting of the particular counter.
B.Tech., 5th Semester, Solved papers, Dec 2013 73

Fig.(a) : Pinouts of 8253

The 8254 has exactly the same pinout as that of the 8253. But the 8254 differs from that
of the 8253 in 2 ways, namely,
(i) no read back  Once the particular counter of the 8253 is programmed, its status
can not be read back.
(ii) The maximum clock frequency it can count is limited to 2 MHz. The upper limit of
clock frequency of 8254 is 8 MHz and that of the 8254-2 is 10 MHz.

Fig.(b) : Block diagram of 8253/8254 programmable interval timer

74 Microprocessing & Interfacing

– Electrical characteristics : The access time of the 8254 is 200ns where as the
access time of the 8254-2 is 175ns. The GATE and CLK inputs present 10 A load and OUT
output can source 400 A in the high state and sink 2 mA in the low state.
– Data bus buffer : The 8-bit tri-state data buffer has 3-basic functions :
(a) Programming different modes of the 8253/8254,
(b) Loading the count register, and
(c) Reading the count value.
– Read/write control logic : The 8253/8254 has 5-signals, namely, CS , A0, A1, RD ,
WR . The functions of these control signals are :
(a) RD (Read Bar) : A low on this pin informs the 8253/8254 that the P is ready to
accept data in the form count value.
(b) WR (Write Bar) : A low on this pin informs the 8253/8254 that the P is ready to
output data in the form of mode informations or data.
Hence, in the isolated I/O mode, RD and WR are directly connected to IOR and
IOW . On the other hand, in the memory mapped I/O, RD and WR are connected to MEMR
and MEMW respectively..
(c) CS (Chip select Bar) : The 8253/8254 is selected only when a low (0) is applied at
this terminal. No reading or writing operations will be performed by or on the 8253/8254 unless
this chip is selected. The CS = 1 does effect the operation of the counters.
(d) A1 A0 (Address Pin) : These lines (A1 A0) are connected to the address bus. The
function of A1 and A0 are to select any one of the three counters and the control word register of
8253/8254 is indicated in below table :
Table : Selection of counter and CWR
A1 A0 Selection of counter
0 0 Counter-0 Selected
0 1 Counter-1 Selected
1 0 Counter-2 Selected
1 1 Control word register selected (CWR)
– Control word Register : As indicated in above table, the control word register is
selected only when A1A0 = 11. It is loaded with the formation of the control word to indicate
which particular counter is to be used in which mode and whether READ and WRITE operation
is to be performed.