TMS320LF/LC240xA

DSP Controllers
Reference Guide

System and Peripherals

Literature Number: SPRU357C

Revised May 2006
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 Preface

  

About This Manual

This reference guide describes the architecture, system hardware, peripher-
als, and general operation of the TMS320Lx2407A/x2406A/x2404A/x2403A/
x2402A/x2401A digital signal processor (DSP) controllers. This book is also
applicable to TMS320Lx2407/2406/2402 and future derivatives of the 240x
family.
For a description of the CPU, assembly language instructions, and XDS510
emulator, refer to TMS320F/C24x DSP Controllers Reference Guide: CPU
and Instruction Set (literature number SPRU160). This reference guide should
be used in conjunction with SPRU160.

Notational Conventions
This document uses the following conventions:

Program listings, program examples, and interactive displays are shown

in a special typeface similar to a typewriter’s. Examples use a bold
version of the special typeface for emphasis; interactive displays use a
bold version of the special typeface to distinguish commands that you
enter from items that the system displays (such as prompts, command
output, error messages, etc.).
Here is a sample program listing:
0011 0005 0001 .field 1, 2
0012 0005 0003 .field 3, 4
0013 0005 0006 .field 6, 3
0014 0006 .even

Here is an example of a system prompt and a command that you might

enter:
C: csr −a /user/ti/simuboard/utilities

Read This First iii

Notational Conventions

In syntax descriptions, the instruction, command, or directive is in a bold

typeface and parameters are in an italic typeface. Portions of a syntax that
are in bold should be entered as shown; portions of a syntax that are in
italics describe the type of information that should be entered. Here is an
example of a directive syntax:

.asect ”section name”, address

.asect is the directive. This directive has two parameters, indicated by sec-
tion name and address. When you use .asect, the first parameter must be
an actual section name, enclosed in double quotes; the second parameter
must be an address.

Square brackets [ ] identify an optional parameter. If you use an optional

parameter, you specify the information within the brackets; you don’t enter
the brackets themselves. Here’s an example of an instruction that has an
optional parameter:

LACC 16-bit constant [, shift]

The LACC instruction has two parameters. The first parameter, 16-bit con-
stant, is required. The second parameter, shift, is optional. As this syntax
shows, if you use the optional second parameter, you must precede it with
a comma.

Square brackets are also used as part of the pathname specification for
VMS pathnames; in this case, the brackets are actually part of the path-
name (they are not optional).

Braces { } indicate a list. The symbol | (read as or) separates items with-
in the list. Here’s an example of a list:

{ * | *+ | *− }

This provides three choices: *, *+, or *−.

Unless the list is enclosed in square brackets, you must choose one item
from the list.

Some directives can have a varying number of parameters. For example,

the .byte directive can have up to 100 parameters. The syntax for this di-
rective is:

.byte value1 [, ... , valuen ]

This syntax shows that .byte must have at least one value parameter, but
you have the option of supplying additional value parameters, separated
by commas.

iv
 Related Documentation From Texas Instruments

Information About Cautions and Warnings

This document may contain cautions.

This is an example of a caution statement.

A caution statement describes a situation that could potentially
damage your software or equipment.

Related Documentation From Texas Instruments

The following books describe the C24x and related support tools. To obtain a
copy of any of these TI documents, call the Texas Instruments Literature Re-
sponse Center at (800) 477-8924. When ordering, please identify the book by
its title and literature number. Many of these documents are located on the In-
ternet at http://www.ti.com.

TMS320C24x DSP Controllers CPU and Instruction Set Reference Guide

(literature number SPRU160) describes the TMS320C24x 16-bit
fixed-point digital signal processor controller. Covered are its
architecture, internal register structure, data and program addressing,
and instruction set. Also includes instruction set comparisons and design
considerations for using the XDS510 emulator.

TMS320LF2407, TMS320LF2406, TMS320LF2402 DSP Controllers

(literature number SPRS094) data sheet contains the electrical and
timing specifications for these devices, as well as signal descriptions and
pinouts for all of the available packages.

TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A,

TMS320LC2406A, TMS320LC2404A, TMS320LC2402A DSP
Controllers (literature number SPRS145) data sheet contains the
electrical and timing specifications for these devices, as well as signal
descriptions and pinouts for all of the available packages.

TMS320LF2401A, TMS320LC2401A DSP Controllers (literature number

SPRS161) data sheet contains the electrical and timing specifications for
these devices, as well as signal descriptions and pinouts for available
packages.

Read This First v

Related Documentation From Texas Instruments

TMS320C1x/C2x/C2xx/C5x Code Generation Tools Release 6.60 Getting

Started Guide (literature number SPRU121) describes how to install the
TMS320C1x, TMS320C2x, TMS320C2xx, and TMS320C5x assembly
language tools and the C compiler for the C1x, C2x, C2xx, and C5x de-
vices. The installations for MS-DOS, OS/2, SunOS, and Solaris
systems are covered.
TMS320C1x/C2x/C2xx/C5x Assembly Language Tools User’s Guide (lit-
erature number SPRU018) describes the assembly language tools (as-
sembler, linker, and other tools used to develop assembly language
code), assembler directives, macros, common object file format, and
symbolic debugging directives for the C1x, C2x, C2xx, and C5x genera-
tions of devices.
TMS320C2x/C2xx/C5x Optimizing C Compiler User’s Guide (literature
number SPRU024) describes the C2x/C2xx/C5x C compiler. This C
compiler accepts ANSI standard C source code and produces TMS320
assembly language source code for the C2x, C2xx, and C5x generations
of devices.

XDS51x Emulator Installation Guide (literature number SPNU070)

describes the installation of the XDS510, XDS510PP, and
XDS510WS emulator controllers. The installation of the XDS511
emulator is also described.

JTAG/MPSD Emulation Technical Reference (literature number SPDU079)

provides the design requirements of the XDS510 emulator controller,
discusses JTAG designs (based on the IEEE 1149.1 standard), and
modular port scan device (MPSD) designs.

Code Composer Studio User’s Guide (literature number SPRU328) ex-

plains how to use the Code Composer Studio development environ-
ment to build and debug embedded real-time DSP applications.

vi
 Trademarks

Trademarks
320 Hotline On-line is a trademark of Texas Instruments.
cDSP is a trademark of Texas Instruments.
Code Composer Studio is a trademark of Texas Instruments.
HP-UX is a trademark of Hewlett-Packard Company.
MS-DOS is a registered trademark of Microsoft Corporation.
OS/2 is a trademark of International Business Machines Corporation.
PC is a trademark of International Business Machines Corporation.
PC-DOS is a trademark of International Business Machines Corporation.
Solaris is a trademark of Sun Microsystems, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
TMS320 is a trademark of Texas Instruments.
TMS320C24x is a trademark of Texas Instruments.
Windows is a registered trademark of Microsoft Corporation.
XDS is a trademark of Texas Instruments.
XDS510 is a trademark of Texas Instruments.
XDS510PP is a trademark of Texas Instruments.
XDS510WS is a trademark of Texas Instruments.
XDS511 is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

Read This First vii

viii
 Contents

 

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Summarizes the TMS320 family of products. Introduces the TMS320x240xA DSP controllers
and lists their key features.
1.1 TMS320 Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 TMS320C240xA Series of DSP Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.4 New Features in 240xA Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.5 240xA Highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

2 System Configuration and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Describes the system configuration. interrupts, and how the peripheral interrupt expansion
(PIE) is used to increase interrupt requests capacity.
2.1 Architecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.1 System Control and Status Registers 1 and 2 (SCSR1, SCSR2) . . . . . . . . . . . 2-3
2.2.2 Device Identification Number Register (DINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.3 Interrupt Priority and Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.4 Peripheral Interrupt Expansion (PIE) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.4.1 Interrupt Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.4.2 Interrupt Request Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.4.3 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.5 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.5.1 Phantom Interrupt Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.5.2 Software Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.5.3 Nonmaskable Interrupt (NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.6 Interrupt Operation Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.7 Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.8 Sample ISR Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.9 CPU Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.9.1 Interrupt Flag Register (IFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.9.2 Interrupt Mask Register (IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2.10 Peripheral Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.10.1 Peripheral Interrupt Vector Register (PIVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.10.2 Peripheral Interrupt Request Registers (PIRQR0, 1, 2) . . . . . . . . . . . . . . . . . . 2-31
2.10.3 Peripheral Interrupt Acknowledge Registers (PIACKR0, 1, 2) . . . . . . . . . . . . . 2-34

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Contents

2.11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

2.12 Illegal Address Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
2.13 External Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
2.13.1 External Interrupt 1 Control Register (XINT1CR) . . . . . . . . . . . . . . . . . . . . . . . . 2-39
2.13.2 External Interrupt 2 Control Register (XINT2CR) . . . . . . . . . . . . . . . . . . . . . . . . 2-40
3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Describes the RAM, ROM, and Flash availability on the 240xA devices.
3.1 On-Chip RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.1.1 Dual-Access On-Chip RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.1.2 Single-Access On-Chip Program/Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Factory Masked On-Chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3.1 Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3.2 Flash Control Mode Register (FCMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3.3 Flash Control Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.3.4 Flash Programming at Variable Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4 Overview of Memory and I/O Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.5 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.5.1 Program Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.6 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.6.1 Global Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.7 I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.8 XMIF Qualifier Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.9 Program and Data Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.10 I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.11 Wait-State Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.11.1 Generating Wait States With the READY Signal . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.11.2 Generating Wait States With the 2407A Wait-State Generator . . . . . . . . . . . 3-17
4 Clocks and Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Describes the PLL, CPU, and watchdog (WD) timer clocks.
4.1 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2.3 PLL-Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.3 Watchdog Timer Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.3.1 Watchdog Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.4.1 Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.4.2 Wake-Up From Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.4.3 Powering Down the Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
5 Digital Input/Output (I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Describes the digital I/O ports module.
5.1 Digital I/O Ports Register Implementation on 240xA Devices . . . . . . . . . . . . . . . . . . . . . 5-2

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 Contents

5.2 Differences in GPIO Implementation in the 240xA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.3 I/O Mux Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.1 I/O Mux Control Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3.2 I/O Mux Output Control Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.3.3 I/O Mux Output Control Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.4 Data and Direction Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

6 Event Manager (EV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

Describes the event manager (EV) module. Includes descriptions of the general-purpose timer,
compare units, pulse-width modulation waveform circuits, capture units, and quadrature en-
coder pulse circuits.
6.1 Event Manager (EV) Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.1.1 Differences Between C240 EV and 240xA EV . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.1.2 EV Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.1.3 Power Drive Protection Interrupt (PDPINTx, x = A or B) . . . . . . . . . . . . . . . . . . . 6-8
6.1.4 EV Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.1.5 EV Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.2 Event Manager (EV) Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.3 Figure 6−13General-Purpose (GP) Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.3.1 GP Timer Counting Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.3.2 GP Timer Compare Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
6.3.3 Timer Control Registers (TxCON and GPTCONA/B) . . . . . . . . . . . . . . . . . . . . 6-32
6.3.4 Generation of PWM Outputs Using the GP Timers . . . . . . . . . . . . . . . . . . . . . . 6-38
6.3.5 GP Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
6.4 Compare Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39
6.4.1 Compare Units Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41
6.4.2 Compare Unit Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47
6.4.3 Compare Unit Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47
6.5 PWM Circuits Associated With Compare Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48
6.5.1 PWM Generation Capability of Event Manager . . . . . . . . . . . . . . . . . . . . . . . . . 6-49
6.5.2 Programmable Dead-Band (Dead-Time) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
6.5.3 Output Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55
6.6 PWM Waveform Generation With Compare Units and PWM Circuits . . . . . . . . . . . . . 6-57
6.6.1 Generation of PWM Outputs With Event Manager . . . . . . . . . . . . . . . . . . . . . . 6-58
6.6.2 Register Setup for PWM Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-58
6.6.3 Asymmetric PWM Waveform Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59
6.6.4 Symmetric PWM Waveform Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60
6.6.5 Double Update PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-61
6.7 Space Vector PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62
6.7.1 3-Phase Power Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62
6.7.2 Space Vector PWM Waveform Generation with Event Manager . . . . . . . . . . . 6-64
6.7.3 Space Vector PWM Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66
6.8 Capture Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-68
6.8.1 Capture Unit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-70

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6.8.2 Operation of Capture Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-71

6.8.3 Capture Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-72
6.8.4 Capture Unit FIFO Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-78
6.8.5 Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-79
6.9 Quadrature Encoder Pulse (QEP) Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-80
6.9.1 QEP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-80
6.9.2 QEP Circuit Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-80
6.9.3 Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-81
6.9.4 QEP Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-82
6.9.5 Register Setup for the QEP Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-82
6.10 Event Manager (EV) Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-84
6.10.1 EV Interrupt Request and Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-84
6.10.2 EV Interrupt Flag Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-87

7 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

Describes the analog-to-digital converter (ADC), Includes a list of features, explains the clock
prescaler, and provides register descriptions.
7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.2 ADC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.2.1 Autoconversion Sequencer: Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.2.2 Uninterrupted Autosequenced Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.2.3 Sequencer Start/Stop Mode (Sequencer “Start/Stop” Operation With
Multiple “Time-Sequenced Triggers”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.2.4 Input Trigger Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.2.5 Interrupt Operation During Sequenced Conversions . . . . . . . . . . . . . . . . . . . . . 7-13
7.3 ADC Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
7.4 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
7.5 Register Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
7.5.1 ADC Control Register 1 (ADCTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
7.5.2 ADC Control Register 2 (ADCTRL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
7.5.3 Maximum Conversion Channels Register (MAXCONV) . . . . . . . . . . . . . . . . . . 7-31
7.5.4 Autosequence Status Register (AUTO_SEQ_SR) . . . . . . . . . . . . . . . . . . . . . . . 7-33
7.5.5 ADC Input Channel Select Sequencing Control Registers (CHSELSEQn) . . 7-35
7.5.6 ADC Conversion Result Buffer Registers (RESULTn) . . . . . . . . . . . . . . . . . . . 7-37
7.6 ADC Conversion Clock Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38

8 Serial Communications Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

Describes the architecture, functions, and programming of the of the Serial Communications
Interface (SCI) module.
8.1 C240 SCI vs. LF/LC240xA SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.1 SCI Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.1.3 SCI Module Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.1.4 Multiprocessor and Asynchronous Communication Modes . . . . . . . . . . . . . . . . 8-7

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8.2 SCI Programmable Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.3 SCI Multiprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.3.1 Idle-Line Multiprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.3.2 Address-Bit Multiprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
8.4 SCI Communication Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8.4.1 Receiver Signals in Communication Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
8.4.2 Transmitter Signals in Communication Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
8.5 SCI Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.6 SCI Baud Rate Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
8.7 SCI Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
8.7.1 SCI Communication Control Register (SCICCR) . . . . . . . . . . . . . . . . . . . . . . . . 8-21
8.7.2 SCI Control Register 1 (SCICTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
8.7.3 Baud-Select Registers (SCIHBAUD, SCILBAUD) . . . . . . . . . . . . . . . . . . . . . . . 8-26
8.7.4 SCI Control Register 2 (SCICTL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
8.7.5 Receiver Status Register (SCIRXST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
8.7.6 Receiver Data Buffer Registers (SCIRXEMU, SCIRXBUF) . . . . . . . . . . . . . . . 8-30
8.7.7 Transmit Data Buffer Register (SCITXBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31
8.7.8 Priority Control Register (SCIPRI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32

9 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

Describes the architecture, functions, and programming of the serial peripheral interface (SPI)
module.
9.1 C240 SPI vs. LF/LC240xA SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.1.1 SPI Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2 Overview of SPI Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.3 SPI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.3.1 Introduction to Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.3.2 SPI Module Slave and Master Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.4 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.4.1 SPI Interrupt Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.4.3 Baud Rate and Clocking Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9.4.4 SPI Clocking Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.4.5 Initialization Upon Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
9.4.6 Data Transfer Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
9.5 SPI Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
9.5.1 SPI Configuration Control Register (SPICCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
9.5.2 SPI Operation Control Register (SPICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
9.5.3 SPI Status Register (SPISTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22
9.5.4 SPI Baud Rate Register (SPIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
9.5.5 SPI Emulation Buffer Register (SPIRXEMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
9.5.6 SPI Serial Receive Buffer Register (SPIRXBUF) . . . . . . . . . . . . . . . . . . . . . . . . 9-26
9.5.7 SPI Serial Transmit Buffer Register (SPITXBUF) . . . . . . . . . . . . . . . . . . . . . . . 9-27
9.5.8 SPI Serial Data Register (SPIDAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28

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9.5.9 SPI Priority Control Register (SPIPRI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29

9.6 SPI Example Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30

10 CAN Controller Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

Describes the CAN controller module, interface signals, CAN peripheral registers, and mailbox
RAM, layout, and operations.
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.2 Overview of the CAN Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2.1 CAN Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2.2 CAN Controller Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.3 Message Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.3.1 Mailbox Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.3.2 Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.3.3 Write Access to Mailbox RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.3.4 Transmit Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.3.5 Receive Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.3.6 Handling of Remote Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.3.7 Mailbox Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.3.8 Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.4 CAN Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
10.4.1 Mailbox Direction/Enable Register (MDER) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
10.4.2 Transmit Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
10.4.3 Receive Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
10.4.4 Master Control Register (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
10.4.5 Bit Configuration Registers (BCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
10.5 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
10.5.1 Error Status Register (ESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
10.5.2 Global Status Register (GSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32
10.5.3 CAN Error Counter Register (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34
10.6 Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35
10.6.1 CAN Interrupt Flag Register (CAN_IFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-36
10.6.2 CAN Interrupt Mask Register (CAN_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-38
10.7 Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39
10.8 Power-Down Mode (PDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-40
10.9 Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-41

11 Watchdog (WD) Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

Describes the features and operation of the watchdog (WD) timer module. Covers the architec-
ture and the registers used to implement WD functions.
11.1 Watchdog Timer Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2 Watchdog Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.2.1 Overview of WD Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.2.2 Watchdog Timer Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

xiv
 Contents

11.2.3 Watchdog Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

11.2.4 Operations of the WD Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.3 Watchdog Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.3.1 WD Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.3.2 WD Reset Key Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11.3.3 WD Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
12 240xA-240 Family Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Describes compatibility issues between the 240xA and the 240 family of processors.
12.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2 Event Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.4 Serial Communications Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.5 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.6 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
13 240xA-24x Family Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Describes the major differences between the 24x and the 240xA family of processors.
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.1.1 Migrating Code from 24x to 240x/240xA Devices . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.2 24x-240xA DSP Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.3.1 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.4 System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.4.1 Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.4.2 Watchdog Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13.4.3 System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.5 Digital I/O (GPIO Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.5.1 Digital I/O and Shared Pin Functions for the 240xA . . . . . . . . . . . . . . . . . . . . 13-11
13.6 Event Manager Module (EVB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.6.1 Input Qualification Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
A Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Provides a summary or changes made in this revision.
A.1 Changes Made in This Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
B Programmable Register Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Provides a summary of all programmable registers on TMS320X240xA devices.

C Program Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1

Presents program examples for the 240xA.
C.1 About These Program Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
C.2 Program Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4
D TMS320F240x/240xA Boot ROM Loader: Protocols and Interfacing . . . . . . . . . . . . . . . . . . D-1
Decribes the boot-load sequence and discusses SPI synchronous and SCI asynchronous
transfer protocol and data formats.
D.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2

Contents xv
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D.1.1 Boot-Load Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2

D.2 Protocol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-6
D.2.1 SPI Synchronous Transfer Protocol and Data Formats . . . . . . . . . . . . . . . . . . . D-6
D.2.2 SCI Asynchronous Transfer Protocol and Data Formats . . . . . . . . . . . . . . . . . . D-7

E Flash/ROM Code Security For LF/LC240xA DSP Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1

Describes the Flash/ROM code security features, lists the code security module (CSM) regis-
ters, and discusses programming considerations for the TMS320LF/LC240xA devices with and
without code security.
E.1 Flash/ROM Security Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2
E.1.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2
E.1.2 CSM Impact on Other On-Chip Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3
E.1.3 Incorporating Code Security in User Applications . . . . . . . . . . . . . . . . . . . . . . . . E-4
E.2 Technical Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5
E.3 Environments that Require Security Unlocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-7
E.3.1 Password Match Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-7
E.4 Unsecuring Considerations for Devices With/Without Code Security . . . . . . . . . . . . . . . E-9
E.4.1 Case 1: Device With Code Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9
E.4.2 Case 2: Device Without Code Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9
E.5 DOs and DON’Ts to Protect Security Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-10
E.5.1 DOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-10
E.5.2 DON’Ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-10
E.6 CSM Features − Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-12
E.7 CSM — Frequently Asked Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-13

F Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-1
Explains terms, abbreviations, and acronyms used throughout this book.

xvi
 Figures

 
1−1. 240xA Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
2−1. 240xA Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2−2. System Control and Status Register 1 (SCSR1) — Address 07018h . . . . . . . . . . . . . . . . . 2-3
2−3. System Control and Status Register 2 (SCSR2) — Address 07019h . . . . . . . . . . . . . . . . . 2-5
2−4. Device Identification Number Register (DINR) — Address 701Ch . . . . . . . . . . . . . . . . . . . 2-8
2−5. Peripheral Interrupt Expansion Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2−6. Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2−7. 240xA Interrupt Response and Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2−8. Interrupt Flag Register (IFR) — Address 0006h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2−9. Interrupt Mask Register (IMR) — Address 0004h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
2−10. Peripheral Interrupt Vector Register (PIVR) — Address 701Eh . . . . . . . . . . . . . . . . . . . . . 2-30
2−11. Peripheral Interrupt Request Register 0 (PIRQR0) — Address 7010h . . . . . . . . . . . . . . . 2-31
2−12. Peripheral Interrupt Request Register 1 (PIRQR1) — Address 7011h . . . . . . . . . . . . . . . 2-32
2−13. Peripheral Interrupt Request Register 2 (PIRQR2) — Address 7012h . . . . . . . . . . . . . . . 2-33
2−14. Peripheral Interrupt Acknowledge Register 0 (PIACKR0) — Address 7014h . . . . . . . . . 2-34
2−15. Peripheral Interrupt Acknowledge Register 1 (PIACKR1) — Address 7015h . . . . . . . . . 2-35
2−16. Peripheral Interrupt Acknowledge Register 2 (PIACKR2) — Address 7016h . . . . . . . . . 2-36
2−17. External Interrupt 1 Control Register (XINT1CR) — Address 7070h . . . . . . . . . . . . . . . . . 2-39
2−18. External Interrupt 2 Control Register (XINT2CR) — Address 7071h . . . . . . . . . . . . . . . . . 2-40
3−1. Program Memory Map for LF2407A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3−2. 2407A Peripheral Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3−3. Data Memory Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3−4. I/O Space Address Map for 2407A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3−5. Program Address/Data — Visibility Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3−6. Data Address/ Data — Visibility Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3−7. 2407A Wait-State Generator Control Register (WSGR) —
I/O-Space Address FFFFh (2407A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
4−1. Reference Resonator/Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4−2. Power and Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
5−1. Shared Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5−2. I/O Mux Control Register A (MCRA) — Address 7090h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5−3. I/O Mux Control Register B (MCRB) — Address 7092h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5−4. I/O Mux Control Register C (MCRC) — Address 7094h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5−5. Port A Data and Direction Control Register (PADATDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5−6. Port B Data and Direction Control Register (PBDATDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5−7. Port C Data and Direction Control Register (PCDATDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

Contents xvii
Figures

5−8. Port D Data and Direction Control Register (PDDATDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

5−9. Port E Data and Direction Control Register (PEDATDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5−10. Port F Data and Direction Control Register (PFDATDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
6−1. Event Manager A (EVA) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6−2. Event Manager B (EVB) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6−3. General-Purpose Timer Block Diagram (x = 2 or 4)
[when x = 2: y = 1 and n = 2; when x = 4: y = 3 and n = 4] . . . . . . . . . . . . . . . . . . . . . . . 6-15
6−4. Timer x Counter Register (TxCNT, where x = 1, 2, 3, or 4) . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6−5. Timer x Compare Register (TxCMPR, where x = 1, 2, 3, or 4) . . . . . . . . . . . . . . . . . . . . . . 6-16
6−6. Timer x Period Register (TxPR, where x = 1, 2, 3, or 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6−7. GP Timer Continuous Up-Counting Mode (TxPR = 3 or 2) . . . . . . . . . . . . . . . . . . . . . . . . 6-24
6−8. GP Timer Directional Up-/Down-Counting Mode: Prescale Factor 1 and TxPR = 3 . . . . 6-25
6−9. GP Timer Continuous Up-/Down-Counting Mode (TxPR = 3 or 2) . . . . . . . . . . . . . . . . . . . 6-26
6−10. GP Timer Compare/PWM Output in Up-Counting Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
6−11. GP Timer Compare/PWM Output in Up-/Down-Counting Modes . . . . . . . . . . . . . . . . . . . 6-30
6−12. Timer x Control Register (TxCON; x = 1, 2, 3, or 4) — Addresses 7404h
(T1CON), 7408h (T2CON), 7504h (T3CON), and 7508h (T4CON) . . . . . . . . . . . . . . . . . . 6-33
6−13. GP Timer Control Register A (GPTCONA) — Address 7400h . . . . . . . . . . . . . . . . . . . . . . 6-35
6−14. GP Timer Control Register B (GPTCONB) — Address 7500h . . . . . . . . . . . . . . . . . . . . . . 6-36
6−15. Compare Unit Block Diagram (For EVA: x = 1, 2, 3; y = 1, 3, 5; z = 1.
For EVB: x = 4, 5, 6; y = 7, 9, 11; z = 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39
6−16. Compare Control Register A (COMCONA) — Address 7411h . . . . . . . . . . . . . . . . . . . . . . 6-42
6−17. Compare Control Register B (COMCONB) — Address 7511h . . . . . . . . . . . . . . . . . . . . . . 6-43
6−18. Compare Action Control Register A (ACTRA) — Address 7413h . . . . . . . . . . . . . . . . . . . 6-44
6−19. Compare Action Control Register B (ACTRB) — Address 7513h . . . . . . . . . . . . . . . . . . . 6-46
6−20. PWM Circuits Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48
6−21. Dead-Band Timer Control Register A (DBTCONA) — Address xx15h . . . . . . . . . . . . . . . 6-50
6−22. Dead-Band Timer Control Register B (DBTCONB) — Address xx15h . . . . . . . . . . . . . . . 6-51
6−23. Dead-Band Unit Block Diagram (x = 1, 2, or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-54
6−24. Output Logic Block Diagram (x = 1, 2, or 3; y = 1, 2, 3, 4, 5, or 6) . . . . . . . . . . . . . . . . . . . 6-56
6−25. Asymmetric PWM Waveform Generation With Compare Unit and PWM Circuits
(x = 1, 3, or 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59
6−26. Symmetric PWM Waveform Generation With Compare Units and PWM
Circuits (x = 1, 3, or 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60
6−27. 3-Phase Power Inverter Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62
6−28. Basic Space Vectors and Switching Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-64
6−29. Symmetric Space Vector PWM Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-67
6−30. Capture Units Block Diagram (EVA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-69
6−31. Capture Units Block Diagram (EVB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-70
6−32. Capture Control Register A (CAPCONA) — Address 7420h . . . . . . . . . . . . . . . . . . . . . . . 6-72
6−33. Capture Control Register B (CAPCONB) — Address 7520h . . . . . . . . . . . . . . . . . . . . . . . 6-74
6−34. Capture FIFO Status Register A (CAPFIFOA) — Address 7422h . . . . . . . . . . . . . . . . . . . 6-76
6−35. Capture FIFO Status Register B (CAPFIFOB) — Address 7522h . . . . . . . . . . . . . . . . . . . 6-77
6−36. Quadrature Encoder Pulse (QEP) Circuit Block Diagram for EVA . . . . . . . . . . . . . . . . . . . 6-80
6−37. Quadrature Encoder Pulse (QEP) Circuit Block Diagram for EVB . . . . . . . . . . . . . . . . . . 6-81

xviii
 Figures

6−38. Quadrature Encoded Pulses and Decoded Timer Clock and Direction . . . . . . . . . . . . . . . 6-82
6−39. EVA Interrupt Flag Register A (EVAIFRA) — Address 742Fh . . . . . . . . . . . . . . . . . . . . . . . 6-87
6−40. EVA Interrupt Flag Register B (EVAIFRB) — Address 7430h . . . . . . . . . . . . . . . . . . . . . . . 6-89
6−41. EVA Interrupt Flag Register C (EVAIFRC) — Address 7431h . . . . . . . . . . . . . . . . . . . . . . 6-90
6−42. EVA Interrupt Mask Register A (EVAIMRA) — Address 742Ch . . . . . . . . . . . . . . . . . . . . . 6-91
6−43. EVA Interrupt Mask Register B (EVAIMRB) — Address 742Dh . . . . . . . . . . . . . . . . . . . . . 6-92
6−44. EVA Interrupt Mask Register C (EVAIMRC) — Address 742Eh . . . . . . . . . . . . . . . . . . . . . 6-93
6−45. EVB Interrupt Flag Register A (EVBIFRA) — Address 752Fh . . . . . . . . . . . . . . . . . . . . . . 6-94
6−46. EVB Interrupt Flag Register B (EVBIFRB) — Address 7530h . . . . . . . . . . . . . . . . . . . . . . 6-96
6−47. EVB Interrupt Flag Register C (EVBIFRC) — Address 7531h . . . . . . . . . . . . . . . . . . . . . . 6-97
6−48. EVB Interrupt Mask Register A (EVBIMRA) — Address 752Ch . . . . . . . . . . . . . . . . . . . . . 6-98
6−49. EVB Interrupt Mask Register B (EVBIMRB) — Address 752Dh . . . . . . . . . . . . . . . . . . . . . 6-99
6−50. EVB Interrupt Mask Register C (EVBIMRC) — Address 752Eh . . . . . . . . . . . . . . . . . . . . 6-100
7−1. Block Diagram of Autosequenced ADC in Cascaded Mode . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7−2. Block Diagram of Autosequenced ADC With Dual Sequencers . . . . . . . . . . . . . . . . . . . . . . 7-6
7−3. Flow Chart for Uninterrupted Autosequenced Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7−4. Example of Event Manager Triggers to Start the Sequencer . . . . . . . . . . . . . . . . . . . . . . . 7-11
7−5. Interrupt Operation During Sequenced Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
7−6. ADC Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
7−7. Clock Prescalers in 240xA ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
7−8. Calibration Register − Address 70B8h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
7−9. ADC Control Register 1 (ADCTRL1) — Address 70A0h . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
7−10. ADC Control Register 2 (ADCTRL2) — Address 70A1h . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
7−11. Maximum Conversion Channels Register (MAXCONV) — Address 70A2h . . . . . . . . . . . 7-31
7−12. Autosequence Status Register (AUTO_SEQ_SR) — Address 70A7h . . . . . . . . . . . . . . . 7-33
7−13. ADC Input Channel Select Sequencing Control Registers (CHSELSEQn) . . . . . . . . . . . 7-35
7−14. ADC Conversion Result Buffer Registers (RESULTn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37
8−1. SCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8−2. Typical SCI Data Frame Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8−3. Idle-Line Multiprocessor Communication Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
8−4. Double-Buffered WUT and TXSHF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
8−5. Address-Bit Multiprocessor Communication Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
8−6. SCI Asynchronous Communications Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8−7. SCI RX Signals in Communication Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
8−8. SCI TX Signals in Communications Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
8−9. SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
8−10. SCI Communication Control Register (SCICCR) — Address 7050h . . . . . . . . . . . . . . . . . 8-21
8−11. SCI Control Register 1 (SCICTL1) — Address 7051h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
8−12. Baud-Select MSbyte Register (SCIHBAUD) — Address 7052h . . . . . . . . . . . . . . . . . . . . . 8-26
8−13. Baud-Select LSbyte Register (SCILBAUD) — Address 7053h . . . . . . . . . . . . . . . . . . . . . . 8-26
8−14. SCI Control Register 2 (SCICTL2) — Address 7054h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
8−15. Receiver Status Register (SCIRXST) — Address 7055h . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
8−16. Register SCIRXST Bit Associations — Address 7055h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30
8−17. Emulation Data Buffer Register (SCIRXEMU) — Address 7056h . . . . . . . . . . . . . . . . . . . 8-31

Contents xix
Figures

8−18. Receiver Data Buffer (SCIRXBUF) — Address 7057h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31

8−19. Transmit Data Buffer Register (SCITXBUF) — Address 7059h . . . . . . . . . . . . . . . . . . . . . 8-31
8−20. SCI Priority Control Register (SCIPRI) — Address 705Fh . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
9−1. SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9−2. SPI Master/Slave Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9−3. SPICLK Signal Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
9−4. SPI: SPICLK-CLKOUT Characteristic when (BRR + 1) is Odd, BRR > 3, and
CLOCK POLARITY = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
9−5. Five Bits per Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
9−6. SPI Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
9−7. SPI Configuration Control Register (SPICCR) — Address 7040h . . . . . . . . . . . . . . . . . . . 9-19
9−8. SPI Operation Control Register (SPICTL) — Address 7041h . . . . . . . . . . . . . . . . . . . . . . . 9-21
9−9. SPI Status Register (SPISTS) — Address 7042h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22
9−10. SPI Baud Rate Register (SPIBRR) — Address 7044h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
9−11. SPI Emulation Buffer Register (SPIRXEMU) — Address 7046h . . . . . . . . . . . . . . . . . . . . 9-25
9−12. SPI Serial Receive Buffer Register (SPIRXBUF) — Address 7047h . . . . . . . . . . . . . . . . . 9-26
9−13. SPI Serial Transmit Buffer Register (SPITXBUF) — Address 7048h . . . . . . . . . . . . . . . . 9-27
9−14. SPI Serial Data Register (SPIDAT) — Address 7049h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
9−15. SPI Priority Control Register (SPIPRI) — Address 704Fh . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
9−16. CLOCK POLARITY = 0, CLOCK PHASE = 0 (All data transitions are during
the rising edge, non-delayed clock. Inactive level is low.) . . . . . . . . . . . . . . . . . . . . . . . . 9-30
9−17. CLOCK POLARITY = 0, CLOCK PHASE = 1 (All data transitions are during
the rising edge, but delayed by half clock cycle. Inactive level is low.) . . . . . . . . . . . . . . . 9-31
9−18. CLOCK POLARITY = 1, CLOCK PHASE = 0 (All data transitions are during
the falling edge. Inactive level is high.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32
9−19. CLOCK POLARITY = 1, CLOCK PHASE = 1 (All data transitions are during
the falling edge, but delayed by half clock cycle. Inactive level is high.) . . . . . . . . . . . . . . 9-33
9−20. SPISTE Behavior in Master Mode (Master lowers SPISTE during the entire
16 bits of transmission.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34
9−21. SPISTE Behavior in Slave Mode (Slave’s SPISTE is driven low during the
entire 16 bits of transmission.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35
10−1. CAN Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10−2. TMS320x240xA CAN Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10−3. TMS320x240xA CAN Module Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10−4. CAN Data Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10−5. Message Identifier for High-Word Mailboxes 0−5 (MSGIDnH) . . . . . . . . . . . . . . . . . . . . . 10-10
10−6. Message Identifier for Low-Word Mailboxes 0−5 (MSGIDnL) . . . . . . . . . . . . . . . . . . . . . . 10-11
10−7. Message Control Field (MSGCTRLn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10−8. Remote Frame Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10−9. Local Acceptance Mask Register n (0, 1) High Word (LAMn_H) −
Addresses 710Bh, 710Dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10−10. Local Acceptance Mask Register n (0, 1) Low Word (LAMn_L) −
Addresses 710Ch, 710Eh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10−11. Mailbox Direction/Enable Register (MDER) — Address 7100h . . . . . . . . . . . . . . . . . . . . 10-19
10−12. Transmission Control Register (TCR) — Address 7101h . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
10−13. Receive Control Register (RCR) — Address 7102h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22

xx
 Figures

10−14. Master Control Register (MCR) — Address 7103h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23

10−15. Bit Configuration Register 2 (BCR2) — Address 7104h . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26
10−16. Bit Configuration Register 1 (BCR1) — Address 7105h . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27
10−17. CAN Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29
10−18. Error Status Register (ESR) — Address 7106h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
10−19. Global Status Register (GSR) — Address 7107h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32
10−20. CAN Error Counter Register (CEC) — Address 7108h . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34
10−21. CAN Interrupt Flag Register (CAN_IFR) — Address 7109h . . . . . . . . . . . . . . . . . . . . . . . 10-36
10−22. CAN Interrupt Mask Register (CAN_IMR) — Address 710Ah . . . . . . . . . . . . . . . . . . . . . . 10-38
10−23. CAN Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39
11−1. Block Diagram of the WD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11−2. WD Counter Register (WDCNTR) — Address 7023h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11−3. WD Reset Key Register (WDKEY) — Address 7025h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11−4. WD Timer Control Register (WDCR) — Address 7029h . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
13−1. LF2407A Memory Map for Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13−2. 240xA Watchdog Clock Generation Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13−3. Functional Block Diagram for Boot EN/XF Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13−4. Functional Block Diagram of XMIF Signals on LF2407 . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
C−1. Procedure for Generating Executable Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
D−1. Example Hardware Configuration for LF240xA Boot ROM Operation . . . . . . . . . . . . . . . . . D-4
D−2. Memory Maps for the LF240xA/LF240x Devices in Microcontroller Mode . . . . . . . . . . . . . D-5
D−3. SPI Data Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-7
D−4. Flowchart for the Serial Loader Baud Rate Match Algorithm . . . . . . . . . . . . . . . . . . . . . . . D-9
D−5. Flowcharts for Serial Asynchronous Loader and the Fetch Header Routine . . . . . . . . . . D-10
D−6. Flowchart for FETCH SCI WORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-11
E−1. Password Match Flow (PMF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-8

Contents xxi
Tables


1−1. Hardware Features of 240xA Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
2−1. Description of Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2−2. 240xA Interrupt Source Priority and Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2−3. Peripheral Interrupt Request Descriptions (PIRQR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2−4. Peripheral Interrupt Request Descriptions (PIRQR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
2−5. Peripheral Interrupt Request Descriptions (PIRQR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
2−6. Peripheral Interrupt Acknowledge Descriptions (PIACKR0) . . . . . . . . . . . . . . . . . . . . . . . . 2-35
2−7. Peripheral Interrupt Acknowledge Descriptions (PIACKR1) . . . . . . . . . . . . . . . . . . . . . . . . 2-36
2−8. Peripheral Interrupt Acknowledge Descriptions (PIACKR2) . . . . . . . . . . . . . . . . . . . . . . . . 2-37
3−1. Data Page 0 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3−2. XMIF Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3−3. Setting the Number of Wait States With the 2407A WSGR Bits . . . . . . . . . . . . . . . . . . . . 3-19
4−1. Low-Power Modes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
5−1. 240xA Digital I/O Port Control Registers Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5−2. I/O Mux Control Register A (MCRA) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5−3. I/O Mux Control Register B (MCRB) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5−4. I/O Mux Control Register C (MCRC) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5−5. PADATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5−6. PBDATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5−7. PCDATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5−8. PDDATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5−9. PEDATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5−10. PFDATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
6−1. Event Manager A Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6−2. Event Manager B Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6−3. Addresses of EVA Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6−4. Addresses of EVB Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6−5. Addresses of EVA Compare Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6−6. Addresses of EVB Compare Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6−7. Addresses of EVA Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6−8. Addresses of EVB Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6−9. Addresses of EVA Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

xxii
 Tables

6−10. Addresses of EVB Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

6−11. GP Timer Compare Output in Continuous Up-Counting Modes . . . . . . . . . . . . . . . . . . . . 6-31
6−12. GP Timer Compare Output in Continuous Up-/Down-Counting Modes . . . . . . . . . . . . . . 6-31
6−13. Dead-Band Generation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53
6−14. Switching Patterns of a 3-Phase Power Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-63
6−15. Interrupt Flag Register and Corresponding Interrupt Mask Register . . . . . . . . . . . . . . . . . 6-84
6−16. Event Manager A (EVA) Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-85
6−17. Event Manager B (EVB) Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-86
6−18. Conditions for Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-86
7−1. Addresses of ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7−2. Comparison of Single and Cascaded Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7−3. ADC Clock Prescale Factors for CLK = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
7−4. ADC Clock Prescale Factors for CLK = 40 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7−5. Reference Voltage Bit Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
7−6. Bit Selections for MAX CONV1 for Various Number of Conversions . . . . . . . . . . . . . . . . . 7-33
7−7. Status Bit Values for SEQ CNTR n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34
7−8. CONVnn Bit Values and the ADC Input Channels Selected . . . . . . . . . . . . . . . . . . . . . . . . 7-36
7−9. ADC Conversion Phases vs CLKOUT cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38
7−10. ACQ Values When ACQ PS = 1, 2, and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38
8−1. Overview of SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8−2. Programming the Data Format Using SCICCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8−3. Asynchronous Baud Register Values for Common SCI Bit Rates . . . . . . . . . . . . . . . . . . . 8-19
8−4. SCI CHAR2−0 Bit Values and Character Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
8−5. SW RESET-Affected Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
9−1. Addresses of SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9−2. SPI Clocking Scheme Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
9−3. Character Length Control Bit Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
10−1. Mailbox Configuration Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10−2. Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10−3. Mailbox Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10−4. CAN Bit Timing Examples for CLKOUT = 40 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29
10−5. CAN Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-42
10−6. Mailbox RAM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-44
11−1. Typical WDKEY Register Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11−2. WD Module Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11−3. WD Overflow (Timeout) Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
13−1. 24x-Compatible Features/Peripherals in 240xA DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13−2. New or Modified Features/Peripherals in 240xA DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13−3. Features of 24x and 240xA DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13−4. 240xA PLL Pin Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13−5. Oscillator/PLL Frequency Input Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13−6. Peripheral Clock Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13−7. LF2407A Shared Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13−8. Event Manager Module and Signal Names for EVA and EVB . . . . . . . . . . . . . . . . . . . . . 13-14

Contents xxiii
Tables

B−1. Summary of Programmable Registers on the 240xA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

B−2. Code Security Module (CSM) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9
C−1. Common Files For All Example Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
C−2. Program Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
D−1. Clock Speeds at Which Baud Rate Locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-8
E−1. Security Mode Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2
E−2. Code Security Module (CSM) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-6

xxiv
 Examples


7−1. Conversion in Dual-Sequencer Mode Using SEQ1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7−2. Sequencer Start/Stop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7−3. MAXCONV Register Bit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32
7−4. Calculating the Conversion Time for a Multiple Conversion Sequence With
CPS = 0 and ACQ = 0: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-39
7−5. Calculating the Conversion Time for a Single Conversion Sequence With
CPS = 1 and ACQ = 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-39
9−1. Transmission of Bit from SPIRXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9−2. Maximum Baud-Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13

Contents xxv
Notes

 
Re-enabling interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Do Not Write to Test/Emulation Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Do Not Write to Test/Emulation Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Validating Resonator/Crystal Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Failure to Clear the Interrupt Flag Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-87
Dual-Sequencer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Using the RESET Bit in the ADCTRL1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
The Address-bit format is for transfers of 11 bytes or less . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
Unused Message Mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
Power-on reset (POR) and WDFLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
Power-on reset (POR) and WDFLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10

xxvi
 Chapter 1

  

The TMS320Lx240xA series of devices are members of the TMS320 family

of digital signal processors (DSPs) designed to meet a wide range of digital
motor control (DMC) and other embedded control applications. This series is
based on the C2xLP 16-bit, fixed-point, low-power DSP CPU, and is
complemented with a wide range of on-chip peripherals and on-chip ROM or
flash program memory, plus on-chip dual-access RAM (DARAM).

This reference guide describes the following 240xA devices: 2407A, 2406A,
2404A, 2403A, 2402A, and 2401A.

This chapter provides an overview of the current TMS320 family, describes the
background and benefits of the 240xA DSP controller products, and
introduces the 240xA devices. These low-cost DSPs are intended to enable
multiple applications for a nominal price.

Throughout this book, all devices are referred to as 240xA devices. This book
is applicable for both the 240x and 240xA families of devices and will be
applicable for future derivatives of the 240xA family. Any feature that is not
applicable for the 240x family is highlighted as appropriate. This book should
be used in conjunction with the TMS320F/C24x DSP Controllers Reference
Guide: CPU and Instruction Set (literature number SPRU160) and the
appropriate device data sheet. Device errata are updated as and when an
exception to functional specification of the silicon is discovered. Refer to the
latest errata for exceptions to functional specifications and possible
workarounds.

Topic Page
1.1 TMS320 Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 TMS320C240xA Series of DSP Controllers . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.4 New Features in 240xA Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.5 240xA Highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1-1
TMS320 Family Overview

1.1 TMS320 Family Overview

The TMS320 family consists of fixed-point, floating-point, multiprocessor
digital signal processors (DSPs), and fixed-point DSP controllers. TMS320
DSPs have an architecture designed specifically for real-time signal
processing. The 240xA series of DSP controllers combines this real-time
processing capability with controller peripherals to create an ideal solution for
control system applications. The following characteristics make the TMS320
family the right choice for a wide range of processing applications:

Very flexible instruction set

Inherent operational flexibility

High-speed performance

Innovative parallel architecture

Cost effectiveness

In 1982, Texas Instruments introduced the TMS32010, the first fixed-point

DSP in the TMS320 family. Before the end of the year, Electronic Products
magazine awarded the TMS32010 the title “Product of the Year”. Today, the
TMS320 family consists of these generations: C1x, C2x, C20x, C24x, C5x,
C54x, and C6x fixed-point DSPs; C3x and C4x floating-point DSPs; and C8x
multiprocessor DSPs. The 240xA devices are considered part of the 24x
generation of fixed-point DSPs, and members of the C2000 platform.

Devices within a generation of a TMS320 platform have the same CPU

structure but different on-chip memory and peripheral configurations. Spin-off
devices use new combinations of on-chip memory and peripherals to satisfy
a wide range of needs in the worldwide electronics market. By integrating
memory and peripherals onto a single chip, TMS320 devices reduce system
costs and save circuit board space.

1-2
 TMS320C240xA Series of DSP Controllers

1.2 TMS320C240xA Series of DSP Controllers

Designers have recognized the opportunity to redesign existing digital motor
control (DMC) systems to use advanced algorithms that yield better
performance and reduce system component count. DSPs enable:

Design of robust controllers for a new generation of inexpensive motors,

such as AC induction, DC permanent magnet, and switched-reluctance
motors

Full variable-speed control of brushless motor types that have lower

manufacturing cost and higher reliability

Energy savings through variable-speed control, saving up to 25% of the

energy used by fixed-speed controllers

Increased fuel economy, improved performance, and elimination of

hydraulic fluid in automotive electronic power steering (EPS) systems

Reduced manufacturing and maintenance costs by eliminating hydraulic

fluid in automotive electronic braking systems

More efficient and quieter operation due to diminished torque ripple, re-
sulting in less loss of power, lower vibration, and longer life

Elimination or reduction of memory lookup tables through real-time poly-

nomial calculation, thereby reducing system cost

Use of advanced algorithms that can reduce the number of sensors

required in a system

Control of power switching inverters, along with control algorithm

processing

Single-processor control of multimotor systems

Control-Based Applications

The 240xA DSP controllers are designed to meet the needs of control-based
applications. By integrating the high performance of a DSP core and the
on-chip peripherals of a microcontroller into a single-chip solution, the 240xA
series yields a device that is an affordable alternative to traditional
microcontroller units (MCUs) and expensive multichip designs. At 40 million
instructions per second (MIPS), the 240xA DSP controllers offer significant
performance over traditional 16-bit microcontrollers and microprocessors.
(240x devices operate at 30 MIPS.)

Introduction 1-3
TMS320C240xA Series of DSP Controllers

The 16-bit, fixed-point DSP core of the 240xA device provides analog
designers a digital solution that does not sacrifice the precision and
performance of their systems. In fact, system performance can be enhanced
through the use of advanced control algorithms for techniques such as
adaptive control, Kalman filtering, and state control. The 240xA DSP
controllers offer reliability and programmability. Analog control systems, on the
other hand, are hardwired solutions and can experience performance
degradation due to aging, component tolerance, and drift.

Reduced Development Time

The high-speed central processing unit (CPU) allows the digital designer to
process algorithms in real time rather than approximate results with look-up
tables. The instruction set of these DSP controllers, which incorporates both
signal processing instructions and general-purpose control functions, coupled
with the extensive development support available for the 240xA devices,
reduces development time and provides the same ease of use as traditional
8- and 16-bit microcontrollers. The instruction set also allows you to retain your
software investment when moving from other general-purpose TMS320
fixed-point DSPs. It is source- and object-code compatible with the other
members of the 24x generation, source-code compatible with the C2x
generation, and upwardly source-code compatible with the C5x generation of
DSPs from Texas Instruments.
The 240xA architecture is also well-suited for processing control signals. It
uses a 16-bit word length along with 32-bit registers for storing intermediate
results, and has two hardware shifters available to scale numbers
independently of the CPU. This combination minimizes quantization and
truncation errors, and increases processing power for additional functions.
Such functions might include a notch filter that could cancel mechanical
resonances in a system or an estimation technique that could eliminate state
sensors in a system.
The 240xA DSP controllers take advantage of an existing set of peripheral
functions that allow Texas Instruments to quickly configure various series
members for different price/performance points or for application optimization.
This library of both digital- and mixed-signal peripherals includes:

Event manager

Controller Area Network (CAN)

Serial communications ports (SCI, SPI)

Analog-to-digital converters (ADC)

Safety features such as watchdog timer and power drive protection
The DSP controller peripheral library is continually growing and changing to
suit the needs of tomorrow’s embedded control marketplace.

1-4
 Peripheral Overview

1.3 Peripheral Overview

The peripheral set for the 240xA devices includes:

Event Manager: Timers and PWM generators for digital motor control

CAN Interface: Controller Area Network (CAN) 2.0b compatible, with six
mailboxes

A/D: 10-bit analog-to-digital converter

SPI: Serial Peripheral Interface − synchronous serial port

SCI: Serial Communications Interface − asynchronous serial port (univer-

sal asynchronous receiver and transmitter − UART)

Watchdog timer

General-purpose bidirectional digital I/O (GPIO) pins

Note:
For device pinouts, electrical characteristics, and timing specifications of
LF240x devices, see the following data sheet:
TMS320LF2407, TMS320LF2406, TMS320LF2402 DSP Controllers Data
Sheet (literature number SPRS094).
For LF/LC240xA devices, see the following data sheets:
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A,
TMS320LF2402A, TMS320LC2406A, TMS320LC2404A,
TMS320LC2402A DSP Controllers Data Sheet (literature number
SPRS145); TMS320LF2401A, TMS320LC2401A DSP Controllers Data
Sheet (literature number SPRS161).

Introduction 1-5
New Features in 240xA Devices

1.4 New Features in 240xA Devices

The following new features were added in the 240xA devices:(compared to
240x devices)

40-MHz operation (as compared to 30 MHz for the 240x family)

Code security for on-chip Flash/ROM

Input qualifier circuitry for PDPINTx, CAPn, XINTn, and ADCSOC pins

Status of the PDPINTx pin is reflected in the COMCONx register

1-6
 1.5 240xA Highlights
Available device configurations and their features are shown in Table 1−1.

Table 1−1. Hardware Features of 240xA Devices

Feature LF2407A LF2406A LF2403A LF2402A LF2401A LC2406A LC2404A LC2402A LC2401A
C2xx DSP Core Yes Yes Yes Yes Yes Yes Yes Yes Yes
Instruction Cycle 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns
MIPS (40 MHz) 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS 40 MIPS
DARAM 544 544 544 544 544 544 544 544 544
RAM (16-bit word)
SARAM 2K 2K 512 512 512 2K 1K — 512
On-chip Flash (16-bit word)
32K 32K 16K 8K 8K — — — —
(4 sectors: 4K, 12K, 12K, 4K)
On-chip ROM (16-bit word) — — — — 32K 16K 6K 8K
Code Security for On-Chip
Yes Yes Yes Yes Yes Yes Yes Yes Yes
Flash/ROM
Boot ROM (16-bit word) Yes Yes Yes Yes Yes — — — Yes
External Memory Interface Yes — — — — — — — —
Event Managers A and B EVA, EVA, EVA, EVA,
EVA EVA EVA EVA EVA
(EVA and EVB) EVB EVB EVB EVB

General-Purpose (GP)
4 4 2 2 2 4 4 2 2
Timers

Compare (CMP)/PWM 12/16 12/16 6/8 6/8 7 12/16 12/16 6/8 7

Capture (CAP)/QEP 6/4 6/4 3/2 3/2 1 6/4 6/4 3/2 1

Input qualifier circuitry on PDPINTx,
Yes Yes Yes Yes Yes† Yes Yes Yes Yes†
CAPn, XINT1/2, and ADCSOC pins

Status of PDPINTx pin reflected in
Yes Yes Yes Yes Yes Yes Yes Yes Yes
COMCONx register
Watchdog Timer Yes Yes Yes Yes Yes Yes Yes Yes Yes
10-Bit ADC Yes Yes Yes Yes Yes Yes Yes Yes Yes

Channels 16 16 8 8 5 16 16 8 5

Introduction

Conversion Time (minimum) 375 ns 375 ns 375 ns 375 ns 500 ns 375 ns 375 ns 425 ns 500 ns
SPI Yes Yes Yes — — Yes Yes — —
Shading denotes features that are different/new compared to 240x devices.
† Some pins may not be applicable to Lx2401A.

1-7
240x Highlights
1-8
Table 1−1. Hardware Features of 240xA Devices (Continued)
Feature LF2407A LF2406A LF2403A LF2402A LF2401A LC2406A LC2404A LC2402A LC2401A
SCI Yes Yes Yes Yes Yes Yes Yes Yes Yes
240x Highlights

CAN Yes Yes Yes — — Yes — — —

Digital I/O Pins (Shared) 41 41 21 21 13 41 41 21 13
External Interrupts 5 5 3 3 2 5 5 3 2

Introduction
Supply Voltage 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Packaging 144-pin 100-pin 64-pin 64-pin 32-pin 100-pin 100-pin 64-pin 32-pin
PGE PZ PAG PG VF PZ PZ PG, PAG VF
Shading denotes features that are different/new compared to 240x devices.
† Some pins may not be applicable to Lx2401A.
 240x Highlights

Figure 1−1 provides a graphical overview of the devices.

Figure 1−1. 240xA Device Overview
PLLF
PLLVCCA
DARAM (B0) PLLF2
256 Words PLL clock
XINT1/IOPA2 XTAL1/CLKIN
RS XTAL2
CLKOUT/IOPE0 ADCIN00−ADCIN07
C2xx DARAM (B1) ADCIN08−ADCIN15
TMS2
DSP 256 Words VCCA
BIO/IOPC1 core 10-Bit ADC VSSA
MP/MC (with twin VREFHI
BOOT EN/XF autosequencer)
DARAM (B2) VREFLO

ÈÈÈÈÈÈÈ
32 Words XINT2/ADCSOC/IOPD0

ÈÈÈÈÈÈÈÈÈÈÈÈÈÈ
SCITXD/IOPA0
SCI SCIRXD/IOPA1

ÈÈÈÈÈÈÈÈÈÈÈÈÈÈ
VDD (3.3 V)
SPISIMO/IOPC2
VSS SARAM (2K Words)
SPISOMI/IOPC3

ÈÈÈÈÈÈÈÈÈÈÈÈÈÈ
SPI SPICLK/IOPC4

ÈÈÈÈÈÈÈÈÈÈÈÈÈÈ
SPISTE/IOPC5
TP1
CANTX/IOPC6

ÈÈÈÈÈÈÈÈÈÈÈÈÈÈ
TP2 Flash/ROM CAN CANRX/IOPC7
VCCP(5V) (32K Words:

ÈÈÈÈÈÈÈ
4K/12K/12K/4K)
WD

ÈÈÈÈÈÈÈ
Port A(0−7) IOPA[0:7]
A0−A15 Port B(0−7) IOPB[0:7]

ÈÈÈÈÈÈÈ
D0−D15 Port C(0−7) IOPC[0:7]
Digital I/O

ÈÈÈÈÈÈÈ
PS, DS, IS (shared with other pins) Port D(0) IOPD[0]
R/W Port E(0−7) IOPE[0:7]

ÈÈÈÈÈÈÈ
RD Port F(0−6) IOPF[0:6]
TRST

ÈÈÈÈÈÈÈ
READY
STRB External memory interface TDO

ÈÈÈÈÈÈÈ
WE TDI
ENA 144 JTAG port TMS

ÈÈÈÈÈÈÈ
TCK

ÈÈÈÈÈÈÈÈÈÈÈÈÈÈ
VIS OE EMU0
W/R / IOPC0 EMU1

ÈÈÈÈÈÈÈ
PDPINTA PDPINTB

ÈÈÈÈÈÈÈ
CAP1/QEP1/IOPA3 CAP4/QEP3/IOPE7
CAP2/QEP2/IOPA4 CAP5/QEP4/IOPF0

ÈÈÈÈÈÈÈ
CAP3/IOPA5 CAP6/IOPF1
PWM1/IOPA6 PWM7/IOPE1

ÈÈÈÈÈÈÈ
PWM2/IOPA7
Event manager A Event manager B
PWM8/IOPE2

ÈÈÈÈÈÈÈ
PWM3/IOPB0  3 × Capture input  3 × Capture input PWM9/IOPE3
PWM4/IOPB1  6 × Compare/PWM  6 × Compare/PWM PWM10/IOPE4

ÈÈÈÈÈÈÈ
PWM5/IOPB2 output output PWM11/IOPE5
 2 × GP timers/PWM  2 × GP timers/PWM

ÈÈÈÈÈÈÈ
PWM6/IOPB3 PWM12/IOPE6
T1PWM/T1CMP/IOPB4 T3PWM/T3CMP/IOPF2

ÈÈÈÈÈÈÈ
T2PWM/T2CMP/IOPB5 T4PWM/T4CMP/IOPF3

ÈÈÈÈÈÈÈ
TDIRA/IOPB6 TDIRB/IOPF4
TCLKINA/IOPB7 TCLKINB/IOPF5

ÈÈÈ
ÈÈÈ
Indicates optional modules. The memory size and peripheral selection of these modules change for different
240xA devices. See Table 1−1 for device-specific details. For a device overview figure of the 2401A device,
see TMS320LF2401A, TMS320LC2401A DSP Controllers Data Sheet (literature number SPRS161).

1-9
 This page intentionally left blank.

1-10
 Chapter 2

        

This chapter describes the system configuration registers and interrupts

associated with the 240xA devices. It also explains how the peripheral
interrupt expansion (PIE) is used to increase interrupt request capacity.

Topic Page

2.1 Architecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 Interrupt Priority and Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.4 Peripheral Interrupt Expansion (PIE) Controller . . . . . . . . . . . . . . . . . 2-13
2.5 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.6 Interrupt Operation Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.7 Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.8 Sample ISR Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.9 CPU Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.10 Peripheral Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2.11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
2.12 Illegal Address Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
2.13 External Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39

2-1
Architecture Summary

2.1 Architecture Summary

The 240xA devices are implemented as ASIC customizable digital signal
processors (cDSPs). In the CPU, program ROM/FLASH is implemented as
ASIC hard macros as shown in the shaded blocks in Figure 2−1. The CPU
uses the LP256 hard macro which consists of the TMS320C2xx DSP CPU
core, 544 x 16 words of dual-access RAM (DARAM), the analysis/JTAG logic,
the internal memory interface, and the logic interface. The logic interface,
however, is not used in the 240xA.
The peripherals interface to the internal memory interface of the CPU through
the PBUS interface. All on-chip peripherals are accessed through the
peripheral bus, PBUS. At lower frequencies, all peripheral accesses (reads
and writes) are zero-wait-state, single-cycle accesses. All peripherals,
excluding the watchdog timer counter, are clocked by the CPU clock. A third
ASIC module is the 10-bit A/D converter.
These devices have up to 41 bit-selectable digital I/O ports. Most or all of these
I/O ports are multiplexed with other functions, such as event manager signals,
serial communication port signals, or interrupts. Most of these multiplexed
digital I/O pins come up in their digital I/O pin mode as an input following a
device reset. For a detailed description of the architecture and instruction set,
refer to the TMS320F/C24x DSP Controllers Reference Guide: CPU and
Instruction Set (SPRU160).

Figure 2−1. 240xA Device Architecture

C2xx CPU + JTAG

+ 544 x 16 DARAM
Logic Flash/ROM
SARAM I/F (up to 32K × 16)
(up to 2K × 16)

Mem I/F

Synthesized ASIC gates

P bus I/F
P bus

Event
ADC Interrupts I/O
Managers SPI SCI CAN WD
control reset, etc. registers
(EVA and EVB)

ADC

2-2
 Configuration Registers

2.2 Configuration Registers

2.2.1 System Control and Status Registers 1 and 2 (SCSR1, SCSR2)

Figure 2−2. System Control and Status Register 1 (SCSR1) — Address 07018h
15 14 13 12 11 10 9 8

Reserved CLKSRC LPM1 LPM0 CLK PS2 CLK PS1 CLK PS0 Reserved

R-0 RW-0 RW-0 RW-0 RW-1 RW-1 RW-1 R-0

7 6 5 4 3 2 1 0

ADC SCI SPI CAN EVB EVA

Reserved ILLADR
CLKEN CLKEN CLKEN CLKEN CLKEN CLKEN

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R-0 RC-0

Note: R = Read access, W = Write access, C = Clear, -0 = value after reset

Bit 15 Reserved

Bit 14 CLKSRC. CLKOUT pin source select

0 CLKOUT pin has CPU Clock (40 MHz on a 40-MHz device) as the
output
1 CLKOUT pin has Watchdog clock as the output

Bits 13−12 LPM(1:0). Low-power mode select

These bits indicate which low-power mode is entered when the CPU executes
the IDLE instruction. See Table 2−1 for a description of the low-power modes.

Table 2−1. Description of Low-Power Modes

LPM(1:0) Low-Power mode selected
00 IDLE1 (LPM0)

01 IDLE2. (LPM1)

1x HALT (LPM2)

System Configuration and Interrupts 2-3

Configuration Registers

Bits 11−9 PLL Clock prescale select. These bits select the PLL multiplication factor for
the input clock.

CLK CLK CLK

System Clock Frequency
PS2 PS1 PS0
0 0 0 4 x Fin
0 0 1 2 x Fin
0 1 0 1.33 x Fin
0 1 1 1 x Fin
1 0 0 0.8 x Fin
1 0 1 0.66 x Fin
1 1 0 0.57 x Fin
1 1 1 0.5 x Fin
Note: Fin is the input clock frequency.

Bit 8 Reserved

Bit 7 ADC CLKEN. ADC module clock enable control bit

0 Clock to module is disabled (i.e., shut down to conserve power)
1 Clock to module is enabled and running normally

Bit 6 SCI CLKEN. SCI module clock enable control bit

0 Clock to module is disabled (i.e., shut down to conserve power)
1 Clock to module is enabled and running normally

Bit 5 SPI CLKEN. SPI module clock enable control bit

0 Clock to module is disabled (i.e., shut down to conserve power)
1 Clock to module is enabled and running normally

Bit 4 CAN CLKEN. CAN module clock enable control bit

0 Clock to module is disabled (i.e., shut down to conserve power)
1 Clock to module is enabled and running normally

Bit 3 EVB CLKEN. EVB module clock enable control bit

0 Clock to module is disabled (i.e., shut down to conserve power)
1 Clock to module is enabled and running normally

Bit 2 EVA CLKEN. EVA module clock enable control bit

0 Clock to module is disabled (i.e., shut down to conserve power)
1 Clock to module is enabled and running normally

2-4
 Configuration Registers

Note:
In order to modify/read the register contents of any peripheral, the clock to
that peripheral must be enabled by writing a 1 to the appropriate bit.

Bit 1 Reserved

Bit 0 ILLADR. Illegal Address detect bit

If an illegal address has occurred this bit will be set. It is up to software to clear
this bit following an illegal address detect. This bit is cleared by writing a 1 to
it and should be cleared as part of the initialization sequence. Note: An illegal
address access will cause an NMI.

Figure 2−3. System Control and Status Register 2 (SCSR2) — Address 07019h
15−8

Reserved

RW-0
7 6 5 4 3 2 1 0

WD
Reserved I/P QUAL XMIF HI-Z BOOT EN MP/MC DON PON
OVERRIDE

RW-0 RC-1 RW-0 RW-BOOT RW- RW-1 RW-1

EN pin MP/MC pin
Note: R = Read access, W = Write access, C = Clear, -0 = value after reset

Bits 15−7 Reserved. Writes have no effect; reads are undefined

Bit 6 Input Qualifier Clocks.

An input-qualifier circuitry qualifies the input signal to the CAP1−6, XINT1/2,
ADCSOC, and PDPINTA/B pins in the 240xA devices. The I/O functions of
these pins do not use the input-qualifier circuitry. The state of the internal input
signal will change only after the pin is held high/low for 6 (or 12) clock edges.
This ensures that a glitch smaller than (or equal to) 5 (or 11) CLKOUT cycles
wide will not change the internal pin input state. The user must hold the pin
high/low for 6 (or 12) cycles to ensure that the device will see the level change.

This bit determines the width of the glitches (in number of internal clock cycles)
that will be blocked. Note that the internal clock is not the same as CLKOUT,
although its frequency is the same as CLKOUT.
0 The input-qualifier circuitry blocks glitches up to 5 clock cycles long
1 The input-qualifier circuitry blocks glitches up to 11 clock cycles
long

System Configuration and Interrupts 2-5

Configuration Registers

Note:
This bit is applicable only for the 240xA devices, not for the 240x devices
since they lack an input-qualifier circuitry.

Bit 5 Watchdog Override. (WD protect bit)

After RESET, this bit gives you the ability to protect the WD function from being
disabled through software (by setting the WDDIS bit = 1 in the WDCR). This
bit is a clear-only bit and defaults to a 1 after reset, Note: this bit is cleared by
writing a 1 to it.
0 Protects the WD from being disabled by software. This bit cannot
be set to 1 by software. It is a clear-only bit, cleared by writing a 1.
Clearing this bit would enable the WD if it were currently disabled.
1 This is the default reset value and allows the user to disable the
WD through the WDDIS bit in the WDCR. Once cleared however,
this bit can no longer be set to 1 by software, thereby protecting
the integrity of the WD timer.

Bit 4 XMIF Hi-Z Control

This bit controls the state of the external memory interface (XMIF) signals.
0 XMIF signals in normal driven mode; i.e., not Hi-Z (high impedance)
1 All XMIF signal are forced to Hi-Z state

Note:
This bit is a reserved bit on all devices other than LF2407/2407A, and must
be written only as a zero.

Bit 3 Boot Enable

This bit reflects the state of the BOOT_EN / XF pin at the time of reset. After
reset and device has “Booted up”, this bit can be changed in software to
re-enable Flash memory visibility, or return to active Boot ROM.
0 Enable Boot ROM — Address space 0000 — 00FF is now occu-
pied by the on-chip Boot ROM Block. Flash memory is totally dis-
abled in this mode. Note: There is no on-chip boot ROM in ROM
devices (i.e., LC240xA)
1 Disable Boot ROM — Program address space 0000 — 7FFF is
mapped to on-chip Flash Memory in the case of LF2407A and
LF2406A. In the case of LF2402A, addresses 0000 − 1FFF are
mapped

2-6
 Configuration Registers

Bit 2 Microprocessor / Microcontroller Select

This bit reflects the state of the MP/MC pin at time of reset. After reset, this bit
can be changed in software to allow dynamic mapping of memory on and off
chip.
0 Set to Microcontroller mode — Program Address range 0000 —
7FFF is mapped internally (i.e., Flash)
1 Set to Microprocessor mode — Program Address range 0000 —
7FFF is mapped externally (i.e., Customer provides external
memory device.)
Note: MP/MC pin is available only in LF2407A and LF2407.

Bits 1−0 SARAM Program / Data Space Select

DON PON SARAM status
0 0 SARAM not mapped (disabled), address space allocated
to external memory
0 1 SARAM mapped internally to Program space
1 0 SARAM mapped internally to Data space
1 1 SARAM block mapped internally to both Data and Pro-
gram spaces. This is the default or reset value

Note: See memory map for location of SARAM addresses

System Configuration and Interrupts 2-7

Configuration Registers

2.2.2 Device Identification Number Register (DINR)

Figure 2−4. Device Identification Number Register (DINR) — Address 701Ch

15 14 13 12 11 10 9 8

DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8

R-x R-x R-x R-x R-x R-x R-x R-x

7 6 5 4 3 2 1 0

DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0

R-x R-x R-x R-x R-x R-x R-x R-x

Note: R = Read access, -x = hardwired device-specific DIN value

Bits 15−4 DIN15−DIN4. These bits contain the hard-wired device-specific device identi-
fication number (DIN).

Bits 3−0 DIN3−DIN0. These bits contain the hard-wired device revision-specific value.
Device Rev # DIN #
LF2407 (rev 1.0 − 1.5) 0510h
LF2407 1.6 0511h
LF240xA, 1.0 0520h
LF240xA 1.1 0521h
LC2406A, LC2404A All revs 0700h
LC2402A All revs 0610h
LF2401A All revs 0810h
LC2401A All revs 0910h

2-8
 Interrupt Priority and Vectors

2.3 Interrupt Priority and Vectors

A centralized interrupt expansion scheme is implemented in order to
accommodate the large number of peripheral interrupts with the six maskable
interrupts supported by the CPU. Table 2−2 provides the interrupt source
priority and vectors for the 240xA devices. The details of the 240xA interrupt
expansion scheme are explained in Chapter 2.
Table 2−2. 240xA Interrupt Source Priority and Vectors

CPU Peripheral
Overall Interrupt Interrupt Interrupt Source
Priority Name Vector Vector Maskable? Peripheral Description
1 Reset RSN N/A N RS Pin, Reset from pin, watch-
0000h Watchdog dog time out
2 Reserved − N/A N CPU Emulator trap
0026h
3 NMI NMI N/A N Nonmaskable Nonmaskable interrupt
0024h interrupt
(a) INT1 (level 1)
CPU Peripheral
Overall Interrupt Interrupt Interrupt Source
Priority Name Vector Vector Maskable? Peripheral Description
4 PDPINTA INT1 0020h Y EVA Power drive protection
0002h interrupt pin
5 PDPINTB INT1 0019h Y EVB Power drive protection
0002h interrupt pin
6 ADCINT INT1 0004h Y ADC ADC interrupt in high-
0002h priority mode
7 XINT1 INT1 0001h Y External External interrupt pin in
0002h interrupt logic high-priority mode
8 XINT2 INT1 0011h Y External External interrupt pin in
0002h interrupt logic high-priority mode
9 SPIINT INT1 0005h Y SPI SPI interrupt in high-
0002h priority mode
10 RXINT INT1 0006h Y SCI SCI receiver interrupt
0002h in high-priority mode
11 TXINT INT1 0007h Y SCI SCI transmitter inter-
0002h rupt in high-priority
mode
12 CANMBINT INT1 0040h Y CAN CAN mailbox interrupt
0002h (high-priority mode)
13 CANERINT INT1 0041h Y CAN CAN error interrupt
0002h (high-priority mode)

System Configuration and Interrupts 2-9

Interrupt Priority and Vectors

Table 2−2. 240xA Interrupt Source Priority and Vectors (Continued)

(b) INT2 (level 2)
CPU Peripheral
Overall Interrupt Interrupt Interrupt Source
Priority Name Vector Vector Maskable? Peripheral Description
14 CMP1INT INT2 0021h Y EVA Compare 1 interrupt
0004h
15 CMP2INT INT2 0022h Y EVA Compare 2 interrupt
0004h
16 CMP3INT INT2 0023h Y EVA Compare 3 interrupt
0004h
17 T1PINT INT2 0027h Y EVA Timer 1 period interrupt
0004h
18 T1CINT INT2 0028h Y EVA Timer 1 compare
0004h interrupt
19 T1UFINT INT2 0029h Y EVA Timer 1 underflow
0004h interrupt
20 T1OFINT INT2 002Ah Y EVA Timer 1 overflow
0004h interrupt
21 CMP4INT INT2 0024h Y EVB Compare 4 interrupt
0004h
INT2
22 CMP5INT 0025h Y EVB Compare 5 interrupt
0004h
23 CMP6INT INT2 0026h Y EVB Compare 6 interrupt
0004h
24 T3PINT INT2 002Fh Y EVB Timer 3 period interrupt
0004h
25 T3CINT INT2 0030h Y EVB Timer 3 compare
0004h interrupt
26 T3UFINT INT2 0031h Y EVB Timer 3 underflow
0004h interrupt
27 T3OFINT INT2 0032h Y EVB Timer 3 overflow
0004h interrupt

2-10
 Interrupt Priority and Vectors

Table 2−2. 240xA Interrupt Source Priority and Vectors (Continued)

(c) INT3 (level 3)
CPU Peripheral
Overall Interrupt Interrupt Interrupt Source
Priority Name Vector Vector Maskable? Peripheral Description
28 T2PINT INT3 002Bh Y EVA Timer 2 period interrupt
0006h
29 T2CINT INT3 002Ch Y EVA Timer 2 compare
0006h interrupt
30 T2UFINT INT3 002Dh Y EVA Timer 2 underflow
0006h interrupt
31 T2OFINT INT3 002Eh Y EVA Timer 2 overflow
0006h interrupt
32 T4PINT INT3 0039h Y EVB Timer 4 period interrupt
0006h
33 T4CINT INT3 003Ah Y EVB Timer 4 compare
0006h interrupt
34 T4UFINT INT3 003Bh Y EVB Timer 4 undeflow
0006h interrupt
35 T4OFINT INT3 003Ch Y EVB Timer 4 overflow
0006h interrupt
(d) INT4 (level 4)
CPU Peripheral
Overall Interrupt Interrupt Interrupt Source
Priority Name Vector Vector Maskable? Peripheral Description
36 CAP1INT INT4 0033h Y EVA Capture 1 interrupt
0008h
37 CAP2INT INT4 0034h Y EVA Capture 2 interrupt
0008h
38 CAP3INT INT4 0035h Y EVA Capture 3 interrupt
0008h
39 CAP4INT INT4 0036h Y EVB Capture 4 interrupt
0008h
40 CAP5INT INT4 0037h Y EVB Capture 5 interrupt
0008h
41 CAP6INT INT4 0038h Y EVB Capture 6 interrupt
0008h

System Configuration and Interrupts 2-11

Interrupt Priority and Vectors

Table 2−2. 240xA Interrupt Source Priority and Vectors (Continued)

(e) INT5 (level 5)
CPU Peripheral
Overall Interrupt Interrupt Interrupt Source
Priority Name Vector Vector Maskable? Peripheral Description
42 SPIINT INT5 0005h Y SPI SPI interrupt
000Ah (low priority)
43 RXINT INT5 0006h Y SCI SCI receiver interrupt
000Ah (low-priority mode)
44 TXINT INT5 0007h Y SCI SCI transmitter interrupt
000Ah (low-priority mode)
45 CANMBINT INT5 0040h Y CAN CAN mailbox interrupt
000Ah (low-priority mode)
46 CANERINT INT5 0041h Y CAN CAN error interrupt
000Ah (low-priority mode)
(f) INT6 (level 6)
CPU Peripheral
Overall Interrupt Interrupt Interrupt Source
Priority Name Vector Vector Maskable? Peripheral Description
47 ADCINT INT6 0004h Y ADC ADC interrupt
000Ch (low priority)
48 XINT1 INT6 0001h Y External External interrupt pins
000Ch interrupt logic (low-priority mode)
49 XINT2 INT6 0011h Y External External interrupt pins
000Ch interrupt logic (low-priority mode)
Reserved 000Eh N/A Y CPU Analysis interrupt
N/A TRAP 0022h N/A N/A CPU TRAP instruction
N/A Phantom N/A 0000h N/A CPU Phantom interrupt
Interrupt vector
Vector
Note: Shaded interrupts are new interrupts added to 240xA by virtue of EVB.

Interrupts of nonexistent peripherals may not be applicable to a particular

device. For example, SPI and CAN interrupts are not applicable to the 2402A
device.

2-12
 Peripheral Interrupt Expansion (PIE) Controller

2.4 Peripheral Interrupt Expansion (PIE) Controller

The 240xA CPU supports one nonmaskable interrupt (NMI) and six maskable
prioritized interrupt requests (INT1−INT6) at the core level. The 240xA devices
have many peripherals, and each peripheral is capable of generating one or
more interrupts in response to many events at the peripheral level.

Because the C240xA CPU does not have sufficient capacity to handle all
peripheral interrupt requests at the core level, a centralized interrupt controller
(PIE) is required to arbitrate the interrupt requests from various sources such
as peripherals and other external pins (see Figure 2−5).

System Configuration and Interrupts 2-13

Peripheral Interrupt Expansion (PIE) Controller

Figure 2−5. Peripheral Interrupt Expansion Block Diagram

PDPINTA
PDPINTB
ADCINT PIE
XINT1
XINT2 Level 1
SPIINT IRQ GEN
RXINT INT1
TXINT
CANMBINT
CANERINT
PIRQR0

CMP1INT
CMP2INT
CMP3INT
T1PINT
T1CINT
T1UFINT INT2
T1OFINT Level 2
CMP4INT IRQ GEN
CMP5INT
CMP6INT
T3PINT
T3CINT CPU
T3UFINT
T3OFINT

T2PINT
T2CINT
T2UFINT INT3
T2OFINT Level 3
T4PINT IRQ GEN
T4CINT
T4UFINT
T4OFINT

CAP1INT
CAP2INT INT4
CAP3INT Level 4
PIRQR1

CAP4INT IRQ GEN

CAP5INT
CAP6INT

SPIINT
RXINT
Level 5 INT5
TXINT IRQ GEN
CANMBINT
CANERINT
INT6
ADCINT Level 6
XINT1 IRQ GEN
XINT2 IACK

PIRQR#
PIACKR#
PIVR#

Data Addr
bus bus

2-14
 Peripheral Interrupt Expansion (PIE) Controller

2.4.1 Interrupt Hierarchy

The number of interrupt slots available is expanded by having two levels of

hierarchy in the interrupt request system. Both the interrupt
request/acknowledge hardware and the interrupt service routine software
have two levels of hierarchy.

2.4.2 Interrupt Request Structure

At the lower level of the hierarchy, the peripheral interrupt requests (PIRQ)
from several peripherals to the interrupt controller are ORed together to
generate an interrupt request (INTn) to the CPU. This is the core level interrupt
request. There is an interrupt flag bit and an interrupt enable bit located in the
peripheral configuration registers for each event that can cause a PIRQ. There
is also one PIRQ for each event. If an interrupt causing event occurs in a
peripheral and the corresponding interrupt enable bit is set, the interrupt
request from the peripheral to the interrupt controller will be asserted. This
interrupt request simply reflects the status of the peripheral’s interrupt flag,
gated with the interrupt enable bit. When the interrupt flag is cleared, the
interrupt request is cleared.

Some peripherals may have the capability to make either a high-priority or a

low-priority interrupt request. If a peripheral has this capability, the value of its
interrupt priority bit is also transmitted to the interrupt controller. The interrupt
request (PIRQ) continues to be asserted until it is either automatically cleared
by an interrupt acknowledge or cleared by the software.

At the upper level of the hierarchy, the ORed PIRQs generate interrupt (INTn)
requests to the CPU. The request to the C240xA CPU is a low-going pulse of
two CPU clock cycles. The PIE controller generates an INTn pulse when any
of the PIRQ’s controlling the INTn become active. If any of the PIRQ’s capable
of asserting the CPU interrupt request are still active in the cycle following an
interrupt acknowledge for the INTn, another INTn pulse is generated. An
interrupt acknowledge clears the highest priority pending PIRQ. Note that the
interrupts are automatically cleared only at the core level and not at the
peripheral level. The interrupt controller (not the peripherals) defines the
following:

Which CPU interrupt request gets asserted by which peripheral

Relative priority of each peripheral interrupt requests

This is shown in Table 2−2, 240xA Interrupt Source Priority and Vectors, on
page 2-9.

System Configuration and Interrupts 2-15

Peripheral Interrupt Expansion (PIE) Controller

2.4.3 Interrupt Acknowledge

The hierarchical interrupt expansion scheme requires one interrupt
acknowledge signal for each peripheral interrupt request to the interrupt
controller. When the CPU asserts its interrupt acknowledge, it simultaneously
puts a value on the program address bus, which corresponds to the CPU
interrupt being acknowledged. (It does this to fetch the interrupt vector from
program memory: each INTn has a vector stored in a dedicated program
memory address.) This value is shown in Table 2−2, 240xA Interrupt Source
Priority and Vectors, on page 2-9. The PIE controller decodes this value to
determine which of the CPU interrupt requests is being acknowledged. It then
generates a peripheral interrupt acknowledge in response to the
highest-priority currently asserted PIRQ associated with that CPU interrupt.

2-16
 Interrupt Vectors

2.5 Interrupt Vectors

When the CPU receives an interrupt request, it does not know which peripheral
event caused the request. To enable the CPU to distinguish between all of
these events, a unique peripheral interrupt vector is generated in response to
an active peripheral interrupt request. This vector is loaded into the peripheral
interrupt vector register (PIVR) in the PIE controller. It can then be read by the
CPU and used to generate a vector to branch to the interrupt service routine
(ISR) which corresponds to the event being acknowledged.

In effect there are two vector tables: The CPU’s vector table which is used to
get to the first, general interrupt service routine (GISR) in response to a CPU
interrupt request; and the peripheral vector table which is used to get to the
event specific interrupt service routine (SISR) corresponding to the event
which caused the PIRQ. The code in the GISR should read the PIVR, and after
saving any necessary context, use this value to generate a vector to the SISR.

Figure 2−6 shows an example of how XINT1 (external interrupt in high-priority

mode) generates an interrupt. For XINT1 in high-priority mode, a value of
0001h is loaded into the PIVR register. The CPU ascertains the value that was
loaded in the PIVR register and uses this value to determine which peripheral
caused the interrupt, and then branches to the appropriate SISR. Such a
branch to the SISR could be a conditional branch (BCND) which is executed
on the condition that the PIVR register holds a particular value. An alternative
scheme would be to left-shift the PIVR register by one bit while loading it in the
accumulator and adding a fixed offset value. Program control could then
branch to the address value stored in the accumulator (using the BACC
instruction). This address would point to the SISR.

System Configuration and Interrupts 2-17

Interrupt Vectors

Figure 2−6. Interrupt Requests

CPU Interrupt Registers and Logic

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INT6 INT5 INT4 INT3 INT2 INT1

IMR
INTM
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt
acknowledge
INT6 INT5 INT4 INT3 INT2 INT1

IFR

Peripheral Interrupt Extension

Interrupt controller
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PIRQ0 register

Peripheral: External Interrupt

Priority
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Flag Mask

XINT1CR register Priority

2.5.1 Phantom Interrupt Vector

The phantom interrupt vector is an interrupt system integrity feature. If the

CPU’s interrupt acknowledge is asserted but there is no associated peripheral
interrupt request asserted, the phantom vector is used so that this fault is
handled in a controlled manner. The phantom interrupt vector is required
when, for example, the CPU executes a software interrupt instruction with an
argument corresponding to a peripheral interrupt (usually INT1−INT6).
Another example is when a peripheral makes an interrupt request but its INTn
flag was cleared by software before the CPU acknowledged the request. In this
case, there may be no peripheral interrupt request asserted to the interrupt
controller; and therefore, the controller does not know which peripheral
interrupt vector to load into the PIVR. In these two situations, the phantom
interrupt vector is loaded into the PIVR in lieu of a peripheral interrupt vector.

2-18
 Interrupt Vectors

2.5.2 Software Hierarchy

There are two levels of interrupt service routine hierarchy: the general interrupt
service routine (GISR), and the specific interrupt service routine (SISR). There
is one GISR for each maskable prioritized request (INT1−INT6) to the CPU
which performs all necessary context saves before it fetches the peripheral
interrupt vector from the PIVR. This vector is used to generate a branch to the
SISR. There is one SISR for every interrupt request (IRQn) from a peripheral
to the interrupt controller, and this SISR performs the required actions in
response to the peripheral interrupt request.

The GISR must read the peripheral interrupt vector from the PIVR before
interrupts are re-enabled. (All interrupts are automatically disabled when an
interrupt is taken.) If the PIVR is not read before interrupts are re-enabled and
another interrupt is asserted, a new peripheral interrupt vector will be loaded
into the PIVR, causing permanent loss of the original peripheral interrupt
vector.

Nonmaskable interrupts such as reset and NMI are not part of PIE. The PIE
controller does not support expansion of nonmaskable interrupts.

2.5.3 Nonmaskable Interrupt (NMI)

The 240xA devices do not have an NMI pin like the 240 or 241/242/243
devices. NMI will be asserted when access to any illegal address is made.
When NMI is asserted, the code will branch to 0024h in program memory,
which is the NMI vector. There is no control register corresponding to the NMI
feature.

The following caution should be observed while using the SARAM on 240xA
devices that lack an external memory interface (XMIF): The last 2 words in
SARAM cannot be used to store a RET or Branch instruction. This is because
when a RET or Branch instruction reaches the execute phase of the pipeline,
the next two instruction words have already been fetched. Since addresses
8800h and above are illegal in 240xA devices that lack XMIF, this asserts an
NMI. As an example, the following code snippet will work:
87FB xxxxx
87FC xxxxx
87FD RET
87FE xxxxx
87FF xxxxx

However, if the RET instruction is pushed down to 87FE or 87FF, an NMI will
be asserted.

System Configuration and Interrupts 2-19

Interrupt Vectors

The following code snippet illustrates the behavior of unconditional branch:

87FB NOP
87FC B ”address”
87FE xxxxx
87FF xxxxx

This will work fine. However, if the B occupies 87FD or above, then NMI will
be asserted. TBLR and TBLW instructions can operate on data at locations
87FE or 87FF without any issue.

2-20
 Interrupt Operation Sequence

2.6 Interrupt Operation Sequence

An interrupt generating event occurs in a peripheral. Refer to Figure 2−7 for
the interrupt responses and flow in each module of the 240xA.The interrupt
flag (IF) bit corresponding to that event is set in a register in the peripheral. If
the corresponding interrupt enable (IE) bit is set, the peripheral generates an
interrupt request to the PIE controller by asserting its PIRQ. If the interrupt is
not enabled, the IF remains set until cleared by software. If the interrupt is
enabled at a later time, and the interrupt flag is still set, the PIRQ will
immediately be asserted.

If no unacknowledged CPU interrupt request of the same priority level (INTn)

has previously been sent, the PIRQ causes the PIE controller to generate a
CPU interrupt request (INTn). This pulse is active low for two CPU clock
cycles.

The interrupt request to the CPU sets the corresponding flag in the CPU’s
interrupt flag register (IFR). If the CPU interrupt has been enabled by setting
the corresponding bit in the CPU’s interrupt mask register (IMR), the CPU
stops what it is doing, masks all other maskable interrupts by setting the INTM
bit, saves some context, and starts executing the general interrupt service
routine (GISR) for that interrupt priority level (INTn). The CPU generates an
interrupt acknowledge automatically which is accompanied by a value on the
program address bus (PAB) corresponding to the interrupt priority level being
responded to. For example, if INT3 is asserted, its vector 0006h is loaded in
the PAB. This is the interrupt vector corresponding to INTn (refer to Table 2−2
240xA Interrupt Source Priority and Vectors, on page 2-9).

The PIE controller decodes the PAB value and generates a peripheral interrupt
acknowledge to clear the PIRQ bit associated with the CPU interrupt being
acknowledged. The PIE controller then loads the peripheral interrupt vector
register (PIVR) with the appropriate peripheral interrupt vector (or the phantom
interrupt vector) from the table stored in the PIE controller.

When the GISR has completed any necessary context saves, it reads the
PIVR and uses that interrupt vector to branch to the specific interrupt service
routine (SISR) for the interrupt event which occurred in the peripheral.

Note: Re-enabling interrupts

Interrupts must not be re-enabled until the PIVR has been read; otherwise,
it’s contents can get overwritten by a subsequent interrupt.

System Configuration and Interrupts 2-21

 This page is intentionally left blank.

2-22
 Figure 2−7. 240xA Interrupt Response and Flow

Start Peripheral Flow

Peripheral
CPU branches
interrupt GISR Flow
Peripheral
Peripheral interrupt
interrupt to
occurs
GISR
occurs
occurs

User code saves

Interrupt flag (IF) Interrupt generation context, reads
set in peripheral awaits IE to be set PIVR for PIV value
register (PR) or software clear of
the IF bit set in
peripheral register
PIV = phantom Yes Interrupt service for
Interrupt enable No phantom vector
vector?
(IE) = 1 in PR?
IE set by S/W
No
Yes
Return
PIE Flow Based on PIV
PIRQ generated CPU interrupt branch to SISR
to PIE acknowledge clears
interrupt request in
PIE (PIRQn) PIE logic also
PIRQ triggers PIE enables pending INTx SISR Flow
flags to be set and SISR user code to
the respective INTx PIE logic loads PIV service the peripheral
is generated value into PIVR interrupt

Next pending INTx

CPU receives INTx issued to CPU Clear IF bit in
peripheral register,
CPU Flow clear INTM bit
Respective CPU recognizes the
IFR bit is set INTx and issues
interrupt acknowledge
Return
Yes Yes
IMR bit = 1? INTM = 0? IFR bit is cleared,
INTM is set,
No No PC jumps to INTx Note:

System Configuration and Interrupts

vector address IF − Interrupt flag. This bit has to be cleared by s/w
Interrupt generation Interrupt logic awaits or future interrupts will be ignored.
0000−000Ch
logic awaits IMR bit INTM to be cleared IE − Interrupt enable
to be set or software GISR − General ISR
clear of the IFR bit SISR − Specific ISR
PR − Peripheral register, EVIFRA, etc.
Interrupt Operation Sequence

2-23
Interrupt Latency

2.7 Interrupt Latency

There are three components to interrupt latency:

1) Synchronization is the time it takes for the request generated in response

to the occurrence of an interrupt generating event to be recognized by the
PIE controller and converted into a request to the CPU.

2) Core Latency is the time it takes for the CPU to recognize the enabled in-
terrupt request, clear it’s pipeline, and begin fetching the first instruction
from the CPU’s interrupt vector table. There is a minimum core latency of
four CPU cycles. If a higher priority maskable interrupt is requested during
this minimum latency period, it is masked until the ISR for the interrupt be-
ing serviced re-enables the interrupt. The latency can be longer than the
minimum if the interrupt request occurs during an uninterruptible opera-
tion; for example, a repeat loop, a multicycle instruction, or during a wait-
stated access. If a higher-priority interrupt occurs during this additional la-
tency period, it gets serviced before the original lower-priority interrupt, as-
suming both are enabled.

3) ISR Latency is the time it takes to get to the specific interrupt service
routine (ISR) code for the event that caused the acknowledged interrupt.
ISR latency can vary depending on how much context saving is required.

2-24
 Sample ISR Code

2.8 Sample ISR Code

; This sample ISR code illustrates how to branch to an SISR corresponding

; to a peripheral interrupt. No context save is done.
; Timer 1 period interrupt is assumed

main code
.
B GISR2 ; This instruction resides at 0004h of PM
.
.
;========================================================================
; ISRs
;========================================================================
GISR2: LDP #PIVR >> 7h ; Load the data page containing PIVR
LACL PIVR ; Load PIVR value in the accumulator
XOR #0027h ; Timer 1 period interrupt ?
BCND SISR27,eq ; Branch to T1PINT if Accumulator = 0
; Else reload PIVR in the accumulator and continue
; checking for other peripheral interrupts

SISR27: ........... ; Execute the ISR specific to T1PINT

........... ; After executing the SISR, clear the flag bit
LDP #0E8h ; that asserted the interrupt, so that future
SPLK #0080h, EVIFRA ; interrupts may be recognized

EXIT_ISR
CLRC INTM ; Before exiting the SISR, clear the interrupt
RET ; mode bit

System Configuration and Interrupts 2-25

CPU Interrupt Registers

2.9 CPU Interrupt Registers

The CPU interrupt registers in the upper level of heirarchy include the
following:

Interrupt flag register (IFR)

Interrupt mask register (IMR)

2.9.1 Interrupt Flag Register (IFR)

The interrupt flag register (IFR), a 16-bit, memory-mapped register at address
0006h in data-memory space, is used to identify and clear pending interrupts.
The IFR contains flag bits for all the maskable interrupts (INT1−INT6).
When a maskable interrupt is requested, the flag bit in the corresponding
peripheral control register is set to 1. If the corresponding mask bit is also 1,
the interrupt request is sent to the CPU, setting the corresponding flag in the
IFR. This indicates that the interrupt is pending or waiting for
acknowledgement.
You can read the IFR to identify pending interrupts and write to the IFR to clear
pending interrupts. To clear a single interrupt, write a one to the corresponding
IFR bit. All pending interrupts can be cleared by writing the current contents
of the IFR back into the IFR.
The following events also clear an IFR flag:

The CPU acknowledges the interrupt.

The 240xA is reset.

Notes:
1) To clear an IFR bit, you must write a one to it, not a zero.
2) When a maskable interrupt is acknowledged, only the IFR bit is cleared
automatically. The flag bit in the corresponding peripheral control regis-
ter is not cleared. If an application requires that the control register flag
be cleared, the bit must be cleared by software.
3) When an interrupt is requested by an INTR instruction and the corre-
sponding IFR bit is set, the CPU does not clear the bit automatically. If
an application requires that the IFR bit be cleared, the bit must be cleared
by software.
4) IMR and IFR registers pertain to core-level interrupts. All peripherals
have their own interrupt mask and flag bits in their respective control/
configuration registers. Note that several peripheral interrupts are
grouped under one core-level interrupt.

2-26
 CPU Interrupt Registers

Figure 2−8. Interrupt Flag Register (IFR) — Address 0006h

15−6 5 4 3 2 1 0

Reserved INT6 flag INT5 flag INT4 flag INT3 flag INT2 flag INT1 flag

0 RW1C-0 RW1C-0 RW1C-0 RW1C-0 RW1C-0 RW1C-0

Note: 0 = Always read as zeros, R = Read access, W1C = Write 1 to this bit to clear it, -0 = value after reset

Bits 15−6 Reserved. These bits are always read as zeros.

Bit 5 INT6. Interrupt 6 flag. This bit is the flag for interrupts connected to interrupt
level INT6.
0 No INT6 interrupt is pending
1 At least one INT6 interrupt is pending. Write a 1 to this bit to clear
it to 0 and clear the interrupt request
Bit 4 INT5. Interrupt 5 flag. This bit is the flag for interrupts connected to interrupt
level INT5.
0 No INT5 interrupt is pending
1 At least one INT5 interrupt is pending. Write a 1 to this bit to clear
it to 0 and clear the interrupt request
Bit 3 INT4. Interrupt 4 flag. This bit is the flag for interrupts connected to interrupt
level INT4.
0 No INT4 interrupt is pending
1 At least one INT4 interrupt is pending. Write a 1 to this bit to clear
it to 0 and clear the interrupt request

Bit 2 INT3. Interrupt 3 flag. This bit is the flag for interrupts connected to interrupt
level INT3.
0 No INT3 interrupt is pending
1 At least one INT3 interrupt is pending. Write a 1 to this bit to clear
it to 0 and clear the interrupt request

Bit 1 INT2. Interrupt 2 flag. This bit is the flag for interrupts connected to interrupt
level INT2.
0 No INT2 interrupt is pending
1 At least one INT2 interrupt is pending. Write a 1 to this bit to clear
it to 0 and clear the interrupt request

Bit 0 INT1. Interrupt 1 flag. This bit is the flag for interrupts connected to interrupt
level INT1.
0 No INT1 interrupt is pending
1 At least one INT1 interrupt is pending. Write a 1 to this bit to clear
it to 0 and clear the interrupt request

System Configuration and Interrupts 2-27

CPU Interrupt Registers

2.9.2 Interrupt Mask Register (IMR)

The IMR is a 16-bit, memory-mapped register located at address 0004h in
data memory space. The IMR contains mask bits for all the maskable interrupt
levels (INT1−INT6). Neither NMI nor RS is included in the IMR; thus, IMR has
no effect on these interrupts.

You can read the IMR to identify masked or unmasked interrupt levels, and you
can write to the IMR to mask or unmask interrupt levels. To unmask an interrupt
level, set its corresponding IMR bit to one. To mask an interrupt level, set its
corresponding IMR bit to zero. When an interrupt is masked, it is not
acknowledged, regardless of the value of the INTM bit. When an interrupt is
unmasked, it is acknowledged if the corresponding IFR bit is one and the INTM
bit is zero.

The IMR is shown in Figure 2−9, and descriptions of the bits follow the figure.

Figure 2−9. Interrupt Mask Register (IMR) — Address 0004h

15−6 5 4 3 2 1 0

Reserved INT6 mask INT5 mask INT4 mask INT3 mask INT2 mask INT1 mask

0 RW RW RW RW RW RW

Note: 0 = Always read as zeros, R = Read access, W = Write access, bit values are not affected by a device reset

Bits 15−6 Reserved. These bits are always read as zeros.

Bit 5 INT6. Interrupt 6 mask. This bit masks or unmasks interrupt level INT6.
0 Level INT6 is masked
1 Level INT6 is unmasked

Bit 4 INT5. Interrupt 5 mask. This bit masks or unmasks interrupt level INT5.
0 Level INT5 is masked
1 Level INT5 is unmasked

Bit 3 INT4. Interrupt 4 mask. This bit masks or unmasks interrupt level INT4.
0 Level INT4 is masked
1 Level INT4 is unmasked

Bit 2 INT3. Interrupt 3 mask. This bit masks or unmasks interrupt level INT3.
0 Level INT3 is masked
1 Level INT3 is unmasked

2-28
 CPU Interrupt Registers

Bit 1 INT2. Interrupt 2 mask. This bit masks or unmasks interrupt level INT2.
0 Level INT2 is masked
1 Level INT2 is unmasked

Bit 0 INT1. Interrupt 1 mask. This bit masks or unmasks interrupt level INT1.
0 Level INT1 is masked
1 Level INT1 is unmasked

Note:
The IMR bits are not affected by a device reset.

System Configuration and Interrupts 2-29

Peripheral Interrupt Registers

2.10 Peripheral Interrupt Registers

The peripheral interrupt registers include the following:

Peripheral interrupt vector register (PIVR)

Peripheral interrupt request register 0 (PIRQR0)

Peripheral interrupt request register 1 (PIRQR1)

Peripheral interrupt request register 2 (PIRQR2)

Peripheral interrupt acknowledge register 0 (PIACKR0)

Peripheral interrupt acknowledge register 1 (PIACKR1)

Peripheral interrupt acknowledge register 2 (PIACKR2)

Note:
PIRQR0/1/2 and PIACKR0/1/2 are control registers internal to the PIE
module used for generating interrupts (INT1 − INT6) to the CPU. While
programming, these registers can be ignored since they monitor the internal
operation of the PIE. These registers are used for test purposes and are not
intended for user applications.

2.10.1 Peripheral Interrupt Vector Register (PIVR)

The peripheral interrupt vector register (PIVR) is a 16-bit read-only register. It
is located at address 701Eh (in data space).

During the peripheral interrupt acknowledge cycle, the PIVR is loaded with the
interrupt vector of the highest-priority pending interrupt associated with the
CPU interrupt (INTn) being acknowledged (or the phantom interrupt vector).
The PIVR is shown in Figure 2−10.

Figure 2−10. Peripheral Interrupt Vector Register (PIVR) — Address 701Eh

15 14 13 12 11 10 9 8

V15 V14 V13 V12 V11 V10 V9 V8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

7 6 5 4 3 2 1 0

V7 V6 V5 V4 V3 V2 V1 V0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

Note: R = Read access; -0 = value after reset

Bits 15−0 V15−V0. Interrupt vector. This register contains the peripheral interrupt vector
of the most recently acknowledged peripheral interrupt.

2-30
 Peripheral Interrupt Registers

2.10.2 Peripheral Interrupt Request Registers (PIRQR0, 1, 2)

The peripheral interrupt request registers (PIRQRx) enable:

The state of the peripheral interrupt requests to be read

A simulated assertion of a particular peripheral interrupt request

PIRQR0 is shown in Figure 2−11, PIRQR1 is shown in Figure 2−12, and

PIRQR2 is shown in Figure 2−13.

Figure 2−11.Peripheral Interrupt Request Register 0 (PIRQR0) — Address 7010h

15 14 13 12 11 10 9 8

IRQ0.15 IRQ0.14 IRQ0.13 IRQ0.12 IRQ0.11 IRQ0.10 IRQ0.9 IRQ0.8

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

IRQ0.7 IRQ0.6 IRQ0.5 IRQ0.4 IRQ0.3 IRQ0.2 IRQ0.1 IRQ0.0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−0 IRQ0.15−IRQ0.0

0 Corresponding peripheral interrupt is not pending

1 Peripheral Interrupt is pending

Note: Writing a 1 sends IRQ to core; writing a 0 has no effect.

Table 2−3. Peripheral Interrupt Request Descriptions (PIRQR0)

Bit position Interrupt Interrupt Description Interrupt Level
IRQ 0.0 PDPINTA Power device protection interrupt pin INT1
IRQ 0.1 ADCINT ADC interrupt. High priority INT1
IRQ 0.2 XINT1 External interrupt pin 1. High priority INT1
IRQ 0.3 XINT2 External interrupt pin 2. High priority INT1
IRQ 0.4 SPIINT SPI interrupt. High priority INT1
IRQ 0.5 RXINT SCI receiver interrupt. High priority INT1
IRQ 0.6 TXINT SCI transmitter interrupt. High priority INT1
IRQ 0.7 CANMBINT CAN mailbox interrupt. High priority INT1
IRQ 0.8 CANERINT CAN error interrupt. High priority INT1
IRQ 0.9 CMP1INT Compare 1 interrupt INT2

System Configuration and Interrupts 2-31

Peripheral Interrupt Registers

Table 2−3. Peripheral Interrupt Request Descriptions (PIRQR0) (Continued)

Bit position Interrupt Interrupt Description Interrupt Level
IRQ 0.10 CMP2INT Compare 2 interrupt INT2
IRQ 0.11 CMP3INT Compare 3 interrupt INT2
IRQ 0.12 T1PINT Timer 1 period interrupt INT2
IRQ 0.13 T1CINT Timer 1 compare interrupt INT2
IRQ 0.14 T1UFINT Timer 1 underflow interrupt INT2
IRQ 0.15 T1OFINT Timer 1 overflow interrupt INT2

Figure 2−12. Peripheral Interrupt Request Register 1 (PIRQR1) — Address 7011h

15 14 13 12 11 10 9 8

Reserved IRQ1.14 IRQ1.13 IRQ1.12 IRQ1.11 IRQ1.10 IRQ1.9 IRQ1.8

R-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

IRQ1.7 IRQ1.6 IRQ1.5 IRQ1.4 IRQ1.3 IRQ1.2 IRQ1.1 IRQ1.0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

Bit 15 Reserved. Reads return zero, writes have no effect.

Bits 14−0 IRQ1.14−IRQ1.0

0 Corresponding peripheral interrupt is not pending

1 Peripheral Interrupt is pending

Note: Writing a 1 sends IRQ to core; writing a 0 has no effect.

2-32
 Peripheral Interrupt Registers

Table 2−4. Peripheral Interrupt Request Descriptions (PIRQR1)

Bit position Interrupt Interrupt Description Interrupt Level
IRQ 1.0 T2PINT Timer 2 period interrupt INT3
IRQ 1.1 T2CINT Timer 2 compare interrupt INT3
IRQ 1.2 T2UFINT Timer 2 underflow interrupt INT3
IRQ 1.3 T2OFINT Timer 2 overflow interrupt INT3
IRQ 1.4 CAP1INT Capture 1 interrupt INT4
IRQ 1.5 CAP2INT Capture 2 interrupt INT4
IRQ 1.6 CAP3INT Capture 3 interrupt INT4
IRQ 1.7 SPIINT SPI interrupt. Low priority INT5
IRQ 1.8 RXINT SCI receiver interrupt. Low priority INT5
IRQ 1.9 TXINT SCI transmitter interrupt. Low priority INT5
IRQ 1.10 CANMBINT CAN mailbox interrupt. Low priority INT5
IRQ 1.11 CANERINT CAN error interrupt. Low priority INT5
IRQ 1.12 ADCINT ADC interrupt. Low priority INT6
IRQ 1.13 XINT1 External interrupt pin 1. Low priority INT6
IRQ 1.14 XINT2 External interrupt pin 2. Low priority INT6

Figure 2−13. Peripheral Interrupt Request Register 2 (PIRQR2) — Address 7012h

15 14 13 12 11 10 9 8

Reserved IRQ2.14 IRQ2.13 IRQ2.12 IRQ2.11 IRQ2.10 IRQ2.9 IRQ2.8

R-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

IRQ2.7 IRQ2.6 IRQ2.5 IRQ2.4 IRQ2.3 IRQ2.2 IRQ2.1 IRQ2.0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, -0 = value after reset

Bit 15 Reserved.

Bits 14−0 IRQ2.14−IRQ2.0

0 Corresponding peripheral interrupt is not pending

1 Peripheral Interrupt is pending

Note: Writing a 1 sends IRQ to core; writing a 0 has no effect.

System Configuration and Interrupts 2-33

Peripheral Interrupt Registers

Table 2−5. Peripheral Interrupt Request Descriptions (PIRQR2)

Bit position Interrupt Interrupt Description Interrupt Level
IRQ 2.0 PDPINTB Power drive protection interrupt pin INT1
IRQ 2.1 CMP4INT Compare 4 interrupt INT2
IRQ 2.2 CMP5INT Compare 5 interrupt INT2
IRQ 2.3 CMP6INT Compare 6 interrupt INT2
IRQ 2.4 T3PINT Timer 3 period interrupt INT2
IRQ 2.5 T3CINT Timer 3 compare interrupt INT2
IRQ 2.6 T3UFINT Timer 3 underflow interrupt INT2
IRQ 2.7 T3OFINT Timer 3 overflow interrupt INT2
IRQ 2.8 T4PINT Timer 4 period interrupt INT3
IRQ 2.9 T4CINT Timer 4 compare interrupt INT3
IRQ 2.10 T4UFINT Timer 4 underflow interrupt INT3
IRQ 2.11 T4OFINT Timer 4 overflow interrupt INT3
IRQ 2.12 CAP4INT Capture 4 interrupt INT4
IRQ 2.13 CAP5INT Capture 5 interrupt INT4
IRQ 2.14 CAP6INT Capture 6 interrupt INT4

2.10.3 Peripheral Interrupt Acknowledge Registers (PIACKR0, 1, 2)

The peripheral interrupt acknowledge registers (PIACKRx) are memory
mapped to enable an easy test of the peripheral interrupt acknowledges.
There are three of these 16-bit registers; and therefore, the PIE controller can
support up to 48 peripheral interrupts. These registers are generally used for
test purposes only and are not for user applications. PIACKR0 is shown in
Figure 2−14, PIACKR1 is shown in Figure 2−15, and PIACKR2 is shown in
Figure 2−16.

Figure 2−14. Peripheral Interrupt Acknowledge Register 0 (PIACKR0) — Address 7014h

15 14 13 12 11 10 9 8

IAK0.15 IAK0.14 IAK0.13 IAK0.12 IAK0.11 IAK0.10 IAK0.9 IAK0.8

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

IAK0.7 IAK0.6 IAK0.5 IAK0.4 IAK0.3 IAK0.2 IAK0.1 IAK0.0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

2-34
 Peripheral Interrupt Registers

Bits 15−0 IACK0.15−IACK0.0. Peripheral interrupt acknowledge bits. Writing a one

causes the corresponding peripheral interrupt acknowledge to be asserted,
which clears the corresponding peripheral interrupt request. Note that assert-
ing the interrupt acknowledge by writing to this register does not update the
PIVR. Reading the register always returns zeros.

Table 2−6. Peripheral Interrupt Acknowledge Descriptions (PIACKR0)

Bit position Interrupt Interrupt Description Interrupt Level

IAK 0.0 PDPINT Power device protection interrupt pin INT1
IAK 0.1 ADCINT ADC interrupt. High priority INT1
IAK 0.2 XINT1 External interrupt pin 1. High priority INT1
IAK 0.3 XINT2 External interrupt pin 2. High priority INT1
IAK 0.4 SPIINT SPI interrupt. High priority INT1
IAK 0.5 RXINT SCI receiver interrupt. High priority INT1
IAK 0.6 TXINT SCI transmitter interrupt. High priority INT1
IAK 0.7 CANMBINT CAN mailbox interrupt. High priority INT1
IAK 0.8 CANERINT CAN error interrupt. High priority INT1
IAK 0.9 CMP1INT Compare 1 interrupt INT2
IAK 0.10 CMP2INT Compare 2 interrupt INT2
IAK 0.11 CMP3INT Compare 3 interrupt INT2
IAK 0.12 T1PINT Timer 1 period interrupt INT2
IAK 0.13 T1CINT Timer 1 compare interrupt INT2
IAK 0.14 T1UFINT Timer 1 underflow interrupt INT2
IAK 0.15 T1OFINT Timer 1 overflow interrupt INT2

Figure 2−15. Peripheral Interrupt Acknowledge Register 1 (PIACKR1) — Address 7015h

15 14 13 12 11 10 9 8

Reserved IAK1.14 IAK1.13 IAK1.12 IAK1.11 IAK1.10 IAK1.9 IAK1.8

R-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

IAK1.7 IAK1.6 IAK1.5 IAK1.4 IAK1.3 IAK1.2 IAK1.1 IAK1.0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

System Configuration and Interrupts 2-35

Peripheral Interrupt Registers

Bit 15 Reserved. Reads return zero; writes have no effect.

Bits 14−0 IACK1.14−IACK1.0. Bit behavior is the same as that of PIACKR0.

Table 2−7. Peripheral Interrupt Acknowledge Descriptions (PIACKR1)

Bit position Interrupt Interrupt Description Interrupt Level
IAK 1.0 T2PINT Timer 2 period interrupt INT3
IAK 1.1 T2CINT Timer 2 compare interrupt INT3
IAK 1.2 T2UFINT Timer 2 underflow interrupt INT3
IAK 1.3 T2OFINT Timer 2 overflow interrupt INT3
IAK 1.4 CAPINT1 Capture 1 interrupt INT4
IAK 1.5 CAPINT2 Capture 2 interrupt INT4
IAK 1.6 CAPINT3 Capture 3 interrupt INT4
IAK 1.7 SPIINT SPI interrupt. Low priority INT5
IAK 1.8 RXINT SCI receiver interrupt. Low priority INT5
IAK 1.9 TXINT SCI transmitter interrupt. Low priority INT5
IAK 1.10 CANMBINT CAN mailbox interrupt. Low priority INT5
IAK 1.11 CANERINT CAN error interrupt. Low priority INT5
IAK 1.12 ADCINT ADC interrupt. Low priority INT6
IAK 1.13 XINT1 External interrupt pin 1. Low priority INT6
IAK 1.14 XINT2 External interrupt pin 2. Low priority INT6

Figure 2−16. Peripheral Interrupt Acknowledge Register 2 (PIACKR2) — Address 7016h

15 14 13 12 11 10 9 8

Reserved IAK2.14 IAK2.13 IAK2.12 IAK2.11 IAK2.10 IAK2.9 IAK2.8

R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

IAK2.7 IAK2.6 IAK2.5 IAK2.4 IAK2.3 IAK2.2 IAK2.1 IAK2.0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Note: R = read access; W = write access; −0 = value after reset

Bit 15 Reserved.

Bits 14−0 IACK2.14−IACK2.0. Bit behavior is the same as that of PIACKR0.

2-36
 Peripheral Interrupt Registers

Table 2−8. Peripheral Interrupt Acknowledge Descriptions (PIACKR2)

Bit position Interrupt Interrupt Description Interrupt Level

IAK 2.0 PDPINTB Power drive protection interrupt pin INT1
IAK 2.1 CMP4INT Compare 4 interrupt INT2
IAK 2.2 CMP5INT Compare 5 interrupt INT2
IAK 2.3 CMP6INT Compare 6 interrupt INT2
IAK 2.4 T3PINT Timer 3 period interrupt INT2
IAK 2.5 T3CINT Timer 3 compare interrupt INT2
IAK 2.6 T3UFINT Timer 3 underflow interrupt INT2
IAK 2.7 T3OFINT Timer 3 overflow interrupt INT2
IAK 2.8 T4PINT Timer 4 period interrupt INT3
IAK 2.9 T4CINT Timer 4 compare interrupt INT3
IAK 2.10 T4UFINT Timer 4 underflow interrupt INT3
IAK 2.11 T4OFINT Timer 4 overflow interrupt INT3
IAK 2.12 CAP4INT Capture 4 interrupt INT4
IAK 2.13 CAP5INT Capture 5 interrupt INT4
IAK 2.14 CAP6INT Capture 6 interrupt INT4

System Configuration and Interrupts 2-37

Reset
Reset / Illegal Address Detect

2.11 Reset
The 240xA devices have two sources of reset:

An external reset pin

A watchdog timer timeout

The reset pin is an I/O pin. If there is an internal reset event (watchdog timer),
the reset pin is put into output mode and driven low to indicate to external
circuits that the 240xA device is resetting itself.

The external reset pin and watchdog timer reset are ORed together to drive
the reset input to the CPU.

2.12 Illegal Address Detect

The decode logic has the capability to detect accesses to illegal addresses (all
unimplemented addresses including reserved registers in each peripheral’s
memory map). The occurrence of an illegal access sets the illegal address flag
(ILLADR) in System Control and Status Register 1 (SCSR1). See
section 2.2.1, System Control and Status Registers 1 and 2 (SCSR1, SCSR2),
on page 2-3. The detection of an illegal address generates a nonmaskable
interrupt (NMI). The illegal address condition is asserted whenever illegal
addresses are accessed. The illegal address flag (ILLADR) remains set
following an illegal address condition until it is cleared by software. A common
reason for illegal address access (and hence, NMI) is incorrect data page
initialization.

2-38
 External Interrupt Control Registers

2.13 External Interrupt Control Registers

The two external interrupt control registers that control and monitor XINT1 and
XINT2 pin activities are XINT1CR and XINT2CR. In the 240xA devices, the
XINT1 and XINT2 pins must be held low for six (or 12) CLKOUT cycles before
they are recognized by the core.

2.13.1 External Interrupt 1 Control Register (XINT1CR)

Figure 2−17. External Interrupt 1 Control Register (XINT1CR) — Address 7070h

15 14−3 2 1 0

XINT1 flag Reserved XINT1 polarity XINT1 priority XINT1 enable

RC-0 R-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, C = Clear by writing a 1, -0 = value after reset

Bit 15 XINT1 Flag

This bit indicates whether the selected transition has been detected on the
XINT1 pin and is set whether or not the interrupt is enabled. This bit is cleared
by the appropriate interrupt acknowledge, by software writing a 1 (writing a 0
has no effect), or by a device reset.
0 No transition detected
1 Transition detected

Bits 14−3 Reserved. Reads return zero; writes have no effect.

Bit 2 XINT1 Polarity

This read/write bit determines whether interrupts are generated on the rising
edge or the falling edge of a signal on the pin.
0 Interrupt generated on a falling edge (high-to-low transition)
1 Interrupt generated on a rising edge (low-to-high transition)

Bit 1 XINT1 Priority

This read/write bit determines which interrupt priority is requested. The CPU
interrupt priority levels corresponding to low and high priority are coded into
the peripheral interrupt expansion controller. These priority levels are shown
in Table 2−2, 240xA Interrupt Source Priority and Vectors, in Chapter 2 on
page 2-9.
0 High priority
1 Low priority

System Configuration and Interrupts 2-39

External Interrupt Control Registers

Bit 0 XINT1 Enable

This read/write bit enables or disables external interrupt XINT1.

0 Disable interrupt
1 Enable interrupt

2.13.2 External Interrupt 2 Control Register (XINT2CR)

Figure 2−18. External Interrupt 2 Control Register (XINT2CR) — Address 7071h

15 14−3 2 1 0

XINT2 flag Reserved XINT2 polarity XINT2 priority XINT2 enable

RC-0 R-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, C = Clear by writing a 1, -0 = value after reset

Bit 15 XINT2 Flag

This bit indicates whether the selected transition has been detected on the
XINT2 pin, and is set whether or not the interrupt is enabled. This bit is cleared
by the appropriate interrupt acknowledge, by software writing a 1 (writing a 0
has no effect), or by a device reset.
0 No transition detected
1 Transition detected

Bits 14−3 Reserved. Reads return zero; writes have no effect.

Bit 2 XINT2 Polarity

This read/write bit determines whether interrupts are generated on the rising
edge or the falling edge of a signal on the pin.
0 Interrupt generated on a falling edge (high-to-low transition)
1 Interrupt generated on a rising edge (low-to-high transition)

Bit 1 XINT2 Priority

This read/write bit determines which interrupt priority is requested. The CPU
interrupt priority levels corresponding to low and high priority are coded into
the peripheral interrupt expansion controller. These priority levels are shown
in Table 2−2, 240xA Interrupt Source Priority and Vectors, in Chapter 2 on
page 2-9.
0 High priority
1 Low priority

2-40
 External Interrupt Control Registers

Bit 0 XINT2 Enable

This read/write bit enables or disables the external interrupt XINT2.

0 Disable interrupt
1 Enable interrupt

System Configuration and Interrupts 2-41

2-42
 Chapter 3

 

This chapter describes the RAM, ROM, and Flash availability on the 240xA.

In addition to single-access RAM (SARAM) and dual-access RAM (DARAM

− B0, B1, B2), which is part of the CPU core, the 240xA devices include flash
EPROM or ROM for additional on-chip program memory. Devices with an LF
prefix are flash devices and those with an LC prefix are ROM devices.

The 2407A device has a 16-bit address bus that can access the following three
individually selectable spaces (192K words total):

64K-word program space

64K-word data space

64K-word I/O space

This chapter shows memory maps for program, data, and I/O spaces. It also
describes available 240xA memory configuration options.

Topic Page

3.1 On-Chip RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2 Factory Masked On-Chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.4 Overview of Memory and I/O Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.5 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.6 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.7 I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.8 XMIF Qualifier Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.9 Program and Data Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.10 I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.11 Wait-State Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

3-1
On-Chip RAM

3.1 On-Chip RAM

The 240xA on-chip RAM includes on-chip dual-access RAM (DARAM) and
on-chip single-access program/data RAM (SARAM).

3.1.1 Dual-Access On-Chip RAM

All Lx240xA devices have 544 words × 16 bits of on-chip DARAM, which can
be accessed twice per machine cycle. The 544 words are divided into three
blocks: B0, B1, and B2. This memory is primarily intended to hold data but, in
the case of B0, can also hold programs. B0 can be configured in one of two
ways depending on the value of the CNF bit. CNF = 0 maps B0 in data memory,
while CNF = 1 maps B0 in program memory.

In the pipeline operation, the CPU reads data on the third cycle and writes data
on the fourth cycle. However, DARAM allows the CPU to write and read in one
cycle; the CPU writes to DARAM on the master phase of the cycle and reads
from DARAM on the slave phase. For example, suppose two instructions, A
and B, store the accumulator value to DARAM and load the accumlator with
a new value from DARAM. Instruction A stores the accumulator value during
the master phase of the CPU cycle, and instruction B loads the new value to
the accumulator during the slave phase. Because part of the dual-access
operation is a write, it only applies to RAM.

3.1.2 Single-Access On-Chip Program/Data RAM

Some of the Lx240xA devices have up to 2K 16-bit words of single-access
RAM (SARAM). The addresses associated with the SARAM can be used for
both data memory and program memory, and are software configurable to
either external memory or the internal SARAM.

When configured as external, these addresses can be used for off-chip

program memory. SARAM is accessed only once per CPU cycle. When the
CPU requests multiple accesses, the SARAM schedules the accesses by
providing a not-ready condition to the CPU and then executing the accesses
one per cycle. For example, if the instruction sequence involves storing the
accumulator value and then loading a value to the accumulator, it would take
two cycles to complete in SARAM, compared to one cycle in DARAM.

3-2
 FactoryFactory
MaskedMasked
On-ChipOn-Chip ROM
ROM / Flash

3.2 Factory Masked On-Chip ROM

The on-chip ROM in ROM devices is mapped in program memory space. This
ROM is always enabled since these devices lack an external memory
interface. This ROM is programmed with customer-specific code.

3.3 Flash
The on-chip flash in flash devices is mapped in program memory space. This
flash memory is always enabled in devices that lack an external memory
interface. For the 2407A, which has an external memory interface, the MP/MC
pin determines whether the on-chip program memory (flash) or the off-chip
program memory (customer design specific) is accessed.

3.3.1 Flash Program Memory

The Flash module is used to provide permanent program storage. The Flash
can be programmed and electrically erased many times to allow code
development. The 240xA Flash is similar to that on the 24x devices, with some
key differences and enhancements. 240xA Flash features are as follows:

Flash run-time execution at 3.3 V

Flash programming requires a 5-V supply (±5%) at VCCP pin

Flash has multiple sectors that can be protected while erasing

Flash programming registers are similar to those on the 24x devices

Flash programming is done through CPU

240xA devices come with JTAG interface to aid programming and emula-
tion

A 256-word Boot ROM is available on 240xA devices to enable program-

ming through SCI or SPI ports

The following sections explain the Flash programming registers and their bit
functions. Flash programming utilities will be provided by Texas Instruments
(TI). Refer to the TI’s web page (www.ti.com, under 24x Flash tools) for
revisions of these utilities.

3.3.2 Flash Control Mode Register (FCMR)

The Flash control mode register is in internal I/O space FF0Fh. This register
is a dummy register address to enable the Flash in Flash array mode or in
Flash control register mode.

Memory 3-3
Flash

The Flash control registers are used to program the Flash array. These
registers are a part of the Flash wrapper and are mapped at the same start
address as the Flash array itself. These registers are not visible (disabled)
during Flash array mode (i.e., Flash read). During the Flash control register
mode, the Flash program control registers are enabled and the Flash array is
disabled (i.e., not accessible to CPU).

3.3.3 Flash Control Register Access

In addition to the flash memory array, the flash module has four registers that
control operations on the flash array. At any given time, you can access the
memory array in the flash module (array-access mode) or you can access the
control registers (register-access mode) but you cannot access both
simultaneously. The flash module has a flash-access control register that
selects between the two access modes. This register is the flash control mode
register (FCMR) and is mapped at FF0Fh in I/O space. This is a special type
of I/O register that cannot be read. The register functions as follows:

An OUT instruction, using the register address as an I/O port, places the
flash module in register-access mode. The data operand used is insignifi-
cant. For example:
OUT dummy, 0FF0Fh; Selects register-access mode

An IN instruction, using the register address as an I/O port, places the flash
module in array-access mode. The data operand used is insignificant. For
example:
IN dummy, 0FF0Fh; Selects array-access mode

The flash array is not directly accessible as memory in register-access mode,

and the control registers are not directly accessible in array-access mode.
When operating as a program memory to store code, the flash module
operates in array-access mode. In user applications, the FCMR is used to
power down the flash prior to entering the LPM2 mode.

3.3.4 Flash Programming at Variable Frequencies

The embedded flash EEPROM on LF240x/LF240xA devices can be
programmed at frequencies ranging from 15 MHz to 40 MHz. For information
on configuring the flash programming utilities to program the flash at any
particular frequency, refer to the documentation included with the flash
programmaing utilities.

3-4
 Flash / Overview of Memory and I/O Spaces

In the case of serial port flash programming utilities, the available number of
frequencies is limited further by the serial port synchronization protocol
implemented within the Boot ROM. See Appendix C, TMS320F240x Boot
ROM Loader: Protocols and Interfacing.

3.4 Overview of Memory and I/O Spaces

The 240xA design is based on an enhanced Harvard architecture. These
devices have multiple memory spaces accessible on three parallel buses: a
program address bus (PAB), a data-read address bus (DRAB), and a
data-write address bus (DWAB). Each of the three buses access different
memory spaces for different phases of the device’s operation. Because the
bus operations are independent, it is possible to access both the program and
data spaces simultaneously. Within a given machine cycle, the CALU can
execute as many as three concurrent memory operations.

The 240xA address map is organized into three individually selectable spaces:

Program memory (64K words) contains the instructions to be executed,

as well as immediate data used during program execution.

Data memory (64K words) holds data used by the instructions.

Input/output (I/O) space (64K words) interfaces to external peripherals

and may contain on-chip registers.

These spaces provide a total address space of 192K words. The 240xA
devices include on-chip memory to aid in system performance and integration.

The advantages of operating from on-chip memory are:

Higher performance than external memory (because the wait states re-
quired for slower external memories are avoided)

Lower cost than external memory

Lower power consumption than external memory

The advantage of operating from external memory is the ability to access a

larger address space. Only the 2407A has an external memory interface.
Other devices have only on-chip memory. Refer to the device data sheets for
the corresponding memory maps.

Memory 3-5
Program Memory

3.5 Program Memory

In addition to storing the user code, the program memory also stores
immediate operands and table information. A maximum of 64K 16-bit words
can be addressed in the program memory for 240xA. This number includes
on-chip DARAM and flash EEPROM/ROM. Whenever an off-chip memory
location needs to be accessed, the appropriate control signals for external
access (PS, DS, STRB, etc.) are automatically generated.

Figure 3−1 shows the LF2407A program memory map.

Figure 3−1. Program Memory Map for LF2407A

0000h
Interrupt Reset 0000h−0001h
vectors
003Fh Interrupt level 1 0002h−0003h
0040h Code security passwords
0043h Interrupt level 2 0004h−0005h
0044h
User code in Interrupt level 3 0006h−0007h
flash memory Interrupt level 4 0008h−0009h
7FFFh
8000h Interrupt level 5 000Ah−000Bh
External

ÇÇÇÇÇÇÇÇ
Interrupt level 6 000Ch−000Dh
FDFFh

ÇÇÇÇÇÇÇÇ
FE00h Reserved 000Eh−000Fh
Reserved

ÇÇÇÇÇÇÇÇ
(CNF = 1) Software interrupts 0010h−0021h

ÇÇÇÇÇÇÇÇ
FEFF
FF00
(External if CNF = 0)

On-chip
TRAP
NMI
0022h−0023h
0024h−0025h
DARAM (B0) Reserved 0026h−0027h
(CNF = 1)
(External if CNF = 0) Software interrupts 0028h−003Fh
FFFF
32K on-chip flash (MP/MC = 0)
External (MP/MC = 1)

3.5.1 Program Memory Configuration

Two factors determine the configuration of program memory:

CNF bit. The CNF bit (bit 12) of status register ST1 determines whether
DARAM B0 is in on-chip program space:
 CNF = 0. The 256 words are mapped as external memory.
 CNF = 1. The 256 words of DARAM B0 are configured for program
use. At reset, B0 is mapped to data space (CNF = 0).

3-6
 Program Memory

MP/MC pin. The level on the MP/MC pin determines whether program
instructions are read from on-chip flash/ROM or external memory:
 MP/MC = 0. The device is configured in microcontroller mode. The on-
chip ROM/flash EEPROM is accessible. The device fetches the reset
vector from on-chip memory. Accesses to program memory
addresses 0000h−7FFFh will be made to on-chip memory in the case
of 2407A. Refer to the respective memory maps for other devices.
 MP/MC = 1. The device is configured in microprocessor mode. The
device fetches the reset vector from external memory. Accesses to
program memory addresses 0000h−7FFFh will be made to off-chip
memory of the 2407A. Refer to the respective memory maps for other
devices.
Regardless of the value of MP/MC, the 240xA fetches its reset vector at
location 0000h in program memory. Note that there is no MP/MC pin avail-
able on devices that lack an external memory interface.

Memory 3-7
Data Memory

3.6 Data Memory

Data memory space addresses up to 64K of 16-bit words. 32K words are
internal memory (0000h to 7FFFh). Internal data memory includes
memory-mapped registers, DARAM, and peripheral memory-mapped
registers. The remaining 32K words of memory (8000h to FFFFh) form part of
the external data memory. Note that addresses 8000h−FFFFh are not
accessible in 2406A, 2404A, and 2402A.

Figure 3−2 shows the data memory map for the 2407A. Each device has three
on-chip DARAM blocks: B0, B1, and B2. B0 is configurable as data memory
or program memory. It is the same memory block accessible either as data
memory or program memory, depending on the CNF bit. Blocks B1 and B2 are
available for data memory only. External data memory is available only on the
2407A.

Data memory can be addressed with either of two addressing modes:

direct-addressing or indirect-addressing.

When direct addressing is used, data memory is addressed in blocks of

128 words called data pages. Figure 3−3 shows how these blocks are
addressed. The entire 64K of data memory consists of 512 data pages labeled
0 through 511. The current data page is determined by the value in the 9-bit
data page pointer (DP) in status register ST0. Each of the 128 words on the
current page is referenced by a 7-bit offset taken from the instruction that is
using direct addressing. Therefore, when an instruction uses direct
addressing, you must specify both the data page (with a preceding instruction)
and the offset (in the instruction that accesses data memory).

An access to the following address spaces in the data memory is illegal and
generates an NMI. In addition to these addresses, an access to any of the
reserved addresses within the peripheral register maps is also illegal.

0080h−00FFh 710Fh−71FFh (inside CAN)

0500h−07FFh 7230h−73FFh (partly inside CAN)
1000h−700Fh 7440h−74FFh
7030h−703Fh 7540h−75FFh
7060h−706Fh 7600h−77EFh
77F4 − 7FFFh
7080h−708Fh 8000h−FFFFh (on 2406A, 2404A, and 2402A only)
70C0h−70FFh

3-8
 Data Memory

Figure 3−2. 2407A Peripheral Memory Map

Hex Hex
0000 0000
Reserved
Memory-mapped registers 0003
and reserved Interrupt-mask register 0004
005F

ÈÈÈÈÈÈÈÈÈ
0060 Reserved 0005
On-chip DARAM B2

ÈÈÈÈÈÈÈÈÈ
007F Interrupt flag register
0080 0006
Illegal Emulation registers 0007

ÈÈÈÈÈÈÈÈÈ
00FF and reserved 005F

ÈÈÈÈÈÈÈÈÈ
0100
Reserved Illegal 7000−700F
01FF System configuration and
0200 7010−701F

ÈÈÈÈÈÈÈÈÈ
control registers
On-chip DARAM B0

ÈÈÈÈÈÈÈÈÈ
Watchdog timer registers 7020−702F
02FF
0300 Illegal 7030−703F
On-chip DARAM B1
03FF

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
0400 SPI 7040−704F
Reserved
SCI 7050−705F

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
04FF
0500 Illegal Illegal 7060−706F

ÈÈÈÈÈÈÈÈÈ
07FF
0800 External-interrupt registers 7070−707F

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
SARAM (2K)
0FFF Illegal 7080−708F

ÈÈÈÈÈÈÈÈÈ
1000
Illegal Digital I/O control registers 7090−709F

ÈÈÈÈÈÈÈÈÈ
6FFF
7000 ADC control registers 70A0−70BF

ÈÈÈÈÈÈÈÈÈ
Peripheral frame 1 (PF1)
73FF Illegal 70C0−70FF
7400

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
Peripheral frame 2 (PF2)
743F CAN control registers 7100−710E

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
7440 Illegal Illegal 710F−71FF

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
74FF
7500 CAN mailbox 7200−722F
Peripheral frame 3 (PF3)

ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ
753F Illegal 7230−73FF
7540 Illegal
77EF Event manager − EVA
77F0
Code security passwords General-purpose timer registers 7400−7408
77F3

ÈÈÈÈÈÈÈÈÈ
77F4 Compare, PWM, and
7411−7419
Reserved deadband registers

ÈÈÈÈÈÈÈÈÈ
77FF
Capture and QEP registers 7420−7429
7800

ÈÈÈÈÈÈÈÈÈ
Illegal Interrupt mask, vector, and
7FFF 742C−7431
8000 flag registers
External†
Illegal 7432−743F

ÈÈÈÈ
FFFF
Event manager − EVB

ÈÈÈÈ “Illegal” indicates that access to these General-purpose timer registers 7500−7508

ÈÈÈÈ
Illegal addresses causes a nonmaskable
Compare, PWM, and
interrupt (NMI). 7511−7519
deadband registers
“Reserved” indicates addresses that are Capture and QEP registers 7520−7529
Reserved reserved for test.
Interrupt mask, vector, and
752C−7531
flag registers
† Available in LF2407A only
Reserved 7532−753F

Memory 3-9
Data Memory

Figure 3−3. Data Memory Pages

DP Value Offset Data memory
0000 0000 0 000 0000
. .
. . Page 0: 0000h−007Fh
. .
0000 0000 0 111 1111
0000 0000 1 000 0000
. .
. . Page 1: 0080h−00FFh
. .
0000 0000 1 111 1111
0000 0001
. 0 000 .0000
. . Page 2: 0100h−017Fh
. .
0000 0001 0 111 1111 .
. . .
. . .
. . .
. . .
. . .
. . .

1111 1111 1 000 0000

. .
. . Page 511: FF80h−FFFFh
. .
1111 1111 1 111 1111

Data Page 0 Address Map

The data memory also includes the device’s memory-mapped registers

(MMR), which reside at the top of data page 0 (addresses 0000h−007Fh).
Note the following:

The two registers that can be accessed with zero wait states are:

 Interrupt mask register (IMR)

 Interrupt flag register (IFR)

The test/emulation reserved area is used by the test and emulation sys-
tems for special information transfers.

Note: Do Not Write to Test/Emulation Addresses

Writing to the test/emulation addresses can cause the device to change its
operating mode, and therefore, affect the operation of an application.

3-10
 Data Memory

The scratch-pad RAM block (B2) includes 32 words of DARAM that pro-
vide for variable storage without fragmenting the larger RAM blocks,
whether internal or external. This RAM block supports dual-access opera-
tions and can be addressed via any data-memory addressing mode.

Table 3−1 shows the address map of data page 0.

Table 3−1. Data Page 0 Address Map

Address Name Description

0000h−0003h − Reserved

0004h IMR Interrupt mask register

0005h − Reserved

0006h IFR Interrupt flag register

0023h−0027h − Reserved

002Bh−002Fh − Reserved for test/emulation

0060h−007Fh B2 Scratch-pad RAM (DARAM B2)

Data Memory Configuration

Two factors that contribute to the configuration of data memory are:

CNF bit. The CNF bit (bit 12) of status register ST1 determines whether
the on-chip DARAM B0 is mapped to data space or program space.
 CNF = 1. B0 is used for program space.
 CNF = 0. B0 is used for data space.
At reset, B0 is mapped into data space (CNF = 0).

3.6.1 Global Data Memory

Note:
Global Data Memory is not available in the 240xA. Hence, the global memory
allocation register (GREG) is a reserved location and should not be ac-
cessed.

Memory 3-11
I/O Space

3.7 I/O Space

The I/O-space memory addresses up to 64K 16-bit words. Figure 3−4 shows
the I/O space address map for the 2407A.

Figure 3−4. I/O Space Address Map for 2407A

0000h

External

ÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇ
FEFF
FF00

FF0E ÇÇÇÇÇÇÇ Reserved

Flash control
FF0F
mode register†

ÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇ
FF10
Reserved
FFFE
Wait-state generator
FFFF control register‡

† Available only on Flash devices.

‡ Available only on LF2407A.
Note: There is no I/O space in ROM devices.

3-12
 XMIF Qualifier Signal Description

3.8 XMIF Qualifier Signal Description

The 240xA can address the following memory sizes in each of the external
memory spaces:

Ext. Memory Space Size (in words) Qualifier signal (strobe)

Program space 64K PS
Data space 64K DS
I/O space 64K IS

The signals that define the XMIF are given in Table 3−2.

Table 3−2. XMIF Signal Descriptions

Signal/s name Signal description

A(0:15) External 16-bit unidirectional address bus.
D(0:15) External 16-bit bidirectional data bus.
PS Program space strobe
DS Data space strobe
IS I/O space strobe
STRB External memory access strobe
WE Write strobe
RD Read strobe
R/W Read / Write qualifier
MP/MC Microprocessor/microcontroller selection pin
VIS OE Is active low whenever the external data bus is driving
as an output during visibility mode. Can be used by
external decode logic to prevent data bus contention
while running in visibility mode
ENA 144 If pulled low, the 2407A device behaves like a
2402A/2404A/2406A; that is, has no external memory
and generates an Illegal address if any of the 3 exter-
nal spaces are accessed.
This pin has an internal pull-down resistor, so when
left disconnected, device behaves appropriately.

Note: These signals allow external memory such as SRAM to be interfaced to

the 240xA in the conventional way.

Figure 3−5 and Figure 3−6 show Visibility mode timing diagrams.

Memory 3-13
XMIF Qualifier Signal Description

Figure 3−5. Program Address/Data — Visibility Functional Timing

 DECODE
FETCH  OPERAND FETCH
 EXECUTE

A0−A15 Op-code addr Op-code addr

D0−D15 Op-code Op-code

STRB

VIS OE

3-14
 XMIF Qualifier Signal Description

Figure 3−6. Data Address/ Data — Visibility Functional Timing

 DECODE
FETCH  OPERAND FETCH
 EXECUTE

A0−A15 Op-code addr Op-code addr

D0−D15 Op-code Op-code

STRB

VIS OE

R/W

Memory 3-15
Program
Program and
and Data
Data Spaces
Spaces / I/O Space

3.9 Program and Data Spaces

PS and STRB are inactive (high) for accesses to on-chip program memory and
data memory. The external data and address busses are active only when
accesses are made to external memory locations, except when in bus visibility
(BVIS) mode (see section 3.11, Wait-State Generation).

Two cycles are required on all external writes, including a half-cycle before WE
goes low and a half-cycle after WE goes high. This prevents data contention
on the external buses.

3.10 I/O Space

I/O space accesses are distinguished from program and data memory
accesses by IS going low. All 64K I/O words (external I/O port and on-chip I/O
registers) are accessed via the IN and OUT instructions.

While accesses are made to the on-chip I/O mapped registers, signals IS and
STRB are made inactive, that is, driven to the high state. The external address
and data bus is only active when accesses are made to external I/O memory
locations.

Two cycles are required on all external writes, including a half-cycle before WE
goes low and a half-cycle after WE goes high. This prevents data contention
on the external busses.

3-16
 Wait-State Generation

3.11 Wait-State Generation

Wait states are necessary when you want to interface the 2407A with slower
external logic and memory. By adding wait states, you lengthen the time the
CPU waits for external memory or an external I/O port to respond when the
CPU reads from or writes to that memory or port. Specifically, the CPU waits
one extra cycle (one CLKOUT cycle) for every wait state. The wait states
operate on CLKOUT cycle boundaries.

To avoid bus conflicts, writes from the 2407A always take at least two
CLKOUT cycles. The 2407A offers two options for generating wait states:

The READY signal. With the READY signal, you can externally generate
any number of wait states.

The on-chip wait-state generator. With this generator, you can generate
zero to seven wait states.

3.11.1 Generating Wait States With the READY Signal

When READY is low, the 2407A waits one CLKOUT cycle and checks READY
again. The 2407A will not continue executing until READY is driven high;
therefore, if the READY signal is not used, it should be pulled high during
external accesses.

The READY pin can be used to generate any number of wait states. However,
when the 2407A operates at full speed, it cannot respond fast enough to
provide a READY-based wait state for the first cycle. For extended wait states
using external READY logic, the on-chip wait-state generator must be
programmed to generate at least one wait state.

Note: The READY pin has no effect on accesses to internal memory.

3.11.2 Generating Wait States With the 2407A Wait-State Generator

The software wait-state generator can be programmed to generate zero to
seven wait states for a given off-chip memory space (program, data, or I/O).
This wait-state generator has the bit fields shown in Figure 3−7 and described
after the figure.

Memory 3-17
Wait-State Generation

Figure 3−7. 2407A Wait-State Generator Control Register (WSGR) —

I/O-Space Address FFFFh (2407A)
15−11 10−9 8−6 5−3 2−0

Reserved BVIS ISWS DSWS PSWS

0 W-11 W-111 W-111 W-111

Note: 0 = Always read as zeros: W = Write access: -n = value after reset

Bits 15−11 Reserved. Bits 15−11 are reserved and always read as 0s.

Bits 10−9 Bus visibility modes. Bits 10−9 allow selection of various bus visibility modes
while running from internal program and/or data memory. These modes pro-
vide a method of tracing internal bus activity.
Bit 10 Bit 9 Visibility mode
0 0 Bus visibility OFF (reduces power and noise)
0 1 Bus visibility OFF (reduces power and noise)
1 0 Data-address bus output to external address bus
Data-data bus output to external data bus
1 1 Program-address bus o/p to external address bus
Program-data bus output to external data bus

Note: On the 2407A device, the bus visibility is turned off until the device is
unsecured.

Bits 8−6 ISWS — I/O-space wait-state bits. Bits 8−6 determine the number of wait
states (0−7) that are applied to reads from and writes to off-chip I/O space. At
reset, the three ISWS bits become 111, setting seven wait states for reads from
and writes to off-chip I/O space.

Bits 5−3 DSWS — Data-space wait-state bits. Bits 5−3 determine the number of wait
states (0−7) that are applied to reads from and writes to off-chip data space.
At reset, the three DSWS bits become 111, setting seven wait states for reads
from and writes to off-chip data space.

Bits 2−0 PSWS — Program-space wait-state bits. Bits 2−0 determine the number of
wait states (0−7) that are applied to reads from and writes to off-chip program
space. At reset, the three PSWS bits become 111, setting seven wait states
for reads from and writes to off-chip program space.

Table 3−3 shows how to set the number of wait states you want for each type
of off-chip memory.

3-18
 Wait-State Generation

Table 3−3. Setting the Number of Wait States With the 2407A WSGR Bits
ISWS Bits DSWS PSWS
8 7 6 I/O WS 5 4 3 Data WS 2 1 0 Prog WS
0 0 0 0 0 0 0 0 0 0 0 0

0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 2 0 1 0 2 0 1 0 2

0 1 1 3 0 1 1 3 0 1 1 3

1 0 0 4 1 0 0 4 1 0 0 4

1 0 1 5 1 0 1 5 1 0 1 5

1 1 0 6 1 1 0 6 1 1 0 6

1 1 1 7 1 1 1 7 1 1 1 7

In summary, while the READY signal remains high,the wait-state generator

inserts from zero to seven wait states to a given memory space, depending on
the values of PSWS, DSWS, and ISWS. The READY signal may then be
driven low to generate additional wait states. If m is the number of CLKOUT
cycles required for a particular read or write operation and w is the number of
wait states added, the operation will take (m + w) cycles. At reset, all WSGR
bits are set to 1, making seven wait states the default for every memory space.

Memory 3-19
3-20
 Chapter 4

 !"#$" 

The 240xA devices use the phase-locked loop (PLL) circuit embedded in the
240xA CPU core to synthesize the on-chip clocks from a lower frequency
external clock.

Topic Page

4.1 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.2 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.3 Watchdog Timer Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4-1
Pins
Pins / Phase-Locked Loop (PLL)

4.1 Pins
There are three device pins associated with clocks:

XTAL1/CLKIN − This is the clock input from the external crystal to the on-
chip oscillator. If an external oscillator is used, its output must be con-
nected to this pin.

XTAL2 − This is the clock output from the on-chip oscillator to drive the
external crystal.

CLKOUT/IOPE0 − This is the clock output pin. It is multiplexed with GPIO

pin IOPE0. This pin can be used to output the device (CPU) clock or the
watchdog timer clock. The clock select control bits are in System Control
and Status Register 1 (SCSR1), described in section 2.2.1 on page 2-3.
This pin is configured to output CLKOUT from the CPU following a device
reset.

4.2 Phase-Locked Loop (PLL)

The PLL used in the 240xA device is different than the one used in the 24x
device. The 240xA PLL supports multiplication factors ranging from 0.5 to
4 times the input clock frequency.

4.2.1 Overview
This module contains a phased-locked loop (PLL), crystal oscillator, clock
monitor circuit, clock enable circuit, and prescaler.

The purpose of using a PLL is to multiply the external frequency reference to

a higher frequency for use internally. This avoids having high frequency
signals sent to externally packaged pins, which could cause excessive EMI.
PLLs also avoid the use of crystals above 20 − 25 MHz. Such crystals usually
operate in overtone mode and require extra tank circuit components.

The advantages of using a PLL-based clock module are:

1) Lower EMI due to lower external oscillator frequencies.

2) Lower cost crystals and resonators can be used.
3) Avoids overtone crystals that require tank circuits.

The PLL’s main disadvantage over a simple oscillator is that they can be
sensitive to noise if proper board decoupling/layout practices are not adhered
to, and thus, require more system-level design effort to insure low jitter, robust
operation.

4-2
 Phase-Locked Loop (PLL)

Main features:

Oscillator operates with both resonators and crystals

Covers external CLKIN frequencies from 4 MHz to 20 MHz

External low-pass loop filter allows maximum flexability and trade-off

between acquisition time and noise immunity

Phase-frequency detector assures lock to the fundamental reference

frequency

Terms applicable to the PLL module:

Charge Pump (CP): a circuit used to convert the pulse-width modulated

correction signals into an analog control voltage.

Electro-Magnetic Interference (EMI): the radio frequency noise radiated

by a circuit which could disturb the proper operation of other equipment;
the radio frequency noise radiated by other equipment which could disturb
the proper operation of the subject circuit.

Jitter : The maximum positive or negative deviation of a clock edge with

respect to it’s normal position within a single clock period expressed in
nanoseconds or in percent of one clock period.

Lock: The condition in which the PLL’s output is synchronized to the phase
and frequency of it’s reference input.

Phase-Frequency Detector (PFD): a circuit which compares two signals

in both phase and frequency. It is not fooled by one signal being a
harmonic or sub-harmonic of the other signal.

Phase Locked Loop(PLL): an oscillator circuit whose output frequency is

typically an integer multiple of it’s reference input frequency.

Voltage Controlled Oscillator (VCO): an oscillator whose output frequency

is proportional to a control voltage input.

Clocks and Low-Power Modes 4-3

Phase-Locked Loop (PLL)

4.2.2 Operation
The sections that follow describe the operation and operating modes of the
PLL.

4.2.2.1 Resonator/Crystal Oscillator

The oscillator requires two external pins: XTAL1/CLKIN and XTAL2 which are
connected to the resonator/crystal and load capacitors (Figure 4−1). The
oscillator is a single-stage inverter held in bias by an integrated bias resistor.
This resistor is disabled only during leakage test measurements and HALT
mode.

Figure 4−1. Reference Resonator/Crystal

VSS (near osc pins)

To reduce EMI, Board ground

keep all of Ca
XTAL1/CLKIN
these routes
short and
minimize loop Resonator
areas. Y1 Resonator oscillator
XTAL2

Cb

Clock Module

Note: Validating Resonator/Crystal Vendors

Texas Instruments strongly encourages each customer to submit samples
of the device to the resonator/crystal vendor for validation. They are
equipped to determine which load capacitors will best tune their resonator/
crystal to the DSP for optimum start-up and operation over temperature/
voltage extremes. They also factor in a margin for the device process
variations.

4.2.2.2 External Oscillator

The PLL can also be driven by an external oscillator whose output is connected
to XTAL1/CLKIN pin. XTAL2 is left open in this case.

4-4
 Phase-Locked Loop (PLL)

4.2.2.3 Loop Filter Components

The 240xA PLL needs external R-C components for the loop filter (see device
data sheet for more details). Keep the loop filter (R1, C2, and C2) components
close to their pins (PLLF and PLLF2). This is the primary entry point for noise
which can result in increased jitter.

All PCB traces pertaining to the PLL circuit must be kept as short as possible.
In addition, the loop area formed by the loop filter components, PCB traces,
and DSP chip should be as small as possible. A bypass capacitor (0.1 µF to
0.01 µF, ceramic) should be connected between the PLLVCCA and VSS pins.

4.2.2.4 Power Connections

The diagram of Figure 4−2 illustrates how to minimize jitter and EMI by
properly filtering VDD, and by using private traces up to the pins as much as
possible.

While Cbypass is required for proper circuit operation, the “T” filter is optional
and is needed only if minimal CPU CLOCK jitter is required in the application.
This is a function of the amount of system noise on the circuit board. Because
this noise is difficult to quantify, optimal results are obtained experimentally.

Figure 4−2. Power and Ground Connections

PLLF

Loop-filter
components
(Make no other connections to
PLLF, PLLF2 pins)
PLLF2
Clock module
Optional filter circuit
fc = 10 MHz
VDD
L1 L2 PLLVCCA
Cf Cbypass

VSS

(Pick VSS pin nearest to PLLVCCA pin)

Clocks and Low-Power Modes 4-5

Phase-Locked Loop (PLL)

You should adhere to the following guidelines when connecting the PLL pins:

1) Connect the VCCA pin to the low-pass T filter with short leads. This 10-MHz
cutoff filter is not essential but may improve jitter significantly and reduce
EMI.
2) Keep the traces short to ensure that Cbypass (0.01 to 0.1 µF ceramic) is
closely coupled to the VCCA and VSS pins.
3) Minimize the loop area formed by these traces, the chip, and the bypass
capacitor. Large loop areas increase EMI. Avoid nearby noisy traces
which may couple noise back into the clock module pins.

4.2.3 PLL-Bypass Mode

The 240x/240xA devices feature a mode in which the on-chip PLL can be
bypassed. This mode is entered by pulling the TRST, TMS, and TMS2 pins low
upon reset. In this mode, not only is the PLL bypassed, but so is the PLL clock
prescaler. Therefore, changing SCSR1 register bits 11,10, and 9 in bypass
mode will have no effect. The only way to change the speed in bypass mode
is to change the input frequency. For example, if a CPU clock speed of 30 MHz
is desired, then a 30 MHz CLKIN must be supplied. To summarize, the device
operates at the same speed as the input clock frequency. The external loop
filter components are not needed in the bypass mode.

4.2.3.1 Input Clock Specification in PLL-Bypass Mode

If the on-chip oscillator is used (i.e., a quartz crystal/ceramic resonator is

used as the clock source), then the min and max CLKIN frequencies are
4 MHz and 20 MHz, respectively.

If the on-chip oscillator is not used (i.e., an external oscillator is used as

the clock source), then the min and max CLKIN frequencies are 4 MHz
and 40 MHz (30 MHz for 240x devices), respectively.

4-6
 Watchdog Timer Clock

4.3 Watchdog Timer Clock

A low frequency clock, WDCLK, is used to clock the watchdog timer. WDCLK
has a nominal frequency of 78125 Hz when CPUCLK = 40 MHz. WDCLK is
derived from the CLKOUT of the CPU. This ensures that the watchdog timer
continues to count when the CPU is in IDLE1 or IDLE 2 mode (see section 4.4,
Low-Power Modes, on page 4-8).

The WDCLK is generated in the watchdog timer peripheral.

WDCLK = CLKOUT
512

4.3.1 Watchdog Suspend

WDCLK is stopped when the CPU’s suspend signal goes active. This is
achieved by stopping the clock input to the clock divider, which generates
WDCLK from CLKIN.

Clocks and Low-Power Modes 4-7

Low-Power Modes

4.4 Low-Power Modes

The 240xA has an IDLE instruction. When executed, the IDLE instruction
stops the clocks to all circuits in the CPU; however, the clock output from the
CPU continues to run. With this instruction, the CPU clocks can be shut down
to save power. The CPU exits the IDLE state if it resets or if it receives an
interrupt request.

4.4.1 Clock Domains

All 240xA-based devices have the following two clock domains:

The CPU clock domain consists of the clock for most of the CPU logic.

The system clock domain consists of the peripheral clock (which is derived
from CLKOUT of the CPU) and the clock for the interrupt logic in the CPU.
When the CPU goes into IDLE mode, the CPU clock domain is stopped while
the system clock domain continues to run. This mode is also known as IDLE1
mode. The 240xA CPU contains support for a second IDLE mode, IDLE2,
implemented in external logic. By asserting the IDLE2 input to the 240xA CPU,
both the CPU clock domain and the system clock domain are stopped,
allowing further power savings. A third low-power mode, HALT mode, which
is the deepest mode, is possible if the oscillator and WDCLK are also shut
down. In HALT mode, the input clock to the PLL is shut off.
The low-power modes do not change the state of the GPIO pins. The pins
maintain the same state which they were in prior to entering the low-power
mode. Also, the GPIO pins are not put into the high-impedance state and the
internal pullup/pulldown is not turned off while in low-power modes.
There are two control bits, LPM (1:0) that specify which of the three possible
low-power modes is entered when the IDLE instruction is executed. This is
described in Table 4−1. These bits are located in system control and status
register 1 (SCSR1) described in section 2.2.1, on page 2-3.

4-8
 Low-Power Modes

Table 4−1. Low-Power Modes Summary

CPU System
Low-Power LPMx Bits Clock Clock WDCLK PLL OSC
Mode SCSR[12:13] Domain Domain Status Status Status Exit Condition
CPU running
XX On On On On On —
normally
Peripheral
IDLE1 − (LPM0) 00 Off On On On On interrupts, XINT1/2,
Reset, PDPINTA/B
Wakeup interrupts,
IDLE2 − (LPM1) 01 Off Off On On On XINT1/2, Reset,
PDPINTA/B
HALT − (LPM2)
{PLL/OSC 1X Off Off Off Off Off Reset, PDPINTA/B
power down}

4.4.2 Wake-Up From Low-Power Modes

A wake-up from a low-power mode can occur for several reasons. The
sections that follow describe how the device exits low-power modes.

4.4.2.1 Reset

A reset (from any source) causes the device to exit any of the IDLE modes.
If the device is halted, the reset initially starts the oscillator; however, initiation
of the CPU reset sequence may be delayed while the oscillator powers up
before clocks are generated.

4.4.2.2 External interrupts

The external interrupts, XINTx, can cause the device to exit any of the
low-power modes, except HALT. If the device is in IDLE2 mode, the
synchronous logic connected to the external interrupt pins is bypassed with
combinatorial logic that recognizes the interrupt on the pin, starts the clocks,
and then allows the clocked logic to generate an interrupt request to the PIE
controller.

4.4.2.3 Wake-Up Interrupts

Some peripherals have the capability to start the device clocks and then
generate an interrupt in response to certain external events, such as activity
on a communication line. As an example, the CAN wake-up interrupt can
assert the CAN error interrupt request even when there are no clocks running.

Clocks and Low-Power Modes 4-9

Low-Power Modes

4.4.2.4 Exiting Low-Power Modes — Some Examples

As outlined in Table 4−1, peripheral interrupts are used to wake up the device
from different low-power modes. The “wake-up” action (and the subsequent
behavior of the device) is dependent upon the following:

Whether the peripheral interrupt in question has been enabled at the pe-
ripheral level

Whether the IMR.n bit corresponding to the peripheral interrupt in question

has been enabled

The status of the INTM bit in the ST0 register

Following are two examples of low-power mode wake-up:

1) Using XINT1 to wake up from LPM0

When XINT1 is used to wake up the device from LPM0, two things can
happen based on how the XINT1 interrupt is configured. If the XINT1 inter-
rupt is enabled (by setting the appropriate bit in the XINT1CR register and
setting bit 0 in IMR to 1) and the INTM bit is zero, a valid XINT1 signal will
first take the device out of LPM0 and will also force the device to the ap-
propriate interrupt vector. However, if INTM = 1, upon an XINT1 interrupt,
the DSP will wake up and continue executing the instruction following the
IDLE instruction.

2) Using PDPINTA to wake up from LPM2 (HALT)

Case 1:
PDPINTA is enabled at peripheral level; the corresponding IMR bit is 1 (en-
abled); INTM = 0 – Upon wake-up from HALT, code branches to INT1 vec-
tor.
Case 2:
PDPINTA is enabled at peripheral level; the corresponding IMR bit is 1 (en-
abled); INTM = 1 – Upon wake-up from HALT, code starts executing the
next instruction after the IDLE instruction.
Case 3:
PDPINTA is enabled at peripheral level; the corresponding IMR bit is 0
(disabled); INTM = 1 – Device does not come out of LPM2.

NOTES:
1) Clock to EVA must be enabled in order for PDPINTA to pull the device out of reset.
2) When the PDPINTA pin is used to wake up the device from LPM2, it must be held low for
4096 CLKIN cycles + (6 or 12) CLKOUT cycles. For a device with a 10-MHz CLKIN and 40-MHz

4-10
 Low-Power Modes

CLKOUT, this translates into about 410 µs. The 4096 cycles are required to initiate a clock output
to the CPU. The remaining 12 cycles trigger a valid PDPINTA interrupt.
3) PDPINTA has both a synchronous path and an asynchronous path. The asynchronous path is used
to wake up from HALT; i.e., the clocks are turned on asynchronously by PDPINTA. Once clocks
start, it generates an interrupt. However, PDPINTA must be held low long enough for the first clock’s
edge to catch it.

4.4.3 Powering Down the Flash

The Flash module can be powered down before entering the LPM2 mode. This
operation is done while executing code from on-chip RAM, such as SARAM
or B0. This mode achieves the lowest possible current consumption. Following
is the sequence of instructions that powers down the Flash module:
***************************************************************************
; Flash−module power−down routine
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
LDP #0h ; Set DP=0
SPLK #0008h,60h ; 0008 puts the flash in powerdown mode
OUT 60h,0FF0Fh ; Puts the FLASH in control reg access mode
LACL #0h ; 0000h is the address of the Pump Control Register
TBLW 60h ; This write powers down the flash.
***************************************************************************

The LPM2 mode can be exited by using either the RS or PDPINTx signals.
While RS automatically powers up the Flash module, the following sequence
of instructions should be executed if PDPINTx is used (to exit LPM2) to power
up the Flash module:
***************************************************************************
; Flash−module power−up routine
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
LDP #0h ; Set DP=0
SPLK #0000h,60h ; 0000 pulls the flash out of powerdown mode
OUT 60h,0FF0Fh ; Puts the FLASH in control reg access mode
LACL #0h ; 0000h is the address of the Pump Control Register
TBLW 60h ; This write powers up the FLASH.
IN 60h,0FF0Fh ; Puts the FLASH in Array access mode
***************************************************************************

Clocks and Low-Power Modes 4-11

Low-Power Modes

After the Flash is powered up, a read of a known location in Flash may be done
to ensure that the Flash is ready for application use. For example, 0000h in
Program memory usually has a “branch” instruction whose opcode is 7980h.
Therefore, address 0000h could be read and checked for 7980h to validate
Flash power-up.

4-12
 Chapter 5

%  &'  (&')

The digital I/O ports module provides a flexible method for controlling both
dedicated I/O and shared pin functions. All I/O and shared pin functions are
controlled using nine 16-bit registers. These registers are divided into two
types:

I/O MUX Control registers (MCRx) − Used to control the multiplexor selec-
tion that chooses between the primary function of a pin or the general-
purpose I/O function.

Data and Direction Control registers (PxDATDIR) − Used to control the

data and data direction of bidirectional I/O pins.

The GPIO pins are controlled through “data-memory mapped registers.” Note
that there is no relationship between the GPIO pins and the I/O space of the
device.

Topic Page

5.1 Digital I/O Ports Register Implementation on 240xA Devices . . . . . . 5-2

5.2 Differences in GPIO Implementation in the 240xA . . . . . . . . . . . . . . . . 5-4
5.3 I/O MUX Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.4 Data and Direction Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5-1
Digital I/O Ports Register Implementation on 240xA Devices

5.1 Digital I/O Ports Register Implementation on 240xA Devices

Table 5−1 lists the registers available to the digital I/O module as implemented
on the 240xA devices. These registers are memory-mapped to data space
from 7090h through 709Fh. All reserved bits are unimplemented: reads return
zero and writes have no effect.

Note that when multiplexed I/O pins are configured for peripheral functions or
as GPIO outputs, the pin status can be monitored by reading the I/O data
register.

Figure 5−1. Shared Pin Configuration

IOP Data Bit Primary Primary

(Read/Write) Function Function
(Output Section) (Input Section)

In Out

IOP DIR Bit

0 = Input
1 = Output

0 1 MUX Control Bit

0 = I/O Function
1 = Primary Function

Pullup
or
Pulldown
(Internal)

Primary Function Pin

or I/O Pin

5-2
 Digital I/O Ports Register Implementation on 240xA Devices

Table 5−1. 240xA Digital I/O Port Control Registers Implementation

Address Register Mnemonic Description

7090h MCRA I/O MUX Control Register A

7092h MCRB I/O MUX Control Register B

7094h MCRC I/O MUX Control Register C

7098h PADATDIR I/O Port A Data and Direction Register

709Ah PBDATDIR I/O Port B Data and Direction Register

709Ch PCDATDIR I/O Port C Data and Direction Register

709Eh PDDATDIR I/O Port D Data and Direction Register

7095h PEDATDIR I/O Port E Data and Direction Register

7096h PFDATDIR I/O Port F Data and Direction Register

Digital Input/Output (I/O) 5-3

Differences
Differences in
in GPIO
GPIO Implementation
Implementation in
in the
the 240xA
240xA / I/O Mux Control Registers

5.2 Differences in GPIO Implementation in the 240xA

There are several differences in the 240xA GPIO implementation when
compared with the 241/242/243.

In the 240xA devices, when the bit value in an MCRx register (OCRx regis-
ter in 24x) is one, the primary function is always chosen. Likewise, when
the bit value is zero, the GPIO function is always chosen. There are no ex-
ceptions, as in the case of 24x, where XF, BIO, and CLKOUT pins have
a different configuration.

Also, some pins (such as XF and CLKOUT) are paired with different GPIO
pins compared to the 24x (i.e., the “primary function/GPIO pin” mapping/
pairing is not exactly identical to the 24x.

Due to the addition of two GPIO ports, E and F, a new MUX Control register
(MCRC) has been added.

5.3 I/O Mux Control Registers

There are three I/O mux control registers: I/O mux control register A (MCRA),
I/O mux control register B (MCRB), and I/O mux control register C (MCRC).

5.3.1 I/O Mux Control Register A

Figure 5−2. I/O Mux Control Register A (MCRA) — Address 7090h

15 14 13 12 11 10 9 8

MCRA.15 MCRA.14 MCRA.13 MCRA.12 MCRA.11 MCRA.10 MCRA.9 MCRA.8

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

MCRA.7 MCRA.6 MCRA.5 MCRA.4 MCRA.3 MCRA.2 MCRA.1 MCRA.0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

5-4
 I/O Mux Control Registers

Table 5−2. I/O Mux Control Register A (MCRA) Configuration

Pin Function Selected
Bit # Name.bit # (MCA.n = 1) (MCA.n = 0)
(Primary) (Secondary)
0 MCRA.0 SCITXD IOPA0
1 MCRA.1 SCIRXD IOPA1
2 MCRA.2 XINT1 IOPA2
3 MCRA.3 CAP1/QEP1 IOPA3
4 MCRA.4 CAP2/QEP2 IOPA4
5 MCRA.5 CAP3 IOPA5
6 MCRA.6 PWM1 IOPA6
7 MCRA.7 PWM2 IOPA7
8 MCRA.8 PWM3 IOPB0
9 MCRA.9 PWM4 IOPB1
10 MCRA.10 PWM5 IOPB2
11 MCRA.11 PWM6 IOPB3
12 MCRA.12 T1PWM/T1CMP IOPB4
13 MCRA.13 T2PWM/T2CMP IOPB5
14 MCRA.14 TDIRA IOPB6
15 MCRA.15 TCLKINA IOPB7

Note: Due to the absence of XINT1/IOPA2 and TDIRA/IOPB6 pins, bits 2 and 14 of MCRA must
be treated as reserved for 2402A devices.

5.3.2 I/O Mux Output Control Register B

Figure 5−3. I/O Mux Control Register B (MCRB) — Address 7092h

15 14 13 12 11 10 9 8

MCRB.15 MCRB.14 MCRB.13 MCRB.12 MCRB.11 MCRB.10 MCRB.9 MCRB.8

RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-0

7 6 5 4 3 2 1 0

MCRB.7 MCRB.6 MCRB.5 MCRB.4 MCRB.3 MCRB.2 MCRB.1 MCRB.0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-1 RW-1

Note: R = Read access, W = Write access, -0 = value after reset

Digital Input/Output (I/O) 5-5

I/O Mux Control Registers

Table 5−3. I/O Mux Control Register B (MCRB) Configuration

Pin Function Selected

Bit # Name.bit # (MCB.n = 1) (MCB.n = 0)
(Primary) (Secondary)
0 MCRB.0 W/R IOPC0
1 MCRB.1 BIO IOPC1
2 MCRB.2 SPISIMO IOPC2
3 MCRB.3 SPISOMI IOPC3
4 MCRB.4 SPICLK IOPC4
5 MCRB.5 SPISTE IOPC5
6 MCRB.6 CANTX IOPC6
7 MCRB.7 CANRX IOPC7
8 MCRB.8 XINT2/ADCSOC IOPD0
9 MCRB.9 EMU0 Reserved
10 MCRB.10 EMU1 Reserved
11 MCRB.11 TCK Reserved
12 MCRB.12 TDI Reserved
13 MCRB.13 TDO Reserved
14 MCRB.14 TMS Reserved
15 MCRB.15 TMS2 Reserved

Notes: 1) Due to the absence of the W/R/IOPC0, BIO/IOPC1, and SPISTE/IOPC5 pins, bits 0,
1, and 5 of MCRB must be treated as reserved in the 2402A.
2) Due to the absence of SPI and CAN modules (in 2402A), bits 2, 3, 4, 6, and 7 of
MCRB should always be written with 0. The corresponding pins work as GPIO pins
only.
3) Due to the absence of the CAN module and W/R function in 2404A, bits 0, 6, and
7 of MCRB should always be written with 0. The corresponding pins work as GPIO
pins only.
4) Due to the absence of the W/R function in 2406A, bit 0 of MCRB should always be
written with 0. The corresponding pin works as a GPIO pin only.

5-6
 I/O Mux Control Registers

5.3.3 I/O Mux Output Control Register C

Figure 5−4. I/O Mux Control Register C (MCRC) — Address 7094h
15 14 13 12 11 10 9 8

Reserved Reserved MCRC.13 MCRC.12 MCRC.11 MCRC.10 MCRC.9 MCRC.8

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

MCRC.7 MCRC.6 MCRC.5 MCRC.4 MCRC.3 MCRC.2 MCRC.1 MCRC.0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-1

Note: R = Read access, W = Write access, -0 = value after reset

Table 5−4. I/O Mux Control Register C (MCRC) Configuration

Pin Function Selected
Bit # Name.bit # (MCC.n = 1) (MCC.n = 0)
(Primary) (Secondary)
0 MCRC.0 CLKOUT IOPE0
1 MCRC.1 PWM7 IOPE1
2 MCRC.2 PWM8 IOPE2
3 MCRC.3 PWM9 IOPE3
4 MCRC.4 PWM10 IOPE4
5 MCRC.5 PWM11 IOPE5
6 MCRC.6 PWM12 IOPE6
7 MCRC.7 CAP4/QEP3 IOPE7
8 MCRC.8 CAP5/QEP4 IOPF0
9 MCRC.9 CAP6 IOPF1
10 MCRC.10 T3PWM/T3CMP IOPF2
11 MCRC.11 T4PWM/T4CMP IOPF3
12 MCRC.12 TDIRB IOPF4
13 MCRC.13 TCLKINB IOPF5
14 MCRC.14 Reserved Reserved
15 MCRC.15 Reserved Reserved
Notes: 1) Due to the absence of the EVB, bits 1 through 13 must be treated as reserved in the
2402A.
2) IOPF6 is not multiplexed with any other function. Independent of the value of
MCRC.14, this pin always works as a GPIO pin.

Digital Input/Output (I/O) 5-7

Data and Direction Control Registers

5.4 Data and Direction Control Registers

There are six data and direction control registers. Refer to Table 5−1, 240xA
Digital I/O Port Control Registers Implementation, on page 5-3 for the
address locations of each register.

Figure 5−5. Port A Data and Direction Control Register (PADATDIR)

15 14 13 12 11 10 9 8

A7DIR A6DIR A5DIR A4DIR A3DIR A2DIR A1DIR A0DIR

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

IOPA7 IOPA6 IOPA5 IOPA4 IOPA3 IOPA2 IOPA1 IOPA0

RW-† RW-† RW-† RW-† RW-† RW-† RW-† RW-†

† The reset value of these bits depends upon the state of the respective pins.
Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−8 AnDIR

0 Configure corresponding pin as an input
1 Configure corresponding pin as an output

Bits 7−0 IOPAn

If AnDIR = 0, then:
0 Corresponding I/O pin is read as a low
1 Corresponding I/O pin is read as a high

If AnDIR = 1, then:
0 Set corresponding I/O pin low
1 Set corresponding I/O pin high

5-8
 Data and Direction Control Registers

Table 5−5. PADATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function)

I/O Port Data Bit Pin Name

IOPA0 SCITXD/IOPA0
IOPA1 SCIRXD/IOPA1
IOPA2 XINT1/IOPA2†
IOPA3 CAP1/QEP1/IOPA3
IOPA4 CAP2/QEP2/IOPA4
IOPA5 CAP3/IOPA5
IOPA6 CMP1/IOPA6
IOPA7 CMP2/IOPA7
† There is no IOPA2 pin on 2402A devices.

Figure 5−6. Port B Data and Direction Control Register (PBDATDIR)

15 14 13 12 11 10 9 8

B7DIR B6DIR B5DIR B4DIR B3DIR B2DIR B1DIR B0DIR

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

IOPB7 IOPB6 IOPB5 IOPB4 IOPB3 IOPB2 IOPB1 IOPB0

RW-† RW-† RW-† RW-† RW-† RW-† RW-† RW-†

† The reset value of these bits depends upon the state of the respective pins.
Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−8 BnDIR

0 Configure corresponding pin as an input
1 Configure corresponding pin as an output

Bits 7−0 IOPBn

If BnDIR = 0, then:
0 Corresponding I/O pin is read as a low
1 Corresponding I/O pin is read as a high

If BnDIR = 1, then:
0 Set corresponding I/O pin low
1 Set corresponding I/O pin high

Digital Input/Output (I/O) 5-9

Data and Direction Control Registers

Table 5−6. PBDATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function)

I/O Port Data Bit Pin Name

IOPB0 CMP3/IOPB0
IOPB1 CMP4/IOPB1
IOPB2 CMP5/IOPB2
IOPB3 CMP6/IOPB3
IOPB4 T1CMP/IOPB4
IOPB5 T2CMP/IOPB5
IOPB6 TDIR/IOPB6†
IOPB7 TCLKIN/IOPB7
† There is no IOPB6 pin in 2402A devices.

Figure 5−7. Port C Data and Direction Control Register (PCDATDIR)

15 14 13 12 11 10 9 8

C7DIR C6DIR C5DIR C4DIR C3DIR C2DIR C1DIR C0DIR

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

IOPC7 IOPC6 IOPC5 IOPC4 IOPC3 IOPC2 IOPC1 IOPC0

RW-† RW-† RW-† RW-† RW-† RW-† RW-† RW-x

† The reset value of these bits depends upon the state of the respective pins.
Note: R = Read access, W = Write access, -0 = value after resett, x = undefined

Bits 15−8 CnDIR

0 Configure corresponding pin as an input
1 Configure corresponding pin as an output

Bits 7−0 IOPCn

If CnDIR = 0, then:
0 Corresponding I/O pin is read as a low
1 Corresponding I/O pin is read as a high

If CnDIR = 1, then:
0 Set corresponding I/O pin low
1 Set corresponding I/O pin high

5-10
 Data and Direction Control Registers

Table 5−7. PCDATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function)

I/O Port Data Bit Pin Name

IOPC0 W/R/IOPC0†
IOPC1 BIO/IOPC1†
IOPC2 SPISIMO/IOPC2
IOPC3 SPISOMI/IOPC3
IOPC4 SPICLK/IOPC4
IOPC5 SPISTE/IOPC5†
IOPC6 CANTX/IOPC6
IOPC7 CANRX/IOPC7
† These pins are not available on 2402A devices.

Figure 5−8. Port D Data and Direction Control Register (PDDATDIR)

15−9 8

Reserved D0DIR

RW-0
7−1 0

Reserved IOPD0

RW-†
† The reset value of this bit depends upon the state of the respective pins.
Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−9 Reserved

Bit 8 D0DIR
0 Configure corresponding pin as an input
1 Configure corresponding pin as an output

Bits 7−1 Reserved

Bit 0 IOPD0

If D0DIR = 0, then:
0 Corresponding I/O pin is read as a low
1 Corresponding I/O pin is read as a high

Digital Input/Output (I/O) 5-11

Data and Direction Control Registers

If D0DIR = 1, then:
0 Set corresponding I/O pin low
1 Set corresponding I/O pin high

Table 5−8. PDDATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function)

I/O Port Data Bit Pin Name

IOPD0 XINT2/ADCSOC/IOPD0
IOPD1 Reserved
IOPD2 Reserved
IOPD3 Reserved
IOPD4 Reserved
IOPD5 Reserved
IOPD6 Reserved
IOPD7 Reserved

Figure 5−9. Port E Data and Direction Control Register (PEDATDIR)

15 14 13 12 11 10 9 8

E7DIR E6DIR E5DIR E4DIR E3DIR E2DIR E1DIR E0DIR

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

IOPE7 IOPE6 IOPE5 IOPE4 IOPE3 IOPE2 IOPE1 IOPE0

RW-† RW-† RW-† RW-† RW-† RW-† RW-† RW-x

† The reset value of these bits depends upon the state of the respective pins.
Note: R = Read access, W = Write access, -0 = value after reset, x = undefined

Bits 15−8 EnDIR

0 Configure corresponding pin as an input
1 Configure corresponding pin as an output

Bits 7−0 IOPEn

If EnDIR = 0, then:
0 Corresponding I/O pin is read as a low
1 Corresponding I/O pin is read as a high

5-12
 Data and Direction Control Registers

If EnDIR = 1, then:
0 Set corresponding I/O pin low
1 Set corresponding I/O pin high

Table 5−9. PEDATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function)

I/O Port Data Bit Pin Name

IOPE0 CLKOUT/IOPE0
IOPE1 PWM7/IOPE1†
IOPE2 PWM8/IOPE2†
IOPE3 PWM9/IOPE3†
IOPE4 PWM10/IOPE4†
IOPE5 PWM11/IOPE5†
IOPE6 PWM12/IOPE6†
IOPE7 CAP4/QEP3/IOPE7†
† These pins are not available on 2402A devices.

Figure 5−10. Port F Data and Direction Control Register (PFDATDIR)

15 14 13 12 11 10 9 8

Reserved F6DIR F5DIR F4DIR F3DIR F2DIR F1DIR F0DIR

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

Reserved IOPF6 IOPF5 IOPF4 IOPF3 IOPF2 IOPF1 IOPF0

RW-† RW-† RW-† RW-† RW-† RW-† RW-†

† The reset value of these bits depends upon the state of the respective pins.
Note: R = Read access, W = Write access, -0 = value after reset

Bit 15 Reserved

Bits 14−8 FnDIR

0 Configure corresponding pin as an input
1 Configure corresponding pin as an output

Bit 7 Reserved

Digital Input/Output (I/O) 5-13

Data and Direction Control Registers

Bits 6−0 IOPFn

If FnDIR = 0, then:
0 Corresponding I/O pin is read as a low
1 Corresponding I/O pin is read as a high

If FnDIR = 1, then:
0 Set corresponding I/O pin low
1 Set corresponding I/O pin high

Table 5−10. PFDATDIR I/O Pin Designation (Assuming Pins Have Been Selected as I/O;
i.e., Secondary Function)

I/O Port Data Bit Pin Name

IOPF0 CAP5/QEP4/IOPF0†
IOPF1 CAP6/IOPF1†
IOPF2 T3PWM/T3CMP/IOPF2†
IOPF3 T4PWM/T4CMP/IOPF3†
IOPF4 TDIR2/IOPF4†
IOPF5 TCLKIN2/IOPF5†
IOPF6 IOPF6†
Reserved Reserved
† These pins are not available on 2402A devices.

5-14
 Chapter 6

*  (+)

This chapter describes the 240xA Event Manager (EV) module. Most of the
EV pins are shared with general-purpose digital I/O signals. This pin sharing
and how it is controlled is described in Chapter 5, Digital Input/Output (I/O).

The EV module provides a broad range of functions and features that are
particularly useful in motion control and motor control applications. There are
differences in terms of the functionality between the EV module of 240xA
devices and the EV module of 240 devices. (However, the EV modules in the
24x and 240xA families of DSPs are exactly identical in terms of functionality.)
Note that all devices of the 240xA family (with the exception of the 2402A) have
two EV modules as opposed to one EV module in the 241/242/243 devices.

Topic Page

6.1 Event Manager (EV) Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.2 Event Manager (EV) Register Addresses . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.3 General-Purpose (GP) Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.4 Compare Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39
6.5 PWM Circuits Associated With Compare Units . . . . . . . . . . . . . . . . . 6-48
6.6 PWM Waveform Generation With Compare Units and
PWM Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57
6.7 Space Vector PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62
6.8 Capture Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-68
6.9 Quadrature Encoder Pulse (QEP) Circuit . . . . . . . . . . . . . . . . . . . . . . . 6-80
6.10 Event Manager (EV) Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-84

6-1
Event Manager (EV) Functional Blocks

6.1 Event Manager (EV) Functional Blocks

All devices of the 240xA family, with the exception of the 2402A, have two
event managers, EVA and EVB. These two event managers are exactly
identical to each other in terms of functionality and register mapping/bit
definition. For the sake of brevity, only the functionality of EVA is explained.
Minor differences (such as naming conventions and register addresses) are
highlighted as appropriate.

Each EV module in the 240xA device contains the following functional blocks:

Two general-purpose (GP) timers (described in section 6.3 on page 6-14)

Three compare units (described in section 6.4 on page 6-39)

Pulse-width modulation (PWM) circuits that include space vector PWM

circuits, dead-band generation units, and output logic (described in sec-
tion 6.5 on page 6-48, section 6.6 on page 6-57, and section 6.7 on
page 6-62, respectively)

Three capture units (described in section 6.8 on page 6-68)

Quadrature encoder pulse (QEP) circuit (described in section 6.9, on

page 6-80)

Interrupt logic (described in section 6.10 on page 6-84)

Figure 6−1 shows a block diagram of the EVA module and Figure 6−2 shows
a block diagram of the EVB module.

6-2
 Event Manager (EV) Functional Blocks

Figure 6−1. Event Manager A (EVA) Block Diagram

240xA DSP core

Data
bus ADDR bus Reset INT1,2,3,4 Clock
16
16
16
EV control registers ADC start of
and control logic conversion

16 GP timer 1 Output T1CMP/

compare logic T1PWM

TDIRA
16 TCLKINA
GP timer 1
Prescaler
CLKOUT

16
T1CON[4,5] T1CON[8,9,10]

3 SVPWM 3 Dead 3 PWM1

16 Full compare state band Output
units machine units logic
PWM6

16 GP timer 2 Output T2CMP/

compare logic T2PWM

TCLKINA
16 Prescaler
GP timer 2 CLKOUT

T2CON[4,5] T2CON[8,9,10]
16
TDIRA
16

DIR Clock

QEP CAPCONA[14,13]
MUX
circuit
2
2 CAP1/QEP1
2 CAP2/QEP2
16
Capture units
CAP3
16

Event Manager (EV) 6-3

Event Manager (EV) Functional Blocks

Figure 6−2. Event Manager B (EVB) Block Diagram

240xA DSP core

Data
bus ADDR bus Reset INT1,2,3,4 Clock
16
16
16
EV control registers ADC start of
and control logic conversion

16 GP timer 3 Output T3CMP/

compare logic T3PWM

TDIRB
16 TCLKINB
GP timer 3
Prescaler
CLKOUT

16
T3CON[4,5] T3CON[8,9,10]

3 SVPWM 3 Dead 3 PWM7

16 Full compare state band Output
units machine units logic
PWM12

16 GP timer 4 Output T4CMP/

compare logic T4PWM

Prescaler TCLKINB
16
GP timer 4 CLKOUT

T4CON[4,5] T4CON[8,9,10]
16
TDIRB
16

DIR Clock

QEP CAPCONB[14,13]
MUX
circuit
2
2 CAP4/QEP3
2 CAP5/QEP4
16
Capture units
CAP6
16

6-4
 Event Manager (EV) Functional Blocks

6.1.1 Differences Between C240 EV and 240xA EV

The single-up count and single-up/down count modes have been re-
moved from the remaining GP timers. Software change: The four timer
modes are now decoded with TMODE1−0. This decoding is different from
the C240 EV. TMODE2 is now a reserved bit.

There is no 32-bit timer mode.

The GP Timers do not stay at the period register value, FFFFh or 0000h
when operating in directional-up/down count mode (including QEP mode).
They now reverse direction when one of these end points is reached.

A capture 3 event is now able to start the ADC.

The capture units of a particular EV can now use any timer associated with
that EV as a time base.

The capture interrupt flag gets set when a capture event occurs only if
there are one or more capture events stored in the FIFO already.

The Capture FIFO status bits are now RW. Bits 5−0 of CAPFIFO are now
unnecessary and are reserved.

Both locations in the capture FIFO can be read individually, not just the top
location.

The QEP logic can only clock GP timer 2 for EVA and GP timer 4 for EVB.

The three simple compare units have been removed.

The compare mode of the (full) compare units has been removed. They
now only operate in PWM mode.

The dead band counters have been reduced from 8 bits to 4 bits. The dead
band prescaler has been increased from 3 bits to 5 bits, adding two more
prescale values: x/16 and x/32. Software change: There are now three
DBTPSx bits. DBTPS0 moves to bit 2 of DBTCON, DBTPS1 moves to
bit 3, and bit 4 becomes DBTPS2.

Any register bits associated with the removed functions are now reserved
(not implemented).

Most interrupt control logic has been removed from each peripheral. Each
peripheral now simply has one interrupt request signal and associated en-
able for each interrupt flag. The peripheral interrupt vector table (contain-
ing the peripheral interrupt vectors) is now located in the peripheral inter-
rupt expansion (PIE) controller.

Event Manager (EV) 6-5

Event Manager (EV) Functional Blocks

Software writing a 1 to the interrupt flag, which has been identified by the
interrupt vector ID, is required to clear the flag. Reading the interrupt vec-
tor ID no longer automatically clears the associated flag.

PDPINTA/B is now enabled following reset.

Only one write is required to initialize COMCONA/B, not two as on the

C240.

6.1.2 EV Pins
Each EV module has eight device pins available for compare/PWM outputs:

Two GP timer compare/PWM output pins:

EVA EVB

T1CMP/T1PWM T3CMP/T3PWM

T2CMP/T2PWM T4CMP/T4PWM

Six (full) compare/PWM output pins:

EVA EVB

PWM1 PWM7

PWM2 PWM8

PWM3 PWM9

PWM4 PWM10

PWM5 PWM11

PWM6 PWM12

The EVA module uses three device pins, CAP1/QEP1, CAP2/QEP2, and
CAP3, as capture or quadrature encoder pulse inputs.

The EVB module uses three device pins, CAP4/QEP3, CAP5/QEP4, and
CAP6, as capture or quadrature encoder pulse inputs.

The timers in the EV module can be programmed to operate based on an

external clock or the internal device clock. The device pin TCLKINA/B supplies
the external clock input.

The device pin TDIRA/B is used to specify the counting direction when a GP
timer is in directional up-/down-counting mode.

The device pins are summarized in Table 6−1, Event Manager A Pins, and
Table 6−2, Event Manager B Pins.

6-6
 Event Manager (EV) Functional Blocks

Table 6−1. Event Manager A Pins

Pin Name Description

CAP1/QEP1 Capture Unit 1 input, QEP circuit input 1

CAP2/QEP2 Capture Unit 2 input, QEP circuit input 2

CAP3 Capture Unit 3 input

PWM1 Compare Unit 1 output 1

PWM2 Compare Unit 1 output 2

PWM3 Compare Unit 2 output 1

PWM4 Compare Unit 2 output 2

PWM5 Compare Unit 3 output 1

PWM6 Compare Unit 3 output 2

T1CMP/T1PWM Timer 1 compare/PWM output

T2CMP/T2PWM Timer 2 compare/PWM output

TCLKINA External clock input for timers in EVA

TDIRA External timer direction input in EVA

Event Manager (EV) 6-7

Event Manager (EV) Functional Blocks

Table 6−2. Event Manager B Pins

Pin Name Description

CAP4/QEP3 Capture Unit 4 input, QEP circuit input 3

CAP5/QEP4 Capture Unit 5 input, QEP circuit input 4

CAP6 Capture Unit 6 input

PWM7 Compare Unit 4 output 1

PWM8 Compare Unit 4 output 2

PWM9 Compare Unit 5 output 1

PWM10 Compare Unit 5 output 2

PWM11 Compare Unit 6 output 1

PWM12 Compare Unit 6 output 2

T3CMP/T3PWM Timer 3 compare/PWM output

T4CMP/T4PWM Timer 4 compare/PWM output

TCLKINB External clock input for timers in EVB

TDIRB External timer direction input in EVB

6.1.3 Power Drive Protection Interrupt (PDPINTx, x = A or B)

The PDPINTx is a safety feature that is provided for the safe operation of
systems such as power converters and motor drives. PDPINTx can be used
to inform the monitoring program of motor drive abnormalities such as over-
voltage, over-current, and excessive temperature rise. If the PDPINTx
interrupt is unmasked, all PWM output pins will be put in the high-impedance
state immediately after the PDPINTx pin is driven low. An interrupt will also be
generated.

The interrupt flag associated with PDPINTx is also set when such an event
occurs; however, it must wait until the transition on PDPINTx has been
qualified and synchronized with the internal clock. The qualification and
synchronization cause a delay of two clock cycles. The setting of the flag does
not depend on whether or not the PDPINTx interrupt is masked: it happens
when a qualified transition occurs on the PDPINTx pin. This interrupt is
enabled following reset. If the PDPINTx interrupt is disabled, the action of
driving the PWM outputs to the high-impedance state (upon a valid PDPINTx
interrupt) is also disabled.

6-8
 Event Manager (EV) Functional Blocks

6.1.3.1 240xA-Specific Features for PDPINTx Function

In 240xA devices, the status of the PDPINTx pin is reflected in bit 8 of the
COMCONx register.

The PDPINTx pin must be held low for 6 (or 12) CLKOUT cycles before
it is recognized by the core.

6.1.4 EV Registers

The Event Manager registers occupy two 64-word (16-bit) frames of address
space. The Event Manager module decodes the lower six-bits of the address;
while the upper 10 bits of the address are decoded by the peripheral address
decode logic, which provides a module select to the Event Manager when the
peripheral address bus carries an address within the range designated for the
EV on that device.

On 240xA devices (as with the C240 device), EVA registers are located in the
range 7400h to 7431h. EVB registers are located in the range of 7500h to
7531h.

The undefined registers and undefined bits of the EV registers all return zero
when read by user software. Writes have no effect. See Section 6.2, Event
Manager(EV) Register Addresses, on page 6-11.

6.1.5 EV Interrupts

The Event Manager interrupts are arranged into three groups. Each group is
assigned one CPU interrupt (INT2, 3 or 4). Since each group has multiple
interrupt sources, the CPU interrupt requests are processed by the peripheral
interrupt expansion (PIE) module. The 240xA interrupt requests have the
following stages of response:

Interrupt source. If peripheral interrupt conditions occur, the respective

flag bits in registers EVxIFRA, EVxIFRB, or EVxIFRC (x = A or B) are set.
Once set, these flags remain set until explicity cleared by the software. It
is mandatory to clear these flags in the software or future interrupts will not
be recognized.

Interrupt enable. The Event Manager interrupts can be individually en-

abled or disabled by interrupt mask registers EVxIMRA, EVxIMRB, and
EVxIMRC (x = A or B). Each bit is set to 1 to enable/unmask the interrupt
or cleared to 0 to disable/mask the interrupt.

Event Manager (EV) 6-9

Event Manager (EV) Functional Blocks

PIE request. If both interrupt flag bits and interrupt mask bits are set, then
the peripheral issues a peripheral interrupt request to the PIE module. The
PIE module can receive more than one interrupt from the peripheral. The
PIE logic records all the interrupt requests and generates the respective
CPU interrupt (INT1, 2, 3, or 4) based on the preassigned priority of the
received interrupts. See Table 2−2, 240xA Interrupt Source Priority and
Vectors, on page 2-9 for priority and vector values.

CPU response. On receipt of an INT1, 2, 3, or 4 interrupt request, the re-

spective bit in the CPU interrupt flag register (IFR) will be set. If the corres-
ponding interrupt mask register (IMR) bit is set and INTM bit is cleared,
then the CPU recognizes the interrupt and issues an acknowledgement
to the PIE. Following this, the CPU finishes executing the current instruc-
tion and branches to the interrupt vector corresponding to INT1, 2, 3, or
4. At this time, the respective IFR bit will be cleared and the INTM bit will
be set disabling further interrupt recognition. The interrupt vector contains
a branch instruction for the interrupt service routine. From here, the inter-
rupt response is controlled by the software.

PIE response. The PIE logic uses the acknowledge signal from the core
to clear the PIRQ bit that issued the CPU interrupt. Along with this, the PIE
updates its PIVR register with the interrupt vector, unique to the peripheral
interrupt, that was just acknowledged. After this, the PIE hardware works
in parallel to the current interrupt software to generate a CPU interrupt and
other pending interrupts, if any.

Interrupt software. The interrupt software has two levels of response.

 Level 1 (GISR). In the first level the software should do any context
save and read the PIVR register from PIE module to decide which in-
terrupt group caused the interrupt.Since the PIVR value is unique, it
can be used to branch to the interrupt service routine specific to this
interrupt condition.
 Level 2 (SISR). This level is optional and could reside as a part of lev-
el 1. However, at this stage the interrupt software has explicit respon-
sibility to avoid improper interrupt response. After executing the inter-
rupt specific code, the routine should clear the interrupt flag in the
EVxIFRA EVxIFRB, or EVxIFRC that caused the serviced interrupt.
Code will return after enabling the CPU’s global interrupt bit INTM
(clear INTM bit).

6-10
 Event Manager (EV) Register Addresses

6.2 Event Manager (EV) Register Addresses

Table 6−3 through Table 6−10 display the addresses of the Event Manager
registers.

Table 6−3. Addresses of EVA Timer Registers

Address Register Name
7400h GPTCONA Timer control register
7401h T1CNT Timer 1 counter register
7402h T1CMPR Timer 1 compare register
Timer 1
7403h T1PR Timer 1 period register
7404h T1CON Timer 1 control register
7405h T2CNT Timer 2 counter register
7406h T2CMPR Timer 2 compare register
Timer 2
7407h T2PR Timer 2 period register
7408h T2CON Timer 2 control register

Table 6−4. Addresses of EVB Timer Registers

Address Register Name
7500h GPTCONB Timer control register
7501h T3CNT Timer 3 counter register
7502h T3CMPR Timer 3 compare register
Timer 3
7503h T3PR Timer 3 period register
7504h T3CON Timer 3 control register
7505h T4CNT Timer 4 counter register
7506h T4CMPR Timer 4 compare register
Timer 4
7507h T4PR Timer 4 period register
7508h T4CON Timer 4 control register

Table 6−5. Addresses of EVA Compare Control Registers

Address Register Name
7411h COMCONA Compare control register
7413h ACTRA Compare action control register
7415h DBTCONA Dead-band timer control register
7417h CMPR1 Compare register 1
7418h CMPR2 Compare register 2
7419h CMPR3 Compare register 3

Event Manager (EV) 6-11

Event Manager (EV) Register Addresses

Table 6−6. Addresses of EVB Compare Control Registers

Address Register Name

7511h COMCONB Compare control register
7513h ACTRB Compare action control register
7515h DBTCONB Dead-band timer control register
7517h CMPR4 Compare register 4
7518h CMPR5 Compare register 5
7519h CMPR6 Compare register 6

Table 6−7. Addresses of EVA Capture Registers

Address Register Name

7420h CAPCONA Capture control register
7422h CAPFIFOA Capture FIFO status register
7423h CAP1FIFO Two-level-deep capture FIFO stack 1
7424h CAP2FIFO Two-level-deep capture FIFO stack 2
7425h CAP3FIFO Two-level-deep capture FIFO stack 3
7427h CAP1FBOT Bottom registers of FIFO stacks,
7428h CAP2FBOT allows most recent CAPTURE value to
be read.
7429h CAP3FBOT

Table 6−8. Addresses of EVB Capture Registers

Address Register Name

7520h CAPCONB Capture control register
7522h CAPFIFOB Capture FIFO status register
7523h CAP4FIFO Two-level-deep capture FIFO stack 4
7524h CAP5FIFO Two-level-deep capture FIFO stack 5
7525h CAP6FIFO Two-level-deep capture FIFO stack 6
7527h CAP4FBOT Bottom registers of FIFO stacks,
7528h CAP5FBOT allows most recent CAPTURE value to
be read.
7529h CAP6FBOT

6-12
 Event Manager (EV) Register Addresses

Table 6−9. Addresses of EVA Interrupt Registers

Address Register Name

742Ch EVAIMRA Interrupt mask register A
742Dh EVAIMRB Interrupt mask register B
742Eh EVAIMRC Interrupt mask register C
742Fh EVAIFRA Interrupt flag register A
7430h EVAIFRB Interrupt flag register B
7431h EVAIFRC Interrupt flag register C

Table 6−10. Addresses of EVB Interrupt Registers

Address Register Name

752Ch EVBIMRA Interrupt mask register A
752Dh EVBIMRB Interrupt mask register B
752Eh EVBIMRC Interrupt mask register C
752Fh EVBIFRA Interrupt flag register A
7530h EVBIFRB Interrupt flag register B
7531h EVBIFRC Interrupt flag register C

Event Manager (EV) 6-13

General-Purpose (GP) Timers

6.3 Figure 6−13General-Purpose (GP) Timers

There are two general-purpose (GP) timers in each module. These timers can
be used as independent time bases in applications such as:

The generation of a sampling period in a control system

Providing a time base for the operation of the quadrature encoder pulse
(QEP) circuit (GP timer 2/4 only) and the capture units

Providing a time base for the operation of the compare units and
associated PWM circuits to generate PWM outputs

Timer Functional Blocks

Figure 6−3 shows a block diagram of a GP timer. Each GP timer includes:

One readable and writeable (RW) 16-bit up and up/down counter register
TxCNT (x = 1, 2, 3, 4) (see Figure 6−4). This register stores the current
value of the counter and keeps incrementing or decrementing depending
on the direction of counting.

One RW 16-bit timer compare register (shadowed), TxCMPR (x = 1, 2,
3, 4) (see Figure 6−5)

One RW 16-bit timer period register (shadowed), TxPR (x = 1, 2, 3, 4) (see
Figure 6−6)

RW 16-bit individual timer control register, TxCON (x = 1, 2, 3, 4) (see
Figure 6−13)

Programmable prescaler applicable to both internal and external clock
inputs

Control and interrupt logic

One GP timer compare output pin, TxCMP (x = 1, 2, 3, 4)

Output conditioning logic

Another overall control register, GPTCONA/B, specifies the action to be taken

by the timers on different timer events, and indicates the counting directions
of the GP timers. GPTCONA/B is readable and writeable, although writing to
the status bits has no effect.

Note:
Timer 2 can select the period register of timer 1 as its period register. In
Figure 6−3, the mux is applicable only when the figure represents timer 2.
Timer 4 can select the period register of timer 3 as its period register. In
Figure 6−3, the mux is applicable only when the figure represents timer 4.

6-14
 General-Purpose (GP) Timers

Bit(s) Name Description

15:0 T1CNT Holds the instantaneous value of Timer 1 counter

Figure 6−3. General-Purpose Timer Block Diagram (x = 2 or 4)

[when x = 2: y = 1 and n = 2; when x = 4: y = 3 and n = 4]

TxPR
TyPR period register
period register
(shadowed)
(shadowed)

GPTCONA/B
GP timer
control
MUX TnCON[0] register

TxCMPR
Symm/asym
compare Compare Output
waveform TxPWM
register logic logic
generator
(shadowed)

Interrupt flags

TxCNT GP
timer counter
ADC start of
conversion

Internal Control
CPU logic TCLKINA/B
clock TDIRA/B

TxCON
GPTx control
register

Event Manager (EV) 6-15

General-Purpose (GP) Timers

Figure 6−4. Timer x Counter Register (TxCNT, where x = 1, 2, 3, or 4)

15 0
T1CNT
R/W-x
Legend: R = Read access, W = Write access, -0 = value after reset

Figure 6−5. Timer x Compare Register (TxCMPR, where x = 1, 2, 3, or 4)

15 0
T1CMPR
R/W-x
Legend: R = Read access, W = Write access, -0 = value after reset
Bit(s) Name Description
15:0 T1CMPR Holds the compare value of Timer 1 counter

Figure 6−6. Timer x Period Register (TxPR, where x = 1, 2, 3, or 4)

15 0
T1PR
R/W-x
Legend: R = Read access, W = Write access, -0 = value after reset

GP Timer Inputs

The inputs to the GP timers are:

The internal device (CPU) clock

An external clock, TCLKINA/B, that has a maximum frequency of one-

fourth that of the device clock

6-16
 General-Purpose (GP) Timers

Direction input, TDIRA/B, for use by the GP timers in directional up-/down-

counting mode

Reset signal, RESET

When a timer is used with the QEP circuit, the QEP circuit generates both the
timer’s clock and the counting direction.

GP Timer Outputs
The outputs of the timers are:

GP timer compare outputs TxCMP, x = 1, 2, 3, 4

ADC start-of-conversion signal to ADC module

Underflow, overflow, compare match, and period match signals to its own
compare logic and to the compare units

Counting direction indication bits

Individual GP Timer Control Register (TxCON)

The operational mode of a timer is controlled by its individual control register
TxCON. Bits in the TxCON register determine:

Which of the four counting modes the timer is in

Whether an internal or external clock is to be used by the GP timer

Which of the eight input clock prescale factors (ranging from 1 to 1/128)
is used

On which condition the timer compare register is reloaded

Whether the timer is enabled or disabled

Whether the timer compare operation is enabled or disabled

Which period register is used by timer 2, its own, or timer 1’s period register
(EVA)
Which period register is used by timer 4, its own, or timer 3’s period register
(EVB)

Overall GP Timer Control Register (GPTCONA/B)

The control register GPTCONA/B specifies the action to be taken by the timers
on different timer events and indicates their counting directions.

Event Manager (EV) 6-17

General-Purpose (GP) Timers

GP Timer Compare Registers

The compare register associated with a GP timer stores the value to be
constantly compared with the counter of the GP timer. When a match happens,
the following events occur:

A transition occurs on the associated compare output according to the bit

pattern in GPTCONA/B

The corresponding interrupt flag is set

A peripheral interrupt request is generated if the interrupt is unmasked

The compare operation of a GP timer can be enabled or disabled by the

appropriate bit in TxCON.

The compare operation and outputs can be enabled in any of the timer modes,
including QEP mode.

GP Timer Period Register

The value in the period register of a GP timer determines the period of the
timer. A GP timer resets to 0, or starts counting downward when a match
occurs between the period register and the timer counter, depending on which
counting mode the timer is in.

Double Buffering of GP Timer Compare and Period Registers

The compare and period registers, TxCMPR and TxPR, of a GP timer are
shadowed. A new value can be written to any of these registers at any time
during a period. However, the new value is written to the associated shadow
register. For the compare register, the content in the shadow register is loaded
into the working (active) register only when a certain timer event specified by
TxCON occurs. For the period register, the working register is reloaded with
the value in its shadow register only when the value of the counter register
TxCNT is 0. The condition on which a compare register is reloaded can be one
of the following:

Immediately after the shadow register is written

On underflow; that is, when the GP timer counter value is 0

On underflow or period match; that is, when the counter value is 0 or when
the counter value equals the value of the period register

The double buffering feature of the period and compare registers allows the
application code to update the period and compare registers at any time during

6-18
 General-Purpose (GP) Timers

a period in order to change the timer period and the width of the PWM pulse
for the period that follows. On-the-fly change of the timer period value, in the
case of PWM generation, means on-the-fly change of PWM carrier frequency.

Note:
The period register of a GP timer should be initialized before its counter is
initialized to a non-zero value. Otherwise, the value of the period register will
remain unchanged until the next underflow.

Note that a compare register is transparent (the newly loaded value goes
directly into the active register) when the associated compare operation is
disabled. This applies to all Event Manager compare registers.

GP Timer Compare Output

The compare output of a GP timer can be specified active high, active low,
forced high, or forced low, depending on how the GPTCONA/B bits are
configured. It goes from low to high (high to low) on the first compare match
when it is active high (low). It then goes from high to low (low to high) on the
second compare match if the GP timer is in an up-/down-counting mode, or
on period match if the GP timer is in up-counting mode. The timer compare
output becomes high (low) right away when it is specified to be forced high
(low).

Timer Counting Direction

The counting directions of the GP timers are reflected by their respective bits
in GPTCONA/B during all timer operations as follows:

1 represents the up-counting direction

0 represents the down-counting direction

The input pin TDIRA/B determines the direction of counting when a GP timer
is in directional up-/down-counting mode. When TDIRA/B is high, upward
counting is specified; when TDIRA/B is low, downward counting is specified.

Timer Clock
The source of the GP timer clock can be the internal device clock or the
external clock input, TCLKINA/B. The frequency of the external clock must be
less than or equal to one-fourth of that of the device clock. GP timer 2 (EVA)
and GP timer 4 (EVB) can be used with the QEP circuits, in directional

Event Manager (EV) 6-19

General-Purpose (GP) Timers

up-/down-counting mode. In this case, the QEP circuits provide both the clock
and direction inputs to the timer.
A wide range of prescale factors are provided for the clock input to each GP
timer.

QEP-Based Clock Input

The quadrature encoder pulse (QEP) circuit, when selected, can generate the
input clock and counting direction for GP timer 2/4 in the directional
up-/down-counting mode. This input clock cannot be scaled by GP timer
prescaler circuits (that is, the prescaler of the selected GP timer is always one
if the QEP circuit is selected as the clock source). Furthermore, the frequency
of the clock generated by the QEP circuits is four times that of the frequency
of each QEP input channel because both the rising and falling edges of both
QEP input channels are counted by the selected timer. The frequency of the
QEP input must be less than or equal to one-fourth of that of the device clock.

GP Timer Synchronization
GP timer 2 can be synchronized with GP timer 1 (for EVA) and GP timer 4 can
be synchronized with GP timer 3 (for EVB) by proper configuration of T2CON
and T4CON, respectively, in the following ways:

EVA:
Set the T2SWT1 bit in T2CON to start GP timer 2 counting with the TEN-
ABLE bit in T1CON (thus, both timer counters start simultaneously)

EVA:
Initialize the timer counters in GP timers 1 and 2 with different values be-
fore starting synchronized operation

EVA:
Specify that GP timer 2 uses the period register of GP timer 1 as its period
register (ignoring its own period register) by setting SELT1PR in T2CON

EVB:
Set the T4SWT3 bit in T4CON to start GP timer 4 counting with the TEN-
ABLE bit in T3CON (thus, both timer counters start simultaneously)

EVB:
Initialize the timer counters in GP timers 3 and 4 with different values be-
fore starting synchronized operation

EVB:
Specify that GP timer 4 uses the period register of GP timer 3 as its period
register (ignoring its own period register) by setting SELT3PR in T4CON

6-20
 General-Purpose (GP) Timers

This allows the desired synchronization between GP timer events. Since each
GP timer starts the counting operation from its current value in the counter
register, one GP timer can be programmed to start with a known delay after
the other GP timer.

Starting the A/D Converter with a Timer Event

The bits in GPTCONA/B can specify that an ADC start signal be generated on
a GP timer event such as underflow, compare match, or period match. This
feature provides synchronization between the GP timer event and the ADC
start without any CPU intervention.

GP Timer in Emulation Suspend

The GP timer control register bits also define the operation of the GP timers
during emulation suspend. These bits can be set to allow the operation of GP
timers to continue when an emulation interrupt occurs making in-circuit
emulation possible. They can also be set to specify that the operation of GP
timers stops immediately, or after completion of the current counting period,
when emulation interrupt occurs.

Emulation suspend occurs when the device clock is stopped by the emulator,
for example, when the emulator encounters a break point.

GP Timer Interrupts

There are sixteen interrupt flags in the EVAIFRA, EVAIFRB, EVBIFRA, and
EVBIFRB registers for the GP timers. Each of the four GP timers can generate
four interrupts upon the following events:

Overflow: TxOFINT (x = 1, 2, 3, or 4)

Underflow: TxUFINT (x = 1, 2, 3, or 4)

Compare match: TxCINT (x = 1, 2, 3, or 4)

Period match: TxPINT (x = 1, 2, 3, or 4)

A timer compare event (match) happens when the content of a GP timer

counter is the same as that of the compare register. The corresponding
compare interrupt flag is set one clock cycle after the match if the compare
operation is enabled.

Event Manager (EV) 6-21

General-Purpose (GP) Timers

An overflow event occurs when the value of the timer counter reaches FFFFh.
An underflow event occurs when the timer counter reaches 0000h. Similarly,
a period event happens when the value of the timer counter is the same as that
of the period register. The overflow, underflow, and period interrupt flags of the
timer are set one clock cycle after the occurrence of each individual event.
Note that the definition of overflow and underflow is different from their
conventional definitions.

6.3.1 GP Timer Counting Operation

Each GP timer has four possible modes of operation:

Stop/Hold mode

Continuous Up-Counting mode

Directional Up-/Down-Counting mode

Continuous Up-/Down-Counting mode

The bit pattern in the corresponding timer control register TxCON determines
the counting mode of a GP timer. The timer enabling bit, TxCON[6], enables
or disables the counting operation of a timer. When the timer is disabled, the
counting operation of the timer stops and the prescaler of the timer is reset
to x/1. When the timer is enabled, the timer starts counting according to the
counting mode specified by other bits of TxCON.

Stop/Hold Mode
In this mode the GP timer stops and holds at its current state. The timer
counter, the compare output, and the prescale counter all remain unchanged
in this mode.

Continuous Up-Counting Mode

The GP timer in this mode counts up according to the scaled input clock until
the value of the timer counter matches that of the period register. On the next
rising edge of the input clock after the match, the GP timer resets to zero and
starts counting up again.

The period interrupt flag of the timer is set one clock cycle after the match
between the timer counter and period register. A peripheral interrupt request
is generated if the flag is not masked. An ADC start is sent to the ADC module
at the same time the flag is set, if the period interrupt of this timer has been
selected by the appropriate bits in GPTCONA/B to start the ADC.

6-22
 General-Purpose (GP) Timers

One clock cycle after the GP timer becomes 0, the underflow interrupt flag of
the timer is set. A peripheral interrupt request is generated by the flag if it is
unmasked. An ADC start is sent to the ADC module at the same time if the
underflow interrupt flag of this timer has been selected by appropriate bits in
GPTCONA/B to start ADC.

The overflow interrupt flag is set one clock cycle after the value in TxCNT
matches FFFFh. A peripheral interrupt request is generated by the flag if it is
unmasked.

The duration of the timer period is (TxPR) + 1 cycles of the scaled clock input
except for the first period. The duration of the first period is the same if the timer
counter is zero when counting starts.

The initial value of the GP timer can be any value between 0h and FFFFh
inclusive. When the initial value is greater than the value in the period register,
the timer counts up to FFFFh, resets to zero, and continues the operation as
if the initial value was zero. When the initial value in the timer counter is the
same as that of the period register, the timer sets the period interrupt flag,
resets to zero, sets the underflow interrupt flag, and then continues the
operation again as if the initial value was zero. If the initial value of the timer
is between zero and the contents of the period register, the timer counts up to
the period value and continue to finish the period as if the initial counter value
was the same as that of the period register.

The counting direction indication bit in GPTCONA/B is one for the timer in this
mode. Either the external or internal device clock can be selected as the input
clock to the timer. TDIRA/B input is ignored by the GP timer in this counting
mode.

The continuous up-counting mode of the GP timer is particularly useful for the
generation of edge-triggered or asynchronous PWM waveforms and sampling
periods in many motor and motion control systems.

Figure 6−7 shows the continuous up-counting mode of the GP timer.

Event Manager (EV) 6-23

General-Purpose (GP) Timers

Figure 6−7. GP Timer Continuous Up-Counting Mode (TxPR = 3 or 2)

TxPR=4−1=3 TxPR=3−1=2

3 3

Timer value 2 2 2

1 1 1
0 0 0 0

TxCON[6]

Timer clock

As shown in Figure 6−7, GP Timer Continuous Up-Counting Mode (TxPR =

3 or 2), no clock cycle is missed from the time the counter reaches the period
register value to the time it starts another counting cycle.

Directional Up-/Down-Counting Mode

The GP timer in directional up-/down-counting mode counts up or down
according to the scaled clock and TDIRA/B inputs. The GP timer starts
counting up until its value reaches that of the period register (or FFFFh if the
initial count is greater than the period) when the TDIRA/B pin is held high.
When the timer value equals that of its period register (or FFFFh) the timer
resets to zero and continues counting up to the period again. When TDIRA/B
is held low, the GP timer counts down until its value becomes zero. When the
value of the timer has counted down to zero, the timer reloads its counter with
the value in the period register and starts counting down again.
The initial value of the timer can be any value between 0000h to FFFFh. When
the initial value of the timer counter is greater than that of the period register,
the timer counts up to FFFFh before resetting itself to zero and counting up to
the period. If TDIRA/B is low when the timer starts with a value greater than
the period register, it counts down to the value of the period register and
continues counting down to zero, at which point the timer counter gets
reloaded with the value from the period register as normal.
The period, underflow, and overflow interrupt flags, interrupts, and associated
actions are generated on respective events in the same manner as they are
generated in the continuous up-counting mode.
The latency from a change of TDIRA/B to a change of counting direction is one
clock cycle after the end of the current count (that is, after the end of the current
prescale counter period).

6-24
 General-Purpose (GP) Timers

The direction of counting is indicated for the timer in this mode by the
corresponding direction indication bit in GPTCONA/B: 1 means counting up;
0 means counting down. Either the external clock from the TCLKINA/B pin or
the internal device clock can be used as the input clock for the timer in this
mode.

Figure 6−8 shows the directional up-/down-counting mode of the GP timers.

Figure 6−8. GP Timer Directional Up-/Down-Counting Mode: Prescale Factor 1 and

TxPR = 3
65535
65534 TxPR=3
65533
Timer
value 3
3 3
2 2 2 2
1 1 1 1
0 0 0 0

TDIRA/B

TxCON[6]
Timer
CLK

The directional up-/down-counting mode of GP timer 2/4 can be used with the
quadrature encoder pulse (QEP) circuits in the EV module. The QEP circuits
provide both the counting clock and direction for GP timer 2/4 in this case. This
mode of operation can also be used to time the occurrence of external events
in motion/motor control and power electronics applications.

Continuous Up-/Down-Counting Mode

This mode of operation is the same as the directional up-/down-counting
mode, but the TDIRA/B pin has no effect on the counting direction. The
counting direction only changes from up to down when the timer reaches the
period value (or FFFFh if the initial timer value is greater than the period). The
timer direction only changes from down to up when the timer reaches zero.

The period of the timer in this mode is 2*(TxPR) cycles of the scaled clock
input, except for the first period. The duration of the first counting period is the
same if the timer counter is zero when counting starts.

The initial value of the GP timer counter can be any value between 0h and
FFFFh inclusive. When the initial value is greater than that of the period
register, the timer counts up to FFFFh, resets to zero, and continues the

Event Manager (EV) 6-25

General-Purpose (GP) Timers

operation as if the initial value was zero. When the initial value in the timer
counter is the same as that of the period register, the timer counts down to zero
and continues again as if the initial value was zero. If the initial value of the
timer is between zero and the contents of the period register, the timer counts
up to the period value and continues to finish the period as if the initial counter
value was the same as that of the period register.

The period, underflow, and overflow interrupt flags, interrupts, and associated
actions are generated on respective events in the same manner as they are
generated in continuous up-counting mode.

The counting direction indication bit for this timer in GPTCONA/B is one when
the timer counts upward and zero when the timer counts downward. Either the
external clock from the TCLKINA/B pin or the internal device clock can be
selected as the input clock. TDIRA/B input is ignored by the timer in this mode.

Figure 6−9 shows the continuous up-/down-counting mode of the GP timer.

Figure 6−9. GP Timer Continuous Up-/Down-Counting Mode (TxPR = 3 or 2)

TxPR=3 TxPR=2
Timer period
2x(TxPR) Timer
3 period

2 2 2 2
Timer value 1 1 1 1 1 1
0 0 0 0

TxCON[6]

Timer clock

Continuous up-/down-counting mode is particularly useful in generating

centered or symmetric PWM waveforms found in a broad range of
motor/motion control and power electronics applications.

6-26
 General-Purpose (GP) Timers

6.3.2 GP Timer Compare Operation

Each GP timer has an associated compare register TxCMPR and a PWM
output pin TxPWM. The value of a GP timer counter is constantly compared
to that of its associated compare register. A compare match occurs when the
value of the timer counter is the same as that of the compare register. Compare
operation is enabled by setting TxCON[1] to one. If it is enabled, the following
happens on a compare match:

The compare interrupt flag of the timer is set one clock cycle after the
match

A transition occurs on the associated PWM output according to the bit con-
figuration in GPTCONA/B, one device clock cycle after the match

If the compare interrupt flag has been selected by the appropriate

GPTCONA/B bits to start ADC, an ADC start signal is generated at the
same time the compare interrupt flag is set

A peripheral interrupt request is generated by the compare interrupt flag if it

is unmasked.

PWM Transition
The transition on the PWM output is controlled by an asymmetric and
symmetric waveform generator and the associated output logic, and depends
on the following:

Bit definition in GPTCONA/B

Counting mode the timer is in

Counting direction when the counting mode is continuous-up/-down mode

Asymmetric/Symmetric Waveform Generator

The asymmetric/symmetric waveform generator generates an asymmetric or
symmetric PWM waveform based on the counting mode the GP timer is in.

Asymmetric Waveform Generation

An asymmetric waveform (Figure 6−10) is generated when the GP timer is in
continuous up-counting mode. When the GP timer is in this mode, the output
of the waveform generator changes according to the following sequence:

zero before the counting operation starts

remains unchanged until the compare match happens

Event Manager (EV) 6-27

 General-Purpose (GP) Timers

toggles on compare match

remains unchanged until the end of the period

resets to zero at the end of a period on period match, if the new compare
value for the following period is not zero

The output is one for the whole period, if the compare value is zero at the
beginning of a period. The output does not reset to zero if the new compare
value for the following period is zero. This is important because it allows the
generation of PWM pulses of 0% to 100% duty cycle without glitches. The
output is zero for the whole period if the compare value is greater than the
value in the period register. The output is one for one cycle of the scaled clock
input if the compare value is the same as that of the period register.

One characteristic of asymmetric PWM waveforms is that a change in the

value of the compare register only affects one side of the PWM pulse.

Figure 6−10. GP Timer Compare/PWM Output in Up-Counting Mode

Timer Timer
(PWM) (PWM)
period 1 period 2

Compare
match
Timer value
New comp
value greater
than period
TxPWM/TxCMP Active
active low
Inactive
TxPWM/TxCMP
active high Active

Compare matches

Symmetric Waveform Generation

A symmetric waveform (Figure 6−11) is generated when the GP timer is in

continuous up-/down-counting modes. When the GP timer is in this mode, the
state of the output of the waveform generator is determined by the following:

zero before the counting operation starts

Remains unchanged until first compare match

6-28
 General-Purpose (GP) Timers

Toggles on the first compare match

Remains unchanged until the second compare match

Toggles on the second compare match

Remains unchanged until the end of the period

Resets to zero at the end of the period if there is no second compare

match, and the new compare value for the following period is not zero

The output is set to one at the beginning of a period and remains one until the
second compare match if the compare value is zero at the beginning of a
period. After the first transition, the output remains one until the end of the
period if the compare value is zero for the second half of the period. When this
happens, the output does not reset to zero if the new compare value for the
following period is still zero. This is done again to assure the generation of
PWM pulses of 0% to 100% duty cycle without any glitches. The first transition
does not happen if the compare value is greater than or equal to that of the
period register for the first half of the period. However, the output still toggles
when a compare match happens in the second half of the period. This error
in output transition, often as a result of calculation error in the application
routine, is corrected at the end of the period because the output resets to zero,
unless the new compare value for the following period is zero. In this case, the
output remains one, which again puts the output of the waveform generator
in the correct state.

Note:
The output logic determines what the active state is for all output pins.

Event Manager (EV) 6-29

 General-Purpose (GP) Timers

Figure 6−11.GP Timer Compare/PWM Output in Up-/Down-Counting Modes

Timer Timer
(PWM) (PWM)
period 1 period 2
Compare
match
Timer value
Reloaded
comp value
greater
than period
TxPWM/TxCMP Active
active low Inactive

TxPWM/TxCMP
active high

Compare matches

Output Logic
The output logic further conditions the output of the waveform generator to
form the ultimate PWM output that controls different kinds of power devices.
The PWM output can be specified active high, active low, forced low, and
forced high by proper configuration of the appropriate GPTCONA/B bits.

The polarity of the PWM output is the same as that of the output of the
associated asymmetric/symmetric waveform generator when the PWM output
is specified active high.

The polarity of the PWM output is the opposite of that of the output of the
associated asymmetric/symmetric waveform generator when the PWM output
is specified active low.

The PWM output is set to one (or zero) immediately after the corresponding
bits in GPTCONA/B are set, and the bit pattern specifies that the state of PWM
output is forced high (or low).

In summary, during a normal counting mode, transitions on the GP timer PWM

outputs happen according to Table 6−11 for the continuous up-counting mode
and according to Table 6−12 for the continuous up-/down-counting mode,
assuming compare is enabled.

Setting active means setting high for active high and setting low for active low.
Setting inactive means the opposite.

The asymmetric/symmetric waveform generation, based on the timer counting

mode and the output logic, is also applicable to the compare units.

6-30
 General-Purpose (GP) Timers

Table 6−11. GP Timer Compare Output in Continuous Up-Counting Modes

Time in a period State of Compare Output

Before compare match Inactive

On compare match Set active

On period match Set inactive

Table 6−12. GP Timer Compare Output in Continuous Up-/Down-Counting Modes

Time in a period State of Compare Output

Before 1st compare match Inactive

On 1st compare match Set active

On 2nd compare match Set inactive

After 2nd compare match Inactive

All GP timer PWM outputs are put in the high-impedance state when any of
the following events occurs:

GPTCONA/B[6] is set to zero by software

PDPINTx is pulled low and is not masked

Any reset event occurs

TxCON[1] is set to zero by software

Active/Inactive Time Calculation

For the continuous up-counting mode, the value in the compare register
represents the elapsed time between the beginning of a period and the
occurrence of the first compare match (length of the inactive phase). This
elapsed time is equal to the period of the scaled input clock multiplied by the
value of TxCMPR. Therefore, the length of the active phase (the output pulse
width) is given by (TxPR) − (TxCMPR) + 1 cycle of the scaled input clock.

For the continuous up-/down-counting mode, the compare register can have
a different value while counting down from the value while counting up. The
length of the active phase (output pulse width) for up-/down-counting modes
is given by (TxPR) − (TxCMPR)up + (TxPR) − (TxCMPR)dn cycles of the scaled
input clock, where (TxCMPR)up is the compare value on the way up and
(TxCMPR)dn is the compare value on the way down.

Event Manager (EV) 6-31

General-Purpose (GP) Timers

When the value in TxCMPR is zero, the GP timer compare output is active for
the whole period if the timer is in the up-counting mode. For the
up-/down-counting mode, the compare output is active at the beginning of the
period if (TxCMPR)up is zero. The output remains active until the end of the
period if (TxCMPR)dn is also zero.

The length of the active phase (the output pulse width) is zero when the value
of TxCMPR is greater than that of TxPR for up-counting modes. For the
up-/down-counting mode, the first transition is lost when (TxCMPR)up is
greater than or equal to (TxPR). Similarly, the second transition is lost when
(TxCMPR)dn is greater than or equal to (TxPR). The GP timer compare output
is inactive for the entire period if both (TxCMPR)up and TxCMPR)dn are greater
than or equal to (TxPR) for the up-/down-counting mode.

Figure 6−10, GP Timer Compare/PWM Output in Up-Counting Mode

(page 6-28) shows the compare operation of a GP timer in the up-counting
mode. Figure 6−11, GP Timer Compare/PWM Output in Up-/Down-Counting
Modes (page 6-30) shows the compare operation of a GP timer in the
up-/down-counting mode.

6.3.3 Timer Control Registers (TxCON and GPTCONA/B)

The addresses of the GP timer registers are given in Table 6−3 and Table 6−4
on page 6-11. The bit definition of the individual GP timer control registers,
TxCON, is shown in Figure 6−12. The bit definition of the overall GP timer
control registers, GPTCONA and GPTCONB, are shown in Figure 6−13 (on
page 6-35) and Figure 6−14 (on page 6-36), respectively.

Individual GP Timer Control Register (TxCON; x = 1, 2, 3, or 4)

Note:
Each Timer Control Register (TxCON) is independently configurable.

6-32
 General-Purpose (GP) Timers

Figure 6−12. Timer x Control Register (TxCON; x = 1, 2, 3, or 4) — Addresses 7404h

(T1CON), 7408h (T2CON), 7504h (T3CON), and 7508h (T4CON)
15 14 13 12 11 10 9 8

Free Soft Reserved TMODE1 TMODE0 TPS2 TPS1 TPS0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

T2SWT1/ SELT1PR/
TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0 TECMPR
T4SWT3† SELT3PR†

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

† Reserved in T1CON andT3CON

Bits 15−14 Free, Soft. Emulation control bits.

00 Stop immediately on emulation suspend
01 Stop after current timer period is complete on emulation suspend
10 Operation is not affected by emulation suspend
11 Operation is not affected by emulation suspend

Bit 13 Reserved. Reads return zero, writes have no effect.

Bits 12−11 TMODE1−TMODE0. Count Mode Selection.

00 Stop/Hold
01 Continuous-Up/-Down Count Mode
10 Continuous-Up Count Mode
11 Directional-Up/-Down Count Mode

Bits 10−8 TPS2−TPS0. Input Clock Prescaler.

000 x/1 100 x/16
001 x/2 101 x/32
010 x/4 110 x/64
011 x/8 111 x/128
x = device (CPU) clock frequency

Event Manager (EV) 6-33

General-Purpose (GP) Timers

Bit 7 T2SWT1. In the case of EVA, this bit is T2SWT1. (GP timer 2 start with GP tim-
er 1.) Start GP timer 2 with GP timer 1’s timer enable bit. This bit is reserved in
T1CON.
T4SWT3. In the case of EVB, this bit is T4SWT3. (GP timer 4 start with GP
timer 3.) Start GP timer 4 with GP timer 3’s timer enable bit. This bit is reserved
in T3CON.
0 Use own TENABLE bit
1 Use TENABLE bit of T1CON (in case of EVA) or T3CON (in case
of EVB) to enable and disable operation ignoring own TENABLE
bit
Bit 6 TENABLE. Timer enable.
0 Disable timer operation (the timer is put in hold and the prescaler
counter is reset)
1 Enable timer operations
Bits 5−4 TCLKS1, TCLKS0. Clock Source Select.
5 4 Source
0 0 Internal
0 1 External
1 0 Reserved
1 1 QEP Circuit† (in case of Timer 2/Timer 4)
Reserved (in case of Timer 1/Timer 3)
† This option is valid only if SELT1PR = 0

Bits 3−2 TCLD1, TCLD0. Timer Compare Register Reload Condition.

00 When counter is 0
01 When counter value is 0 or equals period register value
10 Immediately
11 Reserved
Bit 1 TECMPR. Timer compare enable.
0 Disable timer compare operation
1 Enable timer compare operation
Bit 0 SELT1PR. In the case of EVA, this bit is SELT1PR (Period register select).
When set to1 in T2CON, the period register of Timer 1 is chosen for Timer 2
also, ignoring the period register of Timer 2. This bit is a reserved bit in T1CON.
SELT3PR. In the case of EVB, this bit is SELT3PR (Period register select).
When set to1 in T4CON, the period register of Timer 3 is chosen for Timer 4
also, ignoring the period register of Timer 4. This bit is a reserved bit in T3CON.
0 Use own period register
1 Use T1PR (in case of EVA) or T3PR (in case of EVB) as period
register ignoring own period register

6-34
 General-Purpose (GP) Timers

Overall GP Timer Control RegisterA (GPTCONA)

Figure 6−13. GP Timer Control Register A (GPTCONA) — Address 7400h

15 14 13 12−11 10−9 8−7

Reserved T2STAT T1STAT Reserved T2TOADC T1TOADC

RW-0 R-1 R-1 RW-0 RW-0 RW-0

6 5−4 3−2 1−0

TCOMPOE Reserved T2PIN T1PIN

RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -n = value after reset

Bit 15 Reserved. Reads return zero; writes have no effect.

Bit 14 T2STAT. GP timer 2 Status. Read only.

0 Counting downward
1 Counting upward

Bit 13 T1STAT. GP timer 1 Status. Read only.

0 Counting downward
1 Counting upward

Bits 12−11 Reserved. Reads return zero; writes have no effect.

Bits 10−9 T2TOADC. Start ADC with timer 2 event.

00 No event starts ADC
01 Setting of underflow interrupt flag starts ADC
10 Setting of period interrupt flag starts ADC
11 Setting of compare interrupt flag starts ADC

Bits 8−7 T1TOADC. Start ADC with timer 1 event.

00 No event starts ADC
01 Setting of underflow interrupt flag starts ADC
10 Setting of period interrupt flag starts ADC
11 Setting of compare interrupt flag starts ADC

Bit 6 TCOMPOE. Compare output enable. If PDPINTx is active this bit is set to zero.
0 Disable all GP timer compare outputs (all compare outputs are put
in the high-impedance state)
1 Enable all GP timer compare outputs

Event Manager (EV) 6-35

General-Purpose (GP) Timers

Bits 5−4 Reserved. Reads return zero; writes have no effect.

Bits 3−2 T2PIN. Polarity of GP timer 2 compare output

00 Forced low
01 Active low
10 Active high
11 Forced high

Bits 1−0 T1PIN. Polarity of GP timer 1 compare output

00 Forced low
01 Active low
10 Active high
11 Forced high

Overall GP Timer Control Register B (GPTCONB)

Figure 6−14. GP Timer Control Register B (GPTCONB) — Address 7500h

15 14 13 12−11 10−9 8−7

Reserved T4STAT T3STAT Reserved T4TOADC T3TOADC

RW-0 R-1 R-1 RW-0 RW-0 RW-0

6 5−4 3−2 1−0

TCOMPOE Reserved T4PIN T3PIN

RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -n = value after reset

Bit 15 Reserved. Reads return zero; writes have no effect.

Bit 14 T4STAT. GP timer 4 Status. Read only.

0 Counting downward
1 Counting upward

Bit 13 T3STAT. GP timer 3 Status. Read only.

0 Counting downward
1 Counting upward

Bits 12−11 Reserved. Reads return zero; writes have no effect.

6-36
 General-Purpose (GP) Timers

Bits 10−9 T4TOADC. Start ADC with timer 4 event.

00 No event starts ADC
01 Setting of underflow interrupt flag starts ADC
10 Setting of period interrupt flag starts ADC
11 Setting of compare interrupt flag starts ADC

Bits 8−7 T3TOADC. Start ADC with timer 3 event.

00 No event starts ADC
01 Setting of underflow interrupt flag starts ADC
10 Setting of period interrupt flag starts ADC
11 Setting of compare interrupt flag starts ADC

Bit 6 TCOMPOE. Compare output enable. If PDPINTx is active this bit is set to zero.
0 Disable all GP timer compare outputs (all compare outputs are put
in the high-impedance state)
1 Enable all GP timer compare outputs

Bits 5−4 Reserved. Reads return zero; writes have no effect.

Bits 3−2 T4PIN. Polarity of GP timer 4 compare output.

00 Forced low
01 Active low
10 Active high
11 Forced high

Bits 1−0 T3PIN. Polarity of GP timer 3 compare output.

00 Forced low
01 Active low
10 Active high
11 Forced high

Event Manager (EV) 6-37

General-Purpose (GP) Timers

6.3.4 Generation of PWM Outputs Using the GP Timers

Each GP timer can independently be used to provide a PWM output channel.
Thus, up to two PWM outputs may be generated by the GP timers.

PWM Operation
To generate a PWM output with a GP timer, a continuous up- or
up-/down-counting mode can be selected. Edge-triggered or asymmetric
PWM waveforms are generated when a continuous-up count mode is
selected. Centered or symmetric PWM waveforms are generated when a
continuous-up/-down mode is selected. To set up the GP timer for the PWM
operation, do the following:

Set up TxPR according to the desired PWM (carrier) period

Set up TxCON to specify the counting mode and clock source, and start
the operation

Load TxCMPR with values corresponding to the on-line calculated widths

(duty cycles) of PWM pulses

The period value is obtained by dividing the desired PWM period by the period
of the GP timer input clock, and subtracting one from the resulting number
when the continuous up-counting mode is selected to generate asymmetric
PWM waveforms. When the continuous up-/down-counting mode is selected
to generate symmetric PWM waveforms, this value is obtained by dividing the
desired PWM period by two times the period of the GP timer input clock.

The GP timer can be initialized the same way as in the previous example.
During run time, the GP timer compare register is constantly updated with
newly determined compare values corresponding to the newly determined
duty cycles.

6.3.5 GP Timer Reset

When any RESET event occurs, the following happens:

All GP timer register bits, except for the counting direction indication bits
in GPTCONA/B, are reset to 0; thus, the operation of all GP timers is dis-
abled. The counting direction indication bits are all set to 1

All timer interrupt flags are reset to 0

All timer interrupt mask bits are reset to 0, except for PDPINTx; thus, all
GP timer interrupts are masked except for PDPINTx

All GP timer compare outputs are put in the high-impedance state

6-38
 Compare Units

6.4 Compare Units

There are three (full) compare units (compare units 1, 2, and 3) in the EVA
module and three (full) compare units (compare units 4, 5, and 6) in the EVB
module. Each compare unit has two associated PWM outputs. The time base
for the compare units is provided by GP timer 1 (for EVA) and by GP timer 3
(for EVB)

The compare units in each EV module include:

Three 16-bit compare registers (CMPR1, CMPR2, and CMPR3 for EVA;
and CMPR4, CMPR5, and CMPR6 for EVB), all with an associated shad-
ow register, (RW)

One 16-bit compare control register (COMCONA for EVA, and COM-
CONB for EVB), (RW)

One 16-bit action control register (ACTRA for EVA, and ACTRB for EVB),
with an associated shadow register, (RW)

Six PWM (3-state) output (compare output) pins (PWMy, y = 1, 2, 3, 4,

5, 6 for EVA and PWMz, z = 7, 8, 9, 10, 11, 12 for EVB)

Control and interrupt logic

The functional block diagram of a compare unit is shown in Figure 6−15.

Figure 6−15. Compare Unit Block Diagram

(For EVA: x = 1, 2, 3; y = 1, 3, 5; z = 1.
For EVB: x = 4, 5, 6; y = 7, 9, 11; z = 3.)

TzCNT
GPTz
counter

ACTR
Compare full compare
logic action control register
(shadowed)

CMPRx
full compare Output
register (shad- PWM circuits logic
owed) PWMy,y+1

Event Manager (EV) 6-39

Compare Units

The time base for the compare units and the associated PWM circuits is
provided by GP timer 1 (for EVA) or GP timer 3 (for EVB), which can be in any
of its counting modes when the compare operation is enabled. Transitions
occur on the compare outputs.

Compare Inputs/Outputs
The inputs to a compare unit include:

Control signals from control registers

GP timer 1/3 (T1CNT/T3CNT) and its underflow and period match signals

RESET

The output of a compare unit is a compare match signal. If the compare

operation is enabled, this match signal sets the interrupt flag and causes
transitions on the two output pins associated with the compare unit.

Compare Operation Modes

The operation mode of the compare units is determined by the bits in
COMCONx. These bits determine:

Whether the compare operation is enabled

Whether the compare outputs are enabled

The condition on which the compare registers are updated with the values
in their shadow registers

Whether space vector PWM mode is enabled

Operation
The following paragraph describes the operation of the EVA compare unit. The
operation of the EVB compare unit is identical. For EVB, GP timer 3 and
ACTRB are used.

The value of the GP timer 1 counter is continuously compared with that of the
compare register. When a match is made, a transition appears on the two
outputs of the compare unit according to the bits in the action control register
(ACTRA). The bits in ACTRA can individually specify each output to be toggled
active high or toggled active-low (if not forced high or low) on a compare match.
The compare interrupt flag associated with a compare unit is set when a
compare match is made between GP timer 1 and the compare register of this

6-40
 Compare Units

compare unit, if compare is enabled. A peripheral interrupt request is

generated by the flag if the interrupt is unmasked. The timing of output
transitions, setting of interrupt flags, and generation of interrupt requests are
the same as that of the GP timer compare operation. The outputs of the
compare units in compare mode are subject to modification by the output logic,
dead band units, and the space vector PWM logic.

Register Setup for Compare Unit Operation

The register setup sequence for compare unit operation requires:

For EVA For EVB

Setting up T1PR Setting up T3PR

Setting up ACTRA Setting up ACTRB

Initializing CMPRx Initializing CMPRx

Setting up COMCONA Setting up COMCONB

Setting up T1CON Setting up T3CON

6.4.1 Compare Units Registers

The addresses of registers associated with compare units and associated
PWM circuits are shown in Table 6−5, Addresses of EVA Compare Control
Registers on page 6-11, and in Table 6−6, Addresses of EVB Compare
Control Registers on page 6-12. These registers are discussed in the
subsections that follow.

Compare Control Registers (COMCONA and COMCONB)

The operation of the compare units is controlled by the compare control

registers (COMCONA and COMCONB). The bit definition of COMCONA is
summarized in Figure 6−16 and that of COMCONB is summarized in
Figure 6−17. COMCONA and COMCONB are readable and writeable.

Event Manager (EV) 6-41

Compare Units

Figure 6−16. Compare Control Register A (COMCONA) — Address 7411h

15 14 13 12 11 10 9 8

PDPINTA
CENABLE CLD1 CLD0 SVENABLE ACTRLD1 ACTRLD0 FCOMPOE
STATUS

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R-

PDPINTA
PIN
7−0

Reserved

R-0
Note: R = Read access, W = Write access, -0 = value after reset

Bit 15 CENABLE. Compare enable

0 Disables compare operation. All shadowed registers (CMPRx,
ACTRA) become transparent
1 Enables compare operation

Bits14−13 CLD1, CLD0. Compare register CMPRx reload condition

00 When T1CNT = 0 (that is, on underflow)
01 When T1CNT = 0 or T1CNT = T1PR (that is, on underflow or
period match)
10 Immediately
11 Reserved; result is unpredictable

Bit 12 SVENABLE. Space vector PWM mode enable

0 Disables space vector PWM mode
1 Enables space vector PWM mode

Bits 11−10 ACTRLD1, ACTRLD0. Action control register reload condition

00 When T1CNT = 0 (on underflow)
01 When T1CNT = 0 or T1CNT = T1PR (on underflow or period
match)
10 Immediately
11 Reserved

6-42
 Compare Units

Bit 9 FCOMPOE. Compare output enable. Active PDPINTA clears this bit to zero.
0 PWM output pins are in high-impedance state; that is, they are
disabled
1 PWM output pins are not in high-impedance state; that is, they are
enabled

Bit 8 PDPINTA STATUS. This bit reflects the current status of the PDPINTA pin. An
application could poll this bit to determine whether the fault that activated this
pin has disappeared. (This bit is applicable to 240xA devices only — it is re-
served on 240x devices and returns a zero when read.)

Bits 7−0 Reserved. Read returns zero; writes have no effect.

Figure 6−17. Compare Control Register B (COMCONB) — Address 7511h

15 14 13 12 11 10 9 8

PDPINTB
CENABLE CLD1 CLD0 SVENABLE ACTRLD1 ACTRLD0 FCOMPOE
STATUS

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R-

PDPINTB
PIN
7−0

Reserved

R-0
Note: R = Read access, W = Write access, -0 = value after reset

Bit 15 CENABLE. Compare enable.

0 Disable compare operation. All shadowed registers (CMPRx,
ACTRB) become transparent
1 Enable compare operation

Bits14−13 CLD1, CLD0. Compare register CMPRx reload condition.

00 When T3CNT = 0 (that is, on underflow)
01 When T3CNT = 0 or T3CNT = T3PR (that is, on underflow or
period match)
10 Immediately
11 Reserved; result is unpredictable

Bit 12 SVENABLE. Space vector PWM mode enable.

0 Disables space vector PWM mode
1 Enables space vector PWM mode

Event Manager (EV) 6-43

Compare Units

Bits 11−10 ACTRLD1, ACTRLD0. Action control register reload condition.

00 When T3CNT = 0 (on underflow)
01 When T3CNT = 0 or T3CNT = T3PR (on underflow or period
match)
10 Immediately
11 Reserved

Bit 9 FCOMPOE. Compare output enable. Active PDPINTB clears this bit to zero.
0 PWM output pins are in high-impedance state; that is, they are dis-
abled
1 PWM output pins are not in high-impedance state; that is, they are
enabled

Bit 8 PDPINTB STATUS. This bit reflects the current status of the PDPINTB pin. An
application could poll this bit to determine whether the fault that activated this
pin has disappeared. (This bit is applicable to 240xA devices only — it is re-
served on 240x devices and returns a zero when read.)

Bits 7−0 Reserved. Read returns zero; writes have no effect.

Compare Action Control Registers (ACTRA and ACTRB)

The compare action control registers (ACTRA and ACTRB) control the action
that takes place on each of the six compare output pins (PWMx, where x = 1−6
for ACTRA, and x = 7−12 for ACTRB) on a compare event, if the compare
operation is enabled by COMCONx[15]. ACTRA and ACTRB are double-
buffered. The condition on which ACTRA and ACTRB is reloaded is defined
by bits in COMCONx. ACTRA and ACTRB also contain the SVRDIR, D2, D1,
and D0 bits needed for space vector PWM operation. The bit configuration of
ACTRA is described in Figure 6−18 and that of ACTRB is described in
Figure 6−19.

Figure 6−18. Compare Action Control Register A (ACTRA) — Address 7413h

15 14 13 12 11 10 9 8

SVRDIR D2 D1 D0 CMP6ACT1 CMP6ACT0 CMP5ACT1 CMP5ACT0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

CMP4ACT1 CMP4ACT0 CMP3ACT1 CMP3ACT0 CMP2ACT1 CMP2ACT0 CMP1ACT1 CMP1ACT0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

6-44
 Compare Units

Bit 15 SVRDIR. Space vector PWM rotation direction. Used only in space vector
PWM output generation.
0 Positive (CCW)
1 Negative (CW)

Bits 14−12 D2−D0. Basic space vector bits. Used only in space vector PWM output gener-
ation.

Bits 11−10 CMP6ACT1−0. Action on compare output pin 6, CMP6.

00 Forced low
01 Active low
10 Active high
11 Forced high

Bits 9−8 CMP5ACT1−0. Action on compare output pin 5, CMP5.

00 Forced low
01 Active low
10 Active high
11 Forced high

Bits 7−6 CMP4ACT1−0. Action on compare output pin 4, CMP4.

00 Forced low
01 Active low
10 Active high
11 Forced high

Bits 5−4 CMP3ACT1−0. Action on compare output pin 3, CMP3.

00 Forced low
01 Active low
10 Active high
11 Forced high

Bits 3−2 CMP2ACT1−0. Action on compare output pin 2, CMP2.

00 Forced low
01 Active low
10 Active high
11 Forced high

Event Manager (EV) 6-45

Compare Units

Bits 1−0 CMP1ACT1−0. Action on compare output pin 1, CMP1.

00 Forced low
01 Active low
10 Active high
11 Forced high

Figure 6−19. Compare Action Control Register B (ACTRB) — Address 7513h

15 14 13 12 11 10 9 8

SVRDIR D2 D1 D0 CMP12ACT1 CMP12ACT0 CMP11ACT1 CMP11ACT0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

CMP10ACT1 CMP10ACT0 CMP9ACT1 CMP9ACT0 CMP8ACT1 CMP8ACT0 CMP7ACT1 CMP7ACT0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

Bit 15 SVRDIR. Space vector PWM rotation direction. Used only in space vector
PWM output generation.
0 Positive (CCW)
1 Negative (CW)
Bits 14−12 D2−D0. Basic space vector bits. Used only in space vector PWM output
generation.
Bits 11−10 CMP12ACT1−0. Action on compare output pin 12, CMP12.
00 Forced low
01 Active low
10 Active high
11 Forced high
Bits 9−8 CMP11ACT1−0. Action on compare output pin 11, CMP11.
00 Forced low
01 Active low
10 Active high
11 Forced high
Bits 7−6 CMP10ACT1−0. Action on compare output pin 10, CMP10.
00 Forced low
01 Active low
10 Active high
11 Forced high

6-46
 Compare Units

Bits 5−4 CMP9ACT1−0. Action on compare output pin 9, CMP9.

00 Forced low
01 Active low
10 Active high
11 Forced high

Bits 3−2 CMP8ACT1−0. Action on compare output pin 8, CMP8.

00 Forced low
01 Active low
10 Active high
11 Forced high

Bits 1−0 CMP7ACT1−0. Action on compare output pin 7, CMP7.

00 Forced low
01 Active low
10 Active high
11 Forced high

6.4.2 Compare Unit Interrupts

There is a maskable interrupt flag in EVAIFRA and EVBIFRA for each compare
unit. The interrupt flag of a compare unit is set one clock cycle after a compare
match, if a compare operation is enabled. A peripheral interrupt request is
generated by the flag if it is unmasked.

6.4.3 Compare Unit Reset

When any reset event occurs, all register bits associated with the compare
units are reset to zero and all compare output pins are put in the
high-impedance state.

Event Manager (EV) 6-47

PWM Circuits Associated With Compare Units

6.5 PWM Circuits Associated With Compare Units

The PWM circuits associated with compare units make it possible to generate
six PWM output channels (per EV) with programmable dead-band and output
polarity. The EVA PWM circuits functional block diagram is shown in
Figure 6−20. It includes the following functional units:

Asymmetric/Symmetric Waveform Generators

Programmable Dead-Band Unit (DBU)

Output Logic

Space Vector (SV) PWM State Machine

The EVB PWM circuits functional block diagram is identical to that of the EVA’s
with the corresponding change of configuration registers.

The asymmetric/symmetric waveform generators are the same as those of the

GP timers. The dead-band units and output logic are discussed in
sections 6.5.2 and 6.5.3, respectively. The space vector PWM state machine
and the space vector PWM technique are described later in this chapter.

Figure 6−20. PWM Circuits Block Diagram

TXCON[12−11]

Sym/asym
waveform COMCONA[9]
generator

Compare PHx DTPHx

matches x=1,2,3 Dead DTPHx_
Output PWM1
MUX band
GPT1 flags logic PWM6
units

SVPWM
state ACTRA
DBTCONA
machine full compare
dead-band
COMCONA[12] timer control action control
register register

ACTRA[12−15]

6-48
 PWM Circuits Associated With Compare Units

The PWM circuits are designed to minimize CPU overhead and user
intervention when generating pulse width modulated waveforms used in motor
control and motion control applications. PWM generation with compare units
and associated PWM circuits are controlled by the following control registers:
T1CON, COMCONA, ACTRA, and DBTCONA (in case of EVA); and T3CON,
COMCONB, ACTRB, and DBTCONB (in case of EVB).

6.5.1 PWM Generation Capability of Event Manager

The PWM waveform generation capability of each event manager module
(A and B) is summarized as follows:

Five independent PWM outputs, three of which are generated by the

compare units; the other two are generated by the GP timer compares −
plus three additional PWM outputs, dependent on the three compare unit
PWM outputs

Programmable dead-band for the PWM output pairs associated with the
compare units

Minimum dead-band duration of one device clock cycle

Minimum PWM pulsewidth and pulsewidth increment/decrement of one

clock cycle

16-bit maximum PWM resolution

On-the-fly change of PWM carrier frequency (double buffered period reg-

isters)

On-the-fly change of PWM pulsewidths (double buffered compare regis-

ters)

Power Drive Protection Interrupt

Programmable generation of asymmetric, symmetric, and space vector

PWM waveforms

Minimum CPU overhead because of the auto-reloading of the compare

and period registers

Event Manager (EV) 6-49

PWM Circuits Associated With Compare Units

6.5.2 Programmable Dead-Band (Dead-Time) Unit

EVA and EVB have their own programmable dead-band units (DBTCONA and
DBTCONB, respectively). The programmable dead-band unit features:

One 16-bit dead-band control register, DBTCONx (RW)

One input clock prescaler: x/1, x/2, x/4, etc., to x/32

Device (CPU) clock input

Three 4-bit down-counting timers

Control logic

Dead-Band Timer Control Registers A and B (DBTCONA and DBTCONB)

The operation of the dead-band unit is controlled by the dead-band timer
control registers (DBTCONA and DBTCONB). The bit description of
DBTCONA is given in Figure 6−21 and that of DBTCONB is given in
Figure 6−22.

Figure 6−21. Dead-Band Timer Control Register A (DBTCONA) — Address xx15h

15−12 11 10 9 8

Reserved DBT3 DBT2 DBT1 DBT0

R-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1−0

EDBT3 EDBT2 EDBT1 DBTPS2 DBTPS1 DBTPS0 Reserved

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R-0

Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−12 Reserved. Reads return zero; writes have no effect.

Bits 11−8 DBT3 (MSB)−DBT0 (LSB). Dead-band timer period. These bits define the pe-
riod value of the three 4-bit dead-band timers.
Bit 7 EDBT3. Dead-band timer 3 enable (for pins PWM5 and PWM6 of Compare
Unit 3).
0 Disable
1 Enable
Bit 6 EDBT2. Dead-band timer 2 enable (for pins PWM3 and PWM4 of Compare
Unit 2).
0 Disable
1 Enable

6-50
 PWM Circuits Associated With Compare Units

Bit 5 EDBT1. Dead-band timer 1 enable (for pins PWM1 and PWM2 of Compare
Unit 1).
0 Disable
1 Enable
Bits 4−2 DBTPS2 to DBTPS0. Dead-band timer prescaler.
000 x/1
001 x/2
010 x/4
011 x/8
100 x/16
101 x/32
110 x/32
111 x/32
x = Device (CPU) clock frequency
Bits 1−0 Reserved. Reads return zero; writes have no effect.

Figure 6−22. Dead-Band Timer Control Register B (DBTCONB) — Address xx15h

15−12 11 10 9 8

Reserved DBT3 DBT2 DBT1 DBT0

R-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1−0

EDBT3 EDBT2 EDBT1 DBTPS2 DBTPS1 DBTPS0 Reserved

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R-0

Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−12 Reserved. Reads return zero; writes have no effect.

Bits 11−8 DBT3 (MSB)−DBT0 (LSB). Dead-band timer period. These bits define the pe-
riod value of the three 4-bit dead-band timers.
Bit 7 EDBT3. Dead-band timer 3 enable (for pins PWM11 and PWM12 of Compare
Unit 6).
0 Disable
1 Enable
Bit 6 EDBT2. Dead-band timer 2 enable (for pins PWM9 and PWM10 of Compare
Unit 5).
0 Disable
1 Enable

Event Manager (EV) 6-51

PWM Circuits Associated With Compare Units

Bit 5 EDBT1. Dead-band timer 1 enable (for pins PWM7 and PWM8 of Compare
Unit 4).
0 Disable
1 Enable

Bits 4−2 DBTPS2 to DBTPS0. Dead-band timer prescaler.

000 x/1
001 x/2
010 x/4
011 x/8
100 x/16
101 x/32
110 x/32
111 x/32
x = Device (CPU) clock frequency

Bits 1−0 Reserved. Reads return zero; writes have no effect.

Inputs and Outputs of Dead-Band Unit

The inputs to the dead-band unit are PH1, PH2, and PH3 from the
asymmetric/symmetric waveform generators of compare units 1, 2, and 3,
respectively.

The outputs of the dead-band unit are DTPH1, DTPH1_, DTPH2, DTPH2_,
DTPH3, and DTPH3_, corresponding to PH1, PH2, and PH3, respectively.

Dead Band Generation

For each input signal PHx, two output signals, DTPHx and DTPHx_, are
generated. When dead-band is not enabled for the compare unit and its
associated outputs, the two signals are exactly the same. When the
dead-band unit is enabled for the compare unit, the transition edges of the two
signals are separated by a time interval called dead-band. This time interval
is determined by the DBTCONx bits. If you assume that the value in
DBTCONx[11−8] is m, and that the value in DBTCONx[4−2] corresponds to
prescaler x/p, then the dead-band value is (p*m) device clock cycles.

Table 6−13, on page 6-53, shows the dead-band generated by typical bit
combinations in DBTCONx. The values are based on a 25 ns device clock.
Figure 6−23, on page 6-54, shows the block diagram of the dead-band logic
for one compare unit.

6-52
 PWM Circuits Associated With Compare Units

Table 6−13. Dead-Band Generation Examples

DBTPS2−DBTPS0 (p)
(DBTCONx[4−2])
DBT3−DBT0 (m) 110 and
(DBTCONx[11−8]) 1x1 (P=32) 100 (P=16) 011 (P=8) 010 (P=4) 001 (P=2) 000 (P=1)
0 0 0 0 0 0 0

1 0.8 0.4 0.2 0.1 0.05 0.025

2 1.6 0.8 0.4 0.2 0.1 0.05

3 2.4 1.2 0.6 0.3 0.15 0.075

4 3.2 1.6 0.8 0.4 0.2 0.1

5 4 2 1 0.5 0.25 0.125

6 4.8 2.4 1.2 0.6 0.3 0.15

7 5.6 2.8 1.4 0.7 0.35 0.175

8 6.4 3.2 1.6 0.8 0.4 0.2

9 7.2 3.6 1.8 0.9 0.45 0.225

A 8 4 2 1 0.5 0.25

B 8.8 4.4 2.2 1.1 0.55 0.275

C 9.6 4.8 2.4 1.2 0.6 0.3

D 10.4 5.2 2.6 1.3 0.65 0.325

E 11.2 5.6 2.8 1.4 0.7 0.35

F 12 6 3 1.5 0.75 0.375

Note: Table values are given in µs.

Event Manager (EV) 6-53

PWM Circuits Associated With Compare Units

Figure 6−23. Dead-Band Unit Block Diagram (x = 1, 2, or 3)

Internal CPU clock

DBTCONx
dead-band
Prescale
control
register

CLK
PHx
from waveform Edge
EN Counter
generators/SV detect
state machine

Compare
logic

DBTCONx
dead-band
control
register

DTPHx

DTPHx_

PHx

DTPHx

Dead band

DTPHx_

Note: Signals such as PHx, DTPHx, and DTPHx are internal to the device, and as such, external monitoring/control of these
signals is not possible.

6-54
 PWM Circuits Associated With Compare Units

Other Important Features of Dead-Band Units

The dead-band unit is designed to prevent an overlap under any operating

situation between the turn-on period of the upper and lower devices controlled
by the two PWM outputs associated with each compare unit. This includes
those situations where you have loaded a dead-band value greater than that
of the duty cycle, and when the duty cycle is 100% or 0%. As a result, the PWM
outputs associated with a compare unit do not reset to an inactive state at the
end of a period when dead band is enabled for the compare unit.

6.5.3 Output Logic

The output logic circuit determines the polarity and/or the action that must be
taken on a compare match for outputs PWMx, for x = 1−12. The outputs
associated with each compare unit can be specified active low, active high,
forced low, or forced high. The polarity and/or the action of the PWM outputs
can be programmed by proper configuration of bits in the ACTR register. The
PWM output pins can all be put in the high-impedance state by any of the
following:

Software clearing the COMCONx[9] bit

Hardware pulling PDPINTx low when PDPINTx is unmasked

The occurrence of any reset event

Active PDPINTx (when enabled) and system reset override the bits in
COMCONx and ACTRx

Figure 6−24, on page 6-56, shows a block diagram of the output logic circuit
(OLC). The inputs of Output Logic for the compare units are:

DTPH1, DTPH1_, DTPH2, DTPH2_, DTPH3, and DTPH3_ from the

dead-band unit and compare match signals

The control bits of ACTRx

PDPINTx and RESET

The outputs of the Output Logic for the compare units are:

PWMx, x = 1−6 (for EVA)

PWMy, y = 7−12 (for EVB)

Event Manager (EV) 6-55

PWM Circuits Associated With Compare Units

Figure 6−24. Output Logic Block Diagram (x = 1, 2, or 3; y = 1, 2, 3, 4, 5, or 6)

ACTR[0−1, 2−3, . . . or 10−11]

10
DTPHx
or MUX
DTPHx_
01 PWMy
“1” 11
“0” 00
COMCON[9]

Output logic for PWM mode

6-56
 PWM Waveform Generation With Compare Units and PWM Circuits

6.6 PWM Waveform Generation With Compare Units and PWM Circuits
A pulse width modulated (PWM) signal is a sequence of pulses with changing
pulse widths. The pulses are spread over a number of fixed-length periods so
that there is one pulse in each period. The fixed period is called the PWM
(carrier) period and its inverse is called the PWM (carrier) frequency. The
widths of the PWM pulses are determined, or modulated, from pulse to pulse
according to another sequence of desired values, the modulating signal.
In a motor control system, PWM signals are used to control the on and off time
of switching power devices that deliver the desired current and energy to the
motor windings (see Figure 6−27 on page 6-62). The shape and frequency of
the phase currents and the amount of energy delivered to the motor windings
control the required speed and torque of the motor. In this case, the command
voltage or current to be applied to the motor is the modulating signal. The
frequency of the modulating signal is typically much lower than the PWM
carrier frequency.

PWM Signal Generation

To generate a PWM signal, an appropriate timer is needed to repeat a counting
period that is the same as the PWM period. A compare register is used to hold
the modulating values. The value of the compare register is constantly
compared with the value of the timer counter. When the values match, a
transition (from low to high, or high to low) happens on the associated output.
When a second match is made between the values, or when the end of a timer
period is reached, another transition (from high to low, or low to high) happens
on the associated output. In this way, an output pulse is generated whose on
(or off) duration is proportional to the value in the compare register. This
process is repeated for each timer period with different (modulating) values in
the compare register. As a result, a PWM signal is generated at the associated
output.

Dead Band
In many motion/motor and power electronics applications, two power devices,
an upper and a lower, are placed in series on one power converter leg. The
turn-on periods of the two devices must not overlap with each other in order
to avoid a shoot-through fault. Thus, a pair of non-overlapping PWM outputs
is often required to properly turn on and off the two devices. A dead time
(dead-band) is often inserted between the turning-off of one transistor and the
turning-on of the other transistor. This delay allows complete turning-off of one
transistor before the turning-on of the other transistor. The required time delay
is specified by the turning-on and turning-off characteristics of the power
transistors and the load characteristics in a specific application.

Event Manager (EV) 6-57

PWM Waveform Generation With Compare Units and PWM Circuits

6.6.1 Generation of PWM Outputs With Event Manager

Each of the three compare units, together with GP timer 1 (in the case of EVA)
or GP timer 3 (in the case of EVB), the dead-band unit, and the output logic
in the event manager module, can be used to generate a pair of PWM outputs
with programmable dead-band and output polarity on two dedicated device
pins. There are six such dedicated PWM output pins associated with the three
compare units in each EV module. These six dedicated output pins can be
used to conveniently control 3-phase AC induction or brushless DC motors.
The flexibility of output behavior control by the compare action control register
(ACTRx) also makes it easy to control switched reluctance and synchronous
reluctance motors in a wide range of applications. The PWM circuits can also
be used to conveniently control other types of motors such as DC brush and
stepper motors in single or multi-axis control applications. Each GP timer
compare unit, if desired, can also generate a PWM output based on its own
timer.

Asymmetric and Symmetric PWM Generation

Both asymmetric and symmetric PWM waveforms can be generated by every

compare unit on the EV module. In addition, the three compare units together
can be used to generate 3-phase symmetric space vector PWM outputs. PWM
generation with GP timer compare units has been described in the GP timer
sections. Generation of PWM outputs with the compare units is discussed in
this section.

6.6.2 Register Setup for PWM Generation

All three kinds of PWM waveform generations with compare units and
associated circuits require configuration of the same Event Manager registers.
The setup process for PWM generation includes the following steps:

Setup and load ACTRx

Setup and load DBTCONx, if dead-band is to be used

Initialize CMPRx

Setup and load COMCONx

Setup and load T1CON (for EVA) or T3CON (for EVB) to start the opera-
tion

Rewrite CMPRx with newly determined values

6-58
 PWM Waveform Generation With Compare Units and PWM Circuits

6.6.3 Asymmetric PWM Waveform Generation

The edge-triggered or asymmetric PWM signal is characterized by modulated
pulses which are not centered with respect to the PWM period, as shown in
Figure 6−25. The width of each pulse can only be changed from one side of
the pulse.

Figure 6−25. Asymmetric PWM Waveform Generation With Compare Unit and PWM Circuits
(x = 1, 3, or 5)
Timer Timer
(PWM) (PWM)
period 1 period 1 Compare value
greater than
period
Timer value

PWMx
(active high)
Dead band
PWMx+1
(active low)

Compare matches

To generate an Asymmetric PWM signal, GP timer 1 is put in the continuous

up-counting mode and its period register is loaded with a value corresponding
to the desired PWM carrier period. The COMCONx is configured to enable the
compare operation, set the selected output pins to be PWM outputs, and
enable the outputs. If dead-band is enabled, the value corresponding to the
required dead-band time should be written by software into the DBT(3:0) bits
in DBTCONx(11:8). This is the period for the 4-bit dead-band timers. One
dead-band value is used for all PWM output channels.
By proper configuration of ACTRx with software, a normal PWM signal can be
generated on one output associated with a compare unit while the other is held
low (or off) or high (or on), at the beginning, middle, or end of a PWM period.
Such software controlled flexibility of PWM outputs is particularly useful in
switched reluctance motor control applications.

Event Manager (EV) 6-59

PWM Waveform Generation With Compare Units and PWM Circuits

After GP timer 1 (or GP timer 3) is started, the compare registers are rewritten
every PWM period with newly determined compare values to adjust the width
(the duty cycle) of PWM outputs that control the switch-on and -off duration of
the power devices. Since the compare registers are shadowed, a new value
can be written to them at any time during a period. For the same reason, new
values can be written to the action and period registers at any time during a
period to change the PWM period or to force changes in the PWM output
definition.

6.6.4 Symmetric PWM Waveform Generation

A centered or symmetric PWM signal is characterized by modulated pulses
which are centered with respect to each PWM period. The advantage of a
symmetric PWM signal over an asymmetric PWM signal is that it has two
inactive zones of the same duration: at the beginning and at the end of each
PWM period. This symmetry has been shown to cause less harmonics than
an asymmetric PWM signal in the phase currents of an AC motor, such as
induction and DC brushless motors, when sinusoidal modulation is used.
Figure 6−26 shows two examples of symmetric PWM waveforms.

Figure 6−26. Symmetric PWM Waveform Generation With Compare Units and PWM
Circuits (x = 1, 3, or 5)
Timer (PWM)
period 1

Timer value

PWMx (activelow)
Dead time
PWMx+1 (active high)

Compare matches

The generation of a symmetric PWM waveform with a compare unit is similar

to the generation of an asymmetric PWM waveform. The only exception is that
GP timer 1 (or GP timer 3) now needs to be put in continuous
up-/down-counting mode.

6-60
 PWM Waveform Generation With Compare Units and PWM Circuits

There are usually two compare matches in a PWM period in symmetric PWM
waveform generation, one during the upward counting before period match,
and another during downward counting after period match. A new compare
value becomes effective after the period match (reload on period) because
itmakes it possible to advance or delay the second edge of a PWM pulse. An
application of this feature is when a PWM waveform modification
compensates for current errors caused by the dead-band in AC motor control.

Because the compare registers are shadowed, a new value can be written to
them at any time during a period. For the same reason, new values can be
written to the action and period registers at any time during a period to change
the PWM period or to force changes in the PWM output definition.

6.6.5 Double Update PWM Mode

The 240xA Event Manager supports “Double Update PWM Mode.” This mode
refers to a PWM operation mode in which the position of the leading edge and
the position of the trailing edge of a PWM pulse are independently modifiable
in each PWM period. To support this mode, the compare register that
determines the position of the edges of a PWM pulse must allow (buffered)
compare value update once at the beginning of a PWM period and another
time in the middle of a PWM period.

The compare registers in 240xA Event Managers are all buffered and support
three compare value reload/update (value in buffer becoming active) modes.
These modes have earlier been documented as compare value reload
conditions. The reload condition that supports double update PWM mode is
reloaded on underflow (beginning of PWM period) OR period (middle of PWM
period). Double update PWM mode can be achieved by using this condition
for compare value reload.

Event Manager (EV) 6-61

Space Vector PWM

6.7 Space Vector PWM

Space vector PWM refers to a special switching scheme of the six power
transistors of a 3-phase power converter. It generates minimum harmonic
distortion to the currents in the windings of a 3-phase AC motor. It also provides
more efficient use of supply voltage in comparison with the sinusoidal
modulation method.

6.7.1 3-Phase Power Inverter

The structure of a typical 3-phase power inverter is shown in Figure 6−27,
where Va, Vb, and Vc are the voltages applied to the motor windings. The six
power transistors are controlled by DTPHx and DTPHx_ (x = a, b, and c). When
an upper transistor is switched on (DTPHx = 1), the lower transistor is switched
off (DTPHx_ = 0). Thus, the on and off states of the upper transistors (Q1, Q3,
and Q5) or, equivalently, the state of DTPHx (x = a, b, and c) are sufficient to
evaluate the applied motor voltage Uout.

Figure 6−27. 3-Phase Power Inverter Schematic Diagram

Udc

DTPHa Q1 DTPHb Q3 DTPHc Q5

Va Vb Vc

DTPHa_ Q2 DTPHb_ Q4 DTPHc_ Q6

GND

Power Inverter Switching Patterns and the Basic Space Vectors

When an upper transistor of a leg is on, the voltage Vx (x = a, b, or c) applied

by the leg to the corresponding motor winding is equal to the voltage
supply Udc. When it is off, the voltage applied is zero. The on and off switching
of the upper transistors (DTPHx, x = a, b, or c) have eight possible
combinations. The eight combinations and the derived motor line-to-line and
phase voltage in terms of DC supply voltage Udc are shown in Table 6−14, on
page 6-63, where a, b, and c represent the values of DTPHa, DTPHb, and
DTPHc, respectively.

6-62
 Space Vector PWM

Table 6−14. Switching Patterns of a 3-Phase Power Inverter

a b c Va0(Udc) Vb0(Udc) Vc0(Udc) Vab(Udc) Vbc(Udc) Vca(Udc)

0 0 0 0 0 0 0 0 0

0 0 1 −1/3 −1/3 2/3 0 −1 1

0 1 0 −1/3 2/3 −1/3 −1 1 0

0 1 1 −2/3 1/3 1/3 −1 0 1

1 0 0 2/3 −1/3 −1/3 1 0 −1

1 0 1 1/3 −2/3 1/3 1 −1 0

1 1 0 1/3 1/3 −2/3 0 1 −1

1 1 1 0 0 0 0 0 0

Note: 0 = off, 1 = on

Mapping the phase voltages corresponding to the eight combinations onto the
d-q plane by performing a d-q transformation (which is equivalent to an
orthogonal projection of the 3-vectors (a b c) onto the two dimensional plane
perpendicular to the vector (1,1,1), the d-q plane), results in six nonzero
vectors and two zero vectors. The nonzero vectors form the axes of a
hexagonal. The angle between two adjacent vectors is 60 degrees. The two
zero vectors are at the origin. These eight vectors are called the basic space
vectors and are denoted by U0, U60, U120, U180, U240, U300, O000, and O111.
The same transformation can be applied to the demanded voltage vector Uout
to be applied to a motor. Figure 6−28 shows the projected vectors and the
projected desired motor voltage vector Uout.

The d axis and q axis of a d-q plane correspond here to the horizontal and
vertical geometrical axes of the stator of an AC machine.

The objective of the space vector PWM method is to approximate the motor
voltage vector Uout by a combination of these eight switching patterns of the
six power transistors.

Event Manager (EV) 6-63

Space Vector PWM

Figure 6−28. Basic Space Vectors and Switching Patterns

CCW direction
U120 (010) U60 (011) (SVRDIR=0)

T2 Uout

U380 (110) U0 (001)

T1

U140 (100) U300 (101) CW direction

(SVRDIR=1)

The binary representations of two adjacent basic vectors are different in only
one bit; that is, only one of the upper transistors switches when the switching
pattern switches from Ux to Ux+60 or from Ux+60 to Ux. Also, the zero vectors
O000 and O111 apply no voltage to the motor.

Approximation of Motor Voltage with Basic Space Vectors

The projected motor voltage vector Uout, at any given time, falls into one of the
six sectors. Thus, for any PWM period, it can be approximated by the vector
sum of two vector components lying on the two adjacent basic vectors:
Uout = T1 Ux + T2 Ux+60 + T0 (O000 or O111)
where T0 is given by Tp−T1−T2 and Tp is the PWM carrier period. The third term
on the right side of the equation does not affect the vector sum Uout. The
generation of Uout is beyond the scope of this context. For more details on
space vector PWM and motor control theory, see The Field Orientation
Principle in Control of Induction Motors by Andrzej M. Trzynadlowski (The
Kluwer International Series in Engineering and Computer Science, Vol.
258:Power).
The above approximation means that the upper transistors must have the on
and off pattern corresponding to Ux and Ux+60 for the time duration of T1 and
T2, respectively, in order to apply voltage Uout to the motor. The inclusion of
zero basic vectors helps to balance the turn on and off periods of the
transistors, and thus their power dissipation.

6.7.2 Space Vector PWM Waveform Generation with Event Manager

The EV module has built-in hardware to greatly simplify the generation of
symmetric space vector PWM waveforms. Software is used to generate space
vector PWM outputs.

6-64
 Space Vector PWM

Software
To generate space vector PWM outputs, the user software must:

Configure ACTRx to define the polarity of the compare output pins

Configure COMCONx to enable compare operation and space vector

PWM mode, and set the reload condition for CMPRx to be underflow

Put GP timer 1 (or GP timer 3) in continuous up-/down-counting mode to
start the operation
The user software then needs to determine the voltage Uout to be applied to
the motor phases in the two dimensional d-q plane, decompose Uout, and
perform the following for each PWM period:

Determine the two adjacent vectors, Ux and Ux+60

Determine the parameters T1, T2, and T0

Write the switching pattern corresponding to Ux in ACTRx[14−12] and 1

in ACTRx[15], or the switching pattern of Ux+60 in ACTRx[14−12] and 0 in
ACTRx[15]

Put (1/2 T1) in CMPR1 and (1/2 T1 + 1/2 T2) in CMPR2

Space Vector PWM Hardware

The space vector PWM hardware in the EV module does the following to
complete a space vector PWM period:

At the beginning of each period, sets the PWM outputs to the (new) pattern
Uy defined by ACTRx[14−12]

On the first compare match during up-counting between CMPR1 and GP
timer 1 at (1/2 T1), switches the PWM outputs to the pattern of Uy+60 if
ACTRx[15] is 1, or to the pattern of Uy if ACTRx[15] is 0 (U0−60 = U300,
U360+60 = U60)

On the second compare match during up-counting between CMPR2 and
GP timer 1 at (1/2 T1 + 1/2 T2), switches the PWM outputs to the pattern
(000) or (111), whichever differs from the second pattern by one bit

On the first compare match during down-counting between CMPR2 and
GP timer 1 at (1/2 T1 + 1/2 T2), switches the PWM outputs back to the sec-
ond output pattern

On the second compare match during down-counting between CMPR1
and GP timer 1 at (1/2 T1), switches the PWM outputs back to the first pat-
tern

Event Manager (EV) 6-65

Space Vector PWM

Space Vector PWM Waveforms

The space vector PWM waveforms generated are symmetric with respect to
the middle of each PWM period; and for this reason, it is called the symmetric
space vector PWM generation method. Figure 6−29 shows examples of the
symmetric space vector PWM waveforms.

The Unused Compare Register

Only two compare registers are used in space vector PWM output generation.
The third compare register, however, is still constantly compared with GP
timer 1. When a compare match happens, the corresponding compare
interrupt flag remains set and a peripheral interrupt request is generated, if the
flag is unmasked. Therefore, the compare register that is not used in space
vector PWM output generation can still be used to time events happening in
a specific application. Also, because of the extra delay introduced by the state
machine, the compare output transitions are delayed by one clock cycle in
space vector PWM mode.

6.7.3 Space Vector PWM Boundary Conditions

All three compare outputs become inactive when both compare registers
(CMPR1 and CMPR2) are loaded with a zero value in space vector PWM
mode. It is the user’s responsibility to assure that (CMPR1) ≤ (CMPR2) ≤
(T1PR) in the space vector PWM mode; otherwise, unpredictable behavior
may result.

6-66
 Space Vector PWM

Figure 6−29. Symmetric Space Vector PWM Waveforms

Full compare
match 2
Timer value
Full compare
match 1

DTPH1

DTPH2

DTPH3

U0 U60 U60 U0
(001) (011) (111) (111) (011) (001)

SVRDIR=0, (D2 D1 D0)=(001)

Full compare
match 2
Timer value
Full compare
match 1

DTPH1

DTPH2

DTPH3

U300 U240 U240 U300

(101) (100) (000) (000) (100) (101)

SVRDIR=1, (D2 D1 D0)=(101)

Event Manager (EV) 6-67

Capture Units

6.8 Capture Units

Capture units enable logging of transitions on capture input pins. There are six
capture units, three is each EV module. Capture Units 1, 2, and 3 are
associated with EVA and Capture Units 4, 5, and 6 are associated with EVB.
Each capture unit is associated with a capture input pin.

Each EVA capture unit can choose GP timer 2 or 1 as its time base; however,
CAP1 and CAP2 cannot choose a different timer between themselves as their
timebase. Each EVB capture unit can choose GP timer 4 or 3 as its time base;
however, CAP4 and CAP5 cannot choose a different timer between
themselves as their timebase.

The value of the GP timer is captured and stored in the corresponding

2-level-deep FIFO stack when a specified transition is detected on a capture
input pin (CAPx). Figure 6−30 shows a block diagram of an EVA capture unit
and Figure 6−31 shows a block diagram of an EVB capture unit.

6-68
 Capture Units

Figure 6−30. Capture Units Block Diagram (EVA)

T2CNT T1CNT
GP timer 2 GP timer 1
counter counter

2 CAPCONA[12−14]
CAPCONA[9,10] MUX

16
EN 3
CAP1,2,3
Edge
detect Capture unit 3
16 RS cap. event

Edge CAPCONA[8]
2-level 6 select
FIFO RS
stacks CAPCONA[2−7]
ADC start

8 CAPCONA[15]

Cap FIFO
status
clear

CAPFIFOA[13−15]

Event Manager (EV) 6-69

Capture Units

Figure 6−31. Capture Units Block Diagram (EVB)

T4CNT T3CNT
GP timer 4 GP timer 3
counter counter

2 CAPCONB[12−14]
CAPCONB[9,10] MUX

16
EN 3
CAP4,5,6
Edge
detect Capture unit 6
16 RS cap. event

Edge CAPCONB[8]
2-level 6 select
FIFO RS
stacks CAPCONB[2−7]
ADC start

8 CAPCONB[15]

Cap FIFO
status
clear

CAPFIFOB[13−15]

6.8.1 Capture Unit Features

Capture units have the following features:

One 16-bit capture control register (CAPCONA for EVA, CAPCONB for
EVB), (RW)

One 16-bit capture FIFO status register (CAPFIFOA for EVA, CAPFIFOB
for EVB)

Selection of GP timer 1 or 2 (for EVA) and GP timer 3 or 4 (for EVB) as the

time base

6-70
 Capture Units

Three 16-bit 2-level-deep FIFO stacks, one for each capture unit

Six Schmitt-triggered capture input pins, CAP1 through CAP6, one input
pin for each capture unit. (All inputs are synchronized with the device/CPU
clock: in order for a transition to be captured, the input must hold at its
current level to meet the two rising edges of the device clock. In 240xA
devices, the input must be held for a duration mandated by the input
qualifier circuitry. Input pins CAP1 and CAP2 (CAP4 and CAP5 in EVB)
can also be used as QEP inputs to QEP circuit).

User-specified transition detection (rising edge, falling edge, or both

edges)

Six maskable interrupt flags, one for each capture unit

6.8.2 Operation of Capture Units

After a capture unit is enabled, a specified transition on the associated input
pin causes the counter value of the selected GP timer to be loaded into the
corresponding FIFO stack. At the same time, if there are already one or more
valid capture values stored in the FIFO stack (CAPxFIFO bits not equal to
zero), the corresponding interrupt flag is set. If the flag is unmasked, a
peripheral interrupt request is generated. The corresponding status bits in
CAPFIFOx are adjusted to reflect the new status of the FIFO stack each time
a new counter value is captured in a FIFO stack. The latency from the time a
transition happens in a capture input to the time the counter value of the
selected GP timer is locked is two clock cycles. In 240xA devices, additional
latency due to the input qualifier circuitry must be taken into account.

All capture unit registers are cleared to zero by a RESET condition.

Capture Unit Time Base Selection

For EVA, Capture Unit 3 has a separate time base selection bit from Capture
Units 1 and 2. This allows the two GP timers to be used at the same time, one
for Capture Units 1 and 2, and the other for Capture Unit 3. For EVB, Capture
Unit 6 has a separate time base selection bit.

Capture operation does not affect the operation of any GP timer or the
compare/PWM operations associated with any GP timer.

Event Manager (EV) 6-71

Capture Units

Capture Unit Setup

For a capture unit to function properly, the following register setup must be
performed:
1) Initialize the CAPFIFOx and clear the appropriate status bits.
2) Set the selected GP timer in one of its operating modes.
3) Set the associated GP timer compare register or GP timer period register,
if necessary.
4) Set up CAPCONA or CAPCONB as appropriate.

6.8.3 Capture Unit Registers

The operation of the capture units is controlled by four 16-bit control registers,
CAPCONA/B and CAPFIFOA/B. TxCON (x = 1, 2, 3, or 4) registers are also
used to control the operation of the capture units since the time base for
capture circuits can be provided by any of these timers. Table 6−7 and
Table 6−8 on page 6-12 show the addresses of these registers.

Capture Control Register A (CAPCONA)

Figure 6−32. Capture Control Register A (CAPCONA) — Address 7420h
15 14−13 12 11 10 9 8

CAPRES CAP12EN CAP3EN Reserved CAP3TSEL CAP12TSEL CAP3TOADC

W-0 RW-0 RW-0 R-0 RW-0 RW-0 RW-0

7−6 5−4 3−2 1−0

CAP1EDGE CAP2EDGE CAP3EDGE Reserved

RW-0 RW-0 RW-0 R-0

Note: R = Read access, W = Write access, -0 = value after reset

Bit 15 CAPRES. Capture reset. Always reads zero.

Writing 0 clears the capture registers.
0 Clear all registers of capture units to 0
1 No action
Bits 14−13 CAP12EN. Capture Units 1 and 2 control
00 Disables Capture Units 1 and 2; FIFO stacks retain their contents
01 Enables Capture Units 1 and 2
10 Reserved
11 Reserved

6-72
 Capture Units

Bit 12 CAP3EN. Capture Unit 3 control

0 Disables Capture Unit 3; FIFO stack of Capture Unit 3 retains its
contents
1 Enable Capture Unit 3

Bit 11 Reserved. Reads return zero; writes have no effect.

Bit 10 CAP3TSEL. GP timer selection for Capture Unit 3

0 Selects GP timer 2
1 Selects GP timer 1

Bit 9 CAP12TSEL. GP timer selection for Capture Units 1 and 2

0 Selects GP timer 2
1 Selects GP timer 1

Bit 8 CAP3TOADC. Capture Unit 3 event starts ADC

0 No action
1 Starts ADC when the CAP3INT flag is set

Bits 7−6 CAP1EDGE. Edge detection control for Capture Unit 1

00 No detection
01 Detects rising edge
10 Detects falling edge
11 Detects both edges

Bits 5−4 CAP2EDGE. Edge detection control for Capture Unit 2

00 No detection
01 Detects rising edge
10 Detects falling edge
11 Detects both edges

Event Manager (EV) 6-73

Capture Units

Bits 3−2 CAP3EDGE. Edge detection control for Capture Unit 3

00 No detection
01 Detects rising edge
10 Detects falling edge
11 Detects both edges
Bits 1−0 Reserved. Reads return zero; writes have no effect.

Capture Control Register B (CAPCONB)

Figure 6−33. Capture Control Register B (CAPCONB) — Address 7520h

15 14−13 12 11 10 9 8

CAPRES CAP45EN CAP6EN Reserved CAP6TSEL CAP45TSEL CAP6TOADC

W-0 RW-0 RW-0 R-0 RW-0 RW-0 RW-0

7−6 5−4 3−2 1−0

CAP4EDGE CAP5EDGE CAP6EDGE Reserved

RW-0 RW-0 RW-0 R-0

Note: R = Read access, W = Write access, -0 = value after reset

Bit 15 CAPRES. Capture reset. Always reads zero.

Writing 0 clears the capture registers.
0 Clears all registers of capture units to 0
1 No action
Bits 14−13 CAP45EN. Capture Units 4 and 5 control.
00 Disables Capture Units 4 and 5. FIFO stacks retain their contents.
01 Enables Capture Units 4 and 5
10 Reserved
11 Reserved
Bit 12 CAP6EN. Capture Unit 6 control.
0 Disables Capture Unit 6; FIFO stack of Capture Unit 6 retains its
contents
1 Enables Capture Unit 6
Bit 11 Reserved. Reads return zero; writes have no effect.
Bit 10 CAP6TSEL. GP timer selection for Capture Unit 6.
0 Selects GP timer 4
1 Selects GP timer 3

6-74
 Capture Units

Bit 9 CAP45TSEL. GP timer selection for Capture Units 4 and 5.

0 Selects GP timer 4
1 Selects GP timer 3

Bit 8 CAP6TOADC. Capture Unit 6 event starts ADC.

0 No action
1 Starts ADC when the CAP6INT flag is set

Bits 7−6 CAP4EDGE. Edge detection control for Capture Unit 4.

00 No detection
01 Detects rising edge
10 Detects falling edge
11 Detects both edges

Bits 5−4 CAP5EDGE. Edge detection control for Capture Unit 5.

00 No detection
01 Detects rising edge
10 Detects falling edge
11 Detects both edges

Bits 3−2 CAP6EDGE. Edge detection control for Capture Unit 6.

00 No detection
01 Detects rising edge
10 Detects falling edge
11 Detects both edges

Bits 1−0 Reserved. Reads return zero; writes have no effect.

Capture FIFO Status Register A (CAPFIFOA)

CAPFIFOA contains the status bits for each of the three FIFO stacks of the
capture units. The bit description of CAPFIFOA is given in Figure 6−34. If a
write occurs to the CAPnFIFOA status bits at the same time as they are being
updated (because of a capture event), the write data takes precedence.

Event Manager (EV) 6-75

Capture Units

The write operation to the CAPFIFOx registers can be used as a programming

advantage. For example, if a “01” is written into the CAPnFIFO bits, the EV
module is led to “believe” that there is already an entry in the FIFO.
Subsequently, every time the FIFO gets a new value, a capture interrupt will
be generated.

Figure 6−34. Capture FIFO Status Register A (CAPFIFOA) — Address 7422h

15−14 13−12 11−10 9−8

Reserved CAP3FIFO CAP2FIFO CAP1FIFO

R-0 RW-0 RW-0 RW-0

7−0

Reserved

R-0

Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−14 Reserved. Reads return zero; writes have no effect.

Bits 13−12 CAP3FIFO. CAP3FIFO Status.

00 Empty
01 Has one entry
10 Has two entries
11 Had two entries and captured another one; first entry has been lost

Bits 11−10 CAP2FIFO. CAP2FIFO Status

00 Empty
01 Has one entry
10 Has two entries
11 Had two entries and captured another one; first entry has been lost

Bits 9−8 CAP1FIFO. CAP1FIFO Status.

00 Empty
01 Has one entry
10 Has two entries
11 Had two entries and captured another one; first entry has been lost

Bits 7−0 Reserved. Reads return zero; writes have no effect.

6-76
 Capture Units

Capture FIFO Status Register B (CAPFIFOB)

CAPFIFOB contains the status bits for each of the three FIFO stacks of the
capture units. The bit description of CAPFIFOB is given in Figure 6−35. If a
write occurs to the CAPnFIFOB status bits at the same time as they are being
updated (because of a capture event), the write data takes precedence.

The write operation to the CAPFIFOx registers can be used as a programming

advantage. For example, if a “01” is written into the CAPnFIFO bits, the EV
module is led to “believe” that there is already an entry in the FIFO.
Subsequently, every time the FIFO gets a new value, a capture interrupt will
be generated.

Figure 6−35. Capture FIFO Status Register B (CAPFIFOB) — Address 7522h

15−14 13−12 11−10 9−8

Reserved CAP6FIFO CAP5FIFO CAP4FIFO

R-0 RW-0 RW-0 RW-0

7−0

Reserved

R-0

Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−14 Reserved. Reads return zero; writes have no effect.

Bits 13−12 CAP6FIFO. CAP6FIFO Status.

00 Empty
01 Has one entry
10 Has two entries
11 Had two entries and captured another one; first entry has been lost

Bits 11−10 CAP5FIFO. CAP5FIFO Status

00 Empty
01 Has one entry
10 Has two entries
11 Had two entries and captured another one; first entry has been lost

Event Manager (EV) 6-77

Capture Units

Bits 9−8 CAP4FIFO. CAP4FIFO Status.

00 Empty
01 Has one entry
10 Has two entries
11 Had two entries and captured another one; first entry has been lost
Bits 7−0 Reserved. Reads return zero; writes have no effect.

6.8.4 Capture Unit FIFO Stacks

Each capture unit has a dedicated 2-level-deep FIFO stack. The top stack
consists of CAP1FIFO, CAP2FIFO, and CAP3FIFO (in the case of EVA) or
CAP4FIFO, CAP5FIFO, and CAP6FIFO (in the case of EVB). The bottom
stack consists of CAP1FBOT, CAP2FBOT, and CAP3FBOT (in the case of
EVA) or CAP4FBOT, CAP5FBOT, and CAP6FBOT (in the case of EVB). The
top-level register of any of the FIFO stacks is a read-only register that always
contains the oldest counter value captured by the corresponding capture unit.
Therefore, a read access to the FIFO stack of a capture unit always returns
the oldest counter value stored in the stack. When the oldest counter value in
the top register of the FIFO stack is read, the newer counter value in the bottom
register of the stack, if any, is pushed into the top register.

If desired, the bottom register of the FIFO stack can be read. Reading the
bottom register of the FIFO stack causes the FIFO status bits to change to 01
(has one entry) if they were previously 10 or 11. If the FIFO status bits were
previously 01 when the bottom FIFO register is read, they will change to 00
(empty).

First Capture
The counter value of the selected GP timer (captured by a capture unit when
a specified transition happens on its input pin) is written into the top register
of the FIFO stack, if the stack is empty. At the same time, the corresponding
status bits are set to 01. The status bits are reset to 00 if a read access is made
to the FIFO stack before another capture is made.

Second Capture
If another capture occurs before the previously captured counter value is read,
the newly captured counter value goes to the bottom register. In the meantime,
the corresponding status bits are set to 10. When the FIFO stack is read before
another capture happens, the older counter value in the top register is read
out, the newer counter value in the bottom register is pushed up into the top
register, and the corresponding status bits are set to 01.

6-78
 Capture Units

The appropriate capture interrupt flag is set by the second capture. A

peripheral interrupt request is generated if the interrupt is not masked.

Third Capture

If a capture happens when there are already two counter values captured in
the FIFO stack, the oldest counter value in the top register of the stack is
pushed out and lost, the counter value in the bottom register of the stack is
pushed up into the top register, the newly captured counter value is written into
the bottom register, and the status bits are set to 11 to indicate that one or more
older captured counter values have been lost.

The appropriate capture interrupt flag is also set by the third capture. A
peripheral interrupt request is generated if the interrupt is not masked.

6.8.5 Capture Interrupt

When a capture is made by a capture unit and there is already at least one valid
value in the FIFO (indicated by CAPxFIFO bits not equal to zero), the
corresponding interrupt flag is set, and if unmasked, a peripheral interrupt
request is generated. Thus, a pair of captured counter values can be read by
an interrupt service routine if the interrupt is used. If an interrupt is not desired,
either the interrupt flag or the status bits can be polled to determine if two
captures have occurred allowing the captured counter values to be read.

The write operation to the CAPFIFOx registers can be used as a programming

advantage. For example, if a “01” is written into the CAPnFIFO bits, the EV
module is led to “believe” that there is already an entry in the FIFO.
Subsequently, every time the FIFO gets a new value, a capture interrupt will
be generated.

Event Manager (EV) 6-79

Quadrature Encoder Pulse (QEP) Circuit

6.9 Quadrature Encoder Pulse (QEP) Circuit

Each Event Manager module has a quadrature encoder pulse (QEP) circuit.
The QEP circuit decodes and counts the quadrature encoded input pulses on
pins CAP1/QEP1 and CAP2/QEP2 (in case of EVA) or CAP4/QEP3 and
CAP5/QEP4 (in case of EVB). The QEP circuit can be used to interface with
an optical encoder to get position and speed information from a rotating
machine.

6.9.1 QEP Pins

The two QEP input pins are shared between capture units 1 and 2 (or 3 and 4,
for EVB), and the QEP circuit.

6.9.2 QEP Circuit Time Base

The time base for the QEP circuit is provided by GP timer 2 (GP timer 4, in case
of EVB). The GP timer must be put in directional-up/down count mode with the
QEP circuit as the clock source. Figure 6−36 shows the block diagram of the
QEP circuit for EVA and Figure 6−37 shows the block diagram of the QEP
circuit for EVB.

Figure 6−36. Quadrature Encoder Pulse (QEP) Circuit Block Diagram for EVA

GPT2 clock M CLKIN

GP timer 2 U Prescaler CLKOUT
X

2 T2CON[8,9,10]
T2CON[4,5]

2
CLK
TDIRA QEP
GPT2 dir M
DIR 2
U decoder
X
logic

Capture 2 CAP1/QEP1
unit 1,2 CAP2/QEP2

CAPCONA[13,14]

6-80
 Quadrature Encoder Pulse (QEP) Circuit

Figure 6−37. Quadrature Encoder Pulse (QEP) Circuit Block Diagram for EVB
GPT4 clock M CLKIN
GP timer 4 U Prescaler CLKOUT
X

2 T4CON[8,9,10]
T4CON[4,5]

2
CLK
TDIRB QEP
GPT4 dir M
DIR 2
U decoder
X
logic

Capture 2 CAP4/QEP3
unit 4,5 CAP5/QEP4

CAPCONB[13,14]

6.9.3 Decoding
Quadrature encoded pulses are two sequences of pulses with a variable
frequency and a fixed phase shift of a quarter of a period (90 degrees). When
generated by an optical encoder on a motor shaft, the direction of rotation of
the motor can be determined by detecting which of the two sequences is the
leading sequence. The angular position and speed can be determined by the
pulse count and pulse frequency.

QEP Circuit

The direction detection logic of the QEP circuit in the EV module determines
which one of the sequences is the leading sequence. It then generates a
direction signal as the direction input to GP timer 2 (or 4). The timer counts up
if CAP1/QEP1 (CAP4/QEP3 for EVB) input is the leading sequence, and
counts down if CAP2/QEP2 (CAP5/QEP4 for EVB) is the leading sequence.

Both edges of the pulses of the two quadrature encoded inputs are counted
by the QEP circuit. Therefore, the frequency of the clock generated by the QEP
logic to GP timer 2 (or 4) is four times that of each input sequence. This
quadrature clock is connected to the clock input of GP timer 2 (or 4).

Event Manager (EV) 6-81

Quadrature Encoder Pulse (QEP) Circuit

Quadrature Encoded Pulse Decoding Example

Figure 6−38 shows an example of quadrature encoded pulses and the derived
clock and counting direction.

Figure 6−38. Quadrature Encoded Pulses and Decoded Timer Clock and Direction

QEP1

QEP2

Quadrature CLK

DIR

6.9.4 QEP Counting

GP timer 2 (or 4) always starts counting from its current value. A desired value
can be loaded to the GP timer’s counter prior to enabling the QEP mode. When
the QEP circuit is selected as the clock source, the timer ignores the TDIRA/B
and TCLKINA/B input pins.

GP Timer Interrupt and Associated Compare Outputs in QEP Operation

Period, underflow, overflow, and compare interrupt flags for a GP timer with
a QEP circuit clock are generated on respective matches. A peripheral
interrupt request can be generated by an interrupt flag, if the interrupt is
unmasked.

6.9.5 Register Setup for the QEP Circuit

To start the operation of the QEP circuit in EVA:

1) Load GP timer 2’s counter, period, and compare registers with desired
values.

2) Configure T2CON to set GP timer 2 in directional-up/down mode with the

QEP circuits as clock source, and enable the selected timer.

6-82
 Quadrature Encoder Pulse (QEP) Circuit

To start the operation of the QEP circuit in EVB:

1) Load GP timer 4s counter, period, and compare registers with desired val-
ues, if necessary.

2) Configure T4CON to set GP timer 4 in directional-up/down mode with the

QEP circuits as clock source, and enable the selected timer.

Event Manager (EV) 6-83

Event Manager (EV) Interrupts

6.10 Event Manager (EV) Interrupts

EV interrupt events are organized into three groups: A, B, and C. Each group
is associated with a different interrupt flag and interrupt enable register. There
are several event manager peripheral interrupt requests in each EV interrupt
group. Table 6−16 shows all EVA interrupts, their priority, and grouping; and
Table 6−17 shows all EVB interrupts, their priority, and grouping. There is an
interrupt flag register and a corresponding interrupt mask register for each EV
interrupt group, as shown in Table 6−15. A flag in EVAIFRx (x = A, B, or C) is
masked (will not generate a peripheral interrupt request) if the corresponding
bit in EVAIMRx is zero.

Table 6−15. Interrupt Flag Register and Corresponding Interrupt Mask Register

Flag Register Mask Register EV Module

EVAIFRA EVAIMRA

EVAIFRB EVAIMRB EVA

EVAIFRC EVAIMRC

EVBIFRA EVBIMRA

EVBIFRB EVBIMRB EVB

EVBIFRC EVBIMRC

6.10.1 EV Interrupt Request and Service

When a peripheral interrupt request is acknowledged, the appropriate
peripheral interrupt vector is loaded into the peripheral interrupt vector register
(PIVR) by the PIE controller. The vector loaded into the PIVR is the vector for
the highest priority pending enabled event. The vector register can be read by
the interrupt service routine (ISR).

6-84
 Event Manager (EV) Interrupts

Table 6−16. Event Manager A (EVA) Interrupts

Priority Vector
Group Interrupt within group (ID) Description/Source INT
PDPINTA 1 (highest) 0020h Power Drive Protection Interrupt A 1
A CMP1INT 2 0021h Compare Unit 1 compare interrupt
CMP2INT 3 0022h Compare Unit 2 compare interrupt
CMP3INT 4 0023h Compare Unit 3 compare interrupt
T1PINT 5 0027h GP timer 1 period interrupt 2
T1CINT 6 0028h GP timer 1 compare interrupt
T1UFINT 7 0029h GP timer 1 underflow interrupt
T1OFINT 8 (lowest) 002Ah GP timer 1 overflow interrupt
B T2PINT 1 (highest) 002Bh GP timer 2 period interrupt
T2CINT 2 002Ch GP timer 2 compare interrupt
3
T2UFINT 3 002Dh GP timer 2 underflow interrupt
T2OFINT 4 002Eh GP timer 2 overflow interrupt
C CAP1INT 1 (highest) 0033h Capture Unit 1 interrupt
CAP2INT 2 0034h Capture Unit 2 interrupt 4
CAP3INT 3 0035h Capture Unit 3 interrupt

Event Manager (EV) 6-85

Event Manager (EV) Interrupts

Table 6−17. Event Manager B (EVB) Interrupts

Priority Vector
Group Interrupt within group (ID) Description/Source INT
PDPINTB 1 (highest) 0019h Power Drive Protection Interrupt B 1
A CMP4INT 2 0024h Compare Unit 4 compare interrupt
CMP5INT 3 0025h Compare Unit 5 compare interrupt
CMP6INT 4 0026h Compare Unit 6 compare interrupt
T3PINT 5 002Fh GP timer 3 period interrupt 2
T3CINT 6 0030h GP timer 3 compare interrupt
T3UFINT 7 0031h GP timer 3 underflow interrupt
T3OFINT 8 (lowest) 0032h GP timer 3 overflow interrupt
B T4PINT 1 (highest) 0039h GP timer 4 period interrupt
T4CINT 2 003Ah GP timer 4 compare interrupt
3
T4UFINT 3 003Bh GP timer 4 underflow interrupt
T4OFINT 4 003Ch GP timer 4 overflow interrupt
C CAP4INT 1 (highest) 0036h Capture Unit 4 interrupt
CAP5INT 2 0037h Capture Unit 5 interrupt 4
CAP6INT 3 0038h Capture Unit 6 interrupt

Table 6−18. Conditions for Interrupt Generation

Interrupt Condition For Generation

Underflow When the counter reaches 0000h

Overflow When the counter reaches FFFFh

Compare When the counter register contents match that of the

compare register

Period When the counter register contents match that of the period
register

Interrupt Generation

When an interrupt event occurs in the EV module, the corresponding interrupt

flag in one of the EV interrupt flag registers is set to one. A peripheral interrupt
request is generated to the Peripheral Interrupt Expansion controller, if the flag
is locally unmasked (the corresponding bit in EVAIMRx is set to one).

6-86
 Event Manager (EV) Interrupts

Interrupt Vector
The peripheral interrupt vector corresponding to the interrupt flag that has the
highest priority among the flags that are set and enabled is loaded into the
PIVR when an interrupt request is acknowledged (this is all done in the
peripheral interrupt controller, external to the event manager peripheral).

Note: Failure to Clear the Interrupt Flag Bit

The interrupt flag bit in the peripheral register must be cleared by software
writing a 1 to the bit in the ISR. Failure to clear this bit will prevent future inter-
rupt requests by that source.

6.10.2 EV Interrupt Flag Registers

Addresses of the EVA and EVB interrupt registers are shown in Table 6−9 and
Table 6−10, respectively, on page 6-13. The registers are all treated as 16-bit
memory mapped registers. The unused bits all return zero when read by
software. Writing to unused bits has no effect. Since
EVxIFRx are readable registers, occurrence of an interrupt event can be
monitored by software polling the appropriate bit in EVxIFRx when the
interrupt is masked.

EVA Interrupt Flag Register A (EVAIFRA)

Figure 6−39. EVA Interrupt Flag Register A (EVAIFRA) — Address 742Fh

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
15−11 10 9 8

Reserved
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
T1OFINT

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
FLAG
T1UFINT
FLAG
T1CINT
FLAG

R-0 RW1C-0 RW1C-0 RW1C-0

ÍÍÍÍ 7 6−4
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
3 2 1 0

ÍÍÍÍ
T1PINT

ÍÍÍÍFLAG
Reserved ÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
FLAG ÍÍÍÍÍÍÍÍÍÍ
CMP3INT
ÍÍÍÍÍ
CMP2INT
FLAG
CMP1INT
FLAG
PDPINTA
FLAG

RW1C-0 R-0 RW1C-0 RW1C-0 RW1C-0 RW1C-0

Note: R = Read access, W1C = Write 1 to clear, -0 = value after reset

Bits 15−11 Reserved. Reads return zero; writes have no effect.

Bit 10 T1OFINT FLAG. GP timer 1 overflow interrupt.
Read: 0 Flag is reset
1 Flag is set

Event Manager (EV) 6-87

Event Manager (EV) Interrupts

Write: 0 No effect
1 Resets flag

Bit 9 T1UFINT FLAG. GP timer 1 underflow interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bit 8 T1CINT FLAG. GP timer 1 compare interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bit 7 T1PINT FLAG. GP timer 1 period interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bits 6−4 Reserved. Reads return zero; writes have no effect.

Bit 3 CMP3INT FLAG. Compare 3 interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bit 2 CMP2INT FLAG. Compare 2 interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

6-88
 Event Manager (EV) Interrupts

Bit 1 CMP1INT FLAG. Compare 1 interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag
Bit 0 PDPINTA FLAG. Power drive protection interrupt.
Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

EVA Interrupt Flag Register B (EVAIFRB)

Figure 6−40. EVA Interrupt Flag Register B (EVAIFRB) — Address 7430h

15−4
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
3 2 1 0

Reserved ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
T2OFINT
FLAG
ÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
T2UFINT
FLAG
T2CINT
FLAG
T2PINT
FLAG

R-0 RW1C-0 RW1C-0 RW1C-0 RW1C-0

Note: R = Read access, W1C = Write 1 to clear, -0 = value after reset

Bits 15−4 Reserved. Reads return zero; writes have no effect.

Bit 3 T2OFINT FLAG. GP timer 2 overflow interrupt.
Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag
Bit 2 T2UFINT FLAG. GP timer 2 underflow interrupt.
Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag
Bit 1 T2CINT FLAG. GP timer 2 compare interrupt.
Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Event Manager (EV) 6-89

Event Manager (EV) Interrupts

Bit 0 T2PINT FLAG. GP timer 2 period interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

EVA Interrupt Flag Register C (EVAIFRC)

Figure 6−41. EVA Interrupt Flag Register C (EVAIFRC) — Address 7431h

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
15−3 2 1 0

Reserved

R-0
ÍÍÍÍÍÍÍÍÍÍ
CAP3INT
ÍÍÍÍ
CAP2INT

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
FLAG

RW1C-0
FLAG

RW1C-0
CAP1INT
FLAG

RW1C-0

Note: R = Read access, W1C = Write 1 to clear, -0 = value after reset

Bits 15−3 Reserved. Reads return zero; writes have no effect.

Bit 2 CAP3INT FLAG. Capture 3 interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bit 1 CAP2INT FLAG. Capture 2 interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bit 0 CAP1INT FLAG. Capture 1 interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

6-90
 Event Manager (EV) Interrupts

EVA Interrupt Mask Register A (EVAIMRA)

Figure 6−42. EVA Interrupt Mask Register A (EVAIMRA) — Address 742Ch

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
15−11 10 9 8

Reserved

R-0
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
T1OFINT
ENABLE

RW-0
T1UFINT
ENABLE

RW-0
T1CINT
ENABLE

RW-0

ÍÍÍÍ 7 6−4
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
3 2 1 0

ÍÍÍÍ
T1PINT

ÍÍÍÍ
ENABLE
Reserved ÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍ
CMP3INT
ENABLE ÍÍÍÍÍ CMP2INT
ENABLE
CMP1INT
ENABLE
PDPINTA
ENABLE

RW-0 R-0 RW-0 RW-0 RW-0 RW-1

Note: R = Read access, W = write access, value following dash (−) = value after reset

Bits 15−11 Reserved. Reads return zero; writes have no effect.

Bit 10 T1OFINT ENABLE

0 Disable
1 Enable

Bit 9 T1UFINT ENABLE

0 Disable
1 Enable

Bit 8 T1CINT ENABLE

0 Disable
1 Enable

Bit 7 T1PINT ENABLE

0 Disable
1 Enable

Bits 6−4 Reserved. Reads return zero; writes have no effect.

Bit 3 CMP3INT ENABLE

0 Disable
1 Enable

Bit 2 CMP2INT ENABLE

0 Disable
1 Enable

Event Manager (EV) 6-91

Event Manager (EV) Interrupts

Bit 1 CMP1INT ENABLE

0 Disable
1 Enable

Bit 0 PDPINTA ENABLE. This is enabled (set to 1) following reset.

0 Disable
1 Enable

EVA Interrupt Mask Register B (EVAIMRB)

Figure 6−43. EVA Interrupt Mask Register B (EVAIMRB) — Address 742Dh

15−4
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
3 2 1 0

Reserved ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
T2OFINT
ÍÍÍÍ
T2UFINT

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ENABLE ENABLE
T2CINT
ENABLE
T2PINT
ENABLE

R-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−4 Reserved. Reads return zero; writes have no effect.

Bit 3 T2OFINT ENABLE

0 Disable
1 Enable

Bit 2 T2UFINT ENABLE

0 Disable
1 Enable

Bit 1 T2CINT ENABLE

0 Disable
1 Enable

Bit 0 T2PINT ENABLE

0 Disable
1 Enable

6-92
 Event Manager (EV) Interrupts

EVA Interrupt Mask Register C (EVAIMRC)

Figure 6−44. EVA Interrupt Mask Register C (EVAIMRC) — Address 742Eh

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
15−3 2 1 0

Reserved
ÍÍÍÍÍÍÍÍÍ
CAP3INT
ÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ENABLE
CAP2INT
ENABLE
CAP1INT
ENABLE

R-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−3 Reserved. Reads return zero; writes have no effect.

Bit 2 CAP3INT ENABLE

0 Disable
1 Enable

Bit 1 CAP2INT ENABLE

0 Disable
1 Enable

Bit 0 CAP1INT ENABLE

0 Disable
1 Enable

Event Manager (EV) 6-93

Event Manager (EV) Interrupts

EVB Interrupt Flag Register A (EVBIFRA)

Figure 6−45. EVB Interrupt Flag Register A (EVBIFRA) — Address 752Fh

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
15−11 10 9 8

Reserved
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
T3OFINT

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
FLAG
T3UFINT
FLAG
T3CINT
FLAG

R-0 RW1C-0 RW1C-0 RW1C-0

ÍÍÍÍÍ 7 6−4
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
3 2 1 0

ÍÍÍÍÍ
T3PINT

ÍÍÍÍÍ
FLAG
Reserved ÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
FLAG ÍÍÍÍÍÍÍÍÍ
CMP6INT
ÍÍÍÍ
CMP5INT
FLAG
CMP4INT
FLAG
PDPINTB
FLAG

RW1C-0 R-0 RW1C-0 RW1C-0 RW1C-0 RW1C-0

Note: R = Read access, W1C = Write 1 to clear, -0 = value after reset

Bits 15−11 Reserved. Reads return zero; writes have no effect.

Bit 10 T3OFINT FLAG. GP timer 3 overflow interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bit 9 T3UFINT FLAG. GP timer 3 underflow interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bit 8 T3CINT FLAG. GP timer 3 compare interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

6-94
 Event Manager (EV) Interrupts

Bit 7 T3PINT FLAG. GP timer 3 period interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bits 6−4 Reserved. Reads return zero; writes have no effect.

Bit 3 CMP6INT FLAG. Compare 6 interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bit 2 CMP5INT FLAG. Compare 5 interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bit 1 CMP4INT FLAG. Compare 4 interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bit 0 PDPINTB FLAG. Power drive protection interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Event Manager (EV) 6-95

Event Manager (EV) Interrupts

EVB Interrupt Flag Register B (EVBIFRB)

Figure 6−46. EVB Interrupt Flag Register B (EVBIFRB) — Address 7530h

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
15−4 3 2 1 0

Reserved
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
T4OFINT
ÍÍÍÍ
T4UFINT

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
FLAG FLAG
T4CINT
FLAG
T4PINT
FLAG

R-0 RW1C-0 RW1C-0 RW1C-0 RW1C-0

Note: R = Read access, W1C = Write 1 to clear, -0 = value after reset

Bits 15−4 Reserved. Reads return zero; writes have no effect.

Bit 3 T4OFINT FLAG. GP timer 4 overflow interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bit 2 T4UFINT FLAG. GP timer 4 underflow interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bit 1 T4CINT FLAG. GP timer 4 compare interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bit 0 T4PINT FLAG. GP timer 4 period interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

6-96
 Event Manager (EV) Interrupts

EVB Interrupt Flag Register C (EVBIFRC)

Figure 6−47. EVB Interrupt Flag Register C (EVBIFRC) — Address 7531h

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
15−3 2 1 0

Reserved
ÍÍÍÍÍÍÍÍÍ
CAP6INT
ÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
FLAG
CAP5INT
FLAG
CAP4INT
FLAG

R-0 RW1C-0 RW1C-0 RW1C-0

Note: R = Read access, W1C = Write 1 to clear, -0 = value after reset

Bits 15−3 Reserved. Reads return zero; writes have no effect.

Bit 2 CAP6INT FLAG. Capture 6 interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bit 1 CAP5INT FLAG. Capture 5 interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Bit 0 CAP4INT FLAG. Capture 4 interrupt.

Read: 0 Flag is reset
1 Flag is set
Write: 0 No effect
1 Resets flag

Event Manager (EV) 6-97

Event Manager (EV) Interrupts

EVB Interrupt Mask Register A (EVBIMRA)

Figure 6−48. EVB Interrupt Mask Register A (EVBIMRA) — Address 752Ch

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
15−11 10 9 8

Reserved

R-0
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
T3OFINT

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ENABLE

RW-0
T3UFINT
ENABLE

RW-0
T3CINT
ENABLE

RW-0

ÍÍÍÍÍ 7 6−4
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
3 2 1 0

ÍÍÍÍÍ
T3PINT

ÍÍÍÍÍ
ENABLE
Reserved ÍÍÍÍÍÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ENABLEÍÍÍÍÍÍÍÍÍ
CMP6INT
ÍÍÍÍ
CMP5INT
ENABLE
CMP4INT
ENABLE
PDPINTB
ENABLE

RW-0 R-0 RW-0 RW-0 RW-0 RW-1

Note: R = Read access, W = Write access, -n = value after reset

Bits 15−11 Reserved. Reads return zero; writes have no effect.

Bit 10 T3OFINT ENABLE

0 Disable
1 Enable

Bit 9 T3UFINT ENABLE

0 Disable
1 Enable

Bit 8 T3CINT ENABLE

0 Disable
1 Enable

Bit 7 T3PINT ENABLE

0 Disable
1 Enable

Bits 6−4 Reserved. Reads return zero; writes have no effect.

Bit 3 CMP6INT ENABLE

0 Disable
1 Enable

Bit 2 CMP5INT ENABLE

0 Disable
1 Enable

6-98
 Event Manager (EV) Interrupts

Bit 1 CMP4INT ENABLE

0 Disable
1 Enable

Bit 0 PDPINTB ENABLE. This is enabled (set to 1) following reset.

0 Disable
1 Enable

EVB Interrupt Mask Register B (EVBIMRB)

Figure 6−49. EVB Interrupt Mask Register B (EVBIMRB) — Address 752Dh

15−4
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
3 2 1 0

Reserved ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
T4OFINT
ÍÍÍÍÍ
T4UFINT

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ENABLE ENABLE
T4CINT
ENABLE
T4PINT
ENABLE

R-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−4 Reserved. Reads return zero; writes have no effect.

Bit 3 T4OFINT ENABLE

0 Disable
1 Enable

Bit 2 T4UFINT ENABLE

0 Disable
1 Enable

Bit 1 T4CINT ENABLE

0 Disable
1 Enable

Bit 0 T4PINT ENABLE

0 Disable
1 Enable

Event Manager (EV) 6-99

Event Manager (EV) Interrupts

EVB Interrupt Mask Register C (EVBIMRC)

Figure 6−50. EVB Interrupt Mask Register C (EVBIMRC) — Address 752Eh

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
15−3 2 1 0

Reserved
ÍÍÍÍÍÍÍÍÍÍ
CAP6INT
ÍÍÍÍ
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
ENABLE
CAP5INT
ENABLE
CAP4INT
ENABLE

R-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−3 Reserved. Reads return zero; writes have no effect.

Bit 2 CAP6INT ENABLE

0 Disable
1 Enable

Bit 1 CAP5INT ENABLE

0 Disable
1 Enable

Bit 0 CAP4INT ENABLE

0 Disable
1 Enable

6-100
 Chapter 7

,# #%  *  (,% )

This chapter describes the analog-to-digital converter (ADC), includes a list of

features, explains the clock prescaler, and provides register descriptions.

Topic Page

7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.2 ADC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.3 ADC Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
7.4 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
7.5 Register Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
7.6 ADC Conversion Clock Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38

7-1
Features

7.1 Features

10-bit ADC core with built-in Sample and Hold (S/H)

Fast conversion time (S/H + Conversion): 500 ns

Sixteen (16) multiplexed analog inputs (ADCIN0 – ADCIN15). Eight in

2402A

Autosequencing capability – up to 16 “autoconversions” in a single ses-

sion. Each conversion session can be programmed to select any one of
the 16 input channels

Two independent 8-state sequencers (SEQ1 and SEQ2) that can be oper-
ated individually in dual-sequencer mode or cascaded into one large
16-state sequencer (SEQ) in cascaded mode

Four Sequencing Control Registers (CHSELSEQn) that determine the se-

quence of analog channels that are taken up for conversion in a given se-
quencing mode

Sixteen (individually addressable) result registers to store the converted

values (RESULT0 – RESULT15)

Multiple trigger sources for start-of-conversion (SOC) sequence

 Software: Software immediate start (using SOC SEQn bit)

 EVA: Event manager A (multiple event sources within EVA)
 EVB: Event manager B (multiple event sources within EVB)
 External: ADCSOC pin

Flexible interrupt control allows interrupt request on every end-of-se-

quence (EOS) or every other EOS

Sequencer can operate in start/stop mode, allowing multiple time-

sequenced triggers to synchronize conversions

EVA and EVB can independently trigger SEQ1 and SEQ2, respectively.
(This is applicable for dual-sequencer mode only.)

Sample-and-hold acquisition time window has separate prescale control

Calibration mode

The 240x/240xA ADC is not compatible with the 24x ADC. Therefore,
code written for the 24x ADC cannot be ported to a 240x/240xA device.

7-2
 Features

Table 7−1. Addresses of ADC Registers

Address Register Name

70A0h ADCTRL1 ADC control register 1
70A1h ADCTRL2 ADC control register 2
70A2h MAXCONV Maximum conversion channels register
70A3h CHSELSEQ1 Channel select sequencing control register 1
70A4h CHSELSEQ2 Channel select sequencing control register 2
70A5h CHSELSEQ3 Channel select sequencing control register 3
70A6h CHSELSEQ4 Channel select sequencing control register 4
70A7h AUTO_SEQ_SR Autosequence status register
70A8h RESULT0 Conversion result buffer register 0
70A9h RESULT1 Conversion result buffer register 1
70AAh RESULT2 Conversion result buffer register 2
70ABh RESULT3 Conversion result buffer register 3
70ACh RESULT4 Conversion result buffer register 4
70ADh RESULT5 Conversion result buffer register 5
70AEh RESULT6 Conversion result buffer register 6
70AFh RESULT7 Conversion result buffer register 7
70B0h RESULT8 Conversion result buffer register 8
70B1h RESULT9 Conversion result buffer register 9
70B2h RESULT10 Conversion result buffer register 10
70B3h RESULT11 Conversion result buffer register 11
70B4h RESULT12 Conversion result buffer register 12
70B5h RESULT13 Conversion result buffer register 13
70B6h RESULT14 Conversion result buffer register 14
70B7h RESULT15 Conversion result buffer register 15
70B8h CALIBRATION† Calibration result, used to correct subsequent conversions

† The calibration feature available in 240x devices has some restrictions in usage. See the following device errata for details:
TMS320LF2402 DSP Controller Silicon Errata (literature number SPRZ157), TMS320LF2406 DSP Controller Silicon Errata (lit-
erature number SPRZ159), and TMS320LF2407 DSP Controller Silicon Errata (literature number SPRZ158). Note that the cal-
ibration and self-test features are not supported on the 240xA devices. Hence, bits 0, 1, 2, and 3 of the ADCTRL1 register must
be treated as “reserved” in 240xA devices and must be written with zeroes. Furthermore, the functionality of bit 14 of ADCTRL2
is restricted to RST_SEQ1 only.

Analog-to-Digital Converter (ADC) 7-3

ADC Overview

7.2 ADC Overview

7.2.1 Autoconversion Sequencer: Principle of Operation

The ADC sequencer consists of two independent 8-state sequencers (SEQ1
and SEQ2) that can also be cascaded together to form one 16-state
sequencer (SEQ). The word “state” represents the number of autoconversions
that can be performed with the sequencer. Block diagrams of the single
(16-state, cascaded) and dual (two 8-state, separated) sequencer modes are
shown in Figure 7−1 and Figure 7−2, respectively.

In both cases, the ADC has the ability to autosequence a series of

conversions. For every conversion, any one of the available 16 input channels
can be selected through the analog mux. After conversion, the digital value of
the selected channel is stored in the appropriate result register (RESULTn).
(The first result is stored in RESULT0, the second result in RESULT1, and so
on). It is also possible to sample the same channel multiple times, allowing the
user to perform “over-sampling”, which gives increased resolution over
traditional single sampled conversion results.

Note: Dual-Sequencer Mode

In the dual-sequencer mode, the SOC request from the “inactive” sequencer
will be taken up as soon as the sequence initiated by the “active” sequencer
is completed. For example, assume that the A/D converter is busy catering
to SEQ2. When SEQ1 initiates an SOC, the A/D converter takes up the re-
quest from SEQ1 after completing the sequence initiated by SEQ2; i.e., the
SEQ1 conversion starts immediately after the current SEQ2 conversion fin-
ishes.

7-4
 ADC Overview

Figure 7−1. Block Diagram of Autosequenced ADC in Cascaded Mode

Analog MUX Result MUX

ADCIN0 RESULT0
ADCIN1 RESULT1
ADCIN2
10-bit 10 RESULT2
S/H + A/D
converter
10
ADCIN15 MUX Result RESULT15
SOC EOC
select select

MAX CONV1

State
Ch Sel (state 0) pointer
Ch Sel (state 1)
4 Ch Sel (state 2) 4

Ch Sel (state 3)

Autosequencer
Ch Sel (state 15) Note: Possible values are:
state machine
Channel select = 0 to 15
MAXCONV = 0 to 15
Software
EVA Start-of-sequence trigger
EVB
External pin (ADCSOC)

Analog-to-Digital Converter (ADC) 7-5

ADC Overview

Figure 7−2. Block Diagram of Autosequenced ADC With Dual Sequencers

Result MUX

RESULT0
RESULT1
10
Analog MUX
ADCIN0 10
ADCIN1 Result RESULT7
ADCIN2 select
10-bit 10
S/H + A/D MUX
converter Result MUX

MUX
ADCIN15 RESULT8
select SOC EOC
RESULT9
10
4
Sequencer
arbiter
10
Result RESULT15
4 4 select

SOC1 EOC1 SOC2 EOC2

MAX CONV1 MAX CONV2

State State
Ch Sel (state 0) pointer Ch Sel (state 8) pointer
Ch Sel (state 1) Ch Sel (state 9)
Ch Sel (state 2) Ch Sel (state 10) 4
Ch Sel (state 3) Ch Sel (state 11)

Note: Possible values:

Channel select = 0 to 15
SEQ1 SEQ2
MAX CONV1 = 0 to 7 Ch Sel (state 7) Ch Sel (state 15)
MAX CONV2 = 8 to 15

Start-of-sequence Start-of-sequence
Software trigger trigger
Software
EVA
EVB
External pin (ADCSOC)

Note:
There is only one A/D converter in the DSP. This converter is shared by the
two sequencers in Dual-Sequencer mode.

7-6
 ADC Overview

The sequencer operation for both 8-state and 16-state modes is almost
identical; the few differences are highlighted in Table 7−2.

Table 7−2. Comparison of Single and Cascaded Operating Modes

Single 8-state Single 8-state Cascaded 16-state

Feature sequencer #1 (SEQ1) sequencer #2 (SEQ2) sequencer (SEQ)
Start-of-conversion EVA, software, EVB, software EVA, EVB, software,
triggers external pin external pin

Maximum number of 8 8 16
autoconversions
(i.e., sequence length)
Autostop at end-of- Yes Yes Yes
sequence (EOS)
Arbitration priority High Low Not applicable
ADC conversion result 0 to 7 8 to 15 0 to 15
register locations

CHSELSEQn bit field CONV00 to CONV07 CONV08 to CONV15 CONV00 to CONV15

assignment

For convenience, the sequencer states will be subsequently referred to as:

For SEQ1: CONV00 to CONV07

For SEQ2: CONV08 to CONV15

For Cascaded SEQ: CONV00 to CONV15

The analog input channel selected for each sequenced conversion is defined
by CONVnn bit fields in the ADC input channel select sequencing control
registers (CHSELSEQn). (See section 7.5.5., ADC Input Channel Select
Sequencing Control Registers, on page 7-35.) CONVnn is a 4-bit field that
specifies any one of the 16 channels for conversion. Since a maximum of
16 conversions in a sequence is possible when using the sequencers in
cascaded mode, 16 such 4-bit fields (CONV00 – CONV15) are available and
are spread across four 16-bit registers (CHSELSEQ1 – CHSELSEQ4). The
CONVnn bits can have any value from 0 to 15. The analog channels can be
chosen in any desired order and the same channel may be selected multiple
times.

Analog-to-Digital Converter (ADC) 7-7

ADC Overview

7.2.2 Uninterrupted Autosequenced Mode

The following description applies to the 8-state sequencers (SEQ1 or SEQ2).

In this mode, SEQ1/SEQ2 can autosequence up to eight conversions of any
channel in a single sequencing session. The result of each conversion is
stored in one of the eight result registers (RESULT0 – RESULT7 for SEQ1 and
RESULT8 – RESULT15 for SEQ2). These registers are filled from the lowest
address to the highest address.

The number of conversions in a sequence is controlled by MAX CONVn (a

3-bit or 4-bit field in the MAXCONV register), which is automatically loaded into
the sequencing counter status bits (SEQ CNTR3 – 0) in the autosequence
status register (AUTO_SEQ_SR) at the start of an autosequenced conversion
session. The MAX CONVn field can have a value ranging from zero to seven.
SEQ CNTRn bits count down from their loaded value as the sequencer starts
from state CONV00 and continues sequentially (CONV01, CONV02, and so
on) until SEQ CNTRn has reached zero. The number of conversions
completed during an autosequencing session is equal to (MAX CONVn + 1).

Example 7−1. Conversion in Dual-Sequencer Mode Using SEQ1

Suppose seven conversions are desired from SEQ1 (i.e., Channels 2, 3, 2, 3,

6, 7, and 12 need to be converted as part of the autosequenced session), then
MAX CONV1 should be set to 6 and the CHSELSEQn registers should be set
to the values shown in the table below:

Bits 15−12 Bits 11−8 Bits 7−4 Bits 3−0

70A3h 3 2 3 2 CHSELSEQ1
70A4h x 12 7 6 CHSELSEQ2
70A5h x x x x CHSELSEQ3
70A6h x x x x CHSELSEQ4
Note: Values are in decimal, and x = don’t care

Conversion begins once the start-of-conversion (SOC) trigger is received by

the sequencer. The SOC trigger also loads the SEQ CNTR n bits. Those
channels that are specified in the CHSELSEQ n registers are taken up for
conversion, in the predetermined sequence. The SEQ CNTR n bits are
decremented by one automatically after every conversion. Once SEQ CNTR
n reaches zero, two things can happen depending on the status of the
continuous run bit
(CONT RUN) in the ADCTRL1 register.

7-8
 ADC Overview

If CONT RUN is set, the conversion sequence starts all over again auto-
matically (i.e., SEQ CNTR n gets reloaded with the original value in MAX
CONV1 and SEQ1 state is set to CONV00). In this case, you must ensure
that the result registers are read before the next conversion sequence be-
gins. The arbitration logic designed into the ADC ensures that the result
registers are not corrupted should a contention arise (ADC module trying
to write into the result registers while you try to read from them at the same
time).

Figure 7−3. Flow Chart for Uninterrupted Autosequenced Mode

Initialize the ADC registers

SOC trigger arrives

MAXCONV value gets loaded

into AUTO_SEQ_SR register

Conversion begins. AUTO_SEQ_SR

register is decremented by one for
every conversion

Current conversion complete.

Digital result is written into
corresponding RESULTn register

All
conversions
No complete?
(AUTO_SEQ_SR = 0 ?)

Yes

Set INT FLAG SEQn

Note: Flow chart corresponds

to CONT RUN bit = 0. Stop

Analog-to-Digital Converter (ADC) 7-9

ADC Overview

If CONT RUN is not set, the sequencer stays in the last state (CONV06,
in this example) and SEQ CNTR n continues to hold a value of zero.

Since the interrupt flag is set every time SEQ CNTR n reaches zero, you can
(if needed) manually reset the sequencer (using the RST SEQn bit in the
ADCTRL2 register) in the interrupt service routine (ISR), so that SEQ CNTR
n gets reloaded with the original value in MAX CONV1 at the next SOC and
SEQ1 state is set to CONV00. This feature is useful in the Start/Stop operation
of the sequencer. Example 7−1 also applies to SEQ2 and the cascaded
16-state sequencer (SEQ) with differences outlined in Table 7−2.

7.2.3 Sequencer Start/Stop Mode (Sequencer “Start/Stop” Operation With Multiple

“Time-Sequenced Triggers”)
In addition to the uninterrupted autosequenced mode, any sequencer (SEQ1,
SEQ2, or SEQ) can be operated in a stop/start mode which is synchronized
to multiple start-of-conversion (SOC) triggers, separated in time. This mode
is identical to Example 7−1, but the sequencer is allowed to be retriggered
without being reset to the initial state CONV00, once it has finished its first
sequence (i.e., the sequencer is not reset in the interrupt service routine).
Therefore, when one conversion sequence ends, the sequencer stays in the
current conversion state. The continuous run bit (CONT RUN) in the
ADCTRL1 register must be set to zero (i.e., disabled) for this mode.

Example 7−2. Sequencer Start/Stop Operation

Requirement: To start three autoconversions (e.g., I1,I2,I3) off trigger 1
(underflow) and three autoconversions (e.g., V1,V2,V3) off trigger 2 (period).
Triggers 1 and 2 are separated in time by, say, 25 µs and are provided by Event
Manager A (EVA). See Figure 7−4. Only SEQ1 is used in this case.

Note: Triggers 1 and 2 may be an SOC signal from EVA, external pin, or
software. The same trigger source may occur twice to satisfy the dual-trigger
requirement of this example.

7-10
 ADC Overview

Figure 7−4. Example of Event Manager Triggers to Start the Sequencer

50 µs
25 µs EV1 Timer 1
counter

EV1
PWM

I1,I2,I3 V1,V2,V3 I1,I2,I3 V1,V2,V3

Here MAX CONV1 is set to 2 and the ADC Input Channel Select Sequencing
Control Registers (CHSELSEQn) are set to:

Bits 15−12 Bits 11−8 Bits 7−4 Bits 3−0

70A3h V1 I3 I2 I1 CHSELSEQ1
70A4h x x V3 V2 CHSELSEQ2
70A5h x x x x CHSELSEQ3
70A6h x x x x CHSELSEQ4

Once reset and initialized, SEQ1 waits for a trigger. With the first trigger, three
conversions with channel-select values of: CONV00 (I1), CONV01 (I2), and
CONV02 (I3) are performed. SEQ1 then waits at current state for another
trigger. Twenty-five microseconds later when the second trigger arrives,
another three conversions occur, with channel-select values of CONV03 (V1),
CONV04 (V2), and CONV05 (V3).

The value of MAX CONV1 is automatically loaded into SEQ CNTR n for both
trigger cases. If a different number of conversions are required at the second
trigger point, you must (at some appropriate time before the second trigger)
change the value of MAX CONV1 through software, otherwise, the current
(originally loaded) value will be reused. This can be done by an ISR that
changes the value of MAX CONV1 at the appropriate time. The interrupt
operation modes are described in section 7.2.5, Interrupt Operation During
Sequenced Conversions, on page 7-13.

Analog-to-Digital Converter (ADC) 7-11

ADC Overview

At the end of the second autoconversion session, the ADC result registers will
have the following values:

Buffer Register ADC conversion result buffer

RESULT0 I1
RESULT1 I2
RESULT2 I3
RESULT3 V1
RESULT4 V2
RESULT5 V3
RESULT6 x
RESULT7 x
RESULT8 x
RESULT9 x
RESULT10 x
RESULT11 x
RESULT12 x
RESULT13 x
RESULT14 x
RESULT15 x

At this point, SEQ1 keeps “waiting” at the current state for another trigger. Now,
the user can reset SEQ1 (by software) to state CONV00 and repeat the same
trigger1,2 sessions.

7-12
 ADC Overview

7.2.4 Input Trigger Description

Each sequencer has a set of trigger inputs that can be enabled/disabled. The
valid input triggers for SEQ1, SEQ2, and cascaded SEQ is as follows:

SEQ1 (sequencer 1) SEQ2 (sequencer 2) Cascaded SEQ

Software trigger (software SOC) Software trigger (software SOC) Software trigger (software SOC)
Event manager A (EVA SOC) Event manager B (EVB SOC) Event manager A (EVA SOC)
External SOC pin (ADC SOC) Event manager B (EVB SOC)
External SOC pin (ADC SOC)

Note that:

An SOC trigger can initiate an autoconversion sequence whenever a se-

quencer is in an idle state. An idle state is either CONV00 prior to receiving
a trigger, or any state which the sequencer lands on at the completion of
a conversion sequence, i.e., when SEQ CNTR n has reached a count of
zero.

If an SOC trigger occurs while a current conversion sequence is under-

way, it sets the SOC SEQn bit (which would have been cleared on the com-
mencement of a previous conversion sequence) in the ADCTRL2 register.
If yet another SOC trigger occurs, it is lost (i.e., when the SOC SEQn bit
is already set (SOC pending), subsequent triggers will be ignored).

Once triggered, the sequencer cannot be stopped/halted in mid se-

quence. The program must either wait until an End-of-Sequence (EOS)
or initiate a sequencer reset, which brings the sequencer immediately
back to the idle start state (CONV00 for SEQ1 and cascaded cases;
CONV08 for SEQ2).

When SEQ1/2 are used in cascaded mode, triggers going to SEQ2 are ig-
nored, while SEQ1 triggers are active. Cascaded mode can be viewed as
SEQ1 with 16 states instead of eight.

7.2.5 Interrupt Operation During Sequenced Conversions

The sequencer can generate interrupts under two operating modes. These
modes are determined by the Interrupt-Mode-Enable Control bits in
ADCTRL2.

A variation of Example 7−2 can be used to show how interrupt mode 1 and
mode 2 are useful under different operating conditions.

Analog-to-Digital Converter (ADC) 7-13

ADC Overview

Case 1: Number of samples in the first and second sequences are not equal

Mode 1 Interrupt operation (i.e., Interrupt request occurs at every EOS)

1) Sequencer is initialized with MAX CONVn = 1 for converting I1 and I2

2) At ISR “a”, MAX CONVn is changed to 2 (by software) for converting V1,
V2, and V3

3) At ISR “b”, the following events take place :

1) MAX CONVn is changed to 1 again for converting I1 and I2.
2) Values I1, I2, V1, V2, and V3 are read from ADC result registers.
3) The sequencer is reset.

4) Steps 2 and 3 are repeated. Note that the interrupt flag is set every time
SEQ CNTR n reaches zero and both interrupts are recognized.

Case 2: Number of samples in the first and second sequences are equal

Mode 2 Interrupt operation (i.e., Interrupt request occurs at every other

EOS)

1) Sequencer is initialized with MAX CONVn = 2 for converting I1, I2, and I3
(or V1, V2, and V3).

2) At ISR “b” and “d”, the following events take place :

1) Values I1, I2, I3,V1, V2, and V3 are read from ADC result registers.
2) The sequencer is reset.

3) Step 2 is repeated. Note that the interrupt flag is set every time SEQ CNTR
n reaches zero. This would happen after the ADC has finished converting
I1, I2, and I3 and also after converting V1, V2, and V3. But, only the EOS
generated after the conversion of V1, V2, and V3 triggers the interrupt.

7-14
 ADC Overview

Case 3: Number of samples in the first and second sequences are equal
(with dummy read)

Mode 2 Interrupt operation (i.e., Interrupt request occurs at every other

EOS)

1) Sequencer is initialized with MAX CONVn = 2 for I1, I2, x sampling

2) At ISR “b” and “d”, the following events take place :

1) Values I1, I2, x,V1, V2, and V3 are read from ADC result registers.
2) The sequencer is reset.

3) Step 2 is repeated. Note that the third I-sample (x) is a dummy sample, and
is not really required. However, to minimize ISR overhead and CPU inter-
vention, advantage is taken of the “every other” Interrupt request feature
of Mode 2.

Analog-to-Digital Converter (ADC) 7-15

ADC Overview

Figure 7−5. Interrupt Operation During Sequenced Conversions

50 µs

25 µs
EV1 Timer 1
counter

EV1
PWM

Sampling
I1,I2 V1,V2,V3 I1,I2 V1,V2,V3 request
Case 1
SEQ
“a” “b” “c” “d” interrupt

Sampling
request
I1,I2,I3 V1,V2,V3 I1,I2,I3 V1,V2,V3
Case 2
SEQ
“b” “d” interrupt

Sampling
I1,I2,x V1,V2,V3 I1,I2,x V1,V2,V3 request
Case 3
SEQ
“b” “d” interrupt

7-16
 ADC Clock Prescaler

7.3 ADC Clock Prescaler

The S/H block in the 240xA ADC can be tailored to accomodate the variation
in source impedances. This is achieved by the ACQ PS3−ACQ PS0 bits and
the CPS bit in the ADCTR1 register. The analog-to-digital conversion process
can be divided into two time segments, as shown in Figure 7−6.

Figure 7−6. ADC Conversion Time

••••••

S/H window Conversion

(2 * PS) (11 * ACLK)

1 complete ADC conversion

PS = a prescaled CPU clock

PS will be the same as the CPU clock if the prescaler = 1 (i.e., ACQ PS3−ACQ
PS0 bits are all zero) and if CPS = 0. For any other value of the prescaler, the
magnitude of PS will be magnified (effectively increasing the S/H window time)
as described by the “Acquisition Time Window” column in the bit description
for ACQ PS3−ACQ PS0. If the CPS bit is made 1, the S/H window is doubled.
This doubling of the S/H window is in addition to the “stretching” provided by
the prescaler. Figure 7−7 shows the role played by the various prescaler bits
in the ADC module. Note that PS and ACLK will be equal to CPU clock if
CPS = 0.

Analog-to-Digital Converter (ADC) 7-17

ADC Clock Prescaler

Figure 7−7. Clock Prescalers in 240xA ADC

ACQ PS3−ACQ PS0
Divide
by 2
(CPS = 1)
CLK ACLK Divide by PS S/H
(1 to 16) (2 * PS)
(CPU clock)
(CPS = 0)
×1

A/D
converter
(11 * ACLK)

7-18
 Calibration

7.4 Calibration
In the calibration mode, the sequencers are not operational and the ADCINn
pins are not connected to the A/D converter. The signal that gets connected
to the A/D converter input is determined by BRG ENA (Bridge Enable) and
HI/LO (VREFHI/VREFLO selection) bits. These two signals connect either
VREFLO or VREFHI or their midpoint to the A/D converter input and a single
conversion is then done. The calibration mode can calculate the zero,
midpoint, or full-scale offset errors of the ADC. The 2’s complement of the
offset error should then be loaded in the CALIBRATION register. (The 2’s
complement operation is applicable for “negative” errors only.) From that point
on, the ADC hardware automatically adds the offset error to the converted
value.

Figure 7−8. CALIBRATION Register − Address 70B8h

15 14 13 12 11 10 9 8

D9 D8 D7 D6 D5 D4 D3 D2

7 6 5 4 3 2 1 0

D1 D0 0 0 0 0 0 0

To summarize, the CALIBRATION register stores the end result of calibration

in the calibration mode. In the normal mode of the ADC, the value in the
CALIBRATION register is automatically added to the output of the ADC before
the result is stored in the RESULTn register.

Analog-to-Digital Converter (ADC) 7-19

Register Bit Descriptions

7.5 Register Bit Descriptions

7.5.1 ADC Control Register 1 (ADCTRL1)

Figure 7−9. ADC Control Register 1 (ADCTRL1) — Address 70A0h

15 14 13 12 11 10 9 8

Reserved RESET SOFT FREE ACQ PS3 ACQ PS2 ACQ PS1 ACQ PS0

RS-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

CPS CONT RUN INT PRI SEQ CASC CAL ENA BRG ENA HI/LO STEST ENA

RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, S = Set only, -0 = value after reset

Bit 15 Reserved

Bit 14 RESET. ADC module software reset

This bit causes a master reset on the entire ADC module. All register bits and
sequencer state machines are reset to the initial state as occurs when the
device reset pin is pulled low (or after a power-on reset).
0 No effect
1 Resets entire ADC module (bit is then set back to 0 by ADC
logic)

Note: Using the RESET Bit in the ADCTRL1 Register

The ADC module is reset during a system reset. If an ADC module reset is
desired at any other time, you can do so by writing a 1 to this bit. After a NOP,
you can then write the appropriate values to the ADCTRL1 register bits:
SPLK #01xxxxxxxxxxxxxxb,ADCTRL1; Resets the ADC (RESET = 1)
NOP ; Provides the required delay
; between writes to ADCTRL1
SPLK #00xxxxxxxxxxxxxxb,ADCTRL1; Takes the ADC out of Reset
; (RESET = 0)
Note that the second SPLK is not required if the default configuration is
sufficient.

7-20
 Register Bit Descriptions

Bits 13, 12 SOFT and FREE. Soft and Free bits

These bits determine what occurs when an emulation-suspend occurs (due
to the debugger hitting a breakpoint, for example). In free-run mode, the
peripheral can continue with whatever it is doing. In stop mode, the peripheral
can either stop immediately or stop when the current operation (i.e., the
current conversion) is complete.
Soft Free
0 0 Immediate stop on suspend
1 0 Complete current conversion before stopping
X 1 Free run, continue operation regardless of suspend
Bits 11−8 ACQ PS3 − ACQ PS0. Acquisition time window − prescale bits 3−0
These bits define the ADC clock prescale factor applied to the acquisition
portion of the conversion. The prescale values are defined in Table 7−3 and
Table 7−4.

Analog-to-Digital Converter (ADC) 7-21

Register Bit Descriptions

Table 7−3. ADC Clock Prescale Factors for CLK = 30 MHz

Source Source
Pre- Z Z
ACQ ACQ ACQ ACQ scaler Acquisition Time (CPS=0) (CPS=1)
# PS3 PS2 PS1 PS0 (div by) Window (Ω) (Ω)
0 0 0 0 0 1 2 x Tclk 67 385
1 0 0 0 1 2 4 x Tclk 385 1020
2 0 0 1 0 3 6 x Tclk 702 1655
3 0 0 1 1 4 8 x Tclk 1020 2290
4 0 1 0 0 5 10 x Tclk 1337 2925
5 0 1 0 1 6 12 x Tclk 1655 3560
6 0 1 1 0 7 14 x Tclk 1972 4194
7 0 1 1 1 8 16 x Tclk 2290 4829
8 1 0 0 0 9 18 x Tclk 2607 5464
9 1 0 0 1 10 20 x Tclk 2925 6099
A 1 0 1 0 11 22 x Tclk 3242 6734
B 1 0 1 1 12 24 x Tclk 3560 7369
C 1 1 0 0 13 26 x Tclk 3877 8004
D 1 1 0 1 14 28 x Tclk 4194 8639
E 1 1 1 0 15 30 x Tclk 4512 9274
F 1 1 1 1 16 32 x Tclk 4829 9909
Notes: 1) Period of Tclk is dependent on the “Conversion Clock Prescale” bit (Bit 7); i.e.,
CPS = 0: Tclk = 1/CLK (example, for CLK = 30 MHz, Tclk = 33 ns)
CPS = 1: Tclk = 2 × (1/CLK) (example, for CLK = 30 MHz, Tclk = 66 ns)
2) Source impedance Z is a design estimate only.

7-22
 Register Bit Descriptions

Table 7−4. ADC Clock Prescale Factors for CLK = 40 MHz

Source Source
Pre- Z Z
ACQ ACQ ACQ ACQ scaler Acquisition Time (CPS=0) (CPS=1)
# PS3 PS2 PS1 PS0 (div by) Window (Ω) (Ω)
0 0 0 0 0 1 2 x Tclk 53 291
1 0 0 0 1 2 4 x Tclk 291 767
2 0 0 1 0 3 6 x Tclk 529 1244
3 0 0 1 1 4 8 x Tclk 767 1720
4 0 1 0 0 5 10 x Tclk 1005 2196
5 0 1 0 1 6 12 x Tclk 1244 2672
6 0 1 1 0 7 14 x Tclk 1482 3148
7 0 1 1 1 8 16 x Tclk 1720 3625
8 1 0 0 0 9 18 x Tclk 1958 4101
9 1 0 0 1 10 20 x Tclk 2196 4577
A 1 0 1 0 11 22 x Tclk 2434 5053
B 1 0 1 1 12 24 x Tclk 2672 5529
C 1 1 0 0 13 26 x Tclk 2910 6005
D 1 1 0 1 14 28 x Tclk 3148 6482
E 1 1 1 0 15 30 x Tclk 3386 6958
F 1 1 1 1 16 32 x Tclk 3625 7434
Notes: 1) Period of Tclk is dependent on the “Conversion Clock Prescale” bit (Bit 7); i.e.,
CPS = 0: Tclk = 1/CLK (example, for CLK = 40 MHz, Tclk = 25 ns)
CPS = 1: Tclk = 2 × (1/CLK) (example, for CLK = 40 MHz, Tclk = 50 ns)
2) Source impedance Z is a design estimate only.

Analog-to-Digital Converter (ADC) 7-23

Register Bit Descriptions

Bit 7 CPS. Conversion clock prescale

This bit defines the ADC conversion logic clock prescale
0 Fclk = CLK/1
1 Fclk = CLK/2
CLK = CPU clock frequency
Bit 6 CONT RUN. Continuous run
This bit determines whether the sequencer operates in continuous conversion
mode or start-stop mode. This bit can be written while a current conversion
sequence is active. This bit will take effect at the end of the current conversion
sequence; i.e., software can set/clear this bit until EOS has occurred, for valid
action to be taken. In the continuous conversion mode, there is no need to
reset the sequencer; however, the sequencer must be reset in the start-stop
mode to put the converter in state CONV00.
0 Start-stop mode. Sequencer stops after reaching EOS. This is
used for multiple time-sequenced triggers.
1 Continuous conversion mode. After reaching EOS, the sequencer
starts all over again from state CONV00 (for SEQ1 and cascaded)
or CONV08 (for SEQ2).
Bit 5 INT PRI. ADC interrupt request priority
0 High priority
1 Low priority
Bit 4 SEQ CASC. Cascaded sequencer operation
This bit determines whether SEQ1 and SEQ2 operate as two 8-state
sequencers or as a single 16-state sequencer (SEQ).
0 Dual-sequencer mode. SEQ1 and SEQ2 operate as two 8-state
sequencers.
1 Cascaded mode. SEQ1 and SEQ2 operate as a single 16-state
sequencer (SEQ).
Bit 3 CAL ENA. Offset calibration enable
When set to 1, CAL ENA disables the input channel multiplexer, and connects
the calibration reference selected by the bits HI/LO and BRG ENA to the ADC
core inputs. The calibration conversion can then be started by setting bit 14
of ADCTRL2 register (STRT CAL) to 1. Note that CAL ENA should be set to 1
first before the STRT CAL bit can be used.
Note: This bit should not be set to 1 if STEST ENA = 1
0 Calibration mode disabled
1 Calibration mode enabled

7-24
 Register Bit Descriptions

Bit 2 BRG ENA. Bridge enable

Together with the HI/LO bit, BRG ENA allows a reference voltage to be
converted in calibration mode. See the description of the HI/LO bit for
reference voltage selections during calibration.
0 Full reference voltage is applied to the ADC input
1 A reference midpoint voltage is applied to the ADC input

Bit 1 HI/LO. VREFHI / VREFLO selection

When the fail self-test mode is enabled (STEST ENA = 1), HI/LO defines the
test voltage to be connected. In calibration mode, HI/LO defines the reference
source polarity; see Table 7−5. In normal operating mode, HI/LO has no effect.
0 VREFLO is used as precharge value at ADC input
1 VREFHI is used as precharge value at ADC input

Table 7−5. Reference Voltage Bit Selection

CAL ENA = 1 STEST ENA = 1

BRG ENA HI/LO Reference voltage (V) Reference voltage (V)
0 0 VREFLO VREFLO
0 1 VREFHI VREFHI
1 0 |(VREFHI − VREFLO) / 2| VREFLO
1 1 |(VREFLO − VREFHI) / 2| VREFHI

Bit 0 STEST ENA. Self-test function enable

0 Self-test mode disabled
1 Self-test mode enabled

Analog-to-Digital Converter (ADC) 7-25

Register Bit Descriptions

7.5.2 ADC Control Register 2 (ADCTRL2)

Figure 7−10. ADC Control Register 2 (ADCTRL2) — Address 70A1h

15 14 13 12 11 10 9 8

INT ENA INT ENA

EVB SOC RST SEQ1/ INT FLAG EVA SOC
SOC SEQ1 SEQ1 BSY SEQ1 SEQ1
SEQ STRT CAL SEQ1 SEQ1
(Mode 1) (Mode 0)

RW-0 RS-0 RW-0 R-0 RW-0 RW-0 RC-0 RW-0

7 6 5 4 3 2 1 0

INT ENA INT ENA

EXT SOC INT FLAG EVB SOC
RST SEQ2 SOC SEQ2 SEQ2 BSY SEQ2 SEQ2
SEQ1 SEQ2 SEQ2
(Mode 1) (Mode 0)

RW-0 RS-0 RW-0 R-0 RW-0 RW-0 RC-0 RW-0

Note: R = Read access, W = Write access, S = Set only, C = Clear, -0 = value after reset

Bit 15 EVB SOC SEQ. EVB SOC enable for cascaded sequencer
(Note: This bit is active only in cascaded mode.)
0 No action
1 Setting this bit allows the cascaded sequencer to be started by an
Event Manager B signal. The Event Manager can be programmed
to start a conversion on various events. See chapter 6, Event Man-
ager (EV), for details.

Bit 14 RST SEQ1 / STRT CAL. Reset Sequencer1/Start Calibration

Case: Calibration Disabled (Bit 3 of ADCTRL1) = 0

Writing a 1 to this bit will reset the sequencer immediately to an initial

“pretriggered” state, i.e., waiting for a trigger at CONV00. A currently active
conversion sequence will be aborted.
0 No action
1 Immediately reset sequencer to state CONV00

Case: Calibration Enabled (Bit 3 of ADCTRL1) = 1

Writing a 1 to this bit will begin the converter calibration process.

0 No action
1 Immediately start calibration process

7-26
 Register Bit Descriptions

Bit 13 SOC SEQ1. Start-of-conversion (SOC) trigger for Sequencer 1 (SEQ1). This
bit can be set by the following triggers:

S/W – Software writing a 1 to this bit

EVA – Event Manager A

EVB – Event Manager B (only in cascaded mode)

EXT – External pin (i.e., the ADCSOC pin)

When a trigger occurs, there are three possibilities:

Case 1: SEQ1 idle and SOC bit clear

SEQ1 starts immediately (under arbiter control). This bit is set and cleared,
allowing for any “pending” trigger requests.

Case 2: SEQ1 busy and SOC bit clear

Bit is set signifying a trigger request is pending. When SEQ1 finally starts after
completing current conversion, this bit will be cleared.

Case 3: SEQ1 busy and SOC bit set

Any trigger occurring in this case will be ignored (lost).

0 Clears a pending SOC trigger.

Note: If the sequencer has already started, this bit will automatical-
ly be cleared, and hence, writing a zero will have no effect; i.e., an
already started sequencer cannot be stopped by clearing this bit.
1 Software trigger − Start SEQ1 from currently stopped position (i.e.,
Idle mode)

Note:
The RST SEQ1 (ADCTRL2.14) and the SOC SEQ1 (ADCTRL2.13) bits
should not be set in the same instruction. This will reset the sequencer, but
will not start the sequence. The correct sequence of operation is to set the
RST SEQ1 bit first, and the SOC SEQ1 bit in the following instruction. This
ensures that the sequencer is reset and a new sequence started. This se-
quence applies to the RST SEQ2 (ADCTRL2.6) and SOC SEQ2
(ADCTRL2.5) bits also.

Bit 12 SEQ1 BSY. SEQ1 Busy

This bit is set to a 1 while the ADC autoconversion sequence is in progress.
It is cleared when the conversion sequence is complete.
0 Sequencer is Idle (i.e., waiting for trigger)
1 Conversion sequence is in progress

Analog-to-Digital Converter (ADC) 7-27

Register Bit Descriptions

Checking for End-of-Sequence

After a start-of-sequence (SOC) is initiated, four NOPs need to be executed

before polling the SEQ1 or SEQ2 BSY bit.

Example code:
ADC_LOOP1:
LDP #ADCTRL1>>7
SPLK #0100000000000000b,ADCTRL2 ;Reset for SEQ1
SPLK #0010000000000000b,ADCTRL2 ;SOC for SEQ1
NOP ;Wait for Busy
;bit to set.
NOP
NOP
NOP
CHK_EOS1:
BIT ADCTRL2, 3 ; Wait for SEQ1 Busy bit
; to clear
BCND CHK_EOS1, TC ; If TC=1, keep looping.

A better approach would be to check the INT FLAG SEQn bit for
end-of-sequence. This does not require NOPs, as the bit should already be
cleared prior to starting a sequenced conversion. To reiterate, the NOPs are
required only when polling the SEQn BUSY bit; interrupt-driven conversions
do not have this requirement.

Bits 11−10 INT ENA SEQ1. Interrupt-mode-enable control for SEQ1

Bit 11 Bit 10 Operation Description

0 0 Interrupt is Disabled
0 1 Interrupt Mode 1
Interrupt requested immediately when INT FLAG SEQ1
flag is set
1 0 Interrupt Mode 2
Interrupt requested only if INT FLAG SEQ1 flag is already
set. If clear†, INT FLAG SEQ1 flag is set and INT request
is suppressed. (This mode allows Interrupt requests to be
generated for every other EOS.)
1 1 Reserved
† This means that the last completed sequence is the first of the two sequences needed to assert
an interrupt.

7-28
 Register Bit Descriptions

Bit 9 INT FLAG SEQ1. ADC interrupt flag bit for SEQ1

This bit indicates whether an interrupt event has occurred or not. This bit must
be cleared by the user writing a 1 to it.
0 No interrupt event
1 An interrupt event has occurred.

Bit 8 EVA SOC SEQ1. Event Manager A SOC mask bit for SEQ1
0 SEQ1 cannot be started by EVA trigger.
1 Allows SEQ1/SEQ to be started by Event Manager A trigger. The
Event Manager can be programmed to start a conversion on vari-
ous events. See chapter 6, Event Manager (EV), for details.

Bit 7 EXT SOC SEQ1. External signal start-of-conversion bit for SEQ1
0 No action
1 Setting this bit enables an ADC autoconversion sequence to be
started by a signal from the ADCSOC device pin.

Bit 6 RST SEQ2. Reset SEQ2

0 No action
1 Immediately resets SEQ2 to an initial “pretriggered” state, i.e.,
waiting for a trigger at CONV08. A currently active conversion se-
quence will be aborted.

Analog-to-Digital Converter (ADC) 7-29

Register Bit Descriptions

Bit 5 SOC SEQ2. Start-of-conversion trigger for Sequencer 2 (SEQ2)

(Only applicable in dual-sequencer mode; ignored in cascaded mode.)

This bit can be set by the following triggers:

S/W – Software writing of 1 to this bit

EVB – Event Manager B

When a trigger occurs, there are three possibilities:

Case 1: SEQ2 idle and SOC bit clear

SEQ2 starts immediately (under arbiter control) and the bit is cleared, allowing
for any pending trigger requests.

Case 2: SEQ2 busy and SOC bit clear

Bit is set signifying a trigger request is pending. When SEQ2 finally starts after
completing current conversion, this bit will be cleared.

Case 3: SEQ2 busy and SOC bit set

Any trigger occurring in this case will be ignored (lost).

0 Clears a Pending SOC trigger.

Note: If the sequencer has already started, this bit will automatical-
ly be cleared, and hence, writing a zero will have no effect; i.e., an
already started sequencer cannot be stopped by clearing this bit.
1 Software trigger − Start SEQ2 from currently stopped position (i.e.,
Idle mode)

Bit 4 SEQ2 BSY. SEQ2 Busy

This bit is set to a 1 while the ADC autoconversion sequence is in progress.

It is cleared when the conversion sequence is complete.
0 Sequencer is idle (i.e., waiting for trigger).
1 Conversion sequence is in progress.

7-30
 Register Bit Descriptions

Bits 3−2 INT ENA SEQ2. Interrupt-mode-enable control for SEQ2

Bit 3 Bit 2 Operation Description

0 0 Interrupt is Disabled
0 1 Interrupt Mode 1
Interrupt requested immediate on INT FLAG SEQ2 flag
set
1 0 Interrupt Mode 2
Interrupt requested only if INT FLAG SEQ2 flag is already
set. If clear†, INT FLAG SEQ2 flag is set and INT request
is suppressed. (This mode allows Interrupt requests to be
generated for every other EOS)
1 1 Reserved
† This means that the last completed sequence is the first of the two sequences needed to assert
an interrupt.

Bit 1 INT FLAG SEQ2. ADC interrupt flag bit for SEQ2

This bit indicates whether an interrupt event has occurred or not. This bit must
be cleared by the user writing a 1 to it.
0 No interrupt event.
1 An interrupt event has occurred.

Bit 0 EVB SOC SEQ2. Event Manager B SOC mask bit for SEQ2
0 SEQ2 cannot be started by EVB trigger.
1 Allows SEQ2 to be started by Event Manager B trigger. The Event
Manager can be programmed to start a conversion on various
events. See chapter 6, Event Manager (EV), for details.

7.5.3 Maximum Conversion Channels Register (MAXCONV)

Figure 7−11.Maximum Conversion Channels Register (MAXCONV) — Address 70A2h

15−8

Reserved

R-x

7 6 5 4 3 2 1 0

MAX MAX MAX MAX MAX MAX MAX

Reserved
CONV2_2 CONV2_1 CONV2_0 CONV1_3 CONV1_2 CONV1_1 CONV1_0

R-x RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, x = undefined, -0 = value after reset

Analog-to-Digital Converter (ADC) 7-31

Register Bit Descriptions

Bits 15−7 Reserved

Bits 6−0 MAX CONVn. MAX CONVn bit field defines the maximum number of conver-
sions executed in an autoconversion session. The bit fields and their operation
vary according to the sequencer modes (dual/cascaded).

For SEQ1 operation, bits MAX CONV1_2 – 0 are used.

For SEQ2 operation, bits MAX CONV2_2 – 0 are used.

For SEQ operation, bits MAX CONV1_3 – 0 are used.

An autoconversion session always starts with the initial state and continues
sequentially until the end state if allowed. The result buffer is filled in a
sequential order. Any number of conversions between 1 and (MAX CONVn
+1) can be programmed for a session.

Example 7−3. MAXCONV Register Bit Programming

If only five conversions are required, then MAX CONVn is set to four.

Case 1: Dual mode SEQ1 and cascaded mode

Sequencer goes from CONV00 to CONV04, and the five conversion results
are stored in the registers Result 00 to Result 04 of the Conversion Result
Buffer.

Case 2: Dual mode SEQ2

Sequencer goes from CONV08 to CONV12, and the five conversion results
are stored in the registers Result 08 to Result 12 of the Conversion Result
Buffer.

MAX CONV1 Value >7 for Dual-Sequencer Mode

If a value for MAX CONV1, which is greater than 7, is chosen for the dual-
sequencer mode (i.e., two separate 8-state sequencers), then SEQ CNTR n
will continue counting past seven, causing the sequencer to wrap around to
CONV00 and continue counting.

7-32
 Register Bit Descriptions

Table 7−6. Bit Selections for MAX CONV1 for Various Number of Conversions
MAX CONV1.3−0 Number of conversions
0000 1
0001 2
0010 3
0011 4
0100 5
0101 6
0110 7
0111 8
1000 9
1001 10
1010 11
1011 12
1100 13
1101 14
1110 15
1111 16

7.5.4 Autosequence Status Register (AUTO_SEQ_SR)

Figure 7−12. Autosequence Status Register (AUTO_SEQ_SR) — Address 70A7h

15−12 11 10 9 8

SEQ SEQ SEQ SEQ

Reserved
CNTR 3 CNTR 2 CNTR 1 CNTR 0

R-x R-0 R-0 R-0 R-0

7 6 5 4 3 2 1 0

SEQ2- SEQ2- SEQ2- SEQ1- SEQ1- SEQ1- SEQ1-

Reserved
State2 State1 State0 State3 State2 State1 State0

R-x R-0 R-0 R-0 R-0 R-0 R-0 R-0

Note: R = Read access, x = undefined, -0 = value after reset

Bits 15−12 Reserved

Bits 11−8 SEQ CNTR 3 − SEQ CNTR 0. Sequencing counter status bits

The SEQ CNTR n 4-bit status field is used by SEQ1, SEQ2, and the cascaded
sequencer.

Analog-to-Digital Converter (ADC) 7-33

Register Bit Descriptions

SEQ2 is irrelevant in cascaded mode.

At the start of an autosequenced session, SEQ CNTR n is loaded with the

value from MAX CONVn. The SEQ CNTR n bits can be read at any time during
the countdown process to check status of the sequencer. This value, together
with the SEQ1 and SEQ2 Busy bits, uniquely identifies the progress or state
of the active sequencer at any point in time.

Table 7−7. Status Bit Values for SEQ CNTR n

SEQ CNTR n
Number of conversions remaining
(read only)
0000 1
0001 2
0010 3
0011 4
0100 5
0101 6
0110 7
0111 8
1000 9
1001 10
1010 11
1011 12
1100 13
1101 14
1110 15
1111 16

Bit 7 Reserved

Bits 6−4 SEQ2-State2 − SEQ2-State0

Reflects the state of SEQ2 sequencer at any point of time. If necessary, you
can poll these bits to read interim results before an EOS. SEQ2 is irrelevant
in cascaded mode.

Bits 3−0 SEQ1-State3 − SEQ1-State0

Reflects the state of SEQ1 sequencer at any point of time. If need be, user can
poll these bits to read interim results before an EOS.
Note: The AUTO_SEQ_SR register and the RESULTn registers of the 240xA ADC module are
“Read-only.” Any attempt to write to these registers causes an NMI.

7-34
 Register Bit Descriptions

7.5.5 ADC Input Channel Select Sequencing Control Registers (CHSELSEQn)

Figure 7−13. ADC Input Channel Select Sequencing Control Registers (CHSELSEQn)

Bits 15−12 Bits 11−8 Bits 7−4 Bits 3−0

70A3h CONV03 CONV02 CONV01 CONV00 CHSELSEQ1
RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−12 Bits 11−8 Bits 7−4 Bits 3−0

70A4h CONV07 CONV06 CONV05 CONV04 CHSELSEQ2
RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−12 Bits 11−8 Bits 7−4 Bits 3−0

70A5h CONV11 CONV10 CONV09 CONV08 CHSELSEQ3
RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−12 Bits 11−8 Bits 7−4 Bits 3−0

70A6h CONV15 CONV14 CONV13 CONV12 CHSELSEQ4
RW-0 RW-0 RW-0 RW-0
Note: R = Read access, W = Write access, -0 = value after reset

Each of the 4-bit fields, CONVnn, selects one of the sixteen muxed analog
input ADC channels for an autosequenced conversion.

Analog-to-Digital Converter (ADC) 7-35

Register Bit Descriptions

Table 7−8. CONVnn Bit Values and the ADC Input Channels Selected

CONVnn Value ADC Input Channel Selected

0000 Channel 0
0001 Channel 1
0010 Channel 2
0011 Channel 3
0100 Channel 4
0101 Channel 5
0110 Channel 6
0111 Channel 7
1000 Channel 8
1001 Channel 9
1010 Channel 10
1011 Channel 11
1100 Channel 12
1101 Channel 13
1110 Channel 14
1111 Channel 15

7-36
 Register Bit Descriptions

7.5.6 ADC Conversion Result Buffer Registers (RESULTn)

Note: In the cascaded sequencer mode, registers RESULT8 through RESULT15 will hold the
results of the ninth through sixteenth conversions.

Figure 7−14. ADC Conversion Result Buffer Registers (RESULTn)

15 14 13 12 11 10 9 8

D9 D8 D7 D6 D5 D4 D3 D2

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

7 6 5 4 3 2 1 0

D1 D0 0 0 0 0 0 0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

Notes: 1) Buffer addresses = 70A8h to 70B7h (i.e., 16 registers)

2) The 10-bit conversion result (D9−D0) is left-justified.
3) The AUTO_SEQ_SR register and the RESULTn registers of the 240xA ADC module are “Read-only.” Any attempt
to write to these registers causes an NMI.

Analog-to-Digital Converter (ADC) 7-37

ADC Conversion Clock Cycles

7.6 ADC Conversion Clock Cycles

The conversion time is a function of the number of conversions performed in
a given sequence. The conversion cycle can be divided into five phases:

Start-of-sequence sync-up (SOS synch)

The SOS synch applies only to the first conversion in a sequence.

Acquisition time (ACQ)

Conversion time (CONV)

End-of-Conversion cycle (EOC)

The ACQ, CONV, and EOC apply to all conversions in a sequence

End-of-Sequence flag-setting cycle (EOS)

The EOS applies only to the last conversion in a sequence.

Each category is listed in Table 7−9 with the number of CLKOUT cycles it takes
to complete.

Table 7−9. ADC Conversion Phases vs CLKOUT cycles

Datasheet No- Conversion CLKOUT cycles CLKOUT cycles

menclature phase (CPS = 0) (CPS = 1)
td(SOC−SH) SOS synch 2 2 or 3
tw(SH) ACQ 2 4
tw(C) CONV 10 20
EOC 1 2
td(EOC)
EOS 1 1
† When CPS = 1, a start-of-sequence can take an extra CLKOUT cycle to sync up with the ADC
clock (ADCCLK) depending on which cycle the SOC bit is set in software.
‡ The ACQ value is dependent on the ACQ PSn bits. Values shown in Table 7−9 are applicable
when ACQ PS = 0. As an example, values for ACQ when ACQ PS = 1, 2, and 3 are shown in
Table 7−10. This table can be extrapolated for all ACQ PS values.

Table 7−10. ACQ Values When ACQ PS = 1, 2, and 3

ACQ PS (CPS = 0) (CPS = 1)

1 ACQ = 4 ACQ = 8
2 ACQ = 6 ACQ = 12
3 ACQ = 8 ACQ = 16

7-38
 ADC Conversion Clock Cycles

Example 7−4. Calculating the Conversion Time for a Multiple Conversion Sequence With
CPS = 0 and ACQ = 0:
1st conversion − 15 CLKOUT cycles
2nd conversion − 13 CLKOUT cycles
3rd conversion − 13 CLKOUT cycles
Last conversion − 14 CLKOUT cycles.

Example 7−5. Calculating the Conversion Time for a Single Conversion Sequence With
CPS = 1 and ACQ = 1:
1st and only conversion − 33 or 34 CLKOUT cycles.

Analog-to-Digital Converter (ADC) 7-39

7-40
 Chapter 8

      ( )

This chapter describes the architecture, functions, and programming of the

serial communications interface (SCI) module. All registers in this peripheral
are eight bits wide.

The programmable SCI supports asynchronous serial (UART) digital

communications between the CPU and other asynchronous peripherals that
use the standard NRZ (non-return-to-zero) format. The SCI’s receiver and
transmitter are double buffered, and each has its own separate enable and
interrupt bits. Both may be operated independently or simultaneously in the
full-duplex mode.

To ensure data integrity, the SCI checks received data for break detection,
parity, overrun, and framing errors. The bit rate (baud) is programmable to over
65,000 different speeds through a 16-bit baud-select register.

For convenience, references to a bit in a register are abbreviated using the

register name followed by a period and the number of the bit. For example, the
notation for bit 6 of the SCI priority control register (SCIPRI) is SCIPRI.6.

Topic Page

8.1 C240 SCI vs. LF/LC240xA SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8.2 SCI Programmable Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.3 SCI Multiprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.4 SCI Communication Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8.5 SCI Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
8.6 SCI Baud Rate Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
8.7 SCI Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20

8-1
C240 SCI vs. LF/LC240xA SCI

8.1 C240 SCI vs. LF/LC240xA SCI

Multiplexing the SCI pins with general-purpose I/O is controlled by bits in the
digital I/O peripheral. As a consequence, the register SCIPC2 (705Eh) has
been removed.

The CLKENA bit in SCICTL1 (7051h) has been removed, since it served no
purpose in 2-pin SCI implementations.

The function of the SCIENA bit in SCICCR (7050h) has changed, and is now
a LOOP BACK ENA test mode bit. The enable function is no longer required
for correct operation of the SCI.

There is no difference with respect to the 241/242/243 SCI functionality;

however, the clock for the SCI must be enabled during peripheral initialization

(by writing a 1 to bit 6 of the SCSRI register).

8.1.1 SCI Physical Description

The SCI module, shown in Figure 8−1 on page 8-4, has the following key
features:

Two I/O pins

 SCIRXD (SCI receive data input)

 SCITXD (SCI transmit data output)

Programmable bit rates to over 65,000 different speeds through a 16-bit

baud select register
 Range with 40-MHz CLKOUT: 76 bps to 2500 kbps
 Number of bit rates: 64K

Programmable data word length from one to eight bits

Programmable number of stop bits (one or two)

Internally generated serial clock

Four error detection flags

 Parity error
 Overrun error
 Framing error
 Break detect error

8-2
 C240 SCI vs. LF/LC240xA SCI

Two wake-up multiprocessor modes

 Idle-line wake-up
 Address-bit wake-up

Half- or full-duplex operation

Double-buffered receive and transmit functions

A transmitter and a receiver that can be operated by interrupts or by polling

status flags:
 Transmitter: TXRDY flag (indicates when the transmitter buffer regis-
ter is ready to receive another character from the CPU core) and TX
EMPTY flag (indicates when the transmit shift register is empty)
 Receiver: RXRDY flag (indicates when the receiver buffer register is
ready to receive another character from the external world), BRKDT
flag (indicates when a break condition occurs), and RX ERROR (mon-
itors four interrupt conditions)

Separate enable bits for transmitter and receiver interrupts

Separate error interrupts for multiple error conditions

NRZ (non-return-to-zero) format

Serial Communications Interface (SCI) 8-3

C240 SCI vs. LF/LC240xA SCI

Figure 8−1. SCI Block Diagram

SCITXBUF.7−0 SCI TX interrupt

TXRDY TXINTENA TXINT External
Frame format and mode Transmitter data
SCICTL1.3 SCICTL2.7 connections
buffer register
Parity 1 SCICTL2.0
8 TXEMPTY
Even/odd Enable
SCICTL2.6
SCICCR.6 SCICCR.5 WUT
TXSHF TXENA
SCITXD
register
SCICTL1.1
SCIHBAUD.7−0
SCI priority level
Baud rate 1
Low INT priority
MSbyte
register High INT priority 0
SCI
clock SCILBAUD.7−0 SCITX priority
Baud rate SCIPRI.6
LSbyte 1
register Low INT priority
0
High INT priority
SCIRX priority
SCIPRI.5

RXSHF
RXWAKE register
SCIRXST.1
SCIRXD
RXENA
RXERRINTENA
SCICTL1.6 SCICTL1.0 8 SCI RX interrupt
RXRDY RX/BKINTENA
Receiver data SCIRXST.6
RXINT

RX error buffer register

BRKDT SCICTL2.1
SCIRXST.7 SCIRXST.4−2 SCIRXBUF.7−0 SCIRXST.5
RX error FE OE PE

Note: All SCI registers are eight bits wide. These eight bits are mapped to the lower eight bits of the 16-bit
words.

8-4
 C240 SCI vs. LF/LC240xA SCI

8.1.2 Architecture
The major elements used in full-duplex operation are shown in Figure 8−1,
SCI Block Diagram, and include:

A transmitter (TX) and its major registers (upper half of Figure 8−1)

 SCITXBUF — transmitter data buffer register. Contains data (loaded

by the CPU) to be transmitted
 TXSHF register — transmitter shift register. Accepts data from regis-
ter SCITXBUF and shifts data onto the SCITXD pin, one bit at a time

A receiver (RX) and its major registers (lower half of Figure 8−1)

 RXSHF register — receiver shift register. Shifts data in from SCIRXD

pin, one bit at a time
 SCIRXBUF — receiver data buffer register. Contains data to be read
by the CPU. Data from a remote processor is loaded into register
RXSHF and then into registers SCIRXBUF and SCIRXEMU

A programmable baud generator

Data-memory-mapped control and status registers (see section, 8.1.3,

SCI Module Register Addresses.

The SCI receiver and transmitter can operate either independently or

simultaneously.

8.1.3 SCI Module Register Addresses

Table 8−1 on page 8-6 lists the addresses of the SCI registers.

Serial Communications Interface (SCI) 8-5

C240 SCI vs. LF/LC240xA SCI

Table 8−1. Overview of SCI Registers

Described In

Address Symbol Name Description Section Page

7050h SCICCR SCI communication Defines the character format, pro- 8.7.1 8-21
control register tocol, and communications mode
used by the SCI.
7051h SCICTL1 SCI control register 1 Controls the RX, TX, and receiver 8.7.2 8-23
error interrupt enable, TXWAKE
and SLEEP functions, and the SCI
software reset.
7052h SCIHBAUD SCI baud-select Stores the data (MSbyte) required 8.7.3 8-26
register, high bits to generate the bit rate.
7053h SCILBAUD SCI baud-select Stores the data (LSbyte) required 8.7.3 8-26
register, low bits to generate the bit rate.
7054h SCICTL2 SCI control register 2 Contains the transmitter interrupt 8.7.4 8-27
enable, the receiver-buffer/break
interrupt enable, the transmitter
ready flag, and the transmitter
empty flag.
7055h SCIRXST SCI receiver status Contains seven receiver status 8.7.5 8-28
register flags.
7056h SCIRXEMU SCI emulation data Contains data received for screen 8.7.6.1 8-30
buffer register updates, principally used by the
emulator. (Not a real register − just
an alternate address for reading
SCIRXBUF without clearing
RXRDY)
7057h SCIRXBUF SCI receiver data Contains the current data from the 8.7.6.2 8-31
buffer register receiver shift register.
7058h — Illegal Illegal
7059h SCITXBUF SCI transmiter data Stores data bits to be transmitted 8.7.7 8-31
buffer register by the SCI.
705Ah — Illegal Illegal
705Bh — Illegal Illegal
705Ch — Illegal Illegal
705Dh — Illegal Illegal
705Eh — Illegal Illegal
705Fh SCIPRI SCI priority control Contains the receiver and transmit- 8.7.8 8-32
register ter interrupt priority select bits and
the emulator suspend enable bits.

8-6
 C240 SCI vs. LF/LC240xA SCI

8.1.4 Multiprocessor and Asynchronous Communication Modes

The SCI has two multiprocessor protocols, the idle-line multiprocessor mode
(see section 8.3.1 on page 8-10) and the address-bit multiprocessor mode
(see section 8.3.2 on page 8-13). These protocols allow efficient data transfer
between multiple processors.

The SCI offers the universal asynchronous receiver/transmitter (UART)

communications mode for interfacing with many popular peripherals. The
asynchronous mode (see section 8.4 on page 8-15) requires two lines to
interface with many standard devices such as terminals and printers that use
RS-232-C formats. Data transmission characteristics include:

One start bit

One to eight data bits

An even/odd parity bit or no parity bit

One or two stop bits

Serial Communications Interface (SCI) 8-7

SCI Programmable Data Format

8.2 SCI Programmable Data Format

SCI data, both receive and transmit, is in NRZ (non-return-to-zero) format. The
NRZ data format, shown in Figure 8−2, consists of:

One start bit

One to eight data bits

An even/odd parity bit (optional)

One or two stop bits

An extra bit to distinguish addresses from data (address-bit mode only)

The basic unit of data is called a character and is one to eight bits in length.
Each character of data is formatted with a start bit, one or two stop bits, and
optional parity and address bits. A character of data with its formatting
information is called a frame and is shown in Figure 8−2.

Figure 8−2. Typical SCI Data Frame Formats

Start LSB 2 3 4 5 6 7 MSB Parity Stop

Idle-line mode
(Normal nonmultiprocessor communications)

Address bit

Start LSB 2 3 4 5 6 7 MSB Addr/ Parity Stop

data
Address-bit mode

To program the data format, use the SCICCR register. The bits used to
program the data format are shown in Table 8−2.

Table 8−2. Programming the Data Format Using SCICCR

Bit Name Designation Functions
SCI CHAR2−0 SCICCR.2−0 Select the character (data) length (one to
eight bits). Bit values are shown in
Table 8−4 (page 8-22).

PARITY ENABLE SCICCR.5 Enables the parity function if set to 1, or

disables the parity function if cleared to 0.

EVEN/ODD PARITY SCICCR.6 If parity is enabled, selects odd parity if

cleared to 0 or even parity if set to 1.

STOP BITS SCICCR.7 Determines the number of stop bits trans-

mitted—one stop bit if cleared to 0 or two
stop bits if set to 1.

8-8
 SCI Multiprocessor Communication

8.3 SCI Multiprocessor Communication

The multiprocessor communication format allows one processor to efficiently
send blocks of data to other processors on the same serial link. On one serial
line, there should be only one transfer at a time. In other words, there can be
only one talker on a serial line at a time.

Address Byte
The first byte of a block of information that the talker sends contains an address
byte that is read by all listeners. Only listeners with the correct address can be
interrupted by the data bytes that follow the address byte. The listeners with
an incorrect address remain uninterrupted until the next address byte.

Sleep Bit
All processors on the serial link set their SCI’s SLEEP bit (SCICTL1.2) to 1 so
that they are interrupted only when the address byte is detected. When a
processor reads a block address that corresponds to the CPU’s device
address as set by your application software, your program must clear the
SLEEP bit to enable the SCI to generate an interrupt on receipt of each data
byte.

Although the receiver still operates when the SLEEP bit is 1, it does not set
RXRDY, RXINT, or any of the receiver error status bits to 1 unless the address
byte is detected and the address bit in the received frame is a 1 (applicable to
address-bit mode). The SCI does not alter the SLEEP bit; your software must
alter the SLEEP bit.

Recognizing the Address Byte

A processor recognizes an address byte differently, depending on the
multiprocessor mode used. For example:

The idle-line mode (section 8.3.1 on page 8-10) leaves a quiet space be-
fore the address byte. This mode does not have an extra address/data bit
and is more efficient than the address-bit mode for handling blocks that
contain more than ten bytes of data. The idle-line mode should be used
for typical non-multiprocessor SCI communication.

The address-bit mode (section 8.3.2 on page 8-13) adds an extra bit (that
is, an address bit) into every byte to distinguish addresses from data. This
mode is more efficient in handling many small blocks of data because, un-
like the idle mode, it does not have to wait between blocks of data. Howev-

Serial Communications Interface (SCI) 8-9

SCI Multiprocessor Communication

er, at a high transmit speed, the program is not fast enough to avoid a
10-bit idle in the transmission stream.

Controlling the SCI TX and RX Features

The multiprocessor mode is software selectable via the ADDR/IDLE MODE bit
(SCICCR.3). Both modes use the TXWAKE flag bit (SCICTL1.3), RXWAKE
flag bit (SCIRXST.1), and the SLEEP flag bit (SCICTL1.2) to control the SCI
transmitter and receiver features of these modes.

Receipt Sequence

In both multiprocessor modes, the receive sequence is:

1) At the receipt of an address block, the SCI port wakes up and requests an
interrupt (bit RX/BK INT ENA-SCICTL2.1 must be enabled to request an
interrupt). It reads the first frame of the block, which contains the destina-
tion address.

2) A software routine is entered through the interrupt and checks the incom-
ing address. This address byte is checked against its device address byte
stored in memory.

3) If the check shows that the block is addressed to the device CPU, the CPU
clears the SLEEP bit and reads the rest of the block; if not, the software
routine exits with the SLEEP bit still set and does not receive interrupts un-
til the next block start.

8.3.1 Idle-Line Multiprocessor Mode

In the idle-line multiprocessor protocol (ADDR/IDLE MODE bit=0), blocks are
separated by having a longer idle time between the blocks than between
frames in the blocks. An idle time of ten or more high-level bits after a frame
indicates the start of a new block. The time of a single bit is calculated directly
from the baud value (bits per second). The idle-line multiprocessor
communication format is shown in Figure 8−3 (ADDR/IDLE MODE bit is
SCICCR.3).

8-10
 SCI Multiprocessor Communication

Figure 8−3. Idle-Line Multiprocessor Communication Format

Several blocks of frames

ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇ

ÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇ
Data format
(Pins SCIRXD, SCITXD)
Idle periods of 10 bits or more
separate the blocks

One block of frames

Start

Start
Start

Data format expanded Address Data Last Data

First frame within block Frame within Idle period Idle period
Is address; it follows idle block less than of 10 bits
period of 10 bits or more 10 bits or more

Idle-Line Mode Steps

The steps followed by the idle-line mode:

1) SCI wakes up after receipt of the block-start signal.

2) The processor recognizes the next SCI interrupt.

3) The interrupt service routine compares the received address (sent by a re-
mote transmitter) to its own.

4) If the CPU is being addressed, the service routine clears the SLEEP bit
and receives the rest of the data block.

5) If the CPU is not being addressed, the SLEEP bit remains set. This lets
the CPU continue to execute its main program without being interrupted
by the SCI port until the next detection of a block start.

Block Start Signal

There are two ways to send a block-start signal:

Method 1: Deliberately leave an idle time of ten bits or more by delaying

the time between the transmission of the last frame of data in the previous
block and the transmission of the address frame of the new block.

Serial Communications Interface (SCI) 8-11

SCI Multiprocessor Communication

Method 2: The SCI port first sets the TXWAKE bit (SCICTL1.3) to 1 before
writing to the SCITXBUF register. This sends an idle time of exactly 11 bits.
In this method, the serial communications line is not idle any longer than
necessary. (A don’t care byte has to be written to SCITXBUF after setting
TXWAKE, and before sending the address, so as to transmit the idle time.)

Wake-UP Temporary (WUT) Flag

Associated with the TXWAKE bit is the wake-up temporary (WUT) flag. WUT
is an internal flag, double-buffered with TXWAKE. When TXSHF is loaded
from SCITXBUF, WUT is loaded from TXWAKE, and the TXWAKE bit is
cleared to 0. This arrangement is shown in Figure 8−4. (Figure 8−1, SCI Block
Diagram on page 8-4 shows this in additional detail.)

Figure 8−4. Double-Buffered WUT and TXSHF

TXWAKE Transmit buffer (SCITXBUF)

1 8

WUT TXSHF

Note: WUT = wake-up temporary

Sending a Block Start Signal

To send out a block-start signal of exactly one frame time during a sequence
of block transmissions:

1) Write a 1 to the TXWAKE bit.

2) Write a data word (content not important: a don’t care) to the SCITXBUF
register (transmit data buffer) to send a block-start signal. (The first data
word written is suppressed while the block-start signal is sent out and ig-
nored after that.) When the TXSHF (transmit shift register) is free again,
SCITXBUF’s contents are shifted to TXSHF, the TXWAKE value is shifted
to WUT, and then TXWAKE is cleared.
Because TXWAKE was set to a 1, the start, data, and parity bits are re-
placed by an idle period of 11 bits transmitted following the last stop bit of
the previous frame.
3) Write a new address value to SCITXBUF.

A don’t-care data word must first be written to register SCITXBUF so that the
TXWAKE bit value can be shifted to WUT. After the don’t-care data word is

8-12
 SCI Multiprocessor Communication

shifted to the TXSHF register, the SCITXBUF (and TXWAKE if necessary) can
be written to again because TXSHF and WUT are both double-buffered.

Receiver Operation

The receiver operates regardless of the SLEEP bit. However, the receiver
neither sets RXRDY nor the error status bits, nor does it request a receive
interrupt until an address frame is detected.

8.3.2 Address-Bit Multiprocessor Mode

In the address-bit protocol (ADDR/IDLE MODE bit=1), frames have an extra
bit called an address bit that immediately follows the last data bit. The address
bit is set to 1 in the first frame of the block and to 0 in all other frames. The idle
period timing is irrelevant (see Figure 8−5, ADDR/IDLE MODE bit in
SCICCR.3).

Sending an Address

The TXWAKE bit value is placed in the address bit. During transmission, when
the SCITXBUF register and TXWAKE are loaded into the TXSHF register and
WUT respectively, TXWAKE is reset to 0 and WUT becomes the value of the
address bit of the current frame. Thus, to send an address:

1) Set the TXWAKE bit to 1 and write the appropriate address value to the
SCITXBUF register.
When this address value is transferred to the TXSHF register and
shifted out, its address bit is sent as a 1. This flags the other proces-
sors on the serial link to read the address.

2) Write to SCITXBUF and TXWAKE after TXSHF and WUT are loaded.
(Can be written to immediately since both TXSHF and WUT are both
double-buffered.

3) Leave the TXWAKE bit set to 0 to transmit non-address frames in the

block.

Note: The Address-bit format is for transfers of 11 bytes or less

As a general rule, the address-bit format is typically used for data frames of
11 bytes or less. This format adds one bit value (1 for an address frame, 0
for a data frame) to all data bytes transmitted. The idle-line format is typically
used for data frames of 12 bytes or more.

Serial Communications Interface (SCI) 8-13

SCI Multiprocessor Communication

Figure 8−5. Address-Bit Multiprocessor Communication Format

Blocks of frames

ÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
Data format
(Pins SCIRXD, SCITXD)

Idle periods of no significance

One block
Start

Start

Start
Data format expanded Addr 1 Data 0 Addr 1

First frame within Frame within block Next frame is address

block is address (Address bit is 0) for next block
(Address bit is 1) (Address bit is 1)

Idle time is of
no significance

Address bit

Start LSB MSB 1 Parity Stop

Address-bit mode frame example

8-14
 SCI Communication Format

8.4 SCI Communication Format

The SCI asynchronous communication format uses either single line (one
way) or two line (two way) communications. In this mode, the frame consists
of a start bit, one to eight data bits, an optional even/odd parity bit, and one or
two stop bits (shown in Figure 8−6). There are eight SCICLK periods per data
bit.

The receiver begins operation on receipt of a valid start bit. A valid start bit is
identified by four consecutive internal SCICLK periods of zero bits as shown
in Figure 8−6. If any bit is not zero, then the processor starts over and begins
looking for another start bit.

For the bits following the start bit, the processor determines the bit value by
making three samples in the middle of the bits. These samples occur on the
fourth, fifth, and sixth SCICLK periods, and bit-value determination is on a
majority (two out of three) basis. Figure 8−6 illustrates the asynchronous
communication format for this with a start bit showing how edges are found and
where a majority vote is taken.

Since the receiver synchronizes itself to frames, the external transmitting and
receiving devices do not have to use a synchronized serial clock. The clock
can be generated locally.

Figure 8−6. SCI Asynchronous Communications Format

Falling edge Majority
detected vote
SC ICLK
(internal)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1

SCIRXD
Start bit LSB of data

8 SCICLK periods per data bit 8 SCICLK periods per data bit

Serial Communications Interface (SCI) 8-15

SCI Communication Format

8.4.1 Receiver Signals in Communication Modes

Figure 8−7 illustrates an example of receiver signal timing that assumes the
following conditions:

Address-bit wake-up mode (address bit does not appear in idle-line mode)

Six bits per character

Figure 8−7. SCI RX Signals in Communication Modes

RXENA
1 6

RXRDY
3 4
2 5

SCIRXD pin Start 0 1 2 3 4 5 Ad Pa Stop Start 0 1 2

Frame

Notes: 1) Flag bit RXENA (SCICTL1.0) goes high to enable the receiver.
2) Data arrives on the SCIRXD pin, start bit detected.
3) Data is shifted from RXSHF to the receiver buffer register (SCIRXBUF); an interrupt is requested. Flag bit RXRDY
(SCIRXST.6) goes high to signal that a new character has been received.
4) The program reads SCIRXBUF; flag RXRDY is automatically cleared.
5) The next byte of data arrives on the SCIRXD pin; the start bit is detected, then cleared.
6) Bit RXENA is brought low to disable the receiver. Data continues to be assembled in RXSHF but is not transferred
to the receiver buffer register.

8-16
 SCI Communication Format

8.4.2 Transmitter Signals in Communication Modes

Figure 8−8 illustrates an example of transmitter signal timing that assumes the
following conditions:

Address-bit wake-up mode (address bit does not appear in idle-line mode)

Three bits per character

Figure 8−8. SCI TX Signals in Communications Mode

TXENA
1 6

TXRDY
2 3 4
5
TX EMPTY

First Character Second Character 7

SCITXD pin Start 0 1 2 Ad Pa Stop Start 0 1 2 Ad Pa Stop

Frame Frame

Notes: 1) Bit TXENA (SCICTL1.1) goes high, enabling the transmitter to send data.
2) SCITXBUF is written to; thus, (1) the transmitter is no longer empty, and (2) TXRDY goes low.
3) The SCI transfers data to the shift register (TXSHF). The transmitter is ready for a second character (TXRDY goes
high), and it requests an interrupt (to enable an interrupt, bit TX INT ENA — SCICTL2.0 — must be set).
4) The program writes a second character to SCITXBUF after TXRDY goes high (item 3). (TXRDY goes low again after
the second character is written to SCITXBUF.)
5) Transmission of the first character is complete. Transfer of the second character to shift register TXSHF begins.
6) Bit TXENA goes low to disable the transmitter; the SCI finishes transmitting the current character.
7) Transmission of the second character is complete; transmitter is empty and ready for new character.

Serial Communications Interface (SCI) 8-17

SCI Port Interrupts

8.5 SCI Port Interrupts

The SCI’s receiver and transmitter can be interrupt controlled. The SCICTL2
register has one flag bit (TXRDY) that indicates active interrupt conditions, and
the SCIRXST register has two interrupt flag bits (RXRDY and BRKDT), plus
the RX ERROR interrupt flag which is a logical OR of the FE, OE and PE
conditions. The transmitter and receiver have separate interrupt-enable bits.
When not enabled, the interrupts are not asserted; however, the condition
flags remain active, reflecting transmission and receipt status.

The SCI has independent peripheral interrupt vectors for the receiver and
transmitter. Peripheral interrupt requests can be either high priority or low
priority. This is indicated by the priority bits which are output from the peripheral
to the PIE controller. SCI interrupts can be programmed to assert the high- or
low-priority levels by the SCIRX PRIORITY (SCIPRI.5) and SCITX PRIORITY
(SCIPRI.6) control bits. When both RX and TX interrupt requests are made at
the same priority level, the receiver always has higher priority than the
transmitter, reducing the possibility of receiver overrun.

The operation of peripheral interrupts is described in the Peripheral Interrupt

Expansion controller chapter of the device specification of which this SCI
chapter is a part.

If the RX/BK INT ENA bit (SCICTL2.1) is set, the receiver peripheral inter-
rupt request is asserted when one of the following events occurs:

 The SCI receives a complete frame and transfers the data in the
RXSHF register to the SCIRXBUF register. This action sets the
RXRDY flag (SCIRXST.6) and initiates an interrupt.
 A break detect condition occurs (the SCIRXD is low for ten bit periods
following a missing stop bit). This action sets the BRKDT flag bit
(SCIRXST.5) and initiates an interrupt.

If the TX INT ENA bit (SCICTL2.0) is set, the transmitter peripheral inter-
rupt request is asserted whenever the data in the SCITXBUF register is
transferred to the TXSHF register, indicating that the CPU can write to
SCITXBUF; this action sets the TXRDY flag bit (SCICTL2.7) and initiates
an interrupt.

Note:
Interrupt generation due to the RXRDY and BRKDT bits is controlled by the
RX/BK INT ENA bit (SCICTL2.1). Interrupt generation due to the RX ERROR
bit is controlled by the RX ERR INT ENA bit (SCICTL1.6).

8-18
 SCI Baud Rate Calculations

8.6 SCI Baud Rate Calculations

The internally generated serial clock is determined by the device clock
frequency (CLKOUT) and the baud- select registers. The SCI uses the 16-bit
value of the baud-select registers to select one of the 64K different serial clock
rates possible for a given device clock.

See the bit descriptions in section 8.7.3, Baud-Select Registers, on page 8-26
for the formula to use when calculating the SCI asynchronous baud.

Table 8−3 shows the baud-select values for common SCI bit rates.

Table 8−3. Asynchronous Baud Register Values for Common SCI Bit Rates
Device Clock Frequency, 40 MHz

Ideal Baud BRR Actual Baud % Error

2400 2082 (822h) 2400 0

4800 1040 (411h) 4803 0.06

9600 520 (208h) 9597 −0.03

19200 259 (103h) 19231 0.16

38400 129 (81h) 38462 0.16

Note: The maximum CLKOUT frequency for 240xA devices is 40 MHz.

Serial Communications Interface (SCI) 8-19

SCI Module Registers

8.7 SCI Module Registers

The functions of the SCI are software configurable. Sets of control bits,
organized into dedicated bytes, are programmed to initialize the desired SCI
communications format. This includes operating mode and protocol, baud
value, character length, even/odd parity or no parity, number of stop bits, and
interrupt priorities and enables. The SCI is controlled and accessed through
registers listed in Figure 8−9, and described in the sections that follow.

Figure 8−9. SCI Registers

Bit Number
Address Register Register
Mnemonic 7 6 5 4 3 2 1 0 Name
EVEN/ LOOP- ADDR/ Commu-
STOP PARITY SCI SCI SCI
7050h SCICCR ODD BACK IDLE nication
BITS ENABLE CHAR2 CHAR1 CHAR0
PARITY ENA MODE control

RX ERR SW SCI control

7051h SCICTL1 Reserved Reserved TXWAKE SLEEP TXENA RXENA
INT ENA RESET register1

BAUD15 Baud rate

7052h SCIHBAUD BAUD14 BAUD13 BAUD12 BAUD11 BAUD10 BAUD9 BAUD8
(MSB) (MSbyte)

BAUD0 Baud rate

7053h SCILBAUD BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1
(LSB) (LSbyte)

TX RX/BK TX SCI control

7054h SCICTL2 TXRDY Reserved
EMPTY INT ENA INT ENA register 2

RX Receiver
7055h SCIRXST RXRDY BRKDT FE OE PE RXWAKE Reserved
ERROR status

EMU data
7056h SCIRXEMU ERXDT7 ERXDT6 ERXDT5 ERXDT4 ERXDT3 ERXDT2 ERXDT1 ERXDT0
buffer

Receiver
7057h SCIRXBUF RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDT0
data buffer

7058h −−− Reserved −−−

Transmitter
7059h SCITXBUF TXDT7 TXDT7 TXDT5 TXDT4 TXDT3 TXDT2 TXDT1 TXDT0
data buffer

705Ah −−− Reserved −−−

705Bh −−− Reserved −−−

705Ch −−− Reserved −−−

705Dh −−− Reserved −−−

705Eh −−− Reserved −−−

SCITX SCIRX SCI SCI Priority

705Fh SCIPRI Reserved Reserved
PRIORITY PRIORITY SOFT FREE control

8-20
 SCI Module Registers

8.7.1 SCI Communication Control Register (SCICCR)

SCICCR defines the character format, protocol, and communications mode
used by the SCI.

Figure 8−10. SCI Communication Control Register (SCICCR) — Address 7050h

7 6 5 4 3 2 1 0

STOP EVEN/ODD PARITY LOOPBACK ADDR/IDLE

SCICHAR2 SCICHAR1 SCICHAR0
BITS PARITY ENABLE ENA MODE

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

Bit 7 STOP BITS. SCI number of stop bits.

This bit specifies the number of stop bits transmitted. The receiver checks for
only one stop bit.
0 One stop bit
1 Two stop bits

Bit 6 PARITY. SCI parity odd/even selection.

If the PARITY ENABLE bit (SCICCR.5) is set, PARITY (bit 6) designates odd
or even parity (odd or even number of bits with the value of 1 in both transmitted
and received characters).
0 Odd parity
1 Even parity

Bit 5 PARITY ENABLE. SCI parity enable.

This bit enables or disables the parity function. If the SCI is in the address-bit
multiprocessor mode (set using bit 3 of this register), the address bit is included
in the parity calculation (if parity is enabled). For characters of less than eight
bits, the remaining unused bits should be masked out of the parity calculation.
0 Parity disabled; no parity bit is generated during transmission or is
expected during reception
1 Parity is enabled

Bit 4 LOOP BACK ENA. Loop Back test mode enable.

This bit enables the Loop Back test mode where the Tx pin is internally
connected to the Rx pin.
0 Loop Back test mode disabled
1 Loop Back test mode enabled

Serial Communications Interface (SCI) 8-21

SCI Module Registers

Bit 3 ADDR/IDLE MODE. SCI multiprocessor mode control bit.

This bit selects one of the multiprocessor protocols

0 Idle-line mode protocol selected
1 Address-bit mode protocol selected

Multiprocessor communication is different from the other communication

modes because it uses SLEEP and TXWAKE functions (bits SCICTL1.2 and
SCICTL1.3, respectively). The idle-line mode is usually used for normal
communications because the address-bit mode adds an extra bit to the frame.
The idle-line mode does not add this extra bit and is compatible with RS-232
type communications.

Bits 2−0 SCI CHAR2−0. Character-length control bits 2 − 0.

These bits select the SCI character length from one to eight bits. Characters
of less than eight bits are right-justified in SCIRXBUF and SCIRXEMU and are
padded with leading zeros in SCIRXBUF. SCITXBUF doesn’t need to be
padded with leading zeros. Table 8−4 lists the bit values and character lengths
for SCI CHAR2-0 bits.

Table 8−4. SCI CHAR2−0 Bit Values and Character Lengths

SCI CHAR2−0 Bit Values (Binary)
SCI CHAR2 SCI CHAR1 SCI CHAR0 Character Length (Bits)
0 0 0 1

0 0 1 2

0 1 0 3

0 1 1 4

1 0 0 5

1 0 1 6

1 1 0 7

1 1 1 8

8-22
 SCI Module Registers

8.7.2 SCI Control Register 1 (SCICTL1)

SCICTL1 controls the receiver/transmitter enable, TXWAKE and SLEEP

functions, and the SCI software reset.

Figure 8−11.SCI Control Register 1 (SCICTL1) — Address 7051h

7 6 5 4 3 2 1 0

RX ERR SW
Reserved Reserved TXWAKE SLEEP TXENA RXENA
INT ENA RESET

R-0 RW-0 RW-0 R-0 RS-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, S = Set only, -0 = value after reset

Bit 7 Reserved. Reads return zero; writes have no effect.

Bit 6 RX ERR INT ENA. SCI receive error interrupt enable.

Setting this bit enables an interrupt if the RX ERROR bit (SCIRXST.7)

becomes set because of errors occurring.
0 Receive error interrupt disabled
1 Receive error interrupt enabled

Bit 5 SW RESET. SCI software reset (active low).

Writing a 0 to this bit initializes the SCI state machines and operating flags
(registers SCICTL2 and SCIRXST) to the reset condition.

The SW RESET bit does not affect any of the configuration bits.

All affected logic is held in the specified reset state until a 1 is written to
SW RESET (the bit values following a reset are shown beneath each register
diagram in this section). Thus, after a system reset, re-enable the SCI by
writing a 1 to this bit.

Clear this bit after a receiver break detect (BRKDT flag, bit SCIRXST.5).

SW RESET affects the operating flags of the SCI, but it neither affects the
configuration bits nor restores the reset values.

Once SW RESET is asserted, the flags are frozen until the bit is de-asserted.

Table 8−5 lists the affected flags.

Serial Communications Interface (SCI) 8-23

SCI Module Registers

Table 8−5. SW RESET-Affected Flags

SCI Flag Register.Bit Value After SW RESET

TXRDY SCICTL2.7 1

TX EMPTY SCICTL2.6 1

RXWAKE SCIRXST.1 0

PE SCIRXST.2 0

OE SCIRXST.3 0

FE SCIRXST.4 0

BRKDT SCIRXST.5 0

RXRDY SCIRXST.6 0

RX ERROR SCIRXST.7 0

Bit 4 Reserved. Reads return zero; writes have no effect.

Bit 3 TXWAKE. SCI transmitter wakeup method select.

The TXWAKE bit controls selection of the data-transmit feature, depending on

which transmit mode (idle-line or address-bit) is specified at the ADDR/IDLE
MODE bit (SCICCR.3)
0 Transmit feature is not selected
1 Transmit feature selected is dependent on the mode, idle-line or
address-bit:
In idle-line mode: write a 1 to TXWAKE, then write data to register
SCITXBUF to generate an idle period of 11 data bits
In address-bit mode: write a 1 to TXWAKE, then write data to
SCITXBUF to set the address bit for that frame to 1

TXWAKE is not cleared by the SW RESET bit (SCICTL1.5); it is cleared by a

system reset or the transfer of TXWAKE to the WUT flag.

Bit 2 SLEEP. SCI sleep.

In a multiprocessor configuration, this bit controls the receiver sleep function.

Clearing this bit brings the SCI out of the sleep mode.
0 Sleep mode disabled
1 Sleep mode enabled

8-24
 SCI Module Registers

The receiver still operates when the SLEEP bit is set; however, operation does
not update the receiver buffer ready bit (SCIRXST.6, RXRDY) or the error
status bits (SCIRXST.5−2: BRKDT, FE, OE, and PE) unless the address byte
is detected. SLEEP is not cleared when the address byte is detected.

Bit 1 TXENA. SCI transmitter enable.

Data is transmitted through the SCITXD pin only when TXENA is set. If reset,
transmission is halted but only after all data previously written to SCITXBUF
has been sent.
0 Transmitter disabled
1 Transmitter enabled

Bit 0 RXENA. SCI receiver enable.

Data is received on the SCIRXD pin and is sent to the receiver shift register
and then the receiver buffers. This bit enables or disables the receiver (transfer
to the buffers).
0 Prevent received characters from transfer into the SCIRXEMU and
SCIRXBUF receiver buffers
1 Send received characters to SCIRXEMU and SCIRXBUF

Clearing RXENA stops received characters from being transferred to the two
receiver buffers and also stops the generation of receiver interrupts. However,
the receiver shift register can continue to assemble characters. Thus, if
RXENA is set during the reception of a character, the complete character will
be transferred into the receiver buffer registers, SCIRXEMU and SCIRXBUF.

Serial Communications Interface (SCI) 8-25

SCI Module Registers

8.7.3 Baud-Select Registers (SCIHBAUD, SCILBAUD)

The values in SCIHBAUD and SCILBAUD specify the baud rate for the SCI.

Figure 8−12. Baud-Select MSbyte Register (SCIHBAUD) — Address 7052h

15 14 13 12 11 10 9 8

BAUD15
BAUD14 BAUD13 BAUD12 BAUD11 BAUD10 BAUD9 BAUD8
(MSB)

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, S = Set only, -0 = value after reset

Figure 8−13. Baud-Select LSbyte Register (SCILBAUD) — Address 7053h

7 6 5 4 3 2 1 0

BAUD0
BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1
(LSB)

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, S = Set only, -0 = value after reset

Bits 15−0 BAUD15−BAUD0. SCI 16-bit baud selection.

Registers SCIHBAUD (MSbyte) and SCILBAUD (LSbyte) are concatenated

to form a 16-bit baud value, BRR.

The internally-generated serial clock is determined by the CLKOUT signal and

the two baud-select registers. The SCI uses the 16-bit value of these registers
to select one of 64K serial clock rates for the communication modes.

The SCI baud rate is calculated using the following equation:

SCI Asynchronous Baud = CLKOUT

(BRR + 1) × 8

Alternatively,

BRR = CLKOUT − 1
SCI Asynchronous Baud × 8

Note that the above formulas are applicable only when 1 ≤ BRR ≤ 65535. If
BRR = 0, then

SCI Asynchronous Baud = CLKOUT

16
Where: BRR = the 16-bit value (in decimal) in the baud-select registers.

8-26
 SCI Module Registers

8.7.4 SCI Control Register 2 (SCICTL2)

SCICTL2 enables the receive-ready, break-detect, and transmit-ready
interrupts as well as transmitter-ready and -empty flags.

Figure 8−14. SCI Control Register 2 (SCICTL2) — Address 7054h

7 6 5−2 1 0
TXRDY TX EMPTY Reserved RX/BK INT ENA TX INT ENA
R-1 R-1 R-0 RW-0 RW-0
Note: R = Read access, W = Write access, -n = value after reset

Bit 7 TXRDY. Transmitter buffer register ready flag.

When set, this bit indicates that the transmit data buffer register, SCITXBUF,
is ready to receive another character. Writing data to the SCITXBUF
automatically clears this bit. When set, this flag asserts a transmitter interrupt
request if the interrupt-enable bit, TX INT ENA (SCICTL2.0), is also set.
TXRDY is set to 1 by enabling the SW RESET bit (SCICTL.2) or by a system
reset.
0 SCITXBUF is full
1 SCITXBUF is ready to receive the next character

Bit 6 TX EMPTY. Transmitter empty flag.

This flag’s value indicates the contents of the transmitter’s buffer register
(SCITXBUF) and shift register (TXSHF). An active SW RESET (SCICTL1.2),
or a system reset, sets this bit. This bit does not cause an interrupt request.
0 Transmitter buffer or shift register or both are loaded with data
1 Transmitter buffer and shift registers are both empty

Bits 5−2 Reserved.

Reads return zero; writes have no effect.

Bit 1 RX/BK INT ENA. Receiver-buffer/break interrupt enable.

This bit controls the interrupt request caused by either the RXRDY flag or the
BRKDT flag (bits SCIRXST.6 and .5) being set. However, RX/BK INT ENA
does not prevent the setting of these flags.
0 Disable RXRDY/BRKDT interrupt
1 Enable RXRDY/BRKDT interrupt

Bit 0 TX INT ENA. SCITXBUF-register interrupt enable.

This bit controls the interrupt request caused by setting the TXRDY flag bit
(SCICTL2.7). However, it does not prevent the TXRDY flag from being set
(being set indicates that register SCITXBUF is ready to receive another
character).

Serial Communications Interface (SCI) 8-27

SCI Module Registers

0 Disable TXRDY interrupt

1 Enable TXRDY interrupt

8.7.5 Receiver Status Register (SCIRXST)

SCIRXST contains seven bits that are receiver status flags (two of which can
generate interrupt requests). Each time a complete character is transferred to
the receiver buffers (SCIRXEMU and SCIRXBUF), the status flags are
updated. Figure 8−16 on page 8-30 shows the relationships between several
of the register’s bits.

Figure 8−15. Receiver Status Register (SCIRXST) — Address 7055h

7 6 5 4 3 2 1 0

RX
RXRDY BRKDT FE OE PE RXWAKE Reserved
ERROR

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

Note: R = Read access, W = Write access, -0 = value after reset

Bit 7 RX ERROR. SCI receiver-error flag.

The RX ERROR flag indicates that one of the error flags in the receiver status
register is set. RX ERROR is a logical OR of the break detect, framing error,
overrun, and parity error enable flags (bits 5−2: BRKDT, FE, OE, and PE).
0 No error flags set
1 Error flag(s) set
A 1 on this bit will cause an interrupt if the RX ERR INT ENA bit (SCICTL1.6)
is set. This bit can be used for fast error-condition checking during the interrupt
service routine. This error flag cannot be cleared directly; it is cleared by an
active SW RESET or by a system reset.

Bit 6 RXRDY. SCI receiver-ready flag.

When a new character is ready to be read from the SCIRXBUF register, the
receiver sets this bit, and a receiver interrupt is generated if the RX/BK INT
ENA bit (SCICTL2.1) is a 1. RXRDY is cleared by a reading of the SCIRXBUF
register, by an active SW RESET, or by a system reset.
0 No new character in SCIRXBUF
1 Character ready to be read from SCIRXBUF
Bit 5 BRKDT. SCI break-detect flag.
The SCI sets this bit when a break condition occurs. A break condition occurs
when the SCI receiver data line (SCIRXD) remains continuously low for at

8-28
 SCI Module Registers

least ten bits, beginning after a missing first stop bit. The occurrence of a break
causes a receiver interrupt to be generated if the RX/BK INT ENA bit is a 1,
but it does not cause the receiver buffer to be loaded. A BRKDT interrupt can
occur even if the receiver SLEEP bit is set to 1. BRKDT is cleared by an active
SW RESET or by a system reset. It is not cleared by receipt of a character after
the break is detected. In order to receive more characters, the SCI must be
reset by toggling the SW RESET bit or by a system reset.
0 No break condition
1 Break condition occurred

Bit 4 FE. SCI framing-error flag.

The SCI sets this bit when an expected stop bit is not found. Only the first stop
bit is checked. The missing stop bit indicates that synchronization with the start
bit has been lost and that the character is incorrectly framed. The FE bit is reset
by a clearing of the SW RESET bit or by a system reset.
0 No framing error detected
1 Framing error detected

Bit 3 OE. SCI overrun-error flag.

The SCI sets this bit when a character is transferred into registers SCIRXEMU
and SCIRXBUF before the previous character is fully read by the CPU. The
previous character is overwritten and lost. The OE flag bit is reset by an active
SW RESET or by a system reset.
0 No overrun error detected
1 Overrun error detected

Bit 2 PE. SCI parity-error flag.

This flag bit is set when a character is received with a mismatch between the
number of 1s and its parity bit. The address bit is included in the calculation.
If parity generation and detection is not enabled, the PE flag is disabled and
read as 0. The PE bit is reset by an active SW RESET or a system reset.
0 No parity error or parity is disabled
1 Parity error is detected

Serial Communications Interface (SCI) 8-29

SCI Module Registers

Bit 1 RXWAKE. Receiver wakeup-detect flag.

A value of 1 in this bit indicates detection of a receiver wakeup condition. In
the address-bit multiprocessor mode (SCICCR.3 = 1), RXWAKE reflects the
value of the address bit for the character contained in SCIRXBUF. In the
idle-line multiprocessor mode, RXWAKE is set if the SCIRXD data line is
detected as idle. RXWAKE is a read-only flag, cleared by one of the following:

The transfer of the first byte after the address byte to SCIRXBUF

The reading of SCIRXBUF

An active SW RESET

A system reset

Bit 0 Reserved. Reads return zero; writes have no effect.

Figure 8−16. Register SCIRXST Bit Associations — Address 7055h

7 6 5 4 3 2 1 0

RX ERROR RXRDY BRKDT FE OE PE RXWAKE Reserved

RXRDY or BRKDT causes an interrupt

if RX/BK INT ENA (SCICTL2.1) = 1

RX ERROR = 1 when any of bits 5 through 2 is a 1 value

8.7.6 Receiver Data Buffer Registers (SCIRXEMU, SCIRXBUF)

Received data is transferred from RXSHF to SCIRXEMU and SCIRXBUF.
When the transfer is complete, the RXRDY flag (bit SCIRXST.6) is set,
indicating that the received data is ready to be read. Both registers contain the
same data; they have separate addresses but are not physically separate
buffers. The only difference is that reading SCIRXEMU does not clear the
RXRDY flag; however, reading SCIRXBUF clears the flag.

8.7.6.1 Emulation Data Buffer

Normal SCI data-receive operations read the data received from the
SCIRXBUF register. The SCIRXEMU register is used principally by the
emulator (EMU) because it can continuously read the data received for screen
updates without clearing the RXRDY flag. SCIRXEMU is cleared by a system
reset.

This is the register which should be used in an emulator watch window to view
the contents of SCIRXBUF register.

8-30
 SCI Module Registers

SCIRXEMU is not physically implemented, it is just a different address location

to access the SCIRXBUF register without clearing the RXRDY flag.

Figure 8−17. Emulation Data Buffer Register (SCIRXEMU) — Address 7056h

7 6 5 4 3 2 1 0

ERXDT7 ERXDT6 ERXDT5 ERXDT4 ERXDT3 ERXDT2 ERXDT1 ERXDT0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

Note: R = Read access, -0 = value after reset

8.7.6.2 Receiver Data Buffer (SCIRXBUF)

When the current data received is shifted from RXSHF to the receiver buffer,
flag bit RXRDY is set and the data is ready to be read. If the RX/BK INT ENA
bit (SCICTL2.1) is set, this shift also causes an interrupt. When SCIRXBUF is
read, the RXRDY flag is reset. SCIRXBUF is cleared by a system reset.

Figure 8−18. Receiver Data Buffer (SCIRXBUF) — Address 7057h

7 6 5 4 3 2 1 0

RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDT0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

Note: R = Read access, -0 = value after reset

8.7.7 Transmit Data Buffer Register (SCITXBUF)

Data bits to be transmitted are written to SCITXBUF. These bits must be

right-justified because the leftmost bits are ignored for characters less than
eight bits long. The transfer of data from this register to the TXSHF transmitter
shift register sets the TXRDY flag (SCICTL2.7), indicating that SCITXBUF is
ready to receive another set of data. If bit TX INT ENA (SCICTL2.0) is set, this
data transfer also causes an interrupt.

Figure 8−19. Transmit Data Buffer Register (SCITXBUF) — Address 7059h

7 6 5 4 3 2 1 0

TXDT7 TXDT6 TXDT5 TXDT4 TXDT3 TXDT2 TXDT1 TXDT0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

Serial Communications Interface (SCI) 8-31

SCI Module Registers

8.7.8 Priority Control Register (SCIPRI)

SCIPRI contains the receiver and transmitter interrupt priority select bits and
controls the SCI operation on the XDS emulator during a program-suspend
event, such as hitting a breakpoint.

Figure 8−20. SCI Priority Control Register (SCIPRI) — Address 705Fh

7 6 5 4 3 2−0

SCITX SCIRX
Reserved SCI SOFT SCI FREE Reserved
PRIORITY PRIORITY

R-0 RW-0 RW-0 RW-0 RW-0 R-0

Note: R = Read access, W = Write access, -0 = value after reset

Bit 7 Reserved. Reads return zero; writes have no effect.

Bit 6 SCITX PRIORITY. SCI transmitter interrupt priority select. This bit specifies
the priority level of the SCI transmitter interrupts.
0 Interrupts are high-priority requests
1 Interrupts are low-priority requests

Bit 5 SCIRX PRIORITY. SCI receiver interrupt priority select. This bit specifies the
priority level of the SCI receiver interrupts.
0 Interrupts are high-priority requests
1 Interrupts are low-priority requests

Bits 4,3 SCI SOFT and FREE bits. These bits determine what occurs when an emula-
tion suspend event occurs (for example, when the debugger hits a breakpoint).
The peripheral can continue whatever it is doing (free-run mode), or if in stop
mode, it can either stop immediately or stop when the current operation (the
current receive/transmit sequence) is complete.
Bit 4 Bit 3
SOFT FREE
0 0 Immediate stop on suspend
1 0 Complete current receive/transmit sequence before
stopping
X 1 Free run. Continues SCI operation regardless of suspend

Bits 2−0 Reserved. Reads return zero; writes have no effect.

8-32
 Chapter 9

 $    ($)

The serial peripheral interface (SPI) is a high-speed synchronous serial

input/output (I/O) port that allows a serial bit stream of programmed length
(one to sixteen bits) to be shifted into and out of the device at a programmed
bit-transfer rate. The SPI is normally used for communications between the
DSP controller and external peripherals or another controller. Typical
applications include external I/O or peripheral expansion via devices such as
shift registers, display drivers, and analog-to-digital converters (ADCs).

Most SPI registers are eight bits in width (except for the data registers), a
carryover from the 8-bit version of the SPI on the TMS320C240 device. The
upper 8 bits return zeros when read.

Topic Page

9.1 C240 SPI vs. LF/LC240xA SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.2 Overview of SPI Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.3 SPI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9.4 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.5 SPI Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
9.6 SPI Example Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30

9-1
C240 SPI vs. LF/LC240xA SPI

9.1 C240 SPI vs. LF/LC240xA SPI

This SPI has 16-bit transmit and receive capability, with double-buffered
transmit and double-buffered receive. All data registers are 16-bits wide.

The SPI is no longer limited to a maximum transmission rate of CLKOUT / 8

in slave mode. The maximum transmission rate in both slave mode and master
mode is now CLKOUT / 4.

Note that there is a software change required since writes of transmit data to
the serial data register, SPIDAT (and the new transmit buffer, SPITXBUF),
must be left-justified. On the C240, these writes had to be left-justified within
an 8-bit register. Now they must be left-justified within a 16-bit register.

The control and data bits for general-purpose bit I/O multiplexing have been
removed from this peripheral, along with the associated registers, SPIPC1
(704Dh) and SPIPC2 (704Eh). These bits are now in the General-Purpose I/O
registers.

The polarity of the SPI SW RESET bit in 240xA is the opposite of the 240 SPI.

9.1.1 SPI Physical Description

The SPI module, as shown in Figure 9−1, consists of:

Four I/O pins:

 SPISIMO (SPI slave in, master out)

 SPISOMI (SPI slave out, master in)
 SPICLK (SPI clock)
 SPISTE (SPI slave transmit enable)

Master and slave mode operations

SPI serial receive buffer register (SPIRXBUF)

This buffer register contains the data that is received from the network and
that is ready for the CPU to read

SPI serial transmit buffer register (SPITXBUF)

This buffer register contains the next character to be transmitted when the
current transmit has completed

SPI serial data register (SPIDAT).

This data shift register serves as the transmit/receive shift register

SPICLK phase and polarity control

9-2
 C240 SPI vs. LF/LC240xA SPI

State control logic

Memory-mapped control and status registers

The basic function of the strobe (SPISTE) pin is to act as a transmit enable
input for the SPI module in slave mode. It stops the shift register so it cannot
receive data and puts the SPISOMI pin in the high-impedance state.

Serial Peripheral Interface (SPI) 9-3

C240 SPI vs. LF/LC240xA SPI

Figure 9−1. SPI Module Block Diagram

SPIFFENA
Receiver Overrun
SPIFFTX.14 Overrun Flag INT ENA

RX FIFO registers SPISTS.7

SPICTL.4
SPIRXBUF
RX FIFO _0
RX FIFO _1
SPINT / SPIRXINT
−−−−−
RX FIFO _15
RX FIFO Interrupt
RX Interrupt
Logic
16

SPIRXBUF SPIFFOVF FLAG

Buffer Register
SPIFFRX.15 To CPU
TX FIFO registers
SPITXBUF
TX FIFO _15 TX Interrupt
−−−−− TX FIFO Interrupt Logic
TX FIFO _1
TX FIFO _0 SPITX / SPITXINT
16 SPI INT
SPI INT FLAG ENA
SPITXBUF SPISTS.6
16 Buffer Register
SPICTL.0

16

M M

SPIDAT S
Data Register S SW1 SPISIMO

M M
SPIDAT.15 − 0
S
S SW2 SPISOMI
Talk
SPICTL.1
SPISTE†
*

State Control
Master/Slave
SPI Char SPICCR.3 − 0 SPICTL.2
S
3 2 1 0 SW3
Clock Clock
SPI Bit Rate M S Polarity Phase
LSPCLK SPIBRR.6 − 0 SPICCR.6 SPICTL.3 SPICLK
M
6 5 4 3 2 1 0

† SPISTE of a slave device is driven low by the master.

9-4
 Overview of SPI Module Registers

9.2 Overview of SPI Module Registers

Nine registers inside the SPI module (listed in Table 9−1) control the SPI
operations:

SPICCR (SPI configuration control register). Contains control bits used for
SPI configuration
 SPI module software reset
 SPICLK polarity selection
 Four SPI character-length control bits

SPICTL (SPI operation control register). Contains control bits for data
transmission
 Two SPI interrupt enable bits
 SPICLK phase selection
 Operational mode (master/slave)
 Data transmission enable

SPISTS (SPI status register). Contains two receive buffer status bits and
one transmit buffer status bit
 RECEIVER OVERRUN
 SPI INT FLAG
 TX BUF FULL FLAG

SPIBRR (SPI baud rate register). Contains seven bits that determine the
bit transfer rate

SPIRXEMU (SPI receive emulation buffer register). Contains the received

data. This register is used for emulation purposes only. The SPIRXBUF
should be used for normal operation

SPIRXBUF (SPI receive buffer — the serial receive buffer register). Con-
tains the received data

SPITXBUF (SPI transmit buffer — the serial transmit buffer register). Con-
tains the next character to be transmitted

Serial Peripheral Interface (SPI) 9-5

Overview of SPI Module Registers

SPIDAT (SPI data register). Contains data to be transmitted by the SPI,

acting as the transmit/receive shift register. Data written to SPIDAT is
shifted out on subsequent SPICLK cycles. For every bit shifted out of the
SPI, a bit from the receive bit stream is shifted into the other end of the shift
register

SPIPRI (SPI priority register). Contains bits that specify interrupt priority
and determine SPI operation on the XDS emulator during program sus-
pensions

Table 9−1. Addresses of SPI Registers

Address Register Name

7040h SPICCR SPI configuration control register

7041h SPICTL SPI operation control register

7042h SPISTS SPI status register

7043h Reserved

7044h SPIBRR SPI baud rate register

7045h Reserved

7046h SPIRXEMU SPI receive emulation buffer register

7047h SPIRXBUF SPI serial receive buffer register

7048h SPITXBUF SPI serial transmit buffer register

7049h SPIDAT SPI serial data register

704Ah Reserved

704Bh Reserved

704Ch Reserved

704Dh Reserved

704Eh Reserved

704Fh SPIPRI SPI priority control register

9-6
 SPI Operation

9.3 SPI Operation

This section describes the operation of the SPI. Included are explanations of
the operation modes, interrupts, data format, clock sources, and initialization.
Typical timing diagrams for data transfers are given.

9.3.1 Introduction to Operation

Figure 9−2 shows typical connections of the SPI for communications between
two controllers: a master and a slave.

The master initiates data transfer by sending the SPICLK signal. For both the
slave and the master, data is shifted out of the shift registers on one edge of
the SPICLK and latched into the shift register on the opposite SPICLK clock
edge. If the CLOCK PHASE bit (SPICTL.3) is high, data is transmitted and
received a half-cycle before the SPICLK transition (see section 9.3.2, SPI
Module Slave and Master Operation Modes, on page 9-8). As a result, both
controllers send and receive data simultaneously. The application software
determines whether the data is meaningful or dummy data. There are three
possible methods for data transmission:

Master sends data; slave sends dummy data.

Master sends data; slave sends data.

Master sends dummy data; slave sends data.

The master can initiate data transfer at any time because it controls the
SPICLK signal. The software, however, determines how the master detects
when the slave is ready to broadcast data.

Serial Peripheral Interface (SPI) 9-7

SPI Operation

Figure 9−2. SPI Master/Slave Connection

SPI master (master/slave = 1) SPI slave (master/slave = 0)

Slave in/
SPIRXBUF.15−0 SPISIMO master out SPISIMO SPIRXBUF.15−0
Serial input buffer Serial input buffer
SPIRXBUF SPIRXBUF

SPI
SPISTE SPISTE
strobe
SPIDAT.15−0 SPIDAT.15−0
Shift register SPISOMI Slave out/ SPISOMI Shift register
MSB
(SPIDAT) LSB master in
MSB
(SPIDAT) LSB

Serial
SPICLK SPICLK
clock
SPITXBUF.15−0 SPITXBUF.15−0
Serial transmit buffer Serial transmit buffer
SPITXBUF SPITXBUF

Processor 1 Processor 2

9.3.2 SPI Module Slave and Master Operation Modes

The SPI can operate in master or slave mode. The MASTER/SLAVE bit
(SPICTL.2) selects the operating mode and the source of the SPICLK signal.

Master Mode
In the master mode (MASTER/SLAVE = 1), the SPI provides the serial clock
on the SPICLK pin for the entire serial communications network. Data is output
on the SPISIMO pin and latched from the SPISOMI pin.
The SPIBRR register determines both the transmit and receive bit transfer rate
for the network. SPIBRR can select 126 different data transfer rates.
Data written to SPIDAT or SPITXBUF initiates data transmission on the
SPISIMO pin, MSB (most significant bit) first. Simultaneously, received data
is shifted through the SPISOMI pin into the LSB (least significant bit) of
SPIDAT. When the selected number of bits has been transmitted, the received
data is transferred to the SPIRXBUF (buffered receiver) for the CPU to read.
Data is stored right-justified in SPIRXBUF.
When the specified number of data bits has been shifted through SPIDAT, the
following events occur:

SPIDAT contents are transferred to SPIRXBUF.

SPI INT FLAG bit (SPISTS.6) is set to 1.

9-8
 SPI Operation

If there is valid data in the transmit buffer SPITXBUF, as indicated by the

TXBUF FULL bit in SPISTS, this data is transferred to SPIDAT and is
transmitted; otherwise, SPICLK stops after all bits have been shifted out
of SPIDAT.

If the SPI INT ENA bit (SPICTL.0) is set to 1, an interrupt is asserted.

In a typical application, the SPISTE pin serves as a chip-enable pin for a slave
SPI device and drives this pin high again after transmitting the master data.
This pin is driven low by the master before transmitting data to the slave and
is taken high after the transmission is complete.

Slave Mode
In the slave mode (MASTER/SLAVE = 0), data shifts out on the SPISOMI pin
and in on the SPISIMO pin. The SPICLK pin is used as the input for the serial
shift clock, which is supplied from the external network master. The transfer
rate is defined by this clock. The SPICLK input frequency should be no greater
than the CLKOUT frequency divided by 4.
Data written to SPIDAT or SPITXBUF is transmitted to the network when
appropriate edges of the SPICLK signal are received from the network master.
Data written to the SPITXBUF register will be transferred to the SPIDAT
register when all bits of the character to be transmitted have been shifted out
of SPIDAT. If no character is currently being transmitted when SPITXBUF is
written to, the data will be transferred immediately to SPIDAT. To receive data,
the SPI waits for the network master to send the SPICLK signal and then shifts
the data on the SPISIMO pin into SPIDAT. If data is to be transmitted by the
slave simultaneously, and SPITXBUF has not been previously loaded, the
data must be written to SPITXBUF or SPIDAT before the beginning of the
SPICLK signal.
When the TALK bit (SPICTL.1) is cleared, data transmission is disabled, and
the output line (SPISOMI) is put into the high-impedance state. If this occurs
while a transmission is active, the current character is completely transmitted
even though SPISOMI is forced into the high-impedance state. This ensures
that the SPI is still able to receive incomming data correctly. This TALK bit
allows many slave devices to be tied together on the network, but only one
slave at a time is allowed to drive the SPISOMI line.
The SPISTE pin operates as the slave-select pin. An active-low signal on the
SPISTE pin allows the slave SPI to transfer data to the serial data line; an
inactive-high signal causes the slave SPI’s serial shift register to stop and its
serial output pin to be put into the high-impedance state. This allows many
slave devices to be tied together on the network, although only one slave
device is selected at a time.

Serial Peripheral Interface (SPI) 9-9

SPI Interrupts

9.4 SPI Interrupts

9.4.1 SPI Interrupt Control Bits

Five control bits are used to initialize the SPI’s interrupts:

SPI INT ENA bit (SPICTL.0)

SPI INT FLAG bit (SPISTS.6)

OVERRUN INT ENA bit (SPICTL.4)

RECEIVER OVERRUN FLAG bit (SPISTS.7)

SPI PRIORITY bit (SPIPRI.6)

9.4.1.1 SPI INT ENA Bit (SPICTL.0)

When the SPI interrupt-enable bit is set and an interrupt condition occurs, the
corresponding interrupt is asserted.
0 Disable SPI interrupts
1 Enable SPI interrupts

9.4.1.2 SPI INT FLAG Bit (SPISTS.6)

This status flag indicates that a character has been placed in the SPI receiver
buffer and is ready to be read.

When a complete character has been shifted into or out of SPIDAT, the SPI INT
FLAG bit (SPISTS.6) is set, and an interrupt is generated if enabled by the SPI
INT ENA bit (SPICTL.0). The interrupt flag remains set until it is cleared by one
of the following events:

The interrupt is acknowledged (this is different from the C240).

The CPU reads the SPIRXBUF (reading the SPIRXEMU does not clear
the SPI INT FLAG bit).

The device enters IDLE2 or HALT mode with an IDLE instruction.

Software clears the SPI SW RESET bit (SPICCR.7).

A system reset occurs.

When the SPI INT FLAG bit is set, a character has been placed into the
SPIRXBUF and is ready to be read. If the CPU does not read the character by
the time the next complete character has been received, the new character is

9-10
 SPI Interrupts

written into SPIRXBUF, and the RECEIVER OVERRUN Flag bit (SPISTS.7)
is set.

9.4.1.3 OVERRUN INT ENA Bit (SPICTL.4)

Setting the overrun interrupt enable bit allows the assertion of an interrupt
whenever the RECEIVER OVERRUN Flag bit (SPISTS.7) is set by hardware.
Interrupts generated by SPISTS.7 and by the SPI INT FLAG bit (SPISTS.6)
share the same interrupt vector.
0 Disable RECEIVER OVERRUN Flag bit interrupts
1 Enable RECEIVER OVERRUN Flag bit interrupts

9.4.1.4 RECEIVER OVERRUN FLAG Bit (SPISTS.7)

The RECEIVER OVERRUN Flag bit is set whenever a new character is

received and loaded into the SPIRXBUF before the previously received
character has been read from the SPIRXBUF. The RECEIVER OVERRUN
Flag bit must be cleared by software.

9.4.1.5 SPI PRIORITY Bit (SPIPRI.6)

The value of the SPI PRIORITY bit determines the priority of the interrupt
request from the SPI.
0 Interrupts are high-priority requests
1 Interrupts are low-priority requests

9.4.2 Data Format

Four bits (SPICCR.3–0) specify the number of bits (1 to 16) in the data
character. This information directs the state control logic to count the number
of bits received or transmitted to determine when a complete character has
been processed. The following statements apply to characters with fewer than
16 bits:

Data must be left-justified when written to SPIDAT and SPITXBUF.

Data read back from SPIRXBUF is right-justified.

SPIRXBUF contains the most recently received character, right-justified,

plus any bits that remain from previous transmission(s) that have been
shifted to the left (shown in Example 9−1).

Serial Peripheral Interface (SPI) 9-11

SPI Interrupts

Example 9−1. Transmission of Bit from SPIRXBUF

Conditions:
1) Transmission character length = 1 bit (specified in bits SPICCR.3−0)
2) The current value of SPIDAT = 737Bh

SPIDAT (before transmission)

0 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1

SPIDAT (after transmission)

(TXed) 0 ← 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 x ← (RXed)

SPIRXBUF (after transmission)

1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 x

Note: x = 1 if SPISOMI data is high; x = 0 if SPISOMI data is low; master mode is assumed.

9.4.3 Baud Rate and Clocking Schemes

The SPI module supports 125 different baud rates and four different clock
schemes. Depending on whether the SPI clock is in slave or master mode, the
SPICLK pin can receive an external SPI clock signal or provide the SPI clock
signal, respectively.

In the slave mode, the SPI clock is received on the SPICLK pin from the
external source, and can be no greater than the CLKOUT frequency
divided by 4.

In the master mode, the SPI clock is generated by the SPI and is output
on the SPICLK pin, and can be no greater than the CLKOUT frequency
divided by 4.

Baud Rate Determination

Equation 9−1 shows how to determine the SPI baud rates.

Equation 9−1. SPI Baud-Rate Calculations

For SPIBRR = 3 to 127:

SPI Baud Rate = CLKOUT

(SPIBRR + 1)

9-12
 SPI Interrupts

For SPIBRR = 0, 1, or 2:

SPI Baud Rate = CLKOUT

4

where:

CLKOUT = CPU clock frequency of the device

SPIBRR = Contents of the SPIBRR in the master SPI device

To determine what value to load into SPIBRR, you must know the device
system clock (CLKOUT) frequency (which is device-specific) and the baud
rate at which you will be operating.

Example 9−2 shows how to determine the maximum baud rate at which a
240xA can communicate. Assume that CLKOUT = 40 MHz.

Example 9−2. Maximum Baud-Rate Calculation

Maximum SPI Baud Rate = CLKOUT
4
40 × 10 6
=
4
= 10 ×10 6 bps

9.4.4 SPI Clocking Schemes

The CLOCK POLARITY bit (SPICCR.6) and the CLOCK PHASE bit
(SPICTL.3) control four different clocking schemes on the SPICLK pin. The
CLOCK POLARITY bit selects the active edge, either rising or falling, of the
clock. The CLOCK PHASE bit selects a half-cycle delay of the clock. The four
different clocking schemes are as follows:

Falling Edge Without Delay. The SPI transmits data on the falling edge of
the SPICLK and receives data on the rising edge of the SPICLK.

Falling Edge With Delay. The SPI transmits data one half-cycle ahead of
the falling edge of the SPICLK signal and receives data on the falling edge
of the SPICLK signal.

Rising Edge Without Delay. The SPI transmits data on the rising edge of
the SPICLK signal and receives data on the falling edge of the SPICLK sig-
nal.

Rising Edge With Delay. The SPI transmits data one half-cycle ahead of
the rising edge of the SPICLK signal and receives data on the rising edge
of the SPICLK signal.

Serial Peripheral Interface (SPI) 9-13

SPI Interrupts

The selection procedure for the SPI clocking scheme is shown in Table 9−2.
Examples of these four clocking schemes relative to transmitted and received
data are shown in Figure 9−3.

Table 9−2. SPI Clocking Scheme Selection Guide

CLOCK POLARITY CLOCK PHASE

SPICLK Scheme (SPICCR.6) (SPICTL.3)

Rising edge without delay 0 0

Rising edge with delay 0 1

Falling edge without delay 1 0

Falling edge with delay 1 1

Figure 9−3. SPICLK Signal Options

SPICLK cycle 1 2 3 4 5 6 7 8
number
SPICLK
(Rising edge
without delay)

SPICLK
(Rising edge
with delay)

SPICLK
(Falling edge
without delay)
SPICLK
(Falling edge
with delay)

SPISIMO/ See note MSB LSB

SPISOMI

SPISTE
(Into slave)

Receive latch
points

Note: Previous data bit

9-14
 SPI Interrupts

For the SPI, SPICLK symmetry is retained only when the result of (SPIBRR+1)
is an even value. When (SPIBRR + 1) is an odd value and SPIBRR is greater
than 3, SPICLK becomes asymmetrical. The low pulse of SPICLK is one
CLKOUT longer than the high pulse when the CLOCK POLARITY bit is
clear (0). When the CLOCK POLARITY bit is set to 1, the high pulse of the
SPICLK is one CLKOUT longer than the low pulse, as shown in Figure 9−4.

Figure 9−4. SPI: SPICLK-CLKOUT Characteristic when (BRR + 1) is Odd, BRR > 3, and
CLOCK POLARITY = 1
2 cycles 3 cycles 2 cycles
CLKOUT

SPICLK

9.4.5 Initialization Upon Reset

A system reset forces the SPI peripheral module into the following default
configuration:

Unit is configured as a slave module (MASTER/SLAVE = 0)

Transmit capability is disabled (TALK = 0)

Data is latched at the input on the falling edge of the SPICLK signal

Character length is assumed to be one bit

SPI interrupts are disabled

Data in SPIDAT is reset to 0000h

SPI module pin functions are selected as general-purpose inputs (this is
done in I/O Mux control register B [MCRB])

To change this SPI configuration:

1) Clear the SPI SW RESET bit (SPICCR.7) to 0 to force the SPI to the reset
state.

2) Initialize the SPI configuration, format, baud rate, and pin functions as de-
sired.

3) Set the SPI SW RESET bit to 1 to release the SPI from the reset state.

4) Write to SPIDAT or SPITXBUF (this initiates the communication process

in the master).

5) Read SPIRXBUF after the data transmission has completed

(SPISTS.6 = 1) to determine what data was received.

Serial Peripheral Interface (SPI) 9-15

SPI Interrupts

9.4.5.1 Proper SPI Initialization Using the SPI SW RESET Bit

To prevent unwanted and unforeseen events from occurring during or as a

result of initialization changes, clear the SPI SW RESET bit (SPICCR.7) before
making initialization changes, and then set this bit after initialization is
complete.

Note:
Do not change SPI configuration when communication is in progress.

9.4.6 Data Transfer Example

The timing diagram, shown in Figure 9−5, illustrates an SPI data transfer
between two devices using a character length of five bits with the SPICLK
being symmetrical.

The timing diagram with SPICLK unsymmetrical (Figure 9−4) shares similar
characterizations with Figure 9−5 except that the data transfer is one CLKOUT
cycle longer per bit during the low pulse (CLOCK POLARITY = 0) or during the
high pulse (CLOCK POLARITY = 1) of the SPICLK.

Figure 9−5, Five Bits per Character, is applicable for 8-bit SPI only and is not
for 24x devices that are capable of working with 16-bit data. The figure is
shown for illustrative purposes only.

9-16
 SPI Interrupts

Figure 9−5. Five Bits per Character

Master SPI
Int flag
Slave SPI
Int flag
A B C D E F G H I J K
SPISOMI
from slave
7 6 5 4 3 7 6 5 4 3
SPISIMO
from master

SPICLK signal options:

7 6 5 4 3 7 6 5 4 3
CLOCK POLARITY = 0
CLOCK PHASE = 0

CLOCK POLARITY = 0
CLOCK PHASE = 1

CLOCK POLARITY = 1
CLOCK PHASE = 0

CLOCK POLARITY = 1
CLOCK PHASE = 1

SPISTE

A. Slave writes 0D0h to SPIDAT and waits for the master to shift out the data.
B. Master sets the slave SPISTE signal low (active).
C. Master writes 058h to SPIDAT, which starts the transmission procedure.
D. First byte is finished and sets the interrupt flags.
E. Slave reads 0Bh from its SPIRXBUF (right-justified).
F Slave writes 04Ch to SPIDAT and waits for the master to shift out the data.
G. Master writes 06Ch to SPIDAT, which starts the transmission procedure.
H. Master reads 01Ah from the SPIRXBUF (right−justified).
I. Second byte is finished and sets the interrupt flags.
J. Master reads 89h and the slave reads 8Dh from their respective SPIRXBUF. After the user’s software masks off the
unused bits, the master receives 09h and the slave receives 0Dh.
K. Master clears the slave SPISTE signal high (inactive).

Serial Peripheral Interface (SPI) 9-17

SPI Module Registers

9.5 SPI Module Registers

The SPI is controlled and accessed through registers in the control register file.
Figure 9−6 lists the SPI control registers and bit numbers.

Figure 9−6. SPI Module Registers

Register Bit number
Addr.
Name 15−8 7 6 5 4 3 2 1 0
SPI SW CLOCK SPI SPI SPI SPI
7040h SPICCR − −
RESET POLARITY CHAR3 CHAR2 CHAR1 CHAR0
OVER-
RUN CLOCK MASTER/ SPI INT
7041h SPICTL − − TALK
INT PHASE SLAVE ENA
ENA
RECEIVER TXBUF
SPI INT
7042h SPISTS − OVERRUN FULL −
FLAG
FLAG FLAG
7043h − − −
SPI BIT SPI BIT SPI BIT SPI BIT SPI BIT SPI BIT SPI BIT
7044h SPIBRR − −
RATE 6 RATE 5 RATE 4 RATE 3 RATE 2 RATE 1 RATE 0
7045h − − −
ERXB
7046h SPIRXEMU ERXB7 ERXB6 ERXB5 ERXB4 ERXB3 ERXB2 ERXB1 ERXB0
15−8
RXB
7047h SPIRXBUF RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0
15−8
TXB
7048h SPITXBUF TXB7 TXB6 TXB5 TXB4 TXB3 TXB2 TXB1 TXB0
15−8
SDAT
7049h SPIDAT SDAT7 SDAT6 SDAT5 SDAT4 SDAT3 SDAT2 SDAT1 SDAT0
15−8
704Ah − − −
704Bh − − −
704Ch − − −
704Dh − − −
704Eh − − −
SPI SPI
SPI
704Fh SPIPRI − − SUSP SUSP −
PRIORITY
SOFT FREE

− illegal

9-18
 SPI Module Registers

9.5.1 SPI Configuration Control Register (SPICCR)

SPICCR controls the setup of the SPI for operation.

Figure 9−7. SPI Configuration Control Register (SPICCR) — Address 7040h

7 6 5−4 3 2 1 0

SPI SW CLOCK
Reserved SPI CHAR3 SPI CHAR2 SPI CHAR1 SPI CHAR0
RESET POLARITY

RW-0 RW-0 R-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

Bit 7 SPI SW RESET. SPI Software Reset. When changing configuration, you
should clear this bit before the changes and set this bit before resuming opera-
tion. (See Section 9.4.5.1 on page 9-16.)
0 Initializes the SPI operating flags to the reset condition.
Specifically, the RECEIVER OVERRUN Flag bit (SPISTS.7), the
SPI INT FLAG bit (SPISTS.6), and the TXBUF FULL Flag bit
(SPISTS.5) are cleared. The SPI configuration remains un-
changed. If the module is operating as a master, the SPICLK sig-
nal output returns to its inactive level.
1 SPI is ready to transmit or receive the next character.
When the SPI SW RESET bit is a 0, a character written to the
transmitter will not be shifted out when this bit is set. A new char-
acter must be written to the serial data register.

Bit 6 CLOCK POLARITY. Shift Clock Polarity. This bit controls the polarity of the
SPICLK signal. CLOCK POLARITY and CLOCK PHASE (SPICTL.3) control
four clocking schemes on the SPICLK pin. See Section 9.4.4, SPI Clocking
Schemes, on page 9-13.
0 Data is output on rising edge and input on falling edge. When no
SPI data is sent, SPICLK is at low level.
The data input and output edges depend on the value of the
CLOCK PHASE bit (SPICTL.3) as follows:

CLOCK PHASE = 0: Data is output on the rising edge of the
SPICLK signal; input data is latched on the falling edge of the
SPICLK signal.

CLOCK PHASE = 1: Data is output one half-cycle before the first
rising edge of the SPICLK signal and on subsequent falling edges
of the SPICLK signal; input data is latched on the rising edge of
the SPICLK signal.

Serial Peripheral Interface (SPI) 9-19

SPI Module Registers

1 Data is output on falling edge and input on rising edge. When no

SPI data is sent, SPICLK is at high level.
The data input and output edges depend on the value of the
CLOCK PHASE bit (SPICTL.3) as follows:

CLOCK PHASE = 0: Data is output on the falling edge of the
SPICLK signal; input data is latched on the rising edge of the
SPICLK signal.

CLOCK PHASE = 1: Data is output one half-cycle before the first
falling edge of the SPICLK signal and on subsequent rising
edges of the SPICLK signal; input data is latched on the falling
edge of the SPICLK signal.

Bits 5−4 Reserved. Reads return zero; writes have no effect.

Bits 3−0 SPI CHAR3−SPI CHAR0. Character Length Control Bits 3−0. These four bits
determine the number of bits to be shifted in or out as a single character during
one shift sequence.

Table 9−3 lists the character length selected by the bit values.

Table 9−3. Character Length Control Bit Values

SPI SPI SPI SPI

CHAR3 CHAR2 CHAR1 CHAR0 Character Length
0 0 0 0 1
0 0 0 1 2
0 0 1 0 3
0 0 1 1 4
0 1 0 0 5
0 1 0 1 6
0 1 1 0 7
0 1 1 1 8
1 0 0 0 9
1 0 0 1 10
1 0 1 0 11
1 0 1 1 12
1 1 0 0 13
1 1 0 1 14
1 1 1 0 15
1 1 1 1 16

9-20
 SPI Module Registers

9.5.2 SPI Operation Control Register (SPICTL)

SPICTL controls data transmission, the SPI’s ability to generate interrupts, the
SPICLK phase, and the operational mode (slave or master).

Figure 9−8. SPI Operation Control Register (SPICTL) — Address 7041h

7−5 4 3 2 1 0

OVERRUN CLOCK MASTER/ SPI INT

Reserved TALK
INT ENA PHASE SLAVE ENA

R-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

Bits 7−5 Reserved. Reads return zero; writes have no effect.

Bit 4 OVERRUN INT ENA. Overrun Interrupt Enable. Setting this bit causes an in-
terrupt to be generated when the RECEIVER OVERRUN Flag bit (SPISTS.7)
is set by hardware. Interrupts generated by the RECEIVER OVERRUN Flag
bit and the SPI INT FLAG bit (SPISTS.6) share the same interrupt vector.
0 Disable RECEIVER OVERRUN Flag bit (SPISTS.7) interrupts
1 Enable RECEIVER OVERRUN Flag bit (SPISTS.7) interrupts

Bit 3 CLOCK PHASE. SPI Clock Phase Select. This bit controls the phase of the
SPICLK signal.
0 Normal SPI clocking scheme, depending on the CLOCK POLAR-
ITY bit (SPICCR.6)
1 SPICLK signal delayed by one half-cycle; polarity determined by
the CLOCK POLARITY bit

CLOCK PHASE and CLOCK POLARITY (SPICCR.6) make four different

clocking schemes possible (see Figure 9−3). When operating with CLOCK
PHASE high, the SPI (master or slave) makes the first bit of data available after
SPIDAT is written and before the first edge of the SPICLK signal, regardless
of which SPI mode is being used.

Bit 2 MASTER/SLAVE. SPI Network Mode Control. This bit determines whether
the SPI is a network master or slave. During reset initialization, the SPI is auto-
matically configured as a network slave.
0 SPI configured as a slave.
1 SPI configured as a master.

Bit 1 TALK. Master/Slave Transmit Enable. The TALK bit can disable data trans-
mission (master or slave) by placing the serial data output in the high-
impedance state. If this bit is disabled during a transmission, the transmit shift

Serial Peripheral Interface (SPI) 9-21

SPI Module Registers

register continues to operate until the previous character is shifted out. When
the TALK bit is disabled, the SPI is still able to receive characters and update
the status flags. TALK is cleared (disabled) by a system reset.
0 Disables transmission:

Slave mode operation: If not previously configured as a general-
purpose I/O pin, the SPISOMI pin will be put in the high-
impedance state.

Master mode operation: If not previously configured as a general-
purpose I/O pin, the SPISIMO pin will be put in the high-
impedance state.
1 Enables transmission
For the 4-pin option, ensure to enable the receiver’s SPISTE input
pin.

Bit 0 SPI INT ENA. SPI Interrupt Enable. This bit controls the SPI’s ability to gener-
ate a transmit/receive interrupt. The SPI INT FLAG bit (SPISTS.6) is unaf-
fected by this bit.
0 Disables interrupt
1 Enables interrupt

9.5.3 SPI Status Register (SPISTS)

SPISTS contains the receive buffer status bits.

Figure 9−9. SPI Status Register (SPISTS) — Address 7042h

7 6 5 4−0

RECEIVER
TX BUF FULL
OVERRUN SPI INT FLAG†‡ Reserved
FLAG‡
FLAG†‡

RC-0 RC-0 RC-0 R-0

Note: R = Read access, C = Clear, -0 = value after reset

† The RECEIVER OVERRUN FLAG bit and the SPI INT FLAG bit share the same interrupt vector.
‡ Writing a 0 to bits 5, 6, and 7 has no effect.

Bit 7 RECEIVER OVERRUN FLAG. SPI Receiver Overrun Flag. This bit is a read/
clear-only flag. The SPI hardware sets this bit when a receive or transmit op-
eration completes before the previous character has been read from the buff-
er. The bit indicates that the last received character has been overwritten and
therefore lost (when the SPIRXBUF was overwritten by the SPI module before
the previous character was read by the user application). The SPI requests

9-22
 SPI Module Registers

one interrupt sequence each time this bit is set if the OVERRUN INT ENA bit
(SPICTL.4) is set high. The bit is cleared in one of three ways:

Writing a 1 to this bit

Writing a 0 to SPI SW RESET (SPICCR.7)

Resetting the system

If the OVERRUN INT ENA bit (SPICTL.4) is set, the SPI requests only one
interrupt upon the first occurrence of setting the RECEIVER OVERRUN Flag
bit. Subsequent overruns will not request additional interrupts if this flag bit is
already set. This means that in order to allow new overrun interrupt requests
the user must clear this flag bit by writing a 1 to SPISTS.7 each time an overrun
condition occurs. In other words, if the RECEIVER OVERRUN Flag bit is left
set (not cleared) by the interrupt service routine, another overrun interrupt will
not be immediately re-entered when the interrupt service routine is exited.

However, the RECEIVER OVERRUN Flag bit should be cleared during the
interrupt service routine because the RECEIVER OVERRUN Flag bit and SPI
INT FLAG bit (SPISTS.6) share the same interrupt vector. This will alleviate
any possible doubt as to the source of the interrupt when the next byte is
received.

Bit 6 SPI INT FLAG. SPI Interrupt Flag. SPI INT FLAG is a read-only flag. The SPI
hardware sets this bit to indicate that it has completed sending or receiving the
last bit and is ready to be serviced. The received character is placed in the re-
ceiver buffer at the same time this bit is set. This flag causes an interrupt to be
requested if the SPI INT ENA bit (SPICTL.0) is set. This bit is cleared in one of
three ways:

Reading SPIRXBUF

Writing a 0 to SPI SW RESET (SPICCR.7)

Resetting the system

Bit 5 TX BUF FULL FLAG. SPI Transmit Buffer Full Flag. This read-only bit gets set
to 1 when a character is written to the SPI Transmit buffer SPITXBUF. It is
cleared when the character is automatically loaded into SPIDAT when the
shifting out of a previous character is complete. It is cleared at reset.

Bits 4−0 Reserved. Reads return zero; writes have no effect.

Serial Peripheral Interface (SPI) 9-23

SPI Module Registers

9.5.4 SPI Baud Rate Register (SPIBRR)

SPIBRR contains the bits used for baud-rate selection.

Figure 9−10. SPI Baud Rate Register (SPIBRR) — Address 7044h

7 6 5 4 3 2 1 0

SPI BIT SPI BIT SPI BIT SPI BIT SPI BIT SPI BIT SPI BIT
Reserved
RATE 6 RATE 5 RATE 4 RATE 3 RATE 2 RATE 1 RATE 0

R-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

Bit 7 Reserved. Reads return zero; writes have no effect.

Bits 6−0 SPI BIT RATE 6−SPI BIT RATE 0. SPI Bit Rate (Baud) Control. These bits de-
termine the bit transfer rate if the SPI is the network master. There are 125
data-transfer rates (each a function of the CPU clock, CLKOUT) that can be
selected. One data bit is shifted per SPICLK cycle. (SPICLK is the baud rate
clock output on the SPICLK pin.)

If the SPI is a network slave, the module receives a clock on the SPICLK pin
from the network master; therefore, these bits have no effect on the SPICLK
signal. The frequency of the incoming SPICLK from the master should not
exceed CLKOUT/4.

In master mode, the SPI clock is generated by the SPI and is output on the
SPICLK pin. The SPI baud rates are determined by the following formula:

SPI Baud-Rate Calculations

For SPIBRR = 3 to 127:

SPI Baud Rate = CLKOUT

(SPIBRR + 1)

For SPIBRR = 0, 1, or 2:

SPI Baud Rate = CLKOUT

4

where: CLKOUT = CPU clock frequency of the device

SPIBRR = Contents of the SPIBRR in the master SPI device

9-24
 SPI Module Registers

9.5.5 SPI Emulation Buffer Register (SPIRXEMU)

SPIRXEMU contains the received data. Reading SPIRXEMU does not clear
the SPI INT FLAG bit (SPISTS.6). This is not a real register but a dummy
address from which the contents of SPIRXBUF can be read by the emulator
without clearing the SPI INT FLAG.

Figure 9−11.SPI Emulation Buffer Register (SPIRXEMU) — Address 7046h

15 14 13 12 11 10 9 8

ERXB15 ERXB14 ERXB13 ERXB12 ERXB11 ERXB10 ERXB9 ERXB8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

7 6 5 4 3 2 1 0

ERXB7 ERXB6 ERXB5 ERXB4 ERXB3 ERXB2 ERXB1 ERXB0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

Note: R = Read access, -0 = value after reset

Bits 15−0 ERXB15−ERXB0. Emulation Buffer Received Data. SPIRXEMU functions al-
most identically to SPIRXBUF, except that reading SPIRXEMU does not clear
the SPI INT FLAG bit (SPISTS.6). Once the SPIDAT has received the com-
plete character, the character is transferred to SPIRXEMU and SPIRXBUF,
where it can be read. At the same time, SPI INT FLAG is set.

This mirror register was created to support emulation. Reading SPIRXBUF

clears the SPI INT FLAG bit (SPISTS.6). In the normal operation of the
emulator, the control registers are read to continually update the contents of
these registers on the display screen. SPIRXEMU was created so that the
emulator can read this register and properly update the contents on the display
screen. Reading SPIRXEMU does not clear the SPI INT FLAG bit, but reading
SPIRXBUF clears this flag. In other words, SPIRXEMU enables the emulator
to emulate the true operation of the SPI more accurately.

It is recommended that you view SPIRXEMU in the normal emulator run mode.

Serial Peripheral Interface (SPI) 9-25

SPI Module Registers

9.5.6 SPI Serial Receive Buffer Register (SPIRXBUF)

SPIRXBUF contains the received data. Reading SPIRXBUF clears the SPI
INT FLAG bit (SPISTS.6).

Figure 9−12. SPI Serial Receive Buffer Register (SPIRXBUF) — Address 7047h
15 14 13 12 11 10 9 8

RXB15 RXB14 RXB13 RXB12 RXB11 RXB10 RXB9 RXB8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

7 6 5 4 3 2 1 0

RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

Note: R = Read access, -0 = value after reset

Bits 15−0 RXB15−RXB0. Received Data. Once SPIDAT has received the complete
character, the character is transferred to SPIRXBUF, where it can be read. At
the same time, the SPI INT FLAG bit (SPISTS.6) is set. Since data is shifted
into the SPI’s most significant bit first, it is stored right-justified in this register.

9-26
 SPI Module Registers

9.5.7 SPI Serial Transmit Buffer Register (SPITXBUF)

SPITXBUF stores the next character to be transmitted. Writing to this register
sets the TX BUF FULL Flag bit (SPISTS.5). When transmission of the current
character is complete, the contents of this register are automatically loaded in
SPIDAT and the TX BUF FULL Flag is cleared. If no transmission is currently
active, data written to this register falls through into the SPIDAT register and
the TX BUF FULL Flag is not set.

In master mode, if no transmission is currently active, writing to this register

initiates a transmission in the same manner that writing to SPIDAT does.

Figure 9−13. SPI Serial Transmit Buffer Register (SPITXBUF) — Address 7048h
15 14 13 12 11 10 9 8

TXB15 TXB14 TXB13 TXB12 TXB11 TXB10 TXB9 TXB8

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

TXB7 TXB6 TXB5 TXB4 TXB3 TXB2 TXB1 TXB0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−0 TXB15−TXB0. Transmit Data Buffer. This is where the next character to be
transmitted is stored. When the transmission of the current character has com-
pleted, if the TX BUF FULL Flag bit is set, the contents of this register is auto-
matically transferred to SPIDAT, and the TX BUF FULL Flag is cleared.

Note:
Writes to SPITXBUF must be left-justified.

Serial Peripheral Interface (SPI) 9-27

SPI Module Registers

9.5.8 SPI Serial Data Register (SPIDAT)

SPIDAT is the transmit/receive shift register. Data written to SPIDAT is shifted
out (MSB) on subsequent SPICLK cycles. For every bit (MSB) shifted out of
the SPI, a bit is shifted into the LSB end of the shift register.

Figure 9−14. SPI Serial Data Register (SPIDAT) — Address 7049h

15 14 13 12 11 10 9 8

SDAT15 SDAT14 SDAT13 SDAT12 SDAT11 SDAT10 SDAT9 SDAT8

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

SDAT7 SDAT6 SDAT5 SDAT4 SDAT3 SDAT2 SDAT1 SDAT0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

Bits 15−0 SDAT15−SDAT0. Serial Data. Writing to the SPIDAT performs two functions:

It provides data to be output on the serial output pin if the TALK bit
(SPICTL.1) is set.

When the SPI is operating as a master, a data transfer is initiated. When

initiating a transfer, see the CLOCK POLARITY bit (SPICCR.6) described
in section 9.5.1, SPI Configuration Control Register on page 9-19, and the
CLOCK PHASE bit (SPICTL.3) described in section 9.5.2, SPI Operation
Control Register on page 9-21, for the requirements.

In master mode, writing dummy data to SPIDAT initiates a receiver sequence.

Since the data is not hardware-justified for characters shorter than sixteen bits,
transmit data must be written in left-justified form, and received data read in
right-justified form.

9-28
 SPI Module Registers

9.5.9 SPI Priority Control Register (SPIPRI)

SPIPRI selects the interrupt priority level of the SPI interrupt and controls the
SPI operation on the XDS emulator during program suspends, such as hitting
a breakpoint.

Figure 9−15. SPI Priority Control Register (SPIPRI) — Address 704Fh

7 6 5 4 3−0

SPI SPI SUSP SPI SUSP

Reserved Reserved
PRIORITY SOFT FREE

R-0 RW RW RW-0 R-0

Note: R = Read access, W = Write access, -0 = value after reset

Bit 7 Reserved. Reads return zero; writes have no effect.

Bit 6 SPI PRIORITY. Interrupt Priority Select. This bit specifies the priority level of
the SPI interrupt.
0 Interrupts are high-priority requests
1 Interrupts are low-priority requests

Bits 5−4 SPI SUSP SOFT and SPI SUSP FREE bits. These bits determine what oc-
curs when an emulation suspend occurs (for example, when the debugger hits
a breakpoint). The peripheral can continue whatever it is doing (free-run
mode) or, if in stop mode, it can either stop immediately or stop when the cur-
rent operation (the current receive/transmit sequence) is complete.
Bit 5 Bit 4
Soft Free
0 0 Immediate stop on suspend
1 0 Complete current receive/transmit sequence before stop-
ping
X 1 Free run, continue SPI operation regardless of suspend

Bits 3−0 Reserved. Reads return zero; writes have no effect.

Serial Peripheral Interface (SPI) 9-29

SPI Example Waveforms

9.6 SPI Example Waveforms

Figure 9−16. CLOCK POLARITY = 0, CLOCK PHASE = 0 (All data transitions are during
the rising edge, non-delayed clock. Inactive level is low.)

Ch1 Period
200 ns

SPICLK

SPISIMO

9-30
 SPI Example Waveforms

Figure 9−17. CLOCK POLARITY = 0, CLOCK PHASE = 1 (All data transitions are during
the rising edge, but delayed by half clock cycle. Inactive level is low.)

Ch1 Period
200 ns

SPICLK

SPISIMO

Serial Peripheral Interface (SPI) 9-31

SPI Example Waveforms

Figure 9−18. CLOCK POLARITY = 1, CLOCK PHASE = 0 (All data transitions are during
the falling edge. Inactive level is high.)

Ch1 Period
199 ns

SPICLK

SPISIMO

9-32
 SPI Example Waveforms

Figure 9−19. CLOCK POLARITY = 1, CLOCK PHASE = 1 (All data transitions are during
the falling edge, but delayed by half clock cycle. Inactive level is high.)

Ch1 Period
200 ns

SPICLK

SPISIMO

Serial Peripheral Interface (SPI) 9-33

SPI Example Waveforms

Figure 9−20. SPISTE Behavior in Master Mode (Master lowers SPISTE during the entire
16 bits of transmission.)

Ch1 Period
200 ns

SPICLK

SPISTE

9-34
 SPI Example Waveforms

Figure 9−21. SPISTE Behavior in Slave Mode (Slave’s SPISTE is driven low during the
entire 16 bits of transmission.)

Ch1 Period
398 ns

SPISIMO

SPISTE

Serial Peripheral Interface (SPI) 9-35

 Chapter 10

,   

This chapter describes the controller area network (CAN) module available on
some members of the 24x/240xA family. The interface signals, configuration
registers, and mailbox RAM are described in detail; however, the CAN protocol
itself is not discussed in depth. For details on the protocol, refer to CAN
Specification, Version 2.0, by Robert Bosch GmBH, Germany. The CAN
module is a full-CAN controller designed as a 16-bit peripheral and is fully
compliant with the CAN protocol, version 2.0B.

Topic Page

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.2 Overview of the CAN Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.3 Message Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4 CAN Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
10.5 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
10.6 Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35
10.7 Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39
10.8 Power-Down Mode (PDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-40
10.9 Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-41

10-1
Introduction

10.1 Introduction
The CAN peripheral supports the following features:

Full implementation of CAN protocol, version 2.0B
 Standard and extended identifiers
 Data and remote frames

Six mailboxes for objects with data lengths of 0- to 8-bytes
 Two receive mailboxes (MBOX0,1), two transmit mailboxes
(MBOX4,5)
 Two configurable transmit/receive mailboxes (MBOX2,3)

Local acceptance mask registers (LAMn) for mailboxes 0 and 1 and mail-
boxes 2 and 3

Programmable bit rate

Programmable interrupt scheme

Programmable wake-up on bus activity

Automatic reply to a remote request

Automatic re-transmission in case of error or loss of arbitration

Bus failure diagnostic

 Bus on/off
 Error passive/active
 Bus error warning
 Bus stuck dominant
 Frame error report
 Readable error counter

Self-Test Mode
 The CAN peripheral operates in a loopback mode
 Receives its own transmitted message and generates its own ac-
knowledge signal

Two-Pin Communication
 The CAN module uses two pins for communication, CANTX and
CANRX
 These two pins are connected to a CAN transceiver chip, which in turn
is connected to a CAN bus

10-2
 Overview of the CAN Network

10.2 Overview of the CAN Network

The controller area network (CAN) uses a serial multimaster communication
protocol that efficiently supports distributed real-time control with a very high
level of data integrity, and communication speeds of up to 1 Mbps. The CAN
bus is ideal for applications operating in noisy and harsh environments, such
as in the automotive and other industrial fields that require reliable
communication.
Prioritized messages of up to eight bytes in data length can be sent on a
multimaster serial bus using an arbitration protocol and an error-detection
mechanism for a high level of data integrity.

10.2.1 CAN Protocol Overview

The CAN protocol supports four different frame types for communication:

Data frames that carry data from a transmitter node to receiver node(s)

Remote frames that are transmitted by a node to request the transmis-

sion of a data frame with the same identifier

Error frames that are transmitted by any node on a bus-error detection

Overload frames that provide an extra delay between the preceding and
the succeeding data frames or remote frames
In addition, CAN Specification Version 2.0B defines two different formats that
differ in the length of the identifier field: standard frames with an 11-bit identifier
and extended frames with a 29-bit identifier.
CAN standard data frames contain from 44 to 108 bits, and CAN extended
data frames contain 64 to 128 bits. Furthermore, up to 23 stuff bits can be
inserted in a standard data frame and up to 28 stuff bits in an extended data
frame, depending on the data-stream coding. The overall maximum data
frame length is 131 bits for a standard frame and 156 bits for an extended
frame.
In Figure 10−1, bit fields within the data frame identify:

Start of the frame

Arbitration field containing the identifier and the type of message being
sent

Control field containing the number of data

Up to 8 bytes of data

Cyclic redundancy check (CRC)

Acknowledgment

End-of-frame bits

CAN Controller Module 10-3

Overview of the CAN Network

Figure 10−1. CAN Data Frame

Bit length 1 12 or 32 6 0−8 bytes 16 2 7

Start bit Control bits Data field CRC bits End

Arbitration field which contains: Acknowledge

11-bit identifier + RTR bit for standard frame format

29-bit identifier + SRR bit + IDE bit + RTR bit for extended frame format
Where: RTR = Remote Transmission Request
SRR = Substitute Remote Request
IDE = Identifier Extension

Note: Unless otherwise noted, numbers are amount of bits in field.

10.2.2 CAN Controller Architecture

Figure 10−2 shows the basic architecture of the CAN controller.

Figure 10−2. TMS320x240xA CAN Module Block Diagram

240xA
CAN module

Control/Status registers Transmit buffer

interrupt logic
CANTX
Control
bus CAN
CPU interface/ CAN core transceiver
CPU Memory management chip
unit
CANRX
CAN
bus
Temporary receive buffer
R mailbox 0 Data ID
R mailbox 1
T/R mailbox 2
T/R mailbox 3
T mailbox 4
T mailbox 5 Control Acceptance
logic filter
RAM 48x16
Matched ID

10-4
 Overview of the CAN Network

The CAN module is a 16-bit peripheral that accesses the following:

Control/status registers

Mailbox RAM

Control/Status Registers: The CPU performs 16-bit accesses to the

control/status registers. The CAN peripheral always presents full 16-bit data
to the CPU bus during read cycles.

Mailbox RAM: Writing/reading from the mailbox RAM is always wordwise

(16 bits) and the RAM always presents the full 16-bit word on the bus.

Table 10−1 shows the configuration details of the mailboxes.

Table 10−1. Mailbox Configuration Details

Mailbox Operating Mode LAM Used

0 Receive only LAM0

1 Receive only LAM0

2 Transmit/Receive (configurable) LAM1

3 Transmit/Receive (configurable) LAM1

4 Transmit only —

5 Transmit only —

CAN Controller Module 10-5

Overview of the CAN Network

10.2.3 Memory Map

Figure 10−3 shows memory space, and Table 10−2 and Table 10−3 give the
register and mailbox locations in the CAN module, respectively.

Figure 10−3. TMS320x240xA CAN Module Memory Space

240xA Data Space MDER TCR

0000 7100 RCR MCR

CAN BCR1 BCR2

registers
ESR GSR
710F CEC CAN_IFR

CAN_IMR LAM0_H

Reserved LAM0_L LAM1_H

7100
LAM1_L Reserved
CAN
7200
7230 Mailbox 0

Mailbox 1
MSG ID0L MSG ID0H
Mailbox 2
MSG CTRL0 Reserved
Mailbox 3
MBX0A MBX0B
Mailbox 4
MBX0C MBX0D
7230 Mailbox 5
FFFF
.
.
.

MSG ID5L MSG ID5H

MSG CTRL5 Reserved
MBX5A MBX5B
MBX5C MBX5D

10-6
 Overview of the CAN Network

Table 10−2. Register Addresses

Address Name Description
7100h MDER Mailbox Direction/Enable Register (bits 7 to 0)

7101h TCR Transmission Control Register (bits 15 to 0)

7102h RCR Receive Control Register (bits 15 to 0)

7103h MCR Master Control Register (bits 13 to 6, 1, 0)

7104h BCR2 Bit Configuration Register 2 (bits 7 to 0)

7105h BCR1 Bit Configuration Register 1 (bits 10 to 0)

7106h ESR Error Status Register (bits 8 to 0)

7107h GSR Global Status Register (bits 5 to 3, 1, 0)

7108h CEC CAN Error Counter Register (bits 15 to 0)

7109h CAN_IFR Interrupt Flag Register (bits 13 to 8, 6 to 0)

710Ah CAN_IMR Interrupt Mask Register (bits 15, 13 to 0)

710Bh LAM0_H Local Acceptance Mask for MBOX0 and 1 (bits 31, 28 to 16)

710Ch LAM0_L Local Acceptance Mask for MBOX0 and 1 (bits 15 to 0)

710Dh LAM1_H Local Acceptance Mask for MBOX2 and 3 (bits 31, 28 to 16)

710Eh LAM1_L Local Acceptance Mask for MBOX2 and 3 (bits 15 to 0)

710Fh Reserved Accesses assert the CAADDRx signal from the CAN peripheral
(which will assert an Illegal Address error)

Note: All unimplemented register bits are read as zero; writes have no effect. All register bits are initialized to zero unless other-
wise stated in the definition.

CAN Controller Module 10-7

Overview of the CAN Network

The mailboxes are located in one 48 × 16 RAM with 16-bit access and can be
written to or read by the CPU (user) or CAN. The CAN write or read access,
as well as the CPU read access, needs one clock cycle. The CPU write access
needs two clock cycles because the CAN controller performs a
read-modify-write cycle; and therefore, inserts one wait state for the CPU.

Table 10−3 shows the mailbox locations in the RAM.

Table 10−3. Mailbox Addresses

Mailboxes

Registers MBOX 0 MBOX 1 MBOX 2 MBOX 3 MBOX 4 MBOX 5

MSG IDn L 7200 7208 7210 7218 7220 7228

MSG IDn H 7201 7209 7211 7219 7221 7229

MSG CTRLn 7202 720A 7212 721A 7222 722A

Reserved

MBXn A 7204 720C 7214 721C 7224 722C

MBXn B 7205 720D 7215 721D 7225 722D

MBXn C 7206 720E 7216 721E 7226 722E

MBXn D 7207 720F 7217 721F 7227 722F

10-8
 Message Objects

10.3 Message Objects

CAN allows messages to be sent, received, and stored by using data frames.
Figure 10−4 illustrates the structure of the data frames with extended and
standard identifiers.

Figure 10−4. CAN Data Frame Structure

S Standard Identifier S I Extended Identifier R r r Data Data Data Data C A E
O
F 11 bit R
R
D
E 18 bit T
R 1 0 DLC Byte 0 Byte 1 ... Byte 6 Byte 7 R
C
C
K
O
F

S Standard Identifier R I r Data Data Data Data C A E

O
F 11 bit T
R
D
E 0 DLC Byte 0 Byte 1 ... Byte 6 Byte 7 R
C
C
K
O
F

Data frame contains:

SOF: Start of Frame − signifies the start of frame

Identifier:

 Message priority − determines the priority of the message when two or

more nodes are contending for the bus
 Message filtering − determines if a transmitted message will be re-
ceived by CAN modules

RTR: Remote Transmission Request bit − differentiates a data frame from

a remote frame

SRR: Substitute Remote Request bit − this bit occupies the position as
RTR would in a standard frame

IDE: Identifier Extension bit − differentiates standard and extended frames

r0, r1: reserved

DLC: Data Length Code − denotes the number of bytes (0 to 8) in a data

frame

Data: Four 16-bit words are used to store the (maximum) 8-byte data field
of a CAN message

CAN Controller Module 10-9

Message Objects

CRC: contains a 16-bit checksum calculated on most parts of the mes-

sage. This checksum is used for error detection

ACK: Data Acknowledge

EOF: End of Frame

10.3.1 Mailbox Layout

1) Mailbox RAM:
The mailbox RAM is the area where the CAN frames are stored before they are
transmitted, and after they are received. Each mailbox has four 16-bit registers
which can store a maximum of 8 bytes (MBXnA, MBXnB, MBXnC, and
MBXnD). Mailboxes that are not used for storing messages may be used as
normal memory by the CPU.
2) Message Identifiers:
Each one of the six mailboxes has its own message identifier stored in two
16-bit registers. Figure 10−5 shows the message identifier high word and
Figure 10−6 shows the message identifier low word.

Figure 10−5. Message Identifier for High-Word Mailboxes 0−5 (MSGIDnH)

15 14 13 12−0

IDE AME AAM IDH[28:16]

RW RW RW RW

Note: R = Read access; W = Write access

Bit 15 IDE. Identifier Extension Bit.

0 The received message has a standard identifier (11 bits).†
The message to be sent has a standard identifier (11 bits).‡
1 The received message has an extended identifier (29 bits).†
The message to be sent has an extended identifier (29 bits).‡
† In case of a receive mailbox
‡ In case of a transmit mailbox

Bit 14 AME. Acceptance Mask Enable Bit.

0 No acceptance mask will be used. All identifier bits in the received
message and the receive MBOX must match in order to store the
message.
1 The corresponding acceptance mask is used.
This bit will not be affected by a reception.

This bit is relevant for receive mailboxes only. Hence, it is applicable for
MBOX0 and MBOX1 and also for MBOX2 and MBOX3, if they are configured
as receive mailboxes. It is a don’t care for mailboxes 4 and 5.

10-10
 Message Objects

Bit 13 AAM. Auto Answer Mode Bit.

0 Transmit The mailbox does not reply to remote requests
mailbox automatically. If a matching identifier is received, it is
not stored.
Receive No influence on a receive mailbox.
mailbox
1 Transmit If a matching remote request is received, the CAN
mailbox peripheral answers by sending the contents of the
mailbox.
Receive No influence on a receive mailbox.
mailbox
This bit is only used for mailboxes 2 and 3. This bit will not be affected by a
reception.

Bits 12−0 IDH[28:16]. Upper 13 Bits of extended identifier. For a standard identifier, the
11-bit identifier will be stored in bits 12 to 2 of the MSGID’s upper word.

Figure 10−6. Message Identifier for Low-Word Mailboxes 0−5 (MSGIDnL)

15−0

IDL[15:0]

RW

Note: R = Read access; W = Write access

Bits 15−0 IDL[15:0]. The lower part of the extended identifier is stored in these bits.

3) Message Control Field:

Each one of the six mailboxes has its own “Message Control Field”.
Figure 10−7 illustrates the layout and default mode of the message control
field.

Figure 10−7. Message Control Field (MSGCTRLn)

15−5 4 3−0

Reserved RTR DLC[3:0]

RW RW

Note: R = Read access; W = Write access

Bits 15−5 Reserved.

Bit 4 RTR. Remote Transmission Request bit.

0 Data frame.
1 Remote frame.

CAN Controller Module 10-11

Message Objects

Bits 3−0 DLC. Data Length Code.

This value determines how many data bytes are used for transmission. This
field will be updated by the received data frame (i.e., the DLC value of the data
frame received will be copied in this field).
0001 1 byte
0010 2 bytes
0011 3 bytes
0100 4 bytes
0101 5 bytes
0110 6 bytes
0111 7 bytes
1000 8 bytes

10.3.2 Message Buffers

Message storage is implemented by RAM. The contents of the storage
elements are used to perform the functions of acceptance filtering,
transmission, and interrupt handling.
The mailbox module provides six mailboxes, each consisting of 8 bytes of
data, 29 identifier bits, and several control bits. Mailboxes 0 and 1 are for
reception; mailboxes 2 and 3 are configurable as receive or transmit; and
mailboxes 4 and 5 are transmit mailboxes. Mailboxes 0 and 1 share one
acceptance mask, while mailboxes 2 and 3 share a different mask.

Note: Unused Message Mailboxes

Unused mailbox RAM may be used as normal memory. Because of this, you
must ensure that no CAN function uses the RAM area. This is usually done
by disabling the corresponding mailbox or by disabling the CAN function.

10.3.3 Write Access to Mailbox RAM

There are two different types of write accesses to the Mailbox RAM:
1) write access to the identifier of a mailbox
2) write access to the data or control field

Note:
Write accesses to the identifier can only be accomplished when the mailbox
is disabled (MEn = 0 in MDER register).

10-12
 Message Objects

During accesses to the data field or control field, it is critical that the data does
not change while the CAN module is reading it. Therefore, a write access to
the data field or control field is disabled for a receive mailbox. For transmit
mailboxes, the access is usually denied if the transmit request set (TRS) bit
or the transmit request reset (TRR) bit is set. In these cases, a write-denied
interrupt flag (WDIF) is asserted. A way to access mailboxes 2 and 3 is to set
the change data field request (CDR) bit before accessing the mailbox data.

After the CPU access is finished, the CPU must clear the CDR flag by writing
a 0 to it. The CAN module checks for that flag before and after reading the
mailbox. If the CDR flag is set during the mailbox checks, the CAN module
does not transmit the message but continues to look for other transmit
requests. The setting of the CDR flag also stops the write-denied interrupt
(WDI) from being asserted. CAN read/write and CPU read accesses to the
mailbox RAM take one clock cycle. CPU writes to the mailbox RAM take two
clock cycles.

10.3.4 Transmit Mailbox

Mailboxes 4 and 5 are transmit mailboxes only; whereas, mailboxes 2 and 3
can be configured for reception or transmission.

The CPU stores the data to be transmitted in a mailbox that is configured as

a transmit mailbox. After writing the data and the identifier into RAM, and
provided the corresponding TRS bit has been set, the message is sent.

If more than one mailbox is configured as a transmit mailbox and more than
one corresponding TRS bit is set, the messages are sent one after another,
in falling order, beginning with the highest enabled mailbox.

If a transmission fails due to a law of arbitration or an error, the message

transmission will be re-attempted.

10.3.5 Receive Mailbox

Mailboxes 0 and 1 are receive-only mailboxes. Mailboxes 2 and 3 can be
configured for reception or transmission.

The identifier of each incoming message is compared to the identifiers held in

the receive mailboxes by using the appropriate identifier mask. When equality
is detected, the received identifier, the control bits, and the data bytes are
written into the matching RAM location. At the same time, the corresponding
receive message pending (RMPn) bit is set and a mailbox interrupt (MIFx) is
generated if enabled. If the current identifier does not match, the message is
not stored. The RMPn bit has to be reset by the CPU after reading the data.

CAN Controller Module 10-13

Message Objects

If a second message has been received for this mailbox and the RMP bit is
already set, the corresponding receive message lost (RML) bit is set. In this
case, the stored message is overwritten with the new data if the overwrite
protection control (OPC) bit is cleared. Otherwise, the next mailboxes are
checked.

Note:
For the mailbox interrupt flag (MIFn) bits in the CAN_IFR register to be set,
the corresponding bits in the CAN_IMR register must be enabled. If “polling”
is desired to complete transmission or reception of messages (as opposed
to interrupts), the following bits must be used:

For transmission: TAn bits in the TCR register

For reception: RMPn bits in the RCR register

10.3.6 Handling of Remote Frames

Remote frame handling can only be done with mailboxes 0 to 3; mailboxes 4
and 5 cannot handle remote frames.

Receiving a Remote Request

If a remote request is received (the incoming message has the remote
transmission request bit [RTR] = 1), the CAN module compares the identifier
to all identifiers of the mailboxes using the appropriate masks in descending
order starting with the highest mailbox number.

In case of a matching identifier with the message object configured as a

transmit mailbox and the auto-answer mode bit (AAM) in the message set, the
message object is marked to be sent (TRS bit is set). See Figure 10−8 (A).

In case of a matching identifier with the message object configured as a

transmit mailbox and the AAM bit not set, the message is not received. See
Figure 10−8 (B).

After finding a matching identifier in a send mailbox, no further compare is

done.

In case of a matching identifier with the message object configured as a

receive mailbox, the message is handled like a data frame and the RMP bit in
the receive control register (RCR) is set. The CPU then has to decide how to
handle the situation. See Figure 10−8 (E).

If the CPU wants to change the data in a message object that is configured as
a remote frame mailbox (AAM bit set), it has to set the mailbox number (MBNR)

10-14
 Message Objects

in the master control register and the CDR in the master control register first.
The CPU may then perform the access and clear the CDR to tell the CAN
module that the access is finished. Until the CDR is cleared, the transmission
of this mailbox is not performed. Since the TRS bit is not affected by the CDR,
a pending transmission is stacked after the CDR is cleared. Thus, the newest
data will be sent.

In order to change the identifier in the mailbox, the message object must be
disabled first (ME bit in the MDER = 0).

Sending a Remote Request

If the CPU wants to request data from another node, it may configure the
message object as a receive mailbox (only mailboxes 2 and 3) and set the TRS
bit. See Figure 10−8 (F). In this case, the module sends a remote frame
request and receives the data frame in the same mailbox that sent the request.
Therefore, only one mailbox is necessary to do a remote request.

10.3.7 Mailbox Configurations

A mailbox can be configured in four different ways:

Transmit mailbox (mailboxes 4 and 5 or 2 and 3 configured as transmit)

can only transmit messages.

Receive mailbox (mailboxes 0 and 1) can only receive messages.

Mailboxes 2 and 3 configured as receive mailboxes can transmit a remote

request frame and wait for the corresponding data frame if the TRS bit is
set.

Mailboxes 2 and 3 configured as transmit mailboxes can transmit a data

frame wherever a remote request frame is received for the corresponding
identifier, if the AAM bit is set.

Note:
After successful transmission of a remote frame, the TRS bit is reset but no
transmit acknowledge (TA) or mailbox interrupt flag is set.

CAN Controller Module 10-15

Message Objects

Figure 10−8. Remote Frame Requests

Situation at mailbox: Setting of corresponding flags:
remote frame (RTR = 1)
Transmit mailbox
(A) (AAM = 1) data frame TRS = 1, TA = 1

Transmit mailbox remote frame (RTR = 1)

(B) (AAM = 0) (not received)

remote frame (RTR = 1)

(C) Transmit mailbox

The answer is received in this receive mailbox if permitted or in a mailbox of anoth-

er CAN module if it is configured for this frame

data frame
(D) Receive mailbox RMP = 1

remote frame (RTR = 1)

(E) Receive mailbox RFP = 1, RMP = 1

CPU handles situation

remote frame (RTR = 1)

(F) Receive mailbox TRS = 0, TA remains 0,
no mailbox interrupt asserted
The receive mailbox contains the ID, RTR, DLC, and TRS of this mailbox (2 or 3) = 1.
The answer is received in this receive mailbox, if permitted, or in a mailbox of another
CAN module if it is configured for this frame.

10.3.8 Acceptance Filter

The identifier of the incoming message is first compared to the message
identifier of the receive mailbox (which is stored in the mailbox in MSGIDnH
and MSGIDnL registers). Then the appropriate acceptance mask is used to
mask out the bits of the identifier that should not be compared. The local
acceptance mask can be disabled by setting the acceptance mask enable
(AME) bit to 0 in the message identifier high word (MSGIDn) field.

Local Acceptance Mask (LAM)

The local acceptance filtering allows the user to locally mask (that is, treat as
a don’t care) any identifier bit of the incoming message.

Local acceptance mask register LAM1 is used for mailboxes 2 and 3 while
local acceptance mask register LAM0 is used for mailboxes 0 and 1. During

10-16
 Message Objects

a reception, mailboxes 3 and 2 are checked before mailboxes 1 and 0.

Figure 10−9 illustrates the LAMn_H high word and Figure 10−10 illustrates the
LAMn_L low word.

Figure 10−9. Local Acceptance Mask Register n (0, 1) High Word (LAMn_H) − Addresses
710Bh, 710Dh
15 14−13 12−0

LAMI Reserved LAMn[28:16]

RW-0 RW-0

Note: R = Read access; W = Write access; value following dash (−) = value after reset

Bit 15 LAMI. Local acceptance mask identifier extension bit.

0 The identifier extension bit stored in the mailbox determines which
messages are received (standard or extended).
1 Standard and extended frames can be received. In case of an ex-
tended frame, all 29 bits of the identifier are stored in the mailbox
and all 29 bits of the global acceptance mask register are used for
the filter. In case of a standard frame, only the first eleven bits (bits
12−2 of LAMn_H) of the identifier and the local acceptance mask
are used. The AME bit of the MBX must be 1 to receive both stan-
dard and extended identifiers.
When LAMI = 1:
1) The IDE bit of the receive mailbox is a “don’t care”. The IDE bit
of the receive mailbox is overwritten by the IDE bit of the trans-
mitted message.
2) The filtering criterion must be satisfied in order to receive a mes-
sage.
3) The number of bits to be compared is a function of the value of
the IDE bit of the transmitted message.
When LAMI = 0:
The IDE bit of the receive mailbox determines the number of bits to
be compared.
NOTE: The definition for the IDE bit changes depending on the
value of the LAMI bit:
When LAMI = 1:
IDE = 1: The RECEIVED message had an extended identifier.
IDE = 0: The RECEIVED message had a standard identifier.
When LAMI = 0:
IDE = 1: The TO BE RECEIVED message must have an ex-
tended identifier.
IDE = 0: The TO BE RECEIVED message must have a stan-
dard identifier.

CAN Controller Module 10-17

Message Objects

Bits 14−13 Reserved.

Bits 12−0 LAMn[28:16]. Upper 13 bits of the local acceptance mask.

0 Received identifier bit value must match the identifier bit of the re-
ceive mailbox. For example, if bit 27 of LAM is zero, then bit 27 of
the transmitted MSGID and bit 27 of the receive mailbox MSGID
must be the same.
1 Accept a 0 or a 1 (don’t care) for the corresponding bit of the re-
ceive identifier.

Figure 10−10. Local Acceptance Mask Register n (0, 1) Low Word (LAMn_L) −
Addresses 710Ch, 710Eh
15−0

LAMn[15:0]

RW-0

Note: R = Read access; W = Write access; value following dash (−) = value after reset

Bits 15−0 LAMn[15:0]. Lower part of the local acceptance mask. These bits enable the
masking of any identifier bit of an incoming message.
0 Received identifier bit value must match the identifier bit of the
receive mailbox.
1 Accept a 0 or a 1 (don’t care) for the corresponding bit of the
receive identifier.

10-18
 CAN Control Registers

10.4 CAN Control Registers

The control register bits allow mailbox functions to be manipulated. Each
register performs a specific function, such as enabling or disabling the
mailbox, controlling the transmit/receive mail function, and handling interrupts.

10.4.1 Mailbox Direction/Enable Register (MDER)

The Mailbox Direction/Enable register (MDER) consists of the Mailbox Enable
(ME) and the Mailbox Direction (MD) bits. In addition to enabling/disabling the
mailboxes, MDER is used to select the direction (transmit/receive) for
mailboxes 2 and 3. Mailboxes that are disabled may be used as additional
memory for the DSP. Figure 10−11 illustrates this register.

Figure 10−11. Mailbox Direction/Enable Register (MDER) — Address 7100h

15−8

Reserved

7 6 5 4 3 2 1 0

MD3 MD2 ME5 ME4 ME3 ME2 ME1 ME0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access; W = Write access; value following dash (−) = value after reset

Bits 15−8 Reserved.

Bits 7−6 MDn. Mailbox direction for mailbox n. Mailboxes 2 and 3 can be configured as
a transmit or receive mailbox.

Mailbox direction bits are defined as follows:

0 Transmit mailbox.
1 Receive mailbox.

After power-up, all bits are cleared.

Bits 5−0 MEn. Mailbox-enable for mailbox n. Each mailbox can be enabled or disabled.
If the bit MEn is 0, the corresponding mailbox n is disabled. The mailbox must
be disabled before writing to any identifier field.

If the corresponding bit in ME is set, the write access to the identifier of a

message object is denied and the mailbox is enabled for the CAN module.

Mailboxes that are disabled may be used as additional memory for the DSP.

CAN Controller Module 10-19

CAN Control Registers

Mailbox enable bits are defined as follows:

0 Disable mailbox.
1 Enable mailbox.

10.4.2 Transmit Control Register (TCR)

The transmit control register (TCR) contains bits that control the transmission
of messages (see Figure 10−12).
The control bits to set or reset a transmission request (TRS and TRR,
respectively) can be written independently. In this way, a write access to these
registers does not set bits that were reset because of a completed
transmission.
After power-up, all bits are cleared.

Figure 10−12. Transmission Control Register (TCR) — Address 7101h

15 14 13 12 11 10 9 8

TA5 TA4 TA3 TA2 AA5 AA4 AA3 AA2

RC-0 RC-0 RC-0 RC-0 RC-0 RC-0 RC-0 RC-0

7 6 5 4 3 2 1 0

TRS5 TRS4 TRS3 TRS2 TRR5 TRR4 TRR3 TRR2

RS-0 RS-0 RS-0 RS-0 RS-0 RS-0 RS-0 RS-0

Note: R = Read access; C = Clear; S = Set only; value following dash (−) = value after reset

Bits 15−12 TAn. Transmission Acknowledge (for mailbox n).

If the message in mailbox n was sent successfully, bit TAn is set.
Bits TAn are reset by writing a 1 from the CPU. This also clears the interrupt
if an interrupt was generated. Writing a 0 has no effect. If the CPU tries to reset
the bit while the CAN tries to set it, the bit is set.
These bits set a mailbox interrupt flag (MIFx) in the IF register. The MIFx bits
initiate a mailbox interrupt if enabled; that is, if the corresponding interrupt
mask bit in the IM register is set.
Bits 11−8 AAn. Abort Acknowledge (for mailbox n).
If transmission of the message in mailbox n is aborted, bit AAn is set and the
AAIF bit in the IF register is set. The AAIF bit generates an error interrupt if
enabled.
Bits AAn are reset by writing a 1 from the CPU. Writing a 0 has no effect. If the
CPU tries to reset a bit and the CAN tries to set the bit at the same time, the
bit is set.

10-20
 CAN Control Registers

Bits 7−4 TRSn. Transmission Request Set (for mailbox n).

In order to initiate a transfer, the TRSn bit has to be set in the TCR register.
After this, the entire transmission procedure and possible error handling is
done without any CPU involvement.

If TRSn is set, write access to the corresponding mailbox is denied, and the
message in mailbox n will be transmitted. Several TRS bits can be set
simultaneously.

TRS bits can be set by the CPU (user) or the CAN module and reset by internal
logic. If the CPU tries to set a bit while the CAN tries to clear it, the bit is set.
TRS bits are set by the user writing a 1. Writing a 0 has no effect.

In the event of a remote frame request, the TRS bits are set by the CAN module
for mailboxes 2 and 3.

The TRSn bits are reset after a successful or an aborted transmission (if an
abort is requested).

A write to a mailbox with TRS set will have no effect and will generate the WDIF
interrupt if enabled. A successful transmission initiates a mailbox interrupt, if
enabled.

TRS bits are used for mailboxes 4 and 5, and also for 2 and 3 if they are
configured for transmission.

Bits 3−0 TRRn. Transmission Request Reset (for mailbox n).

TRR bits can only be set by the CPU (user) and reset by internal logic. In case
the CPU tries to set a bit while the CAN module tries to clear it, the bit is set.
The TRR bits are set by the user writing a 1. Writing a 0 has no effect.
If TRRn is set, write access to the corresponding mailboxn is denied. A write
access will initiate a WDIF interrupt, if enabled. If TRRn is set and the
transmission which was initiated by TRSn is not currently processed, the
corresponding transmission request will be cancelled. If the corresponding
message is currently processed, this bit is reset in the event of:

1) A successful transmission
2) An abort due to a lost arbitration
3) An error condition detected on the CAN bus line
If the transmission is successful, the status bit TAn is set. If the transmission
is aborted, the corresponding status bit AAn is set. In case of an error
condition, an error status bit is set in the ESR.
The status of the TRR bits can be read from the TRS bits. For example, if TRS
is set and a transmission is ongoing, TRR can only be reset by the actions

CAN Controller Module 10-21

CAN Control Registers

described above. If the TRS bit is reset and the TRR bit is set, no effect occurs
because the TRR bit will be immediately reset.

10.4.3 Receive Control Register (RCR)

The receive control register (RCR) contains the bits which control the
reception of messages and remote frame handling.

Figure 10−13. Receive Control Register (RCR) — Address 7102h

15 14 13 12 11 10 9 8

RFP3 RFP2 RFP1 RFP0 RML3 RML2 RML1 RML0

RC-0 RC-0 RC-0 RC-0 R-0 R-0 R-0 R-0

7 6 5 4 3 2 1 0

RMP3 RMP2 RMP1 RMP0 OPC3 OPC2 OPC1 OPC0

RC-0 RC-0 RC-0 RC-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access; W = Write access; C = Clear; value following dash (−) = value after reset

Bits 15−12 RFPn. Remote Frame Pending Register (for mailbox n).
Whenever a remote frame request is received by the CAN Peripheral, the
corresponding bit RFPn is set.
It may be cleared by the CPU if the TRSn is not set; otherwise, it is reset
automatically. If the CPU tries to reset a bit and the CAN Peripheral tries to set
the bit at the same time, the bit is cleared.
If the AAM bit in the MSGIDn register is not set (and thus no answer is sent
automatically), the CPU must clear bit RFPn after handling the event.
If the message is sent successfully, RFPn is cleared by the CAN Peripheral.
The CPU cannot interrupt an ongoing transfer.
Bits 11−8 RMLn. Receive Message Lost (for mailbox n).
If an old message is overwritten by a new one in mailbox n, bit RMLn is set.
RMLn is not set in mailboxes that have the OPCn bit set. Thus, a message may
be lost without notification.
These bits can only be reset by the CPU and can be set by the internal logic.
They can be cleared by writing a 1 to RMPn. If the CPU tries to reset a bit and
the CAN tries to set the bit at the same time, the bit is set.
If one or more RML bits in the RCR register are set, the RMLIF in the CAN_IFR
register is also set. This may initiate an interrupt if the RMLIM bit in the
CAN_IMR register is set.

10-22
 CAN Control Registers

Bits 7−4 RMPn. Received Message Pending (for mailbox n).

If a received message is stored in mailbox n, the RMPn bit is set.
The RMP bits can only be reset by the CPU and are set by the CAN internal
logic. The RMPn and RMLn bits are cleared by writing a 1 to the RMPn bit at
the corresponding bit location. If the CPU tries to reset a bit and the CAN tries
to set the bit at the same time, the bit is set.
A new incoming message will overwrite the stored one if the OPCn bit is
cleared. If not, the next mailboxes are checked for a matching identifier. When
the old message is overwritten, the corresponding status bit RMLn is set.
The RMP bits in the RCR register set the mailbox interrupt flag (MIFx) bit in
the CAN_IFR register if the corresponding interrupt mask bit in the CAN_IMR
register is set. The MIFx flag initiates a mailbox interrupt if enabled.
Bits 3−0 OPCn. Overwrite Protection Control (for mailbox n).
If there is an overflow condition for mailbox n, the new message is
stored/ignored depending on the OPCn value. If the corresponding OPCn bit
is set to 1, the old message is protected against being overwritten by the new
message. Thus, the next mailboxes are checked for a matching identifier. If no
other mailbox is found, the message is lost without further notification. If OPCn
bit is not set, the old message is overwritten by the new one.

10.4.4 Master Control Register (MCR)

MCR is used to control the behavior of the CAN core module.

Figure 10−14. Master Control Register (MCR) — Address 7103h

15−14 13 12 11 10 9 8

Reserved SUSP CCR PDR DBO WUBA CDR

RW-0 RW-1 RW-0 RW-0 RW-0 RW-0

7 6 5−2 1−0

ABO STM Reserved MBNR[1:0]

RW-0 RW-0 RW-0

Note: R = Read access; W = Write access; value following dash (−) = value after reset

Bits 15−14 Reserved.

Bit 13 SUSP. Action on emulator suspend. The value of the SUSP bit has no effect on
the receive mailboxes.
0 Soft mode. The peripheral shuts down during suspend after the
current transmission is completed.
1 Free mode. The peripheral continues to run in suspend.

CAN Controller Module 10-23

CAN Control Registers

Bit 12 CCR. Change Configuration Request.

0 The CPU requests normal operation. It also exits the bus-off state
after the obligatory bus-off recovery sequence.
1 The CPU requests write access to the bit configuration registers
(BCRn). Flag CCE in the GSR indicates if the access is granted. CCR
must be set while writing to bit timing registers BCR1 and BCR2. This
bit will automatically be set to 1 if the bus-off condition is valid and the
ABO bit is not set. Thus, it has to be reset to exit the bus-off mode.

Bit 11 PDR. Power-Down Mode Request.

Before the CPU enters its IDLE mode (if IDLE shuts off the peripheral clocks),
it must request a CAN power down by writing to the PDR bit. The CPU must
then poll the PDA bit in the GSR, and enter IDLE only after PDA is set.
0 The power-down mode is not requested (normal operation).
1 The power-down mode is requested.

Bit 10 DBO. Data Byte Order.

0 The data is received or transmitted in the following order: Data byte 3,
2, 1, 0, 7, 6, 5, 4.
1 The data is received or transmitted in the following order: Data byte
0,1, 2, 3, 4, 5, 6, 7.

Note:
The DBO bit is used to define the order in which the data bytes are stored
in the mailbox when received and in which the data bytes are transmitted.
Byte 0 is the first byte in the message and Byte 7 is the last one as shown
in the figure of the CAN message (Figure 10−4).

Bit 9 WUBA. Wake Up on Bus Activity.

0 The module leaves the power-down mode only after the user writes a
0 to clear PDR.
1 The module leaves the power-down mode upon detecting any
dominant value on the CAN bus.

10-24
 CAN Control Registers

Bit 8 CDR. Change Data Field Request.

The CDR bit is applicable for mailboxes 2 and 3 only and in the following
situation: 1) either (or both) of these mailboxes are configured for transmission
and 2) the corresponding AAM bit (MSGIDxH.13) is set.
0 The CPU requests normal operation.
1 The CPU requests write access to the data field of the mailbox in
MBNR (also located in MCR). The CDR bit must be cleared by the
CPU after accessing the mailbox. The CAN module does not transmit
the mailbox if the CDR is set. This is checked by the state machine
before and after it reads the data from the mailbox to store it in the
transmit buffer.

Bit 7 ABO. Auto Bus On.

0 The bus-off state may only be left after 128 × 11 consecutive
recessive bits on the bus and after having reset the CCR bit.
1 After the bus-off state, the module goes back to the bus-on state after
128 × 11 consecutive recessive bits.

Bit 6 STM. Self-Test Mode.

0 The module is in normal mode.
1 The module is in Self-Test mode. In this mode, the CAN module
generates its own ACK signal. Thus, it enables operation without a
bus connected to the module. The message is not sent but read back
and stored in the appropriate mailbox. The remote frame handling
with Auto Answer mode set is not implemented in STM. The received
message ID will not be stored in the receive mailbox in this mode.

Bits 5−2 Reserved.

Bits 1−0 MBNR. Mailbox Number (for CDR bit assertion).

The CPU requests a write access to the data field for the mailbox
having this number and configured for Remote Frame Handling.
These are mailboxes 2 (10) or 3 (11), but not 0, 1, 4 or 5.

10.4.5 Bit Configuration Registers (BCRn)

The bit configuration registers (BCR1 and BCR2) are used to configure the
CAN node with the appropriate network timing parameters. These registers
must be programmed before using the CAN module and are writeable only in
configuration mode. The CCR bit (MCR.12) must be set to put the CAN module
in configuration mode. Figure 10−15 and Figure 10−16 illustrate BCR2 and
BCR1, respectively.

CAN Controller Module 10-25

CAN Control Registers

Note:
To avoid unpredictable behavior, BCR1 and BCR2 should never be pro-
grammed with values not allowed by the CAN protocol specification.

The length of a bit on the CAN bus is determined by the parameters time
segment 1 (TSEG1) and 2 (TSEG2) and by the baud rate prescaler value
(BRP). All controllers on the CAN bus must have the same baud rate and bit
length. At different clock frequencies of the individual controllers, the baud rate
has to be adjusted by the given parameters. In the bit timing logic, the
conversion of the parameters to the required bit timing is realized.

Figure 10−15. Bit Configuration Register 2 (BCR2) — Address 7104h

15−8

Reserved

7−0

BRP[7:0]

RW-0

Note: R = Read access; W = Write access; value following dash (−) = value after reset

Bits 15−8 Reserved.

Bits 7−0 BRP. Baud Rate Prescaler.

Bits 7 to 0 of this field specify the duration of a time quantum (TQ) in CAN
module system clock units. The length of one TQ is defined by:

TQ + ǒCLKOUT
1 Ǔ (BRP ) 1) ns
If BRP = BCR2 = 0, then 1 TQ = 1 CPU clock cycle.

10-26
 CAN Control Registers

Figure 10−16. Bit Configuration Register 1 (BCR1) — Address 7105h

15−11 10 9−8

Reserved SBG SJW[1:0]

RW-0 RW-0
7 6−3 2−0

SAM TSEG1-[3:0] TSEG2-[2:0]

RW-0 RW-0 RW-0

Note: R = Read access; W = Write access; value following dash (−) = value after reset

Bits 15−11 Reserved.

Bit 10 SBG. Synchronization on both edges.
0 The CAN module resynchronizes on the falling edge only.
1 Reserved
Bits 9−8 SJW. Synchronization jump width.
SJW indicates by how many units of TQ a bit is allowed to be lengthened or
shortened when resynchronizing with the receive data stream on the CAN bus.
The synchronization is performed with the falling edge (SBG = 0). SJW is
programmable from 1 to 4 TQ.

Note:
Since the SJW[1:0] value is enhanced by one by the CAN module, the
value that is written in bits [1:0] is actually (SJW − 1), where SJW is
the timing segment referred to in Figure 10−17, CAN Bit
Timing.

Bit 7 SAM. Sample point setting.

This parameter sets the number of samples used by the CAN module to
determine the actual level of the CAN bus. When the SAM bit is set, the level
determined by the CAN bus corresponds to the result from the majority
decision of the last three values. The sample points are at the sample point and
twice before with a distance of 1/2 TQ.

0 The CAN module samples only once.

1 The CAN module samples three times and makes a majority decision.

Bits 6−3 TSEG1[3:0]. Time segment 1.

This parameter specifies the length of the TSEG1 segment in TQ units.

CAN Controller Module 10-27

CAN Control Registers

TSEG1 combines PROP SEG and PHASE SEG1 segments (CAN protocol).

TSEG1 = PROP SEG + PHASE SEG1.

The value of TSEG1 is programmable from 3 to 16 TQ and must be greater

than or equal to TSEG2.

Note:
Since the TSEG1[3:0] value is enhanced by one by the CAN module, the
value that is written in bits [3:0] is actually (TSEG1 − 1), where TSEG1
is the timing segment referred to in Figure 10−17, CAN Bit
Timing.

Bits 2−0 TSEG2[2:0]. Time segment 2.

TSEG2 defines the length of PHASE SEG2 in TQ units.

The value of TSEG2 is programmable from 2 to 8 TQ in compliance with the

formula:
(SJW +1) ≤ TSEG2 ≤ 8

Note:
Since the TSEG2[2:0] value is enhanced by one by the CAN module, the val-
ue that is written in bits [2:0] is actually (TSEG2 − 1), where TSEG2 is the
timing segment referred to in Figure 10−17 CAN Bit
Timing.

Note:
The user-defined values for the SJW, TSEG1, and TSEG2 parameters are
enhanced by one (by the internal logic) when the CAN module accesses
these parameters.

10-28
 CAN Control Registers

CAN Bit Timing

Figure 10−17. CAN Bit Timing

Nominal bit time

SYNCSEG

SJW SJW

(TSEG1 +1) (TSEG2 + 1)

1 TQ

Sample point
Transmit point

Baud rate is calculated as follows (in bits per second):

Baud Rate + CLKOUT + 1

(BRP ) 1) Bit Time TQ * Bit Time

where Bit Time = number of TQ per bit

Bit Time = (TSEG1 + 1) + (TSEG2 + 1) + 1

BRP = Baud rate prescaler

Note: TSEG1 and TSEG2 are the values written by the user in BCR1 register.

Table 10−4. CAN Bit Timing Examples for CLKOUT = 40 MHz

Sampling
TSEG1 TSEG2 Bit Time BRP Point Baud Rate
4 3 10 3 60% 1 Mbit/s

10 7 20 3 60% 500 Kbit/s

9 4 16 9 68.8% 250 Kbit/s

14 8 25 15 64% 100 Kbit/s

11 6 20 39 65% 50 Kbit/s

CAN Controller Module 10-29

Status Registers

10.5 Status Registers

The two status registers are the error status register (ESR) and the global
status register (GSR). As indicated by their names, ESR provides information
about any type of error encountered and GSR provides information about all
functions of the CAN peripheral. Figure 10−18 and Figure 10−19 illustrate the
ESR and the GSR, respectively.

10.5.1 Error Status Register (ESR)

The error status register (see Figure 10−18) is used to display errors that
occurred during operation. Only the first error is stored. Subsequent errors do
not change the status of the register. These registers are cleared by writing a
1 to them except for the SA1 flag, which is cleared by any recessive bit on the
bus.

Bits 8 to 3 are error bits that can be read and cleared by writing a 1 to them.
Bits 2 to 0 are status bits that cannot be cleared, only read.

Figure 10−18. Error Status Register (ESR) — Address 7106h

15−9 8

Reserved FER

RC-0
7 6 5 4 3 2 1 0

BEF SA1 CRCE SER ACKE BO EP EW

RC-0 RC-1 RC-0 RC-0 RC-0 R-0 R-0 R-0

Note: R = Read access; C = Clear; value following dash (−) = value after reset

Bits 15−9 Reserved.

Bit 8 FER. Form Error Flag.

0 The CAN module was able to send and receive correctly.
1 A Form Error occurred on the bus. This means that one or more of the
fixed-form bit fields had the wrong level on the bus.

Bit 7 BEF. Bit Error Flag.

0 The CAN module was able to send and receive correctly.
1 The received bit does not match the transmitted bit outside of the
arbitration field; or during transmission of the arbitration field, a
dominant bit was sent but a recessive bit was received.

10-30
 Status Registers

Bit 6 SA1. Stuck at Dominant Error.

0 The CAN module detected a recessive bit.
1 The CAN module did not detect a recessive bit. The SA1 bit is
always 1 after a hardware or a software reset or a bus-off condition.

Bit 5 CRCE. CRC Error.

0 The CAN module did not receive a wrong CRC.
1 The CAN module received a wrong CRC.

Bit 4 SER. Stuff Error.

0 No stuff bit error occurred.
1 The stuff bit rule was violated.

Bit 3 ACKE. Acknowledge Error.

0 The CAN module received an acknowledge.
1 The CAN module did not receive an acknowledge.

Bit 2 BO. Bus-Off Status.

0 Normal operation.
1 There is an abnormal rate of error occurrences on the CAN bus. This
condition occurs when the transmit error counter TEC has reached
the limit of 256. While in bus-off status, no messages can be received
or transmitted. This state is only exited by clearing the CCR bit in the
Master Control Register (MCR) or if the Auto Bus-On bit in the Master
Control Register is set. After leaving the bus-off state, the error
counters are cleared.

Bit 1 EP. Error Passive Status.

0 The CAN module is not in error-passive mode.
1 The CAN module is in error-passive mode.

Bit 0 EW. Warning Status.

0 The values of both error counters are less than 96.
1 At least one of the error counters reached the warning level of 96.

CAN Controller Module 10-31

Status Registers

10.5.2 Global Status Register (GSR)

Figure 10−19. Global Status Register (GSR) — Address 7107h
15−8

Reserved

7−6 5 4 3 2 1 0

Reserved SMA CCE PDA Rsvd RM TM

R-0 R-1 R-0 R-0 R-0

Note: R = Read access; value following dash (−) = value after reset

Bits 15−6 Reserved.

Bit 5 SMA. Suspend Mode Acknowledge.
0 The CAN peripheral is not in suspend mode.
1 The CAN peripheral has entered suspend mode.
This bit is set after a latency of 1 clock cycle up to the length of one frame after
the SUSPEND signal is activated.
Bit 4 CCE. Change Configuration Enable.
0 Write access to the configuration registers is denied.
1 The CPU has write access to the configuration registers BCR while
the CCR bit (MCR.12) is set. Access is granted after reset or when
the CAN module reaches the idle state.
This bit is set after a latency of 1 clock cycle up to the length of one frame.
Bit 3 PDA. Power-Down Mode Acknowledge.
Before the CPU enters its IDLE mode (to potentially shut off ALL device
clocks), it must request a CAN power down by writing to the PDR bit in MCR.
The CPU must then poll the PDA bit and enter IDLE only after PDA is set.
0 Normal operation.
1 The CAN peripheral has entered the power-down mode.
This bit is set after a latency of 1 clock cycle up to the length of one frame.
Bit 2 Reserved.
Bit 1 RM. The CAN module is in the Receive Mode.
This bit reflects what the CBM is actually doing regardless of mailbox
configuration.
0 The CAN core module is not receiving a message.
1 The CAN core module is receiving a message.

10-32
 Status Registers

Bit 0 TM. The CAN module is in the Transmit Mode.

This bit reflects what the CBM is actually doing regardless of mailbox
configuration.
0 The CAN core module is not transmitting a message.
1 The CAN core module is transmitting a message.

CAN Controller Module 10-33

Status Registers

10.5.3 CAN Error Counter Register (CEC)

The CAN module contains two error counters: the receive error counter (REC)
and the transmit error counter (TEC). The values of both counters can be read
from the CEC register via the CPU interface. Figure 10−20 illustrates the CEC.

Figure 10−20. CAN Error Counter Register (CEC) — Address 7108h

15−8

TEC[7:0]

R-0
7−0

REC[7:0]

R-0

Note: R = Read access; value following dash (−) = value after reset

After exceeding the error passive limit (128), REC is not increased any further.
When a message is received correctly, the counter is set again to a value
between 119 and 127. After reaching the bus-off status, TEC is undefined,
while REC is cleared and its function is changed: It will be incremented after
every 11 consecutive recessive bits on the bus. These 11 bits correspond to
the gap between two telegrams on the bus. If the receive counter reaches 128,
the module changes automatically back to the status bus-on if the ABO bit in
MCR is set. Otherwise, it changes when the recovery sequence of 11 × 128
bits has finished and the CCR bit in the MCR register is reset by the DSP. All
internal flags are reset and the error counters are cleared. The configuration
registers keep the programmed values.

After the power-down mode, the error counters stay unchanged. They are
cleared when entering the configuration mode.

10-34
 Interrupt Logic

10.6 Interrupt Logic

There are two interrupt requests from the CAN peripheral to the peripheral
interrupt expansion (PIE) controller: the mailbox interrupt and the error
interrupt. Both interrupts can assert either a high-priority request or a
low-priority request to the CPU. The following events may initiate an interrupt:

Mailbox Interrupt

 A message was transmitted or received successfully. This event as-

serts the Mailbox interrupt.

Abort Acknowledge Interrupt

 A “send transmission” operation was aborted. This event asserts the

Error interrupt.

Write Denied Interrupt

 The CPU tried to write to a mailbox but was not allowed to. This event
asserts the Error interrupt.

Wake-up Interrupt

 After wake-up, this interrupt is generated. This event asserts the Error
interrupt, even when clocks are not running.

Receive Message Lost Interrupt

 An old message was overwritten by a new one. This event asserts the
Error interrupt.

Bus-Off Interrupt

 The CAN module enters the bus-off state. This event asserts the Error
interrupt.

Error Passive Interrupt

 The CAN module enters the error passive mode. This event asserts
the Error interrupt.

Warning Level Interrupt

 One or both of the error counters is greater than or equal to 96. This
event asserts the Error interrupt.

Note: While servicing a CAN interrupt, the user should check all the bits in the
CAN_IFR register to ascertain if more than one bit has been set. The
corresponding interrupt service routines (ISRs) should be executed for all the
set bits. This must be done since the core interrupt will be asserted only once,
even if multiple bits are set in the CAN_IFR register.

CAN Controller Module 10-35

Interrupt Logic

10.6.1 CAN Interrupt Flag Register (CAN_IFR)

The interrupt flag bits are set if the corresponding interrupt condition occurs.
The appropriate mailbox interrupt request is asserted only if the corresponding
interrupt mask in CAN_IMR register is set. The peripheral interrupt request
stays active until the interrupt flag is cleared by the CPU by writing a 1 to the
appropriate bit. An interrupt acknowledge does not clear the interrupt flags.
The MIFx flags cannot be cleared by writing to the IF register; instead, they
must be cleared by writing a 1 to the appropriate TA bit in the TCR register for
a transmit mailbox (mailboxes 2 to 5), or the RMP bit in the RCR register for
the receive mailbox (mailboxes 0 to 3).

In order to recognize future interrupts, the flag bit of the current interrupt(s)
must be cleared immediately upon entering the ISR. One method of
implementing this is to copy the CAN_IFR register in a memory variable and
then clear the set bits in CAN_IFR. The memory variable could then be read
to determine the appropriate routines to be executed.

Figure 10−21. CAN Interrupt Flag Register (CAN_IFR) — Address 7109h

15−14 13 12 11 10 9 8

Reserved MIF5 MIF4 MIF3 MIF2 MIF1 MIF0

R-0 R-0 R-0 R-0 R-0 R-0

7 6 5 4 3 2 1 0

Rsvd RMLIF AAIF WDIF WUIF BOIF EPIF WLIF

RC-0 RC-0 RC-0 RC-0 RC-0 RC-0 RC-0

Note: R = Read access; C = Clear; value following dash (−) = value after reset

Bits 15−14 Reserved.

Bits 13−8 MIFx. Mailbox Interrupt Flag (receive/transmit).

0 No message was transmitted or received.
1 The corresponding mailbox transmitted or received a message
successfully.

Each of the six mailboxes may initiate an interrupt. These interrupts can be a
receive or a transmit interrupt depending on the mailbox configuration. If one
of the configurable mailboxes is configured as Remote Request Mailbox (AAM
set) and a remote frame is received, a transmit interrupt is set after sending
the corresponding data frame. If a remote frame is sent, a receive interrupt is
set after the reception of the desired data frame.

10-36
 Interrupt Logic

There is one interrupt mask bit for each mailbox. If a message is received, the
corresponding RMPn bit in the RCR is set. If a message is sent, the
corresponding TAn bit in the TCR register is set. The setting of the RMPn bit
or the TAn bit also sets the appropriate MIFx flag in the CAN_IFR register if the
corresponding interrupt mask bit is set. The MIFx flag generates an interrupt.
The MIMx mask bits in the CAN_IMR register determine if an interrupt can be
generated by a mailbox.

Bit 7 Reserved.

Bit 6 RMLIF. Receive Message Lost Interrupt Flag.

0 No message was lost.
1 An overflow condition has occurred in at least one of the receive
mailboxes.

Bit 5 AAIF. Abort Acknowledge Interrupt Flag.

0 No transmission was aborted.
1 A “send transmission” operation was aborted.

Bit 4 WDIF. Write Denied Interrupt Flag.

0 The write access to the mailbox was successful.
1 The CPU tried to write to a mailbox but was not allowed to.

Bit 3 WUIF. Wake-Up Interrupt Flag.

0 The module is still in the sleep mode or in normal operation.
1 The module has left the sleep mode.

Bit 2 BOIF. Bus-Off Interrupt Flag.

0 The CAN module is still in the bus-on mode.
1 The CAN has entered the bus-off mode.

Bit 1 EPIF. Error Passive Interrupt Flag.

0 The CAN module is not in the error-passive mode.
1 The CAN module has entered the error-passive mode.

Bit 0 WLIF. Warning Level Interrupt Flag.

0 None of the error counters has reached the warning level.
1 At least one of the error counters has reached the warning level.

CAN Controller Module 10-37

Interrupt Logic

10.6.2 CAN Interrupt Mask Register (CAN_IMR)

The setup for the interrupt mask register (see Figure 10−22) is the same as
for the interrupt flag register (CAN_IFR) with the addition of the interrupt
priority selection bits MIL and EIL. If a mask bit is set, the corresponding
interrupt request to the PIE controller is enabled.

Figure 10−22. CAN Interrupt Mask Register (CAN_IMR) — Address 710Ah

15 14 13 12 11 10 9 8

MIL Reserved MIM5 MIM4 MIM3 MIM2 MIM1 MIM0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

7 6 5 4 3 2 1 0

EIL RMLIM AAIM WDIM WUIM BOIM EPIM WLIM

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access; W = Write access; value following dash (−) = value after reset

Two additional control bits are included in this register:

Bit 15 MIL. Mailbox Interrupt Priority Level.

For the mailbox interrupts MIF5 − MIF0.

0 The mailbox interrupts generate high-priority requests.
1 The mailbox interrupts generate low-priority requests.

Bit 14 Reserved.

Bits 13−8 See section 10.6.1, CAN Interrupt Flag Register (CAN_IFR), on page 10-36.

Bit 7 EIL. Error Interrupt Priority Level.

For the error interrupts RMLIF, AAIF, WDIF, WUIF, BOIF, EPIF, and WLIF.
0 The named interrupts generate high-priority requests.
1 The named interrupts generate low-priority requests.

Bits 6−0 See section 10.6.1, CAN Interrupt Flag Register (CAN_IFR), on page 10-36.

10-38
 Configuration Mode

10.7 Configuration Mode

The CAN module must be initialized before activation. This is only possible
when the module is in the configuration mode, which is set by programming
CCR with 1. The initialization can be performed only if the status bit CCE
confirms the request by getting 1. Afterwards, the bit configuration registers
can be written. The module is activated again by programming the control bit
CCR with zero. After a hardware reset, the configuration mode is active.

Figure 10−23. CAN Initialization

Normal mode (CCR = 0)

(CCE = 0)

Configuration mode requested

(CCR = 1)
(CCE = 0)

Wait for configuration mode (CCR = 1)

(CCE = 0)
(CCE = 0)

Configuration mode active (CCR = 1)

(CCE = 1)

Changing of bit timing

parameters enabled

Normal mode requested

(CCR = 0)
(CCE = 1)

Wait for normal mode

(CCR = 0)
(CCE = 1)
(CCE = 1)

CAN Controller Module 10-39

Power-Down Mode (PDM)

10.8 Power-Down Mode (PDM)

If the peripheral clocks are to be shut off by the device low-power mode, the
CAN peripheral’s own low-power mode must be requested before a device
low-power mode is entered by executing the IDLE instruction.

Before the CPU enters its IDLE mode prior to the device low-power mode that
potentially shuts off all device clocks, it must first request a CAN peripheral
power down by writing a 1 to the PDR bit in MCR. If the module is transmitting
a message when PDR is set, the transmission is continued until a successful
transmission, a lost arbitration, or an error condition on the CAN bus line
occurs. Then the PDA is asserted. Thus, the module causes no error condition
on the CAN bus line. When the module is ready to enter the power-down mode,
the status bit PDA is set. The CPU must then poll the PDA bit in GSR, and only
enter IDLE after PDA is set.

On exiting the power-down mode, the PDR flag in the MCR must be cleared
by software, or automatically, if the WUBA bit in MCR is set and there is bus
activity on the CAN bus line. When detecting a dominant signal on the CAN
bus, the wake-up interrupt flag (WUIF) is asserted. The power-down mode is
exited as soon as the clock is switched on. There is no internal filtering for the
CAN bus line.

The automatic wake-up on bus activity can be enabled or disabled by setting

the configuration bit WUBA. If there is any activity on the CAN bus line, the
module begins its power-up sequence. The module waits until detecting
11 consecutive recessive bits on the RX pin and goes to bus active afterwards.
The first message, which initiates the bus activity, cannot be received.

When WUBA is enabled, the error interrupt WUIF is asserted automatically to

the PIE controller, which will handle it as a wake-up interrupt and restart the
device clocks if they are stopped.

After leaving the sleep mode with a wake up, the PDR and PDA are cleared.
The CAN error counters remain unchanged.

10-40
 Suspend Mode

10.9 Suspend Mode

The suspend mode can operate in either Free mode, where the CAN
peripheral continues to operate regardless of the suspend signal being active,
or Soft mode, where the CAN peripheral stops operation at the end of the
current transmission. Suspend mode is entered when the CPU activates the
SUSPEND signal. The SUSP bit in MCR determines which of the two suspend
modes (Free or Soft) is entered.

When the module enters the Soft suspend mode, the status bit SMA (in GSR)
is set. If the module is actually transmitting a message when the SUSPEND
signal is activated, the transmission is continued until a successful
transmission, a lost arbitration, or an error condition on the CAN bus line
occurs. Otherwise, it enters suspend mode immediately and sets the SMA bit.

In Free mode, the peripheral ignores the suspend signal and continues to
operate, receiving and transmitting messages.

Either way, the module causes no error condition on the CAN bus line.

When suspended (in Soft mode), the module does not send or receive any
messages. The module is not active on the CAN bus line. Acknowledge flags
and error flags are not sent. The error counters and all other internal registers
are frozen. Suspend is only asserted when a system is being debugged with
an in-circuit emulator.

In case the module is in bus-off mode when suspend mode is requested, it

enters suspend mode immediately. It does, however, still count the 128 × 11
recessive bits needed to return to the bus-on mode. All error counters are
undefined in that state. The bus-off flag and the error-passive flag are set.

The module leaves the suspend mode when the SUSPEND signal is
deactivated. It waits for the next 11 recessive bits on the bus and goes back
to normal operation. This is called the idle mode (different from the CPU’s IDLE
mode). The module waits for the next message or tries to send one itself. When
the module is in bus-off mode, it continues to wait for the bus-on condition. This
occurs when 128 × 11 recessive bits are received. It also counts those that
occurred during the suspend mode.

Note: The clock is not switched off internally for suspend or low-power mode.

For easy reference, Table 10−5 provides a listing of the CAN notation,
definition, and register and bit number.

CAN Controller Module 10-41

Suspend Mode

Table 10−5. CAN Notation

Notation Signification Register Bit No.

AA Abort Acknowledge TCR 11:8
AAIF Abort Acknowledge Interrupt Flag CAN_IFR 5
AAIM Abort Acknowledge Interrupt Mask CAN_IMR 5
AAM Auto Answer Mode MSGIDnH 13
ABO Auto Bus On MCR 7
ACKE Acknowledge Error ESR 3
AME Acceptance Mask Enable MSGIDnH 14
BEF Bit Error Flag ESR 7
BO Bus-Off Status ESR 2
BOIF Bus-Off Interrupt Flag CAN_IFR 2
BOIM Bus-Off Interrupt Mask CAN_IMR 2
BRP Baud Rate Prescaler BCR2 7:0
CCE Change Configuration Enable GSR 4
CCR Change Configuration Request MCR 12
CDR Change Data Field Request MCR 8
CRCE CRC Error ESR 5
DBO Data Byte Order MCR 10
DLC Data Length Code MSGCTRLn 3:0
EIL Error Interrupt Priority Level CAN_IMR 7
EP Error Passive Status ESR 1
EPIF Error Passive Interrupt Flag CAN_IFR 1
EPIM Error Passive Interrupt Mask CAN_IMR 1
EW Warning Status ESR 0
FER Form Error Flag ESR 8
IDE Identifier Extension MSGIDnH 15
IDH Upper Bits (28:16) of Extended Identifier MSGIDnH 12:0
IDL Lower Bits (15:0) of Extended Identifier MSGIDnH 15:0
LAMI Local Acceptance Mask Identifier LAM 15
MBNR Mailbox Number MCR 1:0
ME Mailbox Enable MDER 5:0
MD Mailbox Direction MDER 7:6
MIF Mailbox Interrupt Flag CAN_IFR 13:8
MIL Mailbox Interrupt Priority Level CAN_IMR 15

10-42
 Suspend Mode

Table 10−5. CAN Notation(Continued)

Notation Signification Register Bit No.
MIM Mailbox Interrupt Mask CAN_IMR 13:8
OPC Overwrite Protection Control RCR 3:0
PDA Power-Down Mode Acknowledge GSR 3
PDR Power-Down Mode Request MCR 11
REC Receive Error Counter CEC 7:0
RFP Remote Frame Pending RCR 15:12
RM Receive Mode GSR 1
RML Receive Message Lost RCR 11:8
RMLIF Receive Message Lost Interrupt Flag CAN_IFR 6
RMLIM Receive Message Lost Interrupt Mask CAN_IMR 6
RMP Receive Message Pending RCR 7:4
RTR Remote Transmission Request MSGCTRLn 4
SA1 Stuck at Dominant Error ESR 6
SAM Sample Point Setting BCR1 7
SBG Synchronization on Both Edge BCR1 10
SER Stuff Error ESR 4
SJW Synchronization Jump Width BCR1 9:8
SMA Suspend Mode Acknowledge GSR 5
STM Self-Test Mode MCR 6
SUSP Action on Emulator Suspend MCR 13
TA Transmission Acknowledge TCR 15:12
TEC Transmit Error Counter CEC 15:8
TM Transmit Mode GSR 0
TRS Transmission Request Set TCR 7:4
TRR Transmission Request Reset TCR 3:0
TSEG1 Time Segment 1 BCR1 6:3
TSEG2 Time Segment 2 BCR1 2:0
WDIF Write Denied Interrupt Flag CAN_IFR 4
WDIM Write Denied Interrupt Mask CAN_IMR 4
WLIF Warning Level Interrupt Flag CAN_IFR 0
WLIM Warning Level Interrupt Mask CAN_IMR 0
WUBA Wake Up on Bus Activity MCR 9
WUIF Wake Up Interrupt Flag CAN_IFR 3
WUIM Wake Up Interrupt Mask CAN_IMR 3

CAN Controller Module 10-43

Suspend Mode

Table 10−6. Mailbox RAM Layout

Register/Databyte Address Register/Databyte Address
MSG − ID0H 7201h MSG − ID0L 7200h
Reserved 7203h MSG − CTRL0 7202h
Databyte 3, Databyte 2 (DBO = 1) Databyte 1, Databyte 0 (DBO = 1)
7205h (B) 7204h (A)
Databyte 2, Databyte 1 (DBO = 0) Databyte 2, Databyte 3 (DBO = 0)
Databyte 7, Databyte 6 (DBO = 1) Databyte 5, Databyte 4 (DBO = 1)
7207h (D) 7206h (C)
Databyte 4, Databyte 5 (DBO = 0) Databyte 6, Databyte 7 (DBO = 0)
MSG − ID1H 7209h MSG − ID1L 7208h
Reserved MSG − CTRL1 720Ah
Databyte 0, Databyte 1 (DBO = 1) Databyte 2, Databyte 3 (DBO = 1)
720Dh 720Ch
Databyte 3, Databyte 2 (DBO = 0) Databyte 1, Databyte 0 (DBO = 0)
Databyte 4, Databyte 5 (DBO = 1) Databyte 6, Databyte 7 (DBO = 1)
720Fh 720Eh
Databyte 7, Databyte 6 (DBO = 0) Databyte 5, Databyte 4 (DBO = 0)
•
•
•
•
•
•
MSG − ID5H 7229h MSG − ID5L 7228h
Reserved MSG − CTRL5 722Ah
Databyte 0, Databyte 1 (DBO = 1) Databyte 2, Databyte 3 (DBO = 1)
722Dh 722Ch
Databyte 3, Databyte 2 (DBO = 0) Databyte 3, Databyte 2 (DBO = 0)
Databyte 4, Databyte 5 (DBO = 1) Databyte 6, Databyte 7 (DBO = 1)
722Fh 722Eh
Databyte 7, Databyte 6 (DBO = 0) Databyte 5, Databyte 4 (DBO = 0)
† The DBO (data byte order) bit is located in the MCR register and is used to define the order in which the data bytes are stored
in the mailbox when received and the order in which the data bytes are transmitted. Byte 0 is the first byte in the message and
Byte 7 is the last one shown in the CAN message.

10-44
 Chapter 11

- (-%) 

The watchdog (WD) timer peripheral monitors software and hardware

operations, and implements system reset functions upon CPU disruption. If
the software goes into an improper loop, or if the CPU becomes temporarily
disrupted, the WD timer overflows to assert a system reset.

Most conditions that temporarily disrupt chip operation and inhibit proper CPU
function can be cleared and reset by the watchdog function. By its consistent
performance, the watchdog increases the reliability of the CPU, thus ensuring
system integrity.

All registers in this peripheral are eight bits in width and are attached to the
lower byte of the peripheral data bus of the 16-bit CPU.

The only difference between the 240xA WD timer and that of the C240 is the
lack of real-time interrupt capability.

This implementation of the WD timer generates its own watchdog clock locally
by dividing down the CLKOUT from CPU.

Topic Page

11.1 Watchdog Timer Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.2 Watchdog Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.3 Watchdog Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8

11-1
Watchdog Timer Features

11.1 Watchdog Timer Features

The WD module includes the following features:

8-bit WD counter that generates a system reset upon overflow

6-bit free-running counter that feeds the WD counter via the WD counter
prescale

A WD reset key (WDKEY) register that clears the WD counter when the
correct combination of values are written, and generates a reset if an in-
correct value is written to the register

WD check bits that initiate a system reset if the WD timer is corrupted

Automatic activation of the WD timer once system reset is released

A WD prescale with six selections from the 6-bit free-running counter

Figure 11−1 shows a block diagram of the WD module

11-2
 Watchdog Timer Features

Figure 11−1.Block Diagram of the WD Module

6-bit free- /64

running
/32
counter
WDCLK /16
/8
CLR /4
/2

Register Name

WD prescale WDCNTR Watchdog Counter Register

000 WDKEY Watchdog Reset Key Register
select bits
001 WDCR Watchdog Control Register
010
WDCR.2−0 011
WDPS2−0 100
101
WDCR.6 110 WD FLAG
111
WDDIS WDCNTR.7−0 WDCR.7

8-bit watchdog
counter 1-cycle PS/257
Prescale delay
CLR
WDKEY.7−0 selection System
reset
Bad key request
Watchdog 55+AA
detector Good
reset key WDCHK2−0
key
register
WDCR.5−3 Bad WDCR key

3
System reset
3

1 0 1
(Constant value)

 Writing to bits WDCR.5−3 with anything but the correct pattern (101) generates a system reset.
 These prescale values are with respect to the WDCLK signal.

Watchdog (WD) Timer 11-3

Watchdog Timer Operations

11.2 Watchdog Timer Operations

11.2.1 Overview of WD Timer Operations

Three registers control the WD operations:

WD Counter Register (WDCNTR) — This register contains the value of

the WD counter

WD Key Register (WDKEY) — This register clears the WDCNTR when a

55h value followed by an AAh value is written to WDKEY

WD Control Register (WDCR) — This register contains the following con-

trol bits used for watchdog configuration
 WD disable bit
 WD flag bit
 WD check bits (three)
 WD prescale select bits (three)

11.2.2 Watchdog Timer Clock

The watchdog timer clock (WDCLK) is a low-frequency clock used to clock the
watchdog timer. WDCLK has a nominal frequency of 78125 Hz when
CPUCLK = 40 MHz. WDCLK is derived from the CLKOUT of the CPU. This
ensures that the watchdog continues to count when the CPU is in IDLE1 or
IDLE 2 mode (see section 4.4, Low-Power Modes, on page 4-8). WDCLK is
generated in the watchdog peripheral. The frequency of WDCLK can be
calculated from:

WDCLK = (CLKOUT)/512

WDCLK is seen at the CLKOUT pin only when the watchdog is enabled. If the
watchdog is enabled, the watchdog counter should be reset before it
overflows; otherwise, the DSP will be reset.

11.2.3 Watchdog Suspend

WDCLK is stopped when the CPU’s suspend signal goes active. This is
achieved by stopping the clock input to the clock divider which generates
WDCLK from CLKOUT.

Note that the watchdog timer clock does not run when the real-time monitor
is running. This is different from the F/C240.

11-4
 Watchdog Timer Operations

11.2.4 Operations of the WD Timer

The WD timer is an 8-bit resetable incrementing counter that is clocked by the
output of the prescaler. The timer protects against system software failures
and CPU disruption by providing a system reset when the WDKEY register is
not serviced before a watchdog overflow. This reset returns the system to a
known starting point. Software then clears the WDCNTR register by writing a
correct data pattern to the WD key logic.

A separate internal clocking signal (WDCLK) is generated by the on-chip clock

module and is active in all operational modes except the HALT mode. WDCLK
enables the WD timer to function, regardless of the state of any register bit(s)
on the chip, except during the HALT low-power mode, which disables the
WDCLK signal. The current state of WDCNTR can be read at any time during
its operation.

11.2.4.1 WD Prescale Select

The 8-bit WDCNTR can be clocked directly by the WDCLK signal or through
one of six taps from the free-running counter. The 6-bit free-running counter
continuously increments at a rate provided by WDCLK. The WD functions are
enabled as long as WDCLK is provided to the module. Any one of the six taps
(or the direct input from WDCLK) can be selected by the WD prescale select
(bits WDPS2−0) as the input to the time base for the WDCNTR. This prescale
provides selectable watchdog overflow rates of from 3.28 ms to 209.7 ms for
a WDCLK rate of 78125 Hz. While the chip is in normal operating mode, the
free-running counter cannot be stopped or reset, except by a system reset.
Clearing WDCNTR does not clear the free-running counter.

11.2.4.2 Servicing the WD Timer

The WDCNTR is reset when the proper sequence is written to the WDKEY
before the WDCNTR overflows. The WDCNTR is reset-enabled when a value
of 55h is written to the WDKEY. When the next AAh value is written to the
WDKEY, then the WDCNTR actually is reset. Any value written to the WDKEY
other than 55h or AAh causes a system reset. Any sequence of 55h and AAh
values can be written to the WDKEY without causing a system reset; only a
write of 55h followed by a write of AAh to the WDKEY resets the WDCNTR.

Watchdog (WD) Timer 11-5

Watchdog Timer Operations

Table 11−1 shows a typical sequence written to WDKEY after power-up.

Table 11−1. Typical WDKEY Register Power-Up Sequence

Sequential Value Written
Step to WDKEY Result
1 AAh No action.
2 AAh No action.
3 55h WDCNTR is enabled to be reset by the next AAh.
4 55h WDCNTR is enabled to be reset by the next AAh.
5 55h WDCNTR is enabled to be reset by the next AAh.
6 AAh WDCNTR is reset.
7 AAh No action.
8 55h WDCNTR is enabled to be reset by the next AAh.
9 AAh WDCNTR is reset.
10 55h WDCNTR is enabled to be reset by the next AAh.
11 23h System reset due to an improper key value writ-
ten to WDKEY.

Step 3 above is the first action that enables the WDCNTR to be reset. The
WDCNTR is not actually reset until step 6. Step 8 re-enables the WDCNTR to
be reset, and step 9 resets the WDCNTR. Step 10 again re-enables the
WDCNTR to be reset. Writing the wrong key value to the WDKEY in step 11
causes a system reset.
A WDCNTR overflow or an incorrect key value written to the WDKEY also sets
the WD flag (WDFLAG). After a reset, the program reads this flag to determine
the source of the reset. After reset, WDFLAG should be cleared by the
software to allow the source of subsequent resets to be determined. WD resets
are not prevented when the flag is set.

11.2.4.3 WD Reset
When the WDCNTR overflows, the WD timer asserts a system reset. Reset
occurs one WDCNTR clock cycle (either WDCLK or WDCLK divided by a
prescale value) later. The reset cannot be disabled in normal operation as long
as WDCLK is present. The WD timer is, however, disabled in the oscillator
power-down mode when WDCLK is not active. For software development or
flash programming purposes, the WD timer can be disabled by setting the
WDDIS bit in the WD control register (WDCR.6). Note that there is no WDDIS
pin in the 240xA devices. The “watchdog override” bit in the SCSR2 register
provides the functionality of the WDDIS pin.

11-6
 Watchdog Timer Operations

11.2.4.4 WD Check Bit Logic

The WD check bits (WDCR.5−3, described in detail in section 11.3.3 on

page 11-9) are continuously compared to a constant value (1012). If writes
to the WD check bits do not match this value, a system reset is generated. This
functions as a logic check in case the software improperly writes to the WDCR,
or if an external stimulus (such as voltage spikes, EMI, or other disruptive
sources) corrupt the contents of the WDCR. Writing to bits WDCR.5-3 with
anything but the correct pattern (1012) generates a system reset.

The check bits are always read as zeros (0002), regardless of what value has
been written to them.

11.2.4.5 WD Setup

The WD timer operates independently of the CPU and is always enabled. It

does not need any CPU initialization to function. When a system reset occurs,
the WD timer defaults to the fastest WD timer rate available (3.28 ms for a
78125-Hz WDCLK signal). As soon as reset is released internally, the CPU
starts executing code, and the WD timer begins incrementing. This means
that, to avoid a premature reset, WD setup should occur early in the power-up
sequence.

Watchdog (WD) Timer 11-7

Watchdog Control Registers

11.3 Watchdog Control Registers

The WD module control registers are shown in Table 11−2 and discussed in
detail in the sections that follow the table.

Table 11−2. WD Module Control Registers

Bit Number
Register
Address mnemonic 7 6 5 4 3 2 1 0
7020h — Reserved
7021h — Reserved
7022h —
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ Reserved
7023h WDCNTR
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
D7 D6 D5 D4 D3 D2 D1 D0
7024h —
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ Reserved
7025h
7026h
7027h
WDKEY
—
—
ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
D7 D6 D5 D4 S3
Reserved
Reserved
S2 D1 D0

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
7028h — Reserved

ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
7029h WDCR WDFLAG WDDIS WDCHK2 WDCHK1 WDCHK0 WDPS2 WDPS1 WDPS0

11.3.1 WD Counter Register

The 8-bit WD counter register (WDCNTR) contains the current value of the WD
counter. This register continuously increments at a rate selected through the
WD control register. When WDCNTR overflows, an additional single-cycle
delay (either WDCLK or WDCLK divided by a prescale value) is incurred
before system reset is asserted. Writing the proper sequence to the WD reset
key register clears WDCNTR and prevents a system reset. However, it does
not clear the free-running counter.

Figure 11−2.WD Counter Register (WDCNTR) — Address 7023h

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

Note: R = Read access, -0 = value after reset

Bits 7−0 D7−D0. Data Values. These read-only data bits contain the 8-bit WD counter
value. Writing to this register has no effect.

11-8
 Watchdog Control Registers

11.3.2 WD Reset Key Register

The WD reset key register clears the WDCNTR register when a 55h followed
by an AAh is written to WDKEY. Any combination of AAh and 55h is allowed,
but only a 55h followed by an AAh resets the counter. Any other value causes
a system reset.

Figure 11−3.WD Reset Key Register (WDKEY) — Address 7025h

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Note: R = Read access, W = Write access, -0 = value after reset

Bits 7−0 D7−D0. Data Values. These write-only data bits contain the 8-bit WD reset key
value. When read, the WDKEY register does not return the last key value but
rather returns the contents of the WDCR register.

11.3.3 WD Timer Control Register

WDCR contains control bits used for watchdog configuration. These include
flag bits that indicate if the WD timer initiated a system reset; check bits that
assert a system reset if an incorrect value is written to the WDCR register; and
watchdog prescale select bits that select the counter overflow tap which is
used to clock the WD counter.

Figure 11−4.WD Timer Control Register (WDCR) — Address 7029h

7 6 5 4 3 2 1 0

WDFLAG WDDIS WDCHK2 WDCHK1 WDCHK0 WDPS2 WDPS1 WDPS0

RC-x RWc-0 W-0 W-0 W-0 RW-0 RW-0 RW-0

Note: R = Read access, C = Clear by writing 1, W = Write access, Wc = Write access conditional on WD OVERRIDE bit being
equal to 1, -0 = value after reset, -x = value after reset determined by action/inaction of WD timer

Bit 7 WDFLAG: Watchdog Flag Bit. This bit indicates if a system reset was asserted
by the WD timer. The bit is set to 1 by a WD-generated reset.
0 Indicates that the WD timer has not asserted a reset since the bit
was last cleared
1 Indicates that the WD timer has asserted a reset since the bit was
last cleared

Watchdog (WD) Timer 11-9

Watchdog Control Registers

Note: Power-on reset (POR) and WDFLAG

The power-on reset (POR) state of the WDFLAG bit is undefined. This could
cause confusion if the user code attempts to differentiate a watchdog-initi-
ated reset from a power-on reset. If an application implements a mechanism
to differentiate a POR from other types of reset, the WDFLAG bit must be
cleared after a POR. Once this is done, the WDFLAG bit can be set only by
a watchdog reset.

Bit 6 WDDIS. Watchdog Disable. This bit can be written only when the WD OVER-
RIDE bit in the SCSR2 register is 1.
0 Watchdog is enabled.
1 Watchdog is disabled.
Clearing the WD OVERRIDE bit in the SCSR2 register after disab-
ling the WD would re-enable the WD.

Bit 5 WDCHK2. Watchdog Check Bit 2. This bit must be written as a 1 when you
write to the WDCR register; otherwise, a system reset is asserted. This bit is
always read as 0.
0 System reset is asserted.
1 Normal operation continues if all check bits are written correctly.

Bit 4 WDCHK1. Watchdog Check Bit 1. This bit must be written as a 0 when you
write to the WDCR register; othewise, a system reset is asserted. This bit is
always read as 0.
0 Normal operation continues if all check bits are written correctly.
1 System reset is asserted.

Bit 3 WDCHK0. Watchdog Check Bit 0. This bit must be written as a 1 when you
write to the WDCR register; otherwise, a system reset is asserted. This bit is
always read as 0.
0 System reset is asserted.
1 Normal operation continues if all check bits are written correctly.

11-10
 Watchdog Control Registers

Bits 2−0 WDPS2−WDPS0. Watchdog Prescale Select Bits. These bits select the
counter overflow tap that is used to clock the WD counter. Each selection sets
up the maximum time that can elapse before the WD key logic is serviced.
Table 11−3 shows the overflow times for each prescaler setting when the
WDCLK is running at 78125 Hz. Because the WD timer counts 257 clocks be-
fore overflowing, the times given are the minimum for overflow (reset). The
maximum timeout can be up to 1/256 longer than the times listed in Table 11−3
because of the added uncertainty resulting from not clearing the prescaler.

Table 11−3. WD Overflow (Timeout) Selections

WD Prescale Select Bits 78125 Hz WDCLK†

Overflow Minimum
WDCLK
WDPS2 WDPS1 WDPS0 Frequency Overflow
Divider
(Hz) (ms)
0 0 X 1 305.2 3.28

0 1 0 2 152.6 6.6

0 1 1 4 76.3 13.1

1 0 0 8 38.1 26.2

1 0 1 16 19.1 52.4

1 1 0 32 9.5 104.9

1 1 1 64 4.8 209.7

X = Don’t care
† Generated by a 40-MHz clock

Watchdog (WD) Timer 11-11

11-12
 Chapter 12

./0,#./0    

This chapter describes the compatibility issues between the 240xA and 240
family of processors.

The software changes required between 240 code and 240xA code have been
kept to a minimum. A majority of the register addresses, bit positions, and
functions are identical between the 240 and 240xA devices.

Topic Page

12.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.2 Event Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.4 Serial Communications Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.5 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.6 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

12-1
General

12.1 General
The 240 is a 5-V part, whereas the 240xA devices operate on 3.3 V.

Low-power mode 2 (HALT) is the lowest power mode on the 240xA. It is similar
to the LPM3 (oscillator power down) on the 240. There is no equivalent to
LPM2 (PLL power down) on the 240. The low-power-mode bits are in a
different register (SCSR1) and in different bit positions on the 240xA.

Software reset is not available. However a software reset can be achieved by

writing an incorrect key to the watchdog timer after setting a flag in memory
to indicate that this was a software reset, and not a true watchdog time-out.

Illegal address detection does not have 100% coverage on the 240; however,
it does on 240xA devices. Furthermore, an illegal address generates a reset
on the 240, and an NMI on the 240xA. The NMI service routine must poll the
ILLADDR bit in SCSR1 to determine whether the NMI was caused by an illegal
address.

External interrupts XINT2 and XINT3 on the 240 are similar to external
interrupts XINT1 and XINT2 on the 240xA. The addresses of the registers are
different, however, and the general-purpose I/O multiplexing control bits are
located in the digital I/O registers, not in the external interrupt control registers.
The external interrupt flags are cleared by writing a 1 to the flag bit. This is in
order to be consistent with the other peripherals.

The CLOCKOUT control bits are in a different register (SCSR1) and bit
position.

A code security module (CSM) has been added to the 240xA devices.

12-2
 Event Manager

12.2 Event Manager

In order to port code from 240 to 240xA:

The GP timer 3 must not be used.

The single-up count and single-up/down count modes of the GP timers

must not be used. The decoding of the timer modes from the TMODE1−0
bits has changed, and this code will have to be modified when porting code
from the 240 to the 240xA.

The 32-bit timer mode cannot be used.

Capture 4 on the 240 cannot be used, when porting code from the 240 to
the 240xA.

The capture units can use either GP Timer 1 or 2 as a time base.

When porting code from the the 240 to the 240xA, the capture interrupt
code needs to allow for the fact that an interrupt is usually generated after
every second capture and not every capture as on the 240.

The QEP logic can clock GP timer 1 or 2.

The three simple compare units cannot be used.

The compare mode of the (full) compare units cannot be used; only the
PWM mode can be used.

Software must change from 240 to 240xA to comprehend the changes to

the dead-band counters and dead-band prescaler.

All general interrupt service routines must be changed to get their periph-
eral interrupt vectors from the PIVR (701Eh) and not one of EVIVRA,
EVIVRB or EVIVRC. Reading from PIVR does not clear interrupt flags. In-
terrupt flags must be cleared manually.

Some pins in the EV have an “input qualification” circuitry. See the

 
 
 
  ,

 
 
    Data Sheet
(literature number SPRS145) for more details.

240xA-240 Family Compatibility 12-3

Analog-to-Digital
Analog-to-Digital Converter
Converter / Serial Communications Interface / Serial Peripheral Interface / Watchdog Timer

12.3 Analog-to-Digital Converter

When compared to the 240 ADC, the 240xA ADC has been significantly
enhanced. As a result, code written for the 240 ADC cannot be ported to the
240xA.

12.4 Serial Communications Interface

Some code changes are required. This is code that switches the SCI pins
between their SCI functions and their digital I/O functions, and accesses them
in digital I/O mode. When porting code from a 240 to a 240xA device, it must
access the relevant bits in the digital I/O peripheral instead of the SCIPC2
register.

The SCI has free and soft emulation modes.

12.5 Serial Peripheral Interface

This SPI is no longer limited to a maximum transmission rate of CLKOUT / 8
in slave mode. The maximum transmission rate in both slave mode and master
mode is now CLKOUT / 4.

Some code changes are required. This is code that switches the SPI pins
between their SPI functions and their digital I/O functions, and accesses them
in digital I/O mode. When code is ported from 240 to 240xA devices, it must
access the relevant bits in the digital I/O peripheral instead of the SCIPC1 and
SCIPC2 register.

When code is ported from a 240 to a 240xA device, writes of transmit data to
the serial data register, SPIDAT, must be left-justified within a 16-bit register,
not within an 8-bit register.

The SPI has free and soft emulation modes.

12.6 Watchdog Timer

When porting code from 240 to 240xA devices, all code that uses the RTI
peripheral (if any) must be removed.

12-4
 Chapter 13

./0,#./    

This chapter discusses the compatibility issues between the 24x

(241/242/243) devices and the 240x/240xA devices.

It outlines the points to be considered while migrating from the 24x family to
the 240x/240xA family.

Topic Page

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

13.2 24x-240xA DSP Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.4 System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.5 Digital I/O (GPIO Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.6 Event Manager Module (EVB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14

13-1
Introduction

13.1 Introduction
This chapter highlights the major differences (in terms of features/peripherals)
between the 240xA and the 24x (TMS320F243/F241/C242) family of DSP
devices. The 240xA devices share most of the 24x features; however, 240xA
devices have some enhancements. The common features, differences, and
enhancements are described in Table 13−1 and Table 13−2.

Table 13−1. 24x-Compatible Features/Peripherals in 240xA DSPs

24x-Compatible Features/Peripherals in 240xA Reference Document

TMS320F/C24x DSP Controllers Reference
C2xx CPU, Instruction Set, Interrupt Behavior, and
1 Guide: CPU and Instruction Set (literature num-
B0, B1, B2 DARAM
ber SPRU160)

TMS320F243, TMS320F241 DSP Controllers

2 XMIF (External Memory Interface)
Data Sheet (literature number SPRS064)

Watchdog: (With the minor exception of the ab-

TMS320F243/F241/C242 DSP Controllers
3 sence of the WDDIS pin; this feature is now imple-
Reference Guide (literature number SPRU276)
mented in software.) All WD registers are identical.

EVA (Event Manager): EVA is exactly identical to TMS320F243/F241/C242 DSP Controllers

4
EV2 in 24x family Reference Guide (literature number SPRU276)

TMS320F243/F241/C242 DSP Controllers

5 CAN (Controller Area Network)
Reference Guide (literature number SPRU276)

TMS320F243/F241/C242 DSP Controllers

6 SCI (Serial Communications Interface)
Reference Guide (literature number SPRU276)

TMS320F243/F241/C242 DSP Controllers

7 SPI (Serial Peripheral Interface)
Reference Guide (literature number SPRU276)

13-2
 Introduction

13.1.1 Migrating Code from 24x to 240x/240xA Devices

All 240x/240xA peripherals (with the exception of ADC) are functionally
identical to those in 24x devices. Hence, code written for the 24x can be easily
ported to 240x/240xA devices. However, due to feature enhancements in the
240x/240xA devices, the following points should be kept in mind:

1) 240x/240xA devices operate at higher clock speeds. This warrants a

change in the values written to the event manager registers (that control
parameters such as PWM frequency) and other registers that affect the
communication speed in serial devices such as the SPI, SCI, and CAN.

2) After reset in the 240x/240xA devices, the clock to all of the peripherals
is disabled. The peripheral clock must be enabled as part of the peripheral
initialization. This requirement does not apply to 24x devices since clock
to the peripherals is always on.

Table 13−2. New or Modified Features/Peripherals in 240xA DSPs

New/Modified Features/Peripherals in 240xA Reference Document/Chapter

1 Flash Memory Map and Flash Wrapper Chapter 13

TMS320LF2407A, TMS320LF2406A,
TMS320LF2403A, TMS320LF2402A,
2 On-Chip SARAM TMS320LC2406A, TMS320LC2404A,
TMS320LC2402A DSP Controllers Data Sheet
(literature number SPRS145)

3 Peripheral Register Map Appendix A

4 ADC Chapter 7

5 Interrupt Vector Table Chapter 2

6 PIE (Peripheral Interrupt Expansion Unit) Chapter 2

7 EVB (Event Manager B) Chapter 6

8 Digital I/O Chapter 5

9 PLL Chapter 4

For additional reference materials, see the application report 3.3-V DSP for
Digital Motor Control (literature number SPRA550) or go to http://www.ti.com
and search for a list of 24x application notes.

240xA-24x Family Compatibility 13-3

24x-240xA DSP Overview

13.2 24x-240xA DSP Overview

Table 13−3. Features of 24x and 240xA DSPs
Device Feature LF2407A LF2406A LF2402A 24x (F243)
C2xLP CPU Core Yes Yes Yes Yes

CSM Yes Yes Yes No

DARAM 544 words 544 words 544 words 544 words

SARAM −
2K words 2K words 512 words −
Program/Data

3.3-V Core 3.3-V Core 3.3-V Core 5-V Core

Operating Voltage
3.3-V I/O 3.3-V I/O 3.3-V I/O 5-V I/O

Flash 32K x 16 32K x 16 8K x 16 8K x 16

Sectors 4K/12K/12K/4K 4K/12K/12K/4K 2 x 4K None

Boot ROM Yes Yes Yes −

Event Manager: EVA Yes Yes Yes EV2

Event Manager: EVB Yes Yes − −

CAN Yes Yes − Yes

SPI Yes Yes − Yes

SCI Yes Yes Yes Yes

10-bit ADC Channels 16 16 8 8

WD Yes Yes Yes Yes

40 − Shared with 39 − Shared with 16 − Shared with

General-Purpose 26 − Shared with
other functions other functions other functions
Digital I/O other functions
1 − Dedicated to I/O 2 − Dedicated to I/O 5 − Dedicated to I/O

PDPINTA, PDPINTA,
PDPINT, XINT1,
External Interrupts PDPINTB, XINT1, PDPINTB, XINT1, PDPINTA, XINT2
XINT2, NMI
XINT2 XINT2

External Memory IF Yes No No Yes

Package 144 LQFP 100 LQFP 64 TQFP 144 LQFP

Notes: 1) See the TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A, TMS320LC2406A,

TMS320LC2404A, TMS320LC2402A DSP Controllers Data Sheet (SPRS145) for LF (Flash) and LC (ROM) de-
vice details.
2) F243 and LF2407A are not pin-compatible.
3) 240xA ADC is not compatible with 24x ADC.

13-4
 Memory Map

13.3 Memory Map

13.3.1 Program Space

Figure 13−1. LF2407A Memory Map for Program Space

0000 Flash Block Details
Interrupt Vectors
003F 0000
0040 4K Sector
Security Passwords 0FFF
0043
0044 1000
00FF
0100 12K Sector

3FFF
4000

12K Sector
7FFF
8000 6FFF
SARAM 7000
2K words 4K Sector
(Program/Data) 7FFF
87FF
8800

External
(off-chip)

FDFF
FE00
DARAM (B0)
256 words
(CNF=1)
FEFF 32K on-chip Flash memory
FF00 Note: (External if MP/MC = 1)
DARAM (B0)
(CNF=1)
FFFF

Note: When boot ROM is enabled, on-chip locations 0000−00FFh in program memory is mapped to the bootloader. Boot ROM
and Flash Memory share the same starting address, and hence, are not visible (active) at the same time. If the BOOT
EN/XF pin = 0 during reset, the BOOT EN bit in SCSR2 register (bit 3) will be set and enable the Boot ROM at 0000 in
program space. While Boot ROM is enabled, the entire Flash memory will be disabled. The SCSR2.3 bit should be dis-
abled (0) to have Flash array enabled instead of Boot ROM. See Appendix D for bootloader details.

240xA-24x Family Compatibility 13-5

System Features

13.4 System Features

This section presents some of the system features that are new to the 240xA
devices. Understanding these key features will help with system initialization
and 24x-to-240xA migration.

13.4.1 Oscillator and PLL

Unlike the 24x device, the 240xA devices have a 5-pin PLL with a 3-bit ratio
control to provide eight different CPU clock options. Table 13−4 describes the
pins that are used for the PLL/Oscillator module and Table 13−5 lists the
oscillator/PLL frequency input specification. PLL is preceded by an on-chip
oscillator which can accept a resonator or a crystal. The PLL accepts the
on-chip oscillator or external clock as its input clock. Refer to
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A,
TMS320LC2406A, TMS320LC2404A, TMS320LC2402A DSP Controllers
Data Sheet (literature number SPRS145) for clock circuits and recommended
values for the external filter components.

Table 13−4. 240xA PLL Pin Names

Pin Names Description

Oscillator input, crystal and ceramic resonator input, or

XTAL1/CLKIN
external clock input

XTAL2 Used only by crystal or ceramic resonators as an output

PLLF PLL loop filter terminal 1

PLLVCCA PLL supply (3.3 V)

PLLF2 PLL loop filter terminal 2

Table 13−5. Oscillator/PLL Frequency Input Specification

Value

Input crystal frequency range 4−20 MHz

Input ceramic resonator frequency range 4−13 MHz

Input oscillator/CLOCKIN frequency range 4−20 MHz

13-6
 System Features

13.4.2 Watchdog Clock

Watchdog clock generation logic is different in 240xA devices with respect to
24x devices. Unlike the fixed PLL (x4) in 24x, the 240xA devices have a
variable clock from the PLL. This changes the input clock options for the
watchdog module. The clock flow diagram below explains the watchdog clock
generation logic.

240xA devices have a watchdog override bit in the SCSR2 register, which is
similar to the WDDIS pin available on the 24x devices. Refer to the description
of SCSR2 register bit 5 (section 2.2.1 on page 2-3) for details on this bit
function.

Figure 13−2. 240xA Watchdog Clock Generation Logic

Oscillator clock/
External clock

CLKOUT WDCLK

PLL 3-bit ratio selector /512 Watchdog module

13.4.2.1 Other Low-Power Management Features

All 240xA devices have a clock-enable bit in the SCSR1 register to save power
and selectively enable peripheral functions. At reset, these peripheral
clock-enable bits are disabled, and the applications software should enable
the required modules. The peripheral clocks of the following peripherals can
be independently enabled/disabled. See section 2.2.1 on page 2-3 for bit
descriptions of the SCSR1 register.

Table 13−6. Peripheral Clock Enable Bits

Peripheral SCSR1 Bits Description

EVA SCSR1.2 Event Manager A

EVB SCSR1.3 Event Manager B

CAN SCSR1.4 Controller Area Network

SPI SCSR1.5 Serial Peripheral Interface

SCI SCSR1.6 Serial Communications Interface

ADC SCSR1.7 Analog-to-Digital Converter

240xA-24x Family Compatibility 13-7

System Features

13.4.3 System Control Registers

240xA devices have two system control and status registers: SCSR1 and
SCSR2 (see section 2.2.1 on page 2-3). These registers have control and
status bits for several on-chip modules. These register bits should be
initialized after reset to enable/disable on-chip functionality for the selected
application. 24x has only one SCSR register and all its on-chip peripherals are
powered up after reset. The SCSR2 register is unique to 240xA and its
peripherals are disabled after reset.

13.4.3.1 Boot EN/XF Pin Operation

During the Reset phase (i.e., RS low), this pin functions as a Boot EN input pin,
and its logic level is latched into bit 3 of the SCSR2 register. If the bit is set to 1,
Boot ROM is active.

At the completion of the reset phase (rising edge of RS), this pin will be XF
output (external flag) function, and the Boot EN function is no longer available
through this pin. However, the Boot EN bit in SCSR2 can be used to control
the visibility of the Boot ROM or the Flash array.

Figure 13−3. Functional Block Diagram for Boot EN/XF Feature

SCSR2 Boot En
Boot EN

Boot EN/XF
pin
XF (from core)

RS

Program Memory Boot EN Pin /

Operating Mode Comment
Active for the CPU SCSR2 Bit 3

Can be changed later by

Functional Boot ROM: 0x0000−0x00FF 0
software bit in SCSR2

Can be changed later by

Functional Flash Array: 0x0000−0x7FFF 1
software bit in SCSR2

13-8
 System Features

13.4.3.2 Fast RD Strobe Operation

LF2407 is the only device that supports external memory interface (XMIF) to
expand the internal memory space with the addition of external memory
devices. The interface offers decode signals for Program, Data, and I/O space.
LF2407 external memory interface signals have critical timings while
interfacing zero-wait-state memory at higher CPU clock speeds. CPU memory
reads are single-cycle and read-enable (RD) timing is critical to meet the
output-enable timing for memories that can be interfaced to this device. To
alleviate the memory read interface timing, an additional signal W/R is
provided to be used as output-enable signal instead of RD. W/R is essentially
an inverted R/W signal from the core.

In the LF2407A device, the W/R signal will remain low all the time after reset
and will go high during external write cycles. In other LF240xA devices, the
W/R signal will remain low all the time after reset until the application
configures it as a GPIO pin and drives it to the desired level. During reset, this
pin floats and gets pulled up by the internal pullup circuitry. If an application
needs this pin to be low even during reset, then an external pulldown resistor
may be added.

In LC240xA devices, the W/R signal will remain “pulled up” all the time from
reset until the application configures it as a GPIO pin and drives it to the desired
level.

See the External Memory Interface timings in the TMS320LF2407A,

TMS320LF2406A, TMS320LF2403A, TMS320LF2402A, TMS320LC2406A,
TMS320LC2404A, TMS320LC2402A DSP Controllers data sheet (literature
number SPRS145).

240xA-24x Family Compatibility 13-9

System Features

Figure 13−4. Functional Block Diagram of XMIF Signals on LF2407

External pins

Address bus
A0−A15
C2xx
CPU
core
Data bus
D0−D15

XMIF
module
Control bus
PS, DS, IS,
STRB,
R/W, WR

RD
RD

R/W
W/R/IOPC0

LF2407 DSP

13-10
 Digital I/O (GPIO Pins)

13.5 Digital I/O (GPIO Pins)

Some members of the 240xA family have more GPIO pins than the 24x
devices. This necessitates additional registers. The bit definitions for some
multiplexed pins such as XF, CLKOUT, etc. are different from those of the 24x.
See Chapter 5 for more details.

Note that when multiplexed I/O pins are in input mode, the pin is connected
to both the I/O data register and the shared peripheral. The I/O Mux control
register (MCRx) in 240xA devices is synonymous to the OCRx in 24x devices.
Both MCRx and OCRx have the same function in 240xA and 24x devices,
respectively.

13.5.1 Digital I/O and Shared Pin Functions for the 240xA
LF2407 device has a total of 41 pins shared between primary functions and
I/Os.

Table 13−7 lists all the pins that are shared between the primary functions and
the dedicated I/O Ports A, B, C, D, E, F.

240xA-24x Family Compatibility 13-11

Digital I/O (GPIO Pins)

Table 13−7. LF2407A Shared Pin Configuration

Shared Pin Functions IOP Data

Mux Mux MCRx.n IOP
and IOP Data
Primary Control Control Value at Direction
I/O (0) Direction Bit #
Function (1) Register Bit # Reset Bit #
Register
SCITXD IOPA0 MCRA 0 0 PADATDIR 0 8

SCIRXD IOPA1 MCRA 1 0 PADATDIR 1 9

XINT1 IOPA2 MCRA 2 0 PADATDIR 2 10

CAP1/QEP1 IOPA3 MCRA 3 0 PADATDIR 3 11

CAP2/QEP2 IOPA4 MCRA 4 0 PADATDIR 4 12

CAP3 IOPA5 MCRA 5 0 PADATDIR 5 13

PWM1 IOPA6 MCRA 6 0 PADATDIR 6 14

PWM2 IOPA7 MCRA 7 0 PADATDIR 7 15

PWM3 IOPB0 MCRA 8 0 PBDATDIR 0 8

PWM4 IOPB1 MCRA 9 0 PBDATDIR 1 9

PWM5 IOPB2 MCRA 10 0 PBDATDIR 2 10

PWM6 IOPB3 MCRA 11 0 PBDATDIR 3 11

T1PWM/CMP IOPB4 MCRA 12 0 PBDATDIR 4 12

T2PWM/CMP IOPB5 MCRA 13 0 PBDATDIR 5 13

TDIRA IOPB6 MCRA 14 0 PBDATDIR 6 14

TCLKINA IOPB7 MCRA 15 0 PBDATDIR 7 15

W/R IOPC0 MCRB 0 1 PCDATDIR 0 8

BIO IOPC1 MCRB 1 1 PCDATDIR 1 9

SPISIMO IOPC2 MCRB 2 0 PCDATDIR 2 10

SPISOMI IOPC3 MCRB 3 0 PCDATDIR 3 11

SPICLK IOPC4 MCRB 4 0 PCDATDIR 4 12

SPISTE IOPC5 MCRB 5 0 PCDATDIR 5 13

CANTX IOPC6 MCRB 6 0 PCDATDIR 6 14

CANRX IOPC7 MCRB 7 0 PCDATDIR 7 15

13-12
 Digital I/O (GPIO Pins)

Table 13−7. LF2407A Shared Pin Configuration (Continued)

Shared Pin Functions IOP Data

Mux Mux MCRx.n IOP
and IOP Data
Primary Control Control Value at Direction
I/O (0) Direction Bit #
Function (1) Register Bit # Reset Bit #
Register
XINT2/ADCSOC IOPD0 MCRB 8 0 PDDATDIR 0 8

EMU0 IOPD1 Reserved 9 1 PDDATDIR − −

EMU1 IOPD2 Reserved 10 1 PDDATDIR − −

TCK IOPD3 Reserved 11 1 PDDATDIR − −

TDI IOPD4 Reserved 12 1 PDDATDIR − −

TDO IOPD5 Reserved 13 1 PDDATDIR − −

TMS IOPD6 Reserved 14 1 PDDATDIR − −

TMS2 IOPD7 Reserved 15 1 PDDATDIR − −

CLKOUT IOPE0 MCRC 0 1 PEDATDIR 0 8

PWM7 IOPE1 MCRC 1 0 PEDATDIR 1 9

PWM8 IOPE2 MCRC 2 0 PEDATDIR 2 10

PWM9 IOPE3 MCRC 3 0 PEDATDIR 3 11

PWM10 IOPE4 MCRC 4 0 PEDATDIR 4 12

PWM11 IOPE5 MCRC 5 0 PEDATDIR 5 13

PWM12 IOPE6 MCRC 6 0 PEDATDIR 6 14

CAP4/QEP3 IOPE7 MCRC 7 0 PEDATDIR 7 15

CAP5/QEP4 IOPF0 MCRC 8 0 PFDATDIR 0 8

CAP6 IOPF1 MCRC 9 0 PFDATDIR 1 9

T3PWM/CMP IOPF2 MCRC 10 0 PFDATDIR 2 10

T4PWM/CMP IOPF3 MCRC 11 0 PFDATDIR 3 11

TDIRB IOPF4 MCRC 12 0 PFDATDIR 4 12

TCLKINB IOPF5 MCRC 13 0 PFDATDIR 5 13

IOPF6 IOPF6 X X X PFDATDIR 6 14

240xA-24x Family Compatibility 13-13

Event Manager Module (EVB)

13.6 Event Manager Module (EVB)

The event manager module available on 240xA devices is identical to the
event manager in the 24x family. EVA and EVB are exactly identical modules,
except that their registers start at 7400h and 7500h, respectively, in the
peripheral space. The functional description of the event manager, available
in the TMS320F243/F241/C242 DSP Controllers Reference Guide (literature
number SPRU276C), is applicable to EVB as well. EVA and EVB modules and
signals are uniquely identified and in Table 13−8 for comparison.

Table 13−8. Event Manager Module and Signal Names for EVA and EVB

EV Modules EVA Modules EVA Pins EVB Modules EVB Pins

Timer 1 T1PWM/T1CMP Timer 3 T3PWM/T3CMP
GP Timers
Timer 2 T2PWM/T2CMP Timer 4 T4PWM/T4CMP

Compare 1 PWM1/2 Compare 4 PWM7/8

Compare Units Compare 2 PWM3/4 Compare 5 PWM9/10

Compare 3 PWM5/6 Compare 6 PWM11/12

Capture 1 CAP1 Capture 4 CAP4

Capture Units Capture 2 CAP2 Capture 5 CAP5

Capture 3 CAP3 Capture 6 CAP6

QEP 1 QEP1 QEP 3 QEP3

QEP
QEP 2 QEP2 QEP 4 QEP4

Direction TDIRA Direction TDIRB

External Inputs
External Clock TCLKINA External Clock TCLKINB

13.6.1 Input Qualification Circuitry

Some pins in the EV have an “input qualification” circuitry. See the

 
 
 
  ,

 
 
    Data Sheet
(literature number SPRS145) for more details.

13-14
240xA-24x Family Compatibility 13-15
 Appendix
AppendixAA

* 1  

This document was revised to SPRU357C from SPRU357B.

The scope of the revisions was limited to adding technical changes as

described on the next page.

A-1
Changes Made in This Revision

A.1 Changes Made in This Revision

The following changes were made in this revision:

Page Additions/Modifications/Deletions

v Updated Related Documentation section

vvii Added Trademarks

1-5 Modified the bullets in Section 1.3

1-7 Added LF2401A and LC2401A to Table 1−1

1-9 Added note to Figure 1−1

2-2 Modified last sentence in the second paragraph of Section 2.1.

2-5 Changed the description of Bit 0 of SCSR1 Register.

2-6 Changed the description of Bit 5 of SCSR2 Register

2-8 Changed the description of Bits 3−0 in DINR Register

2-19 Added new data to Section 2.5.3, Nonmaskable Interrupt (NMI)

3-17 Modified first paragraph in Section 3.11.2

4-9 Modified Table 4−1 in the Exit Condiiton column

5-2 Replaced Figure 5−1, Shared Pin Configuration.

5-7 Changed secondary pin function of Bit 14, IOPF6 in the MCRC Register to reserved

5-7 Added a note to Table 5−4

6-39 Changed the first paragraph of Section 6.4, Compare Units

6-39 Modified Figure 6−12, Compare Unit Block Diagram

6-40 Modified first paragraph on page 6-40, changing GP timer 2 to GP timer 3

6-43 Changed description of Bit 8 of the COMCONA Register

6-44 Changed description of Bit 8 of the COMCONB Register

6-47 Corrected register names in Section 6.4.2, Compare Unit Interrupts

6-48 Modified Figure 6−17

6-54 Modified Figure 6−20

6-61 Added Section 6.6.56.6.5, Double Update PWM Mode

6-70 Modified Figure 6−31, Capture Units Block Diagram (EVB)

A-2
 Changes Made in This Revision

Page Additions/Modifications/Deletions

6-71 Added a sentence to the fifth (second on page 6-71) bullet in Section 6.8.1, Capture Unit
Features

6-71 Added to first paragraph in Section 6.8.2, Operation of Capture Units

6-72 Changed first paragraph in Section 6.8.3, Capture Unit Registers

6-72 Changed the CAPQEPN field (14:13) to CAP12EN bit in Figure 6−32

Deleted “and QEP circuit” from description of Bit 15 in CAPCONA Register (Figure 6−32)

6-74 Changed name and description of Bits 14−13 of CAPCONB Register (Figure 6−30)

6.9 Modified Section 6.9, first paragraph

6-80 Modified Section 6.9.1, QEP Pins

6-80 Replaced Figure 6−36

6-81 Replaced Figure 6−34

6-82, Modified lists in Section 6.9.5, Register Setup for the QEP Circuit
6-83

7-2 Modified second bullet item (conversion time rates) in Section 7.1, Features

7-5 Modified Figure 7−1

7-6 Modified Figure 7−2

7-34 Added a note to description of bits 3−0 of AUTO_SEQ_SR Register

7-37 Added a note to Figure 7−14

7-38 Added data sheet nomenclature column to Table 7−9

8-23 Modified description of Bit 6 of RX ERR INT ENA in Figure 8−11

8-28 Modified first paragraph of Section 8.7.5, Receiver Status Register (SCIRXST)

9-6 Changed bits from “illegal” to “reserved” in Table 9−1

9-9 Modified last paragraph in Master Mode

9-24 Modified description of bits 6:0 in Figure 9−10

9-35 Modified title of Figure 9−21

10-17 Modified description of bit 15 in Figure 10−9

10-24 Modified description of bit 9 (WUBA) in Figure 10−14

10-27 Modified descriptions for Bits 10−0 in BCR1 Register (Figure 10−16)

Revision History A-3

Changes Made in This Revision

Page Additions/Modifications/Deletions

10-29 Modified Figure 10−17

10-29 Replaced Table 10−4

11-10 Changed description of Bit 6 in the WDCR Register (Figure 11−4) and changed reset information
on bits 5:3

12-2 Added new first paragraph and new last paragraph to Section 12.1

12-3 Added a new bullet item to port code instructions in Section 12.2

13-4 Added a row to Table 13−3 for the CSM

13-9 Modified Section 13.4.3.2, Fast RD Strobe Operation

13-14 Added Section 13.6.1, Input Qualification Circuitry

C-24 Replaced code for REM_ANS.asm and REM_REQ.asm

D-12 Replaced code for BOOT.asm

A-4
 Appendix
AppendixBA

$  
  ,   

Table B−1 starting on page B-2 shows the peripheral register map for 240xA
devices. The shaded table entries represent the registers that are in addition
to the 24x registers. These additions are also explained in the data sheet titled
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A,
TMS320LC2406A, TMS320LC2404A, TMS320LC2402A DSP Controllers
(literature number SPRS145), and TMS320LF2401A DSP Controller
(literature number SPRS161). Note that:

The ADC registers are completely different from those in the 24x.

The ADC register map has been moved from 7030h to 70A0h.

The second event manager (EVB) has been placed at 7500h.

Table B−2 on page B-9 shows the code security module (CSM) registers.

B-1
Summary of Programmable Registers on the 240xA

Table B−1. Summary of Programmable Registers on the 240xA

Data Memory Register

Address Mnemonic Register Name Data Page Page
Interrupt and System
7010h PIRQR0 Peripheral Interrupt Request Register 0 E0h (224) 2-31
7011h PIRQR1 Peripheral Interrupt Request Register 1 E0h (224) 2-32
7012h PIRQR2 Peripheral Interrupt Request Register 2 E0h (224) 2-33
7014h PIACKR0 Peripheral Interrupt Acknowledge E0h (224) 2-34
Register 0
7015h PIACKR1 Peripheral Interrupt Acknowledge E0h (224) 2-35
Register 1
7016h PIACKR2 Peripheral Interrupt Acknowledge E0h (224) 2-36
Register 2
7018h SCSR1 System Control and Status Register 1 E0h (224) 2-3
7019h SCSR2 System Control and Status Register 2 E0h (224) 2-5
701Ch DINR Device Identification Number Register E0h (224) 2-8
701Eh PIVR Peripheral Interrupt Vector Register E0h (224) 2-30
Watchdog
7023h WDCNTR Watchdog Counter Register E0h (224) 11-8
7025h WDKEY Watchdog Reset Key Register E0h (224) 11-9
7029h WDCR Watchdog Timer Control Register E0h (224) 11-9
Serial Peripheral Interface (SPI)
7040h SPICCR SPI Configuration Control Register E0h (224) 9-19
7041h SPICTL SPI Operation Control Register E0h (224) 9-21
7042h SPISTS SPI Status Register E0h (224) 9-22
7044h SPIBRR SPI Baud Rate Register E0h (224) 9-24
7046h SPIRXEMU SPI Emulation Buffer Register E0h (224) 9-25
7047h SPIRXBUF SPI Serial Receive Buffer Register E0h (224) 9-26
7048h SPITXBUF SPI Serial Transmit Buffer Register E0h (224) 9-27
7049h SPIDAT SPI Serial Data Register E0h (224) 9-28
704Fh SPIPRI SPI Priority Control Register E0h (224) 9-29
Serial Communications Interface (SCI)
7050h SCICCR SCI Communication Control Register E0h (224) 8-21
7051h SCICTL1 SCI Control Register 1 E0h (224) 8-23
7052h SCIHBAUD SCI Baud-Select Register, high bits E0h (224) 8-26
7053h SCILBAUD SCI Baud-Select Register, low bits E0h (224) 8-26

B-2
 Summary of Programmable Registers on the 240xA

Table B−1. Summary of Programmable Registers on the 240xA (Continued)

Data Memory Register
Address Mnemonic Register Name Data Page Page
7054h SCICTL2 SCI Control Register 2 E0h (224) 8-27
7055h SCIRXST SCI Receiver Status Register E0h (224) 8-28
7056h SCIRXEMU SCI Emulation Data Buffer Register E0h (224) 8-31
7057h SCIRXBUF SCI Receiver Data Buffer Register E0h (224) 8-31
7059h SCITXBUF SCI Transmit Data Buffer Register E0h (224) 8-31
705Fh SCIPRI SCI Priority Control Register E0h (224) 8-32
External Interrupt
7070h XINT1CR External Interrupt 1 Control Register E0h (224) 2-39
7071h XINT2CR External Interrupt 2 Control Register E0h (224) 2-40
Digital I/O
7090h MCRA I/O Mux Control Register A E1h (225) 5-4
7092h MCRB I/O Mux Control Register B E1h (225) 5-5
7094h MCRC I/O Mux Control Register C E1h (225) 5-7
7098h PADATDIR Port A Data and Direction Control E1h (225) 5-8
Register
709Ah PBDATDIR Port B Data and Direction Control E1h (225) 5-9
Register
709Ch PCDATDIR Port C Data and Direction Control E1h (225) 5-10
Register
709Eh PDDATDIR Port D Data and Direction Control E1h (225) 5-11
Register
7095h PEDATDIR Port E Data and Direction Control E1h (225) 5-12
Register
7096h PFDATDIR Port F Data and Direction Control E1h (225) 5-13
Register
Analog-to-Digital Converter (ADC) (10-Bit)
70A0h ADCTRL1 ADC Control Register 1 E1h (225) 7-20
70A1h ADCTRL2 ADC Control Register 2 E1h (225) 7-26
70A2h MAX CONV Maximum Conversion Channels E1h (225) 7-31
Register
70A3h CHSELSEQ1 Channel Select Sequencing Control E1h (225) 7-35
Register 1
70A4h CHSELSEQ2 Channel Select Sequencing Control E1h (225) 7-35
Register 2

Programmable Register Address Summary B-3

Summary of Programmable Registers on the 240xA

Table B−1. Summary of Programmable Registers on the 240xA (Continued)

Data Memory Register
Address Mnemonic Register Name Data Page Page
70A5h CHSELSEQ3 Channel Select Sequencing Control E1h (225) 7-35
Register 3
70A6h CHSELSEQ4 Channel Select Sequencing Control E1h (225) 7-35
Register 4
70A7h AUTO_SEQ_SR Autosequence Status Register E1h (225) 7-33
70A8h RESULT0 Conversion Result Buffer Register 0 E1h (225) −
70A9h RESULT1 Conversion Result Buffer Register 1 E1h (225) −
70AAh RESULT2 Conversion Result Buffer Register 2 E1h (225) −
70ABh RESULT3 Conversion Result Buffer Register 3 E1h (225) −
70ACh RESULT4 Conversion Result Buffer Register 4 E1h (225) −
70ADh RESULT5 Conversion Result Buffer Register 5 E1h (225) −
70AEh RESULT6 Conversion Result Buffer Register 6 E1h (225) −
70AFh RESULT7 Conversion Result Buffer Register 7 E1h (225) −
70B0h RESULT8 Conversion Result Buffer Register 8 E1h (225) −
70B1h RESULT9 Conversion Result Buffer Register 9 E1h (225) −
70B2h RESULT10 Conversion Result Buffer Register 10 E1h (225) −
70B3h RESULT11 Conversion Result Buffer Register 11 E1h (225) −
70B4h RESULT12 Conversion Result Buffer Register 12 E1h (225) −
70B5h RESULT13 Conversion Result Buffer Register 13 E1h (225) −
70B6h RESULT14 Conversion Result Buffer Register 14 E1h (225) −
70B7h RESULT15 Conversion Result Buffer Register 15 E1h (225) −
70B8h CALIBRATION Calibration result which is used to E1h (225) −
correct subsequent conversions
Controller Area Network (CAN)
7100h MDER Mailbox Direction/Enable Register E2h (226) 10-19
7101h TCR Transmission Control Register E2h (226) 10-20
7102h RCR Receive Control Register E2h (226) 10-22
7103h MCR Master Control Register E2h (226) 10-23
7104h BCR2 Bit Configuration Register 2 E2h (226) 10-26
7105h BCR1 Bit Configuration Register 1 E2h (226) 10-27
7106h ESR Error Status Register E2h (226) 10-30
7107h GSR Global Status Register E2h (226) 10-32
7108h CEC Transmit and Receive Error Counters E2h (226) 10-34

B-4
 Summary of Programmable Registers on the 240xA

Table B−1. Summary of Programmable Registers on the 240xA (Continued)

Data Memory Register
Address Mnemonic Register Name Data Page Page
7109h CAN IFR Interrupt Flag Register E2h (226) 10-36
710Ah CAN IMR Interrupt Mask Register E2h (226) 10-38
710Bh LAM0_H Local Acceptance Mask E2h (226) 10-17
(MBOX 0 and MBOX 1)
710Ch LAM0_L Local Acceptance Mask E2h (226) 10-18
(MBOX 0 and MBOX 1)
710Dh LAM1_H Local Acceptance Mask E2h (226) 10-17
(MBOX 2 and MBOX 3)
710Eh LAM1_L Local Acceptance Mask E2h (226) 10-18
(MBOX 2 and MBOX 3)
7200h MSGID0L CAN Message ID for Mailbox 0 E4h (228) 10-11
(lower 16 bits)
7201h MSGID0H CAN Message ID for Mailbox 0 E4h (228) 10-10
(upper 16 bits)
7202h MSGCTRL0 MBOX 0 RTR and DLC E4h (228) 10-11
7204h MBOX0A CAN 2 of 8 bytes of Mailbox 0 E4h (228) −
7205h MBOX0B CAN 2 of 8 bytes of Mailbox 0 E4h (228) −
7206h MBOX0C CAN 2 of 8 bytes of Mailbox 0 E4h (228) −
7207h MBOX0D CAN 2 of 8 bytes of Mailbox 0 E4h (228) −
7208h MSGID1L CAN Message ID for mailbox 1 E4h (228) 10-11
(lower 16 bits)
7209h MSGID1H CAN Message ID for mailbox 1 E4h (228) 10-10
(upper 16 bits)
720Ah MSGCTRL1 MBOX 1 RTR and DLC E4h (228) 10-11
720Ch MBOX1A CAN 2 of 8 bytes of Mailbox 1 E4h (228) −
720Dh MBOX1B CAN 2 of 8 bytes of Mailbox 1 E4h (228) −
720Eh MBOX1C CAN 2 of 8 bytes of Mailbox 1 E4h (228) −
720Fh MBOX1D CAN 2 of 8 bytes of Mailbox 1 E4h (228) −
7210h MSGID2L CAN Message ID for mailbox 2 E4h (228) 10-11
(lower 16 bits)
7211h MSGID2H CAN Message ID for mailbox 2 E4h (228) 10-10
(upper 16 bits)
7212h MSGCTRL2 MBOX 2 RTR and DLC E4h (228) 10-11
7214h MBOX2A CAN 2 of 8 bytes of Mailbox 2 E4h (228) −
7215h MBOX2B CAN 2 of 8 bytes of Mailbox 2 E4h (228) −

Programmable Register Address Summary B-5

Summary of Programmable Registers on the 240xA

Table B−1. Summary of Programmable Registers on the 240xA (Continued)

Data Memory Register
Address Mnemonic Register Name Data Page Page
7216h MBOX2C CAN 2 of 8 bytes of Mailbox 2 E4h (228) −
7217h MBOX2D CAN 2 of 8 bytes of Mailbox 2 E4h (228) −
7218h MSGID3L CAN Message ID for Mailbox 3 E4h (228) 10-11
(lower 16 bits)
7219h MSGID3H CAN Message ID for Mailbox 3 E4h (228) 10-10
(upper 16 bits)
721Ah MSGCTRL3 MBOX 3 RTR and DLC E4h (228) 10-11
721Ch MBOX3A CAN 2 of 8 bytes of Mailbox 3 E4h (228) −
721Dh MBOX3B CAN 2 of 8 bytes of Mailbox 3 E4h (228) −
721Eh MBOX3C CAN 2 of 8 bytes of Mailbox 3 E4h (228) −
721Fh MBOX3D CAN 2 of 8 bytes of Mailbox 3 E4h (228) −
7220h MSGID4L CAN Message ID for Mailbox 4 E4h (228) 10-11
(lower 16 bits)
7221h MSGID4H CAN Message ID for Mailbox 4 E4h (228) 10-10
(upper 16 bits)
7222h MSGCTRL4 MBOX 4 RTR and DLC E4h (228) 10-11
7224h MBOX4A CAN 2 of 8 bytes of Mailbox 4 E4h (228) −
7225h MBOX4B CAN 2 of 8 bytes of Mailbox 4 E4h (228) −
7226h MBOX4C CAN 2 of 8 bytes of Mailbox 4 E4h (228) −
7227h MBOX4D CAN 2 of 8 bytes of Mailbox 4 E4h (228) −
7228h MSGID5L CAN Message ID for Mailbox 5 E4h (228) 10-11
(lower 16 bits)
7229h MSGID5H CAN Message ID for Mailbox 5 E4h (228) 10-10
(upper 16 bits)
722Ah MSGCTRL5 MBOX 5 RTR and DLC E4h (228) 10-11
722Ch MBOX5A CAN 2 of 8 bytes of Mailbox 5 E4h (228) −
722Dh MBOX5B CAN 2 of 8 bytes of Mailbox 5 E4h (228) −
722Eh MBOX5C CAN 2 of 8 bytes of Mailbox 5 E4h (228) −
722Fh MBOX5D CAN 2 of 8 bytes of Mailbox 5 E4h (228) −
Event Manager A (EVA)
7400h GPTCONA GP Timer Control Register A E8h (232) 6-35
7401h T1CNT Timer 1 Counter Register E8h (232) −
7402h T1CMPR Timer 1 Compare Register E8h (232) −
7403h T1PR Timer 1 Period Register E8h (232) −

B-6
 Summary of Programmable Registers on the 240xA

Table B−1. Summary of Programmable Registers on the 240xA (Continued)

Data Memory Register
Address Mnemonic Register Name Data Page Page
7404h T1CON Timer 1 Control Register E8h (232) 6-33
7405h T2CNT Timer 2 Counter Register E8h (232) −
7406h T2CMPR Timer 2 Compare Register E8h (232) −
7407h T2PR Timer 2 Period Register E8h (232) −
7408h T2CON Timer 2 Control Register E8h (232) 6-33
7411h COMCONA Compare Control Register A E8h (232) 6-42
7413h ACTRA Compare Action Control Register A E8h (232) 6-44
7415h DBTCONA Dead-Band Timer Control Register A E8h (232) 6-50
7417h CMPR1 Compare Register 1 E8h (232) −
7418h CMPR2 Compare Register 2 E8h (232) −
7419h CMPR3 Compare Register 3 E8h (232) −
7420h CAPCONA Capture Control Register A E8h (232) 6-72
7422h CAPFIFOA Capture FIFO Status Register A E8h (232) 6-76
7423h CAP1FIFO Two-Level-Deep Capture FIFO stack 1 E8h (232) −
7424h CAP2FIFO Two-Level-Deep Capture FIFO stack 2 E8h (232) −
7425h CAP3FIFO Two-Level-Deep Capture FIFO stack 3 E8h (232) −
7427h CAP1FBOT Bottom Register of Capture FIFO E8h (232) −
stack 1
7428h CAP2FBOT Bottom Register of Capture FIFO E8h (232) −
stack 2
7429h CAP3FBOT Bottom Register of Capture FIFO E8h (232) −
stack 3
742Ch EVAIMRA EVA Interrupt Mask Register A E8h (232) 6-91
742Dh EVAIMRB EVA Interrupt Mask Register B E8h (232) 6-92
742Eh EVAIMRC EVA Interrupt Mask Register C E8h (232) 6-93
742Fh EVAIFRA EVA Interrupt Flag Register A E8h (232) 6-87
7430h EVAIFRB EVA Interrupt Flag Register B E8h (232) 6-89
7431h EVAIFRC EVA Interrupt Flag Register C E8h (232) 6-90
Event Manager B (EVB)
7500h GPTCONB GP Timer Control Register B EAh (234) 6-36
7501h T3CNT Timer 3 Counter Register EAh (234) −
7502h T3CMPR Timer 3 Compare Register EAh (234) −
7503h T3PR Timer 3 Period Register EAh (234) −

Programmable Register Address Summary B-7

Summary of Programmable Registers on the 240xA

Table B−1. Summary of Programmable Registers on the 240xA (Continued)

Data Memory Register
Address Mnemonic Register Name Data Page Page
7504h T3CON Timer 3 Control Register EAh (234) 6-33
7505h T4CNT Timer 4 Counter Register EAh (234) −
7506h T4CMPR Timer 4 Compare Register EAh (234) −
7507h T4PR Timer 4 Period Register EAh (234) −
7508h T4CON Timer 4 Control Register EAh (234) 6-33
7511h COMCONB Compare Control Register B EAh (234) 6-43
7513h ACTRB Compare Action Control Register B EAh (234) 6-46
7515h DBTCONB Dead-Band Timer Control Register B EAh (234) 6-51
7517h CMPR4 Compare Register 4 EAh (234) −
7518h CMPR5 Compare Register 5 EAh (234) −
7519h CMPR6 Compare Register 6 EAh (234) −
7520h CAPCONB Capture Control Register B EAh (234) 6-74
7522h CAPFIFOB Capture FIFO Status Register B EAh (234) 6-77
7523h CAP4FIFO Two-Level-Deep Capture FIFO stack 4 EAh (234) −
7524h CAP5FIFO Two-Level-Deep Capture FIFO stack 5 EAh (234) −
7525h CAP6FIFO Two-Level-Deep Capture FIFO stack 6 EAh (234) −
7527h CAP4FBOT Bottom Register of Capture FIFO EAh (234) −
stack 4
7528h CAP5FBOT Bottom Register of Capture FIFO EAh (234) −
stack 5
7529h CAP6FBOT Bottom Register of Capture FIFO EAh (234) −
stack 6
752Ch EVBIMRA EVB Interrupt Mask Register A EAh (234) 6-98
752Dh EVBIMRB EVB Interrupt Mask Register B EAh (234) 6-99
752Eh EVBIMRC EVB Interrupt Mask Register C EAh (234) 6-100
752Fh EVBIFRA EVB Interrupt Flag Register A EAh (234) 6-94
7530h EVBIFRB EVB Interrupt Flag Register B EAh (234) 6-96
7531h EVBIFRC EVB Interrupt Flag Register C EAh (234) 6-97
IO-FF0Fh FCMR Flash Control Mode Register EAh (234) −
IO-FFFFh WSGR Wait State Generator Register EAh (234) 3-18

B-8
 Summary of Programmable Registers on the 240xA

Table B−2. Code Security Module (CSM) Registers

Data Memory
Address Register Name Reset Values Register Description
KEY registers − Accessible by the user

77F0h KEY3 FFFFh High word of the 64-bit KEY register

77F1h KEY2 FFFFh Third word of the 64-bit KEY register

77F2h KEY1 FFFFh Second word of the 64-bit KEY register

77F3h KEY0 FFFFh Low word of the 64-bit KEY register

Program Memory PWL in program memory − Reserved for

Address passwords only

0040h PWL3 0000, FFFFh or High word of the 64-bit password

user defined

0041h PWL2 0000, FFFFh or Third word of the 64-bit password

user defined

0042h PWL1 0000, FFFFh or Second word of the 64-bit password

user defined

0043h PWL0 0000, FFFFh or Low word of the 64-bit password

user defined

Programmable Register Address Summary B-9

Summary of Programmable Registers on the 240xA

B-10
 Appendix
AppendixCA

$   

This appendix provides:

A brief introduction to the tools used for generating executable COFF files
that run on the 240xA devices.

Sample programs to test some of the peripherals available in the 240xA

devices.

This appendix is not intended to teach you how to use the software
development tools. The following documents cover these tools in detail:

TMS320C1x/C2x/C2xx/C5x Assembly Language Tools User’s Guide

(literature number SPRU018)

TMS320C2x/C2xx/C5x Optimizing C Compiler User’s Guide

(literature number SPRU024)

TMS320C2xx C Source Debugger User’s Guide

(literature number SPRU151)

For further information about ordering these documents, see Related

Documentation From Texas Instruments on page v of the Preface.

Topic Page

C.1 About These Program Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2

C.2 Program Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4

C-1
About
About These
These Program
Program Examples
Examples

C.1 About These Program Examples

Figure C−1 illustrates the basic process for generating executable COFF files:
1) Use any ASCII editor to create:

An assembly language program (test.asm in the figure)

A linker command file (240xA.cmd in the figure) that defines address
ranges according to the architecture of the particular device and
where the various sections of the user code should be located
2) Assemble the program. The command shown under Step 2 in the figure
generates an object file (.obj) and list file (.lst) containing a listing of as-
sembler messages.
3) Use the linker to bring together the information in the object file and the
command file and create an executable file (test.out in the figure). The
command shown also generates a map file, which explains how the linker
assigned the individual sections in the memory.

Note:
The procedure here applies to the PC development environment and is giv-
en only as an example.

Figure C−1. Procedure for Generating Executable Files

Step 1
Using any ASCII editor, create source program
test.asm
and command file
240xA.cmd

Step 2 Output files

Assemble source program test.lst − error listings
dspa test.asm −l −v2xx −s test.obj − assembled file

Step 3 Output files

Run linker test.out − executable file
dsplnk test.obj 240xA.cmd −o test.out −m test.map − map file
test.map

C-2
 About These Program Examples

Table C−1. Common Files For All Example Programs

Program Functional Description

240xA_PM.cmd Linker command file that defines the program, data, and I/O memory maps of the target
hardware. It also locates the various sections in the user code into predetermined
segments of memory. This .cmd file locates user code (vectors and .text sections) in
program memory beginning at 0000h.

240xA.h Header file that designates labels for the addresses of the various registers.

vector.h File that contains the vectors for various interrupts.

Table C−2. Program Examples

Program Functional Description

SPI.asm Program to output serial data through the SPI port

SCI.asm Program to check the SCI module in 240xA

PC_ECHO.asm Program to echo received characters back to the source

ADC.asm Program to check ADC of 240xA

GPIO_OUT.asm Program that checks GPIO pins of 240xA as outputs

GPIO_IN.asm Program that checks GPIO pins of 240xA as inputs

REM_ANS.asm Programs that perform RTR (Remote Transmission Request) operations in the
REM_REQ.asm CAN module

EV_T1INT.asm Program to check the operation of timer 1 in EVA

CAP.asm Program to check the operation of capture units in the EV modules

Program Examples C-3

Program Examples

C.2 Program Examples

/******************************************************************************/
/* File Name: 2407_PM.cmd */
/* Description: Linker command file to place user code (vectors & .text) */
/* sections beginning at 0000h of external program memory (in MP mode). */
/* This file should be modified if it is desired to load code in B0 memory or */
/* if on−chip SARAM is to be used. This example file is applicable for 2407A. */
/* It needs to be modified to make it suitable for other devices. */
/******************************************************************************/

MEMORY
{

PAGE 0: /* PROGRAM MEMORY */

PM :ORIGIN=0H , LENGTH=08000H /* 32K On−chip flash memory */

SARAM_P :ORIGIN=08000H, LENGTH=0800H /* 2K SARAM in program space */
EX1_PM :ORIGIN=08800H, LENGTH=07600H /* External RAM */
B0_PM :ORIGIN=0FF00h, LENGTH=0100h /* On−chip DARAM if CNF=1, else */
/* external */
/* B0 = FF00 to FFFF */

PAGE 1: /* DATA MEMORY */

REGS :ORIGIN=0h , LENGTH=60h /* Memory mapped regs & reservd address*/

BLK_B2 :ORIGIN=60h , LENGTH=20h /* Block B2 */
BLK_B0 :ORIGIN=200h , LENGTH=100h /* Block B0, On−chip DARAM if CNF=0 */
BLK_B1 :ORIGIN=300h , LENGTH=100h /* Block B1 */
SARAM_D :ORIGIN=0800H , LENGTH=0800H /* 2K SARAM in data space */
PERIPH :ORIGIN=7000h , LENGTH=1000h /* Peripheral register space */
EX2_DM :ORIGIN=8000h , LENGTH=8000h /* External data RAM */

PAGE 2: /* I/O MEMORY */

IO_EX :ORIGIN=0000h , LENGTH=0FFF0h /* External I/O mapped peripherals */

IO_IN :ORIGIN=0FFF0h, LENGTH=0Fh /* On−chip I/O mapped peripherals */

SECTIONS

vectors :{} > PM PAGE 0

.text :{} > PM PAGE 0
.bss :{} > BLK_B2 PAGE 1
.data :{} > BLK_B1 PAGE 1
}

C-4
 Program Examples

;************************************************************************
; File name: 240x.h
;
; Description: 240x register definitions, Bit codes for BIT instruction
;************************************************************************

; 240x CPU core registers

IMR .set 0004h ; Interrupt Mask Register

IFR .set 0006h ; Interrupt Flag Register

; System configuration and interrupt registers

SCSR1 .set 7018h ; System Control & Status register. 1

SCSR2 .set 7019h ; System Control & Status register. 2
DINR .set 701Ch ; Device Identification Number register.
PIVR .set 701Eh ; Peripheral Interrupt Vector register.
PIRQR0 .set 7010h ; Peripheral Interrupt Request register 0
PIRQR1 .set 7011h ; Peripheral Interrupt Request register 1
PIRQR2 .set 7012h ; Peripheral Interrupt Request register 2
PIACKR0 .set 7014h ; Peripheral Interrupt Acknowledge register 0
PIACKR1 .set 7015h ; Peripheral Interrupt Acknowledge register 1
PIACKR2 .set 7016h ; Peripheral Interrupt Acknowledge register 2

; External interrupt configuration registers

XINT1CR .set 7070h ; External interrupt 1 control register

XINT2CR .set 7071h ; External interrupt 2 control register

; Digital I/O registers

MCRA .set 7090h ; I/O Mux Control Register A

MCRB .set 7092h ; I/O Mux Control Register B
MCRC .set 7094h ; I/O Mux Control Register C
PADATDIR .set 7098h ; I/O port A Data & Direction register
PBDATDIR .set 709Ah ; I/O port B Data & Direction register
PCDATDIR .set 709Ch ; I/O port C Data & Direction register
PDDATDIR .set 709Eh ; I/O port D Data & Direction register
PEDATDIR .set 7095h ; I/O port E Data & Direction register
PFDATDIR .set 7096h ; I/O port F Data & Direction register

; Watchdog (WD) registers

WDCNTR .set 7023h ; WD Counter register

WDKEY .set 7025h ; WD Key register
WDCR .set 7029h ; WD Control register

; ADC registers

ADCTRL1 .set 70A0h ; ADC Control register 1

ADCTRL2 .set 70A1h ; ADC Control register 2
MAXCONV .set 70A2h ; Maximum conversion channels register
CHSELSEQ1 .set 70A3h ; Channel select Sequencing control register 1
CHSELSEQ2 .set 70A4h ; Channel select Sequencing control register 2
CHSELSEQ3 .set 70A5h ; Channel select Sequencing control register 3

Program Examples C-5

Program Examples

CHSELSEQ4 .set 70A6h ; Channel select Sequencing control register 4

AUTO_SEQ_SR .set 70A7h ; Auto−sequence status register
RESULT0 .set 70A8h ; Conversion result register 0
RESULT1 .set 70A9h ; Conversion result register 1
RESULT2 .set 70Aah ; Conversion result register 2
RESULT3 .set 70Abh ; Conversion result register 3
RESULT4 .set 70Ach ; Conversion result register 4
RESULT5 .set 70Adh ; Conversion result register 5
RESULT6 .set 70Aeh ; Conversion result register 6
RESULT7 .set 70Afh ; Conversion result register 7
RESULT8 .set 70B0h ; Conversion result register 8
RESULT9 .set 70B1h ; Conversion result register 9
RESULT10 .set 70B2h ; Conversion result register 10
RESULT11 .set 70B3h ; Conversion result register 11
RESULT12 .set 70B4h ; Conversion result register 12
RESULT13 .set 70B5h ; Conversion result register 13
RESULT14 .set 70B6h ; Conversion result register 14
RESULT15 .set 70B7h ; Conversion result register 15
CALIBRATION .set 70B8h ; Calibration result, used to correct
; subsequent conversions

; SPI registers

SPICCR .set 7040h ; SPI Config Control register

SPICTL .set 7041h ; SPI Operation Control register
SPISTS .set 7042h ; SPI Status register
SPIBRR .set 7044h ; SPI Baud rate control register
SPIRXEMU .set 7046h ; SPI Emulation buffer register
SPIRXBUF .set 7047h ; SPI Serial receive buffer register
SPITXBUF .set 7048h ; SPI Serial transmit buffer register
SPIDAT .set 7049h ; SPI Serial data register
SPIPRI .set 704Fh ; SPI Priority control register

; SCI registers

SCICCR .set 7050h ; SCI Communication control register

SCICTL1 .set 7051h ; SCI Control register 1
SCIHBAUD .set 7052h ; SCI Baud Rate MS byte register
SCILBAUD .set 7053h ; SCI Baud Rate LS byte register
SCICTL2 .set 7054h ; SCI Control register 2
SCIRXST .set 7055h ; SCI Receiver Status register
SCIRXEMU .set 7056h ; SCI Emulation Data Buffer register
SCIRXBUF .set 7057h ; SCI Receiver Data buffer register
SCITXBUF .set 7059h ; SCI Transmit Data buffer register
SCIPRI .set 705Fh ; SCI Priority control register

; Event Manager A (EVA) registers

GPTCONA .set 7400h ; GP Timer control register A

T1CNT .set 7401h ; GP Timer 1 counter register
T1CMPR .set 7402h ; GP Timer 1 compare register
T1PR .set 7403h ; GP Timer 1 period register
T1CON .set 7404h ; GP Timer 1 control register
T2CNT .set 7405h ; GP Timer 2 counter register
T2CMPR .set 7406h ; GP Timer 2 compare register

C-6
 Program Examples

T2PR .set 7407h ; GP Timer 2 period register

T2CON .set 7408h ; GP Timer 2 control register

COMCONA .set 7411h ; Compare control register A

ACTRA .set 7413h ; Full compare Action control register A
DBTCONA .set 7415h ; Dead-band timer control register A

CMPR1 .set 7417h ; Full compare unit compare register1

CMPR2 .set 7418h ; Full compare unit compare register2
CMPR3 .set 7419h ; Full compare unit compare register3

CAPCONA .set 7420h ; Capture control register A

CAPFIFOA .set 7422h ; Capture FIFO status register A

CAP1FIFO .set 7423h ; Capture Channel 1 FIFO Top

CAP2FIFO .set 7424h ; Capture Channel 2 FIFO Top
CAP3FIFO .set 7425h ; Capture Channel 3 FIFO Top

CAP1FBOT .set 7427h ; Bottom reg. of capture FIFO stack 1

CAP2FBOT .set 7428h ; Bottom reg. of capture FIFO stack 2
CAP3FBOT .set 7429h ; Bottom reg. of capture FIFO stack 3

EVAIMRA .set 742Ch ; Group A Interrupt Mask Register

EVAIMRB .set 742Dh ; Group B Interrupt Mask Register
EVAIMRC .set 742Eh ; Group C Interrupt Mask Register

EVAIFRA .set 742Fh ; Group A Interrupt Flag Register

EVAIFRB .set 7430h ; Group B Interrupt Flag Register
EVAIFRC .set 7431h ; Group C Interrupt Flag Register

; Event Manager B (EVB) registers

GPTCONB .set 7500h ; GP Timer control register B

T3CNT .set 7501h ; GP Timer 3 counter register
T3CMPR .set 7502h ; GP Timer 3 compare register
T3PR .set 7503h ; GP Timer 3 period register
T3CON .set 7504h ; GP Timer 3 control register
T4CNT .set 7505h ; GP Timer 4 counter register
T4CMPR .set 7506h ; GP Timer 4 compare register
T4PR .set 7507h ; GP Timer 4 period register
T4CON .set 7508h ; GP Timer 4 control register

COMCONB .set 7511h ; Compare control register B

ACTRB .set 7513h ; Full compare Action control register B
DBTCONB .set 7515h ; Dead-band timer control register B

CMPR4 .set 7517h ; Full compare unit compare register4

CMPR5 .set 7518h ; Full compare unit compare register5
CMPR6 .set 7519h ; Full compare unit compare register6

CAPCONB .set 7520h ; Capture control register B

CAPFIFOB .set 7522h ; Capture FIFO status register B

CAP4FIFO .set 7523h ; Capture Channel 4 FIFO Top

CAP5FIFO .set 7524h ; Capture Channel 5 FIFO Top

Program Examples C-7

Program Examples

CAP6FIFO .set 7525h ; Capture Channel 6 FIFO Top

CAP4FBOT .set 7527h ; Bottom reg. of capture FIFO stack 4

CAP5FBOT .set 7527h ; Bottom reg. of capture FIFO stack 5
CAP6FBOT .set 7527h ; Bottom reg. of capture FIFO stack 6

EVBIMRA .set 752Ch ; Group A Interrupt Mask Register

EVBIMRB .set 752Dh ; Group B Interrupt Mask Register
EVBIMRC .set 752Eh ; Group C Interrupt Mask Register

EVBIFRA .set 752Fh ; Group A Interrupt Flag Register

EVBIFRB .set 7530h ; Group B Interrupt Flag Register
EVBIFRC .set 7531h ; Group C Interrupt Flag Register

; CAN registers

CANMDER .set 7100h ; CAN Mailbox Direction/Enable register

CANTCR .set 7101h ; CAN Transmission Control register
CANRCR .set 7102h ; CAN Recieve Control register
CANMCR .set 7103h ; CAN Master Control register
CANBCR2 .set 7104h ; CAN Bit Config register 2
CANBCR1 .set 7105h ; CAN Bit Config register 1
CANESR .set 7106h ; CAN Error Status register
CANGSR .set 7107h ; CAN Global Status register
CANCEC .set 7108h ; CAN Trans and Rcv Err counters
CANIFR .set 7109h ; CAN Interrupt Flag Register
CANIMR .set 710ah ; CAN Interrupt Mask Register
CANLAM0H .set 710bh ; CAN Local Acceptance Mask MBX0/1
CANLAM0L .set 710ch ; CAN Local Acceptance Mask MBX0/1
CANLAM1H .set 710dh ; CAN Local Acceptance Mask MBX2/3
CANLAM1L .set 710eh ; CAN Local Acceptance Mask MBX2/3

CANMSGID0L .set 7200h ; CAN Message ID for mailbox 0 (lower 16 bits)

CANMSGID0H .set 7201h ; CAN Message ID for mailbox 0 (upper 16 bits)
CANMSGCTRL0 .set 7202h ; CAN RTR and DLC
CANMBX0A .set 7204h ; CAN 2 of 8 bytes of Mailbox 0
CANMBX0B .set 7205h ; CAN 2 of 8 bytes of Mailbox 0
CANMBX0C .set 7206h ; CAN 2 of 8 bytes of Mailbox 0
CANMBX0D .set 7207h ; CAN 2 of 8 bytes of Mailbox 0

CANMSGID1L .set 7208h ; CAN Message ID for mailbox 1 (lower 16 bits)

CANMSGID1H .set 7209h ; CAN Message ID for mailbox 1 (upper 16 bits)
CANMSGCTRL1 .set 720Ah ; CAN RTR and DLC
CANMBX1A .set 720Ch ; CAN 2 of 8 bytes of Mailbox 1
CANMBX1B .set 720Dh ; CAN 2 of 8 bytes of Mailbox 1
CANMBX1C .set 720Eh ; CAN 2 of 8 bytes of Mailbox 1
CANMBX1D .set 720Fh ; CAN 2 of 8 bytes of Mailbox 1

CANMSGID2L .set 7210h ; CAN Message ID for mailbox 2 (lower 16 bits)

CANMSGID2H .set 7211h ; CAN Message ID for mailbox 2 (upper 16 bits)
CANMSGCTRL2 .set 7212h ; CAN RTR and DLC
CANMBX2A .set 7214h ; CAN 2 of 8 bytes of Mailbox 2
CANMBX2B .set 7215h ; CAN 2 of 8 bytes of Mailbox 2
CANMBX2C .set 7216h ; CAN 2 of 8 bytes of Mailbox 2
CANMBX2D .set 7217h ; CAN 2 of 8 bytes of Mailbox 2

C-8
 Program Examples

CANMSGID3L .set 7218h ; CAN Message ID for mailbox 3 (lower 16 bits)

CANMSGID3H .set 7219h ; CAN Message ID for mailbox 3 (upper 16 bits)
CANMSGCTRL3 .set 721Ah ; CAN RTR and DLC
CANMBX3A .set 721Ch ; CAN 2 of 8 bytes of Mailbox 3
CANMBX3B .set 721Dh ; CAN 2 of 8 bytes of Mailbox 3
CANMBX3C .set 721Eh ; CAN 2 of 8 bytes of Mailbox 3
CANMBX3D .set 721Fh ; CAN 2 of 8 bytes of Mailbox 3

CANMSGID4L .set 7220h ; CAN Message ID for mailbox 4 (lower 16 bits)

CANMSGID4H .set 7221h ; CAN Message ID for mailbox 4 (upper 16 bits)
CANMSGCTRL4 .set 7222h ; CAN RTR and DLC
CANMBX4A .set 7224h ; CAN 2 of 8 bytes of Mailbox 4
CANMBX4B .set 7225h ; CAN 2 of 8 bytes of Mailbox 4
CANMBX4C .set 7226h ; CAN 2 of 8 bytes of Mailbox 4
CANMBX4D .set 7227h ; CAN 2 of 8 bytes of Mailbox 4

CANMSGID5L .set 7228h ; CAN Message ID for mailbox 5 (lower 16 bits)

CANMSGID5H .set 7229h ; CAN Message ID for mailbox 5 (upper 16 bits)
CANMSGCTRL5 .set 722Ah ; CAN RTR and DLC
CANMBX5A .set 722Ch ; CAN 2 of 8 bytes of Mailbox 5
CANMBX5B .set 722Dh ; CAN 2 of 8 bytes of Mailbox 5
CANMBX5C .set 722Eh ; CAN 2 of 8 bytes of Mailbox 5
CANMBX5D .set 722Fh ; CAN 2 of 8 bytes of Mailbox 5

; Code security module (CSM) registers (Data memory)

KEY3 .set 77F0h ; High word of the 64-bit KEY register

KEY2 .set 77F1h ; Third word of the 64-bit KEY register
KEY1 .set 77F2h ; Second word of the 64-bit KEY register
KEY0 .set 77F3h ; Low word of the 64-bit KEY register

; Code security module (CSM) registers (Program memory)

PWL3 .set 0040h ; High word of the 64−bit password

PWL2 .set 0041h ; Third word of the 64−bit password
PWL1 .set 0042h ; Second word of the 64−bit password
PWL0 .set 0043h ; Low word of the 64−bit password

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; I/O space mapped registers
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
WSGR .set 0FFFFh ; Wait-State Generator Control register
FCMR .set 0FF0Fh ; Flash control mode register

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Bit codes for Test bit instruction (BIT) (15 Loads bit 0 into TC)
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
BIT15 .set 0000h ; Bit Code for 15
BIT14 .set 0001h ; Bit Code for 14
BIT13 .set 0002h ; Bit Code for 13
BIT12 .set 0003h ; Bit Code for 12
BIT11 .set 0004h ; Bit Code for 11
BIT10 .set 0005h ; Bit Code for 10

Program Examples C-9

Program Examples

BIT9 .set 0006h ; Bit Code for 9

BIT8 .set 0007h ; Bit Code for 8
BIT7 .set 0008h ; Bit Code for 7
BIT6 .set 0009h ; Bit Code for 6
BIT5 .set 000Ah ; Bit Code for 5
BIT4 .set 000Bh ; Bit Code for 4
BIT3 .set 000Ch ; Bit Code for 3
BIT2 .set 000Dh ; Bit Code for 2
BIT1 .set 000Eh ; Bit Code for 1
BIT0 .set 000Fh ; Bit Code for 0

C-10
 Program Examples

;************************************************************
; File name: vector.h
; Interrupt Vector declarations
; This section contains the vectors for various interrupts in
; the ’240x. Unused interrupts are shown to branch to a ”phantom”
; interrupt service routine which loops on itself. Users should
; replace the label PHANTOM with the label of their interrupt
; subroutines in case these interrupts are used.
;************************************************************
.sect ”vectors”
RSVECT B START ; Reset Vector
INT1 B GISR1 ; Interrupt Level 1
INT2 B GISR2 ; Interrupt Level 2
INT3 B GISR3 ; Interrupt Level 3
INT4 B GISR4 ; Interrupt Level 4
INT5 B GISR5 ; Interrupt Level 5
INT6 B GISR6 ; Interrupt Level 6
RESERVED B PHANTOM ; Reserved
SW_INT8 B PHANTOM ; Software Interrupt
SW_INT9 B PHANTOM ; Software Interrupt
SW_INT10 B PHANTOM ; Software Interrupt
SW_INT11 B PHANTOM ; Software Interrupt
SW_INT12 B PHANTOM ; Software Interrupt
SW_INT13 B PHANTOM ; Software Interrupt
SW_INT14 B PHANTOM ; Software Interrupt
SW_INT15 B PHANTOM ; Software Interrupt
SW_INT16 B PHANTOM ; Software Interrupt
TRAP B PHANTOM ; Trap vector
NMI B NMI ; Non−maskable Interrupt
EMU_TRAP B PHANTOM ; Emulator Trap
SW_INT20 B PHANTOM ; Software Interrupt
SW_INT21 B PHANTOM ; Software Interrupt
SW_INT22 B PHANTOM ; Software Interrupt
SW_INT23 B PHANTOM ; Software Interrupt
SW_INT24 B PHANTOM ; Software Interrupt
SW_INT25 B PHANTOM ; Software Interrupt
SW_INT26 B PHANTOM ; Software Interrupt
SW_INT27 B PHANTOM ; Software Interrupt
SW_INT28 B PHANTOM ; Software Interrupt
SW_INT29 B PHANTOM ; Software Interrupt
SW_INT30 B PHANTOM ; Software Interrupt
SW_INT31 B PHANTOM ; Software Interrupt
; Code−security passwords are stored from 40h − 43h
.word 0000h ; Replace values with
.word 0000h ; code−security passwords
.word 0000h
.word 0000h

Program Examples C-11

Program Examples

;=================================================================================
* File Name: SPI.asm
* Description: PROGRAM TO OUTPUT SERIAL DATA THROUGH THE SPI PORT
* This program outputs a set of incrementing words (that roll over) through
* the SPI. If a Digital−to−analog (DAC) converter is connected to the SPI,
* the DAC outputs a sawtooth waveform. The program sends data to the serial DAC
* by means of the SPI. For this example, the TLC5618 serial DAC from TI was used.
;=================================================================================

.include 240xA.h
.include vector.h
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Variable Declarations for on chip RAM Blocks
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
.bss GPR0,1 ;General purpose registers.
.bss GPR3,1

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; M A C R O − Definitions
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
KICK_DOG .macro ;Watchdog reset macro
LDP #00E0h
SPLK #05555h, WDKEY
SPLK #0AAAAh, WDKEY
LDP #0h
.endm
;===========================================================================
; M A I N C O D E − starts here
;===========================================================================
.text
START: LDP #0
SETC INTM ;Disable interrupts during initialization.
SPLK #0h,GPR3
OUT GPR3,WSGR ;Set XMIF to run with no wait states.
CLRC SXM ;Clear Sign Extension Mode
CLRC OVM ;Reset Overflow Mode
CLRC CNF ;Config Block B0 to Data mem.
LDP #WDCR>>7
SPLK #006Fh,WDCR ;Disable WD
KICK_DOG
LDP #SCSR1>>7 ;Set PLL for x4 mode
SPLK #0020h,SCSR1 ;Enable clock to SPI module

C-12
 Program Examples

;===========================================================================
; SPI Initialization
;===========================================================================
SPI_INIT: LDP #SPICCR>>7
SPLK #000Fh, SPICCR ;16 char bits,
SPLK #0006h, SPICTL ;Enable master mode, normal clock
;and enable talk.
SPLK #0002h, SPIBRR ;Set up the SPI to max speed.
LDP #MCRB>>7 ;Set up the GPIO pins to function
SPLK #003CH, MCRB ;as SPI pins
LDP #SPICCR>>7
SPLK #008Fh, SPICCR ;Relinquish SPI from Reset.
;===========================================================================
; This section generates the sawtooth by ramping a counter down to zero
; reloading it every time it under−flows.
;===========================================================================;
LP: LAR AR0,#07FEh ;Load AR0 with a count
XMIT_VALUE: LDP #0
SAR AR0,GPR0
LACC GPR0
ADD #8000H ;MSB should be one (DAC requirement)
XOR #07FFH ;To change the direction of counting to
;upward
LDP #SPITXBUF>>7
SACL SPITXBUF ;Write xmit value to SPI Trasmit Buffer.
LDP #SPISTS>>7
XMIT_RDY: BIT SPISTS,BIT6 ;Test SPI_INT bit
BCND XMIT_RDY, NTC ;If SPI_INT=0,then repeat loop
;i.e. wait for the completion of
;transmission.
LDP #SPIRXBUF>>7 ;else read SPIRXBUF
LACC SPIRXBUF ;dummy read to clear SPI_INT flag.

MAR *,AR0
BANZ XMIT_VALUE ;xmit next value, if counter is non zero.
B LP ;if counter reaches zero repeat loop
;re−loading the counter.
PHANTOM RET
GISR1 RET
GISR2 RET
GISR3 RET
GISR4 RET
GISR5 RET
GISR6 RET

Program Examples C-13

Program Examples

;===========================================================================
* File Name: SCI.asm
* Description: PROGRAM TO PERFORM A LOOPBACK IN THE SCI MODULE
* This program is capable of doing either an internal loopback or an external
* loopback, depending on the value written in SCICCR. SCITXD−SCIRXD pins
* should be connected together, if external loopback is desired. This is not
* required for an internal loopback. The SCI receives the bit−stream and stores
* the received data in memory (60h and above) for verification.
* An 8 bit value is transmitted through the SCITXD pin at a baud rate of
* 9600 bits/sec. A counter is used to determine how many times data is
* transmitted and received.
* This code is useful to determine the health of the SCI hardware quickly
* without the aid of any other equipment.
;===========================================================================
.include 240x.h

KICK_DOG .macro ;Watchdog reset macro

LDP #00E0h
SPLK #05555h, WDKEY
SPLK #0AAAAh, WDKEY
LDP #0h
.endm
;===========================================================================
; M A I N C O D E − starts here
;===========================================================================
.text
START:
LDP #0
SETC INTM ; Disable interrupts
LDP #00E0h
SPLK #0040h,SCSR1 ; Enable clock for SCI module
SPLK #006Fh,WDCR ; Disable WD
KICK_DOG
SPLK #0h,60h ; Set wait state generator for:
OUT 60h,WSGR ; Program Space, 0−7 wait states

;===========================================================================
;SCI TRANSMISSION TEST − starts here
;===========================================================================

SCI: LDP #0E1h

SPLK #0003h,MCRA
LAR AR0, #SCITXBUF ; Load AR0 with SCI_TX_BUF address
LAR AR1, #SCIRXBUF ; Load AR1 with SCI_RX_BUF address
LAR AR2, #1Fh ; AR2 is the counter
LAR AR3, #60h ; AR3 is the pointer

LDP #SCICCR>>7
SPLK #17h, SCICCR ; 17 for internal loopback
; 07−External
; 1 stop bit,odd parity,8 char bits,
; async mode, idle−line protocol
SPLK #0003h, SCICTL1 ; Enable TX, RX, internal SCICLK,
; Disable RX ERR, SLEEP, TXWAKE
SPLK #0000h, SCICTL2 ; Disable RX & TX INTs

C-14
 Program Examples

SPLK #0002h, SCIHBAUD

SPLK #0008h, SCILBAUD ; Baud Rate=9600 b/s (40 MHz SYSCLK)
SPLK #0023h, SCICTL1 ; Relinquish SCI from Reset.
XMIT_CHAR:
LACL #55h ; Load ACC with xmit character
MAR *,AR0
SACL *,AR1 ; Write xmit char to TX buffer

XMIT_RDY:
BIT SCICTL2,BIT7 ; Test TXRDY bit
BCND XMIT_RDY,NTC ; If TXRDY=0,then repeat loop
RCV_RDY:
BIT SCIRXST,BIT6 ; Test TXRDY bit
BCND RCV_RDY,NTC ; If RXRDY=0,then repeat loop
READ_CHR:
LACL *,AR3 ; The received (echoed) character is
; stored in 60h
SACL *+,AR2 ; This loop is executed 20h times
BANZ XMIT_CHAR ; Repeat the loop again

LOOP B LOOP ; Program idles here after executing

; transmit loops
.end

Program Examples C-15

Program Examples

;===========================================================================
* File Name: PC−ECHO.asm
* Description: PROGRAM TO ECHO RECEIVED CHARACTERS BACK TO THE SOURCE
* The SCI is set up to bounce back any character received through the
* serial link. When connected to a PC (running a terminal emulation program),
* the PC sees the transmitted characters bounce back.
* This code is useful to determine the health of the communication channel
* between the SCI and any other serial device, such as PC’s serial port.
;===========================================================================

.include 240x.h

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; M A C R O − Definitions
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
KICK_DOG .macro ;Watchdog reset macro
LDP #00E0h
SPLK #05555h, WDKEY
SPLK #0AAAAh, WDKEY
LDP #0h
.endm
;================================================================
; M A I N C O D E − starts here
;================================================================
.text
START:
LDP #0
SPLK #0,60h
OUT 60h,WSGR ; Set XMIF to run w/no wait states
SETC INTM ; Disable interrupts
LDP #00E0h
SPLK #0040h,SCSR1 ; Enables clock to the SCI module

SPLK #006Fh,WDCR ; Disable WD

KICK_DOG

;=============================================================
;SCI TRANSMISSION TEST − starts here
;=============================================================
SCI:
LDP #0E1h
SPLK #0003h,MCRA
LAR AR1, #SCIRXBUF ;Load AR1 with SCI_RX_BUF address
LAR AR0, #SCITXBUF ;Load AR0 with SCI_TX_BUF address
LARP AR0
LDP #0E0h
SPLK #0007h, SCICCR ;1 stop bit,No parity,8 char bits,
;async mode, idle−line protocol
SPLK #0003h, SCICTL1 ;Enable TX, RX, internal SCICLK,
;Disable RX ERR, SLEEP, TXWAKE
SPLK #0000h, SCICTL2 ; Disable RX & TX INTs
* Baud rate prescaler values for 240x devices running @ 40 MHz.

C-16
 Program Examples

SPLK #0000h, SCIHBAUD ; Baud Rate=38400 (81h)

SPLK #0081h, SCILBAUD
SPLK #0023h, SCICTL1 ; Relinquish SCI from Reset

RCV_RDY: BIT SCIRXST,BIT6 ; Test RXRDY bit

BCND RCV_RDY,NTC ; If RXRDY=0,then repeat loop
READ_CHR: LACL SCIRXBUF
XMIT_CHAR: SACL *,AR0 ;Write xmit char to TX buffer

B RCV_RDY ;else wait for nexr character

.end
; Connect the SCI to the PC’s serial port. Use any terminal emulation software.
; Choose 1 stop bit, No parity. Default baud rate is 38400. Set emulation to
; ANSI. Disable flow control.
; Since this code does not use interrupts, it can be run from B0 memory also.

Program Examples C-17

Program Examples

;============================================================================*
* File name : ADC.asm *
* Description : PROGRAM TO INITIALIZE THE ADC MODULE OF 240xA *
* This program initializes the ADC module of the 240xA and does a conversion*
* of all the analog input channels. The results of the conversion are *
* available in the RESULTSn register, which can be accessed by the user *
* application. The ADC operates as one 16−state sequencer & the conversions *
* are stopped once the sequencer reaches EOS (End of sequence) *
;============================================================================*

.title ”ADC”

.bss GPR0,1 ; General purpose register

.include 240xA.h
.copy ”vector.h”

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; M A C R O − Definitions
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
KICK_DOG .macro ; Watchdog reset macro
LDP #00E0h ; DP−−>7000h−707Fh
SPLK #05555h, WDKEY
SPLK #0AAAAh, WDKEY
LDP #0h ; DP−−>0000h−007Fh
.endm

.text
START: LDP #0h ; Set DP=0
SETC INTM ; Disable interrupts
CLRC SXM
SPLK #0000h,IMR ; Mask all core interrupts
LACC IFR ; Read Interrupt flags
SACL IFR ; Clear all interrupt flags
LDP #00E0h ; (E0=224)(E0*80=7000)
SPLK #006Fh, WDCR ; Disable WD
SPLK #0080h,SCSR1 ; Enable clock to ADC module
KICK_DOG
SPLK #0h,GPR0 ; Set wait state generator for:
OUT GPR0,WSGR ; Program Space, 0−7 wait states

* Initialize ADC registers

LDP #0E1h
SPLK #0100000000000000b,ADCTRL1 ; Reset ADC module
NOP
SPLK #0011000000010000b,ADCTRL1 ; Take ADC out of reset
; ||||||||||||||||
; 5432109876543210
; 15 − RSVD | 14 − Reset(1) | 13,12 − Soft & Free
; 11,10,9,8 − Acq.prescalers | 7 − Clock prescaler
; 6 − Cont.run (1) | 5 − Int.priority (Hi.0)
; 4 − Seq.casc (0−dual)

C-18
 Program Examples

* Setup a maximum of 16 conversions

SPLK #15, MAXCONV ; Setup for 16 conversions

* Program the conversion sequence. This is the sequence of channels that will
* be used for the 16 conversions.

SPLK #03210h, CHSELSEQ1 ; Convert Channels 0,1,2,3

SPLK #07654h, CHSELSEQ2 ; Convert Channels 4,5,6,7
SPLK #0BA98h, CHSELSEQ3 ; Convert Channels 8,9,10,11
SPLK #0FEDCh, CHSELSEQ4 ; Convert Channels 12,13,14,15

SPLK #0010000000000000b,ADCTRL2 ; Start the conversions

; ||||||||||||||||
; 5432109876543210
NOP
NOP
NOP
NOP

CHK_EOS1: BIT ADCTRL2, BIT12 ; Wait for SEQ1 Busy bit to

; clear
BCND CHK_EOS1, TC ; If TC=1, keep looping.

RPT #8
NOP

LOOP: B LOOP ; The conversion results are now

; available in the RESULTSn regs.
GISR1: RET
GISR2: RET
GISR3: RET
GISR4: RET
GISR5: RET
GISR6: RET
PHANTOM: RET
.end

Program Examples C-19

Program Examples

;=========================================================================
* File name : GPIO_OUT.asm
* Description : PROGRAM TO CHECK THE GPIO PINS OF 240xA as outputs *
* This program writes a running pattern of 0’s to the GPIO pins of 240xA*
* It ouputs a total of 8 bit patterns to the five GPIO ports (A,B,C,E,F) *
* Each bit pattern forces a particular bit low and forces the other 7 *
* bits high. This goes on in an endless loop. *
;=========================================================================

.title ” 240xA GPIO”

.data ; Loaded @ 300h in data memory

b0 .word 0FFFEh ; Turn−on GPIO0
b1 .word 0FFFDh ; Turn−on GPIO1
b2 .word 0FFFBh ; Turn−on GPIO2
b3 .word 0FFF7h ; Turn−on GPIO3
b4 .word 0FFEFh ; Turn−on GPIO4
b5 .word 0FFDFh ; Turn−on GPIO5
b6 .word 0FFBFh ; Turn−on GPIO6
b7 .word 0FF7Fh ; Turn−on GPIO7
GPR0 .word 0 ; Gen purp reg

.include 240xA.h

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; M A C R O − Definitions
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
KICK_DOG .macro ;Watchdog reset macro
LDP #00E0h ;DP−−>7000h−707Fh
SPLK #05555h, WDKEY
SPLK #0AAAAh, WDKEY
LDP #0h ;DP−−>0000h−007Fh
.endm

.text
START: LDP #0h ; Set DP=0
SETC INTM ; Disable interrupts
SETC CNF
SPLK #0000h,IMR ; Mask all core interrupts
LACC IFR ; Read Interrupt flags
SACL IFR ; Clear all interrupt flags
LDP #00E0h ; (E0=224)(E0*80=7000)
SPLK #0000h,SCSR1
SPLK #006Fh, WDCR ; Disable WD
KICK_DOG
SPLK #0h,GPR0 ; Set wait state generator for
OUT GPR0,WSGR ; external address space

LDP #00E1h
SPLK #00000h,MCRA ; Select IOPAn & IOPBn as GPIO pins
SPLK #0FF00h,MCRB ; Select IOPCn as GPIO pins
SPLK #00000h,MCRC ; Select IOPEn & IOPFn as GPIO pins

SPLK #0FFFFh, PADATDIR ; All pins are o/p’s

C-20
 Program Examples

SPLK #0FFFFh, PBDATDIR ; and forced high

SPLK #0FFFFh, PCDATDIR ;
SPLK #0FFFFh, PEDATDIR ;
SPLK #0FFFFh, PFDATDIR ;

MAIN LDP #0
LAR AR0,#300h ; AR0 points to bit pattern in
; data memory
LAR AR1,#7 ; AR1 is the counter

LOOP MAR *,AR0

LACC *+,AR2 ; Load bit pattern in accumulator
LDP #00E1h
SACL PADATDIR ; Output the same bit pattern
SACL PBDATDIR ; to all the GPIO ports
SACL PCDATDIR
SACL PEDATDIR
SACL PFDATDIR

CALL DELAY ; Delay provided in between

; each pattern
MAR *,AR1 ; Check if all 8 patterns have
BANZ LOOP ; been output. If not, continue.
B MAIN

DELAY LAR AR2,#0FFFFh

D_LOOP RPT #0FFh
NOP
BANZ D_LOOP
RET

PHANTOM KICK_DOG ;Resets WD counter

B PHANTOM

Program Examples C-21

Program Examples

;=========================================================================
* File name : GPIO_IN.asm *
* Description : PROGRAM TO CHECK GPIO PINS OF 240xA as inputs *
* All GPIO bits are programmed as inputs and the values read from the *
* GPIO pins are written in 60h,61h,62h,63h,64h of Data memory *
;=========================================================================

.title ” 240xA GPIO”

.bss GPR0,1 ; Gen purp reg

.include 240xA.h

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; M A C R O − Definitions
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
KICK_DOG .macro ; Watchdog reset macro
LDP #00E0h ; DP−−>7000h−707Fh
SPLK #05555h, WDKEY
SPLK #0AAAAh, WDKEY
LDP #0h ; DP−−>0000h−007Fh
.endm

.text
START: LDP #0h ; Set DP=0
SETC INTM ; Disable interrupts
SETC CNF
SPLK #0000h,IMR ; Mask all core interrupts
LACC IFR ; Read Interrupt flags
SACL IFR ; Clear all interrupt flags
LDP #00E0h ; (E0=224)(E0*80=7000)
SPLK #006Fh, WDCR ; Disable WD
SPLK #0,SCSR1 ; Put PLL in x4 mode.

KICK_DOG
SPLK #0h,GPR0 ; Set wait state generator for
OUT GPR0,WSGR ; external address space.
LDP #00E1h
SPLK #00000h,MCRA ; Select IOPAn & IOPBn as GPIO pins
SPLK #0FF00h,MCRB ; Select IOPCn as GPIO pins
SPLK #00000h,MCRC ; Select IOPEn & IOPFn as GPIO pins

SPLK #0h, PADATDIR ; All GPIO pins are programmed

SPLK #0h, PBDATDIR ; as inputs
SPLK #0h, PCDATDIR
SPLK #0h, PEDATDIR
SPLK #0h, PFDATDIR

MAIN LDP #0 ; This loop reads the level on

LAR AR0,#60h ; the GPIO pins. The bit patterns
MAR *,AR0 ; read from the 5 GPIO ports
LDP #00E1h ; is copied in the data memory

LACL PADATDIR
SACL *+

C-22
 Program Examples

LACL PBDATDIR
SACL *+
LACL PCDATDIR
SACL *+
LACL PEDATDIR
SACL *+
LACL PFDATDIR
SACL *+
B MAIN

PHANTOM
B PHANTOM

Program Examples C-23

Program Examples

Program to auto-answer a remote frame request in CAN. To be used along with

REM−REQ.asm.
;===============================================================================
* File name : REM_ANS.asm *
* PROGRAM TO AUTO−ANSWER TO A REMOTE FRAME REQUEST IN 24x/240xA CAN *
* To be used along with REM−REQ.asm *
* Reception and transmission by MBX2. Low priority interrupt used *
; Transmit acknowledge for MBX2 is set after running this program
; and the message is transmitted.
.title ”REM_ANS” ; Title
.include ”240x.h” ; Variable and register declaration
.include ”vector.h” ; Vector table (takes care of dummy password)
.global START
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Constant definitions
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
DP_PF1 .set 0E0h ; Page 1 of peripheral file (7000h/80h
DP_CAN .set 0E2h ; CAN Register (7100h)
DP_CAN2 .set 0E4h ; CAN RAM (7200h)
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; M A C R O − Definitions
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
KICK_DOG .macro ; Watchdog reset macro
LDP #00E0h
SPLK #05555h, WDKEY
SPLK #0AAAAh, WDKEY
LDP #0h
.endm
;==============================================================================
; M A I N C O D E − starts here
;==============================================================================
.text
START: KICK_DOG ; Reset Watchdog counter
SPLK #0,60h
OUT 60h,WSGR ; Set waitstates for external memory (if used)
LDP #0E0h
SPLK #006Fh, WDCR ; Disable WD
SPLK #0010h,SCSR1 ; Enable clock to CAN module (For 240xA only)
LDP #225
SPLK #00C0H,MCRB ; Configure CAN pins
;**************************************************************************
; Enable 1 core interrupt
;**************************************************************************
LDPK #0
SPLK #0000000000010000b, IMR ; core interrupt mask register
; |||||||||||||||| ; Enable INT5 for CAN
; FEDCBA9876543210
SPLK #000FFh,IFR ; Clear all core interrupt flags
CLRC INTM ; enable interrupt
LDP #DP_CAN
SPLK #1011111111111111b,CANIMR ; Enable all CAN interrupts
;**************************************************************************
;****** DISABLE MBX BEFORE WRITING TO MSGID/MSGCTRL OF MBX2 **********
;**************************************************************************
SPLK #0000000000000000b,CANMDER
; ||||||||||||||||

C-24
 Program Examples

; FEDCBA9876543210
;**************************************************************************
;*********** Write CAN Mailboxes **********
;**************************************************************************
LDP #DP_CAN2
SPLK #1011111111111111b,CANMSGID2H
; ||||||||||||||||
; FEDCBA9876543210
;bit 0−12 upper 13 bits of extended identifier
;bit 13 Auto answer mode bit
;bit 14 Acceptance mask enable bit
;bit 15 Identifier extension bit
SPLK #1111111111111111b,CANMSGID2L
; ||||||||||||||||
; FEDCBA9876543210
;bit 0−15 lower part of extended identifier
SPLK #0000000000001000b,CANMSGCTRL2
; ||||||||||||||||
; FEDCBA9876543210
;bit 0−3 Data length code: 1000 = 8 bytes
;bit 4 0: data frame
LDP #DP_CAN
SPLK #0000000100000000b,CANMCR ; Set CDR bit before writing
; ||||||||||||||||
; FEDCBA9876543210
LDP #DP_CAN2
SPLK #0BEBEh,CANMBX2A ; Message to transmit
SPLK #0BABAh,CANMBX2B
SPLK #0DEDEh,CANMBX2C
SPLK #0DADAh,CANMBX2D
LDP #DP_CAN
SPLK #0000000000000000b,CANMCR ; Clear CDR bit after writing
; ||||||||||||||||
; FEDCBA9876543210
;**************************************************************************
;*********** Enable Mailbox **********
;**************************************************************************
SPLK #0000000000000100b,CANMDER
; ||||||||||||||||
; FEDCBA9876543210
;bit 0−5 Enable MBX2
;bit 6 MBX2 configured as Transmit MBX
;**************************************************************************
;*********** Bit timing Registers configuration **********************
;**************************************************************************
SPLK #0001000000000000b,CANMCR
; ||||||||||||||||
; FEDCBA9876543210
;bit 12 Change configuration request for write−access to BCR (CCR=1)
W_CCE BIT CANGSR,#0Bh ; Wait for Change config Enable
BCND W_CCE,NTC ; bit to be set in GSR
;SPLK #0000000000000000b,CANBCR2 ; For 1 Mbps @ 20 MHz CLKOUT
SPLK #0000000000000001b,CANBCR2 ; For 1 Mbps @ 40 MHz CLKOUT
; ||||||||||||||||
; FEDCBA9876543210

Program Examples C-25

Program Examples

; bit 0−7 Baud rate prescaler

; bit 8−15 Reserved
SPLK #0000000011111010b,CANBCR1 ; For 1 Mbps @ 85 % samp. pt
; ||||||||||||||||
; FEDCBA9876543210
; bit 0−2 TSEG2
; bit 3−6 TSEG1
; bit 7 Sample point setting (1: 3 times, 0: once)
; bit 8−9 Synchronization jump width
; bit A−F Reserved
SPLK #0000000000000000b,CANMCR
; ||||||||||||||||
; FEDCBA9876543210
;bit 12 Change conf register
W_NCCE BIT CANGSR,#0Bh ; Wait for Change config disable
BCND W_NCCE,TC
ELOOP B ELOOP ; Wait for Receive Interrupt
;==================================================================
; ISR used to toggle XF to indicate remote frame was received
;==================================================================
GISR5:
LOOP2 MAR *,AR0
SETC XF
CALL DELAY
CLRC XF
CALL DELAY
B LOOP2
DELAY LAR AR0,#0FFFFh
LOOP RPT #080h
NOP
BANZ LOOP
RET
GISR1: RET
GISR2: RET
GISR3: RET
GISR4: RET
GISR6: RET
PHANTOM RET
.end
; When data in MBX2 is transmitted in response to a ”Remote frame request,”
; XF is toggled. Note that TRS bit is not set for MBX2. The transmission of
; MBX2 data is automatic ,in response to a ”Remote frame request.”

C-26
 Program Examples

This program transmits a remote frame and expects a data frame in response.
Transmission of a remote frame by (and reception of the data frame in) MBX3. To be
used along with REM−ANS.asm
;==============================================================================
* File name : REM_REQ.asm *
* PROGRAM TO TRANSMIT A REMOTE FRAME REQUEST IN THE 24x/240xA CAN
* This program transmits a remote frame and expects a data frame in response
* Transmission of a remote frame by (and reception of the data frame in) MBX3
* To be used along with REM−ANS.asm

.title ”REM_REQ” ; Title

.include ”240x.h” ; Variable and register declaration
.include ”vector.h” ; Vector table (takes care of dummy password)
.global START
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Other constant definitions
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
DP_PF1 .set 0E0h ; Page 1 of peripheral file (7000h/80h
DP_CAN .set 0E2h ; Can Registers (7100h)
DP_CAN2 .set 0E4h ; Can RAM (7200h)
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; M A C R O − Definitions
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
KICK_DOG .macro ; Watchdog reset macro
LDP #00E0h
SPLK #05555h, WDKEY
SPLK #0AAAAh, WDKEY
LDP #0h
.endm

;==============================================================================
; M A I N C O D E − starts here
;==============================================================================
.text
START: KICK_DOG ; Reset Watchdog counter
SPLK #0,60h
OUT 60h,WSGR ; Set waitstates for external memory (if used)
SETC INTM ; Disable interrupts
SPLK #0000h,IMR ; Mask all core interrupts
LDP #0E0h
SPLK #006Fh, WDCR ; Disable WD
SPLK #0010h,SCSR1 ; Enable clock to CAN module (For 240xA only)
LDP #225
SPLK #00C0H,MCRB ; Configure CAN pins
LDP #DP_CAN
SPLK #1011111111111111b,CANIMR ; Enable all CAN interrupts

;**************************************************************************
;****** DISABLE MBX BEFORE WRITING TO MSGID/MSGCTRL OF MBX3 **********
;**************************************************************************
SPLK #0000000000000000b,CANMDER
; ||||||||||||||||
; FEDCBA9876543210

;**************************************************************************
;*********** Write CAN Mailboxes **********
;**************************************************************************

Program Examples C-27

Program Examples

LDP #DP_CAN2

SPLK #1001111111111111b,CANMSGID3H
; ||||||||||||||||
; FEDCBA9876543210
;bit 0−12 upper 13 bits of extended identifier
;bit 13 Auto answer mode bit
;bit 14 Acceptance mask enable bit
;bit 15 Identifier extension bit

SPLK #1111111111111111b,CANMSGID3L
; ||||||||||||||||
; FEDCBA9876543210
;bit 0−15 lower part of extended identifier
SPLK #0000000000011000b,CANMSGCTRL3
; ||||||||||||||||
; FEDCBA9876543210
;bit 0−3 Data length code. 1000 = 8 bytes
;bit 4 1: Remote frame
;**************************************************************************
;*********** Enable Mailbox **********
;**************************************************************************
LDP #DP_CAN
SPLK #0000000010001000b,CANMDER
; ||||||||||||||||
; FEDCBA9876543210
;bit 0−5 enable mailbox 3
;bit 7 1: mailbox 3 = receive

;**************************************************************************
;*********** Bit timing Registers configuration **********************
;**************************************************************************
SPLK #0001000000000000b,CANMCR
; ||||||||||||||||
; FEDCBA9876543210
;bit 12 Change configuration request for write−access to BCR (CCR=1)
W_CCE BIT CANGSR,#0Bh ; Wait for Change config Enable
BCND W_CCE,NTC ; bit to be set in GSR
;SPLK #0000000000000000b,CANBCR2 ; For 1 Mbps @ 20 MHz CLKOUT
SPLK #0000000000000001b,CANBCR2 ; For 1 Mbps @ 40 MHz CLKOUT
; ||||||||||||||||
; FEDCBA9876543210
; bit 0−7 Baud rate prescaler
; bit 8−15 Reserved
SPLK #0000000011111010b,CANBCR1 ; For 1 Mbps @ 85 % samp. pt
; ||||||||||||||||
; FEDCBA9876543210
; bit 0−2 TSEG2
; bit 3−6 TSEG1
; bit 7 Sample point setting (1: 3 times, 0: once)
; bit 8−9 Synchronization jump width
; bit A−F Reserved
SPLK #0000000000000000b,CANMCR
; ||||||||||||||||
; FEDCBA9876543210

C-28
 Program Examples

;bit 12 Change conf register

W_NCCE BIT CANGSR,#0Bh ; Wait for Change config disable
BCND W_NCCE,TC

;**************************************************************************
;*********** TRANSMIT **********
;**************************************************************************
SPLK #0020h,CANTCR ; Transmit request for MBX3
W_TA BIT CANTCR,2 ; Wait for transmission acknowledge
BCND W_TA,NTC
SPLK #2000h,CANTCR ; reset TA
RX_LOOP:
W_RA BIT CANRCR,BIT7 ; Wait for data from remote node
BCND W_RA,NTC ; to be written into MBX3
LOOP B LOOP
GISR1:
GISR2:
GISR3:
GISR4:
GISR5:
GISR6:
PHANTOM RET
.end

Program Examples C-29

Program Examples

;=========================================================================
* File name : EV_T1INT.asm *
* Description : PROGRAM TO CHECK THE OPERATION OF TIMER1 IN EVA *
* Mode: Continous Up/Down counting, x/128 *
* Output: OF,UF,CMPR & PERIOD interrupts that toggles IOPB0,1,2,3 *
;=========================================================================

.title ” EV test routine” ; Title

.include ”240xA.h” ; Variable and register declaration
.include vector.h ; Vector label declaration

;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; M A C R O − Definitions
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
KICK_DOG .macro ;Watchdog reset macro
LDP #00E0h ;DP−−>7000h−707Fh
SPLK #05555h, WDKEY
SPLK #0AAAAh, WDKEY
LDP #0h ;DP−−>0000h−007Fh
.endm

.text

START: LDP #0h ; set DP=0

SETC INTM ; Disable interrupts
SPLK #0000h,IMR ; Mask all core interrupts
LACC IFR ; Read Interrupt flags
SACL IFR ; Clear all interrupt flags
LDP #WDKEY >> 7h ; Peripheral page
SPLK #0004h,SCSR1 ; EVA module clock enable
SPLK #006Fh, WDCR ; Disable WD
KICK_DOG
MAR *,AR0
LDP #0E1h ; Peripheral page
SPLK #1111111100000000b,PBDATDIR
; set IOPBn as outputs,0

* Load TIMER 1 registers

LDP #GPTCONA >> 7h ; Peripheral page
SPLK #0000000000000000b,GPTCONA
SPLK #0000000000000000b,T1CNT ; zero timer 1 count
SPLK #0000111101000010b,T1CON
;000 01 Cont, Up/Down
;111 x/128
;01 Tenable reserved for T1
;00 Internal clk
;00 LD CMPR whencntr =0
;1 enable compare
;0 use own period register

SPLK #1111111111111111b,T1PR
SPLK #0000000011111111b,T1CMPR
SPLK #0000011110000000b,EVAIMRA
; Enable OV,U,C,P interrupt bits

C-30
 Program Examples

SPLK #0000011110000000b,EVAIFRA
; clear interrupts

LDP #0
SPLK #0000000000000010b,IMR ; Enable INT2
CLRC INTM

wait: NOP ; main loop

NOP
B wait

GISR2: NOP ; Int2 GISR

LDP #PIVR >> 7h ; Peripheral page
LACL PIVR ; PIVR value
XOR #002ah ; T1 overflow
BCND SISR2a,eq
LACL PIVR
XOR #0029h ; T1 underflow
BCND SISR29,eq
LACL PIVR
XOR #0028h ; T1 Compare
BCND SISR28,eq
LACL PIVR
XOR #0027h ; T1 Period
BCND SISR27,eq
RET

SISR2a:
LDP #0E1h ; Peripheral page
SPLK #0FF01h,PBDATDIR ; Set IOPB0
CALL DELAY
LDP #GPTCONA >> 7h ; Peripheral page
LACC #0400h ; clear overflow int. flag
SACL EVAIFRA ; in EVAIFRA
CLRC INTM ; Enable all interrupts
RET

SISR29:
LDP #0E1h ; Peripheral page
SPLK #0FF02h,PBDATDIR ; Set IOPB1
CALL DELAY
LDP #GPTCONA >> 7h ; Peripheral page
LACC #0200h ; clear underflow int. flag
SACL EVAIFRA ; in EVAIFRA
CLRC INTM ; Enable all interrupts
RET

SISR28:
LDP #0E1h ; Peripheral page
SPLK #0FF04h,PBDATDIR ; Set IOPB2
CALL DELAY
LDP #GPTCONA >> 7h ; Peripheral page
LACC #0100h ; clear compare int. flag
SACL EVAIFRA ; in EVAIFRA
CLRC INTM ; Enable all interrupts

Program Examples C-31

Program Examples

RET

SISR27:
LDP #0E1h ; Peripheral page
SPLK #0FF08h,PBDATDIR ; Set IOPB3
CALL DELAY
LDP #GPTCONA >> 7h ; Peripheral page
LACC #0080h ; clear period int. flag
SACL EVAIFRA ; in EVAIFRA
CLRC INTM ; Enable all interrupts
RET

DELAY LAR AR0,#01h ; Gen. purpose delay

D_LOOP RPT #01h ; Delay parameters may need to be
NOP ; modified for easy observation
BANZ D_LOOP
RET

GISR1: RET
GISR3: RET
GISR4: RET
GISR5: RET
GISR6: RET

PHANTOM RET

.end

C-32
 Program Examples

;===========================================================================
* File name : CAP.asm *
* Description : PROGRAM TO CHECK THE CAPTURE UNITS OF 240X *
* This program checks the Capture units of EVA & EVB. On each EV module, *
* the capture units are setup to detect different transitions. On EVA, *
* CAP1 detects a rising edge, CAP2 detects a falling edge and CAP3 detects *
* both edges. All capture interrupts are enabled. Timers 1 & 2 provide *
* input signals (through external connections) and also serve as a *
* time−base for these capture units. Upon detection, the capture interrupt *
* reads the proper CAPFIFO value to ensure that the capture units detected *
* the correct transition. The same scheme is implemented on EVB, to check *
* CAP4,5 and 6 using Timers 3 and 4. *
;===========================================================================

* Both Timers count in CONTINUOUS−UP mode.

* CAP1 is rising edge detect (T1 CMP Active low) *
* CAP2 is falling edge detect (T1 CMP Active low) *
* CAP3 on both edges (T2 CMP Active high) *

* This program tests the following in EVA :− *

* CAP1 & CAP2 using Timer 1 *
* CAP3 using Timer 2 *

* This program tests the following in EVB :− *

* CAP4 & CAP5 using Timer 3 *
* CAP6 using Timer 4 *

* COMMENTS: Connect T1CMP to CAP1,2; T2CMP to CAP3 inputs *

* Connect T3CMP to CAP4,5; T4CMP to CAP6 inputs *

* PERIPHERAL CODE : 5 (EVA) and 6 (EVB) *

* TEST CODE : CAP 1,2,3,4,5,6 − 1,2,3,1,2,3 respectively *

.title ” EV capture test” ; Title

.include ”240xA.h” ; Variable and register declaration
.include ”vector.h” ; Vector label declaration

del .set 0fffh ; define delay

.text
START: LDP #0h ; set DP=0
SETC INTM ; Disable interrupts
SPLK #0000h,IMR ; Mask all core interrupts
LACC IFR ; Read Interrupt flags
SACL IFR ; Clear all interrupt flags
LDP #WDKEY >> 7h ; Peripheral page
SPLK #006Fh, WDCR ; Disable WD if VCCP=5V

LDP #SCSR1>>7
SPLK #000Ch,SCSR1 ; EVA & EVB modules clock enable

LDP #EVAIMRA>>7 ; Peripheral page

SPLK #0FFFFh,EVAIFRA ; clear all EVA interrupt flags
SPLK #0FFFFh,EVAIFRB
SPLK #0FFFFh,EVAIFRC

Program Examples C-33

Program Examples

LDP #EVBIMRA>>7 ; Peripheral page

SPLK #0FFFFh,EVBIFRA ; clear all EVB interrupt flags
SPLK #0FFFFh,EVBIFRB
SPLK #0FFFFh,EVBIFRC

LAR AR7,#del ; Load AR7 with delay value

MAR *,AR7 ; Set ARP to ar7
LDP #0E1h ; Peripheral page
SPLK #1111111111111111b,MCRA ; enable all EV signals
SPLK #1111111111111111b,MCRC ; enable all EV signals

*=====================================================================
* EVA Capture test
* This portion of the code tests the EVA Capture unit. It is assumed
* that the test is failed, unless an interrupt is called (error code 4)
* GISR4 verifies the values in CAPFIFO and reports the results.

* PERIPHERAL CODE : 5, TEST CODE : 1,2,3 After successful completion

* of this test case, the value 5100,5200,5300 must be present in 351h,
* 352, 353 (DM) respectively
*
* Error code: 5101 −− CAP1 value is incorrect
* 5102 −− CAP2 value is incorrect
* 5103 −− CAP3 value is incorrect
*=====================================================================
* Load EVA TIMERS registers
LDP #GPTCONA >> 7h ; Peripheral page
SPLK #0000000001001001b,GPTCONA
; 0000 0000 0
; 1 − Enable Compare o/ps
; 00 reserved
; 10 − T2 CMP active hi
; 01 − T1 CMP active lo
SPLK #0000000000000000b,T1CNT ; zero timer 1 count
SPLK #0000000000000000b,T2CNT ; zero timer 2 count
SPLK #0001011101000010b,T1CON
; 000 10 Cont, Up
; 111 x/128,
; 0 reserved for T1,Tenable select
; 1 Tenable for Timer 1
; 00 Internal clk
; 00 cntr =0
; 1 enable compare
; 0 use own period register
SPLK #0001011111000011b,T2CON
; TSWT1=1: Use Timer 1 tenable bit
; SELT1PR=1: Use Timer 1 period
; register

SPLK #1111111111111111b,T1PR
SPLK #0011111100000000b,T1CMPR
SPLK #0011111100000000b,T2CMPR
SPLK #0000000000000000b,EVAIMRA
SPLK #0000000000000000b,EVAIMRB
; disable group A,B interrupts

C-34
 Program Examples

* Load Capture registers

SPLK #0011001001101100b,CAPCONA
; 0 clear capture registers
; 01−enable Capture 1,2 disable QEP
; 1 −enable Capture 3
; 0 −reserved
; 0 −Use GPTimer 2 for CAP3
; 1 −Use GPTimer 1 for CAP1,2
; 0 −No ADC start on CAP3 interrupt
; 01 −CAP1 is rising edge detect
; 10 −CAP2 is falling edge detect
; 11 −CAP3 on both edges
; 00 −reserved
SPLK #0000000000000111b,EVAIMRC
; 0000 0000 0000 0
; 111, enable CAP3,CAP2,CAP1
; interrupts

LDP #6h ; Write the failure code to begin

; with.
SPLK #5101h,51h ; This will be overwritten if the
; test passes
SPLK #5201h,52h
SPLK #5301h,53h

LDP #0
SPLK #0000000000001000b,IMR ; Enable INT4
CLRC INTM ; Enable interrupts globally

CALL CAPDLY

*=====================================================================
* EVB Capture test
* This portion of the code tests the EVB Capture unit. It is assumed
* that the test is failed, unless an interrupt is called (error code 4)
* GISR4 verifies the values in CAPFIFO and reports the results.

* PERIPHERAL CODE : 6, TEST CODE : 1 After successful completion

* of this test case, the value 6100,6200,6300 must be present in 361h,
* 362, 363 (DM) respectively.
*
* Error code: 6101 −− CAP1 value is incorrect
* 6201 −− CAP2 value is incorrect
* 6301 −− CAP3 value is incorrect
*=====================================================================

* Load EVB TIMERS registers

SETC INTM
LDP #GPTCONB >> 7h ; Peripheral page
SPLK #0000000001001001b,GPTCONB
; 0000 0000 0
; 1 − Enable Compare o/ps
; 00 reserved

Program Examples C-35

Program Examples

; 10 − T2 CMP active hi
; 01 − T1 CMP active lo
SPLK #0000000000000000b,T3CNT ; zero timer 3 count
SPLK #0000000000000000b,T4CNT ; zero timer 4 count
SPLK #0001011101000010b,T3CON
; 000 10 Cont, Up
; 111 x/128,
; 0 reserved for T3,Tenable select
; 1 Tenable for Timer 3
; 00 Internal clk
; 00 cntr =0
; 1 enable compare
; 0 use own period register
SPLK #0001011111000011b,T4CON
; TSWT3=1: Use Timer 3 tenable bit
; SELT3PR=1: Use Timer 3 period
; register

SPLK #1111111111111111b,T3PR
SPLK #0011111100000000b,T3CMPR
SPLK #0011111100000000b,T4CMPR
SPLK #0000000000000000b,EVBIMRA
SPLK #0000000000000000b,EVBIMRB
; disable group A,B interrupts

* Load Capture registers

SPLK #0011001001101100b,CAPCONB
; 0 clear capture registers
; 01−enable Capture 4,5 disable QEP
; 1 −enable Capture 6
; 0 −reserved
; 0 −Use GPTimer 4 for CAP6
; 1 −Use GPTimer 3 for CAP4,5
; 0 −No ADC start on CAP6 interrupt
; 01 −CAP4 is rising edge detect
; 10 −CAP5 is falling edge detect
; 11 −CAP6 on both edges
; 00 −reserved
SPLK #0000000000000111b,EVBIMRC
; 0000 0000 0000 0
; 111, enable CAP6,CAP5,CAP4
; interrupts

LDP #6h ; Write the failure code to begin

; with.
SPLK #6101h,61h ; This will be overwritten if the
; test passes
SPLK #6201h,62h
SPLK #6301h,63h
CLRC INTM ; Enable interrupts globally

CALL CAPDLY

C-36
 Program Examples

;=====================================================================
; Exit routine
;=====================================================================
LDP #0h
SPLK #0h,IMR ; Mask all interrupts
LACC IFR ; Read Interrupt flags
SACL IFR ; Clear all interrupt flags
SETC INTM
LDP #EVAIMRA>>7 ; Peripheral page
SPLK #0h,EVAIMRA ; Mask all EVA interrupts
SPLK #0h,EVAIMRB
SPLK #0h,EVAIMRC
SPLK #0FFFFh,EVAIFRA ; clear all EVA interrupt flags
SPLK #0FFFFh,EVAIFRB
SPLK #0FFFFh,EVAIFRC
LDP #EVBIMRA>>7 ; Peripheral page
SPLK #0h,EVBIMRA ; Mask all EVB interrupts
SPLK #0h,EVBIMRB
SPLK #0h,EVBIMRC
SPLK #0FFFFh,EVBIFRA ; clear all EVB interrupt flags
SPLK #0FFFFh,EVBIFRB
SPLK #0FFFFh,EVBIFRC
LDP #SCSR1>>7
SPLK #0000h,SCSR1 ; disable EVA & EVB clocks
LDP #GPTCONA>>7
SPLK #0000000000000000b,T1CON
SPLK #0000000000000000b,T2CON
LDP #GPTCONB>>7
SPLK #0000000000000000b,T3CON
SPLK #0000000000000000b,T4CON

DONE B DONE ; End of test module

;==================================================================
; ISR
;==================================================================
GISR4: ; Int4 GISR
NOP
LDP #PIVR >> 7h ; Peripheral page
LACL PIVR ; PIVR value
XOR #0033h ; CAP1 interrupt
BCND SISR33,eq
LACL PIVR ; PIVR value
XOR #0034h ; CAP2 interrupt
BCND SISR34,eq
LACL PIVR ; PIVR value
XOR #0035h ; CAP3 interrupt
BCND SISR35,eq
LACL PIVR ; PIVR value
XOR #0036h ; CAP4 interrupt
BCND SISR36,eq
LACL PIVR ; PIVR value
XOR #0037h ; CAP5 interrupt
BCND SISR37,eq
LACL PIVR ; PIVR value

Program Examples C-37

Program Examples

XOR #0038h ; CAP6 interrupt

BCND SISR38,eq
RET

SISR33: ; CAP1 SISR

LDP #GPTCONA >> 7h ; Peripheral page
SPLK #0001h,EVAIFRC ; clear Capture flag
LDP #0h
BLDD #CAP1FIFO,70h
BLDD #CAP1FIFO,71h
LACL 70h ; Check FIFO values
XOR #0h
BCND CAP1FAIL,NEQ
LACL 71h
XOR #0h
BCND CAP1PASS,EQ
CAP1FAIL ; Report CAP1 error
LDP #6h
SPLK #5101h,51h
B END_INT
CAP1PASS
LDP #6h
SPLK #5100h,51h
END_INT CLRC INTM
RET

SISR34: ; CAP2 SISR

LDP #GPTCONA >> 7h ; Peripheral page
SPLK #0002h,EVAIFRC ; clear Capture flag
LDP #0h
BLDD #CAP2FIFO,72h
BLDD #CAP2FIFO,73h
LACL 72h ; Check FIFO values
XOR #3F00h
BCND CAP2FAIL,NEQ
LACL 73h
XOR #3F00h
BCND CAP2PASS,EQ
CAP2FAIL ; Report CAP2 error
LDP #6h
SPLK #5201h,52h
B END_INT
CAP2PASS
LDP #6h
SPLK #5200h,52h
CLRC INTM
RET

SISR35: ; CAP3 SISR

LDP #GPTCONA >> 7h ; Peripheral page
SPLK #0004h,EVAIFRC ; clear Capture flag
LDP #0h
BLDD #CAP3FIFO,74h
BLDD #CAP3FIFO,75h

C-38
 Program Examples

LACL 74h ; Check FIFO values

XOR #0h
BCND CAP3FAIL,NEQ
LACL 75h
XOR #3F00h
BCND CAP3PASS,EQ
CAP3FAIL ; Report CAP3 error
LDP #6h
SPLK #5301h,53h
B END_INT
CAP3PASS
LDP #6h
SPLK #5300h,53h
CLRC INTM
RET

SISR36: ; CAP4 SISR

LDP #GPTCONB >> 7h ; Peripheral page
SPLK #0001h,EVBIFRC ; clear Capture flag
LDP #0h
BLDD #CAP4FIFO,76h
BLDD #CAP4FIFO,77h
LACL 76h ; Check FIFO values
XOR #0h
BCND CAP4FAIL,NEQ
LACL 77h
XOR #0h
BCND CAP4PASS,EQ
CAP4FAIL ; Report CAP4 error
LDP #6h
SPLK #6101h,61h
B END_INT
CAP4PASS
LDP #6h
SPLK #6100h,61h
CLRC INTM
RET

SISR37: ; CAP5 SISR

LDP #GPTCONB >> 7h ; Peripheral page
SPLK #0002h,EVBIFRC ; clear Capture flag
LDP #0h
BLDD #CAP5FIFO,78h
BLDD #CAP5FIFO,79h
LACL 78h ; Check FIFO values
XOR #3F00h
BCND CAP5FAIL,NEQ
LACL 79h
XOR #3F00h
BCND CAP5PASS,EQ
CAP5FAIL ; Report CAP5 error
LDP #6h
SPLK #6201h,62h
B END_INT

Program Examples C-39

Program Examples

CAP5PASS
LDP #6h
SPLK #6200h,62h
CLRC INTM
RET

SISR38: ; CAP6 SISR

LDP #GPTCONB >> 7h ; Peripheral page
SPLK #0004h,EVBIFRC ; clear Capture flag
LDP #0h
BLDD #CAP6FIFO,7Ah
BLDD #CAP6FIFO,7Bh
LACL 7Ah ; Check FIFO values
XOR #0h
BCND CAP6FAIL,NEQ
LACL 7Bh
XOR #3F00h
BCND CAP6PASS,EQ
CAP6FAIL ; Report CAP6 error
LDP #6h
SPLK #6301h,63h
B END_INT
CAP6PASS
LDP #6h
SPLK #6300h,63h
CLRC INTM
RET

;======================================================================
; Delay routine
;======================================================================

CAPDLY MAR *,AR0 ; Routine to generate delay

; between modes
LAR AR0,#0FFFFh
CAPDLP2 RPT #0FFh
NOP
BANZ CAPDLP2
RET

PHANTOM RET

GISR1 RET
GISR2 RET
GISR3 RET
GISR5 RET
GISR6 RET
.end

C-40
 Appendix
AppendixDA

2.0 ./0&./0, 3
' ! 4

$     

This appendix describes the boot-load sequence and discusses SPI

synchronous and SCI asynchronous transfer protocol and data formats.

Topic Page

D.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2

D.2 Protocol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-6

D-1
Introduction

D.1 Introduction
The LF240xA/LF240x Digital Signal Processors (DSPs) include on-chip
read-only memory (ROM) containing bootloader code. This code loads code
from an external serial boot device at reset and transfers control to the code
loaded from the external device. This chapter describes working with this
feature of the device.

The LF240xA/LF240x device Boot ROM offers the user two options: it can load
code through either asynchronous or synchronous serial transfer.

The synchronous transfer is done through the serial peripheral interface (SPI),
and the asynchronous transfer is done through the serial communications
interface (SCI). The code is loaded to a user-specified location which is
completely flexible; it can be anywhere in program memory where RAM is
available. The serial transfer packet must contain the address as specified in
the applicable Serial Transfer Format, which is described in section D.2,
Protocol Definitions, on page D-6.

D.1.1 Boot-Load Sequence

There are a few things that must be set up correctly for the control to transfer
to the Boot ROM and a valid boot load to occur:

1) Microcontroller mode. In the case of LF2407A/LF2407, the device must

be placed in microcontroller mode by pulling the MP/MC pin LOW.

2) Boot ROM loader invocation. The bootloader is invoked by pulling the

BOOT EN/XF pin low through a resistor, prior to device reset. This trans-
fers control to the boot-load program located in the on-chip ROM. At reset
time, internal logic takes a “snapshot” of this pin and, if this pin is a low lev-
el, then the Boot ROM appears in the memory map as shown in
Figure D−2 on page D-5. Otherwise, the on-chip flash memory is en-
abled and the program counter begins execution at 0000h. This pin can
be driven high/low or through a jumper via a resistor, allowing control of
the boot sequence of the DSP. The resistor must be present since the
XF pin is an output at all other times.

3) PLL Multiplier selection (available on LF240xA only). Bootloader code

sets the PLL to multiply the incoming clock by either x2 or x4. This selec-
tion is made by looking at the state of the IOPA0 pin at reset. If this pin is
pulled low, the PLL is set to multiply by x2. If the pin is pulled high, the PLL
is set to multiply the incoming clock by a factor of x4. It is recommended
that this pin be pulled high or low through a resistor since this pin will be
an output when set to the primary function. Refer to Table D−1 on

D-2
 Introduction

page D-8 for the effect on the SCI bootload lock. Also note that the com-
bination of the PLL multiplication factor chosen and the input clock fre-
quency must result in a clock rate less than or equal to the maximum CPU
clock rate allowed for the device.
On the LF240x devices, the PLL multiplication factor is always set to x4 by
the Boot ROM initialization code.
4) SCI or SPI selection. The bootloader code selects the source of the in-
coming code, depending on the state of the IOPC2 pin on the device. The
code takes a snapshot of this pin after being invoked, and determines
which loader (SPI or SCI) to invoke based on the status of this pin.
 If IOPC2 is pulled low, an SCI transfer is commenced.
 If IOPC2 is pulled high, an SPI transfer is commenced.
 Note that the SPI selection is invalid on devices without the SPI.
It is suggested that this pin should be driven via a resistor as well,
because SPISIMO will be an output if the SPI is used at any time dur-
ing the operation of the system.
5) Destination check. The incoming destination is now compared to the
range FE00h to FFFFh. If the destination matches this range, the CNF bit
(Bit 12) in status register ST1 is set, configuring the DARAM memory block
B0 to Program Memory Space. No other checks are performed and it is
entirely up to the host/external boot device to supply a valid combination
of the memory destination address and the length for the incoming
code.This means that the target code must fit into the internal memory or
external memory must be available.
6) Data transfer. Once the incoming destination and length are fetched (this
protocol is defined in separate sections for the SCI and SPI), the actual
data transfer commences. The fetch is basically destination, length, and
data with no error-checking. On the SCI, the incoming data is echoed back
allowing the host to implement error-checking, if desired.
7) Execution of incoming code. Once the Boot ROM loader completes
transfer of the packet, a branch is made into the incoming code.
8) Watchdog. The watchdog timer on the device is active during the entire
sequence and is being reset at key points in the code. When a branch is
made into the user code, it is the responsibility of the user code to handle
watchdog overflow as appropriate.
9) Restrictions on the incoming code.
 The combination of the destination address and transfer length must
point to valid locations. There is absolutely no error-handling whatso-
ever.

TMS320F240x/240xA Boot ROM Loader: Protocols and Interfacing D-3

Introduction

 The combination also must point to a memory block that is contiguous.

 The address check is performed only on the first location of the incom-
ing destination. It is expected that this allows enough space for the rest
of the incoming words. This means that if you have external program
memory at range FDFEh to FDFFh (two words) and you attempt to
load code into the range FDFEh to FEFFh (attempting to use the inter-
nal memory FE00h to FEFFh), this combination is invalid since the
destination check will not switch B0 into the program space upon en-
countering the destination FDFEh. Lastly, the incoming address and
length are expected to be 16 bits, as defined in the SPI and SCI trans-
fer protocols.

Figure D−1. Example Hardware Configuration for LF240xA Boot ROM Operation
SCI boot SPI boot
load load
VDD
LF240xA EEPROM

SPISIMO/IOPC2 DIN
SPISOMI DOUT
SPICLK CLK
BOOT EN/XF CS
BOOT EN

Boot Flash
ROM execute Host
VDD
RS232
transceiver

SCITXD/IOPAO
SCIRXD

PLL=x2 PLL=x4 (PLL multiplier

(PLL multiplier
is set to x2) VDD is set to x4)

Note: For LF240x devices, the bootloader sets the PLL to x4 mode. For LF240xA devices, the multiplier depends on the state of
the IOPA0 pin. For a list of valid CLKIN frequencies, refer to Table D−1, Clock Speeds At Which Baud Rate Locks, on
page D-8.

D-4
 Introduction

Figure D−2. Memory Maps for the LF240xA/LF240x Devices in Microcontroller Mode
0000
0000

ÉÉÉÉÉÉÉÉÉÉÉ
Bootloader

ÉÉÉÉÉÉÉÉÉÉÉ
00FF

ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ Reserved

ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
7FFF

ÉÉÉÉÉÉÉÉÉÉÉ
8000
SARAM

ÉÉÉÉÉÉÉÉÉÉÉ
2K words
(Program/Data) 7FFF
87FF
8800
Bootloader enabled
(BOOT EN/XF = 0)

External
(off-chip)

FDFF
FE00
Reserved† (CNF = 1) 32K on-chip Flash memory
External (CNF = 0) (External if MP/MC = 1)
FEFF
Note: Flash size varies depending on the
FF00
On-Chip DARAM (B0)† (CNF = 1) device. LF2407A is depicted as an
External (CNF = 0) example.
FFFF
† When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory
space. For example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are
referred to as reserved when CNF = 1.
Note: When boot ROM is enabled, on-chip locations 0000−00FFh in program memory is mapped to the bootloader. Boot ROM
and Flash Memory share the same starting address, and hence, are not visible (active) at the same time. If the BOOT
EN/XF pin = 0 during reset, the BOOT EN bit in SCSR2 register (bit 3) will be set and will enable the Boot ROM at 0000 in
program space. While Boot ROM is enabled, the entire Flash memory will be disabled. The SCSR2.3 bit should be dis-
abled (0) to have Flash array enabled instead of Boot ROM. See Appendix D for bootloader details.

TMS320F240x/240xA Boot ROM Loader: Protocols and Interfacing D-5

Protocol Definitions

D.2 Protocol Definitions

The transfer of data is done according to a defined protocol for the SPI and
SCI. The protocol for the synchronous transfer over the SPI is discussed in
section D.2.1, and the protocol for the SCI transfer is discussed in
section D.2.2.

D.2.1 SPI Synchronous Transfer Protocol and Data Formats

The ROM loader expects an 8-bit-wide SPI-compatible EEPROM device to be
present on the SPI pins as indicated in Figure D−1, Example Hardware
Configuration for LF240xA Boot ROM Operation, on page D-4. If the
download is to be performed from an SPI port on another device, then that
device must be set up to operate in the slave mode and mimic a serial
EEPROM. Immediately after entering the SPI loader, the pin functions for the
SPI pins are set to primary, and the SPI is initialized. The initialization is done
at the slowest speed possible. The data transfer is done in “burst” mode for the
EEPROM. The transfer is carried out entirely in byte mode (SPI at 8
bits/character). A step-by-step description of the sequence follows:
1) The SPI is initialized.
2) The XF pin is now used as a chip-select for the EEPROM.
3) The SPI outputs a read command for the EEPROM (03h).
4) The SPI sends the EEPROM an address 0000h; that is, the host requires
that the EEPROM must have the downloadable packet beginning at ad-
dress 0000h in the EEPROM.
5) From this point onward, the next two bytes fetched constitute the destina-
tion address.
The most significant byte of this word is the byte read first, and the
least significant byte is the next byte fetched. This is true of all word
transfers on the SPI.
6) The next word (two bytes) fetched is the length N.
7) The destination is checked to see if it is in the range FE00h to FFFFh. If
necessary, the DARAM block B0 is configured in program memory space.
8) From now on, N words are fetched and stored in program memory at the
address pointed to by destination. The EEPROM is read off in one continu-
ous burst.
9) Finally, once the last word is stored, a simple branch is made into the code
at the destination address; therefore, the entry point for the boot-loaded
code must be at the destination address.

D-6
 Protocol Definitions

Figure D−3. SPI Data Packet Definition

Byte0:Byte1 Destination

Byte2:Byte3 Length (n)

Byte4:Byte5 Opcode 0

Byte6:Byte7 Opcode 1

•
•
•

Opcode n−1

D.2.2 SCI Asynchronous Transfer Protocol and Data Formats

The SCI-based loader operation is more involved than the SPI-based loader
operation. The SCI-based loader incorporates a mechanism for baud-rate
matching. Once the baud rate from the host is matched, the SCI loader
commences the transfer. Section D.2.2.1 describes the baud rate protocol.

D.2.2.1 Baud Rate Protocol

The baud rate over the communication link is always 38400 bps. The baud rate
protocol is necessary because the LF240xA device may be operated at
different speeds. The underlying assumption for the baud rate matching is that
the device is clocked at a clock frequency from a given, predetermined set. The
host is required to send “probe” characters, with the hexadecimal value 0Dh
(same as the carriage return character). The target listens in on the serial port,
at the set speeds, in succession. Every time a character is detected, it is
compared to 0Dh. If more than three characters do not match, the target tries
a new baud rate. If the baud rate is correct and the character matches 0Dh,
then the target expects to receive nine successive 0Dh characters. If any other
character is received, the baud match fails. Once the nine characters are
received correctly, the target sends an acknowledge character. Once the
acknowledge character is sent, each and every character hereafter is bounced
back to the host to ensure data transfer integrity. All the communications are
with 8 bit characters, 1 stop bit, and no parity. Baud rate locks are possible at
clock speeds/CLKIN combinations listed in Table D−1, Clock Speeds at Which
Baud Rate Locks, on page D-8 A flowchart of the baud rate match protocol
is shown in Figure D−4, Flowchart for the Serial Loader Baud Rate Match
Algorithm, on page D-9.

TMS320F240x/240xA Boot ROM Loader: Protocols and Interfacing D-7

Protocol Definitions

Table D−1. Clock Speeds at Which Baud Rate Locks

CLKIN (MHz) CLKIN (MHz)

CLKOUT (MHz) PLL = x4 PLL = x2
40† 10† 20†

36† 9† 18†

32† 8† 16†

30 7.5 15†

28 7 14†

24 6 12†

20 5 10†

16 4 8†
† Note that these clocking options are valid only on the LF240xA; i.e., not available on the LF240x.

D.2.2.2 Data Transfer

Once the communications are synchronized, the actual data transfer is

commenced. The first two bytes fetched are interpreted as the destination.
The next two bytes fetched are the length. Once the destination is known, a
check is performed to see if the destination lies within B0. If it does, then the
bootloader will switch the block B0 into program memory and transfer code into
B0. After this, the user code is transferred to the destination and then a branch
is executed to the first address of the code. So, as is the case with the SPI, the
entry point of the code must be at the first location for the SCI.

D.2.2.3 SCI Data Transfer Completion

A noteworthy point is the completion of transmission of the SCI data echo.

There can be a character still in transmission when the control is transferred
to the user code. So, if the user code does anything which disturbs the
transmission of the SCI, then that last character may be lost. An example is
changing the bit definition of the SCI transmit pin. If this is allowed, the host
must take this fact into account. A second possible option is to incorporate a
small delay in the user code, or perform an SCI check to confirm that the
character transmission is complete.

D-8
 Protocol Definitions

Figure D−4. Flowchart for the Serial Loader Baud Rate Match Algorithm

Initialize Baud Rate Parameters

Clear VBR COUNTER

Listen for a character

N
Is the RX flag set?

Fetch character

N
Is Char = 0x0D?

Increment VBR

N
Is VBR > max?

Send 0xAA to host

TMS320F240x/240xA Boot ROM Loader: Protocols and Interfacing D-9

Protocol Definitions

Figure D−5. Flowcharts for Serial Asynchronous Loader and the Fetch Header Routine

Start
B

FETCH SCI WORD

FETCH HEADER
Store destination address

FETCH SCI WORD

Get user code from the host
(XFER SCI 2 PROG)

Store length

Branch to user code

Return

D-10
 Protocol Definitions

Figure D−6. Flowchart for FETCH SCI WORD

Start

N Has a character
been received?

Store Lower Byte

Echo Byte to Host

N Has a character
been received?

Store High Byte

Echo Byte to Host

Form the word

Return

;*****************************************************************************

TMS320F240x/240xA Boot ROM Loader: Protocols and Interfacing D-11

Protocol Definitions

; File Name: BOOT.asm

; Originator: Digital Systems Control group (Texas Instruments)
;
;*****************************************************************************
; Constant definitions
;*****************************************************************************
READ_COMMAND .set 0300H ;Serial EEPROM Read Command in HByte
VBR_MAX .set 09h ;# times valid char needs to be received
CRC_MAX .set 03h ;# retries at each speed before giving up.

;*****************************************************************************
; Debug directives
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
.def GPR0 ;General purpose registers.
.def GPR1
.def GPR2
.def GPR3
.def DEST
.def LENGTH
.def data_buf
.def VBR_CNTR
.def DELAY
.def CHAR_RETRY_CNTR
.def BAUD_TBL_PTR
;*****************************************************************************
; Include header file for peripheral address references.
;
;*****************************************************************************
.include 240x.h

;*****************************************************************************
; Variable Declarations for on chip RAM Blocks
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
.bss GPR0,1 ;General purpose registers.
.bss GPR1,1
.bss GPR2,1
.bss GPR3,1
.bss DEST,1
.bss LENGTH,1
.bss stk0,1
.bss stk1,1
.bss data_buf,1
.bss VBR_CNTR,1
.bss DELAY,1
.bss CHAR_RETRY_CNTR,1
.bss BAUD_TBL_PTR,1

;*****************************************************************************
; M A C R O − Definitions
;*****************************************************************************
POINT_B1 .macro
LDP #06h
.endm

D-12
 Protocol Definitions

POINT_PF1 .macro

LDP #0E0h
.endm

;*****************************************************************************
; M A I N C O D E − starts here
;*****************************************************************************
.text
START:
SELECT_PLLMULT: LDP #PADATDIR>>7
SPLK #0000H,PADATDIR ;Config all I/O to be inputs.
LACC PADATDIR ;Read I/O pins.
AND #0001H ;Mask out all bits except IOPA0.
BCND PLL_MULT_4,NEQ ;If the pin is high, multiply
;by 4 (backward compatible).
;else
;continue with PLL_MULT_2.

PLL_MULT_2: LDP #SCSR1>>7

SPLK #0260h,SCSR1 ;
B SELECT_LOADER

PLL_MULT_4: LDP #SCSR1>>7

SPLK #0060h,SCSR1 ;

SELECT_LOADER: LDP #PCDATDIR>>7

SPLK #0000H,PCDATDIR ;Config all as i/ps.
;SPI pins MUST be I/Os by
;default at reset(controlled by MCRB).
LACC PCDATDIR

AND #0004H ;Mask for check on SPISIMO.

BCND SCI_LOADER,EQ ;if SPISIMO is low, branch to SCI load

;else SPI loader and set SPISTE high.

SETC XF ;Drive (!CS=XF) High.

;*****************************************************************************
; SPI Initialization
;*****************************************************************************
SPI_INIT:
LACC MCRB ;Set up the SPI pins to primary
;functions.
OR #001CH
SACL MCRB
LDP #SPICCR>>7
SPLK #0007h, SPICCR ;8 char bits,
SPLK #000Eh, SPICTL ;Enable master mode and enable talk.

TMS320F240x/240xA Boot ROM Loader: Protocols and Interfacing D-13

Protocol Definitions

SPLK #007fh, SPIBRR ;SPI Speed =

; ASAP (as slow as possible)
SPLK #0087h,SPICCR ;Relinquish SPI from Reset.

;*****************************************************************************
; Select the Serial EEPROM
; by driving the select line low.
;*****************************************************************************
CS_ACTIVE CLRC XF ;Drive (!CS=XF) Low.

;*****************************************************************************
; Next send the Serial EEPROM a ’Read Command’ − it is then
; read out in burst mode, two bytes at a time by using GET_WORD
; Note that CS stays low all the time.
;*****************************************************************************
LACC #READ_COMMAND ;Load Read Command for EEPROM
CALL XMIT_VALUE ;Transmit Read Command.

;*****************************************************************************
; Now send a word (16 bits) to the EEPROM as address.
; Hard coded zero bytes are sent by the GET_WORD, but this is fine
; since the EEPROM is defined to contain boot code at origin.
;
;*****************************************************************************
CALL GET_WORD ;Get word sends two zero chars
;i.e. Top address in EEPROM
;*****************************************************************************
; Do two word transfers and have the two words for
; (DEST)ination and (LENGTH) of code boot−loaded.
;*****************************************************************************
CALL GET_WORD
SACL DEST
SACL GPR1 ;GPR1 used as dest ptr in TBLW
CALL CHECK_DEST ;Decide if B0 is to be switched to
;program space
CALL GET_WORD
SACL LENGTH
;*****************************************************************************
; This segment does all the work to transfer the code to program memory.
;
;*****************************************************************************
MAR *,AR0
LAR AR0,LENGTH ;Load AR0 and set ARP = AR0
SBRK #1 ;AR = length−1, since the loop is
;executed N times for AR=(N−1).

XFER_TO_PROG: LDP #00E0h ;DP now points to WDOG/SPI/SCI

CALL reset_WD ;Watchdog reset routine
;reset_WD needs the DP to be 0xE0.

CALL GET_WORD ;get WORD does not care for DP!

D-14
 Protocol Definitions

SACL GPR0 ;Store word in GPR0 (temp storage)

LACC GPR1 ;Get current dest ptr in ACC.
TBLW GPR0 ;GPR0 is transferred to PGM_MEM
;pointed to by acc

ADD #1 ;Acc now points to the next location.

SACL GPR1 ;Store incremented pointer.
BANZ XFER_TO_PROG ;Repeat for length−1 time

;*****************************************************************************
; Finally the program is loaded in the memory.
; Branch to it and get there.
; As a last step, the Chip Select is de−activated.
;*****************************************************************************

CS_NOT_ACTIVE: SETC XF ;Drive (!CS=XF) High.

POINT_B1
LACC DEST ;Branch to Boot Loader Code.
BACC ;

;*****************************************************************************
;
; G E T _ W O R D
;
; This routine gets a word from the EEPROM and packs it.
; It is returned in the accumulator
;
;
; Exit Conditions:
; 1. DP is set to B1 on Exit.
; 2. ACC,GPR0 are destroyed.
; 3. Result returned in ACC
; 4. Does not care about DP on enter.
;*****************************************************************************

GET_WORD: LACC #0000H ;Zero Character

CALL XMIT_VALUE ;Transmit char & get response
POINT_B1
AND #0FFH ;MSByte of start address is in the
;acc. Get rid of any higher bits !
SACL GPR0 ;
LACC #0000H ;Zero Character
CALL XMIT_VALUE ;Transmit char & get response
POINT_B1
;LSByte of start address is in ACC
AND #00FFH ;Mask any upper byte
ADD GPR0,8 ;Bring in the MS Byte.
RET

TMS320F240x/240xA Boot ROM Loader: Protocols and Interfacing D-15

Protocol Definitions

;*****************************************************************************
; Transmit a char on the SPI Bus and return received data in accumulator
;
;
; Exit Conditions:
; 1. DP is set to B1 on Exit
; 2. ACC is destroyed.
; 3. Does not care about DP on enter
;
;*****************************************************************************
XMIT_VALUE: LDP #SPITXBUF>>7
SACL SPITXBUF ;Write xmit value to SPI TX Buffer.
XMIT_NCOMPL: BIT SPISTS,BIT6 ;Test SPI_INT bit
BCND XMIT_NCOMPL,NT ;If (bit=TC=0) ,then wait for TX Compl
;i.e., wait for transmit to finish
LACC SPIRXBUF ;Read also clears SPI_INT flag.
RET

;*****************************************************************************
; Transmit a char on the SPI Bus and return received data in accumulator
;
;
; Exit Conditions:
; 1. DP is set to B1 on Exit
; 2. ACC is destroyed.
;
;
;*****************************************************************************

;*****************************************************************************
; The rest of the implementation is the asynchronous serial port loader.
;*****************************************************************************
;Initialization
;*****************************************************************************
SCI_LOADER:
UART_INIT:

;*****************************************************************************
;SCI Initialization
;*****************************************************************************
SCI_INIT: LDP #MCRA>>7
LACC MCRA ; Set up pins as SCI pins.
OR #0003H
SACL MCRA
LDP #SCICCR>>7 ;1 stop bit, no parity,8bits/ch
SPLK #0007h, SCICCR ;async mode, idle−line protocol

LACK #0

SACL SCICTL2 ;Disable RX Int, TX Int.

SACL SCIHBAUD
SACL SCIPRI

D-16
 Protocol Definitions

;*****************************************************************************
; The SCI module is held in ’reset’ until the parameter is loaded
; for the Baud Rate register from the Baud Rate table in SCILBAUD
; so the next lines stay commented out!
;*****************************************************************************
; SPLK #0023h, SCICTL1 ;Relinquish SCI from Reset.
; SPLK #65, SCILBAUD ;
;*****************************************************************************
;Baudrate lock protocol with Host
;*****************************************************************************
CLR_VBR_CNTR: POINT_B1
SACL CHAR_RETRY_CNTR ;Clear retry counter
SACL VBR_CNTR ;Clear valid baud rate counter
SACL BAUD_TBL_PTR ;BAUD_TBL_PTR is really only
;the offset from BAUD_TBL.
UI00
SET_BAUD: LACC BAUD_TBL_PTR
ADD #BAUD_TBL
POINT_PF1

SPLK #0013h, SCICTL1 ;Enable TX, RX, internal SCICLK

TBLR SCILBAUD
SPLK #0023h, SCICTL1 ;Relinquish SCI from Reset.

UI01 CALL reset_WD

BIT SCIRXST,BIT6 ;Test RXRDY bit
BCND UI01, NTC ;If RXRDY = 0,then repeat loop
LACC SCIRXBUF ;First byte is Lo byte

;Check if Char is as expected

CHECK_CHAR AND #0FFh ;Clear upper byte
SUB #00Dh ;Compare with ”CR”
BCND BAUD_RETRY, NEQ

INC_VBRC POINT_B1
LACC VBR_CNTR ;Inc VBR counter
ADD #1h
SACL VBR_CNTR
SUB #VBR_MAX ;Is VBR counter > max value ?
POINT_PF1
BCND UI01, NEQ ;No! fetch another char

SND_ECHO LACC #0AAh ;Yes!

SACL SCITXBUF ;Indicate Host Baud rate lock
B BAUD_DETECTED

BAUD_RETRY POINT_B1
SPLK #0h, VBR_CNTR
LACC CHAR_RETRY_CNTR ;Inc CRC counter
ADD #1h
SACL CHAR_RETRY_CNTR
SUB #CRC_MAX ;Is CRC > max value ?
BCND INC_TBL_PTR, GEQ ;Yes! try next baud rate
POINT_PF1

TMS320F240x/240xA Boot ROM Loader: Protocols and Interfacing D-17

Protocol Definitions

B UI01 ;No! fetch another char

INC_TBL_PTR LACC BAUD_TBL_PTR ;Inc CRC counter

ADD #1h
AND #0007H ; BAUD_TBL_PTR is MOD(8)
SACL BAUD_TBL_PTR
SPLK #0h, CHAR_RETRY_CNTR
B UI00
BAUD_DETECTED:
;*****************************************************************************
;M A I N P R O G R A M
;*****************************************************************************
MAIN:
;Load & Execute incoming algorithm.

M00 CALL FETCH_HEADER

CALL CHECK_DEST

M01: CALL XFER_SCI_2_PROG

LACC DEST
BACC ; Branch to the address where
; code is loaded.

;*****************************************************************************
; Routine Name: F E T C H _ H E A D E R Routine Type: SR
;*****************************************************************************
FETCH_HEADER: CALL FETCH_SCI_WORD
LACC data_buf
SACL DEST
CALL FETCH_SCI_WORD
LACC data_buf
SACL LENGTH
RET

;*****************************************************************************
; Routine Name: X F E R _ S C I _ 2 _ P R O G Routine Type: SR
;*****************************************************************************
XFER_SCI_2_PROG:
MAR *, AR0
LAR AR0, LENGTH
LACC DEST ;ACC=dest address

XSP0 CALL FETCH_SCI_WORD

TBLW data_buf ;data_buff−−>[*ACC]
ADD #01h ;ACC++
BANZ XSP0 ;loop ”length” times
RET

D-18
 Protocol Definitions

;*****************************************************************************
; Routine Name: F E T C H _ S C I _ W O R D Routine Type: SR
;
; Description: Version that expects Lo byte/Hi byte sequence from Host &
; also echoes byte
;*****************************************************************************
FETCH_SCI_WORD: POINT_B1
SACL stk0
LDP #SCIRXST>>7
FSW0 CALL RESET_WD
BIT SCIRXST,BIT6 ;Test RXRDY bit
BCND FSW0, NTC ;If RXRDY = 0,then repeat loop
LACC SCIRXBUF ;First byte is Lo byte
SACL SCITXBUF ;Echo byte back
AND #0FFh ;Clear upper byte

FSW1 CALL RESET_WD

BIT SCIRXST,BIT6 ;Test RXRDY bit
BCND FSW1, NTC ;If RXRDY=0,then repeat loop
NOP
ADD SCIRXBUF,8 ;Concatenate Hi byte to Lo
SFL ;used because 7 is max in SACH
SACH SCITXBUF,7 ;Echo byte back (after SFL 8)

POINT_B1
SFR ;restore ACC as before
SACL data_buf ;Save received word

LACC stk0
RET

;*****************************************************************************
; Check the destination address, and switch B0 into program space if needed.
;*****************************************************************************

CHECK_DEST: LACC DEST

AND #0FE00H ;Anywhere in B0 means flip B0
SUB #0FE00h ;use both pri & sec B0 ranges
AND #0FFFFH ;mask bits in Acc High.
BCND CHK_DST_EXIT,NEQ
SETC CNF
CHK_DST_EXIT: RET

;*****************************************************************************

Reset_WD: SPLK #05555h, WDKEY

SPLK #0AAAAh, WDKEY
RET

;*****************************************************************************

TMS320F240x/240xA Boot ROM Loader: Protocols and Interfacing D-19

Protocol Definitions

;*****************************************************************************
; Table of SCI_LBAUD Contents.
;*****************************************************************************
; SCI_LBAUD @38.4 Kbps ; SYSCLK ; CLKIN
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
BAUD_TBL: .word 130 ; 40MHz ; 10 MHz
.word 117 ; 36MHz ; 9.0 MHz
.word 104 ; 32MHz ; 8.0 MHz
.word 97 ; 30MHz ; 7.5 MHz
.word 91 ; 28MHz ; 7.0 MHz
.word 78 ; 24MHz ; 6.0 MHz
.word 65 ; 20MHz ; 5.0 MHz
.word 52 ; 16MHz ; 4.0 MHz

.end

D-20
 Appendix
AppendixEA

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This chapter describes the Flash/ROM code security features, lists the code
security module (CSM) registers, and discusses programming considerations
for TMS320LF/LC240xA devices with and without code security.

Topic Page

E.1 Flash/ROM Security Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2

E.2 Technical Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5
E.3 Environments that Require Security Unlocking . . . . . . . . . . . . . . . . . . E-7
E.4 Unsecuring Considerations for Devices With/Without
Code Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-9
E.5 DOs and DON’Ts to Protect Security Logic . . . . . . . . . . . . . . . . . . . . . E-10
E.6 CSM Features − Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-12
E.7 CSM − Frequently Asked Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . E-13

E-1
Flash/ROM Security Feature

E.1 Flash/ROM Security Feature

TMS320LF2407A, LF2406A, LF2403A, LF2402A (LF240xA) flash devices
and LC2406A, LC2404A and LC2402A (LC240xA) ROM devices are
designed with on-chip Flash and ROM memories in program space. These
memories range from 32K words to 6K words depending on the device
derivative in this family. All of these devices have a code security logic that can
protect access to their respective Flash or ROM program memory spaces.

E.1.1 Functional Description

In many applications, there is an increasing need to have code security once
the application code is fully developed and released to production. Security is
defined with respect to the read access to on-chip program memory, and
prevents unauthorized copying of proprietary code. The security module is
intended to block the CPU’s read access to on-chip program memory. This in
effect blocks read access to Flash/ROM through the JTAG port or external
peripherals. The Security Mode Table (Table E−1) explains the conditions
under which the 240xA devices are considered secure or unsecure.

Table E−1. Security Mode Table

240xA memory
Mode access Mode select conditions Device status Remarks
1 Runtime using on-chip MP/MC = 0 (upon reset) − Unsecure Code is free-run from
program memory Microcontroller mode. on-chip flash/ROM.
(without JTAG (On-chip bootloader Typical usage of the DSP
connector connected) disabled) in an end-product.

2 Runtime using external MP/MC = 1 (upon reset) − Secure Code is run from external
program memory Microprocessor mode. program memory.
(On-chip flash/ROM and
bootloader disabled)

3 Using TI debugger Secure Debugging/testing the

(ex., Code Composer) device with the aid of a
JTAG connector.

4 While running BOOT XF/BOOT EN = 0 Secure On-chip bootloader is

ROM code (upon reset) invoked.

E-2
 Flash/ROM Security Feature

Mode 1: This is the typical mode that would be employed in the end-customer
application. The application code stored in on-chip flash/ROM free runs. In this
mode, the device is unsecure, since the core should be able to read the
contents of on-chip flash/ROM to be able to execute it. The JTAG port is left
unconnected. Connecting the JTAG connector would immediately secure the
device, thereby thwarting any attempt to read the contents of flash/ROM. To
reiterate, during run-time execution of the application, the device will run the
application without any impact from the “Code Security Module (CSM)”, which
is inactive. If visibility to flash/ROM contents is desired, the device must be first
unsecured.

Mode 2: If the DSP is powered up in microprocessor mode, the device is

immediately secured. If a code running in external memory needs to access
the on-chip flash memory, the device must be first unsecured.

Mode 3: If access to on-chip flash/ROM is desired using a debugger (via

JTAG), the device must be first unsecured.

Mode 4: If the on-chip bootloader is invoked, the device is immediately

secured. If the bootloader transfers any code that needs access to on-chip
flash, the device must be first unsecured.

In all the four modes, the device is unsecured by executing the “Password
Match Flow (PMF)”.

E.1.2 CSM Impact on Other On-Chip Resources

The CSM has no impact whatsoever on the following on-chip resources:

RAM blocks such as DARAM and SARAM − These memory blocks can
be freely accessed and code run from them, whether the device is in se-
cure or unsecure mode.

Boot ROM contents − Visibility to the boot ROM contents is not impacted
by the CSM; however, invoking the boot ROM code would immediately se-
cure the device.

On-chip peripheral registers − The peripheral registers can be initialized

by code running off on-chip program memory, whether the device is in se-
cure or unsecure.

To summarize, it is possible to load code onto on-chip program RAM via the
JTAG connector without any impact from the CSM. The code can be debugged
and the peripheral registers initialized, independent of whether the device is
in secure or unsecure mode.

Flash/ROM Code Security For LF/LC240xA DSP Devices E-3

Flash/ROM Security Feature

E.1.3 Incorporating Code Security in User Applications

Code security is typically not required in the development phase of a project;
however, security is needed once a robust code is developed. Before such a
code is programmed in the flash memory (or committed to ROM), a password
should be chosen to secure the device. Once a password is in place, the
device is secured (i.e., programming a password at the appropriate locations
is the action that secures the device). From that time on, access to debug the
contents of flash/ROM by any means (via JTAG, code running off
external/on-chip memory etc.) requires the supply of a valid password. A
password is not needed to run the code out of flash/ROM (such as in a typical
end-customer usage); however, access to flash/ROM contents for debug
purpose requires a password.

E-4
 Technical Definitions

E.2 Technical Definitions

Secure − CPU’s read access to the on-chip Flash/ ROM memory locations
is blocked. This is also referred to as the Code Secure mode of the device.
This in effect blocks the JTAG debugger read access to on-chip flash or
ROM locations. Furthermore, the flash cannot be cleared, erased or
programmed while the device is in the secure mode. The device must be
unsecured before these operations can commence.

Unsecure − CPU’s read access to on-chip Flash/ ROM memory locations

is not blocked. All program memory locations are unprotected and;
therefore, allows unhindered CPU read and flash programming
operations.

Password − 64-bit data (four 16-bit words) that is used to secure or

unsecure the device.

Password locations (PWL) − Code security password locations in

Flash/ROM memory (0040h, 0041h, 0042h and 0043h). These locations
store the password pre-determined by the system designer.
In flash devices, the password can be changed anytime if the old
password is known. In ROM devices, the password cannot be changed
after the device is manufactured by Texas Instruments (TI).
If PWL have all 64 bits as ones or zeros, the device is unsecure. Since new
flash devices have erased flash (all ones), the device comes up in
unsecure mode. To summarize, a device with a cleared/erased flash array
is unsecure.

KEY registers − User accessible registers (four 16-bit words) which will
be used to secure or unsecure the device. These registers are mapped in
the data memory space at addresses 77F0h, 77F1h, 77F2h and 77F3h.

Flash/ROM Code Security For LF/LC240xA DSP Devices E-5

Technical Definitions

Table E−2. Code Security Module (CSM) Registers

Data Memory
Address Register Name Reset Values Register Description
77F0h KEY3 FFFFh High word of the 64-bit KEY register

KEY registers − Accessible by the user

77F1h KEY2 FFFFh Third word of the 64-bit KEY register

77F2h KEY1 FFFFh Second word of the 64-bit KEY register

77F3h KEY0 FFFFh Low word of the 64-bit KEY register

Program Memory PWL in program memory − Reserved for

Address passwords only

0040h PWL3 0000, FFFFh or High word of the 64-bit password

user defined

0041h PWL2 0000, FFFFh or Third word of the 64-bit password

user defined

0042h PWL1 0000, FFFFh or Second word of the 64-bit password

user defined

0043h PWL0 0000, FFFFh or Low word of the 64-bit password

user defined

E-6
 Environments that Require Security Unlocking

E.3 Environments that Require Security Unlocking

Following are the typical situations under which unsecuring may be required:

Code development using debuggers (such as Code Composer)

This is the most common environment during the design phase of a

product.

Flash programming using TI’s flash utilities

Flash programming is common during code development and testing.

Once the user supplies the necessary password, the flash utilities disable
the security logic before attempting to program the flash. The flash utilities
can disable the code security logic in new devices without any
authorization, since new devices come with an erased flash. However,
reprogramming devices (that already contain custom passwords) require
passwords to be supplied to the flash utilities in order to enable
programming.

Custom environment defined by the application

In addition to the above, access to flash/ROM memory contents may be

required in situations such as:

 Using the on-chip bootloader to program the flash

 Executing code from external memory (LF2407A device only) and

requiring access to flash for code libraries, etc.

The unsecuring sequence is identical in all the above situations. This

sequence is referred to as the password match flow (PMF) for simplicity. The
following flowcharts explain the sequence of operation that is required every
time the user attempts to unsecure a device. Code examples are also listed
for clarity.

E.3.1 Password Match Flow

Password match flow (PMF) is essentially a sequence of four dummy reads

from password locations (PWL) followed by four writes to KEY registers.

Figure E−1 explains how PMF helps to initialize the security logic registers and
disable security logic. See the flowchart boxes for the actual instructions that
accomplish the PMF.

Flash/ROM Code Security For LF/LC240xA DSP Devices E-7

Environments that Require Security Unlocking

Figure E−1. Password Match Flow (PMF)

Start

Flash/ROM Device
secure,
after reset or runtime

KEY = Undefined

Do dummy Read
Example code for dummy read
of PWL, 0040−0043h
LDP #0
BLPD #40h, 60h ; update high word
BLPD #41h, 60h ; third word
BLPD #42h, 60h ; second word
BLPD #43h, 60h ; low word

Is PWL = Yes
240xA instructions all 0’s or F’s?
Example to update KEY register
Assume xpwd has password

LDP #0EFh ; page EFh No

SPLK #hpwd, 77F0h ; high word
SPLK #tpwd, 77F1h ; third word
SPLK #spwd, 77F2h : second word
SPLK #lpwd, 77F3h ; low word Write the Password
to KEY registers

Yes
Correct Password
Device unsecure!
? CPU
can access
No on chip Flash/ROM !

E-8
 Unsecuring Considerations for Devices With/Without Code Security

E.4 Unsecuring Considerations for Devices With/Without Code Security

Case 1 and Case 2 provide unsecuring considerations for devices with and
without code security.

E.4.1 Case 1: Device With Code Security

A device with code security should have a predetermined password stored in
the PWL (locations 0040h through 0043h in program memory). The following
are steps to unsecure this device:

1) Perform a dummy read of the PWL.

2) Write the password into the KEY registers (locations 77F0h through
77F3h in data memory).

3) If the password is correct, the device becomes unsecure; otherwise, it

stays secure.

E.4.2 Case 2: Device Without Code Security

A device without code security should have 0000 0000 0000 0000h or FFFF
FFFF FFFF FFFFh stored in the PWL. The following are steps to use this
device:

1) Perform a dummy read of the PWL.

2) The device can be used soon after this operation is completed.

Note: A dummy read operation must be performed prior to using the device, even though the
device is not protected with a password.

Flash/ROM Code Security For LF/LC240xA DSP Devices E-9

DOs and DON’Ts to Protect Security Logic

E.5 DOs and DON’Ts to Protect Security Logic

E.5.1 DOs

To keep the debug and code development phase simple, use the device
in the unsecure mode; i.e., use 0000 0000 0000 0000h or FFFF FFFF
FFFF FFFFh as PWL words (or use a password that is easy to remember).
Use passwords after the development phase when the code is frozen.

Recheck the passwords in PWL before programming the COFF file using
flash utilities.

While migrating code from 240x or 24x devices to the 240xA devices,
recheck the PWL contents before committing the code to flash memory.
Note that program memory locations 0040h through 0043h in 240x/24x
devices are not reserved for passwords and these locations can contain
user code. If 0040h−0043h contain code, it would inadvertently secure the
240xA device.

Refer to Table E−1, Security Mode Table, on page E-2 and its conditions
before designing the reset circuit for the LC/LF240xA devices.

E.5.2 DON’Ts
There are some situations when the code security feature could be
compromised. However, awareness of these situations during the design
phase could eliminate any possibility of code security being violated. Some
design configurations to be avoided are:

An application code should not transfer control to any code that could be
loaded through a peripheral (such as SCI or CAN). For example, suppose
that a customer develops their own version of the bootloader to be able
to bootload from CAN. Typically, this program would initialize the CAN
module, transfer a piece of code through the CAN bus onto on-chip RAM
and then transfer control to the loaded code. A hacker could potentially
transfer a piece of code that could read the flash/ROM contents and then
output the same through any on-chip peripheral or the external memory
interface, if present. This is not a concern with the boot-ROM embedded
in the LF240xA device since the device is secured the moment the on-chip
boot-loader is invoked.

E-10
 DOs and DON’Ts to Protect Security Logic

LF2407A is the only device that has external memory interface (XMIF).
This device can execute code in microprocessor mode using external
memory. If the device powers up in microprocessor mode (MP/MC pin =1),
the on-chip flash memory will be disabled and the flash access will remain
secure. If on-chip flash access is desired, it can be done only if the
password is known. The CPU has to initiate a PMF and flash access will
be granted, if the password is valid. However, if the device powers up in
micro-controller mode (MP/MC pin =0) and branches to an external
memory address, the flash memory cannot be protected. A hacker could
potentially have code in the external memory that could read the
flash/ROM contents.

Similarly, code running in flash should not transfer control to on-chip boot
ROM. A hacker could potentially transfer a piece of code that could read
the flash contents.

Flash/ROM Code Security For LF/LC240xA DSP Devices E-11

CSM Features − Summary

E.6 CSM Features − Summary

1) The flash is unsecured after a reset, if the following conditions are met:
 The JTAG connector is not connected.
 The device is powered up in microcomputer mode (MP/MC pin is low).
 The on-chip boot ROM is not invoked.
Violating any one of the three conditions mentioned above would immedi-
ately secure the device.

2) The standard way of running code out of the flash is to program the flash
with the code and powering up the DSP in microcomputer mode. Since the
flash is unsecured after reset (provided none of the security conditions are
violated), the code will function correctly.

3) Connecting a JTAG emulator at any time will immediately put the flash into
secure mode. In addition, running the ROM bootloader at reset, or having
the MP/MC pin high at reset also puts the flash into secure mode. This
functionality keeps hackers from accessing the flash by using the emula-
tor, by trying to bootload code into the device that copies the flash contents
to the outside world, or by booting up directly into external memory and
running code that tries to copy the flash contents to the outside world.

E-12
 CSM — Frequently Asked Questions

E.7 CSM — Frequently Asked Questions

What is CSM?

CSM is a security feature incorporated in TMS320Lx240xA DSP controllers.

It prevents access/visibility to on-chip Flash/ROM memory (in program space)
to unauthorized persons—i.e., it prevents duplication/reverse engineering of
proprietary code.

What do the terms “secure” and “unsecure” mean?

“Secure” means access to on-chip flash/ROM memory is protected.

“Unsecure” means access to on-chip flash/ROM memory is not
protected—i.e., the contents of the flash/ROM could be read by any means
(through a debugging tool such as Code Composer, for example).

Under what conditions is the device unsecure?

A device is unsecure when the device comes up in the intended application

mode in which code is executed from on-chip flash/ROM, without JTAG
connector connected—i.e., the device is brought up in “microcontroller”
mode upon reset (with the on-chip ROM bootloader disabled). Note that this
is the typical usage of the DSP in an end-product.

Under what conditions is the device secure?

1) When the on-chip ROM bootloader is invoked.

2) When the JTAG connector is connected.

3) When the DSP is powered up in MP mode.

4) When the KEY register values and the PWL values are different.

Can you explain the terms PWL and KEY registers?

PWL stands for “Password locations”. These are memory locations at

addresses 40h to 43h in on-chip flash/ROM which store the passwords. PWL
is mapped in program memory space.

The KEY registers are memory locations at addresses 77F0h to 77F3h in

on-chip data memory space. Writing the password to the KEY register is part
of the procedure to unlock the device.

Flash/ROM Code Security For LF/LC240xA DSP Devices E-13

CSM — Frequently Asked Questions

How do I secure a device?

You secure a device by ensuring the presence of passwords (other than
FFFFFFFFFFFFFFFFh or 0000000000000000h) in the PWL.

ROM: Place password into ROM code at location 40h−43h. This password will
be fabricated into the ROM with the ROM code.

Flash: Program addresses 40h−43h with a password other than all zeros or
all ones.

How do I unsecure a device?

You unsecure a device by executing the following steps:

1) Do a “dummy” read of PWL. The word “dummy” implies that the destina-
tion address of this read is insignificant. Only the read of the PWL is impor-
tant.

2) Write the passwords to the KEY. The value of these passwords should al-
ready be known by the user and should match the value stored in the PWL.

Should I program all 64 bits of the password?

For maximum protection, it is advisable to program all 64 bits.

I don’t want to use the CSM. Can I “bypass” it?

There is no way to “bypass” the CSM in TMS320Lx240xA DSP controllers. If
code security is not a concern, you can program the “dummy” passwords
(FFFFFFFFFFFFFFFFh or 0000000000000000h) in the PWL.

I have programmed the PWL with “dummy” passwords. Do I still need to perform
dummy reads of the PWL when I am doing JTAG emulation/debug?”
A dummy read of the PWL is still essential to gain visibility to on-chip
flash/ROM. A write to the KEY is not required. In situations where a debugger
is used, a read of the PWL by the debugger (in the disassembly window) is
sufficient. For example, right-click in the disassembly window, select Start
Address, and enter 0x0040 in the box. This will unsecure the on-chip
ROM/FLASH.

Are there any precautions I should observe while developing code?

During the code-development phase, it is a good idea to use the dummy
passwords (or stick to a single password).

E-14
 CSM — Frequently Asked Questions

Should I incorporate routines to “unsecure” the device in my application code?

There is no need to incorporate routines to “unsecure” the device in your

application code. Recall that the device comes up as “unsecure” when you
power it up in “microcontroller” mode (without JTAG connector connected/with
the on-chip ROM bootloader disabled). Unsecuring is necessary only when
you need visibility to ROM/Flash on a currently secured device.

Is CSM applicable to any other memory space?

No, it is applicable only to on-chip Flash/ROM memory.

Should the device be unsecure to run application code?

Yes. The device must be unsecure in order to be able to execute code out of
on-chip Flash/ROM memory.

I don’t need code security. Can I store code in PWL also?

This is not advisable. Keeping tab of the password may be difficult, especially
if code changes are possible. It is a good practice to define a password section
in the project to isolate the PWL from the rest of the code. This forces the user
code to begin at 44h and precludes the possibility of code starting from 40h.
This practice is especially advantageous when migrating code from LF240x,
where code starts at 40h.

How does the presence of CSM affect flash programming of LF240xA devices? Or,
I successfully programmed the flash once, but I am unable to do it again. What could
be wrong?

The device must be first unsecured before Clear/Erase/Program (CEP) can

be performed. Update the key.asm program with the correct passwords.
Assemble and link the program using key.bat. Then run unlock.bat to unsecure
the device. You should now be able to clear/erase/program.

After I invoked Code Composer, I couldn’t see my code (programmed in flash) in the
disassembly window. I see some “garbage” code instead. What could be wrong?

The device is still in secure mode. In order to be able to view your code in the
disassembly window, the device must first be unsecured.

Flash/ROM Code Security For LF/LC240xA DSP Devices E-15

CSM — Frequently Asked Questions

Can you provide me a simple code to unsecure the device?

The following code can be executed from B0 or SARAM:
.text

LDP #00E0h ; (E0=224)(E0*80=7000)

SPLK #006Fh, 7029h ; Disable Watchdog

LDP #0h ; Dummy read of the PWL

BLPD #0040h,60h ; update high word
BLPD #0041h,60h ; third word
BLPD #0042h,60h ; second word
BLPD #0043h,60h ; low word

LDP #0EFh ; Writing the password

SPLK #00123h, 77F0h ; to the KEY registers.
SPLK #04567h, 77F1h ; Replace the words shown
SPLK #089ABh, 77F2h ; with the appropriate
SPLK #0CDEFh, 77F3h ; passwords.

LOOP B LOOP

I forgot the password I programmed in PWL. Will I be able to reprogram the flash?
No. Not unless you know which COFF file you used to program the flash. It is
for this reason you should always store a known value in the PWL during the
code development phase.

Are there any restrictions on debug capabilities when secure mode is used?
No. Once the device is unsecured, the CSM has no impact on debug
capabilities.

Are all of the ‘Real-Time’ capabilities still available?

Yes. CSM does not impact the ‘Real-Time’ capabilities.

Does the addition of Secure Mode require any modifications to the Application Code
itself?
The only requirement is the presence of passwords in the PWL.

E-16
 CSM — Frequently Asked Questions

Are there any ’bad practices’ which should be avoided (which compromise security)?

Please refer to section E.5, DOs and DON’Ts to Protect Security Logic, of this
reference guide.

In mass production, can the Flash be programmed, and made secure, in ONE, fast,
operation?

There is no special operation needed “to secure” a device, other than ensuring
the presence of passwords in the PWL.

Do the BLPD and TBLR instructions still work when in secure mode ? If so, what pre-
vents a ’Trojan Horse’ program...attached to the external bus, from copying from Pro-
gram to Data space, then allowing data space to be copied to the UART ...or being vis-
ible via JTAG?

No, BLPD and TBLR do not work when the device is in secure mode. Using
the external bus implies Microprocessor mode. The device is secured in MP
mode. The device will also be secured immediately when the JTAG connector
is connected.

Flash/ROM Code Security For LF/LC240xA DSP Devices E-17

E-18
 Appendix
AppendixFA

5  

A
A0−A15: Collectively, the external address bus; the 16 pins are used in par-
allel to address external data memory, program memory, or I/O space.
ACC: See accumulator.
ACCH: Accumulator high word. The upper 16 bits of the accumulator. See
also accumulator.
ACCL: Accumulator low word. The lower 16 bits of the accumulator. See
also accumulator.
accumulator: A 32-bit register that stores the results of operations in the
central arithmetic logic unit (CALU) and provides an input for subsequent
CALU operations. The accumulator also performs shift and rotate opera-
tions.
address: The location of program code or data stored in memory.
addressing mode: A method by which an instruction interprets its operands
to acquire the data it needs. See also direct addressing; immediate
addressing; indirect addressing.
analog-to-digital (A/D) converter: A circuit that translates an analog signal
to a digital signal.
AR: See auxiliary register.
AR0−AR7: Auxiliary registers 0 through 7. See auxiliary register.
ARAU: See auxiliary register arithmetic unit (ARAU).
ARB: See auxiliary register pointer buffer (ARB).
ARP: See auxiliary register pointer (ARP).
auxiliary register: One of eight 16-bit registers (AR7−AR0) used as point-
ers to addresses in data space. The registers are operated on by the aux-
iliary register arithmetic unit (ARAU) and are selected by the auxiliary
register pointer (ARP).

F-1
Glossary

auxiliary register arithmetic unit (ARAU): A 16-bit arithmetic unit used to

increment, decrement, or compare the contents of the auxiliary registers.
Its primary function is manipulating auxiliary register values for indirect
addressing.

auxiliary register pointer (ARP): A 3-bit field in status register ST0 that
points to the current auxiliary register.

auxiliary register pointer buffer (ARB): A 3-bit field in status register ST1
that holds the previous value of the auxiliary register pointer (ARP).

B
B0: An on-chip block of dual-access RAM that can be configured as either
data memory or program memory, depending on the value of the CNF
bit in status register ST1.

B1: An on-chip block of dual-access RAM available for data memory.

B2: An on-chip block of dual-access RAM available for data memory.

BIO pin: A general-purpose input pin that can be tested by the conditional
branch instruction (BCND) that causes a branch when BIO is driven low
externally.

bit-reversed indexed addressing: A method of indirect addressing that

allows efficient I/O operations by resequencing the data points in a
radix-2 fast Fourier transform (FFT) program. The direction of carry
propagation in the ARAU is reversed.

bootloader: A built-in segment of code that transfers code from an external

source to a 16-bit external program destination at reset.

branch: A switching of program control to a nonsequential program-

memory address.

BRR: The value in the baud select registers (SPI).

F-2
 Glossary

C
C bit: See carry bit.
CALU: See central arithmetic logic unit (CALU).
carry bit: Bit 9 of status register ST1; used by the CALU for extended
arithmetic operations and accumulator shifts and rotates. The carry bit
can be tested by conditional instructions.
central arithmetic logic unit (CALU): The 32-bit wide main arithmetic logic
unit for the 24x CPU that performs arithmetic and logic operations. It
accepts 32-bit values for operations, and its 32-bit output is held in the
accumulator.

CLKIN: Input clock signal. A clock source signal supplied to the on-chip
clock generator at the CLKIN/X2 pin or generated internally by the
on-chip oscillator. The clock generator divides or multiplies CLKIN to
produce the CPU clock signal, CLKOUT.
CLKOUT: Master clock output signal. The output signal of the on-chip clock
generator. The CLKOUT high pulse signifies the CPU’s logic phase
(when internal values are changed), and the CLKOUT low pulse signifies
the CPU’s latch phase (when the values are held constant).
CNF bit: DARAM configuration bit. Bit 12 in status register ST1. CNF is used
to determine whether the on-chip RAM block B0 is mapped to program
space or data space.

codec: A device that codes in one direction of transmission and decodes in

another direction of transmission.
COFF: Common object file format. A system of files configured according to
a standard developed by AT&T. These files are relocatable in memory
space.

context saving/restoring: Saving the system status when the device

enters a subroutine (such as an interrupt service routine) and restoring
the system status when exiting the subroutine. On the 24x, only the pro-
gram counter value is saved and restored automatically; other context
saving and restoring must be performed by the subroutine.
CPU: Central processing unit. The 24x CPU is the portion of the processor
involved in arithmetic, shifting, and Boolean logic operations, as well as
the generation of data- and program-memory addresses. The CPU
includes the central arithmetic logic unit (CALU), the multiplier, and the
auxiliary register arithmetic unit (ARAU).

Glossary F-3
Glossary

CPU cycle: The time required for the CPU to go through one logic phase
(during which internal values are changed) and one latch phase (during
which the values are held constant).
current AR: See current auxiliary register.
current auxiliary register: The auxiliary register pointed to by the auxiliary
register pointer (ARP). The auxiliary registers are AR0 (ARP = 0)
through AR7 (ARP = 7). See also auxiliary register; next auxiliary
register.
current data page: The data page indicated by the content of the data page
pointer (DP). See also data page; DP.

D
D0−D15: Collectively, the external data bus; the 16 pins are used in parallel
to transfer data between the 24x and external data memory, program
memory, or I/O space.
DARAM: Dual-access RAM. RAM that can be accessed twice in a single
CPU clock cycle. For example, your code can read from and write to
DARAM in the same clock cycle.
DARAM configuration bit (CNF): See CNF bit.
data-address generation logic: Logic circuitry that generates the address-
es for data memory reads and writes. This circuitry, which includes the
auxiliary registers and the ARAU, can generate one address per
machine cycle. See also program-address generation logic.
data page: One block of 128 words in data memory. Data memory contains
512 data pages. Data page 0 is the first page of data memory (addresses
0000h−007Fh); data page 511 is the last page (addresses
FF80h−FFFFh). See also data page pointer (DP); direct addressing.
data page 0: Addresses 0000h−007Fh in data memory; contains the
memory-mapped registers, a reserved test/emulation area for special
information transfers, and the scratch-pad RAM block (B2).
data page pointer (DP): A 9-bit field in status register ST0 that specifies
which of the 512 data pages is currently selected for direct address
generation. When an instruction uses direct addressing to access a data-
memory value, the DP provides the nine MSBs of the data-memory
address, and the instruction provides the seven LSBs.
data-read address bus (DRAB): A 16-bit internal bus that carries the
address for each read from data memory.

F-4
 Glossary

data read bus (DRDB): A 16-bit internal bus that carries data from data
memory to the CALU and the ARAU.

data-write address bus (DWAB): A 16-bit internal bus that carries the
address for each write to data memory.

data write bus (DWEB): A 16-bit internal bus that carries data to both
program memory and data memory.

decode phase: The phase of the pipeline in which the instruction is

decoded. See also pipeline; instruction-fetch phase; operand-fetch
phase; instruction-execute phase.

direct addressing: One of the methods used by an instruction to address

data-memory. In direct addressing, the data-page pointer (DP) holds the
nine MSBs of the address (the current data page), and the instruction
word provides the seven LSBs of the address (the offset). See also
indirect addressing.

DP: See data page pointer (DP).

DRAB: See data-read address bus (DRAB).

DRDB: See data read bus (DRDB).

DS: Data memory select pin. The 24x asserts DS to indicate an access to
external data memory (local or global).

DSWS: Data-space wait-state bit(s). A value in the wait-state generator

control register (WSGR) that determines the number of wait states
applied to reads from and writes to off-chip data space.

dual-access RAM: See DARAM.

dummy cycle: A CPU cycle in which the CPU intentionally reloads the
program counter with the same address.

DWAB: See data-write address bus (DWAB).

DWEB: See data write bus (DWEB).

E
execute phase: The fourth phase of the pipeline; the phase in which the
instruction is executed. See also pipeline; instruction-fetch phase;
instruction-decode phase; operand-fetch phase.

external interrupt: A hardware interrupt triggered by an external event

sending an input through an interrupt pin.

Glossary F-5
Glossary

F
FIFO buffer: First-in, first-out buffer. A portion of memory in which data is
stored and then retrieved in the same order in which it was stored. The
synchronous serial port has two four-word-deep FIFO buffers: one for its
transmit operation and one for its receive operation.

flash memory: Electrically erasable and programmable, nonvolatile (read-

only) memory.

G
general-purpose input/output pins: Pins that can be used to accept input
signals or send output signals. These pins are the input pin BIO, the out-
put pin XF, and the GPIO pins.

H
hardware interrupt: An interrupt triggered through physical connections
with on-chip peripherals or external devices.

I
IFR: See interrupt flag register (IFR).

immediate addressing: One of the methods for obtaining data values used
by an instruction; the data value is a constant embedded directly into the
instruction word; data memory is not accessed.

immediate operand/immediate value: A constant given as an operand in

an instruction that is using immediate addressing.

IMR: See interrupt mask register (IMR).

indirect addressing: One of the methods for obtaining data values used by
an instruction. When an instruction uses indirect addressing, data
memory is addressed by the current auxiliary register. See also direct
addressing.

input clock signal: See CLKIN.

input shifter: A 16- to 32-bit left barrel shifter that shifts incoming 16-bit data
from 0 to 16 positions left relative to the 32-bit output.

F-6
 Glossary

instruction-decode phase: The second phase of the pipeline; the phase in

which the instruction is decoded. See also pipeline; instruction-fetch
phase; operand-fetch phase; instruction-execute phase.

instruction-execute phase: The fourth phase of the pipeline; the phase in

which the instruction is executed. See also pipeline; instruction-fetch
phase; instruction-decode phase; operand-fetch phase.

instruction-fetch phase: The first phase of the pipeline; the phase in which
the instruction is fetched from program-memory. See also pipeline;
instruction-decode phase; operand-fetch phase; instruction-execute
phase.

instruction register (IR): A 16-bit register that contains the instruction

being executed.

instruction word: A 16-bit value representing all or half of an instruction. An

instruction that is fully represented by 16 bits uses one instruction word.
An instruction that must be represented by 32 bits uses two instruction
words (the second word is a constant).

internal interrupt: A hardware interrupt caused by an on-chip peripheral.

interrupt: A signal sent to the CPU that (when not masked or disabled)
forces the CPU into a subroutine called an interrupt service routine (ISR).
This signal can be triggered by an external device, an on-chip peripheral,
or an instruction (INTR, NMI, or TRAP).

interrupt flag register (IFR): A 16-bit memory-mapped register that indi-

cates pending interrupts. Read the IFR to identify pending interrupts and
write to the IFR to clear selected interrupts. Writing a 1 to any IFR flag
bit clears that bit to 0.

interrupt latency: The delay between the time an interrupt request is made
and the time it is serviced.

interrupt mask register (IMR): A 16-bit memory-mapped register used to

mask external and internal interrupts. Writing a 1 to any IMR bit position
enables the corresponding interrupt (when INTM = 0).

interrupt mode bit (INTM): Bit 9 in status register ST0; either enables all
maskable interrupts that are not masked by the IMR or disables all mask-
able interrupts.

interrupt service routine (ISR): A module of code that is executed in

response to a hardware or software interrupt.

interrupt trap: See interrupt service routine (ISR).

Glossary F-7
Glossary

interrupt vector: A branch instruction that leads the CPU to an interrupt

service routine (ISR).

interrupt vector location: An address in program memory where an inter-

rupt vector resides. When an interrupt is acknowledged, the CPU
branches to the interrupt vector location and fetches the interrupt vector.

INTM bit: See interrupt mode bit (INTM).

I/O-mapped register: One of the on-chip registers mapped to addresses in

I/O (input/output) space. These registers, which include the registers for
the on-chip peripherals, must be accessed with the IN and OUT instruc-
tions. See also memory-mapped register.

IR: See instruction register (IR).

IS: I/O space select pin. The 24x asserts IS to indicate an access to external
I/O space.

ISR: See interrupt service routine (ISR).

ISWS: I/O-space wait-state bit(s). A value in the wait-state generator control

register (WSGR) that determines the number of wait states applied to
reads from and writes to off-chip I/O space.

L
latch phase: The phase of a CPU cycle during which internal values are held
constant. See also logic phase; CLKOUT1.

logic phase: The phase of a CPU cycle during which internal values are
changed. See also latch phase; CLKOUT1.

long-immediate value: A 16-bit constant given as an operand of an

instruction that is using immediate addressing.

LSB: Least significant bit. The lowest order bit in a word. When used in plural
form (LSBs), refers to a specified number of low-order bits, beginning
with the lowest order bit and counting to the left. For example, the four
LSBs of a 16-bit value are bits 0 through 3. See also MSB.

M
machine cycle: See CPU cycle.

maskable interrupt: A hardware interrupt that can be enabled or disabled

through software. See also nonmaskable interrupt.

F-8
 Glossary

master clock output signal: See CLKOUT1.

master phase: See logic phase.

memory-mapped register: One of the on-chip registers mapped to

addresses in data memory. See also I/O-mapped register.

microcontroller mode: A mode in which the on-chip ROM or flash memory

in program memory space is enabled. This mode is selected with the MP/
MC pin.

microprocessor mode: A mode in which the on-chip ROM or flash memory

is disabled and external program memory is enabled. This mode is se-
lected with the MP/MC pin.

microstack (MSTACK): A register used for temporary storage of the

program counter (PC) value when an instruction needs to use the PC to
address a second operand.

MIPS: Million instructions per second.

MP/MC pin: A pin that indicates whether the processor is operating in micro-
processor mode or microcontroller mode. MP/MC high selects micropro-
cessor mode; MP/MC low selects microcontroller mode. This pin is used
to execute the on-chip bootloader/user code at reset. When MP/MC is
held low during reset, program control transfers to on-chip non-volatile
memory at location 0000h. When MP/MC is held high, control transfers
to 0000h in external program memory.

MSB: Most significant bit. The highest order bit in a word. When used in
plural form (MSBs), refers to a specified number of high-order bits, begin-
ning with the highest order bit and counting to the right. For example, the
eight MSBs of a 16-bit value are bits 15 through 8. See also LSB.

MSTACK: See microstack.

multiplier: A part of the CPU that performs 16-bit × 16-bit multiplication and
generates a 32-bit product. The multiplier operates using either signed
or unsigned 2s-complement arithmetic.

N
next AR: See next auxiliary register.

next auxiliary register: The register that is pointed to by the auxiliary regis-
ter pointer (ARP) when an instruction that modifies ARP is finished
executing. See also auxiliary register; current auxiliary register.

Glossary F-9
Glossary

nonmaskable interrupt: An interrupt that can be neither masked by the

interrupt mask register (IMR) nor disabled by the INTM bit of status
register ST0.
NPAR: Next program address register. Part of the program-address genera-
tion logic. This register provides the address of the next instruction to the
program counter (PC), the program address register (PAR), the micro
stack (MSTACK), or the stack.

O
operand: A value to be used or manipulated by an instruction; specified in
the instruction.
operand-fetch phase: The third phase of the pipeline; the phase in which
an operand or operands are fetched from memory. See also pipeline;
instruction-fetch phase; instruction-decode phase; instruction-execute
phase.
output shifter: 32- to 16-bit barrel left shifter. Shifts the 32-bit accumulator
output from 0 to 7 bits left for quantization management, and outputs
either the 16-bit high or low half of the shifted 32-bit data to the data write
bus (DWEB).
OV bit: Overflow flag bit. Bit 12 of status register ST0; indicates whether the
result of an arithmetic operation has exceeded the capacity of the
accumulator.
overflow (in a register): A condition in which the result of an arithmetic
operation exceeds the capacity of the register used to hold that result.
overflow mode: The mode in which an overflow in the accumulator causes
the accumulator to be loaded with a preset value. If the overflow is in the
positive direction, the accumulator is loaded with its most positive
number. If the overflow is in the negative direction, the accumulator is
filled with its most negative number.
OVM bit: Overflow mode bit. Bit 11 of status register ST0; enables or
disables overflow mode. See also overflow mode.

P
PAB: See program address bus (PAB).
PAR: Program address register. A register that holds the address currently
being driven on the program address bus for as many cycles as it takes
to complete all memory operations scheduled for the current machine
cycle.

F-10
 Glossary

PC: See program counter (PC).

PCB: Printed circuit board.
pending interrupt: A maskable interrupt that has been successfully
requested but is awaiting acknowledgement by the CPU.
pipeline: A method of executing instructions in an assembly line fashion.
The 24x pipeline has four independent phases. During a given CPU
cycle, four different instructions can be active, each at a different stage
of completion. See also instruction-fetch phase; instruction-decode
phase; operand-fetch phase; instruction-execute phase.
PLL: Phase lock loop circuit.
PM bits: See product shift mode bits (PM).
power-down mode: The mode in which the processor enters a dormant
state and dissipates considerably less power than during normal opera-
tion. This mode is initiated by the execution of an IDLE instruction. During
a power-down mode, all internal contents are maintained so that opera-
tion continues unaltered when the power-down mode is terminated. The
contents of all on-chip RAM also remains unchanged.
PRDB: See program read bus (PRDB).
PREG: See product register (PREG).
product register (PREG): A 32-bit register that holds the results of a multi-
ply operation.
product shifter: A 32-bit shifter that performs a 0-, 1-, or 4-bit left shift, or
a 6-bit right shift of the multiplier product based on the value of the
product shift mode bits (PM).
product shift mode: One of four modes (no-shift, shift-left-by-one, shift-left-
by-four, or shift-right-by-six) used by the product shifter.
product shift mode bits (PM): Bits 0 and 1 of status register ST1; they iden-
tify which of four shift modes (no-shift, left-shift-by-one, left-shift-by-four,
or right-shift-by-six) will be used by the product shifter.
program address bus (PAB): A 16-bit internal bus that provides the
addresses for program-memory reads and writes.
program-address generation logic: Logic circuitry that generates the
addresses for program memory reads and writes, and an operand
address in instructions that require two registers to address operands.
This circuitry can generate one address per machine cycle. See also
data-address generation logic.

Glossary F-11
Glossary

program control logic: Logic circuitry that decodes instructions, manages

the pipeline, stores status of operations, and decodes conditional
operations.
program counter (PC): A register that indicates the location of the next
instruction to be executed.
program read bus (PRDB): A 16-bit internal bus that carries instruction
code and immediate operands, as well as table information, from
program memory to the CPU.
PS: Program select pin. The 24x asserts PS to indicate an access to external
program memory.
PSLWS: Lower program-space wait-state bits. A value in the wait-state
generator control register (WSGR) that determines the number of wait
states applied to reads from and writes to off-chip lower program space
(addresses 0000h−7FFFh). See also PSUWS.
PSUWS: Upper program-space wait-state bits. A value in the wait-state
generator control register (WSGR) that determines the number of wait
states applied to reads from and writes to off-chip upper program space
(addresses 8000h−FFFFh). See also PSLWS.

R
RD: Read select pin. The 24x asserts RD to request a read from external pro-
gram, data, or I/O space. RD can be connected directly to the output en-
able pin of an external device.
READY: External device ready pin. Used to create wait states externally.
When this pin is driven low, the 24x waits one CPU cycle and then tests
READY again. After READY is driven low, the 24x does not continue pro-
cessing until READY is driven high.
repeat counter (RPTC): A 16-bit register that counts the number of times
a single instruction is repeated. RPTC is loaded by an RPT instruction.
reset: A way to bring the processor to a known state by setting the registers
and control bits to predetermined values and signaling execution to start
at address 0000h.
reset pin (RS): A pin that causes a reset.
reset vector: The interrupt vector for reset.
return address: The address of the instruction to be executed when the
CPU returns from a subroutine or interrupt service routine.

F-12
 Glossary

RPTC: See repeat counter (RPTC).

RS: Reset pin. When driven low, causes a reset on any 24x device.

R/W: Read/write pin. Indicates the direction of transfer between the 24x and
external program, data, or I/O space.

S
scratch-pad RAM: Another name for DARAM block B2 in data space
(32 words).

short-immediate value: An 8-, 9-, or 13-bit constant given as an operand

of an instruction that is using immediate addressing.

sign bit: The MSB of a value when it is seen by the CPU to indicate the sign
(negative or positive) of the value.

sign extend: Fill the unused high order bits of a register with copies of the
sign bit in that register.

sign-extension mode (SXM) bit: Bit 10 of status register ST1; enables or

disables sign extension in the input shifter. It also differentiates between
logic and arithmetic shifts of the accumulator.

slave phase: See latch phase.

software interrupt: An interrupt caused by the execution of an INTR, NMI,

or TRAP instruction.

software stack: A program control feature that allows you to extend the
hardware stack into data memory with the PSHD and POPD instructions.
The stack can be directly stored and recovered from data memory, one
word at time. This feature is useful for deep subroutine nesting or protec-
tion against stack overflow.

ST0 and ST1: See status registers ST0 and ST1.

stack: A block of memory reserved for storing return addresses for subrou-
tines and interrupt service routines. The 24x stack is 16 bits wide and
eight levels deep.

status registers ST0 and ST1: Two 16-bit registers that contain bits for
determining processor modes, addressing pointer values, and indicating
various processor conditions and arithmetic logic results. These regis-
ters can be stored into and loaded from data memory, allowing the status
of the machine to be saved and restored for subroutines.

Glossary F-13
Glossary

STRB: External access active strobe. The 24x asserts STRB during ac-
cesses to external program, data, or I/O space.
SXM bit: See sign-extension mode bit (SXM).

T
TC bit: Test/control flag bit. Bit 11 of status register ST1; stores the results
of test operations done in the central arithmetic logic unit (CALU) or the
auxiliary register arithmetic unit (ARAU). The TC bit can be tested by
conditional instructions.
temporary register (TREG): A 16-bit register that holds one of the oper-
ands for a multiply operation; the dynamic shift count for the LACT,
ADDT, and SUBT instructions; or the dynamic bit position for the BITT
instruction.
TOS: Top of stack. Top level of the 8-level last-in, first-out hardware stack.
TREG: See temporary register (TREG).
TTL: Transistor-transistor logic.

V
vector: See interrupt vector.
vector location: See interrupt vector location.

W
wait state: A CLKOUT cycle during which the CPU waits when reading from
or writing to slower external memory.
wait-state generator: An on-chip peripheral that generates a limited
number of wait states for a given off-chip memory space (program, data,
or I/O). Wait states are set in the wait-state generator control register
(WSGR).
WE: Write enable pin. The 24x asserts WE to request a write to external pro-
gram, data, or I/O space.
WSGR: Wait-state generator control register. This register, which is mapped
to I/O memory, controls the wait-state generator.

X
XF bit: XF-pin status bit. Bit 4 of status register ST1 that is used to read or
change the logic level on the XF pin.

F-14
 Glossary

XF pin: External flag pin. A general-purpose output pin whose status can be
read or changed by way of the XF bit in status register ST1.

XINT1−XINT2: External pins used to generate general-purpose hardware

interrupts.

Z
zero fill: A way to fill the unused low or high order bits in a register by insert-
ing 0s.

Glossary F-15
F-16
 Index



conversion clock cycles 7-38

A ACQ values when ACQ PS = 1,2, and
3 7-38
A/D converter, starting with a timer event 6-21
calculating the conversion time for a multiple
AAn (abort acknowledge for mailbox n) 10-20 conversion sequence with CPS = 0 and
acceptance filter 10-16 ACQ = 0 7-39
accumulator, definition F-1 calculating the conversion time for a single
conversion sequence with CPS = 1 and
ACK, CAN data frame 10-10
ACQ = 1 7-39
ACQ (acquisition time) 7-38 conversion phases vs CLKOUT cycles 7-38
active/inactive time calculation, compare operation, conversion result buffer registers, (for
GP timer 6-31 dual-sequencer mode) 7-37
ACTRn, compare action control registers (ACTRA features 7-2
and ACTRB) 6-44 input channel select sequencing control registers
ADC (analog-to-digital converter) 7-1 (CHSELSEQn) 7-35
ADC control register 1 (ADCTRL1) 7-20 input trigger description 7-13
ADC control register 2 (ADCTRL2) 7-26 interrupt operation during sequenced
autoconversion sequencer conversions 7-13
basic operation, conversion in dual-sequencer figure 7-16
mode using SEQ1 7-8 maximum conversion channels register
principle of operation 7-4 (MAXCONV) 7-31
sequencer start/stop operation with multiple bit selections for MAX_CONV1 for various
time-sequenced triggers number of conversions 7-33
example of event manager triggers to start the MAX_CONV1 value >7 for dual-sequencer
sequencer 7-11 mode 7-32
example of sequencer start/stop operation 7-10 register bit programming 7-32
with multiple time-sequenced triggers 7-10 overview 7-4
uninterrupted autosequenced mode 7-8 register addresses 7-3
autosequence status register register bit descriptions 7-20
(AUTO_SEQ_SR) 7-33 single and cascaded operating modes,
autosequenced ADC in cascaded mode, block comparison 7-7
diagram 7-5 address-bit multiprocessor communication format,
autosequenced ADC with dual sequencers, block SCI (serial communications interface) 8-14
diagram 7-6
address-bit multiprocessor mode, SCI (serial com-
calibration 7-19
munications interface) 8-13
CALIBRATION register 7-19
sending an address 8-13
clock prescaler 7-17
ADC conversion time 7-17 addressing, bit-reversed indexed F-2
in 240xA ADC 7-18 addressing modes, definition F-1

Index-1
Index

analog-to-digital converter (ADC), 240xA to 240 capture units (EVA) 6-69

family compatibility 12-4 capture units (EVB) 6-70
architectural summary, 240xA devices 2-2 compare unit (EVA, EVB) 6-39
figure 2-2 dead-band unit 6-54
asynchronous communication format, SCI (serial EV general-purpose timer 6-15
communications interface) 8-15 event manager A (EVA) 6-3
event manager B (EVB) 6-4
autoconversion sequencer
output logic for PWM mode 6-56
basic operation, conversion in dual-sequencer
peripheral interrupt expansion (PIE) 2-14
mode using SEQ1 7-8
PWM circuits 6-48
block diagram of autosequenced ADC in
QEP circuit for EVA 6-80
cascaded mode 7-5
QEP circuit for EVB 6-81
block diagram of autosequenced ADC with dual
SCI (serial communication interface) block
sequencers 7-6
diagram 8-4
comparison of single and cascaded operating
watchdog timer (WD) module 11-3
modes 7-7
XMIF signals on LF2407 13-10
input trigger description 7-13
block start signal, SCI (serial communications inter-
interrupt operation during sequenced
face) 8-11
conversions 7-13
sending a block start signal 8-12
figure 7-16
principle of operation 7-4 Boot EN/XF pin operation 13-8
sequencer start/stop operation with multiple boot ROM loader
time-sequenced triggers introduction D-2
example of event manager triggers to start the boot-load sequence D-2
sequencer 7-11 example hardware configuration for LF240xA
example of sequencer start/stop boot ROM operation D-4
memory maps for the LF2407A devices in micro-
operation 7-10
controller modeA D-5
with multiple time-sequenced triggers 7-10
protocol definitions D-6
uninterrupted autosequenced mode 7-8
SCI asynchronous transfer protocol and data
auxiliary register pointer (ARP) F-2 formats D-7
auxiliary register pointer buffer (ARB) F-2 baud rate protocol D-7
clock speeds at which baud rate locks D-8
data transfer D-8
B flow chart for the serial loader baud rate match
algorithm D-9
baud rate calculations, SCI (serial communications flowchart for FETCH SCI WORD D-11
interface) 8-19 flowchart for serial asynchronous loader and the
asynchronous baud register values for common fetch header routine D-10
SCI data transfer completion D-8
SCI bit rates 8-19
SPI synchronous transfer protocol and data
BCR1 (bit configuration register 1) 10-27 formats D-6
BCR2 (bit configuration register 2) 10-26 SPI data packet definition D-7
BCRn (bit configuration registers) 10-25 TMS320F240x/240xA, protocols and
bit timing, CAN (controller area network) 10-29 interfacing D-1
examples 10-29
bit-reversed indexed addressing F-2 C
block diagrams 9-4
autosequenced ADC in cascaded mode 7-5 calibration, ADC (analog-to-digital converter) 7-19
autosequenced ADC with dual sequencers 7-6 CALIBRATION register, ADC (analog-to-digital con-
Boot EN/XF feature 13-8 verter) 7-19
CAN module, TMS320x240xA 10-4 CALU (central arithmetic logic unit), definition F-3

Index-2
 Index

CAN (controller area network) 10-1 message identifiers 10-10

abort acknowledge for mailbox n (AAn) 10-20 message objects 10-9
acceptance filter 10-16 CAN data frame structure, figure 10-9
architecture 10-4 overview of the CAN network 10-3
bit configuration register 1 (BCR1) 10-27 overwrite protection control for mailbox n
bit configuration register 2 (BCR2) 10-26 (OPCn) 10-23
bit configuration registers (BCRn) 10-25 power-down mode 10-40
block diagram 10-4 receive control register (RCR) 10-22
CAN bit timing examples 10-29 receive message lost for mailbox n
CAN bit timing, figure 10-29 (RMLn) 10-22
CAN data frame, figure 10-4 receive message pending for mailbox n
CAN error counter register (CEC) 10-34 (RMPn) 10-23
CAN initialization, diagram 10-39 register addresses, table 10-7
CAN interrupt flag register (CAN_IFR) 10-36 remote frame handling 10-14
CAN interrupt mask register (CAN_IMR) 10-38 remote frame pending register for mailbox n
CAN notation 10-42 (RFPn) 10-22
table 10-42 remote frame requests, figure 10-16
CAN protocol overview 10-3 remote requests
data, remote, error, and overload receiving 10-14
frames 10-3 sending 10-15
configuration mode 10-39 status registers 10-30
control registers 10-19 suspend mode 10-41
error status register (ESR) 10-30 transmission acknowledge for mailbox n
global status register (GSR) 10-32 (TAn) 10-20
interrupt logic 10-35 transmission control register (TCR) 10-20
introduction 10-2 transmission request reset for mailbox n
(TRRn) 10-21
local acceptance mask (LAM) 10-16
transmission request set for mailbox n
local acceptance mask register n (0,1) high word
(TRSn) 10-21
(LAMn_H) 10-17
local acceptance mask register n (0,1) low word CAN bit timing, figure 10-29
(LAMn_L) 10-18 CAN bit timing examples 10-29
mailbox addresses 10-8 CAN configuration mode 10-39
mailbox configuration details, table 10-5 CAN control registers 10-19
mailbox configurations 10-15
CAN initialization, diagram 10-39
mailbox direction/enable register (MDER) 10-19
mailbox layout 10-10 CAN interrupt logic 10-35
mailbox RAM 10-10 CAN notation 10-42
write access 10-12 CAN power-down mode 10-40
mailbox RAM layout 10-44 CAN status registers 10-30
mailboxes
CAN suspend mode 10-41
receive 10-13
transmit 10-13 CAN_IFR (CAN interrupt flag register) 10-36
master control register (MCR) 10-23 CAN_IMR (CAN interrupt mask register) 10-38
memory map 10-6 CAPCONA, capture control register A 6-72
message buffers 10-12 CAPCONB, capture control register B 6-74
message control field (MSGCTRLn) 10-11
CAPFIFOA, capture FIFO status register A 6-75
message identifier for high-word mailboxes 0−5
(MSGIDnH) 10-10 CAPFIFOB, capture FIFO status register B 6-77
message identifier for low-word mailboxes 0−5 CEC (CAN error counter register) 10-34
(MSGIDnL) 10-11 CLKOUT signal, definition F-3

Index-3
Index

clock cycles, conversion, ADC (analog-to-digital features E-2

converter) 7-38 functional description E-2
ACQ values when ACQ PS = 1, 2, and 3 7-38 LF/LC240xA DSP devices E-1
calculating the conversion time for a multiple programming considerations
conversion sequence with CPS = 0 and ACQ devices with code security E-9
= 0 7-39 devices without code security E-9
calculating the conversion time for a single security mode table E-2
conversion sequence with CPS = 1 and ACQ technical definitions E-5
= 1 7-39 codec, definition F-3
conversion phases vs CLKOUT cycles 7-38
COMCONA and COMCONB, compare control regis-
clock domains 4-8
ters 6-41
clock prescaler, ADC (analog-to-digital convert-
communication format, SCI (serial communications
er) 7-17
interface) 8-15
ADC conversion time 7-17
in 240xA ADC 7-18 compare action control register A (ACTRA) 6-44
clocks 4-1 compare action control register B (ACTRB) 6-46
clocks and low-power modes 4-1 compare control register A (COMCONA) 6-42
flash, powering down the flash 4-11
compare control register B (COMCONB) 6-43
low-power modes 4-8
clock domains 4-8 compare operation, GP timer 6-27
exiting low-power modes, examples 4-10 active/inactive time calculation 6-31
low-power modes summary table 4-9 asymmetric waveform generator 6-27
wake-up from low-power modes 4-9 asymmetric/symmetric waveform
external interrupts 4-9 generator 6-27
reset 4-9 compare/PWM output in up-/down-counting
wake-up interrupts 4-9 mode, figure 6-30
phase-locked loop (PLL) 4-2 compare/PWM output in up-counting mode,
operation 4-4 figure 6-28
external oscillator 4-4 output logic 6-30
loop filter components 4-5 PWM transition 6-27
power and ground connections figure 4-5
symmetric waveform generation 6-28
power connections 4-5
reference resonator/crystal 4-4 compare units
resonator/crystal oscillator 4-4 block diagram 6-39
terms applicable to the PLL module 4-3 compare inputs/outputs 6-40
pins 4-2 compare operation modes 6-40
watchdog timer clock 4-7 event manager 6-39
watchdog suspend 4-7 interrupts 6-47
code, migrating code from 24x to 240xA de- operation 6-40
vices 13-3 register setup for compare unit operation 6-41
registers 6-41
code security, Flash/ROM code security
reset 6-47
code security module (CSM) registers,
table E-6 compatibility
DOs and DON’Ts to protect security logic 240xA−240 12-1
DON’Ts E-10 analog-to-digital converters 12-4
DOs E-10 event manager 12-3
environments that require security general 12-2
unlocking E-7 serial communication interface 12-4
password match flow E-7 serial peripheral interface 12-4
flowchart E-8 watchdog timer 12-4

Index-4
 Index

24x−240xA family compatibility 13-1 configuration mode 10-39

24x−240xA DSP overview 13-4 control registers 10-19
features of 24x and 240xA DSPs, table 13-4 error status register (ESR) 10-30
compatible features/peripherals, table 13-2 global status register (GSR) 10-32
digital I/O (GPIO pins) 13-11 interrupt logic 10-35
LF2407A shared pin configuration 13-12 introduction 10-2
shared pin functions for the 240xA 13-11 local acceptance mask (LAM) 10-16
event manager module (EVB) 13-14 local acceptance mask register n (0,1) high word
event manager module and signal names for (LAMn_H) 10-17
EVA and EVB 13-14
local acceptance mask register n (0,1) low word
introduction 13-2
(LAMn_L) 10-18
memory map, LF2407A memory map for
mailbox addresses 10-8
program space 13-5
mailbox configuration details, table 10-5
migrating code form 24x to 240x/240xA
mailbox configurations 10-15
devices 13-3
mailbox direction/enable register (MDER) 10-19
new or modified features/peripherals in 240xA
mailbox layout 10-10
DSPs, table 13-3
mailbox RAM 10-10
system features 13-6
oscillator and PLL 13-6
write access 10-12
frequency input specification 13-6 mailbox RAM layout 10-44
oscillator and PLL pin names 13-6 mailboxes
other low-power management features 13-7 receive 10-13
peripheral clock enable bits 13-7 transmit 10-13
system control registers 13-8 master control register (MCR) 10-23
Boot EN/XF pin operation 13-8 memory map 10-6
fast RD strobe operation 13-9
message buffers 10-12
watchdog clock 13-7
message control field (MSGCTRLn) 10-11
configuration registers, system configuration and message identifier for high-word mailboxes 0−5
interrupts 2-3 (MSGIDnH) 10-10
control-based applications 1-3 message identifier for low-word mailboxes 0−5
controller area network (CAN) 10-1 (MSGIDnL) 10-11
abort acknowledge for mailbox n (AAn) 10-20 message identifiers 10-10
acceptance filter 10-16 message objects 10-9
architecture 10-4 CAN data frame structure, figure 10-9
bit configuration register 1 (BCR1) 10-27 overview of the CAN network 10-3
bit configuration register 2 (BCR2) 10-26 overwrite protection control for mailbox n
bit configuration registers (BCRn) 10-25 (OPCn) 10-23
bit timing, figure 10-29 receive control register (RCR) 10-22
block diagram 10-4 receive message lost for mailbox n
CAN bit timing examples 10-29 (RMLn) 10-22
CAN data frame, figure 10-4 receive message pending for mailbox n
CAN error counter register (CEC) 10-34 (RMPn) 10-23
CAN initialization, diagram 10-39 register addresses, table 10-7
CAN interrupt flag register (CAN_IFR) 10-36 remote frame handling 10-14
CAN interrupt mask register (CAN_IMR) 10-38 remote frame pending register for mailbox n
CAN notation 10-42 (RFPn) 10-22
table 10-42 remote frame requests, figure 10-16
power-down mode 10-40 remote requests
CAN protocol overview 10-3 receiving 10-14
data, remote, error, and overload sending 10-15
frames 10-3 status registers 10-30

Index-5
Index

suspend mode 10-41 DBTCONn, dead-band timer control registers 6-50

transmission acknowledge for mailbox n dead band unit
(TAn) 10-20 block diagram 6-54
transmission control register (TCR) 10-20 dead band generation 6-52
transmission request reset for mailbox n dead-band generation examples 6-53
(TRRn) 10-21 features 6-55
transmission request set for mailbox n inputs and outputs 6-52
(TRSn) 10-21 dead-band timer control register A (DBTCO-
CONV (conversion time) 7-38 NA) 6-50
CONVnn bit values and ADC input channels 7-36 dead-band timer control register B
counting operation, GP timer 6-22 (DBTCONB) 6-51
compare output in continuous up-/down-counting digital input/output (I/O)
mode, table 6-31 differences in GPIO implementation in the
compare output in continuous up-counting mode, 240xA 5-4
table 6-31 digital I/O ports register implementation on 240xA
continuous up-/down-counting mode 6-25 devices
figure 6-26 shared pin configuration 5-2
continuous up-counting mode 6-22 table of I/O port control registers
figure 6-24 implementation 5-3
directional up-/down-counting mode 6-24 digital input/output (I/O) ports module 5-1
figure 6-25 digital I/O ports register implementation on 240xA
stop/hold mode 6-22 devices 5-2
CPU, definition F-3 DINR (device identification number register) 2-8
CRC, CAN data frame 10-10 DLC, CAN data frame 10-9
DMC systems 1-3
dual-access RAM (DARAM) F-4
D
D0−D15 (external data bus), definition F-4 E
data, CAN data frame 10-9 emulation suspend, GP timer in 6-21
data frame, CAN protocol, figure 10-4 EOC (end-of-conversion cycle) 7-38
data frame structure, CAN protocol, figure 10-9 EOF, CAN data frame 10-10
data frames, CAN protocol 10-3 EOS (end-of-sequence flag-setting cycle) 7-38
data memory ESR (error status register) 10-30
configuration 3-11 EVAIFRA (EVA interrupt flag register A) 6-87
data address/data − visibility functional EVAIFRB (EVA interrupt flag register B) 6-89
timing 3-15 EVAIFRC (EVA interrupt flag register C) 6-90
global data memory 3-11 EVAIMRA (EVA interrupt mask register A) 6-91
local data memory 3-8 EVAIMRB (EVA interrupt mask register B) 6-92
pages 3-10
EVAIMRC (EVA interrupt mask register C) 6-93
data page 0 address map 3-10
table 3-11 EVBIFRA (EVB interrupt flag register A) 6-94
data page 0 EVBIFRB (EVB interrupt flag register B) 6-96
address map 3-10 EVBIFRC (EVB interrupt flag register C) 6-97
table 3-11 EVBIMRA (EVB interrupt mask register A) 6-98
RAM block B2 (scratch-pad RAM) 3-11 EVBIMRB (EVB interrupt mask register B) 6-99
data transfer, SPI (serial peripheral interface), EVBIMRC (EVB interrupt mask register C) 6-100
example 9-16 event manager, 240xA to 240 family
five bits per character 9-17 compatibility 12-3

Index-6
 Index

event manager (EV) 6-1 EVB interrupt flag register B

asymmetric PWM waveform generation 6-59 (EVBIFRB) 6-96
capture interrupts 6-79 EVB interrupt flag register C
capture unit FIFO stacks 6-78 (EVBIFRC) 6-97
first capture 6-78 EVA interrupt mask registers
second capture 6-78 EVA interrupt mask register A
third capture 6-79 (EVAIMRA) 6-91
capture unit registers 6-72 EVA interrupt mask register B
capture control register A (CAPCONA) 6-72 (EVAIMRB) 6-92
capture control register B (CAPCONB) 6-74 EVA interrupt mask register C
capture FIFO status register A (EVAIMRC) 6-93
(CAPFIFOA) 6-75 EVB interrupt mask register A
capture FIFO status register B (EVBIMRA) 6-98
(CAPFIFOB) 6-77 EVB interrupt mask register B
capture units 6-68 (EVBIMRB) 6-99
block diagram (EVA) 6-69 EVB interrupt mask register C
block diagram (EVB) 6-70 (EVBIMRC) 6-100
features 6-70 functional blocks 6-2
compare unit interrupts 6-47 general-purpose (GP) timers 6-14
compare unit registers 6-41 double buffering of GP timer compare and
compare action control registers period registers 6-18
(ACTRn) 6-44 GP timer block diagram 6-15
compare control registers (COMCONA and GP timer compare output 6-19
COMCONB) 6-41 GP timer compare registers 6-18
compare unit reset 6-47 GP timer in emulation suspend 6-21
compare units 6-39 GP timer inputs 6-16
compare inputs/outputs 6-40 GP timer interrupts 6-21
compare operation modes 6-40 GP timer outputs 6-17
operation 6-40 GP timer period register 6-18
register setup for compare unit GP timer synchronization 6-20
operation 6-41 individual GP timer control register
comparison to C240 EV 6-5 (TxCON) 6-17
EV interrupts 6-9, 6-84 overall GP timer control register
conditions for interrupt generation 6-86 (GPTCONA/B) 6-17
EV interrupt request and service 6-84 QEP-based clock input 6-20
EVA interrupts, table 6-85 starting the A/D converter with a timer
EVB interrupts, table 6-86 event 6-21
flag registers 6-87 timer clock 6-19
interrupt flag register and corresponding timer counting direction 6-19
interrupt mask register, table 6-84 timer functional blocks 6-14
interrupt generation 6-86 generation of PWM outputs using GP
interrupt vector 6-87 timers 6-38
EVA interrupt flag registers PWM operation 6-38
EVA interrupt flag register A (EVAIFRA) 6-87 generation of PWM outputs with event
EVA interrupt flag register B (EVAIFRB) 6-89 manager 6-58
EVA interrupt flag register C asymmetric and symmetric PWM
(EVAIFRC) 6-90 generation 6-58
EVB interrupt flag register A GP timer compare operation 6-27
(EVBIFRA) 6-94 active/inactive time calculation 6-31

Index-7
Index

asymmetric waveform generation 6-27 quadrature encoder pulse (QEP) circuit 6-80
asymmetric/symmetric waveform decoding 6-81
generator 6-27 decoding example 6-82
compare/PWM output in up-/down-counting QEP circuit 6-81
mode 6-30 QEP circuit block diagram for EVA 6-80
compare/PWM output in up-counting QEP circuit block diagram for EVB 6-81
mode 6-28 QEP circuit time base 6-80
compare/PWM transition 6-27 QEP counting 6-82
output logic 6-30 operation with GP timer interrupt and associated
symmetric waveform generation 6-28 compare outputs 6-82
GP timer counting operation 6-22 QEP pins 6-80
compare output in continuous register setup for the QEP circuit 6-82
up-/down-counting mode, table 6-31 register addresses 6-11
compare output in continuous up-counting register setup for PWM generation 6-58
mode, table 6-31 registers 6-9
continuous-up counting mode 6-22 space vector PWM 6-62
figure 6-24 3-phase power inverter 6-62
continuous-up/down-counting mode 6-25 basic space vectors and switching pat-
figure 6-26 terns 6-64
directional-up/down-counting mode 6-24 schematic diagram 6-62
figure 6-25 table of switching patterns 6-63
stop/hold mode 6-22 approximating motor voltage with
GP timer reset 6-38 basic space vectors 6-64
operation of capture units 6-71 power inverter switching patterns
capture unit setup 6-72 and basic space vectors 6-62
capture unit time base selection 6-71 space vector PWM boundary conditions 6-66
output logic 6-55 space vector PWM waveform generation with
block diagram for PWM mode 6-56 event manager 6-64
pins 6-6 hardware 6-65
power drive protection interrupt 6-8 software 6-65
programmable dead-band unit 6-50 space vector PWM waveforms 6-66
dead-band generation 6-52 unused compare register 6-66
dead-band generation examples 6-53 symmetric PWM waveform generation 6-60
timer control registers (TxCON and
dead-band timer control registers
GPTCONA/B) 6-32
(DBTCONn) 6-50
individual GP timer control register
dead-band unit block diagram 6-54
(TxCON) 6-32
features of dead-band units 6-55
overall GP timer control register A
inputs and outputs of dead-band unit 6-52
(GPTCONA) 6-35
PWM asymmetric waveform generation with
overall GP timer control register B
compare units and PWM circuits, figure 6-59
(GPTCONB) 6-36
PWM circuits associated with compare
units 6-48 event manager A (EVA)
PWM generation capability of EV 6-49 block diagram 6-3
PWM symmetric waveform generation with pins 6-7
compare units and PWM circuits, figure 6-60 register addresses
PWM symmetric waveforms, figure 6-67 EVA capture registers 6-12
PWM waveform generation with compare units EVA compare control registers 6-11
and PWM circuits 6-57 EVA interrupt registers 6-13
dead band 6-57 EVA timer registers 6-11
PWM signal generation 6-57 EVB capture registers 6-12

Index-8
 Index

EVB compare control registers 6-12 programming considerations

EVB timer registers 6-11 devices with code security E-9
event manager B (EVB) devices without code security E-9
block diagram 6-4 security mode table E-2
pins 6-8 technical definitions E-5
register addresses, EVB interrupt registers 6-13 frames, CAN protocol
examples of 240xA program code C-1 to C-40 acceptance filter 10-16
local acceptance mask (LAM) 10-16
executable files, procedure for generating C-2
CAN data frame structure, figure 10-9
external interrupt control registers 2-39 CAN data frame, figure 10-4
external memory interface (XMIF) data, remote, error, and overload 10-3
I/O space 3-16 frame contents 10-9
program and data space 3-16 handling of remote frames 10-14
wait-state generator 3-17 remote frame requests, figure 10-16
2407A wait-state generator control
register (WSGR) 3-18
setting the number of wait states with
G
the 2407A WSGR bits 3-19 general purpose (GP) timers 6-14
with the 2407A wait-state generator 3-17 counting operation 6-22
with the READY signal 3-17 compare output in continuous
XMIF qualifier signal description 3-13 up-/down-counting mode, table 6-31
data address data − visibility compare output in continuous
functional timing 3-15 up-counting mode, table 6-31
program address data − visibility continuous up-/down-counting mode 6-25
functional timing 3-14 figure 6-26
XMIF signal descriptions 3-13 continuous up-counting mode 6-22
figure 6-24
directional up-/down-counting mode 6-24
F figure 6-25
stop/hold mode 6-22
GP timer compare and period registers,
factory masked on-chip ROM 3-3
double buffering 6-18
flash 3-3 GP timer compare output 6-19
embedded flash EEPROM 3-4 GP timer compare registers 6-18
flash control register access 3-4 GP timer period register 6-18
powering down the flash 4-11 GP timer synchronization 6-20
Flash/ROM, code security for LF/LC240xA DSP in emulation suspend 6-21
devices E-1 individual GP timer control register
Flash/ROM , code security for LF/LC240xA DSP (TxCON) 6-17
devices interrupts 6-21
code security module (CSM) registers, overall GP timer control register
table E-6 (GPTCONA/B) 6-17
DOs and DON’Ts to protect security logic QEP-based clock input 6-20
DON’Ts E-10 reset 6-38
DOs E-10 starting the A/D converter with a timing
environments that require security event 6-21
unlocking E-7 timer clock 6-19
password match flow E-7 timer counting direction 6-19
flowchart E-8 timer functional blocks 6-14
features E-2 timer inputs 6-16
functional description E-2 timer outputs 6-17

Index-9
Index

generating executable files, figure C-2 initialization, SPI (serial peripheral interface)
generating wait states with the 2407A wait-state initialization upon reset 9-15
generator 3-17 using the SPI SW RESET bit 9-16
global data memory 3-11 input/output (I/O)
glossary F-1 differences in GPIO implementation in the
GP timer control register A (GPTCONA) 6-35 240xA 5-4
digital I/O ports register implementation on
GP timer control register B (GPTCONB) 6-36
240xA devices
GP timer reset 6-38 shared pin configuration 5-2
GPIO (general-purpose input/output), differences in table of I/O port control registers
GPIO implementation in the 240xA 5-4 implementation 5-3
GSR (global status register) 10-32 I/O mux control register A (MCRA) 5-4
configuration table 5-5
I/O mux control register B (MCRB),
H configuration table 5-6
I/O mux control register C (MCRC) 5-7
hardware, table of hardware features of the 240xA configuration table 5-7
devices 1-7 mux control registers (MCRn) 5-4
highlights, 240xA 1-7 input/output (I/O) ports module 5-1
digital I/O ports register implementation
on 240xA devices 5-2
I instruction register (IR), definition F-7
I/O mux control registers, I/O mux control register B interrupt
(MCRB) 5-5 acknowledge 2-16
I/O space 3-12 definition F-7
address map for 2407A 3-12 hierarchy 2-15
I/O spaces, overview 3-5 latency 2-24
IDE, CAN data frame 10-9 nonmaskable 2-19
operation sequence 2-21
identifier, CAN data frame 10-9
peripheral interrupt acknowledge descriptions
message filtering 10-9
PIACKR0 2-35
message priority 10-9
PIACKR1 2-36
identifiers PIACKR2 2-37
message 10-10 peripheral interrupt request descriptions
message control field (MSGCTRLn) 10-11 PIRQR0 2-31
message identifier for high-word mailboxes 0−5 PIRQR1 2-33
(MSGIDnH) 10-10 PIRQR2 2-34
message identifier for low-word mailboxes 0−5 request structure 2-15
(MSGIDnL) 10-11 requests, figure 2-18
idle-line mode steps, SCI (serial communications vectors 2-17
interface) 8-11 phantom 2-18
idle-line multiprocessor communication format, SCI software hierarchy 2-19
(serial communications interface) 8-11 interrupt flag register (IFR) 2-26 to 2-42
idle-line multiprocessor mode, SCI (serial
communications interface) 8-10 interrupt latency, definition F-7
IFR 2-26 to 2-42 interrupt logic, CAN (controller area
illegal address detect 2-38 network) 10-35
IMR 2-28 to 2-42 interrupt mask register (IMR) 2-28 to 2-42

Index-10
 Index

interrupt priority and vectors baud rate determination 9-12

240xA interrupt source priority and vectors example of maximum baud rate
table 2-9 calculation 9-13
system configuration and interrupts 2-9 example of SPI baud rate calculations
for SPIBRR = 0, 1, or 2 9-13
interrupt service routine (ISR), definition F-7 example of SPI baud rate calculations
for SPIBRR = 3 to 127 9-12
interrupts clocking schemes 9-13
event manager (EV) 6-9, 6-84 selection guide 9-14
conditions for interrupt generation 6-86 SPICLK signal options 9-14
EV interrupt flag registers 6-87 SPICLK−CLKOUT characteristics 9-15
EV interrupt request and service 6-84 data format 9-11
EVA interrupt flag register A (EVAIFRA) 6-87 example transmission of bit from SPIRX-
EVA interrupt flag register B (EVAIFRB) 6-89 BUF 9-12
EVA interrupt flag register C data transfer example 9-16
(EVAIFRC) 6-90 five bits per character 9-17
EVA interrupt mask register A initialization upon reset 9-15
proper SPI initialization using the SPI SW
(EVAIMRA) 6-91
RESET bit 9-16
EVA interrupt mask register A
SPI interrupt control bits 9-10
(EVAIMRC) 6-93 OVERRUN INT ENA bit (SPICTL.4) 9-11
EVA interrupt mask register B RECEIVER OVERRUN FLAG bit
(EVAIMRB) 6-92 (SPISTS.7) 9-11
EVA interrupts, table 6-85 SPI INT ENA bit (SPICTL.0) 9-10
EVB interrupt flag register A SPI INT FLAG bit (SPISTS.6) 9-10
(EVBIFRA) 6-94 SPI PRIORITY bit (SPIPRI.6) 9-11
EVB interrupt flag register B wake-up from low-power modes
(EVBIFRB) 6-96 external interrupts 4-9
EVB interrupt flag register C wake-up interrupts 4-9
(EVBIFRC) 6-97 introduction
EVB interrupt mask register A TMS320 family overview 1-2
(EVBIMRA) 6-98 TMS320Lx240xA series of devices 1-1
EVB interrupt mask register B IR (instruction register), definition F-7
(EVBIMRB) 6-99 ISR (interrupt service routine), definition F-7
EVB interrupt mask register C
ISR code, sample 2-25
(EVBIMRC) 6-100
EVB interrupts, table 6-86
interrupt flag register and corresponding
interrupt mask register, table 6-84
L
interrupt generation 6-86 LAM (local acceptance mask) 10-16
interrupt vector 6-87 LAMn_H (local acceptance mask register n (0,1)
exiting low-power modes, examples 4-10 high word) 10-17
GP timer 6-21 LAMn_L (local acceptance mask register n (0,1)
IMR register 2-28 low word) 10-18
interrupt mask register 2-28
latch phase of CPU cycle F-8
masking, interrupt mask register (IMR) 2-28 to
2-42 local data memory 3-8
pending, interrupt flag register (IFR) 2-26 to logic phase of CPU cycle F-8
2-42 low-power modes 4-8
power drive protection 6-8 clock domains 4-8
SPI (serial peripheral interface) 9-10 exiting low-power modes, examples 4-10
baud rate and clocking schemes 9-12 summary table 4-9

Index-11
Index

wake-up from low-power modes 4-9 wait-state generation 3-17

setting the number of wait states with
the 2407A WSGR bits 3-19
M with the 2407A wait-state generator 3-17
with the READY signal 3-17
mailbox XMIF qualifier signal description 3-13
CAN (controller area network), RAM layout, data address/data − visibility functional
table 10-44 timing 3-15
CAN mailbox addresses, table 10-8 program address/data − visibility
CAN mailbox configuration details 10-5 functional timing 3-14
CAN mailbox layout 10-10 signal description table 3-13
CAN mailbox RAM 10-10 memory map
mailbox configurations 10-15 CAN (controller area network) 10-6
mailbox RAM layout, table 10-44 CAN module memory space,
TMS320x240xA 10-6
MCR (master control register) 10-23
LF2407A memory map for program space 13-5
MCRA (I/O mux control register A) 5-4 message buffers 10-12
configuration table 5-5
message identifiers 10-10
MCRB, I/O mux control register B 5-5
message objects, CAN (controller area
MCRB (I/O mux control register B), network) 10-9
configuration table 5-6 acceptance filter 10-16
MCRC (I/O mux control register C) 5-7 local acceptance mask (LAM) 10-16
configuration table 5-7 handling of remote frames 10-14
MDER (mailbox direction/enable register) 10-19 mailbox layout 10-10
memory 3-1 message buffers 10-12
factory masked on-chip ROM 3-3 receive mailbox 10-13
flash 3-3 transmit mailbox 10-13
embedded flash EEPROM 3-4 write access to mailbox RAM 10-12
flash control register access 3-4 MSGCTRLn (CAN message control field) 10-11
global data 3-11 MSGIDnH (message identifier for high-word
I/O space 3-12 mailboxes 0−5) 10-10
I/O space address map for 2407A 3-12 MSGIDnL (message identifier for low-word
local data 3-8 to 3-11 mailboxes 0−5) 10-11
2407A peripheral memory map 3-9 multiprocessor communication, SCI (serial
configuration 3-11 communications interface) 8-9
memory pages 3-10 address byte 8-9
data page 0 address map 3-10 controlling the SCI TX and RX Features 8-10
data page 0 address map (table) 3-11 receipt sequence 8-10
on-chip RAM 3-2 recognizing the address byte 8-9
dual-access on-chip RAM (DARAM) 3-2 sleep bit 8-9
single-access on-chip program/data
RAM (SARAM) 3-2
on-chip, advantages 3-5 N
overview of memory and I/O spaces 3-5
program 3-6 to 3-7 new features
program memory configuration 3-6 240xA devices 1-6
program and data spaces 3-16 hardware features of the 240xA devices 1-7
program memory map for LF2407A 3-6 next program address register (NPAR),
segments 3-5 definition F-10
total address range 3-1 nonmaskable interrupt (NMI) 2-19

Index-12
 Index

notation, CAN (controller area network) 10-42 PEDATDIR (port E data and direction control
NPAR (next program address register), register) 5-12
definition F-10 peripheral clock enable bits, 240xA devices 13-7
peripheral interrupt acknowledge descriptions
PIACKR0 2-35
O PIACKR1 2-36, 2-37
PIACKR2 2-37
on-chip RAM 3-2
peripheral interrupt acknowledge register 0
dual-access on-chip RAM (DARAM) 3-2
(PIACKR0) 2-34
single-access on-chip program/data RAM
(SARAM) 3-2 peripheral interrupt acknowledge register 1
(PIACKR1) 2-34
on-chip memory, advantages 3-5
peripheral interrupt acknowledge register 2
OPCn (overwrite protection control for (PIACKR2) 2-34
mailbox n) 10-23
peripheral interrupt expansion (PIE) controller 2-13
oscillator and PLL, 240xA devices 13-6 block diagram 2-14
frequency input specification 13-6 interrupt
pin names 13-6 acknowledge 2-16
output logic hierarchy 2-15
compare match for outputs PWMx 6-55 request structure 2-15
compare operation, GP timer 6-30 peripheral interrupt registers 2-30
overview peripheral interrupt request descriptions
240xA device graphical overview 1-9 PIRQR0 2-31
peripherals 1-5 PIRQR1 2-33
TMS320 family 1-2 PIRQR2 2-34
peripheral interrupt request register 0
P (PIRQR0) 2-31
peripheral interrupt request register 1
PADATDIR, port A data and direction control (PIRQR1) 2-31
register, I/O pin designation table 5-9 peripheral interrupt request register 2
PADATDIR (port A data and direction control (PIRQR2) 2-31
register) 5-8 peripheral interrupt vector register (PIVR) 2-30
PAR (program address register), definition F-10 peripheral memory map, 2407A 3-9
password match flow (PMF), code security E-8 PFDATDIR, port F data and direction control
register, pin designation table 5-14
PBDATDIR, port B data and direction control
register, I/O pin designation table 5-10 PFDATDIR (port F data and direction control
register) 5-13
PBDATDIR (port B data and direction control
register) 5-9 phantom interrupt vector 2-18
PCDATDIR, port C data and direction control phase-locked loop (PLL) 4-2
register, I/O pin designation table 5-11 operation 4-4
external oscillator 4-4
PCDATDIR (port C data and direction control
loop filter components 4-5
register) 5-10
power and ground connections, figure 4-5
PDDATDIR, port D data and direction control power connections 4-5
register, I/O pin designation table 5-12 reference resonator/crystal, figure 4-4
PDDATDIR (port D data and direction control resonator/crystal oscillator 4-4
register) 5-11 terms applicable to the PLL module 4-3
PEDATDIR, port E data and direction control PIACKR0 (peripheral interrupt acknowledge
register , I/O pin designation table 5-13 register 0) 2-34

Index-13
Index

PIACKR1 (peripheral interrupt acknowledge ports register implementation on 240xA

register 1) 2-34 devices 5-2
PIACKR2 (peripheral interrupt acknowledge power-down mode, CAN (controller area
register 2) 2-34 network) 10-40
PIE (peripheral interrupt expansion controller) 2-13 prescaler, clock (ADC) 7-17
block diagram 2-14 ADC conversion time 7-17
interrupt in 240xA ADC 7-18
acknowledge 2-16
hierarchy 2-15 program address register (PAR), definition F-10
request structure 2-15 program and data spaces 3-16
pin configuration, shared pin configuration, digital
program examples C-1
I/O ports register implementation 5-2
240x register definitions, bit codes for bit
pins 4-2 instruction C-5
event manager (EV) 6-6 common files for all example programs C-3
event manager A (EVA) pins 6-7 linker command file to place user code sections
event manager B (EVB) pins 6-8 beginning at 0000h of external program
PIRQR0 (peripheral interrupt request register memory C-4
0) 2-31 overview C-2
PIRQR1 (peripheral interrupt request register program to check GPIO pins of 240xA as
1) 2-31 inputs C-22
program to check the capture units of
PIRQR2 (peripheral interrupt request register 240x C-33
2) 2-31 program to check the GPIO pins of 240xA
PIVR (peripheral interrupt vector register) 2-30 as outputs C-20
PLL pin names, 240xA 13-6 program to check the operation of TIMER1
in EVA C-30
port A data and direction control register
program to echo received characters back
(PADATDIR) 5-8
to the source C-16
I/O pin designation table 5-9
program to initialize the ADC module of
port B data and direction control register 240xA C-18
(PBDATDIR) 5-9 program to output serial data through the SPI
I/O pin designation table 5-10 port C-12
port C data and direction control register program to perform a loopback in the SCI
(PCDATDIR) 5-10 module C-14
I/O pin designation table 5-11
program memory 3-6
port control registers, 240xA digital I/O port control configuration 3-6
registers implementation 5-3 program address/data − functional timing 3-14
port D data and direction control register program memory map for LF2407A 3-6
(PDDATDIR) 5-11 programmable register address summary B-1
I/O pin designation table 5-12 code security module (CSM) registers B-9
port E data and direction control register table B-2
(PEDATDIR) 5-12
protocols and interfacing, boot ROM loader
I/O pin designation table 5-13
introduction D-2
port F data and direction control register boot-load sequence D-2
(PFDATDIR) 5-13 example hardware configuration for
pin designation table 5-14 LF240xA boot ROM operation D-4
port interrupts, SCI (serial communications memory maps for the LF2407A devices in
interface) 8-18 microcontroller mode D-5

Index-14
 Index

protocol definitions D-6 space vector PWM 6-62

SCI asynchronous transfer protocol and 3-phase power inverter 6-62
data formats D-7 approximation of motor voltage with space
baud rate protocol D-7 vectors 6-64
clock speeds at which baud rate locks D-8 basic space vectors and switching
data transfer D-8 patterns 6-64
flowchart for FETCH SCI WORD D-11 power inverter switching patterns and basic
flowchart for the serial loader baud rate space vectors 6-62
match algorithm D-9 schematic diagram 6-62
flowcharts for serial asynchronous loader table of switching patterns 6-63
and the fetch header routine D-10 waveform boundary conditions 6-66
SCI data transfer completion D-8 waveform generation with event
SPI synchronous transfer protocol and manager 6-64
data formats D-6 software 6-65
SPI data packet definition D-7 space vector PWM hardware 6-65
TMS320F240x/240xA D-1 space vector PWM waveforms 6-66
the unused compare register 6-66
PWM circuits
associated with compare units 6-48 symmetric PWM waveform generation with
block diagram 6-48 compare unit and PWM circuits, figure 6-60
symmetric space vector PWM waveforms,
PWM generation capability of event manager 6-49 figure 6-67
PWM operation 6-38 with compare units and PWM circuits 6-57
PWM outputs, generation using the GP asymmetric and symmetric PWM
timers 6-38 generation 6-58
PWM operation 6-38 asymmetric PWM waveform generation 6-59
PWM waveform generation dead band 6-57
asymmetric PWM waveform generation with PWM output generation with event
compare unit and PWM circuits, figure 6-59 manager 6-58
capture interrupts 6-79 PWM signal generation 6-57
capture unit FIFO stacks 6-78 register setup for PWM generation 6-58
first capture 6-78 symmetric PWM waveform generation 6-60
second capture 6-78
third capture 6-79
capture unit registers 6-72
Q
capture units 6-68 QEP circuit 6-80, 6-81
block diagram (EVA) 6-69 block diagram
block diagram (EVB) 6-70 EVA 6-80
features 6-70 EVB 6-81
operation 6-71 QEP counting 6-82
capture unit setup 6-72 QEP decoding example 6-82
time base selection 6-71 QEP pins 6-80
quadrature encoder pulse (QEP) circuit 6-80 register setup 6-82
decoding 6-81 time base 6-80
decoding example 6-82 QEP-based clock input 6-20
QEP circuit 6-81
QEP circuit block diagram for EVA 6-80
QEP circuit block diagram for EVB 6-81 R
QEP counting 6-82
operation with GP timer interrupt and associated r0, r1, CAN data frame 10-9
compare outputs 6-82 RAM
QEP pins 6-80 dual-access on-chip RAM (DARAM) 3-2
register setup for the QEP circuit 6-82 on-chip RAM 3-2

Index-15
Index

single-access on-chip RAM (SARAM) 3-2 capture FIFO status registers

capture FIFO status register A
RCR (receive control register) 10-22
(CAPFIFOA) 6-76
receive mailboxes 10-13 capture FIFO status register B
receiver operation, SCI (serial communications (CAPFIFOB) 6-77
interface) 8-13 code security module (CSM) B-9
compare action control registers (ACTRn) 6-44
receiver signals in communication modes, SCI compare action control register A
(serial communications interface) 8-16 (ACTRA) 6-44
reducing development time 1-4 compare action control register B
(ACTRB) 6-46
register address summary compare control registers (COMCONn) 6-41
code security module (CSM) registers, compare control register A
table B-9 (COMCONA) 6-42
programmable B-1 compare control register B
table B-2 (COMCONB) 6-43
registers dead-band timer control registers
2407A wait-state generator control register (DBTCONn) 6-50
(WSGR) 3-18 dead-band timer control register A
ADC control register 1 (ADCTRL1) 7-20 (DBTCONA) 6-50
ADC control register 2 (ADCTRL2) 7-26 dead-band timer control register B
ADC conversion result buffer registers (DBTCONB) 6-51
(RESULTn) 7-37 device identification number register (DINR) 2-8
ADC input channel select sequencing control emulation data buffer register
register 1 (CHSELSEQ1) 7-35 (SCIRXEMU) 8-31
ADC input channel select sequencing control error status register (ESR) 10-30
register 2 (CHSELSEQ2) 7-35 EVA capture register addresses 6-12
ADC input channel select sequencing control EVA compare control register addresses 6-11
register 3 (CHSELSEQ3) 7-35 EVA interrupt flag register A (EVAIFRA) 6-87
ADC input channel select sequencing control EVA interrupt flag register B (EVAIFRB) 6-89
register 4 (CHSELSEQ4) 7-35 EVA interrupt flag register C (EVAIFRC) 6-90
ADC register addresses 7-3 EVA interrupt mask register A (EVAIMRA) 6-91
ADC register bit descriptions 7-20 EVA interrupt mask register B (EVAIMRB) 6-92
autosequence status register EVA interrupt mask register C (EVAIMRC) 6-93
(AUTO_SEQ_SR) 7-33 EVA Interrupt register addresses 6-13
baud-select LSbyte register (SCILBAUD) 8-26 EVA timer register addresses 6-11
baud-select MSbyte register (SCIHBAUD) 8-26 EVB capture register addresses 6-12
bit configuration register 1 (BCR1) 10-27 EVB compare control register addresses 6-12
bit configuration register 2 (BCR2) 10-26 EVB interrupt flag register A (EVBIFRA) 6-94
CALIBRATION 7-19 EVB interrupt flag register B (EVBIFRB) 6-96
CAN error counter register (CEC) 10-34 EVB interrupt flag register C (EVBIFRC) 6-97
CAN interrupt flag register (CAN_IFR) 10-36 EVB interrupt mask register A (EVBIMRA) 6-98
CAN interrupt mask register (CAN_IMR) 10-38 EVB interrupt mask register B (EVBIMRB) 6-99
CAN module register addresses, table 10-7 EVB interrupt mask register C
capture control register A (CAPCONA) 6-72 (EVBIMRC) 6-100
capture control register B (CAPCONB) 6-74 EVB interrupt register addresses 6-13
capture FIFO status register A EVB timer register addresses 6-11
(CAPFIFOA) 6-75 event manager (EV) 6-9
capture FIFO status register B external interrupt 1 control register
(CAPFIFOB) 6-77 (XINT1CR) 2-39

Index-16
 Index

external interrupt 2 control register peripheral interrupt request register 2

(XINT2CR) 2-40 (PIRQR2) 2-33
global status register (GSR) 10-32 peripheral interrupt vector register (PIVR) 2-30
GP timer control registers, overall (GPTCONn) port A data and direction control register
GP timer control register A (PADATDIR) 5-8
(GPTCONA) 6-35 I/O pin designation table 5-9
GP timer control register B port B data and direction control register
(GPTCONB) 6-36 (PBDATDIR) 5-9
I/O mux control registers (MCRn) 5-4 I/O pin designation table 5-10
I/O mux control register A (MCRA) 5-4 port C data and direction control register
I/O mux control register B (MCRB) 5-5 (PCDATDIR) 5-10
I/O mux control register C (MCRC) 5-7 I/O pin designation table 5-11
individual GP timer control register port D data and direction control register
(TxCON) 6-32 (PDDATDIR) 5-11
interrupt flag register (IFR) 2-26 to 2-42 I/O pin designation table 5-12
interrupt mask register (IMR) 2-28 to 2-42 port E data and direction control register
local acceptance mask register n (0,1) high word (PEDATDIR) 5-12
(LAMn_H) 10-17 I/O pin designation table 5-13
local acceptance mask register n (0,1) low word port F data and direction control register
(LAMn_L) 10-18 (PFDATDIR) 5-13
mailbox direction/enable register (MDER) 10-19 pin designation table 5-14
mapped to data page 0 3-11 programmable register address summary B-1
master control register (MCR) 10-23 receive control register (RCR) 10-22
maximum conversion channels register receiver data buffer register (SCIRXBUF) 8-31
(MAXCONV) 7-31 receiver data buffer registers (SCIRXEMU,
bit selections for MAX_CONV1 for various SCIRXBUF)) 8-30
number of conversions 7-33 receiver status register (SCIRXST) 8-28
MAX_CONV1 value >7 for dual-sequencer bit associations 8-30
mode 7-32 SCI communication control register
register bit programming 7-32 (SCICCR) 8-21
output control register A (MCRA) 5-4 SCI CHAR2−0 bit values and character
overall GP timer control register A lengths 8-22
(GPTCONA) 6-35 SCI control register 1 (SCICTL1) 8-23
overall GP timer control register B SW RESET affected flags 8-24
(GPTCONB) 6-36 SCI control register 2 (SCICTL2) 8-27
peripheral interrupt 2-30 SCI module registers, overview 8-6
peripheral interrupt acknowledge registers SCI priority control register (SCIPRI) 8-32
(PIACKRn) SPI baud rate register (SPIBRR) 9-24
peripheral interrupt acknowledge register 0 SPI configuration control register
(PIACKR0) 2-34 (SPICCR) 9-19
peripheral interrupt acknowledge register 1 SPI emulation buffer register (SPIRXEMU) 9-25
(PIACKR1) 2-35 SPI module addresses 9-6
peripheral interrupt acknowledge register 2 SPI operation control register (SPICTL) 9-21
(PIACKR2) 2-36 SPI priority control register (SPIPRI) 9-29
peripheral interrupt request registers (PIRQRn) SPI serial data register (SPIDAT) 9-28
peripheral interrupt request register 0 SPI serial receive buffer register
(PIRQR0) 2-31 (SPIRXBUF) 9-26
peripheral interrupt request register 1 SPI serial transmit buffer register
(PIRQR1) 2-32 (SPITXBUF) 9-27

Index-17
Index

SPI status register (SPISTS) 9-22 C240 SCI vs. LF/LC240xA SCI 8-2
summary of programmable registers on communication format 8-15
the 240xA B-2 receiver signals in communication
system control and status register 1 modes 8-16
(SCSR1) 2-3 RX signals in communication modes,
low-power modes 2-3 figure 8-16
system control and status register 2 transmitter signals in communication
(SCSR2) 2-5 modes 8-17
timer x control register (TxCON), TX signals in communication modes,
x = 1,2,3, or 4 6-33 figure 8-17
transmission control register (TCR) 10-20 multiprocessor and asynchronous
transmit data buffer register (SCITXBUF) 8-31
communication modes 8-7
WD counter register (WDCNTR) 11-8
multiprocessor communication 8-9
WD reset key register (WDKEY) 11-9
address byte 8-9
WD timer control register (WDCR) 11-9
block start signal 8-11
XINT1 control register (XINT1CR) 2-39
sending a block start signal 8-12
XINT2 control register (XINT2CR) 2-40
controlling the SCI TX and RX features 8-10
remote frames 10-14
idle-line mode steps 8-11
remote requests idle-line multiprocessor communication
receiving 10-14 format 8-11
sending 10-15 idle-line multiprocessor mode 8-10
reset 2-38 receipt sequence 8-10
wake-up from low-power modes 4-9 receiver operation 8-13
RFPn (remote frame pending register for recognizing the address byte 8-9
mailbox n) 10-22 sleep bit 8-9
RMLn (receive message lost for mailbox n) 10-22 wake-up temporary (WUT), double-buffered
RMPn (receive message pending for WUT and TXSHF 8-12
mailbox n) 10-23 wake-up temporary (WUT) flag 8-12
ROM, factory masked on-chip ROM 3-3 physical description 8-2
port interrupts 8-18
RTR, CAN data frame 10-9
programmable data format 8-8
RX signals in communication modes, SCI
data frame formats, typical 8-8
(serial communications interface)
programming using SCICCR 8-8
figure 8-17
SCI block diagram 8-4
SCI RX signals in communication modes,
SCI module registers 8-20
figure 8-16
address table 8-20
baud-select LSbyte register
S (SCILBAUD) 8-26
baud-select MSbyte register
sample ISR code 2-25 (SCIHBAUD) 8-26
SCI (serial communications interface) 8-1 emulation data buffer register
address-bit multiprocessor mode 8-13 (SCIRXEMU) 8-31
communication format 8-14 overview 8-6
sending an address 8-13 receiver data buffer register
architecture 8-5 (SCIRXBUF) 8-31
asynchronous communication format 8-15 receiver data buffer registers (SCIRXEMU,
baud rate calculations 8-19 SCIRXBUF) 8-30
asynchronous baud register values for receiver status register (SCIRXST) 8-28
common SCI bit rates 8-19 bit associations 8-30

Index-18
 Index

SCI communication control register serial communication interface (SCI), 240xA to 240
(SCICCR) 8-21 family compatibility 12-4
SCI control register 1 (SCICTL1) 8-23
serial communications interface (SCI) 8-1
SCI control register 2 (SCICTL2) 8-27
architecture 8-5
SCI priority control register (SCIPRI) 8-32
asynchronous communication format 8-15
transmit data buffer register
(SCITXBUF) 8-31 baud rate calculations 8-19
SCI physical description asynchronous baud register values for
error detection flags 8-2 common SCI bit rates 8-19
half- or full-duplex operation 8-3 C240 SCI vs. LF/LC240xA SCI 8-2
I/O pins 8-2 communication format 8-15
non-return-to-zero format 8-3 receiver signals in communication
programmable bit rates 8-2 mode 8-16
programmable data word length 8-2 RX signals in communication mode,
programmable number of stop bits 8-2 figure 8-16
receive and transmit functions 8-3 transmitter signals in communication
separate enable bits for TX and RX mode 8-17
interupts 8-3 TX signals in communication mode,
separate error interrupts for multiple error figure 8-17
conditions 8-3 multiprocessor and asynchronous
serial clock, internally generated 8-2 communication modes 8-7
transmitter and receiver operation 8-3 multiprocessor communication 8-9
wake-up multiprocessor modes 8-3 address byte 8-9
address−bit multiprocessor mode 8-13
SCSR1 (system control and status register 1) 2-3
communication format 8-14
low-power modes 2-3
sending an address 8-13
SCSR2 (system control and status register 2) 2-5 block start signal 8-11
sending a block start signal 8-12
sequencer, autoconversion 7-4
controlling the SCI TX and RX features 8-10
basic operation, conversion in
idle-line mode steps 8-11
dual-sequencer mode using SEQ1 7-8
idle-line multiprocessor communication
block diagram of autosequenced ADC in
format 8-11
cascaded mode 7-5
idle-line multiprocessor mode 8-10
block diagram of autosequenced ADC with
receipt sequence 8-10
dual sequencers 7-6
comparison of single and cascaded receiver operation 8-13
operating modes 7-7 recognizing the address byte 8-9
input trigger description 7-13 sleep bit 8-9
interrupt operation during sequenced wake-up temporary (WUT), double-buffered
conversion 7-13 WUT and TXSHF 8-12
figure 7-16 wake-up temporary (WUT) flag 8-12
Sequencer start/stop operation with multiple physical description 8-2
time-sequenced triggers port interrupts 8-18
example of event manager triggers to start the programmable data format 8-8
sequencer 7-11 data frame formats, typical 8-8
example of sequencer start/stop programming using SCICCR 8-8
operation 7-10 SCI block diagram 8-4
sequencer start/stop operation with multiple SCI module registers 8-20
time-sequenced triggers, with multiple address table 8-20
time-sequenced triggers 7-10 baud-select LSbyte register
uninterrupted autosequenced mode 7-8 (SCILBAUD) 8-26

Index-19
Index

baud-select MSbyte register data format 9-11

(SCIHBAUD) 8-26 example transmission of bit from SPIRX-
emulation data buffer register BUF 9-12
(SCIRXEMU) 8-31 data transfer example 9-16
overview 8-6 five bits per character 9-17
receiver data buffer register initialization upon reset 9-15
(SCIRXBUF) 8-31 proper SPI initialization using the SPI SW RE-
receiver data buffer registers (SCIRXEMU, SET bit 9-16
SCIRXBUF) 8-30 SPI interrupt control bits 9-10
OVERRUN INT ENA bit (SPICTL.4) 9-11
receiver status register (SCIRXST) 8-28
RECEIVER OVERRUN FLAG bit
bit associations 8-30
(SPISTS.7) 9-11
SCI communication control register
SPI INT ENA bit (SPICTL.0) 9-10
(SCICCR) 8-21 SPI INT FLAG bit (SPISTS.6) 9-10
SCI control register 1 (SCICTL1) 8-23 SPI PRIORITY bit (SPIPRI.6) 9-11
SCI control register 2 (SCICTL2) 8-27 operation 9-7
SCI priority control register (SCIPRI) 8-32 introduction 9-7
transmit data buffer register master mode 9-8
(SCITXBUF) 8-31 master/slave connection, figure 9-8
SCI physical description slave mode 9-9
error detection flags 8-2 physical description 9-2
half- or full-duplex operation 8-3 I/O pins 9-2
I/O pins 8-2 master and slave mode operations 9-2
non-return-to-zero format 8-3 memory-mapped status and control
programmable bit rates 8-2 registers 9-3
programmable data word length 8-2 SPI serial data register (SPIDAT) 9-2
programmable number of stop bits 8-2 SPI serial receive buffer register
receive and transmit functions 8-3 (SPIRXBUF) 9-2
separate enable bits for TX and RX SPI serial transmit buffer register
interrupts 8-3
(SPITXBUF) 9-2
separate error interrupts for multiple error
SPICLK phase and polarity control 9-2
conditions 8-3
static and control logic 9-3
serial clock, internally generated 8-2
SPI module registers
transmitter and receiver operation 8-3
overview 9-5
wake-up multiprocessor modes 8-3
register addresses 9-6
serial peripheral interface (SPI) 9-1 SPI baud rate register (SPIBRR) 9-24
240xA to 240 family compatibility 12-4 SPI configuration control register
block diagram 9-4 (SPICCR) 9-19
C240 SPI vs. LF/LC240xA SPI 9-2 character length control bit values 9-20
interrupts 9-10 SPI emulation buffer register
baud rate and clocking schemes 9-12 (SPIRXEMU) 9-25
baud rate determination 9-12 SPI example waveforms 9-30
example of baud rate calculations for CLOCK POLARITY = 0, CLOCK
SPIBRR = 0, 1, or2 9-13 PHASE = 0 9-30
example of baud rate calculations for CLOCK POLARITY = 0, CLOCK
SPIBRR = 3 to 127 9-12 PHASE = 1 9-31
example of maximum baud rate CLOCK POLARITY = 1, CLOCK
calculation 9-13 PHASE = 0 9-32
clocking schemes 9-13 CLOCK POLARITY = 1, CLOCK
selection guide 9-14 PHASE = 1 9-33
SPICLK signal options 9-14 SPISTE behavior in master mode 9-34
SPICLK-CLKOUT characteristics 9-15 SPISTE behavior in slave mode 9-35

Index-20
 Index

SPI operation control register (SPICTL) 9-21 SPI serial data register (SPIDAT) 9-2
SPI priority control register (SPIPRI) 9-29 SPI serial receive buffer register
SPI serial data register (SPIDAT) 9-28 (SPIRXBUF) 9-2
SPI serial receive buffer register SPI serial transmit buffer register
(SPIRXBUF) 9-26 (SPITXBUF) 9-2
SPI serial transmit buffer register SPICLK phase and polarity control 9-2
(SPITXBUF) 9-27 static and control logic 9-3
SPI status register (SPISTS) 9-22 SPI module registers
overview 9-5
SOF, CAN data frame 10-9
register addresses 9-6
SOS synch, start-of-sequence sync-up 7-38 SPI baud rate register (SPIBRR) 9-24
SPI configuration control register
SPI (serial peripheral interface) 9-1
(SPICCR) 9-19
block diagram 9-4
character length control bit values 9-20
C240 SPI vs. LF/LC240xA SPI 9-2
SPI emulation buffer register
interrupts 9-10
(SPIRXEMU) 9-25
baud rate and clocking schemes 9-12
SPI example waveforms 9-30
baud rate determination 9-12 CLOCK POLARITY = 0, CLOCK
example of baud rate calculations for PHASE = 0 9-30
SPIBRR = 0, 1, or2 9-13 CLOCK POLARITY = 0, CLOCK
example of baud rate calculations for PHASE = 1 9-31
SPIBRR = 3 to 127 9-12 CLOCK POLARITY = 1, CLOCK
example of maximum baud rate PHASE = 0 9-32
calculation 9-13 CLOCK POLARITY = 1, CLOCK
clocking schemes 9-13 PHASE = 1 9-33
selection guide 9-14 SPISTE behavior in master mode 9-34
SPICLK signal options 9-14 SPISTE behavior in slave mode 9-35
SPICLK-CLKOUT characteristics 9-15 SPI operation control register (SPICTL) 9-21
data format 9-11 SPI priority control register (SPIPRI) 9-29
example transmission of bit from SPI serial data register (SPIDAT) 9-28
SPIRXBUF 9-12
SPI serial receive buffer register
data transfer example 9-16
(SPIRXBUF) 9-26
five bits per character 9-17
SPI serial transmit buffer register
initialization upon reset 9-15
proper SPI initialization using the SPI SW
(SPITXBUF) 9-27
RESET bit 9-16 SPI status register (SPISTS) 9-22
SPI interrupt control bits 9-10 SPIO pins, 240xA devices 13-11
OVERRUN INT ENA bit (SPICTL.4) 9-11
RECEIVER OVERRUN FLAG bit SRR, CAN data frame 10-9
(SPISTS.7) 9-11
suspend mode, CAN (controller area
SPI INT ENA bit (SPICTL.0) 9-10
network) 10-41
SPI INT FLAG bit (SPISTS.6) 9-10
SPI PRIORITY bit (SPIPRI.6) 9-11 system configuration and interrupts 2-1
operation 9-7 240xA architectural summary 2-2
introduction 9-7 figure 2-2
master mode 9-8 configuration registers 2-3
master/slave connection, figure 9-8 device identification number
slave mode 9-9 register (DINR) 2-8
physical description 9-2 system control and status
I/O pins 9-2 register 1 (SCSR1) 2-3
master and slave mode operations 9-2 low-power modes 2-3
memory-mapped control and system control and status
status registers 9-3 register 2 (SCSR2) 2-5

Index-21
Index

interrupt priority and vectors 2-9 wake up from low-power modes

240xA interrupt source priority and vectors external interrupts 4-9
table 2-9 reset 4-9
peripheral interrupt expansion (PIE) wake-up interrupts 4-9
controller 2-13 wake-up temporary (WUT), SCI (serial
block diagram 2-14 communications interface),
interrupt double buffered WUT and TXSHF 8-12
acknowledge 2-16
wake-up temporary (WUT) flag, SCI (serial
hierarchy 2-15
NMI (nonmaskable) 2-19 communications interface) 8-12
operation sequence 2-21 watchdog clock, 240xA devices 13-7
request structure 2-15 watchdog suspend 4-7
request, figure 2-18
vectors 2-17
watchdog timer, 240xA to 240 family
vectors, phantom 2-18 compatibility 12-4
vectors, software hierarchy 2-19 watchdog timer (WD) 11-1
system control registers, 240xA devices 13-8 features 11-2
Boot EN/XF pin operation 13-8 block diagram of the WD module 11-3
fast RD strobe operation 13-9 operation overview 11-4
watchdog suspend 11-4
watchdog timer clock (WDCLK) 11-4
T operations 11-4
operations of the WD timer 11-5
TAn (transmission acknowledge for mailbox servicing the WD timer 11-5
n) 10-20 WD check bit logic 11-7
TCR (transmission control register) 10-20 WD prescale select 11-5
WD reset 11-6
timer x control register (TxCON),
WD setup 11-7
x = 1,2,3, or 4 6-33
WDKEY register power-up sequence,
TMS320 family 1-2 to 1-6 typical 11-6
advantages 1-2 watchdog control registers 11-8
development 1-2 table 11-8
history 1-2 WD counter register (WDCNTR) 11-8
overview 1-2 WD overflow (timeout) selections 11-11
transmit mailboxes 10-13 WD reset key register (WDKEY) 11-9
transmitter signals in communication modes, SCI WD timer control register (WDCR) 11-9
(serial communications interface) 8-17 WD timer clock 11-4
TRRn (transmission request reset for watchdog timer clock 4-7
mailbox n) 10-21 waveforms, SPI (serial peripheral interface),
TRSn (transmission request set for examples 9-30
mailbox n) 10-21 CLOCK POLARITY = 0, CLOCK
PHASE = 0 9-30
CLOCK POLARITY = 0, CLOCK
W PHASE = 1 9-31
CLOCK POLARITY = 1, CLOCK
wait state, definition F-14 PHASE = 0 9-32
wait-state generation 3-17 CLOCK POLARITY = 1, CLOCK
setting the number of wait states with the 2407A PHASE = 1 9-33
WSGR bits 3-19 SPISTE behavior in master mode 9-34
with the 2407A wait-state generator 3-17 SPISTE behavior in slave mode 9-35
with the READY signal 3-17 WDCNTR, watchdog counter register 11-8

Index-22
 Index

WDCR, watchdog timer control XINT2CR, XINT2 control register 2-40

register 11-9 XMIF qualifier signal description 3-13
WDKEY, watchdog reset key data address/data − visibility
register 11-9 functional timing 3-15
WSGR (2407A wait-state generator program address/data − visibility
control register) 3-18 functional timing 3-14
signal description table 3-13
X
XINT1CR, XINT1 control register 2-39

Index-23
Index

Index-24