International Journal of Trend in Scientific Research and Development (IJTSRD)

Volume 8 Issue 2, March-April 2024 Available Online: www.ijtsrd.com e-ISSN: 2456 – 6470

Implementation of 8x8 Vedic Multiplier using Verilog

Mr. Parasurama1, Singamsetti Raviteja2, Mohamad Shajahan3
1
Assistant Professor & HOD, 2,3Student,
1,2,3
Department of Electronics and Communication and Engineering, JNTUK University College,
PPDCET, Vijayawada, Andhra Pradesh, India

ABSTRACT How to cite this paper: Mr. Parasurama |

A Multiplier is one of the key hardware blocks in most fast Singamsetti Raviteja | Mohamad
processing system which requires less power dissipation. A Shajahan “Implementation of 8x8 Vedic
conventional multiplier consumes more power. This paper presents a Multiplier using Verilog" Published in
low power 8 bit Vedic. Multiplier (VM) based on Vertically & International Journal
of Trend in
Crosswise method of Vedic mathematics; a general multiplication Scientific Research
formulae equally applicable to all cases of multiplication. It is based and Development
on generating all partial products and their sum in one step. The (ijtsrd), ISSN: 2456-
implementation is done using cadence Virtuoso tool. The power 6470, Volume-8 |
dissipation of 8x8 bit Vedic multiplier obtained after synthesis is Issue-2, April 2024, IJTSRD64769
compared with conventional multipliers such as Wallace tree and pp.808-815, URL:
array multipliers and found that the proposed Vedic multiplier circuit www.ijtsrd.com/papers/ijtsrd64769.pdf
seems to have better performance in terms of power dissipation. The
essential persistence of this project is to advance the swiftness of the Copyright © 2024 by author (s) and
digital circuits like multiplier, meanwhile the multiplier and adder International Journal of Trend in
Scientific Research and Development
stay unique of the crucial hardware modules in an extraordinary Journal. This is an
performance systems like DSP (digital signal processors), Open Access article
microprocessors and FIR filters etc. Vedic multiplier is alone such distributed under the
extraordinary and swift multiplier architecture. This Vedic terms of the Creative Commons
Mathematics is the forename specified to the original system of Attribution License (CC BY 4.0)
mathematics. It has a sole process of calculations founded on 16 (http://creativecommons.org/licenses/by/4.0)
Sutras. The multiplication sutra midst these 16 sutras is the Urdhva
Tiryakbhyam sutra which means upright and diagonal. The projected
system is designed using Verilog and it is fulfilled over Xilinx ISE
14.2.

Keywords: URDHVATIRYAKBHYAM, FPGA, RSIC

I. Introduction:
Increase could be a energetic pointless errand in basic to triumph the anticipated execution in huge
number-crunching methods. Duplication based real-time flag and picture preparing applications. A
operations such as MAC (Duplicate and Amass) and few of the arranged number juggling operations in
internal relic are in the midst of about of the reliably such applications are duplication and the advance of
utilized Computation- Seriously Math Capacities firm multiplier circuit has remained a theme of
(CIAF) once in the past started in a few Advanced concern over decades. Dropping the time delay and
Flag Preparing (DSP) applications such as Quick control utilization stay exceptionally basic
Fourier Change (FFT), convolution, sifting and chip prerequisites implied for voluminous applications.
in its math and rationale unit. Ever since duplication This unite presents diverse multiplier developments.
leads the execution time of furthermost DSP Multiplier established on Vedic Arithmetic is single
calculations, thus in this manner there's a prerequisite of the quick and small control multiplier.
of tall speed multiplier. Once, duplication time is still
A. OBJECTIVE
the winning figure in characterizing the instruction Utilizing the standards of Vedic Arithmetic,
cycle time of a DSP chip. The request for exceptional especially calculations like Urdhva Tiryagbhyam
speed handling has been developing as an result of (Vertically and Crosswise), these multipliers
expanding computer and flag handling applications. guarantee noteworthy improvements in computerized
Progressed yield number-crunching operations are
circuit plan. The key goals of an 4x4 and 8×8 Vedic

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multiplier in VLSI , parallel multiplier and a • Structural Plan: Once the algorithmic decay is
pipelined multipliers to realize the taking after built up, analysts work on planning the design of
properties: the multiplier. This includes choosing on the
structure of the multiplier circuit, counting the
• Tall speed
course of action of adders, shifters, and other
• Moo Control Utilization rationale components. Structural choices such as
• Compact plan array-based plans or tree-based plans are
investigated to optimize execution measurements
• Adaptability such as speed and range.
• Moo inactivity • Equipment Portrayal and Reenactment:
• Tall throughput Utilizing equipment depiction dialects (HDLs) like
Verilog or VHDL, analysts interpret the building
• Precision and Unwavering quality plan into computerized circuit depictions. These
• Compatibility and Integration depictions are at that point reenacted utilizing
computer program apparatuses to confirm the
• Cost-effectiveness
rightness and usefulness of the multiplier.
• Less Delay, Less region and Less control Reenactment permits analysts to evaluate
II. Related work execution characteristics and recognize regions for
Within the domain of algorithmic optimization, enhancement.
analysts explore methods to upgrade the productivity • Union and Optimization: After reenactment, the
and speed of 8x8 Vedic multipliers. This includes HDL portrayals are synthesized into real
refining the Vedic increase calculation to suit equipment executions. Amalgamation instruments
advanced circuitry prerequisites, such as minimizing outline the HDL code to particular equipment
basic way delay and maximizing parallelism. Thinks components and optimize the plan for the target
about may center on fine-tuning the deterioration and innovation, such as field-programmable door
recreation steps of the calculation to realize ideal clusters (FPGAs) or application-specific
execution. coordinates circuits (ASICs). Optimization
Structural plan plays a vital part in realizing proficient methods may incorporate rationale optimization,
8x8 Vedic multipliers. Analysts investigate distinctive timing closure, and range minimization.
structural choices, such as array-based plans, tree- • Physical Usage: Once synthesized, the plan
based plans, and crossover approaches that combine moves to the physical execution stage, where it is
components of both. Each design offers interesting realized as a physical circuit format. Format
trade-offs in terms of speed, region, and control optimization procedures are connected to play
utilization, provoking researchers to investigate plan down wire lengths, decrease parasitic impacts, and
space investigation strategies to distinguish the guarantee appropriate flag keenness. Physical
foremost appropriate engineering for a given execution contemplations are pivotal for
application situation. accomplishing high-performance and dependable
III. IMPLEMENTATION PROCESS operation of the multiplier.
The execution of 8x8 Vedic multipliers includes a • Testing and Approval: At last, the executed 8x8
few preparing steps, from algorithmic deterioration to Vedic multiplier experiences thorough testing and
equipment realization. Here's a diagram of the key approval to guarantee its rightness and usefulness.
handling works included in executing an 8x8 Vedic Test vectors are connected to the multiplier, and its
multiplier: yield is compared against anticipated comes about
• Algorithmic Decay: The primary step in to confirm legitimate operation. Different testing
actualizing an 8x8 Vedic multiplier is to break procedures, counting useful testing, timing
down the increase operation into less difficult investigation, and blame reenactment, are utilized
subproblems based on Vedic science standards. to approve the multiplier's execution beneath
This ordinarily includes breaking down the 8x8 distinctive conditions.
duplication into littler duplications and increases, IV . EXISTING SYSTEM
leveraging procedures such as Nikhilam Sutra A Vedic multiplier could be a sort of computerized
(common increase) or Urdhva-Tiryagbhyam Sutra multiplier based on antiquated Indian science
(vertically and crosswise). standards. The Vedic increase calculation is known
for its effortlessness and productivity in performing

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increase. An 8x8 Vedic multiplier would be planned decreasing zone, tall speed and control are the major
to increase two 8-bit numbers utilizing this ranges in VLSI framework plan. The yield of these
calculation. A few inquire about works have Vedic multipliers is included by adjusting the
investigated the usage of 8x8 Vedic multipliers, rationale levels of swell carry viper.
leveraging the old Vedic science strategies to plan
productive advanced circuits for increase
assignments. These multipliers point to make strides
execution and decrease equipment complexity
compared to routine duplication strategies.
Ordinarily, they utilize standards from old Indian
numerical writings such as the "Vedas" to break down
the increase handle into less difficult steps.
In these implementations, the Vedic duplication
calculation is adjusted to function on twofold
numbers, adjusting with cutting edge advanced
circuitry prerequisites. The center thought behind
Vedic duplication is to break down the multiplicands
into littler parts and perform operations on these parts
in parallel. Different models have been proposed for Fig 2: 8x8 bits vedic multiplier
8x8 Vedic multipliers, each advertising trade-offs
B . Design flow of the 8x8 vedic multiplier
between speed, range, and control utilization. The plan stream of an 8x8 Vedic multiplier includes a
V. PROPOSED METHOD few consecutive steps to decipher the scientific
The conspiring of Vedic Multiplier is established on calculation into a working advanced circuit. Here's a
an inventive ability of advanced duplication which is point by point diagram of the plan stream:
tolerably changed from the standard plot of
Calculation Determination and Investigation:
duplication like move and include. Where minor
Select a reasonable Vedic increase calculation for 8x8
squares are reused to plan the prevalent one. The duplication. Common calculations incorporate
Vedic Multiplier is raised in Verilog HDL, because it
Nikhilam Sutra (common duplication) or Urdhva-
contributes genuine utilization of basic strategy of Tiryagbhyam Sutra (vertically and crosswise).
displaying. The unmistakable piece is realized by
Analyze the algorithm's reasonableness for advanced
means of Verilog equipment depiction dialect. equipment execution, considering components such
as parallelism, asset utilization, and basic way delay.
Engineering Plan: Plan the engineering structure of
the 8x8 Vedic multiplier based on the chosen
calculation. Decide the course of action of essential
computational units such as adders, shifters, and
registers. Investigate engineering optimizations to
make strides execution measurements like speed,
zone, and control utilization.
RTL (Enlist Exchange Level) Plan: Actualize the
engineering plan in RTL employing a equipment
depiction dialect (HDL) such as Verilog or VHDL.
Compose RTL code to depict the usefulness of the
multiplier, counting input/output ports, inner
operations, and control rationale.
Fig 1: Block Diagram of 8X8 Vedic Multiplier Recreation and Confirmation: Utilize HDL
reenactment instruments like Demonstrate Sim or
IMPLEMENTATION OF 8X8 VEDIC VCS to reenact the RTL plan. Create testbenches to
MULTIPLIER: confirm the rightness and usefulness of the multiplier
8x8 Vedic Multiplier 8 bit Vedic multiplier is beneath different input conditions. Investigate any
actualized by utilizing four 4x4multiplier, moreover issues or blunders distinguished amid reenactment to
8bit and 12 bit snake is utilized. The square graph of guarantee the RTL plan carries on as anticipated.
8x8 Vedic multiplier is appeared in figure. Plan of

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Blend and Optimization: Synthesize the RTL plan C. EXECUTION OF 8X8 VEDIC MULTIPLIER
utilizing blend devices like Synopsys Plan Compiler To execute the 8x8 Vedic multiplier in Xilinx ISE
or Xilinx Vivado. 14.7, you'll have to be taken after these common
steps:
Optimize the synthesized plan for the target
innovation (e.g., FPGA or ASIC), considering RTL Plan: Type in the RTL (Enlist Exchange Level)
components such as timing limitations, zone code for the 8x8 Vedic multiplier in Verilog or
utilization, and control utilization. Perform timing VHDL. This code ought to portray the usefulness of
examination to guarantee that the plan meets the the multiplier based on the chosen Vedic duplication
specified execution necessities. calculation and building plan.
Physical Plan: Interpret the synthesized plan into a Make a Unused Venture: Open Xilinx ISE 14.7 and
physical circuit format, counting situation and make a modern venture by selecting "Record" >
directing of rationale components. Utilize "Unused Extend". Take after the prompts to indicate
Floorplanning strategies to optimize the physical the venture title, area, and target gadget (e.g., FPGA
format for variables such as flag astuteness, wire family and particular gadget).
length, and steering clog. Include Source Records: Include the RTL source
Post-Layout Confirmation: Perform post-layout file(s) containing the 8x8 Vedic multiplier plan to the
verification to guarantee that the physical plan meets venture. Right-click on "Venture Pilot" and select
timing, range, and control limitations. Utilize devices "Include Source". Select the suitable source file(s)
like inactive timing examination (STA) and physical from your extend catalog.
confirmation instruments to distinguish and resolve
Imperatives: Characterize any fundamental
any plan run the show infringement or timing issues. imperatives for the plan, such as stick assignments,
Testing and Approval: Send the manufactured chip timing limitations, and clock signals. Make or purport
or modified FPGA onto a test stage. Conduct a imperatives record (.ucf or .xdc) and include it to
comprehensive testing and approval to confirm the the venture.
usefulness and execution of the 8x8 Vedic multiplier Synthesize Plan: Right-click on the top-level module
in real-world conditions. Utilize test vectors and of your plan within the "Progression" see and select
corner cases to evaluate the strength and precision of "Synthesize - XST". This will begin the
the multiplier execution. amalgamation prepare, which changes over the RTL
Documentation and Detailing: Report the plan code into a gate-level netlist.
handle, strategy, and execution points of interest for Actualize Plan: After synthesis completes
future reference. Get ready reports and introductions effectively, right-click on the synthesized module and
summarizing the plan stream, comes about, and select "Actualize Plan - NCD". This step performs the
experiences picked up from the venture. mapping of the synthesized netlist to the target FPGA
Iterative Refinement: Repeat on the plan based on gadget, counting situation and directing.
criticism from testing, reenactment, and examination. Produce Programming Record: Once usage is total,
Fine-tune the calculation, engineering, and execution right-click on the top-level module and select
to advance optimize execution, region, and control "Produce Programming Record - BIT". This creates a
productivity. programming record (.bit) that can be utilized to
arrange the FPGA.
Program FPGA: Interface your FPGA board to the
computer, open Xilinx affect or any other reasonable
programming apparatus, and program the FPGA with
the produced .bit record. Guarantee that the FPGA is
accurately designed and prepared for testing. Test and
Investigate: After programming the FPGA, test the
usefulness of the 8x8 Vedic multiplier utilizing
suitable test vectors and jolts. Investigate any issues
that emerge, utilizing recreation instruments or
equipment investigating highlights.
Documentation and Announcing: Record the plan
Fig 3: 8X8 Vedic Multiplier design flow
prepare, usage subtle elements, test comes about, and

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any perceptions or bits of knowledge picked up amid 8x8 multiplication errands. These varieties may
testing. Plan reports or introductions summarizing the center on minimizing basic way delay, diminishing
extend for documentation purposes. equipment complexity, or upgrading parallelism to
progress in general execution.
Keep in mind to allude to the Xilinx ISE
documentation and client guides for nitty gritty E. DESIGN IMPLEMENTATION
enlightening on utilizing particular highlights and The plan usage comprises of the taking after:
tools within the computer program. Furthermore,
 Interpretation: The Interpret movement
guarantee merely have the vital information of
amalgamates all the input netlists, plan confinements
Verilog or VHDL coding, FPGA design, and
data and yields a Xilinx Local Bland Database record.
advanced plan standards to successfully plan and
actualize the 8x8 Vedic multiplier in Xilinx ISE 14.7.  Mapping: The Outline movement will run after the
Change handle is completed. Mapping maps the
D. ALOGRITHM FOR 8X8 VEDIC
consistent plan assigned in NGD record to
MULTIPLIER
slices/CLBs, show on the objective gadget.
The 8x8 Vedic multiplier can be executed utilizing
different Vedic increase calculations, each with its  Put and Course: The put and course handle will run
possess approach to breaking down and duplicating after the plan has mapped. Standard employments the
two 8-bit numbers. Here are two commonly utilized NCD record shaped by Outline handle to put and
calculations: course the plan on the target FPGA plan.
Nikhilam Sutra (General Multiplication): The  Bit stream Era: The combination of twofold
Nikhilam Sutra could be a common increase information utilized to code reconfigurable rationale
calculation from Vedic science, appropriate for gadget is generally signified as bit stream, whereas
multiplying two numbers of any estimate. Within the usually somewhat equivocal since the information are
setting of an 8x8 Vedic multiplier, the calculation no more bit arranged than that of an instruction set
includes breaking down each 8-bit number into littler processor and there's for the most part no gushing.
segments and performing increase and expansion
operations on these portions.  Utilitarian Recreation: utilitarian recreation may be
finished earlier to mapping. This reenactment
The fundamental steps of the Nikhilam Sutra for an movement licenses the client to confirm that their
8x8 Vedic multiplier include vertically and crosswise plan has been synthesized suitably and any transforms
duplication, taken after by flat expansion to get the due to lower level of recognition can be recognized.
ultimate result.
 Inactive timing investigation: Three assortments of
Urdhva-Tiryagbhyam Sutra (Vertically and inactive timing investigation be fulfilled that are:
Crosswise):
The Urdhva-Tiryagbhyam Sutra, moreover known as  Post-fit Inactive timing examination: Post-Fit
the vertically and crosswise increase algorithm, is Inactive timing prepare opens the timing Analyzer
another Vedic increase procedure. In this calculation, outline, which lets your intuitiveness select timing
the multiplication is carried out by increasing digits trails in your plan for sketching out the timing comes
vertically and corner to corner and after that summing about.
the comes about askew to get the ultimate item.  Post Put and Course Inactive Timing
For an 8x8 Vedic multiplier, the Urdhva- Examination: Post-PAR timing reports incorporate
Tiryagbhyam Sutra includes breaking down each 8- all delays to convey a full timing rundown. In the
bit number into littler sections and performing event that a set and directed plan has experienced all
duplication and expansion operations agreeing to the of your timing restrictions, at that point you'll be able
vertically and crosswise strategy. advance by developing setup information and
downloading a gadget.
Both calculations point to use the standards of Vedic
science to break down the increase handle into less
complex steps, empowering quicker computation and
effective utilize of equipment assets. The choice
between these calculations may depend on variables
such as execution prerequisites, equipment
imperatives, and ease of execution in digital circuits.
Furthermore, varieties and optimizations of these
calculations may exist, custom-made particularly for

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scale operations, its advantage gets to be more clear
as the estimate of the operands increments. In
scenarios including bigger numbers, the multiplier's
capacity to streamline the duplication handle can lead
to striking picks up in computational proficiency. In
addition, its asset utilization, in spite of the fact that
subordinate on execution specifics, regularly
demonstrates great compared to ordinary calculations,
making it an alluring choice for applications requiring
optimized equipment utilization.

Fig 4: Design Flow of FPGA Implementation

Fig 6: Waveform of 8X8 vedic multiplier

VII. CONCLUSION
The comes about of our investigate show that the 8x8
Vedic multiplier offers promising preferences in
terms of speed, region proficiency, and control
utilization compared to customary duplication
strategies. By saddling the parallelism characteristic
in Vedic arithmetic, we were able to attain
noteworthy execution changes whereas keeping up
moo equipment complexity. In addition, the
adaptability of the Vedic multiplier engineering
permits for customization and optimization custom-
made to particular application necessities.
Moreover, our think about highlights the significance
of intrigue collaboration between mathematicians,
computer researchers, and electrical engineers in
Fig 5: Procedure Followed for Implementation progressing computational procedures. By bridging
VI. RESULTS & ANALYSIS antiquated numerical intelligence with present day
The comes about and investigation of the Vedic 8X8 advanced plan techniques, we have unlocked new
multipliers are will be as appeared within the roads for advancement within the field of number
underneath figures. The 4x4 Vedic multiplier is juggling circuits.
utilized to increase four twofold numbers and this Looking ahead, future investigate seem investigate
multiplier deliver a lesser sum of control. This paper extra optimizations, such as algorithmic refinements
presents a tall speed 4x4 bit Vedic Multiplier (VM) and technology-specific upgrades, to assist make
based on Vertically & Crosswise strategy of Vedic strides the execution and effectiveness of Vedic
arithmetic, a common duplication formulae similarly multipliers. Moreover, examinations into real-world
pertinent to all cases of increase. It is based on applications and integration into bigger computerized
producing all halfway items and their entirety in one frameworks would give important experiences into
step. The Vedic multiplier can be utilized in the down to earth utility of Vedic duplication
numerous quick computing processors since of their procedures.
less time delay and a littler number of cut LUTs. The
result examines the delay and number of cut LUTs for In rundown, this consider contributes to the body of
the executed 32-bit multiplier. Analyzing the information on Vedic arithmetic and its pertinence to
execution characteristics of the 8x8 Vedic multiplier advanced circuit plan, advertising experiences into
uncovers subtleties in its viability. Whereas it may elective computational approaches and clearing the
not illustrate critical speed advancements for small-

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