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CSA Project Report - Anum - Shaheer

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30 views7 pages

CSA Project Report - Anum - Shaheer

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shaheerkz12
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DEPARTMENT OF COMPUTER & SOFTWARE

ENGINEERING
COLLEGE OF E&ME, NUST, RAWALPINDI

Course

Computer System & Architecture

Project Report

SUBMITTED TO:
Dr. Yasin

SUBMITTED BY:
Anum Zafar Reg# 410092
Shaheer Mukhtiar Reg# 432017

DEPT: Computer Engineering


CE- 44
Submission date: June 5th , 2024
Project Statement/Problem:
Implementation of RISC-V Pipelined processor
Platforms:
-Xilinx IDE
-Github

Methodology:
Conduct a thorough analysis of project requirements and specifications, defining the ISA
based on RISC-V standards and determining necessary features.

Design the microarchitecture by breaking down the processor into functional units and
defining data paths and control signals.

Implement the microarchitecture using a hardware description language (HDL) like


Verilog and simulate the design to verify functionality.

OBJECTIVES SET:
Short term objectives to Execute:

Difference Between and RISC and MIPS Architecture and ISA:

o RISC architecture emphasizes simplicity and efficiency with a reduced set of


instructions, relying on compiler optimization.

o MIPS architecture adheres to RISC principles but focuses on optimizing


instruction execution through a streamlined pipeline structure and fixed
instruction formats.
o RISC processors typically use a load-store architecture, separating memory
access from arithmetic operations.

o MIPS processors embrace a similar load-store model but introduce a fixed


instruction format for efficient decoding and execution.

o MIPS ISA features a simplified yet powerful instruction set architecture,


characterized by orthogonality and a consistent instruction format.

Targeted Modules to Convert MIPS into RISC:


o Instruction Decoder
o Branch Prediction
o Instruction Format

Advantages of Pipelining over Single Cycle Processor:


o Increased Throughput: Pipelining allows for simultaneous processing of
multiple instructions, enhancing overall throughput compared to single-cycle
designs.
o Improved Resource Utilization: By overlapping instruction execution,
pipelined processors utilize hardware resources more efficiently, leading to
better performance.

o Reduced Cycle Time: Pipelined processors achieve shorter clock cycles by


operating pipeline stages in parallel, resulting in higher clock frequencies.

o Smaller Area Requirement: Pipelined architectures achieve higher


performance without significantly increasing hardware complexity or area.
o Better Scalability: Pipelined designs offer scalability advantages, allowing for
easier extension and optimization to meet evolving requirements and add new
features.

RISC V Circuit Diagram:

What is achieved?
o RISC-V ISA Construction: Successfully constructed the RISC-V Instruction Set
Architecture (ISA) as the foundation of the processor design.

o Pipeline Enhancement: Introduced four pipeline registers to the processor design,


enhancing its efficiency and throughput.

o Pipeline Control Implementation: Developed robust pipeline control mechanisms to


manage the flow of instructions through the pipeline stages effectively.

o Instruction Implementation: Implemented key instruction types including R-Type and


I-Type instructions, ensuring the processor's ability to execute fundamental
operations.
o Branch Instruction Progress: Partially implemented branch instructions, a crucial step
towards enabling conditional execution and control flow within the processor
architecture.
What is left?
o Correct Functionality of Branch Instructions.
o FPGA implementations.
o Adding more instructions to the Design.

Simulation Snap shots:


Conclusion:
In conclusion, our project on the implementation of a RISC-V pipelined processor has made
significant strides in enhancing processing efficiency for computer systems. By constructing
the RISC-V ISA, integrating four pipeline registers, and implementing robust pipeline control
mechanisms, we have laid a solid foundation for efficient instruction execution. Progress in
incorporating key instruction types and partial implementation of branch instructions mark
substantial achievements, although tasks such as ensuring correct branch instruction
functionality and FPGA implementations remain. Our project underscores the importance of
efficient processor architectures and sets the stage for further advancements in computer
system design.

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