ALC5616

ALC5616
Ultra-Low Power Audio CODEC

for Mobile Devices
Datasheet
Rev. 0.1
Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
ALC5616
Datasheet
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Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT

This document is intended for the hardware and software engineer’s general information on the Realtek
ALC5616 Audio Codec IC.
Though every effort has been made to ensure that this document is current and accurate, more
information may have become available subsequent to the production of this guide.
I2S Audio CODEC for Mobile Devices ii Rev. 0.1

ALC5616
Datasheet
REVISION HISTORY
Revision Release Date Summary
0.1 2012/7/29 Preliminary version
I2S Audio CODEC for Mobile Devices iii Rev. 0.1

ALC5616
Datasheet
Table of Contents
1. GENERAL DESCRIPTION .............................................................................................................................................. 1
2. FEATURES ......................................................................................................................................................................... 2
3. SYSTEM APPLICATION ................................................................................................................................................. 2
4. FUNCTION BLOCK AND MIXER PATH ..................................................................................................................... 3

4.1. FUNCTION BLOCK ........................................................................................................................................................ 3
4.2. AUDIO MIXER PATH..................................................................................................................................................... 4
4.3. DIGITAL MIXER PATH .................................................................................................................................................. 5
5. PIN ASSIGNMENTS ......................................................................................................................................................... 6
6. PIN DESCRIPTIONS......................................................................................................................................................... 7
6.1. DIGITAL I/O PINS ......................................................................................................................................................... 7
6.2. ANALOG I/O PINS ........................................................................................................................................................ 7
6.3. FILTER/REFERENCE...................................................................................................................................................... 8
6.4. POWER/GROUND .......................................................................................................................................................... 9
7. FUNCTION DESCRIPTION .......................................................................................................................................... 10
7.1. POWER ....................................................................................................................................................................... 10
7.2. POWER SUPPLY ON/OFF SEQUENCE ........................................................................................................................... 11
7.3. RESET ........................................................................................................................................................................ 12
7.3.1. Power-On Reset (POR) ........................................................................................................................................ 12
7.3.2. Software Reset ...................................................................................................................................................... 12
7.4. CLOCKING .................................................................................................................................................................. 13
7.4.1. Phase-Locked Loop .............................................................................................................................................. 14
7.4.2. I2C and I2S/PCM Interface ................................................................................................................................... 15
7.5. DIGITAL DATA INTERFACE ........................................................................................................................................ 16
7.5.1. Two I2S/PCM Interface ......................................................................................................................................... 16
7.6. AUDIO DATA PATH .................................................................................................................................................... 19
7.6.1. Stereo Analog ADCs Record Path ........................................................................................................................ 19
7.6.2. Stereo Analog DACs with Playback Path ............................................................................................................. 20
7.6.3. Mixers ................................................................................................................................................................... 21
7.7. ANALOG AUDIO INPUT PORT ..................................................................................................................................... 22
7.8. ANALOG AUDIO OUTPUT PORT .................................................................................................................................. 23
7.9. MULTI-FUNCTION PINS .............................................................................................................................................. 24
7.10. DRC AND AGC FUNCTION ........................................................................................................................................ 25
7.11. EQUALIZER BLOCK .................................................................................................................................................... 28
7.12. WIND FILTER WITH DYNAMIC WIND NOISE DETECTOR ............................................................................................. 28
7.12.1. Wind Filter ....................................................................................................................................................... 28
7.13. I2C CONTROL INTERFACE .......................................................................................................................................... 31
7.13.1. Address Setting ................................................................................................................................................ 31
7.13.2. Complete Data Transfer .................................................................................................................................. 31
7.14. GPIO, INTERRUPT AND JACK DETECTION .................................................................................................................. 33
7.15. POWER MANAGEMENT............................................................................................................................................... 36
8. REGISTERS LIST ........................................................................................................................................................... 37
8.1. REGISTER MAP .......................................................................................................................................................... 37
8.2. MX-00H: S/W RESET & DEVICE ID ........................................................................................................................... 39
8.3. MX-02H: HEADPHONE OUTPUT CONTROL................................................................................................................. 39
I2S Audio CODEC for Mobile Devices iv Rev. 0.1
ALC5616
Datasheet
8.4. MX-03H: LINE OUTPUT CONTROL 1 ......................................................................................................................... 41
8.5. MX-05H: LINE OUTPUT CONTROL 2 ......................................................................................................................... 42
8.6. MX-0DH: IN1/2 INPUT CONTROL .............................................................................................................................. 42
8.7. MX-0FH: INL & INR VOLUME CONTROL ................................................................................................................. 43
8.8. MX-19H: DACL1/R1 DIGITAL VOLUME ................................................................................................................... 44
8.9. MX-1CH: STEREO1 ADC DIGITAL VOLUME CONTROL ............................................................................................. 46
8.10. MX-1EH: ADC DIGITAL BOOST GAIN CONTROL ...................................................................................................... 48
8.11. MX-27H: STEREO1 ADC DIGITAL MIXER CONTROL ................................................................................................. 48
8.12. MX-29H: STEREO ADC TO DAC DIGITAL MIXER CONTROL..................................................................................... 49
8.13. MX-2AH: STEREO DAC DIGITAL MIXER CONTROL .................................................................................................. 49
8.14. MX-3BH: RECMIXL CONTROL 1 ............................................................................................................................. 50
8.15. MX-3CH: RECMIXL CONTROL 2 ............................................................................................................................. 51
8.16. MX-3DH: RECMIXR CONTROL 1 ............................................................................................................................. 51
8.17. MX-3EH: RECMIXR CONTROL 2 ............................................................................................................................. 52
8.18. MX-45H: HPOMIX CONTROL ................................................................................................................................... 53
8.19. MX-4DH: OUTMIXL CONTROL 1 ............................................................................................................................ 53
8.20. MX-4EH: OUTMIXL CONTROL 2 ............................................................................................................................. 54
8.21. MX-4FH: OUTMIXL CONTROL 3 ............................................................................................................................. 54
8.22. MX-50H: OUTMIXR CONTROL 1 ............................................................................................................................. 55
8.25. MX-53H: LOUTMIX CONTROL ................................................................................................................................ 57
8.26. MX-61H: POWER MANAGEMENT CONTROL 1 ............................................................................................................ 58
8.32. MX-6AH: PRIVATE REGISTER INDEX......................................................................................................................... 62
8.33. MX-6CH: PRIVATE REGISTER DATA.......................................................................................................................... 62
8.34. MX-70H: I2S1 DIGITAL INTERFACE CONTROL .......................................................................................................... 62
8.35. MX-73H: ADC/DAC CLOCK CONTROL 1 .................................................................................................................. 63
8.36. MX-74H: ADC/DAC CLOCK CONTROL 2 .................................................................................................................. 63
8.37. MX-80H: GLOBAL CLOCK CONTROL ......................................................................................................................... 64
8.38. MX-81H: PLL CONTROL 1......................................................................................................................................... 64
8.39. MX-82H: PLL CONTROL 2......................................................................................................................................... 65
8.40. MX-8EH: HP AMP CONTROL 1 .................................................................................................................................. 65
8.41. MX-8FH: HP AMP CONTROL 2 .................................................................................................................................. 66
8.42. MX-93H: MICBIAS CONTROL .................................................................................................................................. 66
8.43. MX-94H: JACK DETECTION CONTROL ....................................................................................................................... 67
8.44. MX-B0H: EQ CONTROL 1 .......................................................................................................................................... 67
8.45. MX-B1H: EQ CONTROL 2 .......................................................................................................................................... 68
8.46. MX-B4H: DRC/AGC CONTROL 1 ............................................................................................................................. 69
8.49. MX-BBH: JACK DETECTION CONTROL 1 ................................................................................................................... 73
8.50. MX-BCH: JACK DETECTION CONTROL 2 ................................................................................................................... 73
8.51. MX-BDH: IRQ CONTROL 1 ....................................................................................................................................... 74
8.52. MX-BEH: IRQ CONTROL 2 ........................................................................................................................................ 75
8.53. MX-BFH: GPIO AND INTERNAL STATUS ................................................................................................................... 75
8.54. MX-C0H: GPIO CONTROL 1 ...................................................................................................................................... 76
8.55. MX-C1H: GPIO CONTROL 2 ...................................................................................................................................... 76
8.56. MX-D3H: WIND FILTER CONTROL 1 ......................................................................................................................... 77
8.57. MX-D4H: WIND FILTER CONTROL 2 ......................................................................................................................... 77
8.58. MX-D9H: SOFT VOLUME & ZCD CONTROL .............................................................................................................. 78
I2S Audio CODEC for Mobile Devices v Rev. 0.1

ALC5616
Datasheet
8.59. MX-FAH: GENERAL CONTROL 1 ............................................................................................................................... 79
8.60. PR-3DH: ADC/DAC RESET CONTROL .................................................................................................................... 79
8.61. PR-A0H: EQ LOW PASS FILTER COEFFICIENT (LPF:A1) ........................................................................................... 80
8.62. PR-A1H: EQ LOW PASS FILTER GAIN (LPF:H0) ....................................................................................................... 80
8.63. PR-A2H: EQ BAND 1 COEFFICIENT (BPF1:A1) ......................................................................................................... 80
8.65. PR-A4H: EQ BAND 1 GAIN (BPF1:H0) ..................................................................................................................... 81
8.68. PR-A7H: EQ BAND 2 GAIN (BPF2:H0) ..................................................................................................................... 81
8.71. PR-AAH: EQ BAND 3 GAIN (BPF3:H0) .................................................................................................................... 82
8.72. PR-ABH: EQ BAND 4 COEFFICIENT (BPF4:A1) ......................................................................................................... 82
8.73. PR-ACH: EQ BAND 4 COEFFICIENT (BPF4:A2) ......................................................................................................... 83
8.74. PR-ADH: EQ BAND 4 GAIN (BPF4:H0) .................................................................................................................... 83
8.75. PR-AEH: EQ HIGH PASS FILTER 1 COEFFICIENT (HPF1:A1) ..................................................................................... 83
8.76. PR-AFH: EQ HIGH PASS FILTER 1 GAIN (HPF1:H0) ................................................................................................. 83
8.77. PR-B0H: EQ HIGH PASS FILTER 2 COEFFICIENT (HPF2:A1) ...................................................................................... 84
8.78. PR-B1H: EQ HIGH PASS FILTER 2 COEFFICIENT (HPF2:A2) ...................................................................................... 84
8.79. PR-B2H: EQ HIGH PASS FILTER 2 GAIN (HPF2:H0) ................................................................................................. 84
8.80. PR-B3H: EQ PRE VOLUME CONTROL ........................................................................................................................ 84
8.81. PR-B4H: EQ POST VOLUME CONTROL ...................................................................................................................... 85
8.82. MX-FEH: VENDOR ID ............................................................................................................................................... 85
9. ELECTRICAL CHARACTERISTICS .......................................................................................................................... 86
9.1. DC CHARACTERISTICS ............................................................................................................................................... 86
9.1.1. Absolute Maximum Ratings .................................................................................................................................. 86
9.1.2. Recommended Operating Conditions ................................................................................................................... 86
9.1.3. Static Characteristics ........................................................................................................................................... 86
9.2. ANALOG PERFORMANCE CHARACTERISTICS .............................................................................................................. 87
9.3. SIGNAL TIMING .......................................................................................................................................................... 89
9.3.1. I2C Control Interface ............................................................................................................................................ 89
9.3.2. I2S/PCM Interface Master Mode .......................................................................................................................... 90
9.3.3. I2S/PCM Interface Slave Mode ............................................................................................................................. 91
10. APPLICATION CIRCUITS ....................................................................................................................................... 92
11. PACKAGE INFORMATION ..................................................................................................................................... 94
12. ORDERING INFORMATION ................................................................................................................................... 95
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ALC5616
Datasheet
List of Tables
TABLE 1. DIGITAL I/O PINS .......................................................................................................................................................... 7
TABLE 2. ANALOG I/O PINS .......................................................................................................................................................... 7
TABLE 3. FILTER/REFERENCE ....................................................................................................................................................... 8
TABLE 4. POWER/GROUND ........................................................................................................................................................... 9
TABLE 5. POWER SUPPLY FOR BEST PERFORMANCE................................................................................................................... 10
TABLE 6. POWER SUPPLY CONDITION FOR POWER DOWN LEAKAGE.......................................................................................... 10
TABLE 7. RESET OPERATION ...................................................................................................................................................... 12
TABLE 8. POWER-ON RESET VOLTAGE....................................................................................................................................... 12
TABLE 9. CLOCK SETTING TABLE FOR 48K (UNIT: MHZ) .......................................................................................................... 14
TABLE 10. CLOCK SETTING TABLE FOR 44.1K (UNIT: MHZ) ..................................................................................................... 14
TABLE 11. THE RELATIVE OF SYSCLK/BCLK/LRCK ............................................................................................................... 15
TABLE 12. SAMPLE RATE WITH FILTER COEFFICIENT FOR WIND FILTER..................................................................................... 29
TABLE 13. ADDRESS SETTING (0X36H) ...................................................................................................................................... 31
TABLE 14. WRITE WORD PROTOCOL ........................................................................................................................................ 32
TABLE 15. READ WORD PROTOCOL .......................................................................................................................................... 32
TABLE 16. REGISTER MAP .......................................................................................................................................................... 37
TABLE 17. MX-00H: S/W RESET & DEVICE ID .......................................................................................................................... 39
TABLE 18. MX-02H: HEADPHONE OUTPUT CONTROL ................................................................................................................ 39
TABLE 19. MX-03H: LINE OUTPUT CONTROL 1 ........................................................................................................................ 41
TABLE 20. MX-05H: LINE OUTPUT CONTROL 2 ........................................................................................................................ 42
TABLE 21. MX-0DH: IN1/2 INPUT CONTROL ............................................................................................................................. 42
TABLE 22. MX-0FH: INL & INR VOLUME CONTROL................................................................................................................. 43
TABLE 23. MX-19H: DACL1/R1 DIGITAL VOLUME .................................................................................................................. 44
TABLE 24. MX-1CH: STEREO1 ADC DIGITAL VOLUME CONTROL ............................................................................................ 46
TABLE 25. MX-1EH: ADC DIGITAL BOOST GAIN CONTROL ...................................................................................................... 48
TABLE 26. MX-27H: STEREO1 ADC DIGITAL MIXER CONTROL ................................................................................................ 48
TABLE 27. MX-29H: STEREO ADC TO DAC DIGITAL MIXER CONTROL .................................................................................... 49
TABLE 28. MX-2AH: STEREO DAC DIGITAL MIXER CONTROL ................................................................................................. 49
TABLE 29. MX-3BH: RECMIXL CONTROL 1 ............................................................................................................................ 50
TABLE 30. MX-3CH: RECMIXL CONTROL 2 ............................................................................................................................ 51
TABLE 31. MX-3DH: RECMIXR CONTROL 1 ............................................................................................................................ 51
TABLE 32. MX-3EH: RECMIXR CONTROL 2 ............................................................................................................................ 52
TABLE 33. MX-45H: HPOMIX CONTROL .................................................................................................................................. 53
TABLE 34. MX-4DH: OUTMIXL CONTROL 1 ............................................................................................................................ 53
TABLE 35. MX-4EH: OUTMIXL CONTROL 2 ............................................................................................................................ 54
TABLE 36. MX-4FH: OUTMIXL CONTROL 3 ............................................................................................................................ 54
TABLE 37. MX-50H: OUTMIXR CONTROL 1 ............................................................................................................................ 55
TABLE 38 MX-51H: OUTMIXR CONTROL 2 ............................................................................................................................. 56
TABLE 39. MX-52H: OUTMIXR CONTROL 3 ............................................................................................................................ 56
TABLE 40 MX-53H: LOUTMIX CONTROL ................................................................................................................................ 57
TABLE 41. MX-61H: POWER MANAGEMENT CONTROL 1 ........................................................................................................... 58
TABLE 47. MX-6AH: PRIVATE REGISTER INDEX ........................................................................................................................ 62
TABLE 48. MX-6CH: PRIVATE REGISTER DATA ......................................................................................................................... 62
TABLE 49. MX-70H: I2S1 DIGITAL INTERFACE CONTROL.......................................................................................................... 62
TABLE 50. MX-73H: ADC/DAC CLOCK CONTROL 1 ................................................................................................................. 63
TABLE 51. MX-74H: ADC/DAC CLOCK CONTROL 2 ................................................................................................................. 63
TABLE 52. MX-80H: GLOBAL CLOCK CONTROL ........................................................................................................................ 64
I2S Audio CODEC for Mobile Devices vii Rev. 0.1

ALC5616
Datasheet
TABLE 53. MX-81H: PLL CONTROL 1 ........................................................................................................................................ 64
TABLE 54. MX-82H: PLL CONTROL 2 ........................................................................................................................................ 65
TABLE 55. MX-8EH: HP AMP CONTROL 1 ................................................................................................................................. 65
TABLE 56. MX-8FH: HP AMP CONTROL 2 ................................................................................................................................. 66
TABLE 57. MX-93H: MICBIAS CONTROL ................................................................................................................................. 66
TABLE 58. MX-94H: JACK DETECTION CONTROL ...................................................................................................................... 67
TABLE 59. MX-B0H: EQ CONTROL 1 ......................................................................................................................................... 67
TABLE 60. MX-B1H: EQ CONTROL 2 ......................................................................................................................................... 68
TABLE 61. MX-B4H: DRC/AGC CONTROL 1 ............................................................................................................................. 69
TABLE 64. MX-BBH: JACK DETECTION CONTROL 1 .................................................................................................................. 73
TABLE 65. MX-BCH: JACK DETECTION CONTROL 2 .................................................................................................................. 73
TABLE 66. MX-BDH: IRQ CONTROL 1 ....................................................................................................................................... 74
TABLE 67. MX-BEH: IRQ CONTROL 2 ....................................................................................................................................... 75
TABLE 68. MX-BFH: GPIO AND INTERNAL STATUS .................................................................................................................. 75
TABLE 69. MX-C0H: GPIO CONTROL 1 ..................................................................................................................................... 76
TABLE 70. MX-C1H: GPIO CONTROL 2 ..................................................................................................................................... 76
TABLE 71. MX-D3H: WIND FILTER CONTROL 1 ......................................................................................................................... 77
TABLE 72. MX-D3H: WIND FILTER CONTROL 2 ......................................................................................................................... 77
TABLE 73. MX-D9H: SOFT VOLUME & ZCD CONTROL ............................................................................................................. 78
TABLE 74. MX-FAH: GENERAL CONTROL 1............................................................................................................................... 79
TABLE 75. PR-3DH: ADC/DAC RESET CONTROL .................................................................................................................... 79
TABLE 76. PR-A0H: EQ LOW PASS FILTER COEFFICIENT (LPF:A1) ........................................................................................... 80
TABLE 77. PR-A1H: EQ LOW PASS FILTER GAIN (LPF:H0) ....................................................................................................... 80
TABLE 78. PR-A2H: EQ BAND 1 COEFFICIENT (BPF1:A1) ......................................................................................................... 80
TABLE 80. PR-A4H: EQ BAND 1 GAIN (BPF1:H0)..................................................................................................................... 81
TABLE 81 PR-A5H: EQ BAND 2 COEFFICIENT (BPF2:A1) .......................................................................................................... 81
TABLE 83. PR-A7H: EQ BAND 2 GAIN (BPF2:H0)..................................................................................................................... 81
TABLE 86. PR-AAH: EQ BAND 3 GAIN (BPF3:H0) .................................................................................................................... 82
TABLE 87. PR-ABH: EQ BAND 4 COEFFICIENT (BPF4:A1) ........................................................................................................ 82
TABLE 88. PR-ACH: EQ BAND 4 COEFFICIENT (BPF4:A2) ........................................................................................................ 83
TABLE 89. PR-ADH: EQ BAND 4 GAIN (BPF4:H0) .................................................................................................................... 83
TABLE 90. PR-AEH: EQ HIGH PASS FILTER 1 COEFFICIENT (HPF1:A1) .................................................................................... 83
TABLE 91. PR-AFH: EQ HIGH PASS FILTER 1 GAIN (HPF1:H0) ................................................................................................ 83
TABLE 92. PR-B0H: EQ HIGH PASS FILTER 2 COEFFICIENT (HPF2:A1) ..................................................................................... 84
TABLE 93. PR-B1H: EQ HIGH PASS FILTER 2 COEFFICIENT (HPF2:A2) ..................................................................................... 84
TABLE 94. PR-B2H: EQ HIGH PASS FILTER 2 GAIN (HPF2:H0) ................................................................................................. 84
TABLE 95. PR-B3H: EQ PRE VOLUME CONTROL ....................................................................................................................... 84
TABLE 96. PR-B4H: EQ POST VOLUME CONTROL ..................................................................................................................... 85
TABLE 97. MX-FEH: VENDOR ID............................................................................................................................................... 85
TABLE 98. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 86
TABLE 99. RECOMMENDED OPERATING CONDITIONS ................................................................................................................ 86
TABLE 110. STATIC CHARACTERISTICS ...................................................................................................................................... 86
TABLE 111. ANALOG PERFORMANCE CHARACTERISTICS ........................................................................................................... 87
TABLE 112. I2C TIMING .............................................................................................................................................................. 89
TABLE 113 TIMING OF I2S/PCM MASTER MODE ........................................................................................................................ 90
TABLE 114. I2S/PCM SLAVE MODE TIMING ............................................................................................................................... 91
TABLE 115. ORDERING INFORMATION ........................................................................................................................................ 95
I2S Audio CODEC for Mobile Devices viii Rev. 0.1

ALC5616
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM ....................................................................................................................................................... 3
FIGURE 2. AUDIO MIXER PATH ................................................................................................................................................... 4
FIGURE 3. DIGITAL MIXER PATH ................................................................................................................................................ 5
FIGURE 4. PIN ASSIGNMENTS ...................................................................................................................................................... 6
FIGURE 5. AUDIO CLOCK TREE ................................................................................................................................................. 13
FIGURE 6. PCM MONO DATA MODE A FORMAT (BCLK POLARITY=0) .............................................................................. 16
FIGURE 7. PCM MONO DATA MODE A FORMAT (BCLK POLARITY=1) .............................................................................. 16
FIGURE 8. PCM MONO DATA MODE B FORMAT (BCLK POLARITY=0) .............................................................................. 17
FIGURE 9. PCM STEREO DATA MODE A FORMAT (BCLK POLARITY=0) .............................................................................. 17
FIGURE 10. PCM STEREO DATA MODE B FORMAT (BCLK POLARITY=0).............................................................................. 17
FIGURE 11. I2S DATA FORMAT (BCLK POLARITY=0)............................................................................................................. 18
FIGURE 12. LEFT-JUSTIFIED DATA FORMAT (BCLK POLARITY=0) ........................................................................................ 18
FIGURE 13. 2-CHANNEL RECORDING PATH ................................................................................................................................ 19
FIGURE 14. 4-CHANNEL PLAYBACK PATH .................................................................................................................................. 20
FIGURE 15. DAC DRC FUNCTION BLOCK .................................................................................................................................. 25
FIGURE 16. ADC AGC FUNCTION BLOCK .................................................................................................................................. 25
FIGURE 17. DRC/AGC FOR PLAYBACK/RECORDING MODE ....................................................................................................... 26
FIGURE 18. DRC/AGC FOR NOISE GATE MODE ......................................................................................................................... 27
FIGURE 19. DATA TRANSFER OVER I2C CONTROL INTERFACE ................................................................................................... 31
FIGURE 20. GPIO FUNCTION BLOCK .......................................................................................................................................... 33
FIGURE 21. IRQ FUNCTION BLOCK............................................................................................................................................. 33
FIGURE 22. JD SOURCE SELECTION ............................................................................................................................................ 34
FIGURE 23. POWER MANAGEMENT ............................................................................................................................................. 36
FIGURE 24. I2C CONTROL INTERFACE ......................................................................................................................................... 89
FIGURE 25. TIMING OF I2S/PCM MASTER MODE ........................................................................................................................ 90
FIGURE 26. I2S/PCM SLAVE MODE TIMING ............................................................................................................................... 91
FIGURE 27. APPLICATION CIRCUIT ............................................................................................................................................. 93
FIGURE 28. PACKAGE DIMENSION .............................................................................................................................................. 94
I2S Audio CODEC for Mobile Devices ix Rev. 0.1

ALC5616
Datasheet
1. General Description
The ALC5616 is a high performance, low power, stereo channel I2S interface audio CODEC. The
transmitted data can from analog input or digital microphone input. Also the received data can to
headphone output, line output.
The ALC5616 features an ultra low power cap-free headphone amplifier. It consumes only less than
6.5mW power during playback, providing mobile system longer battery life under headphone listening
mode.
The integrated DRC(Dynamic Range Controller) and 7-band parametric Equalizer provide further digital
sound processing capability of audio playback paths. The DRC in ALC5616 continuously monitors the
DAC output level. When the power level is low, it increases the input signal gain to make it sound louder.
At the same time, if a peaking signal is detected, it autonomously reduces the applied gain to avoid hard
clipping. It ensures the maximum/consistent signal amplitude without producing audio clipping and
speaker damage. The 7-band parametric Equalizer contains 7 independent filters with programmable gain,
center frequency and bandwidth to tailor the frequency characteristics of embedded speaker system
according to user preferences.
For microphone recording, the DRC in ALC5616 can be used as AGC(Auto Gain Controller) to maintain
a constant recording volume. Besides, a dynamic wind reduction filter is built in on recording path. The
filter can detect the level of wind noise and on/off dynamically to keep the recording quality.
ALC5616 only requires two voltage supplies and consume ultra low power, making it ideal for mobile
devices.
Two-Channel Audio Hub/CODEC and SounzRealTM 1 Rev. 0.1

Digital Sound Effect for Mobile Devices
ALC5616
Datasheet
2. Features
Analog Features:
 Digital-to-Analog Converter with 98dBA SNR

 Analog-to-Digital Converter with 94dBA SNR
 Differential analog microphone inputs with boost pre-amplifiers and low noise microphone bias
 +20/+24/+30/+35/+40/+44/+50/+52 dB microphone boost gain
 MIC input to ADC with 50dB boost gain, SNR > 66dBA and THD+N < -65dB
 Adjustable MICBIAS (0.9*MICVDD or 0.75*MICVDD)
 Stereo line inputs
 Line input to ADC with 0dB gain, SNR >= 94dBA, THD+N <= -83dB
 Stereo line outputs
 DAC to line output with 0dB gain, SNR >= 98dBA, THD+N <= -86dB
 Stereo Cap-Free headphone amplifier with ultra low power consumption for playback
 20mW/CH (AVDD=CPVDD=1.8V, THD+N <= -80dB, 16Ohm Load)
 Playback power consumption <= 6.5mW (AVDD=VBVDD=CPVDD=1.8V, 16Ohm, With I2S
Clock, Playback Silence)
 Playback power consumption <= 14mW (AVDD=VBVDD=CPVDD=1.8V, 16Ohm, With I2S
Clock, Playback 1mW/CH)
 Audio jack detection
 Inside PLL can receiver wide range clock input
Digital Features:
 One 24bit/8kHz ~ 192kHz I2S/PCM interface for stereo DAC and stereo ADC
 I2C control interface
 7-bands flexible equalizer (EQ) for DAC path or ADC path
 Enhanced DRC(Dynamic Range Control)/AGC(Auto Gain Control) function for DAC path or ADC
path
 One wind noise reduction filter
 Zero detection and soft volume for pop noise suppression
3. System Application
 Smart Phones
 Tablet
I2S Audio CODEC for Mobile Devices 2 Rev. 0.1

ALC5616
Datasheet
4. Function Block and Mixer Path

4.1. Function Block
MICVDD
CPVDD
DBVDD
AVDD
CPP
CPN
Digtial I/O Analog Core
MICBIAS
Charge Pump CPP2
DCVDD Headphone
Digital Core 0.9 * MICVDD
0.75 * MICVDD block CPN2
CPVEE
CPVPP
LDO
CPGND
Charge Pump
DGND
AGND
AIN HPOL
IN1P
HPOR
BST1
ADC_L
INL_Vol REC Output
Mixer DACL1
Mixer
INR_Vol Audio Signal &
ADC
Volume Processing DAC
Volume Volume LOUTL/P
ADC_R
IN2P/INL1 High Pass
Filter
High Pass
Filter LOUTR/N
IN2N/INR1 DACR1
BST2
JD1/2 Analog JD
LDO
MICBIAS MICBIAS
AVDD
Reference Digital Audio Interface

VREF Voltage I 2C
PLL
Control
GPIO1/IRQ1
DACDAT1
SDA
LRCK1
ADCDAT1
SCL
BCLK1
MCLK
Figure 1. Block Diagram

ALC5616
Datasheet
4.2. Audio Mixer Path
HPOVOLL
RECMIXL Gain
mu_hpvol_hpo, MX45[13] En_bst_hp HPOL
-18 ~ 0dB, 3dB/step -18 ~ 0dB, 3dB/step MX45[12]
0/20/24/30/35/40/44/50/52
BST2 HPOVOLL DACL1 mu_hpo_l
IN1P BST2 Gain HPOVOLL Gain MX02[15]
Gain mu_bst2_outmixl, MX4F[6] Gain_bst2_outmixl, MX4D[12:10] mu_hpovoll_in vol_hpol
mu_bst2_recmixl mu_dac1_hpo, MX45[14]-6 ~ 0dB, 6dB/step
Digital Volume
BST1 Gain_bst2_recmixl, MX3B[3:1] BST1 MX02[14] MX02[13:8] HPOLMIX
MX3C[2] Gain
Filter &
mu_bst1_outmixl, MX4F[5] (-46.5 ~ +12dB, 1.5dB/step)
Sel_bst1 BST1 Gain ADC_L Gain_bst1_outmixl, MX4D[9:7]
VMID INL1
Digital Volume
MX0D[15:12] mu_bst1_recmixl Gain_bst1_recmixl, MX3C[15:13] Gain
BST1 mu_inl1_outmixl, MX4F[4]
Filter &
MX3C[1] DACL1 Gain_inl1_outmixl, MX4D[6:4]
INL1 DAC_L1 RECMIXL OUTVOLL
Gain Gain OUTVOLL
mu_inl1_recmixl mu_recmixl_outmixl, MX4F[3] Gain_recmixl_outmixl, MX4D[3:1] mu_outvoll_in vol_outl
Gain_inl1_recmixl, MX3B[12:10]
MX3C[5] RECMIXL DACL1 MX03[14] MX03[13:8] DACL1
Gain Gain
0/20/24/30/35/40/44/50/52 (-46.5 ~ +12dB, 1.5dB/step)
mu_dacl1_outmixl, MX4F[0] Gain_inl2_outmixl, MX4E[6:4] mu_dacl1_lout, MX53[15] LOUTL
IN2P bst_lout
OUTMIXL MX53[11] mu_lout_l
En_in2_df BST2 MX03[15] LOUTL/P
OUTVOLL
IN2N MX0D[6] Gain
Sel_bst2 mu_outvoll_lout, MX53[13]
MX0D[11:8] DACR1
Gain mu_lout_r
VMID BST2
mu_dacr1_lout, MX53[14] LOUTR MX03[7] LOUTR/N
-18 ~ 0dB, 3dB/step
Audio Signal bst_lout
Digital Volume
MX53[11]
INR1 -18 ~ 0dB, 3dB/step
Filter &
INR1 Gain OUTVOLR
DAC_R1 DACR1 DACR1 Gain
Digital Volume
mu_inr1_recmixr Gain_inr1_recmixr, MX3D[12:10]
-34.5~+12dB,1.5dB/step MX3E[5] Processing Gain
mu_dacr1_outmixr, MX52[0] Gain_dacr1_outmixr, MX51[9:7] OUTVOLR
OUTVOLR
mu_outvolr_lout, MX53[12]
Filter &
vol_inr1 BST1 mu_outvolr_in vol_outr -6 ~ 0dB, 6dB/step LOUTMIX
Gain ADC_R RECMIXR MX03[6]
MX0F[4:0] mu_bst1_recmixr Gain MX03[5:0]
Gain_bst1_recmixr, MX3E[15:13] mu_recmixr_outmixr, MX52[3] Gain_recmixr_outmixr, MX50[3:1] (-46.5 ~ +12dB, 1.5dB/step)
MX3E[1]
BST2 INR1
INL1 Gain Gain
mu_bst2_recmixr mu_inr1_outmixr, MX52[4] Gain_inr1_outmixr, MX50[6:4]
-28.5~+18dB,1.5dB/step MX3E[2] Gain_bst2_recmixr, MX3D[3:1] BST1
vol_inl1 RECMIXR Gain HPOVOLR
mu_bst1_outmixr, MX52[5] HPOVOLR
MX0F[12:8] Gain_bst1_outmixr, MX50[9:7] mu_hpovolr_in vol_hpor
RECMIXR BST2 HPOVOLR
Gain MX02[6] MX02[5:0] Gain
mu_bst2_outmixr, MX52[6] -46.5 ~ +12dB, 1.5dB/step) mu_hpvol_hpo, MX45[13] En_bst_hp HPOR
Gain_bst2_outmixr, MX50[12:10]
OUTMIXR MX45[12] mu_hpo_r
DACR1
Gain MX02[7]
mu_dac1_hpo, MX45[14] HPORMIX
-6 ~ 0dB, 6dB/step
DACDAT1
ADCDAT1
Figure 2. Audio Mixer Path

ALC5616
Datasheet
4.3. Digital Mixer Path
Stereo1_ADC_Mixer_R
mu_stereo1_adc_mixer_1
MX29[15]
mu_stereo1_adcl1 gain_dacl1_to_stereo_l, MX2A[13]
DACL1 mu_stereo_dacl1_mixl
Gain
MX27[13] EQ ALC EQ ALC MX2A[14]
ADC_L Wind
VOL IF1_DAC1_L Stereo_DAC_MIXL
filter mu_adc1_vol_l VOL DACL1
vol_adc1_l MX1C[15] mu_dac1_l
MX1C[14:8] vol_dac1_l
MX29[14]
DACR1 mu_stereo_dacr1_mixl
Gain
Only one of DAC/ADC MX19[15:8]
Only one of DAC/ADC MX2A[9]
gain_dacr1_to_stereo_l, MX2A[8]
path pass through RTK path pass through RTK
Effect mu_dac1_r Effect
IF1_DAC1_R VOL MX29[6]
vol_dac1_r gain_dacr1_to_stereo_r, MX2A[5]
mu_stereo1_adcr1 MX19[7:0]
DACR1 mu_stereo_dacr1_mixr
Wind MX2A[6] Gain
ADC_R
MX27[6]
VOL EQ ALC EQ ALC
filter mu_adc1_vol_r Stereo_DAC_MIXR
vol_adc1_r MX1C[7]
mu_stereo1_adc_mixer_r
DACR1
MX1C[6:0]
MX29[7] DACL1 mu_stereo_dacl1_mixr
Gain
MX2A[1]
gain_dacl1_to_stereo_r, MX2A[0]
Stereo1_ADC_Mixer_L
Stereo1_ADC_Mixer_L
IF1_ADC1
Stereo1_ADC_Mixer_R
IF1_DAC1_L
IF1_DAC1_R
IF1_ADC1
Digital Interface
I2S Digital Interface Process
DACDAT1
ADCDAT1
Figure 3. Digital Mixer Path

ALC5616
Datasheet
5. Pin Assignments
ADCDAT1
DACDAT1
CPVREF
LRCK1
BCLK1
HPO_L
CPVEE
HPO_R
24 23 22 21 20 19 18 17
MCLK 25 16 CPVPP
SCL 26 15 CPVDD
SDA 27 14 CPP1
GPIO1/IRQ1 28 13 CPN1
DBVDD 29 ALC5616 12 CPP2

DCVDD 30 xxxxxxx ywwvs 11 CPN2
MICVDD 31 (Top View) 10 LOUTR/N
MICBIAS1 32 9 LOUTL/P
1 2 3 4 5 6 7 8
VREF
JD1
IN2P
IN2N/JD2
DACREF
AVDD
AGND
IN1P
Figure 4. Pin Assignments

ALC5616
Datasheet
6. Pin Descriptions
6.1. Digital I/O Pins
Table 1. Digital I/O Pins
Name Type Pin Description Characteristic Definition
First I2S interface serial data input Schmitt trigger
DACDAT1 I 22
(VIL=0.35*DBVDD, VIH=0.65*DBVDD)
ADCDAT1 O 21 First I2S interface serial data output VOL=0.1*DBVDD, VOH=0.9*DBVDD
First I2S interface serial bit clock Master: VOL =0.1*DBVDD, VOH =0.9*DBVDD
BCLK1 I/O 24 Slave: Schmitt trigger
First I2S interface synchronous signal Master: VOL =0.1*DBVDD, VOH =0.9*DBVDD
LRCK1 I/O 23 Slave: Schmitt trigger
SDA I/O 27 I2C interface serial data Open drain structure
SCL I 26 I2C interface clock input Schmitt trigger
I2S interface master clock input Schmitt trigger
MCLK I 25
General purpose input and output Output: VOL =0.1*DBVDD, VOH =0.9*DBVDD
GPIO1/IRQ I/O 28 Interrupt output Input: Schmitt trigger
Total: 8 Pins
6.2. Analog I/O Pins

Table 2. Analog I/O Pins
Line output type Analog output
LOUTR/N O 10 Right channel single-end output
Negative channel differential output
Line output type Analog output
LOUTL/P O 9 Left channel single-end output
Positive channel differential output
Positive differential input for microphone Analog input
IN2P I 3 2
Left channel line input
Negative differential input for Analog input
microphone 2 JD threshold: VIL = 0.5V, VIH = 1.2V
IN2N/JD2 I 4
Right channel line input
Second jack detection pin

ALC5616
Datasheet
IN1P I 2 Single-end input for microphone 1 Analog input
First jack detection pin Multi-level jack detection pin
JD threshold:
JD1 I 1 Vt1 = 1.485V
Vt2 = 1.925V
Vt3 = 2.7V
Headphone amplifier output Analog output
HPO_R O 17
Right channel
Headphone amplifier output Analog output
HPO_L O 20
Left channel
Total: 8 Pins
6.3. Filter/Reference
Table 3. Filter/Reference
MICBIAS1 O 32 Bias voltage output for microphone Programmable analog DC output
VREF O 8 Internal reference voltage 4.7uF capacitor to analog ground
CPVREF - 18 Headphone reference ground Headphone ground
CPN1 - 13 First charge pump bucket capacitor 2.2uf capacitor to CPP1
CPP1 - 14 First charge pump bucket capacitor 2.2uf capacitor to CPN1
CPN2 - 11 Second charge pump bucket capacitor 2.2uf capacitor to CPP2
CPP2 - 12 Second charge pump bucket capacitor 2.2uf capacitor to CPN2
Total: 7 Pins

ALC5616
Datasheet
6.4. Power/Ground
Table 4. Power/Ground
MICVDD P 31 Analog power for MICBIAS 3.0V ~ 3.3V (Default 3.3V is recommended)
AVDD P 6 Analog power 1.71V ~ 1.9V (Default 1.8V is recommended)
DACREF P 5 Analog power 1.71V ~ 1.9V (Default 1.8V is recommended)
AGND P 7 Analog ground
Analog power for headphone charge 1.71V ~ 1.9V (Default 1.8V is recommended)
CPVDD P 15
pump
CPVEE P 19 Charge pump negative voltage output 2.2uf capacitor to analog ground
CPVPP P 16 Charge pump positive voltage output 2.2uf capacitor to analog ground
DCVDD P 30 Digital power for digital core. Internal LDO generated
DBVDD P 29 Digital power for digital I/O buffer 1.71V~3.3V (Default 1.8V is recommended)
CPGND/ Charge pump ground Exposed-Pad
P 33*
DGND Digital ground
Total: 9 Pins

ALC5616
Datasheet
7. Function Description
7.1. Power
There are different power types in ALC5616. DBVDD is for digital I/O power, DCVDD is for digital
core power, AVDD and DACREF are for analog power, CPVDD is for charge pump power, MICVDD is
for MICBIAS power.
The power supplier limit condition are MICVDD > AVDD = DACREF = CPVDD, and for the best
performance, our design setting is show on below.
Table 5. Power Supply for Best Performance

Power DBVDD DCVDD AVDD DACREF CPVDD MICVDD
Setting 1.8V 1.2V 1.8V 1.8V 1.8V 3.3V
*1.2V DCVDD was generated by internal LDO.
To prevent all power down leakage, needs keep all power supply on.
Table 6. Power Supply Condition for Power Down Leakage

Power DBVDD AVDD DACREF CPVDD MICVDD
Setting Supplied Supplied Supplied Supplied Supplied

ALC5616
Datasheet
7.2. Power Supply On/Off Sequence

To prevent pop noise and make sure function work normally, following power on and off sequence are
recommended.
Power On Sequence: (Sequentially turn on power pins)
1. DBVDD/AVDD/DACREF/CPVDD power supply on.
2. MICVDD power supply on.
3. Software starts to initialize ALC5616.
Power Off Sequence: (Sequentially turn off power pins)
1. Power down all Codec function (Write 0x0000’h to register MX-00’h).
2. MICVDD power supply off.
3. DBVDD/AVDD/DACREF/CPVDD power supply off

ALC5616
Datasheet
7.3. Reset
There are 2 types of reset operation: power on reset (POR) and register reset.
Table 7. Reset Operation

Reset Type Trigger Condition CODEC Response
POR Monitor digital power supply voltage reach Reset all hardware logic and all registers to default
VPOR values.
Register Reset Write MX-00h Reset all registers to default values except some specify
control registers and logic.
7.3.1. Power-On Reset (POR)

When powered on, DCVDD passes through the VPOR band of the ALC5616 (VPOR_ON ~VPOR_OFF). A
power on reset (POR) will generate an internal reset signal (POR reset ‘LOW’) to reset the whole chip.
Table 8. Power-On Reset Voltage

Symbol Min Typical Max Unit
VPOR_ON - 0.8 - V
VPOR_OFF - 0.52 - V
Note:
1.VPOR_OFF must be below VPOR_ON
2. ToC = 25oC
3. When DCVDD is supplied 1.2V
7.3.2. Software Reset

When MX-00h is wrote, all registers become to default value.

ALC5616
Datasheet
7.4. Clocking
The system clock of ALC5616 can be selected from MCLK or PLL. MCLK is always provided externally
while the reference clock of PLL can be selected from MCLK, BCLK1. The driver should arrange the
clock of each block and setup each divider.
The Clk_sys_i2s1=256*Fs provides clocks into stereo1 DAC/ADC filter that can be selected from MCLK
or PLL. Refer to Figure 5. Audio SYSCLK
When ALC5616 at master mode, the clock source from MCLK will be divided and be sent to external
device. The ratio of BCLK and LRCK can set by register – MX73.
MX80[15:14]
MCLK
MX73[14:12]
MX80[3] Clk_sys_i2s1(256FS) Stereo1
MX80[13:12] DIV_F1
MCLK ÷2 Inter. Clock DAC/ADC
(Slave)
PLL
PLL
MX81 & MX82
MX70[15]
BCLK1(Master)
BCLK1
Master Mode
Clk_sys_i2s1 (256FS)
LRCK/BCLK
MX70[15] LRCK1(Master) Ratio
LRCK1 (64FS)
LRCK1(Slave)
Figure 5. Audio Clock Tree

ALC5616
Datasheet
7.4.1. Phase-Locked Loop

A Phase-Locked Loop (PLL) is used to provide a flexible input clock from 2.048MHz to 40MHz. The
source of the PLL can be set to MCLK, BCLK1 by setting register.
The S/W driver can set up the PLL to output a frequency to match the requirement of system clock.
The PLL transmit formula as below:
FOUT = (MCLK * (N+2)) / ((M+2) * (K+2)) {Typical K=2}
Table 9. Clock Setting Table for 48K (Unit: MHz)

MCLK N M FVCO K FOUT
13 66 7 98.222 2 24.555
3.6864 78 1 98.304 2 24.576
2.048 94 0 98.304 2 24.576
4.096 70 1 98.304 2 24.576
12 80 8 98.4 2 24.6
15.36 81 11 98.068 2 24.517
16 78 11 98.462 2 24.615
19.2 80 14 98.4 2 24.6
19.68 78 14 98.4 2 24.6
24 39 8 98.4 2 24.6
Table 10. Clock Setting Table for 44.1K (Unit: MHz)

MCLK N M FVCO K FOUT
13 68 8 91 2 22.75
3.6864 72 1 90.931 2 22.733
2.048 86 0 90.112 2 22.528
4.096 64 1 90.112 2 22.528
12 66 7 90.667 2 22.667
15.36 63 9 90.764 2 22.691
16 66 10 90.667 2 22.667
19.2 64 12 90.514 2 22.629
19.68 67 13 90.528 2 22.632
24 62 15 90.352 2 22.588

ALC5616
Datasheet
7.4.2. I2C and I2S/PCM Interface

The ALC5616 supports I2C for the digital control interface, and has one I2S/PCM for digital data
interface. The I2S/PCM audio digital interface was used to send data to stereo DACs or receive data from
a stereo ADC. The I2S/PCM audio digital interface was also can be configured to Master mode or Slave
mode.
Master Mode
Under master mode, BCLK and LRCK are configured as output. If I2S SYSCLK is selected from MCLK
source, sel_sysclk1 (MX-80[15:14]) should set as 00’b. If selected from PLL output, sel_sysclk1 should
set as 01’b. PLL’s source is suggested to provide frequency from 2.048MHz to 40MHz. The driver
should set each divider (MX-73 and MX-89) to arrange the clock distribution. Refer to Figure5. Audio
Clock Tree, for details.
Table 11. The relative of SYSCLK/BCLK/LRCK

Register Settings MCLK BCLK LRCK
MX-73[15]=0’b 256*FS=12.288MHz 32*FS=1.536MHz FS=48KHz
MX-73[15]=1’b 256*FS=12.288MHz 64*FS=3.072MHz FS=48KHz
MX-73[15]=0’b 256*FS=11.2896MHz 32*FS=1.4112MHz FS=44.1KHz
MX-73[15]=1’b 256*FS=11.2896MHz 64*FS=2.8224MHz FS=44.1KHz
Example for master mode:

Target format:
Sample Rate: 48 KHz
Channel Length: 32 bits
LRCK=48KHz
BCLK=3.071MHz (64 * 48KHz)
MCLK clock request:

MCLK=12.288MHz (256 * 48 KHz)
Register settings:
Set MX-FA[0] to “1” // For MCLK input clock getting control
Set MX-61[15] to “1” // Enable I2S-1
Set MX-70[15] to “0” // Enable Master mode
Slave Mode
Under slave mode BCLK and LRCK are configured as input. The SYSCLK can be input from MCLK or
PLL and BCLK is need to synchronous to MCLK. If the SYSCLK is selected from PLL, the internal PLL
should generate 256*FS by BCLK. And the driver should set each divider to arrange the clock
distribution. Refer to Figure5. Audio Clock Tree, for details.

ALC5616
Datasheet
7.5. Digital Data Interface

7.5.1. Two I2S/PCM Interface
The two I2S/PCM interface can be configured as master mode or slave mode. Four audio data formats are
supported:
 PCM mode
 Left justified mode
 I2S mode
1/Fs
LRCK
BLCK
DACDAT/
1 2 n-1 n
ADCDAT
MSB LSB
Figure 6. PCM MONO Data Mode A Format (BCLK POLARITY=0)
1/Fs
LRCK
BLCK
DACDAT/
1 2 n-1 n
ADCDAT
MSB LSB
Figure 7. PCM MONO Data Mode A Format (BCLK POLARITY=1)

ALC5616
Datasheet
1/Fs
LRCK
BLCK
DACDAT/
1 2 n-1 n
ADCDAT
MSB LSB
Figure 8. PCM MONO Data Mode B Format (BCLK POLARITY=0)
1/ Fs
LRCK
BLCK
DACDAT/
1 2 3 n-1 n 1 2 3 n-1 n
ADCDAT
MSB LSB MSB LSB
Left-Channel Right-Channel
Figure 9. PCM Stereo Data Mode A Format (BCLK POLARITY=0)
1/Fs
LRCK
BLCK
DACDAT/
1 2 3 n-1 n 1 2 3 n-1 n
ADCDAT
MSB LSB MSB LSB
Left-Channel Right-Channel
Figure 10. PCM Stereo Data Mode B Format (BCLK POLARITY=0)

ALC5616
Datasheet
1/ Fs
Left Channel Right Channel

LRCK
BLCK
DACDAT/ 1 2 n-1 n 1 2 n-1 n

ADCDAT
MSB LSB MSB LSB
2
Figure 11. I S Data Format (BCLK POLARITY=0)
1/ Fs
Left Channel Right Channel

LRCK
BLCK
DACDAT/
1 2 n-1 n 1 2 n-1 n
ADCDAT
MSB LSB MSB LSB
Figure 12. Left-Justified Data Format (BCLK POLARITY=0)

ALC5616
Datasheet
7.6. Audio Data Path

The ALC5616 provides 2-channel analog DACs for playback and 2-channel analog ADCs for recording.
7.6.1. Stereo Analog ADCs Record Path

There are two analog ADCs and with 2-channel recording path. You can use two analog microphones
pass to analog ADCs or stereo line inputs to analog ADCs.
The full scale input of analog ADC with 0dB path setting is around 0.7Vrms. In order to save power, the
left and right analog ADC can be powered down separately by setting pow_adc_l (MX-61[2]) and
pow_adc_r (MX-61[1]). And the volume control of the stereo ADC is also separately controlled by
ad_gain_l (MX-1C[14:8]) and ad_gain_r (MX-1C[6:0]).
Analog ADC_L
CH1
I2S IF1_ADC
Analog ADC_R
CH2
Figure 13. 2-Channel Recording Path

ALC5616
Datasheet
7.6.2. Stereo Analog DACs with Playback Path

There are two analog DACs and with 2-channel playback path. The stereo analog DACs can output audio
signal to headphone output or line output.
The full scale output of analog DAC with 0dB path setting is around 1Vrms at line output port. In order to
save power, the two analog DACs can be powered down separately by setting pow_dac_l_1 (MX-61[12]),
pow_dac_r_1 (MX-61[11]). And the two digital volume controls are also separately controlled by
vol_dac1_l (MX-19[15:8]) and vol_dac1_r (MX-19[7:0]).
L CH1 Analog DACL1
IF1_DAC I2S
R CH2 Analog DACR1
Figure 14. 4-Channel Playback Path

ALC5616
Datasheet
7.6.3. Mixers
The ALC5616 has analog mixers build-in.
 Output mixer - OUTMIXL/R

The stereo analog mixer can do mixing for DAC output and analog input. The mixer output is mainly
for headphone output and line output. Each input path has individual mute control to the mixer block
in MX-4D ~ MX-52. pow_outmixl and pow_outmixr can be used to power on/off OUTMIXL/R
 Record mixer – RECMIXL/R

The stereo analog mixer can do mixing for analog input and OUTMIX output. The mixer output is for
ADC input. Each input path has individual mute control to the mixer block in MX-3B ~ MX-3E.
pow_recmixl and pow_recmixr can be used to power on/off RECMIXL/R.

ALC5616
Datasheet
7.7. Analog Audio Input Port

The ALC5616 has two types analog input ports: microphone input and line input.
 IN1P
The IN1P is a microphone type input port. The input port is single-ended type input. The microphone
input port has its microphone bias and microphone boost. The low noise microphone bias can improve
recording performance and enhance recording quality. Build-in short current detection scheme can be
used for switch detection. Multi-steps microphone boost gain set by sel_bst1 (MX-0D[15:12]) is easy
to use for microphone application. Pow_bst1 can be used to power down the MIC1 boost and
pow_micbias1 can be used to power down the microphone bias 1.
 IN2P/N
The IN2P/N is a dual type input port: microphone input and line input. Microphone input can be
configured to differential input or single-ended input by MX-0D[6]. Multi-steps microphone boost
gain set by sel_bst2 (MX-0D[11:8]) is easy to use for microphone application. Pow_bst2 can be used
to power down the MIC2 boost. As line input, it has volume control for tuning by MX-0F[12:8] and
MX-0F[4:0].

ALC5616
Datasheet
7.8. Analog Audio Output Port

The ALC5616 supports two type output ports:
 HPO_L/R
The headphone output of ALC5616 is a stereo output with cap-free type headphone amplifier. It does
not need to connect external capacitor and can connect to earphone device directly. The headphone
output source can mix from output mixer (OUTMIX) or DAC by setting MX-45. The front stage of
headphone output has volume control and gain control. The volume range is from +12dB to -46.5dB
with 1.5dB/step by MX-02.
En_l_hp and en_r_hp (MX-63[7/6]) can be used to power on/off Headphone Amplifier, and
pow_hpo_voll and pow_hpo_volr (MX-66[11/10]) can be used to power on/off headphone volume
control. In addition, pow_pump_hp (MX-8E[3]) can be used to power on/off charge pump circuit for
Headphone Amplifier.
 Line_OUT_L/R/P/N
The output type is line type output. The output is a stereo single ended output or mono differential
output. The input can be selected from OUTVOL or DAC output by setting MX-53[15:12]. The front
stage of LOUT output has gain control for attenuation. The gain control is 0dB or -6dB by
MX-53[11].

ALC5616
Datasheet
7.9. Multi-Function Pins

There are two multi-function pins in ALC5616. For different function on pin is controlled by register.
You need to set the right register settings for multi-function pin by your application.
 GPIO1/IRQ – Pin 38
The pin default is GPIO function. If want to change to IRQ output, write MX-C0[15] to 1’b that will
switch to IRQ function.
 IN2N/JD2 – Pin 4
In IN2N microphone input function, need to disable JD2 jack detection function – MX-64[1] = 0’b.
In JD2 jack detection function, need to set these register settings:

1. Power on JD2 – MX-64[1] = 1’b
2. Mute IN2 to each analog mixer - (RECMIXL/RECMIXR/OUTMIXR).
3. Set MX-64[4] = 1’b
4. Enable JD2 as jack detection source – MX-BC[11:9] = 011’b

ALC5616
Datasheet
7.10. DRC and AGC Function

The Dynamic Range Controller (DRC) dynamically adjusts the input signal and let the output signal
achieve the target level. The ALC5616 supports playback DRC for DAC path, and the DRC can also be
used as AGC(Auto Gain Controller) for ADC path. The control register is at MX-B4[15:14]. The function
block is shown as below. The signal input pass through the Pre-Gain first, then DRC volume and
Post-Gain then output. The Pre-Gain is use to enlarge the input signal. The DRC volume is use to
attenuate the signal after detected by DRC. The Post-Gain is use to fine tune the signal after pass DRC
tuning.
0 ~ 28.5dB, 1.5/step -95.625 ~ 0dB -11.625 ~ 12dB, 0.375/step

MXB5[4:0] 0.375/step MXB5[13:8]
DRC
I2C Interface Pre-Gain Post-Gain DAC
Volume
DRC
1. Limiter level
2. Attack / Release time
3. Zero data
Figure 15. DAC DRC Function Block
0 ~ 28.5dB, 1.5/step -95.625 ~ 0dB -11.625 ~ 12dB, 0.375/step

MXB5[4:0] 0.375/step MXB5[13:8]
Analog AGC
ADC Pre-Gain Post-Gain I2S Interface
Pre-Boost Volume
AGC
1. Limiter level
2. Attack / Release time
3. Noise gate
Figure 16. ADC AGC Function Block

ALC5616
Datasheet
Playback/Recording Mode:
For DAC playback or ADC recording mode, when the input signal exceeds target threshold, the signal
will decrease “DRC/AGC Digital Volume” (0.375dB/step at every zero-crossing) until drop to target
level then keep the digital volume. When input signal is below the target threshold, the signal will step-up
“DRC/AGC Digital Volume” (0.375dB/step every zero-crossing) until return to original level. If want to
return to the target level, need to set the pre-gain to achieve.
Fine tune parameters:

 Limiter Threshold: 0 ~ -46.5dB, 1.5dB/step, MX-B6[11:7]
 Attack Rate: T=(4*2^n)/sample rate, n = MX-B4[12:8]
 Recovery Rate: T=(4*2^n)/sample rate, n = MX-B4[4:0]
Input signal
Target Level
Volume
0dB
Attack Rate
Recovery Rate
Output signal
Figure 17. DRC/AGC for Playback/Recording Mode

ALC5616
Datasheet
Noise Gate Mode:
The Noise Gate Function is use to reduce the noise floor for DAC path or ADC path. When input signal is
below noise gate level, the input signal will be reduced by DRC/AGC volume in order to suppress the
background noise. The reducing level can be set by register. And when input signal is above noise gate,
the input signal will be boosted to target level.
Fine tune parameters:

 Noise Gate Threshold: -36 ~ -82.5dB, 1.5dB/step, MX-B6[4:0]
 Noise Gate Attack Rate: T=(4*2^n)/sample rate, n = PR-06[4:0]
 Noise Gate Recovery Rate: T=(4*2^n)/sample rate, n = PR-02[12:8]
 Reducing Noise Level: 0 ~ 45dB, 3dB/step, MX-B6[15:12]
Input signal
Target Level
Noise Gate
Volume
0dB
Attack Rate Recovery Rate

Attack Rate Recovery Rate
Noise Reduction
Output signal
Target Level
Noise Gate
Figure 18. DRC/AGC for Noise Gate Mode

ALC5616
Datasheet
7.11. Equalizer Block

The equalizer block cascades 7 bands of equalizer to tailor the frequency characteristics of embedded
speaker system according to user preferences and to emulate environment sound. The 7 bands equalizer
includes two high pass filter, four band pass filter and one low pass filter. One high pass filter cascaded in
the front end is used to drop low frequency tone, The tone has a large amplitude and may damage a mini
speaker. The high pass filter can be used to adjust Treble strength with gain control. One low pass filter
with gain control can adjust the Bass strength. Four bands of bi-quad band pass filters are used to emulate
environment sounds, e.g., ‘Pub’, ‘Live’, ‘Rock’,… etc.. The gain, center frequency and bandwidth of each
filter are all programmable.
7.12. Wind Filter with Dynamic Wind Noise Detector

7.12.1. Wind Filter
The wind filter is implemented by a high pass filter. The wind filter is mainly for ADC recording used.
The cut-off frequency of wind filter is programmable and is varied according to different sample rate. The
filter is used to remove DC offset at normal condition, and to remove wind noise at application mode.
Wind filter setting procedure:

Step1: Disable wind filter – MX-D3[15]
Step2: Select target sample rate – MX-D3[14:12] and MX-D3[10:8]
Step3: Fine tune wind filter Fc – MX-D4[13:8] and MX-D4[5:0]
Step4: Enable wind filter – MX-D3[15]
The following table is shown the Fc with sample rate selection.

For the formula of Fc calculation is also shown as:
Fc = (Fs * tan-1(a/(2-a))) / π
Where:
Sample rate = 8K/12K/16K (MX-D3[14:12] & [10:8]), a = 2-6 + n * 2-6 (n is MX-D4[13:8] & [5:0])
Sample rate = 24K/32K (MX-D3[14:12] & [10:8]), a = 2-7 + n * 2-7 (n is MX-D4[13:8] & [5:0])
Sample rate = 44.1K/48L (MX-D3[14:12] & [10:8]), a = 2-8 + n * 2-8 (n is MX-D4[13:8] & [5:0])

ALC5616
Datasheet
Table 12. Sample Rate with filter coefficient for Wind Filter
MX-D4 L & R Channel Sample Rate Setting
n 8K 16K 32K 44.1K 48K
000000’b, 0 20.0 40.1 39.9 27.4 29.8
000001’b, 1 40.4 80.8 80.2 55.0 59.9
000010’b, 2 61.1 122.2 120.7 82.7 90.0
000011’b, 3 82.1 164.2 161.6 110.5 120.3
000100’b, 4 103.4 206.9 202.8 138.4 150.6
000101’b, 5 125.1 250.2 244.4 166.4 181.1
000110’b, 6 147.1 294.3 286.2 194.5 211.7
000111’b, 7 169.5 339.0 328.4 222.7 242.5
001000’b, 8 192.2 384.4 371.0 251.1 273.3
001001’b, 9 215.2 430.5 413.8 279.5 304.3
001010’b, 10 238.7 477.4 457.0 308.1 335.4
001011’b, 11 262.4 524.9 500.5 336.8 366.6
001100’b, 12 286.6 573.2 544.4 365.6 397.9
001101’b, 13 311.1 622.3 588.6 394.5 429.4
001110’b, 14 336.0 672.1 633.2 423.5 460.9
001111’b, 15 361.3 722.6 678.1 452.6 492.6
010000’b, 16 386.9 773.9 723.3 481.9 524.5
010001’b, 17 413.0 826.0 768.9 511.2 556.4
010010’b, 18 439.4 878.9 814.9 540.7 588.5
010011’b, 19 466.2 932.5 861.2 570.3 620.7
010100’b, 20 493.5 987.0 907.8 600.0 653.0
010101’b, 21 521.1 1042.2 954.9 629.8 685.5
010110’b, 22 549.1 1098.2 1002.2 659.7 718.1
010111’b, 23 577.5 1155.0 1050.0 689.8 750.8
011000’b, 24 606.3 1212.7 1098.1 719.9 783.6
011001’b, 25 635.5 1271.1 1146.6 750.2 816.6
011010’b, 26 665.1 1330.3 1195.5 780.6 849.6
011011’b, 27 695.2 1390.4 1244.7 811.1 882.9
011100’b, 28 725.6 1451.2 1294.3 841.8 916.2
011101’b, 29 756.4 1512.9 1344.3 872.5 949.7
011110’b, 30 787.6 1575.3 1394.7 903.4 983.3
011111’b, 31 819.3 1638.6 1445.4 934.4 1017.0
100000’b, 32 851.3 1702.7 1496.5 965.5 1050.9
100001’b, 33 883.7 1767.5 1548.0 996.8 1084.9
100010’b, 34 916.6 1822.3 1599.9 1028.1 1119.0
100011’b, 35 949.8 1899.6 1652.2 1059.6 1153.3
100100’b, 36 983.3 1966.7 1704.9 1091.2 1187.7
100101’b, 37 1017.3 2034.7 1757.9 1122.9 1222.2
100110’b, 38 1051.6 2103.3 1811.4 1154.8 1256.9
100111’b, 39 1086.3 2172.7 1865.2 1186.7 1291.7
101000’b, 40 1121.4 2242.9 1919.5 1218.8 1326.6
101001’b, 41 1156.8 2313.7 1974.1 1251.0 1361.7
101010’b, 42 1192.6 2385.2 2029.1 1283.4 1396.9
101011’b, 43 1228.7 2457.4 2084.6 1315.8 1432.2
101100’b, 44 1265.1 2530.2 2140.4 1348.4 1467.7
101101’b, 45 1301.8 2603.6 2196.6 1381.1 1503.3
101110’b, 46 1338.8 2677.7 2253.3 1414.0 1539.0
101111’b, 47 1376.1 2752.3 2310.3 1447.0 1574.9
110000’b, 48 1413.7 2827.5 2367.7 1480.0 1610.9
110001’b, 49 1451.5 2903.1 2425.5 1513.3 1647.1

ALC5616
Datasheet
MX-D4 L & R Channel Sample Rate Setting
n 8K 16K 32K 44.1K 48K
110010’b, 50 1489.6 2979.3 2483.8 1546.6 1683.4
110011’b, 51 1528.0 3056.0 2542.4 1580.1 1719.8
110100’b, 52 1566.5 3133.1 2601.5 1613.7 1756.4
110101’b, 53 1605.3 3210.6 2660.9 1647.4 1793.1
110110’b, 54 1644.2 3288.4 2720.8 1681.3 1830.0
110111’b, 55 1683.3 3366.6 2781.0 1715.3 1867.0
111000’b, 56 1722.5 3445.1 2841.7 1749.4 1904.1
111001’b, 57 1761.9 3523.9 2902.7 1783.6 1941.4
111010’b, 58 1801.4 3602.9 2964.2 1818.0 1978.8
111011’b, 59 1841.0 3682.1 3026.1 1852.5 2016.3
111100’b, 60 1880.7 3761.4 3088.3 1887.1 2054.0
111101’b, 61 1920.4 3840.8 3151.0 1921.9 2091.9
111110’b, 62 1960.2 3920.4 3214.1 1956.8 2129.9
111111’b, 63 2000.0 4000.0 3277.5 1991.8 2168.0

ALC5616
Datasheet
7.13. I2C Control Interface

I2C is a 2-wire (SCL/SDA) half-duplex serial communication interface, supporting only slave mode. SCL
is used for clock and SDA is for data. SCL clock supports up to 400KHz rate and SDA data is a open
drain structure.
7.13.1. Address Setting

Table 13. Address Setting (0x36h)
(MSB) BIT (LSB)
0 0 1 1 0 1 0 R/W
7.13.2. Complete Data Transfer

Data Transfer over I2C Control Interface
2
Figure 19. Data Transfer Over I C Control Interface

ALC5616
Datasheet
Write WORD Protocol
Table 14. Write WORD Protocol
1 7 1 1 8 1 8 1 8 1 1
S Device Address Wr A Register Address A Data Byte High A Data Byte Low A P
Read WORD Protocol

Table 15. Read WORD Protocol
1 7 1 1 8 1 7 1 8 1 8 1 1
S Device Address Wr A Register Address A S Device Address Rd A Data Byte High A Data Byte Low NA P
S: Start Condition A: 0 for ACK, 1 for NACK

Slave Address: 7-bit Device Address Data Byte: 16-bit Mixer data
Wr: 0 for Write Command : Master-to-Slave
Rd: 1 for Read Command : Slave-to-Master
Command Code: 8-bit Register Address

ALC5616
Datasheet
7.14. GPIO, Interrupt and Jack Detection

The ALC5616 supports one GPIO – GPIO1 and two jack detection pins.
For GPIO function, the GPIO can be configured to input or output. For input type, the internal circuit can
read pin status and report to register table. For output type, the internal circuit can drive this pin to high or
low to control external device. In GPIO function, the pin polarity can be controlled by register at output
type.
MX-C2[3]
MX-C2[4]
High GPIO1
EN_OBUF
Low
MX-BF[11]
EN_IBUF
MX-C2[5]
Figure 20. GPIO Function Block
For IRQ function is shown at Figure 22, the IRQ output source can be selected from gpio_jd Status, jd1_1
Status, jd1_2 Status, jd2 Status and MICBIAS1 Over-Current Status. When either status is trigged, the
GPIO will output a flag as interrupt signal to external device.
MX-BD[11]
MX-BD[13]
sta_gpio_jd(MX-BF[4]) Sticky Control
MX-BD[7]
MX-BD[8] MX-BD[3]
MX-BE[15]
MX-BD[6]
MX-BD[9]
sta_jd1_1(MX-BF[12]) Sticky Control MX-FB[15]
MX-BD[4]
MX-BD[5]
IRQ
sta_jd1_2(MX-BF[13]) Sticky Control
MX-BE[7]
MX-BE[11]
sta_micbias1_ovcd(MX-BE[3]) Sticky Control
MX-BD[1]
MX-BD[2]
sta_jd2(MX-BF[14]) Sticky Control
Figure 21. IRQ Function Block

ALC5616
Datasheet
In general, the IRQ output needs to combine with JD function. When JD is trigger, IRQ will output a flag
to host to notice S/W driver. The S/W driver will do something by system design. The behavior flow
chard as following:
Initial Settings
(For JD and IRQ)
Device Plug-In
JD Triggered
IRQ Flag Output to Host
S/W Driver Settings
Clear JD Status for Next

JD Trigger
The MICBIAS supports short detection function. When MICBIAS circuit is short, MICBIAS circuit will
generate an over-current flag. The flag can generate an interrupt signal to notice host and let S/W do
follow-up processes.
For jack detection pins are shown at Figure 23. There is GPIO1 pins can be selected and control by
MX-BB[15:13]. When has GPIO been triggered, the status sta_jd_internal – MX-BF[4] will change. JD1
pin can used to detect two jacks and has two statuses for each jack. JD2 pin only used to detection one
jack.
Enable GPIO JD
MX-BF[4]
sta_gpio_jd GPIO1
MX-BB[15:13]
MX-BF[12]
sta_jd1_1 JD1
MX-BF[13]
sta_jd1_2
MX-BF[14]
sta_jd2 JD2
Figure 22. JD Source Selection

ALC5616
Datasheet
The jack detect function can be used to turn-on or turn-off the related output ports. When jack detect pin
is trigged, the selected output ports will turn-on or turn-off. For example on HP and LOUT auto switch
when JD is trigger.
Setting procedure:
1. Select JD source: use sta_jd1_1 as JD status. MX-BC[11:9] = 001’b
2. Set target behavior by JD active – HP & LOUT auto switch when JD is triggered.
MX-BB[11:10] = 11’b & MX-BB[3:2] = 10’b
3. When JD status is low, HP_OUT is mute and LOUT is un-mute.
When JD status is low go high, HP is un-mute and LOUT is mute.
Note: For HP and SPK jack switch function, driver need to turn-on DAC to HP path and DAC to LOUT
path first. The register control of MX-BB is only do mute/un-mute function for HP and SPK.

ALC5616
Datasheet
7.15. Power Management

ALC5616 detailed Power Management control registers are supported in MX-61h, 62h, 63h, 64h, 65h and
66h. Each particular block will only be active when each bit of each register is set to enable.
MX-61
I2S-1 Power DACL1 Power DACR1 Power ADCL Power ADCR Power
MX-62
AD Digital DA Digital
Filter Power Filter Power
MX-63
Analog MBias Analog Vref LOUT Mixer Headphone

Power Power Power Amp Power
MX-64
MIC BST1 MIC BST2 MICBIAS1 PLL JD1 JD2

Power Power Power Power Power Power
MX-65
OUTMIXR OUTMIXL RECMIXR RECMIXL

Power Power Power Power
MX-66
OUTVOLL OUTVOLR HPOVOLR HPOVOLL INRVOL INLVOL

Power Power Power Power Power Power
Figure 23. Power Management

ALC5616
Datasheet
8. Registers List
ALC5616 register map as shown as following and accessing unimplemented registers will return a 0.
8.1. Register Map

Table 16. Register Map
Type Name Description Register Address Reset State
Reset S/W Reset S/W Reset & Device ID MX-00h 0x0000’h
HPOUT Headphone Output Volume & Mute/Un-Mute MX-02h 0xC8C8’h
Line Output Control 1 MX-03h 0xC8C8’h
Line Output
Line Output Control 2 MX-05h 0x0000’h
MIC Input IN1/2 Mode and Gain Boost Control MX-0Dh 0x0000’h
Line Input INL/INR Volume Control MX-0Fh 0x0808’h
DACL1/R1 DACL1/R1 Digital Volume Control MX-19h 0xAFAF’h
Digital
ADCL/R-1 ADCL/R Digital Volume & Mute/Un-Mute Control MX-1Ch 0x2F2F’h
Gain/Volume
ADCL/R-2 ADC Boost Gain MX-1Eh 0x0000’h
ADC-1 ADC Stereo1 Digital Mixer Control MX-27h 0x7860’h
Digital Mixer ADC-2 ADC to DAC Digital Mixer Control MX-29h 0x8080’h
DAC-1 DAC Stereo Digital Mixer Control MX-2Ah 0x5252’h
RECMIXL-1 RECMIXL Gain Control MX-3Bh 0x0000’h
RECMIXL-2 RECMIXL Gain & Selection Control MX-3Ch 0x006F’h
Input Mixer
RECMIXR-1 RECMIXR Gain Control MX-3Dh 0x0000’h
RECMIXR-2 RECMIXR Gain & Selection Control MX-3Eh 0x006F’h
HPOMIX HPOMIX Gain & Selection Control MX-45h 0x6000’h
OUTMIXL-1 OUTMIXL Control 1 MX-4Dh 0x0000’h
OUTMIXL-2 OUTMIXL Control 2 MX-4Eh 0x0000’h
OUTMIXL-3 OUTMIXL Control 3 MX-4Fh 0x0279’h
Output Mixer
OUTMIXR-1 OUTMIXR Control 1 MX-50h 0x0000’h
LOUTMIX LOUTMIX Control MX-53h 0xF000’h
Management-
I2S & DAC & ADC & Power Control MX-61h 0x0000’h
1
Management-
Digital Filter Power Control MX-62h 0x0000’h
2
Management- VREF & MBias & LOUTMIX & HP & LDO Power
MX-63h 0x00C0’h
Power 3 Control
Management Management-
MICBST & MICBIAS & JD Power Control MX-64h 0x0000’h
4
Management-
OUTMIX & RECMIX Power Control MX-65h 0x0000’h
5
Management-
OUTVOL & HPOVOL & INVOL Power Control MX-66h 0x0000’h
6
PR Index PR Register Index MX-6Ah 0x0000’h
PR Register
PR Data PR Register Data Mx-6Ch 0x0000’h
I2S1 Port Ctrl I2S-1 Interface Control MX-70h 0x8000’h
Digital
ADC/DAC
Interface ADC/DAC Clock Control-1 MX-73h 0x1104’h
Clock-1

ALC5616
Datasheet
Type Name Description Register Address Reset State
ADC/DAC
ADC/DAC Clock Control-2 MX-74h 0x0C00’h
Clock-2
Global Clock Global Clock Control MX-80h 0x0000’h
Global Clock PLL-1 PLL Control-1 MX-81h 0x0000’h
PLL-2 PLL Control-2 MX-82h 0x0000’h
HP Amp Control 1 MX-8Eh 0x0004’h
HP Amp HP
HP Amp Control 2 MX-8Fh 0x1100’h
MICBIAS MICBIAS MICBIAS Control MX-93h 0x2000’h
JD JD Jack Detection Control MX-94h 0x0200’h
EQ-1 EQ Control-1 MX-B0h 0x2080’h
EQ-2 EQ Control-2 MX-B1h 0x0000’h
EQ-Parameter EQ Low Pass Filter – a1 PR-A0h 0x1C10’h
EQ-Parameter EQ Low Pass Filter – H0 PR-A1h 0x01F4’h
EQ-Parameter EQ Band Pass Filter 1 – a1 PR-A2h 0xC5E9’h
EQ-Parameter EQ Band Pass Filter 1 – a2 PR-A3h 0x1A98’h
EQ-Parameter EQ Band Pass Filter 1 – H0 PR-A4h 0x1D2C’h
EQ-Parameter EQ Band Pass Filter 2 – a1 PR-A5h 0xC882’h
EQ-Parameter EQ Band Pass Filter 2 – a2 PR-A6h 0x1C10’h
EQ-Parameter EQ Band Pass Filter 2 – H0 PR-A7h 0x01F4’h
EQ EQ-Parameter EQ Band Pass Filter 3 – a1 PR-A8h 0xE904’h
EQ-Parameter EQ Band Pass Filter 3 – a2 PR-A9h 0x1C10’h
EQ-Parameter EQ Band Pass Filter 3 – H0 PR-AAh 0x01F4’h
EQ-Parameter EQ Band Pass Filter 4 – a1 PR-ABh 0xE904’h
EQ-Parameter EQ Band Pass Filter 4 – a2 PR-ACh 0x1C10’h
EQ-Parameter EQ Band Pass Filter 4 – H0 PR-ADh 0x01F4’h
EQ-Parameter EQ High Pass Filter 1 – a1 PR-AEh 0x1C10’h
EQ-Parameter EQ High Pass Filter 1 – H0 PR-AFh 0x01F4’h
EQ-Parameter EQ High Pass Filter 2 – a1 PR-B0h 0x2000’h
EQ-Parameter EQ High Pass Filter 2 – a2 PR-B1h 0x0000’h
EQ-Parameter EQ High Pass Filter 2 – H0 PR-B2h 0x2000’h
DRC/AGC-1 DRC/AGC Control-1 MX-B4h 0x2206’h
DRC/AGC DRC/AGC-2 DRC/AGC Control-2 MX-B5h 0x1F00’h
DRC/AGC-3 DRC/AGC Control-3 MX-B6h 0x0000’h
JD-1 Jack Detection Control-1 MX-BBh 0x0000’h
Jack Detection
JD-2 Jack Detection Control-2 MX-BCh 0x0000’h
IRQ-1 IRQ Control-1 MX-BDh 0x0000’h
IRQ
IRQ-2 IRQ Control-2 MX-BEh 0x0000’h
Flag Status Status GPIO & Internal Status MX-BFh 0x0000’h
GPIO-1 GPIO Control-1 MX-C0h 0x0100’h
GPIO
GPIO-2 GPIO Control-2 MX-C1h 0x0000’h
Control-1 Wind Filter Control 1 MX-D3h 0xB320’h
Wind Filter
Control-2 Wind Filter Control 2 MX-D4h 0x0000’h
SVOL & ZCD SVOL & ZCD Soft Volume and ZCD Control MX-D9h 0x0809’h
General General Control 1 MX-FAh 0x0010’h
Control ADC/DAC RESET Control PR-3Dh 0x2800’h
Vendor ID ID Vendor ID MX-FEh 0x10EC’h

ALC5616
Datasheet
8.2. MX-00h: S/W Reset & Device ID

Default: 0020’h
Table 17. MX-00h: S/W Reset & Device ID

Port Name Bits Read/Write Reset State Description
Reserved 15:6 R 0020’h Reserved
Note: Writes to this register will reset all registers to their default values.
8.3. MX-02h: Headphone Output Control

Default: C8C8’h
Table 18. MX-02h: Headphone Output Control

Name Bits Read/Write Reset State Description
mu_hpo_l 15 R/W 1’h Mute Control for Left Headphone Output Port (HPOL)
0’b: Un-Mute
1’b: Mute
Mu_hpovoll_in 14 R/W 1’h Mute Control for Left Headphone Volume Channel
(HPOVOLL)
0’b: Un-Mute
1’b: Mute
vol_hpol 13:8 R/W 8’h Left Headphone Channel Volume Control (HPOVOLL) 
00’h: +12dB
…
08’h: 0dB
…
27’h: -46.5dB, with 1.5dB/step
mu_hpo_r 7 R/W 1’h Mute Control Right Headphone Output Port (HPOR)
0’b: Un-Mute
1’b: Mute
Mu_hpovolr_in 6 R/W 1’h Mute Control for Right Headphone Volume Channel
(HPOVOLR)
0’b: Un-Mute
1’b: Mute

ALC5616
Datasheet
Vol_hpor 5:0 R/W 8’h Right Headphone Channel Volume Control (HPOVOLR)
00’h: +12dB
…
08’h: 0dB
…
Volume Table
DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain
0 0 12 16 10 -12 32 20 -36
1 1 10.5 17 11 -13.5 33 21 -37.5
2 2 9 18 12 -15 34 22 -39
3 3 7.5 19 13 -16.5 35 23 -40.5
4 4 6 20 14 -18 36 24 -42
5 5 4.5 21 15 -19.5 37 25 -43.5
6 6 3 22 16 -21 38 26 -45
7 7 1.5 23 17 -22.5 39 27 -46.5
8 8 0 24 18 -24
9 9 -1.5 25 19 -25.5
10 A -3 26 1A -27
11 B -4.5 27 1B -28.5
12 C -6 28 1C -30
13 D -7.5 29 1D -31.5
14 E -9 30 1E -33
15 F -10.5 31 1F -34.5

ALC5616
Datasheet
8.4. MX-03h: LINE Output Control 1

Default: C8C8’h
Table 19. MX-03h: LINE Output Control 1

Mu_lout_l 15 R/W 1’h Mute Control for Left Line Output Port(LOUTL)
0’b: Un-Mute
1’b: Mute
Mu_outvoll_in 14 R/W 1’h Mute Control for Left Output Volume Channel (OUTVOLL)
0’b: Un-Mute
1’b: Mute
Vol_outl 13:8 R/W 08’h Left Output Volume Control (OUTVOLL) 
00’h: +12dB
…
08’h: 0dB
…
Mu_lout_r 7 R/W 1’h Mute Control for Right Line Output Port (LOUTR)
0’b: Un-Mute
1’b: Mute
Mu_outvolr_in 6 R/W 1’h Mute Control for Right Output Volume Channel
(OUTVOLR)
0’b: Un-Mute
1’b: Mute
Vol_outr 5:0 R/W 08’h Right Output Volume Control 
00’h: +12dB
…
08’h: 0dB
…
Volume Table
DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain
0 0 12 16 10 -12 32 20 -36
1 1 10.5 17 11 -13.5 33 21 -37.5
2 2 9 18 12 -15 34 22 -39
3 3 7.5 19 13 -16.5 35 23 -40.5
4 4 6 20 14 -18 36 24 -42
5 5 4.5 21 15 -19.5 37 25 -43.5
6 6 3 22 16 -21 38 26 -45
7 7 1.5 23 17 -22.5 39 27 -46.5
8 8 0 24 18 -24
9 9 -1.5 25 19 -25.5

ALC5616
Datasheet
10 A -3 26 1A -27
11 B -4.5 27 1B -28.5
12 C -6 28 1C -30
13 D -7.5 29 1D -31.5
14 E -9 30 1E -33
15 F -10.5 31 1F -34.5
8.5. MX-05h: LINE Output Control 2

Default: 0000’h
Table 20. MX-05h: LINE Output Control 2

En_dfo 15 R/W 0’h Enable Differential Line Output
0’b: Disable
1’b: Enable (LP / RN)
reserved 14:0 R 0’h Reserved
8.6. MX-0Dh: IN1/2 Input Control

Default: 0000’h
Table 21. MX-0Dh: IN1/2 Input Control

Sel_bst1 15:12 R/W 0’h IN1 Boost Control (BST1)
0000’b: Bypass
0001’b: +20dB
0010’b: +24dB
0011’b: +30dB
0100’b: +35dB
0101’b: +40dB
0110’b: +44dB
0111’b: +50dB
1000’b: +52dB
Others : Reserved

ALC5616
Datasheet
Sel_bst2 11:8 R/W 0’h IN2 Boost Control (BST2)
0000’b: Bypass
0001’b: +20dB
0010’b: +24dB
0011’b: +30dB
0100’b: +35dB
0101’b: +40dB
0110’b: +44dB
0111’b: +50dB
1000’b: +52dB
Others : Reserved
En_in1_df 7 R/W 0’h IN1 Input Mode Control
0’b: Single Ended Mode
1’b: Differential Mode
En_in2_df 6 R/W 0’h IN2 Input Mode Control
0’b: Single Ended Mode
1’b: Differential Mode
reserved 5:0 R/W 0’h Reserved
8.7. MX-0Fh: INL & INR Volume Control

Default: 0808’h
Table 22. MX-0Fh: INL & INR Volume Control

Vol_inl 12:8 R/W 8’h INL Channel Volume Control 
00’h: +12dB
…
08’h: 0dB
…
1F’h: -34.5dB, with 1.5dB/step
Vol_inr 4:0 R/W 8’h INR Channel Volume Control 
00’h: +12dB
…
08’h: 0dB
…
1F’h: -34.5dB, with 1.5dB/step
Volume Table:
DEC HEX Boost Gain DEC HEX Boost Gain

ALC5616
Datasheet
0 0 12 16 10 -12
1 1 10.5 17 11 -13.5
2 2 9 18 12 -15
3 3 7.5 19 13 -16.5
4 4 6 20 14 -18
5 5 4.5 21 15 -19.5
6 6 3 22 16 -21
7 7 1.5 23 17 -22.5
8 8 0 24 18 -24
9 9 -1.5 25 19 -25.5
10 A -3 26 1A -27
11 B -4.5 27 1B -28.5
12 C -6 28 1C -30
13 D -7.5 29 1D -31.5
14 E -9 30 1E -33
15 F -10.5 31 1F -34.5
8.8. MX-19h: DACL1/R1 Digital Volume

Default: AFAF’h
Table 23. MX-19h: DACL1/R1 Digital Volume

vol_dac1_l 15:8 R/W AF’h DAC1 Left Channel Digital Volume 
00’h: -65.625dB
…
AF’h: 0dB, with 0.375dB/Step
vol_dac1_r 7:0 R/W AF’h DAC1 Right Channel Digital Volume 
00’h: -65.625dB
…
AF’h: 0dB, with 0.375dB/Step
Volume Table:
DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain
0 0 -65.625 53 35 -45.75 106 6A -25.875 159 9F -6 212 D4
1 1 -65.25 54 36 -45.375 107 6B -25.5 160 A0 -5.625 213 D5
2 2 -64.875 55 37 -45 108 6C -25.125 161 A1 -5.25 214 D6

ALC5616
Datasheet
3 3 -64.5 56 38 -44.625 109 6D -24.75 162 A2 -4.875 215 D7

4 4 -64.125 57 39 -44.25 110 6E -24.375 163 A3 -4.5 216 D8
5 5 -63.75 58 3A -43.875 111 6F -24 164 A4 -4.125 217 D9
6 6 -63.375 59 3B -43.5 112 70 -23.625 165 A5 -3.75 218 DA
7 7 -63 60 3C -43.125 113 71 -23.25 166 A6 -3.375 219 DB
8 8 -62.625 61 3D -42.75 114 72 -22.875 167 A7 -3 220 DC
9 9 -62.25 62 3E -42.375 115 73 -22.5 168 A8 -2.625 221 DD
10 A -61.875 63 3F -42 116 74 -22.125 169 A9 -2.25 222 DE
11 B -61.5 64 40 -41.625 117 75 -21.75 170 AA -1.875 223 DF
12 C -61.125 65 41 -41.25 118 76 -21.375 171 AB -1.5 224 E0
13 D -60.75 66 42 -40.875 119 77 -21 172 AC -1.125 225 E1
14 E -60.375 67 43 -40.5 120 78 -20.625 173 AD -0.75 226 E2
15 F -60 68 44 -40.125 121 79 -20.25 174 AE -0.375 227 E3
16 10 -59.625 69 45 -39.75 122 7A -19.875 175 AF 0 228 E4
17 11 -59.25 70 46 -39.375 123 7B -19.5 176 B0 229 E5
18 12 -58.875 71 47 -39 124 7C -19.125 177 B1 230 E6
19 13 -58.5 72 48 -38.625 125 7D -18.75 178 B2 231 E7
20 14 -58.125 73 49 -38.25 126 7E -18.375 179 B3 232 E8
21 15 -57.75 74 4A -37.875 127 7F -18 180 B4 233 E9
22 16 -57.375 75 4B -37.5 128 80 -17.625 181 B5 234 EA
23 17 -57 76 4C -37.125 129 81 -17.25 182 B6 235 EB
24 18 -56.625 77 4D -36.75 130 82 -16.875 183 B7 236 EC
25 19 -56.25 78 4E -36.375 131 83 -16.5 184 B8 237 ED
26 1A -55.875 79 4F -36 132 84 -16.125 185 B9 238 EE
27 1B -55.5 80 50 -35.625 133 85 -15.75 186 BA 239 EF
28 1C -55.125 81 51 -35.25 134 86 -15.375 187 BB 240 F0
29 1D -54.75 82 52 -34.875 135 87 -15 188 BC 241 F1
30 1E -54.375 83 53 -34.5 136 88 -14.625 189 BD 242 F2
31 1F -54 84 54 -34.125 137 89 -14.25 190 BE 243 F3
32 20 -53.625 85 55 -33.75 138 8A -13.875 191 BF 244 F4
33 21 -53.25 86 56 -33.375 139 8B -13.5 192 C0 245 F5
34 22 -52.875 87 57 -33 140 8C -13.125 193 C1 246 F6
35 23 -52.5 88 58 -32.625 141 8D -12.75 194 C2 247 F7
36 24 -52.125 89 59 -32.25 142 8E -12.375 195 C3 248 F8
37 25 -51.75 90 5A -31.875 143 8F -12 196 C4 249 F9
38 26 -51.375 91 5B -31.5 144 90 -11.625 197 C5 250 FA

ALC5616
Datasheet
39 27 -51 92 5C -31.125 145 91 -11.25 198 C6 251 FB

40 28 -50.625 93 5D -30.75 146 92 -10.875 199 C7 252 FC
41 29 -50.25 94 5E -30.375 147 93 -10.5 200 C8 253 FD
42 2A -49.875 95 5F -30 148 94 -10.125 201 C9 254 FE
43 2B -49.5 96 60 -29.625 149 95 -9.75 202 CA 255 FF
44 2C -49.125 97 61 -29.25 150 96 -9.375 203 CB
45 2D -48.75 98 62 -28.875 151 97 -9 204 CC
46 2E -48.375 99 63 -28.5 152 98 -8.625 205 CD
47 2F -48 100 64 -28.125 153 99 -8.25 206 CE
48 30 -47.625 101 65 -27.75 154 9A -7.875 207 CF
49 31 -47.25 102 66 -27.375 155 9B -7.5 208 D0
50 32 -46.875 103 67 -27 156 9C -7.125 209 D1
51 33 -46.5 104 68 -26.625 157 9D -6.75 210 D2
52 34 -46.125 105 69 -26.25 158 9E -6.375 211 D3
8.9. MX-1Ch: Stereo1 ADC Digital Volume Control

Default: 2F2F’h
Table 24. MX-1Ch: Stereo1 ADC Digital Volume Control

Mu_adc_vol_l 15 R/W 0’h Mute Control for Stereo1 ADC Left Volume Channel
0’b: Un-Mute
1’b: Mute
Vol_adc1_l 14:8 R/W 2F’h Stereo1 ADC Left Channel Volume Control
00’h: -17.625dB
…
2F’h: 0dB
…
7F’h: +30dB, with 0.375dB/Step
Mu_adc_vol_r 7 R/W 0’h Mute Control for Stereo1 ADC Right Volume Channel
0’b: Un-Mute
1’b: Mute

ALC5616
Datasheet
Vol_adc1_r 6:0 R/W 2F’h Stereo1 ADC Right Channel Volume Control
00’h: -17.625dB
…
2F’h: 0dB
…
7F’h: +30dB, with 0.375dB/Step
Volume Table:
0 0 -17.625 26 1A -7.875 52 34 1.875 78 4E 11.625 104 68 21.375
1 1 -17.25 27 1B -7.5 53 35 2.25 79 4F 12 105 69 21.75
2 2 -16.875 28 1C -7.125 54 36 2.625 80 50 12.375 106 6A 22.125
3 3 -16.5 29 1D -6.75 55 37 3 81 51 12.75 107 6B 22.5
4 4 -16.125 30 1E -6.375 56 38 3.375 82 52 13.125 108 6C 22.875
5 5 -15.75 31 1F -6 57 39 3.75 83 53 13.5 109 6D 23.25
6 6 -15.375 32 20 -5.625 58 3A 4.125 84 54 13.875 110 6E 23.625
7 7 -15 33 21 -5.25 59 3B 4.5 85 55 14.25 111 6F 24
8 8 -14.625 34 22 -4.875 60 3C 4.875 86 56 14.625 112 70 24.375
9 9 -14.25 35 23 -4.5 61 3D 5.25 87 57 15 113 71 24.75
10 A -13.875 36 24 -4.125 62 3E 5.625 88 58 15.375 114 72 25.125
11 B -13.5 37 25 -3.75 63 3F 6 89 59 15.75 115 73 25.5
12 C -13.125 38 26 -3.375 64 40 6.375 90 5A 16.125 116 74 25.875
13 D -12.75 39 27 -3 65 41 6.75 91 5B 16.5 117 75 26.25
14 E -12.375 40 28 -2.625 66 42 7.125 92 5C 16.875 118 76 26.625
15 F -12 41 29 -2.25 67 43 7.5 93 5D 17.25 119 77 27
16 10 -11.625 42 2A -1.875 68 44 7.875 94 5E 17.625 120 78 27.375
17 11 -11.25 43 2B -1.5 69 45 8.25 95 5F 18 121 79 27.75
18 12 -10.875 44 2C -1.125 70 46 8.625 96 60 18.375 122 7A 28.125
19 13 -10.5 45 2D -0.75 71 47 9 97 61 18.75 123 7B 28.5
20 14 -10.125 46 2E -0.375 72 48 9.375 98 62 19.125 124 7C 28.875
21 15 -9.75 47 2F 0 73 49 9.75 99 63 19.5 125 7D 29.25
22 16 -9.375 48 30 0.375 74 4A 10.125 100 64 19.875 126 7E 29.625
23 17 -9 49 31 0.75 75 4B 10.5 101 65 20.25 127 7F 30
24 18 -8.625 50 32 1.125 76 4C 10.875 102 66 20.625
25 19 -8.25 51 33 1.5 77 4D 11.25 103 67 21

ALC5616
Datasheet
8.10. MX-1Eh: ADC Digital Boost Gain Control

Default: 0000’h
Table 25. MX-1Eh: ADC Digital Boost Gain Control

Ad_boost_gain_l 15:14 R/W 0’h ADC Left Channel Digital Boost Gain
00’b: 0dB
01’b: 12dB
10’b: 24dB
11’b: 36dB
Ad_boost_gain_r 13:12 R/W 0’h ADC Right Channel Digital Boost Gain
00’b: 0dB
01’b: 12dB
10’b: 24dB
11’b: 36dB
8.11. MX-27h: Stereo1 ADC Digital Mixer Control

Default: 7860’h
Table 26. MX-27h: Stereo1 ADC Digital Mixer Control

reserved 15 R 0’h reserved
mu_stereo1_adcl1 14 R/W 1’h Mute Control for Stereo1 ADC1 Left Channel
0’b: Un-Mute
1’b: Mute
mu_stereo1_adcr1 6 R/W 1’h Mute Control for Stereo1 ADC1 Right Channel
0’b: Un-Mute
1’b: Mute
reserved 4:0 R 20’h reserved

ALC5616
Datasheet
8.12. MX-29h: Stereo ADC to DAC Digital Mixer Control

Default: 8080’h
Table 27. MX-29h: Stereo ADC to DAC Digital Mixer Control

mu_stereo1_adc_mix 15 R/W 1’h Mute Control for Stereo1 ADC Left Channel to DAC
er_l 0’b: Un-Mute
1’b: Mute
mu_dac1_l 14 R/W 0’h Mute Control for I2S-1 to DAC Left Channel
0’b: Un-Mute
1’b: Mute
mu_stereo1_adc_mix 7 R/W 1’h Mute Control for Stereo1 ADC Right Channel to DAC
er_r 0’b: Un-Mute
1’b: Mute
mu_dac1_r 6 R/W 0’h Mute Control for I2S-1 to DAC Right Channel
0’b: Un-Mute
1’b: Mute
8.13. MX-2Ah: Stereo DAC Digital Mixer Control

Default: 5252’h
Table 28. MX-2Ah: Stereo DAC Digital Mixer Control

mu_stereo_dacl1_mix 14 R/W 1’h Mute Control for DACL1 to Stereo DAC Left Mixer
l 0’b: Un-Mute
1’b: Mute
gain_dacl1_to_stereo 13 R/W 0’h Gain Control for DACL1 to Stereo DAC Left Mixer
_l 0’b: 0dB
1’b: -6dB
Reserved 12:10 R 4’h reserved
mu_stereo_dacr1_mi 9 R/W 1’h Mute Control for DACR1 to Stereo DAC Left Mixer
xl 0’b: Un-Mute
1’b: Mute
gain_dacr1_to_stereo 8 R/W 0’h Gain Control for DACR1 to Stereo DAC Left Mixer
_l 0’b: 0dB
1’b: -6dB
Reserved 7 R 0’h reserved
mu_stereo_dacr1_mi 6 R/W 1’h Mute Control for DACR1 to Stereo DAC Right Mixer
xr 0’b: Un-Mute
1’b: Mute
gain_dacr1_to_stereo 5 R/W 0’h Gain Control for DACR1 to Stereo DAC Right Mixer
_r 0’b: 0dB
1’b: -6dB

ALC5616
Datasheet
mu_stereo_dacl1_mix 1 R/W 1’h Mute Control for DACL1 to Stereo DAC Right Mixer
r 0’b: Un-Mute
1’b: Mute
gain_dacl1_to_stereo 0 R/W 0’h Gain Control for DACL1 to Stereo DAC Right Mixer
_r 0’b: 0dB
1’b: -6dB
8.14. MX-3Bh: RECMIXL Control 1

Default: 0000’h
Table 29. MX-3Bh: RECMIXL Control 1

Gain_inl_recmixl 12:10 R/W 0’h Gain Control for INL to RECMIXL
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: Reserved
Gain_bst2_recmixl 3:1 R/W 0’h Gain Control for BST2 to RECMIXL
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: Reserved

ALC5616
Datasheet
8.15. MX-3Ch: RECMIXL Control 2

Default: 006F’h
Table 30. MX-3Ch: RECMIXL Control 2

Gain_bst1_recmixl 15:13 R/W 0’h Gain Control for BST1 to RECMIXL
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: Reserved
Mu_inl_rexmixl 5 R/W 1’h Mute Control for INL to RECMIXL
0’b: Un-Mute
1’b: Mute
Mu_bst2_recmixl 2 R/W 1’h Mute Control for BST2 to RECMIXL
0’b: Un-Mute
1’b: Mute
Mu_bst1_recmixl 1 R/W 1’h Mute Control for BST1 to RECMIXL
0’b: Un-Mute
1’b: Mute
Reserved 0 R 1’h Reserved
8.16. MX-3Dh: RECMIXR Control 1

Default: 0000’h
Table 31. MX-3Dh: RECMIXR Control 1

Gain_inr_recmixr 12:10 R/W 0’h Gain Control for INR to RECMIXR
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: Reserved

ALC5616
Datasheet
Gain_bst2_recmixr 3:1 R/W 0’h Gain Control for BST2 to RECMIXR
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: Reserved
reserved 0 R 0’h Reserved
8.17. MX-3Eh: RECMIXR Control 2

Default: 006F’h
Table 32. MX-3Eh: RECMIXR Control 2

Gain_bst1_recmixr 15:13 R/W 0’h Gain Control for BST1 to RECMIXR
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: Reserved
Mu_inr_rexmixr 5 R/W 1’h Mute Control for INR to RECMIXR
0’b: Un-Mute
1’b: Mute
Mu_bst2_recmixr 2 R/W 1’h Mute Control for BST2 to RECMIXR
0’b: Un-Mute
1’b: Mute
Mu_bst1_recmixr 1 R/W 1’h Mute Control for BST1 to RECMIXR
0’b: Un-Mute
1’b: Mute

ALC5616
Datasheet
8.18. MX-45h: HPOMIX Control

Default: 6000’h
Table 33. MX-45h: HPOMIX Control

mu_dac1_hpomix 14 R/W 1’h Mute Control for DAC1 to HPOMIX
0’b: Un-Mute
1’b: Mute
mu_hpovol_hpomix 13 R/W 1’h Mute Control for HPOVOL to HPOMIX
0’b: Un-Mute
1’b: Mute
Gain_hpomix 12 R/W 0’h Gain Control for HPOMIX
0’b: 0dB
1’b: -6dB
8.19. MX-4Dh: OUTMIXL Control 1

Default: 0000’h
Table 34. MX-4Dh: OUTMIXL Control 1

Gain_bst2_outmixl 12:10 R/W 0’h Gain Control for BST2 to OUTMIXL
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved
Gain_bst1_outmixl 9:7 R/W 0’h Gain Control for BST1 to OUTMIXL
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved

ALC5616
Datasheet
Gain_inl_outmixl 6:4 R/W 0’h Gain Control for INL to OUTMIXL
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved
Gain_recmixl_outmix 3:1 R/W 0’h Gain Control for RECMIXL to OUTMIXL
l 000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved
Reserved 0 R 0’h reserved
8.20. MX-4Eh: OUTMIXL Control 2

Default: 0000’h
Table 35. MX-4Eh: OUTMIXL Control 2

Gain_dacl1_outmixl 9:7 R/W 0’h Gain Control for DACL1 to OUTMIXL
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved
8.21. MX-4Fh: OUTMIXL Control 3

Default: 0279’h
Table 36. MX-4Fh: OUTMIXL Control 3


ALC5616
Datasheet
Mu_bst2_outmixl 6 R/W 1’h Mute Control for BST2 to OUTMIXL
0’b: Un-Mute
1’b: Mute
Mu_bst1_outmixl 5 R/W 1’h Mute Control for BST1 to OUTMIXL
0’b: Un-Mute
1’b: Mute
Mu_inl_outmixl 4 R/W 1’h Mute Control for INL to OUTMIXL
0’b: Un-Mute
1’b: Mute
Mu_recmixl_outmixl 3 R/W 1’h Mute Control for RECMIXL to OUTMIXL
0’b: Un-Mute
1’b: Mute
Mu_dacl1_outmixl 0 R/W 1’h Mute Control for DACL1 to OUTMIXL
0’b: Un-Mute
1’b: Mute
8.22. MX-50h: OUTMIXR Control 1

Default: 0000’h
Table 37. MX-50h: OUTMIXR Control 1

Gain_bst2_outmixr 12:10 R/W 0’h Gain Control for BST2 to OUTMIXR
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved
Gain_bst1_outmixr 9:7 R/W 0’h Gain Control for BST1 to OUTMIXR
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved

ALC5616
Datasheet
Gain_inr_outmixr 6:4 R/W 0’h Gain Control for INR to OUTMIXR
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved
Gain_recmixr_outmix 3:1 R/W 0’h Gain Control for RECMIXR to OUTMIXR
r 000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved

Default: 0000’h
Table 38 MX-51h: OUTMIXR Control 2

Gain_dacr1_outmixr 9:7 R/W 0’h Gain Control for DACR1 to OUTMIXR
000’b: 0dB
001’b: -3dB
010’b: -6dB
011’b: -9dB
100’b: -12dB
101’b: -15dB
110’b: -18dB
Others: reserved

Default: 0279’h
Table 39. MX-52h: OUTMIXR Control 3


ALC5616
Datasheet
Mu_bst2_outmixr 6 R/W 1’h Mute Control for BST2 to OUTMIXR
0’b: Un-Mute
1’b: Mute
Mu_bst1_outmixr 5 R/W 1’h Mute Control for BST1 to OUTMIXR
0’b: Un-Mute
1’b: Mute
Mu_inr_outmixr 4 R/W 1’h Mute Control for INR to OUTMIXR
0’b: Un-Mute
1’b: Mute
Mu_recmixr_outmixr 3 R/W 1’h Mute Control for RECMIXR to OUTMIXR
0’b: Un-Mute
1’b: Mute
Mu_dacr1_outmixr 0 R/W 1’h Mute Control for DACR1 to OUTMIXR
0’b: Un-Mute
1’b: Mute
8.25. MX-53h: LOUTMIX Control

Default: F000’h
Table 40 MX-53h: LOUTMIX Control

Mu_dacl1_lout 15 R/W 1’h Mute Control for DACL1 to LOUTMIX
0’b: Un-Mute
1’b: Mute
Mu_dacr1_lout 14 R/W 1’h Mute Control for DACR1 to LOUTMIX
0’b: Un-Mute
1’b: Mute
Mu_outvoll_lout 13 R/W 1’h Mute Control for OUTVOLL to LOUTMIX
0’b: Un-Mute
1’b: Mute
Mu_outvolr_lout 12 R/W 1’h Mute Control for OUTVOLR to LOUTMIX
0’b: Un-Mute
1’b: Mute
Gain_lout 11 R/W 0’h Gain Control for LOUTMIX
0’b: 0dB
1’b: -6dB

ALC5616
Datasheet
8.26. MX-61h: Power Management Control 1

Default: 0000’h
Table 41. MX-61h: Power Management Control 1

En_i2s1 15 R/W 0’h I2S1 Digital Interface Power Control
0’b: Power Down
1’b: Power On
Pow_dac_l_1 12 R/W 0’h Analog DACL1 Power Control
0’b: Power Down
1’b: Power On
Pow_dac_r_1 11 R/W 0’h Analog DACR1 Power Control
0’b: Power Down
1’b: Power On
Pow_adc_l 2 R/W 0’h Analog ADCL Power Control
0’b: Power Down
1’b: Power On
Pow_adc_r 1 R/W 0’h Analog ADCR Power Control
0’b: Power Down
1’b: Power On

Default: 0000’h

Pow_adc_stereo1_filt 15 R/W 0’h Stereo1 ADC Digital Filter Power Control
er 0’b: Power Down
1’b: Power On
Pow_dac_stereo1_filt 11 R/W 0’h Stereo1 DAC Digital Filter Power Control
er 0’b: Power Down
1’b: Power On

ALC5616
Datasheet

Default: 00C0’h

Pow_vref1 15 R/W 0’h VREF1 Power Control
0’b: Power Down
1’b: Power On
En_fastb1 14 R/W 0’h VREF1 Fast Mode Control
0’b: Fast VREF
1’b: Slow VREF, (For good analog performance)
Pow_main_bias 13 R/W 0’h MBIAS Power Control
0’b: Power Down
1’b: Power On
Pow_lout 12 R/W 0’h LOUTMIX Power Control
0’b: Power Down
1’b: Power On
Pow_bg_bias 11 R/W 0’h MBIAS Bandgap Power Control
0’b: Power Down
1’b: Power On
En_l_hp 7 R/W 1’h Left Headphone Amp Power Control
0’b: Power Down
1’b: Power On
En_r_hp 6 R/W 1’h Right Headphone Amp Power Control
0’b: Power Down
1’b: Power On
En_amp_hp 5 R/W 0’h Improve HP Amp Driving
0’b: Disable
1’b: Enable
Pow_vref2 4 R/W 0’h VREF2 Power Control
0’b: Power Down
1’b: Power On
En_fastb2 3 R/W 0’h VREF2 Fast Mode Control
0’b: Fast VREF
1’b: Slow VREF, (For good analog performance)
Ldo_dvo 1:0 R/W 0’h LDO Output Control
00’b: 1.1V
01’b: 1.2V
10’b: 1.3V
11’b: 1.4V

ALC5616
Datasheet

Default: 0000’h

Pow_bst1 15 R/W 0’h MIC BST1 Power Control
0’b: Power Down
1’b: Power On
Pow_bst2 14 R/W 0’h MIC BST2 Power Control
0’b: Power Down
1’b: Power On
Pow_micbias1 11 R/W 0’h MICBIAS1 Power Control
0’b: Power Down
1’b: Power On
reserved 10 R/W 0’h reserved
Pow_pll 9 R/W 0’h PLL Power Control
0’b: Power Down
1’b: Power On
Pow_bst1_op2 5 R/W 0’h MIC1 SE Mode Control
0’b: For differential mode
1’b: For single-end mode
Pow_bst2_op2 4 R/W 0’h MIC2 SE Mode Control
0’b: For differential mode
1’b: For single-end mode or line-input mode
Pow_jd_m 2 R/W 0’h JD_Multilevel Power Control
0’b: Power down
1’b: Power on
Pow_jd2 1 R/W 0’h JD2 Power Control
0’b: Power down
1’b: Power on

Default: 0000’h

Pow_outmixl 15 R/W 0’h OUTMIXL Power Control
0’b: Power Down
1’b: Power On
Pow_outmixr 14 R/W 0’h OUTMIXR Power Control
0’b: Power Down
1’b: Power On

ALC5616
Datasheet
Pow_recmixl 11 R/W 0’h RECMIXL Power Control
0’b: Power Down
1’b: Power On
Pow_recmixr 10 R/W 0’h RECMIXR Power Control
0’b: Power Down
1’b: Power On

Default: 0000’h

Pow_outvoll 13 R/W 0’h OUTVOLL Power Control
0’b: Power Down
1’b: Power On
Pow_outvolr 12 R/W 0’h OUTVOLR Power Control
0’b: Power Down
1’b: Power On
Pow_hpovoll 11 R/W 0’h HPOVOLL Power Control
0’b: Power Down
1’b: Power On
Pow_hpovolr 10 R/W 0’h HPOVOLR Power Control
0’b: Power Down
1’b: Power On
Pow_inlvol 9 R/W 0’h INLVOL Power Control
0’b: Power Down
1’b: Power On
Pow_inrvol 8 R/W 0’h INRVOL Power Control
0’b: Power Down
1’b: Power On

ALC5616
Datasheet
8.32. MX-6Ah: Private Register Index

Default: 0000’h
Table 47. MX-6Ah: Private Register Index

Pr_index 7:0 R/W 0’h PR Register Index
8.33. MX-6Ch: Private Register Data

Default: 0000’h
Table 48. MX-6Ch: Private Register Data

Pr_data 15:0 R/W 0’h PR Register Data
8.34. MX-70h: I2S1 Digital Interface Control

Default: 8000’h
Table 49. MX-70h: I2S1 Digital Interface Control

Sel_i2s1_ms 15 R/W 1’h I2S1 Digital Interface Mode Control
0’b: Master Mode
1’b: Slave Mode
en_i2s1_out_comp 11:10 R/W 0’h I2S1 Output Data Compress (For ADCDAT1 Output)
00’b: OFF
01’b: µ law
10’b: A law
11’b: Reserved
en_i2s1_in_comp 9:8 R/W 0’h I2S1 Input Data Compress (For DACDAT1 Input)
00’b: OFF
01’b: µ law
10’b: A law
11’b: Reserved
Inv_i2s1_bclk 7 R/W 0’h I2S1 BCLK Polarity Control
0’b: Normal
1’b: Invert
sel_i2s1_len 3:2 R/W 0’h I2S1 Data Length Selection
00’b: 16 bits
01’b: 20 bits
10’b: 24 bits
11’b: 8 bits

ALC5616
Datasheet
sel_i2s1_format 1:0 R/W 0’h I2S1 PCM Data Format Selection
00’b: I2S format
01’b: Left justified
10’b: PCM Mode A (LRCK One Plus at Master Mode)
11’b: PCM Mode B (LRCK One Plus at Master Mode)
8.35. MX-73h: ADC/DAC Clock Control 1

Default: 1104’h
Table 50. MX-73h: ADC/DAC Clock Control 1

sel_i2s_pre_div1 14:12 R/W 1’h I2S Clock Pre-Divider 1
000’b: ÷ 1
001’b: ÷ 2
010’b: ÷ 3
011’b: ÷ 4
100’b: ÷ 6
101’b: ÷ 8
110’b: ÷ 12
111’b: ÷ 16
sel_dac_osr 3:2 R/W 1’h Stereo DAC Over Sample Rate Select
00’b: 128Fs
01’b: 64Fs
10’b: 32Fs
11’b: 128Fs/3
sel_adc_osr 1:0 R/W 0’h Stereo ADC Over Sample Rate Select
00’b: 128Fs
01’b: 64Fs
10’b: 32Fs
11’b: 128Fs/3
8.36. MX-74h: ADC/DAC Clock Control 2

Default: 0C00’h
Table 51. MX-74h: ADC/DAC Clock Control 2

Dahpf_en 11 R/W 1’h Stereo1 DAC Filter HPF Power Control
0’b: Disable
1’b: Enable

ALC5616
Datasheet
adhpf_en 10 R/W 1’h Stereo1 ADC Filter HPF Power Control
0’b: Disable
1’b: Enable
8.37. MX-80h: Global Clock Control

Default: 0000’h
Table 52. MX-80h: Global Clock Control

sel_sysclk1 15:14 R/W 0’h System Clock Source MUX Control
00’b: MCLK
01’b: PLL
10’b: Reserved
11’b: Reserved
sel_pll_sour 13:12 R/W 0’h PLL Source Selection
00’b: From MCLK
01’b: From BCLK1
10’b: Reserved
11’b: Reserved
sel_pll_pre_div 3 R/W 0’h PLL Pre-Divider
0’b: ÷ 1
1’b: ÷ 2
8.38. MX-81h: PLL Control 1

Default: 0000’h
Table 53. MX-81h: PLL Control 1

Pll_n_code 15:7 R/W 0’h PLL N[8:0] Code
000000000’b: Div 2
000000001’b: Div 3
…
111111111’b: Div 513
Pll_k_code 4:0 R/W 0’h PLL K[4:0] Code
00000’b: Div 2
00001’b: Div 3
…
11111’b: Div 33

ALC5616
Datasheet
8.39. MX-82h: PLL Control 2

Default: 0000’h
Table 54. MX-82h: PLL Control 2

Pll_m_code 15:12 R/W 0’h PLL M[3:0] Code
0000’b: Div 2
0001’b: Div 3
…
1111’b: Div 17
Pll_m_bypass 11 R/W 0’h Bypass PLL M Code
0’b : No bypass
1’b : Bypass
8.40. MX-8Eh: HP Amp Control 1

Default: 0004’h
Table 55. MX-8Eh: HP Amp Control 1

Smttrig_hp 15 R/W 0’h Enable Softgen Trigger for Soft Mute Depop
0’b: Disable
1’b: Enable
En_smt_l_hp 9 R/W 0’h Enable HP_L Mute/Un-Mute Depop
0’b: Disbale
1’b: Enable
En_smt_r_hp 8 R/W 0’h Enable HP_R Mute/Un-Mute Depop
0’b: Disbale
1’b: Enable
Pdn_hp 7 R/W 0’h Capless Depop Power Down Control
0’b: Disbale
1’b: Enable
Softgen_rstn 6 R/W 0’h Reset Softgen to Initialize SOFTP=1
0’b: Disbale
1’b: Reset
Softgen_rstp 5 R/W 0’h Reset Softgen to Initialize SOFTP=0
0’b: Disbale
1’b: Reset
En_out_hp 4 R/W 0’h Enable Headphone Output
0’b: Disable
1’b: Enable
Pow_pump_hp 3 R/W 0’h Charge Pump Power Control
0’b: Power Down
1’b: Power On
En_softgen_hp 2 R/W 1’h Power On Soft Generator
0’b: Power down
1’b: Power on

ALC5616
Datasheet
reserved 1 R/W 0’h Reserved
Pow_capless 0 R/W 0’h HP Amp All Power On Control
0’b: Power Down
1’b: Power On
8.41. MX-8Fh: HP Amp Control 2

Default: 1100’h
Table 56. MX-8Fh: HP Amp Control 2

Depop_mode_hp 13 R/W 0’h Select HP Depop Mode
0’b: Depop mode 1
1’b: Depop mode 2
En_depop_mode1 6 R/W 0’h HP Depop Mode 1 Control
0’b: Disbale
1’b: Enable
8.42. MX-93h: MICBIAS Control

Default: 2000’h
Table 57. MX-93h: MICBIAS Control

Sel_micbias1 15 R/W 0’h MICBIAS1 Output Voltage Control
0’b: 0.9 * MICVDD
1’b: 0.75 * MICVDD
Pow_mic1_ovcd 11 R/W 0’h MICBIAS1 Short Current Detector Control
0’b: Disable
1’b: Enable
Mic1_ovcd_th_sel 10:9 R/W 0’h MICBIAS1 Short Current Detector Threshold
00’b: 600uA
01’b: 1500uA
1x’b: 2000uA
Note: tolerance is 200uA
reserved 8:0 R/W 0’h reserved

ALC5616
Datasheet
8.43. MX-94h: Jack Detection Control

Default: 0200’h
Table 58. MX-94h: Jack Detection Control

Jad_cmp 13 R 0’h JD2 Status
Pullup_jd 11 R/W 0’h JD2 Pull Up Control
0’b: Off
1’b: Pull up
Pulldown_jd 10 R/W 0’h JD2 Pull Down Control
0’b: Off
1’b: Pull down
Reserved 9:7 R/W 4’h Reserved
Jd_m_cmp 6:4 R 0’h JD_M Output
Pullup_jd_m 3 R/W 0’h JD_M Pull Up Control
0’b: Off
1’b: Pull up
Pulldown_jd_m 2 R/W 0’h JD_M Pull Down Control
0’b: Off
1’b: Pull down
8.44. MX-B0h: EQ Control 1

Default: 2080’h
Table 59. MX-B0h: EQ Control 1

eq_sour 15 R/W 0’h EQ Path Control
0’b: DAC path
1’b: ADC path
eq_para_update 14 R/W 0’h EQ Parameter Update Control
0’b: No action
1’b: Update parameter
sta_hpf2 6 R 0’h EQ High Pass Filter (HPF2) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
sta_hpf1 5 R 0’h EQ High Pass Filter (HPF1) Status.
0’b: Normal
1’b: Overflow.

ALC5616
Datasheet
sta_bpf4 4 R 0’h EQ Band-4 (BP4) Status.
0’b: Normal
1’b: Overflow.
0’b: Normal
1’b: Overflow.
0’b: Normal
1’b: Overflow.
0’b: Normal
1’b: Overflow.
sta_lpf 0 R 0’h EQ Low Pass Filter (LPF) Status.
0’b: Normal
1’b: Overflow.
8.45. MX-B1h: EQ Control 2

Default: 0000’h
Table 60. MX-B1h: EQ Control 2

reg_typ_hpf_en 8 R/W 0’h EQ High Pass Filter1 Mode Control
0’b: High frequency shelving filter
1’b: 1st order Butterworth HPF (-20dB per decade)
reg_typ_lpf_en 7 R/W 0’h EQ Low Pass Filter Mode Control
0’b: Low frequency shelving filter
1’b: 1st order Butterworth LPF (-20dB per decade)
en_hpf2 6 R/W 0’h EQ High Pass 2nd Butterworth Filter (HPF) Control.
0’b: Disabled (bypass) and reset
1’b: Enabled
en_hpf1 5 R/W 0’h EQ High Pass Filter (HPF) Control.
0’b: Disabled (bypass) and reset
1’b: Enabled
en_bpf4 4 R/W 0’h EQ Band-4 (BP4) shelving Filter Control.
0’b: Disabled and reset
1’b: Enabled.

ALC5616
Datasheet
1’b: Enabled.
1’b: Enabled.
1’b: Enabled.
en_lpf 0 R/W 0’h EQ Low Pass Filter (LPF) Filter Control.
1’b: Enabled.
8.46. MX-B4h: DRC/AGC Control 1

Default: 2206’h
Table 61. MX-B4h: DRC/AGC Control 1

sel_drc_agc 15:14 R/W 0’h DRC/AGC Enable
00’b: Disable DRC/AGC
01’b: Enable DRC to DAC Path
10’b: Disable DRC/AGC
11’b: Enable AGC to ADC Path
update_drc_agc_para 13 R 1’h Update DRC/AGC Parameter
m Write 1’b to update all DRC/AGC parameter
sel_drc_agc_atk 12:8 R/W 2’h Select DRC/AGC attack rate (0.375dB/TU)
00’h: 83 uSec
01’h: 0.167 mSec
…
10’h: 5.46 Sec
Others: Reserved

ALC5616
Datasheet
Drc_agc_rate_sel 7:5 R/W 0’h DRC/AGC Rate Control for Sample Rate Change
001’b: 48kHz
010’b: 96kHz
011’b: 192kHz
101’b: 44.1kHz
110’b: 88.2kHz
111’b: 176.4kHz
Others: Reserved
sel_rc_rate 4:0 R/W 6’h Select DRC/AGC recovery rate (0.375dB/TU)
00’h: 83 uSec
01’h: 0.167 mSec
…
10’h: 5.46 Sec
Others: Reserved
 attack time=(4*2^n)/Sample_Rate, n = MX-B4[12:8], default=0.33mS
 recovery time=(4*2^n)/Sample_Rate, n = MX-B4[4:0], default=5.3mS
 When change I2S’s sample rate, the DRC/AGC rate control is need to be changed same with I2S’s sample rate. When
change the DRC/AGC rate, the parameter of DRC/AGC isn’t need be modified.
When I2S’s sample rate is below 48kHz, that need to set the DRC/AGC rate to 48kHz and re-calculate the DRC/AGC’s
parameter by I2S’s sample rate.

Default: 1F00’h

sel_drc_agc_post_bst 13:8 R/W 1f’h DRC/AGC Digital Post-Boost Gain (0.375dB/step)

00’h= -11.625dB
………………..
3F’h= 12dB
Others: Reserved
En_drc_agc_compres 7 R/W 0’h DRC/AGC Compression Function Control
s 0’b: Disable
1’b: Enable

ALC5616
Datasheet
Sel_ratio 6:5 R/W 0’h DRC/AGC Compression Ratio Selection
00’b: 1:1
01’b: 1:2
10’b: 1:4
11’b: 1:8
sel_drc/agc_pre_bst 4:0 R/W 0’h DRC/AGC Digital Pre-Boost Gain (1.5dB/step)
00’h= 0dB
01’h= 1.5dB
02’h= 3dB
03’h= 4.5dB
………………..
13’h= 28.5dBFS
Others: Reserved
Gain table:
0 0 -11.625 16 10 -5.625 32 20 0.375 48 30 6.375 64 40
1 1 -11.25 17 11 -5.25 33 21 0.75 49 31 6.75 65 41
2 2 -10.875 18 12 -4.875 34 22 1.125 50 32 7.125 66 42
3 3 -10.5 19 13 -4.5 35 23 1.5 51 33 7.5 67 43
4 4 -10.125 20 14 -4.125 36 24 1.875 52 34 7.875 68 44
5 5 -9.75 21 15 -3.75 37 25 2.25 53 35 8.25 69 45
6 6 -9.375 22 16 -3.375 38 26 2.625 54 36 8.625 70 46
7 7 -9 23 17 -3 39 27 3 55 37 9 71 47
8 8 -8.625 24 18 -2.625 40 28 3.375 56 38 9.375 72 48
9 9 -8.25 25 19 -2.25 41 29 3.75 57 39 9.75 73 49
10 A -7.875 26 1A -1.875 42 2A 4.125 58 3A 10.125 74 4A
11 B -7.5 27 1B -1.5 43 2B 4.5 59 3B 10.5 75 4B
12 C -7.125 28 1C -1.125 44 2C 4.875 60 3C 10.875 76 4C
13 D -6.75 29 1D -0.75 45 2D 5.25 61 3D 11.25
14 E -6.375 30 1E -0.375 46 2E 5.625 62 3E 11.625
15 F -6 31 1F 0 47 2F 6 63 3F 12

DEC HEX Boost Gain DEC HEX Boost Gain
0 0 0 16 10 24
1 1 1.5 17 11 25.5
2 2 3 18 12 27

ALC5616
Datasheet
3 3 4.5 19 13 28.5
4 4 6 20 14
5 5 7.5 21 15
6 6 9 22 16
7 7 10.5 23 17
8 8 12 24 18
9 9 13.5 25 19
10 A 15 26 1A
11 B 16.5 27 1B
12 C 18 28 1C
13 D 19.5 29 1D
14 E 21 30 1E
15 F 22.5 31 1F

Default: 0000’h

Noise_gate_boost 15:12 R/W 0’h Select Compensation Gain When Signal is Below Noise Gate
0’h: 0dB
1’h: 3dB
2’h: 6dB
…
E’h: 42dB
F’h: 45dB
sel_drc_agc_thmax 11:7 R/W 0’h DRC/AGC Limiter Level (1.5dB/step)
00’h= 0dBFS
01’h= -1.5dBFS
02’h= -3dBFS
03’h= -4.5dBFS
…
1F’h= -46.5dBFS
en_drc_agc_noise_ga 6 R/W 0’h Enable Noise Gate function
te 0’b: Diaable
1’b: Enable

ALC5616
Datasheet
En_drc_agc_noise_ga 5 R/W 0’h Enable Noise Gate Hold Data Function
te_hold 0’b: Disable
1’b: Enable
sel_drc_agc_noise_th 4:0 R/W 0’h Noise Gate Threshold (-1.5dB/step)
00’h: -36dBFS
01’h: -375dBFS
………………..
1F’h: -82.5 dBFS
8.49. MX-BBh: Jack Detection Control 1

Default: 0000’h
Table 64. MX-BBh: Jack Detection Control 1

sel_gpio_jd 15:13 R/W 0’h Jack Detect Selection
000’b: OFF
001’b: GPIO1
Others: Reserved
en_jd_hpo 11 R/W 0’h Enable Jack Detect Trigger HPOUT
0’b: Disable
1’b: Enable
polarity_jd_tri_hpo 10 R/W 0’h Select Jack Detect Polarity Trigger HPOUT
0’b: Low trigger
1’b: High trigger
en_jd_lout 3 R/W 0’h Enable Jack Detect Trigger LOUT
0’b: Disable
1’b: Enable
polarity_jd_tri_lout 2 R/W 0’h Select Jack Detect Polarity Trigger LOUT
0’b: Low trigger
1’b: High trigger
reserved 1:0 R/W 0’h reserved
8.50. MX-BCh: Jack Detection Control 2

Default: 0000’h
Table 65. MX-BCh: Jack Detection Control 2


ALC5616
Datasheet
Sel_jd_trigger 11:9 R/W 0’h JD Trigger Source Selection
000’b: From sta_gpio_jd
001’b: From sta_jd1_1
010’b: From sta_jd1_2
011’b: From sta_jd2
Others: Reserved
8.51. MX-BDh: IRQ Control 1

Default: 0000’h
Table 66. MX-BDh: IRQ Control 1

en_irq_gpio_jd 15 R/W 0’h IRQ Output Source Configure of GPIO Jack Detection Status
0’b: Disable
1’b: Enable
en_gpio_jd_sticky 13 R/W 0’h Sticky Control for GPIO Jack Detect
0’b: Disable
1’b: Enable
inv_gpio_jd 11 R/W 0’h GPIO Jack Detection Status Polarity
0’b: Normal
1’b: Output Invert
en_irq_jd1_1 9 R/W 0’h IRQ Output Source Configure of JD1_1 Jack Detection
Status
0’b: Disable
1’b: Enable
en_jd1_1_sticky 8 R/W 0’h Sticky Control for JD1_1 Jack Detect
0’b: Disable
1’b: Enable
inv_jd1_1 7 R/W 0’h JD1_1 Jack Detection Status Polarity
0’b: Normal
en_irq_jd1_2 6 R/W 0’h IRQ Output Source Configure of JD1_2 Jack Detection
Status
0’b: Disable
1’b: Enable
en_jd1_2_sticky 5 R/W 0’h Sticky Control for JD1_2 Jack Detect
0’b: Disable
1’b: Enable
inv_jd1_2 4 R/W 0’h JD1_2 Jack Detection Status Polarity
0’b: Normal

ALC5616
Datasheet
en_irq_jd2 3 R/W 0’h IRQ Output Source Configure of JD2 Jack Detection Status
0’b: Disable
1’b: Enable
en_jd2_sticky 2 R/W 0’h Sticky Control for JD2 Jack Detect
0’b: Disable
1’b: Enable
inv_jd2 1 R/W 0’h JD2 Jack Detection Status Polarity
0’b: Normal
8.52. MX-BEh: IRQ Control 2

Default: 0000’h
Table 67. MX-BEh: IRQ Control 2

en_irq_micbias1_ovc 15 R/W 0’h IRQ Output Source Configure of MICBIAS1 Over Current
d Status
0’b: Disable
1’b: Enable
en_micbias1_ovcd_st 11 R/W 0’h Sticky Control for MICBIAS1 Over Current
icky 0’b: Disable
1’b: Enable
inv_micbias1_ovcd 7 R/W 0’h MICBIAS1 over current status polarity
0’b: Normal
Ovc_micbias1 3 R 0’h MICBIAS1 Over Current Status
Read: return status of each status pin
Write: Write ‘0’ to clear stick bit
8.53. MX-BFh: GPIO and Internal Status

Default: 0000’h
Table 68. MX-BFh: GPIO and Internal Status

sta_jd2 14 R 0’h JD2 Pin Status
Read: return status of JD2 pin

ALC5616
Datasheet
sta_jd1_2 13 R 0’h JD1 Pin Status
Read: return status of JD1_2
sta_jd1_1 12 R 0’h JD1 Pin Status
Read: return status of JD1_1
sta_gpio1 8 R 0’h GPIO1 Pin Status
Read: return status of GPIO1 pin
sta_gpio_jd 4 R 0’h GPIO_JD Status
Read: Return status of Jack Detect Select output
8.54. MX-C0h: GPIO Control 1

Default: 0100’h
Table 69. MX-C0h: GPIO Control 1

sel_gpio1_type 15 R/W 0’h GPIO1 Pin Function Select
0’b: GPIO1
1’b: IRQ output
8.55. MX-C1h: GPIO Control 2

Default: 0000’h
Table 70. MX-C1h: GPIO Control 2

sel_gpio1 2 R/W 0’h GPIO1 Pin Configuration
0’b: Input
1’b: Output
sel_gpio1_logic 1 R/W 0’h GPIO1 Output Pin Control
0’b: Drive Low
1’b: Drive High
inv_gpio1 0 R/W 0’h GPIO1 Pin Polarity
0’b: Normal

ALC5616
Datasheet
8.56. MX-D3h: Wind Filter Control 1

Default: B320’h
Table 71. MX-D3h: Wind Filter Control 1

adj_hpf_2nd_en 15 R/W 1’h Enable Adjustable 2nd Wind Filter
0'b : Disable (bypass mode)
1'b : Enable
adj_hpf_coef_l_sel 14:12 R/W 3’h Left Channel Coefficient Sample Rate Selection
000'b: 8K/12K/16K Hz
001'b: 24K/32K Hz
010'b: 48K/44.1K Hz
011'b: 96K/88.2K Hz
100'b: 192K/176.4K Hz
Others: Reserved
adj_hpf_coef_r_sel 10:8 R/W 2’h Right Channel Coefficient Sample Rate Selection
000'b: 8K/12K/16K Hz
001'b: 24K/32K Hz
010'b: 48K/44.1K Hz
011'b: 96K/88.2K Hz
100'b: 192K/176.4K Hz
Others: Reserved
8.57. MX-D4h: Wind Filter Control 2

Default: 0000’h
Table 72. MX-D3h: Wind Filter Control 2

adj_hpf_coef_l_num 13:8 R/W 0’h Left Channel Coefficient Fine Parameter Selection
(0 ~ 63)
adj_hpf_coef_r_num 5:0 R/W 0’h Right Channel Coefficient Fine Parameter Selection
(0 ~ 63)

ALC5616
Datasheet
8.58. MX-D9h: Soft Volume & ZCD Control

Default: 0809’h
Table 73. MX-D9h: Soft Volume & ZCD Control

en_softvol 15 R/W 0’h Digital Soft Volume Delay Control
0’b: Disable
1’b: Enable
en_o_svol 13 R/W 0’h OUTVOLL/R Soft Volume Delay Control
0’b: Disable
1’b: Enable
en_hpo_svol 12 R/W 0’h HPOVOLL/R Soft Volume Delay Control
0’b: Disable
1’b: Enable
en_zcd_digital 11 R/W 1’h Digital Volume Zero Crossing Detection Control
0’b: Disable
1’b: Enable
pow_zcd 10 R/W 0’h Power On Zero Crossing
0’b: Power Down
1’b: Power On
En_zcd_outmixr 7 R/W 0’h OUTMIXR Mute/Un-Mute ZCD Control
0’b: Disable
1’b: Enable
En_zcd_outmixl 6 R/W 0’h OUTMIXL Mute/Un-Mute ZCD Control
0’b: Disable
1’b: Enable
En_zcd_recmixr 5 R/W 0’h RECMIXR Mute/Un-Mute ZCD Control
0’b: Disable
1’b: Enable
En_zcd_recmixl 4 R/W 0’h RECMIXL Mute/Un-Mute ZCD Control
0’b: Disable
1’b: Enable
sel_svol 3:0 R/W 9’h Soft Volume Change Delay Time
0000: 1 SVSYNC
0001: 2 SVSYNC
0010: 4 SVSYNC
0011: 8 SVSYNC
0100: 16 SVSYNC
0101: 32 SVSYNC
0110: 64 SVSYNC
0111: 128 SVSYNC
1000: 256 SVSYNC
1001: 512 SVSYNC
1010: 1024 SVSYNC
Others: Reserved
Note: SVSYNC=1/Fs, Step:-1.5dBFS

ALC5616
Datasheet
8.59. MX-FAh: General Control 1

Default: 0010’h
Table 74. MX-FAh: General Control 1

En_detect_clk_sys 3 R/W 0’h Enable MCLK Detection and Auto Switch to Internal Clock
0’b: Disable
1’b: Enable
Digital_gate_ctrl 0’h R/W 0’h MCLK Clock Gating Control
0’b: Gating input clock
0’b: Enable input clock
8.60. PR-3Dh: ADC/DAC RESET Control

Default: 2000’h
Table 75. PR-3Dh: ADC/DAC RESET Control

En_ckgen_adc 12 R/W 0’h Enable ADC Clock Generator
0’b: Disable
1’b: Enable
Reserved 11 R/W 0’h Reserved
Ckxen_dac 10 R/W 0’h Enable DAC Clock1 Generator
0’b: Disable
1’b: Enable
En_ckgen_dac 9 R/W 0’h Enable DAC Clock2 Generator
0’b: Disable
1’b: Enable

ALC5616
Datasheet
8.61. PR-A0h: EQ Low Pass Filter Coefficient (LPF:a1)

Default: 1C10’h
Table 76. PR-A0h: EQ Low Pass Filter Coefficient (LPF:a1)

lpf_a1 15:0 R/W 1C10’h 2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
8.62. PR-A1h: EQ Low Pass Filter Gain (LPF:H0)

Default: 01F4’h
Table 77. PR-A1h: EQ Low Pass Filter Gain (LPF:H0)

lpf_h0 15:0 R/W 01F4’h 2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
8.63. PR-A2h: EQ Band 1 Coefficient (BPF1:a1)

Default: C5E9’h
Table 78. PR-A2h: EQ Band 1 Coefficient (BPF1:a1)

Bpf1_a1 15:0 R/W C5E9’h 2’s complement in 3.13 format. (The range is from –4~3.99,

Default: 1A98’h

Bpf1_a2 15:0 R/W 1A98’h 2’s complement in 3.13 format. (The range is from –4~3.99,

ALC5616
Datasheet
8.65. PR-A4h: EQ Band 1 Gain (BPF1:H0)

Default: 1D2C’h
Table 80. PR-A4h: EQ Band 1 Gain (BPF1:H0)

Bpf1_h0 15:0 R/W 1D2C’h 2’s complement in 3.13 format. (The range is from –4~3.99,

Default: C882’h
Table 81 PR-A5h: EQ Band 2 Coefficient (BPF2:a1)

Bpf2_a1 15:0 R/W C882’h 2’s complement in 3.13 format. (The range is from –4~3.99,

Default: 1C10’h

Bpf2_a2 15:0 R/W 1C10’h 2’s complement in 3.13 format. (The range is from –4~3.99,
8.68. PR-A7h: EQ Band 2 Gain (BPF2:H0)

Default: 01F4’h
Table 83. PR-A7h: EQ Band 2 Gain (BPF2:H0)

Bpf2_h0 15:0 R/W 01F4’h 2’s complement in 3.13 format. (The range is from –4~3.99,

ALC5616
Datasheet

Default: E904’h

Bpf3_a1 15:0 R/W E904’h 2’s complement in 3.13 format. (The range is from –4~3.99,

Default: 1C10’h

8.71. PR-AAh: EQ Band 3 Gain (BPF3:H0)

Default: 01F4’h
Table 86. PR-AAh: EQ Band 3 Gain (BPF3:H0)

8.72. PR-ABh: EQ Band 4 Coefficient (BPF4:a1)

Default: E904’h
Table 87. PR-ABh: EQ Band 4 Coefficient (BPF4:a1)

Bpf4_a1 15:0 R/W E904’h 2’s complement in 3.13 format. (The range is from –4~3.99,

ALC5616
Datasheet
8.73. PR-ACh: EQ Band 4 Coefficient (BPF4:a2)

Default: 1C10’h
Table 88. PR-ACh: EQ Band 4 Coefficient (BPF4:a2)

8.74. PR-ADh: EQ Band 4 Gain (BPF4:H0)

Default: 01F4’h
Table 89. PR-ADh: EQ Band 4 Gain (BPF4:H0)

8.75. PR-AEh: EQ High Pass Filter 1 Coefficient (HPF1:a1)

Default: 1C10’h
Table 90. PR-AEh: EQ High Pass Filter 1 Coefficient (HPF1:a1)

Hpf1_a1 15:0 R/W 1C10’h 2’s complement in 3.13 format. (The range is from –4~3.99,
8.76. PR-AFh: EQ High Pass Filter 1 Gain (HPF1:H0)

Default: 01F4’h
Table 91. PR-AFh: EQ High Pass Filter 1 Gain (HPF1:H0)

Hpf1_h0 15:0 R/W 01F4’h 2’s complement in 3.13 format. (The range is from –4~3.99,

ALC5616
Datasheet
8.77. PR-B0h: EQ High Pass Filter 2 Coefficient (HPF2:a1)

Default: 2000’h
Table 92. PR-B0h: EQ High Pass Filter 2 Coefficient (HPF2:a1)

Hpf2_a1 15:0 R/W 2000’h 2’s complement in 3.13 format. (The range is from –4~3.99,
8.78. PR-B1h: EQ High Pass Filter 2 Coefficient (HPF2:a2)

Default: 0000’h
Table 93. PR-B1h: EQ High Pass Filter 2 Coefficient (HPF2:a2)

Hpf2_a2 15:0 R/W 0000’h 2’s complement in 3.13 format. (The range is from –4~3.99,
8.79. PR-B2h: EQ High Pass Filter 2 Gain (HPF2:H0)

Default: 2000’h
Table 94. PR-B2h: EQ High Pass Filter 2 Gain (HPF2:H0)

Hpf2_h0 15:0 R/W 2000’h 2’s complement in 3.13 format. (The range is from –4~3.99,
8.80. PR-B3h: EQ Pre Volume Control

Default: 0800’h
Table 95. PR-B3h: EQ Pre Volume Control

Eq_pre_vol 15:0 R/W 0800’h 2’s complement in 5.11 format. (Default is 0dB)
(The range is from –16~15.99, pre-gain should be in 0 ~
15.99 [+24dB ~ -66dB])

ALC5616
Datasheet
8.81. PR-B4h: EQ Post Volume Control

Default: 0800’h
Table 96. PR-B4h: EQ Post Volume Control

Eq_post_vol 15:0 R/W 0800’h 2’s complement in 5.11 format. (Default is 0dB)
(The range is from –16~15.99, pre-gain should be in 0 ~
15.99 [+24dB ~ -66dB])
8.82. MX-FEh: Vendor ID

Default: 10EC’h
Table 97. MX-FEh: Vendor ID

Vendor_id 15:0 R 10EC’h Vendor ID

ALC5616
Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1. Absolute Maximum Ratings
Table 98. Absolute Maximum Ratings
Parameter Symbol Min Typ Max Units
Power Supplies
Digital IO Buffer DBVDD -0.3 - 3.63 V
Digital Core DCVDD -0.3 - 1.98 V
Analog AVDD -0.3 - 1.98 V
Analog DACREF -0.3 - 1.98 V
Headphone CPVDD -0.3 - 1.98 V
Micbias MICVDD -0.3 - 3.63 V
o
Operating Ambient Temperature Ta -25 - +85 C
o
Storage Temperature Ts -55 - +125 C
9.1.2. Recommended Operating Conditions

Table 99. Recommended Operating Conditions
Digital IO Buffer DBVDD 1.71 1.8 3.6 V
Digital Core DCVDD 1.1 1.2 1.9 V
Analog AVDD 1.71 1.8 1.9 V
Analog DACREF 1.71 1.8 1.9 V
Headphone CPVDD 1.71 1.8 1.9 V
Micbias MICVDD 3.0 3.3 3.6 V
9.1.3. Static Characteristics

Table 110. Static Characteristics
Input Voltage Range VIN -0.30 - DBVDD+0.30 V
Low Level Input Voltage VIL - - 0.35DBVDD V
High Level Input Voltage VIH 0.65DBVDD - - V
High Level Output Voltage VOH 0.9DBVDD - - V
Low Level Output Voltage VOL - - 0.1DBVDD V
Output Buffer High Drive Current - 0.6 1.8 4.3 mA
Output Buffer Low Drive Current - 0.7 2.1 4.8 mA
Input Buffer Pull-Up Resistor - 55 110 270 K
Input Buffer Pull-Down Resistor - 63 130 300 K
Note: DBVDD=1.8V, DCVDD=1.2V, Tambient=40C.

ALC5616
Datasheet
9.2. Analog Performance Characteristics

Table 111. Analog Performance Characteristics
Parameter Min Typ Max Units
Full Scale Input Voltage
Line Inputs (Single-ended) - 0.6 - Vrms
MIC Inputs (Single-ended ) - 0.6 - Vrms
MIC Inputs (Differential) - 1.2 - Vrms
Full Scale Output Voltage
Line Outputs (Single-ended) - 1.0 - Vrms
Line Outputs (Differential) - 1.0 - Vrms
Headphone Amplifiers Outputs (For 10KOhm Load) - 1.0 - Vrms
Headphone Amplifiers Outputs (For 16Ohm Load) 0.7 Vrms
S/N Ratio
Stereo DAC Direct to HP_L/R with 32Ohm - 98 100 dBA
-
Line_In to Stereo ADC with 0dB (Single-end) 94 95 dBA
MIC_In to Stereo ADC with 0dB (Differential or Single-end) 94 95 dBA
MIC_In to Stereo ADC with 20dB and MICBIAS (Differential or 89 dBA
Single-end)
Single-end)
Single-end)
Total Harmonic Distortion + Noise

DAC Direct to HP_L/R with 16Ohm
Po = 20mW/CH -80 -83 dB
DAC Direct to HP_L/R with 10KOhm

-3dBFS -86 dB
Line_In to Stereo ADC with 0dB (Single-end) -83 dB

MIC_In to Stereo ADC with 0dB (Differential or Single-end) -83 dB
MIC_In to Stereo ADC with 20dB and MICBIAS (Differential or -81 dB
Single-end)
Single-end)
Single-end)
Power Consumption (Slave I2S Mode, 24-bit, SR: 44.1KHz)

P_power down (No Clock Input) <50 uW
P_playback (Stereo DAC to HP_OUT with 16 Ohm Load, With <= 6.5 mW
Clock, play silence)
P_playback (Stereo DAC to HP_OUT with 16 Ohm Load, With <= 14 mW
Clock, Po=1mW/CH)
P_record (LINE_IN to Stereo ADC, With Clock) <9 mW
Power Down Current

ALC5616
Datasheet
Parameter Min Typ Max Units
IDD_1.8V - - 20 µA
IDDD_3.3V - - 10 µA
MICBIAS1 Output Voltage
Setting 1 - 0.9*MICVDD - V
0.75*MICVDD
Setting 2 - - V
MICBIAS1 Drive Current
MICBIAS = 0.9*MICVDD - 4 - mA
Note: Standard test conditions:
Tambient=25C
DBVDD=1.8V
DCVDD=1.2V
AVDD=1.8V
MICVDD=3.3V
CPVDD=1.8V
1kHz input sine wave; PCM Sampling frequency=48kHz; Test bench Characterization BW: 10Hz~22kHz, 0dB attenuation

ALC5616
Datasheet
9.3. Signal Timing

9.3.1. I2C Control Interface
tw (9) tw (10)
t sp
SCLK
tsu (7) tsu(8)

t h(5) th(6)
SDA
2
Figure 24. I C Control Interface
2
Table 112. I C Timing
Clock Pulse Duration tw(9) 1.3 - - µs
Clock Pulse Duration tw(10) 600 - - ns
Clock Frequency F 0 - 400K Hz
Start Hold Time th(5) 600 - - ns
Data Setup Time tsu(7) 100 - - ns
Data Hold Time th(6) - - 900 ns
Rising Time tr - - 300 ns
Falling Time tf - - 300 ns
Stop Setup Time tsu(8) 600 - - ns
Pulse Width of Spikes Suppressed Input Filter tsp 0 - 50 ns

ALC5616
Datasheet
9.3.2. I2S/PCM Interface Master Mode
2
Figure 25. Timing of I S/PCM Master Mode
2
Table 113 Timing of I S/PCM Master Mode
LRCK Output to BCLK Delay tLRD - - 30 ns
Data Output to BCLK Delay tADD - - 30 ns
Data Input Setup Time tDAS 10 - - ns
Data Input Hold Time tDAH 10 - - ns

ALC5616
Datasheet
9.3.3. I2S/PCM Interface Slave Mode
2
Figure 26. I S/PCM Slave Mode Timing
2
Table 114. I S/PCM Slave Mode Timing
BCLK High Pulse Width tBCH 20 - - ns
BCLK Low Pulse Width tBCL 20 - - ns
LRCK Input Setup Time tLRS 30 - - ns
Data Output to BCLK Delay tADD - - 30 ns
Data Input Setup Time tDAS 10 - - ns
Data Input Hold Time tDAH 10 - - ns

ALC5616
Datasheet
10. Application Circuits
MICVDD
DACREF
DCVDD
CPVDD
DBVDD
AVDD
C32
2.2uF
U1
31
15
30
29
5
6
DACREF
AVDD
MICVDD
CPVDD
DCVDD
DBVDD
MICBIAS1 32
R19 0/5% MICBIAS1 14 C41 2.2uF/6.3V
C7
CPP1 13
MIC_IN 2 CPN1
4.7uF/6.3V
IN1P
12 C42 2.2uF/6.3V
INL 3 CPP2 11
INR 4 IN2P CPN2
IN2N/JD2
17 HPOR
HPO_R 20 HPOL
HPO_L
MCLK_IC 25 9 LOUTL
DACDAT 22 MCLK LOUTL/P 10 LOUTR
ADCDAT 21 DACDAT1 LOUTR/N
BCLK 24 ADCDAT1
LRCK 23 BCLK1
LRCK1 16 C10 2.2uF/6.3V
CPVPP 19 C12 2.2uF/6.3V
CPVEE 18
CPVREF 8 C18 4.7uF/6.3V
VREF2
GPIO1/IRQ SCL
I2C Interface
28 26
GPIO1/IRQ1 SCL SDA SCL_Host
27
SDA SDA_Host
1
CPGND
HPGND
JD1
DGND
AGND
R26 10k/5%
MIC_VDD R29 10k/5% R27 DBVDD
10k/5%
JD1_1 ALC5651
7
DGND 33
CPGND 33
CPGND 33
JD1_2 R5 0/5%/0805
AGND

ALC5616
Datasheet
Line Output Heaphone Output

R20 33/5%
HPOL 1 PH8
2
R24 22/5% R21 JD1_1 3
C24 1u/6.3V 33/5%
LOUTL 1 PH7 HPOR 4
2 5
3 C66 C55
LOUTR C26 1u/6.3V 4
5 0.1uF/6.3V 0.1uF/6.3V RJ4
R25 22/5%
R23 R22
10K/5%
22/5% 22/5%
Line Input MIC Input
MICBIAS1
R3
INL C25 2.2uF/6.3V 1 PH9
MIC1
2 2.2K/5%
JD1_2 3 C4 2.2uF/6.3V
C27 2.2uF/6.3V
INR 4 MIC_IN SE1 P 1
5
2
N
RJ5
20K/5%
Power I2S1 Interface

MICVDD C45 NC/22pF/6.3V
AVDD DACREF CPVDD
1.71V ~ 1.9V 1.71V ~ 1.9V 3.0V ~ 3.6V MCLK_IC R9 0/5%
R28 47/5% MCLK
C22 C43 C44 C33 NC/22pF/6.3V
C19 C20 C23 C21
0.1uF/6.3V 0.1uF/6.3V 4.7uF/6.3V BCLK R7 0/5%

0.1uF/6.3V 4.7uF/6.3V 4.7uF/6.3V 4.7uF/6.3V BCLK1
C34 NC/22pF/6.3V
LRCK R16 0/5%

LRCK1
C46 NC/22pF/6.3V
DBVDD DACDAT R17 0/5%
DACDAT1
1.71V ~ 3.3V
C47 NC/22pF/6.3V
C29 C30 ADCDAT R18 0/5%
ADCDAT1
0.1uF/6.3V 2.2uF/6.3V
By-Pass Capcity Near The Power Pins
Figure 27. Application Circuit

ALC5616
Datasheet
11. Package Information

Plastic Quad Flat No-Lead Package 32 Leads 4x4mm2 Outline
Dimension in mm Dimension in inch

Symbol
Min Nom Max Min Nom Max
A 0.80 0.85 0.90 0.031 0.033 0.035
A1 0.00 0.02 0.05 0.000 0.001 0.002
A2 — 0.65 0.70 — 0.026 0.028
A3 0.20 REF 0.008 REF
b 0.15 0.20 0.25 0.006 0.080 0.010
D/E 4.00 BSC 0.157 BSC
D2/E2 2.55 2.70 2.85 0.100 0.106 0.112
e 0.40 BSC 0.016 BSC
L 0.30 0.40 0.50 0.012 0.016 0.020
L1 0.282 0.382 0.482 0.011 0.015 0.019
：
Notes
：
1. CONTROLLING DIMENSION MILLIMETER(mm).

：
2. REFERENCE DOCUMENTL JEDEC MO-220.

Figure 28. Package Dimension

ALC5616
Datasheet
12. Ordering Information

Table 115. Ordering Information
Part Number Package Status
ALC5616-CG 32-Pin QFN (4mm x 4mm) in ‘Green’ Package (Tray) N/A
ALC5616-CGT 32-Pin QFN (4mm x 4mm) in ‘Green’ Package (Tape & Reel) N/A
Realtek Semiconductor Corp.

Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com

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ALC5616

Ultra-Low Power Audio CODEC

Realtek Semiconductor Corp.

USING THIS DOCUMENT

I2S Audio CODEC for Mobile Devices ii Rev. 0.1

I2S Audio CODEC for Mobile Devices iii Rev. 0.1

3. SYSTEM APPLICATION ................................................................................................................................................. 2

4. FUNCTION BLOCK AND MIXER PATH ..................................................................................................................... 3

I2S Audio CODEC for Mobile Devices v Rev. 0.1

11. PACKAGE INFORMATION ..................................................................................................................................... 94

12. ORDERING INFORMATION ................................................................................................................................... 95

I2S Audio CODEC for Mobile Devices vi Rev. 0.1

I2S Audio CODEC for Mobile Devices vii Rev. 0.1

I2S Audio CODEC for Mobile Devices viii Rev. 0.1

I2S Audio CODEC for Mobile Devices ix Rev. 0.1

Two-Channel Audio Hub/CODEC and SounzRealTM 1 Rev. 0.1

 Digital-to-Analog Converter with 98dBA SNR

I2S Audio CODEC for Mobile Devices 2 Rev. 0.1

4. Function Block and Mixer Path

Reference Digital Audio Interface

Figure 1. Block Diagram

I2S Audio CODEC for Mobile Devices 3 Rev. 0.1

4.2. Audio Mixer Path

Figure 2. Audio Mixer Path

Two-Channel Audio Hub/CODEC and SounzRealTM 4 Rev. 0.1

4.3. Digital Mixer Path

I2S Digital Interface Process

Two-Channel Audio Hub/CODEC and SounzRealTM 5 Rev. 0.1

DBVDD 29 ALC5616 12 CPP2

Figure 4. Pin Assignments

Two-Channel Audio Hub/CODEC and SounzRealTM 6 Rev. 0.1

6.2. Analog I/O Pins

I2S Audio CODEC for Mobile Devices 7 Rev. 0.1

I2S Audio CODEC for Mobile Devices 8 Rev. 0.1

I2S Audio CODEC for Mobile Devices 9 Rev. 0.1

Table 5. Power Supply for Best Performance

*1.2V DCVDD was generated by internal LDO.

Table 6. Power Supply Condition for Power Down Leakage

I2S Audio CODEC for Mobile Devices 10 Rev. 0.1

7.2. Power Supply On/Off Sequence

Power On Sequence: (Sequentially turn on power pins)

1. DBVDD/AVDD/DACREF/CPVDD power supply on.

2. MICVDD power supply on.

3. Software starts to initialize ALC5616.

Power Off Sequence: (Sequentially turn off power pins)

1. Power down all Codec function (Write 0x0000’h to register MX-00’h).

2. MICVDD power supply off.

3. DBVDD/AVDD/DACREF/CPVDD power supply off

I2S Audio CODEC for Mobile Devices 11 Rev. 0.1

Table 7. Reset Operation

7.3.1. Power-On Reset (POR)

Table 8. Power-On Reset Voltage

7.3.2. Software Reset

I2S Audio CODEC for Mobile Devices 12 Rev. 0.1

Figure 5. Audio Clock Tree

I2S Audio CODEC for Mobile Devices 13 Rev. 0.1

7.4.1. Phase-Locked Loop

The PLL transmit formula as below: