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UCC2897A
SLUS829G – AUGUST 2008 – REVISED FEBRUARY 2020
UCC2897A Advanced Current-Mode Active-Clamp PWM Controller

1 Features 3 Description
•
1 Low-output jitter The UCC2897A PWM controller simplifies
implementation of the various active clamp or reset
• Soft-stop shutdown of MAIN and AUX and synchronous rectifier switching power topologies.
• 110-V input startup function
The UCC2897A is a peak current-mode fixed-
• Ideal for active-clamp, reset-forward, flyback and frequency high-performance pulse-width modulator.
synchronous rectifier uses The controller includes the logic and the drive
• Provides complementary auxiliary driver with capability for the P-channel auxiliary switch along with
programmable dead time (Turn-On Delay) a simple method of programming the critical delays
between AUX and MAIN switches for proper active-clamp operation.
• Peak current-mode control with 0.5-V cycle-by- Features include an internal programmable slope
cycle current limiting compensation circuit, precise DMAX limit, and a
• TrueDrive™ 2-A Sink, 2-A source outputs synchronizable oscillator with an internal-timing
capacitor. An accurate line-monitoring function also
• Trimmed internal-bandgap reference for accurate programs the ON and OFF transitions of the
line UV and line OV threshold converter with regard to the bulk input voltage, VIN.
• Programmable slope compensation
The UCC2897A adds a second-level hiccup-mode
• High-performance 1-MHz synchronizable oscillator current-sense threshold, bi-directional
with internal timing capacitor synchronization and input-overvoltage protection
• Precise programmable maximum duty cycle functionalities. The UCC2897A is offered in 20-pin
• PB-free lead finish package TSSOP (PW) and 20-pin QFN (RGP) packages.
Device Information(1)
2 Applications
PART NUMBER PACKAGE BODY SIZE (NOM)
• High-efficiency DC-to-DC power supplies TSSOP (20) 6.60 mm x 6.60 mm
• Server power, 48-V telecom, datacom, and 42-V UCC2897A
VQFN (20) 4.15 mm x 4.15 mm
automotive applications
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC2897A
SLUS829G – AUGUST 2008 – REVISED FEBRUARY 2020 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 13
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 27
3 Description ............................................................. 1 9 Application and Implementation ........................ 28
4 Revision History..................................................... 2 9.1 Application Information............................................ 28
9.2 Typical Application ................................................. 28
5 Device Options....................................................... 3
6 Pin Configuration and Functions ......................... 3 10 Power Supply Recommendations ..................... 34
7 Specifications......................................................... 5 11 Layout................................................................... 34
11.1 Layout Guidelines ................................................. 34
7.1 Absolute Maximum Ratings ...................................... 5
11.2 Layout Example .................................................... 34
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5 12 Device and Documentation Support ................. 36
7.4 Thermal Information .................................................. 6 12.1 Documentation Support ....................................... 36
7.5 Electrical Characteristics........................................... 6 12.2 Receiving Notification of Documentation Updates 36
7.6 Timing Requirements ............................................... 7 12.3 Community Resources.......................................... 36
7.7 Typical Characteristics .............................................. 9 12.4 Trademarks ........................................................... 36
12.5 Electrostatic Discharge Caution ............................ 36
8 Detailed Description ............................................ 12
12.6 Glossary ................................................................ 36
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12 13 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (November 2017) to Revision G Page
• Changed Modified Typical Application diagram .................................................................................................................... 1

• Changed Updated the RDEL1 calculation............................................................................................................................ 31
• Changed Updated the RDEL2 calculation ........................................................................................................................... 31
Changes from Revision E (April 2015) to Revision F Page
• Changed Equation 1 From; tDEL2 = 11.1 × 10–2 To: tDEL2 = 11.1 × 10–12 .............................................................................. 13
• Changed Equation 15 From: QG(main) x QG(aux) To: QG(main) + QG(aux) .................................................................................... 31
Changes from Revision D (July 2009) to Revision E Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
• Changed Thermal Resistance Information table to new Thermal Information layout and updated PW and RGP
package data .......................................................................................................................................................................... 3
• Added RON and ROFF, RDEL test conditions to DMAX parameter in the PWM section of the Electrical Characteristics table... 7
• Changed Oscillator equations in Step 1 for RON and ROFF ................................................................................................... 30
2 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated
Product Folder Links: UCC2897A

UCC2897A
www.ti.com SLUS829G – AUGUST 2008 – REVISED FEBRUARY 2020
5 Device Options
CYCLE-BY- 110-V HV JFET PART NUMBER

AUX OUTPUT HICCUP MODE
APPLICATION CYCLE CS START-UP
POLARITY CS THRESHOLD TSSOP-20 (PW) (1) QFN-20 (RGP) (2)
THRESHOLD CIRCUIT
DC/DC P-Channel 0.5 V 0.75 V Yes UCC2897APW UCC2897ARGP
(1) The PW package is available taped and reeled. Add R suffix to the device type (for example: UCC2897APWR) to order quantities of
2,000 devices per reel. Bulk quantities are 70 units per tube. The RGP package is available in two options of tape and reel. The RGPT
is orderable in small reels of 250 (for example: UCC2897ARGPT); the RGPR contains 3000 pieces per reel (for example:
UCC2897ARGPR).
(2) The TSSOP-20 (PW) and QFN-20 (RGP) package uses Pb-free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C
to 260°C peak reflow temperature and compatible with either lead-free, tin, or lead soldering operations.
6 Pin Configuration and Functions
PW Package
20-Pin TSSOP
Top View
VIN 1 20 N/C
N/C 2 19 LINEOV
RDEL 3 18 LINEUV
RON 4 17 VDD
ROFF 5 16 PVDD
VREF 6 15 OUT
SYNC 7 14 AUX
GND 8 13 PGND
CS 9 12 SS/SD
RSLOPE 10 11 FB
RGP Package
20-Pin VQFN
Bottom View
SYNC
ROFF
VREF
RON
GND
1 2 3 4 5
RDEL 20 6 CS
NC 19 7 RSLOPE
VIN 18 8 FB
NC 17 9 SS/SD
LINEOV 16 10 PGND
15 14 13 12 11
VDD
PVDD
LINEUV
AUX
OUT
Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 3

UCC2897A
Pin Functions
PIN
NO. I/O DESCRIPTION
NAME
TSSOP VQFN
This output drives the auxiliary-clamp MOSFET which turns on when the main
AUX 14 11 O PWM-switching device turns off. The AUX pin directly drives the auxiliary switch
with a 2-A source turn-on current and a 2-A sink turn-off current.
This pin senses the peak current utilized for current-mode control and for current-
CS 9 6 I limiting functions. The peak signal is applied to this pin before pulse-by-pulse
current limiting activates and is approximately 0.5 V.
This pin brings the error signal from an external optocoupler or error amplifier into
the PWM-control circuitry. Often, there is a resistor tied from FB to VREF, and an
FB 11 8 I
optocoupler pulls the control pin closer to GND to reduce the pulse width of the
OUT output driving the main-power switch of the converter.
This pin serves as the fundamental-analog ground for the PWM-control circuitry.
GND 8 5
This pin is connected to PGND directly at the device.
The LINEOV pin is an input pin of voltage comparator with programmable
LINEOV 19 16 I
hysteresis and 1.27-V threshold, providing LINE overvoltage or other functions.
This pin provides a means to accurately enable/disable the power converter stage
by monitoring the bulk input voltage or another parameter. When the circuit initially
starts (or restarts from a disabled condition), a rising input on LINEUV enables the
LINEUV 18 15 I outputs when the threshold of 1.27 V is crossed. After the circuit is enabled, a
falling LINEUV signal disables the outputs when the same threshold is reached.
The hysteresis between the two levels is programmed using an internal current
source.
This output pin drives the main PWM switching element MOSFET in an active-
clamp controller. The OUT pin directly drives an N-channel device with a 2-A
OUT 15 12 O
source turnon-current and a 2-A sink turnoff-current. TI recommends connecting a
10-kΩ resistor from this pin to PGND pin.
The PGND should serve as the current return for the high-current output drivers
PGND 13 10 OUT and AUX. Ideally, the current path from the outputs to the switching devices,
and back would be as short as possible, and enclose a minimal-loop area.
The PVDD pin is the supply pin for the power devices. It is separated internally
PVDD 16 13 I
from the VDD pin.
A resistor connected from this pin to GND programs an internal current source that
RSLOPE 10 7 I
sets the slope-compensation ramp for the current-mode control-circuitry.
A resistor from this pin to GND programs the turn-on delay of the two gate-drive
RTDEL 3 20 I outputs to accommodate the resonant transitions of the active-clamp power
converter.
A resistor connected from this pin to GND programs an internal-current source that
ROFF 5 2 I
discharges the internal timing-capacitor.
A resistor connected from this pin to GND programs an internal-current source that
RON 4 1 I
charges the internal timing-capacitor.
A capacitor from SS/SD to ground is charged by an internal-current source of
SS/SD 12 9 I IRON to program the soft-start interval for the controller. During a fault condition
this capacitor is discharged by a current source equal to IRON.
The SYNC pin serves as a bidirectional-synchronization input for the internal
oscillator. The synchronization function is implemented such that the user-
SYNC 7 4 I programmable maximum duty-cycle (set by RON and ROFF) remains accurate
during synchronized operation. This pin is left open when not in use. The external
capacitance is minimized. No capacitors are connected to this pin.
The VDD pin is the power supply for the device. There should be a 1-μF capacitor
directly from VDD to PGND. The capacitor value should be at least 10-times larger
than that on VREF. PGND and GND are connected externally and directly from
VDD 17 14 I
PGND pin to GND pin. (To make a full design of capacitance on VDD pin, please
refer to, Application Note: Understanding and Designing an Active Clamp Current
Mode Controlled Converter (SLUA535), section 7.3)
This pin is connected to the input-power rail directly. Inside the device, a high-
VIN 1 18 I voltage start-up device is utilized to provide the start-up current for the controller
until a bootstrap-type bias rail becomes available.

UCC2897A
Pin Functions (continued)

PIN
NO. I/O DESCRIPTION
NAME
TSSOP VQFN
The VREF pin is the 5-V reference voltage that is used for an external load of up to
5 mA. Since this reference provides the supply rail for internal logic, VREF is
VREF 6 3 O
bypassed to AGND as close as possible to the device. The VREF bias profile is
not always monotonic before VDD reaches 5 V.
7 Specifications
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Line input voltage 120
VDD Supply voltage 16.5 V
Analog inputs, FB, CS, SYNC, LINEOV, LINEUV –0.3 (VREF+ 0.3)
IO_SOURCE Output source current (peak) OUT AUX 2.5
A
IO_SINK Output sink current (peak) OUT AUX –2.5
TJ Operating junction temperature range –55 150
°C
Tsol Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds 300
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- ±500 V
C101 (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Line input voltage 18 110 V
VDD Supply voltage 8.5 12 16 V
VDD Supply bypass capacitance 1 µF
RON = ROFF Timing resistance (for 250-kHz 75 kΩ
operation)
TJ Operating junction temperature –40 125 °C
CREF Reference bypass capacitance 0.1 µF

UCC2897A
7.4 Thermal Information

UCC2897A
THERMAL METRIC (1) QFN (RGP) TSSOP (PW) UNIT
20 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance 34.1 91.6
RθJC(top) Junction-to-case (top) thermal resistance 33.3 26.3
RθJB Junction-to-board thermal resistance 9.2 42.6
°C/W
ψJT Junction-to-top characterization parameter 0.4 1.1
ψJB Junction-to-board characterization parameter 9.1 42.1
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.9 N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics

VDD = 12 V (1), 1-µF capacitor for VDD to GND, 0.01-µF capacitor from VREF to GND, RON = ROFF = 75 kΩ, RSLOPE = 50 kΩ,
–40°C ≤ TA = TJ ≤ 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OVERALL
ISTARTUP Start-up current VDD < VUVLO 300 500 µA
VFB = 0 V,
IDD Operating supply current (1) (2) VCS = 0V, 2 3 mA
Outputs not switching
HIGH-VOLTAGE BIAS
Current available from VDD during
IDD-ST VDD startup current startup, TA = –40°C to +85°C, VIN = 4 11 mA
36 V (3)
IVIN JFET leakage current VIN = 120 V; VDD = 14 V 75 µA
UNDERVOLTAGE LOCKOUT
UVLO Start threshold voltage 12.2 12.7 13.2
Minimum operating voltage after
7.6 8 8.4 V
start
Hysteresis 4.4 4.7 5
LINE MONITOR
VLINEUV Line UV voltage threshold 1.243 1.268 1.294 V
ILINEUVHYS Line UV hysteresis current –11.5 –13 –14.5 µA
VLINEOV Line OV voltage threshold 1.243 1.268 1.294 V
ILINEOVHYS Line OV hysteresis current –11.5 –13 –14.5 µA
Soft-Start
ISSC SS charge current RON = 75 kΩ (4) –10.5 –14.5 –18.5
µA
ISSD SS discharge current RON = 75 kΩ (4) 10.5 14.5 18.5
Discharge/shutdown threshold
VSS/SD 0.4 0.5 0.6 V
voltage
VOLTAGE REFERENCE
VREF Reference voltage TJ = 25°C 4.85 5 5.15
V
VREF Reference voltage 0 A < IREF < 5 mA, over temperature 4.75 5 5.25
ISC Short circuit current REF = 0 V, TJ = 25°C –20 –11 –8 mA
INTERNAL SLOPE COMPENSATION
(1) Set VDD above the start threshold before setting at 12 V.

(2) Does not include current of the external oscillator network.
(3) The power supply starts with IDD–ST load on VDD, the part starts up with no load up to 125°C. For more information see the section for
VIN and VDD
(4) ISSC and ISS/SD are directly proportional to IRON. See Equation 8.

UCC2897A
Electrical Characteristics (continued)

VDD = 12 V(1), 1-µF capacitor for VDD to GND, 0.01-µF capacitor from VREF to GND, RON = ROFF = 75 kΩ, RSLOPE = 50 kΩ,
–40°C ≤ TA = TJ ≤ 125°C (unless otherwise noted)
RCS /
m Slope FB = High –10% +10%
RSLOPE
OSCILLATOR
TJ = 25°C 237 250 265
fOSC Oscillator frequency –40°C < TJ < 125°C; 8.5 V < VDD < kHZ
225 270
14.5 V
VP_P Oscillator amplitude (peak-to-peak) 2 V
SYNCHRONIZATION
SYNC input high voltage 3
V
SYNC input low voltage 1.6
SYNC pull down output current 600
µA
SYNC pull up output current –600
SYNC output pulse width 150
ns
tDEL SYNC-to-output delay 50
PWM (5)
DMAX Maximum duty cycle RON = ROFF = 75 kΩ, RDEL = 10 kΩ 66% 70% 74%
Minimum duty cycle 0%
PWM offset CS = 0 V 0.43 0.5 0.61 V
CURRENT SENSE
VLVL Current sense level shift voltage 0.4 0.5 0.6
VERR(max) Maximum voltage error (clamped) 5
V
Current sense threshold cycle-by-
VCS 0.43 0.48 0.53
cycle
OUTPUT (OUT AND AUX)
IOUT(src) Output source current –2
A
IOUT(sink) Output sink current 2
VOUT(low) Low-level output voltage IOUT = 150 mA 0.4
V
VOUT(high) High-level output voltage IOUT = –150 mA 11.1
(5) Maximum pulse width needs to be less than DMAX, which is a function of RON and ROFF. For more information on DMAX, see detailed
description for ROFF in .
7.6 Timing Requirements

MIN NOM MAX UNIT
OUTPUT (OUT AND AUX)
tR Rise time CLOAD = 2 nF 19 28
tF Fall time CLOAD = 2 nF 14 23
tDEL1 Delay time (AUX to OUT) CLOAD = 2 nF, RDEL = 10 110 ns
kΩ
tDEL2 Delay time (OUT to AUX) CLOAD = 2 nF, RDEL = 10 115
kΩ

UCC2897A
50% 50%
OUT
t
AUX
50% 50% t
(P--channel)
tDEL1 tDEL2
Figure 1. Output Timing Diagram

UCC2897A
7.7 Typical Characteristics
14 2.5
12
UVLO On
VUVLO -- UVLO Voltage Thresholds -- V
2.0
IDD -- Supply Current -- mA

10
1.5
8
UVLO Off
6
1.0
UVLO Hysteresis
4
0.5
2
0 0
--50 --25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16
TJ -- Junction Temperature -- °C VDD -- Supply Voltage -- V
Figure 2. UVLO Voltage Thresholds vs. Junction Figure 3. Quiescent Current vs. Supply Voltage
Temperature
10 20
VIN = 36 V
External VDD Current -- mA 15

IDD -- Supply Current -- mA
--10
10
--20
--30
JFET Source Current 5
--40
0
--50 --50 --25 0 25 50 75 100 125
0 2 4 6 8 10 12 14 16
TJ -- Junction Temperature -- °C
VDD -- Supply Voltage -- V
Figure 5. Typical Startup Current Available From VDD vs.

Figure 4. Supply Current vs. Supply Voltage
Temperature
1.30 20
ISS(DIS)/ISS(CHG) -- Softstart Currents -- μA
15
1.28 Softstart Discharge Current
VTH -- Line Thresholds -- V
10
1.26 5
1.24
--5
--10
1.22
--15 Softstart Charge Current
1.20 --20
--50 --25 0 25 50 75 100 125 --50 --25 0 25 50 75 100 125
TJ -- Junction Temperature -- °C TJ -- Junction Temperature -- °C
Figure 6. Line UV/OV Voltage Threshold vs. Junction Figure 7. Softstart Currents vs. Temperature
Temperature

UCC2897A
Typical Characteristics (continued)

VTH -- Softstart/Shutdown Threshold Voltage -- V 0.60 10 M
0.58
0.56
fSW -- Switching Frequency -- Hz

1M
0.54
0.52
0.50 100 K
0.48
0.46
10 K
0.44
0.42
0.40 1K
--50 --25 0 25 50 75 100 125
10 100 1000
TJ -- Junction Temperature -- °C RON = ROFF -- Timing Resistance -- kΩ
Figure 8. Soft Start/Shutdown Threshold Voltage vs. Figure 9. Switching Frequency vs. Programming Resistance
Junction Temperature
275 74
RON = ROFF = 75 kΩ RON = ROFF = 75 kΩ
270
73
265
fSW -- Switching Frequency -- kHz
DMAX -- Maximum Duty Cycle -- %

72
260
71
255
250 70
245
69
240
68
235
230 67
225 66
--50 --25 0 25 50 75 100 125 --50 --25 0 25 50 75 100 125
Figure 10. Oscillator Frequency vs. Junction Temperature Figure 11. Maximum Duty Cycle vs. Junction Temperature
1.4 2.50
VSYNC -- Synchronization Threshold Voltage -- V
VCS -- Current Sense Threshold Voltage -- V
1.2 2.45
2.40
1.0
2.35
0.8
2.30
Hiccup Mode
0.6
2.25
0.4 Cycle-by-Cycle Current Limit 2.20
0.2 2.15
2.10
0 --50 --25 0 25 50 75 100 125
--50 --25 0 25 50 75 100 125
Figure 12. Current Sense Threshold Voltage vs. Junction Figure 13. Synchronization Threshold Voltage vs. Junction
Temperature Temperature

UCC2897A
Typical Characteristics (continued)

25 800
CLOAD = 2 nF
Rise Time 700

20 t DEL1
tR/tF -- Rise and Fall Times -- ns
600
t DEL2
tDEL -- Delay Time -- ns

500
15 Fall Time
400
10 300
200
5
100
0
0 0 10 20 30 40 50 60 70
--50 --25 0 25 50 75 100 125
RDEL -- Delay Resistance -- kΩ
Figure 14. Out And AUX Rise And Fall Time vs. Junction Figure 15. Delay Time vs. Delay Resistance
Temperature
250 800
RDEL = 10 kΩ RDEL = 50 kΩ
700
200
600
tDEL -- Delay Time -- ns
OUT to AUX tDEL -- Delay Time -- μs

500 AUX to OUT
150
OUT to AUX
400
100 300
200
50 AUX to OUT
100
0 0
--50 --25 0 25 50 75 100 125 --50 --25 0 25 50 75 100 125
Figure 16. Delay Time vs. Junction Temperature Figure 17. Delay Time vs. Junction Temperature
5.3
No Load
10 mA Load
5.2
VREF -- Reference Voltage -- V
5.1
5.0
4.9
4.8
4.7
--50 --25 0 25 50 75 100 125
Figure 18. Reference Voltage vs. Temperature

UCC2897A
8 Detailed Description
8.1 Overview
The UCC2897A is a peak current mode active clamp PWM controller. It provides simple interface to program the
critical timings such as soft start, gate turn on delay, switching period, maximum operating duty cycle, and slope
compensation. Features includes a high voltage JFET circuit, UVLO protection, line under/over voltage
protection, pulse skipping, and synchronization. The UCC2897A also has the logic and the drive capability for a
P-channel auxiliary switch. The VDD supply is generated from a bootstrap circuit connected to a bias winding.
8.2 Functional Block Diagram
VIN 1
2.5 V
N/C 2 VREF
IRDEL
20 N/C
VREF
0.05 x IRDEL
RDEL 3
2.5 V CLOCK 0.05 x IRDEL 19 LINEOV
ICHG Start
LineOV
1.27 V
End
RTON 4 LineU 18 LINEUV
1 - DMAX V 1.27
2.5 V V 13V / 8V
IDSCHG VDD
CT
VREF
RTOFF 5 OUT PWM 17 VDD
SYNC OFF
VDD
IRDEL 16 PVDD
OUT
6 REF
VREF S Q Turn-on Delay 15 OUT
GEN
RD Q VREF GND
IRDEL
SYNC 7 14 AUX
+
0.5 V GND
Turn-on Delay
GND 8 13 PGND
VREF VREF
0.43 x ICHG
5 x ISLOPE
CS 99 12 SS/SD
CT 1 - DMAX 4xR 0.43 x ICHG
R VDD
ISLOPE VREF
LineUV UVLO & SS Enable
LineOV
RSLOPE 10 11 FB
Copyright © 2017, Texas Instruments Incorporated

UCC2897A
8.3 Feature Description

8.3.1 Detailed Pin Descriptions
8.3.1.1 RDEL
This pin is internally connected to an approximately 2.5-V DC source. A resistor (RDEL) to GND sets the turn-on
delay for both gate drive signals of the UCC2987A controller. The delay time is identical for both switching
transitions between OUT turning off and AUX turning on, as well as when AUX is turning off and OUT is turning
on. The delay time is defined in Equation 1.
tDEL1 = tDEL2 = 11.1 × 10–12 ×RDEL + 15 × 10 –9 seconds (1)
For proper selection of the delay time refer to the various references describing the design of active-clamp
power-converters.
8.3.1.2 RON
This pin is internally connected to an approximately 2.5-V DC source. A resistor (RON) to GND (pin 6) sets the
charge current of the internal-timing capacitor. The RON pin, in conjunction with the ROFF pin (pin 3), sets the
operating frequency and maximum-operating duty cycle.
8.3.1.3 ROFF
This pin is internally connected to an approximately 2.5-V DC source. A resistor (ROFF) to GND (pin 6) sets the
discharge current of the internal-timing capacitor. The RON and ROFF pins set the switching period (TSW) and
maximum-operating duty cycle (DMAX) according to the following equations:
æSö
t ON = 36.1´ 10-12 ´ RON ´ ç ÷ - tDEL (s ) sec onds
èWø (2)
æSö
t OFF = 15 ´ 10-12 ´ ROFF ´ ç ÷ + tDEL (s ) + 170 ´ 10-9 ´ (s ) sec onds
èWø (3)
TSW = tON + tOFF (4)
t ON
DMAX =
t ON + t OFF (5)
8.3.1.4 VREF
The internal 5-V bias rail of the controller is connected to this pin. The internal bias-regulator requires a high-
quality ceramic-bypass capacitor (CVREF) to GND for noise filtering and to provide compensation to the regulator
circuitry. The recommended CVREF value is 0.22 μF and X7R capacitors are recommended. The minimum-bypass
capacitor value is 0.022 μF limited by stability considerations of the bias regulator, while the maximum is
approximately 22 μF. The capacitance on VREF and VDD should be in a minimum ratio of 1:10.
The VREF pin is internally current-limited and supplies approximately 5 mA to external circuits. The 5-V bias is
available only when the undervoltage lock-out (UVLO) circuit enables the operation of UCC2897A controller. The
VREF-bias profile may not be monotonic before VDD reaches 5 V.
For the detailed functional description of the undervoltage lock-out (UVLO) circuit refer to the section of this
datasheet.

UCC2897A
Feature Description (continued)

8.3.1.5 SYNC
This pin is a bi-directional synchronization terminal. This pin should be left open if not used.
This pin provides an input for an external-clock signal which synchronizes the internal oscillator of the
UCC2897A controller. The synchronizing frequency must be higher than the free-running frequency of the
onboard oscillator (TSYNC < TSW). The acceptable minimum pulse-width of the synchronization signal is
approximately 50 ns (positive logic), and should remain shorter than Equation 6.
(1 – DMAX) × TSYNC
where
• DMAX is set by RON and ROFF (6)
If the pulse-width of the synchronization signal stays within these limits, the maximum-operating duty ratio
remains valid as defined by the ratio of RON and ROFF, and DMAX is the same in free-running and in
synchronized modes of operation. If the pulse width of the synchronization signal would exceed the (1 – DMAX) ×
TSYNC limit, the maximum-operating duty cycle is defined by the synchronization pulse width.
In the stand-alone mode, the sync pin is driven by the internal oscillator which provides output pulses. The pulse
width from SYNC output does not vary with the duty cycle. That signal synchronizes other PWM controllers or
circuits requiring a constant-frequency time base.
External capacitance should be minimized on this pin layout. Capacitors are not connected between SYNC and
GND or PGND. For more information on synchronization of the UCC2897A refer to the section of this datasheet.
8.3.1.6 GND
This pin provides a reference potential for all small-signal control and programming circuitry inside the
UCC2897A. Ground layout is critical for correct operation. High-current surges from the MOSFET drivers conduct
through PVDD, OUT, AUX, and PGND. To localize these surges, PVDD must bypass directly to PGND. PGND
current must be electrically, capacitively, and inductively isolated from GND with only one short trace connecting
PGND to GND, located to best minimize noise into GND.
8.3.1.7 CS
CS is a direct input to the PWM and current-limit comparators of the UCC2897A controller. The CS pin never
connects directly across the current-sense resistor (RCS) of the power converter. A small, customary R-C filter
between the current-sense resistor and the CS pin is necessary to accommodate the proper operation of the
onboard slope-compensation circuit and in order to protect the interna- discharge transistor connected to the CS
pin (RF1, CF).
Slope compensation is achieved across RF by a linearly-increasing current flowing out of the CS pin. The slop-
compensation current is only present during the on-time of the gate-drive signal of the main-power switch (OUT)
of the converter. The internal-pulldown transistor of the CS pin is activated during the discharge time of the
timing capacitor. This time interval is (1 – DMAX) × TSW long and represents the specified off-time of the main-
power switch.

UCC2897A

8.3.1.8 RSLOPE
A resistor (RSLOPE) connected between this pin and GND (pin 6) sets the amplitude of the slope-compensation
current. During the on time of the main gate-drive output (OUT) the voltage across RSLOPE is a representation of
the internal-timing-capacitor waveform. As the timing capacitor is being charged, the voltage across RSLOPE also
increases, generating a linearly-increasing current waveform. The current provided at the CS pin for slope
compensation is proportional to this current flowing through RSLOPE.
Due to the high speed, AC-voltage waveform present at the RSLOPE pin, the parasitic capacitance and
inductance of the external-circuit components connected to the RSLOPE pin should be carefully minimized.
For more information on how to program the internal-slope compensation refer to the section of this datasheet.
8.3.1.9 FB
FB and SS/SD interact. The one with the lower-voltage value takes control on the duty cycle, refer to SS/SD
description. This pin is an input for the control voltage of the pulse-width modulator of the UCC2897A.The control
voltage is generated by an external-error amplifier by comparing the output voltage of the converter to a voltage
reference and employing the compensation for the voltage-regulation loop. Usually, the error amplifier is located
on the secondary side of the isolated-power converter and the output voltage is sent across the isolation
boundary by an optocoupler. Thus, the FB pin is usually driven by the optocoupler. An external-pullup resistor to
the VREF pin (pin 4) is also required for proper operation as part of the feedback circuitry.
The control voltage is internally buffered and connected to the PWM comparator through a voltage divider to
make it compatible to the signal level of the current-sense circuit. The useful voltage range of the FB pin is
between approximately 2.5 V and 4.5 V. Control voltages below the 2.5-V threshold result in zero-duty cycle
(pulse skipping) while voltages above 4.5 V result in full-duty-cycle (DMAX) operation.
8.3.1.10 SS/SD
A capacitor (CSS) connected between this pin and GND (pin 6) programs the soft-start time of the power
converter. The soft-start capacitor is charged by a precise, internal DC-current source which is programmed by
the RON resistor connected to pin 2. The soft-start current is defined in Equation 7.
V 1
ISS = 0.43 ´ IRON = 0.43 ´ REF ´
2 RON (7)
This DC current charges CSS from 0 V to approximately 5 V. Internal to the UCC2897A, the soft-start capacitor
voltage is buffered and ORed with the control voltage present at the FB pin (pin 9). The lower of the two voltages
manipulates the PWM engine of the controller through the voltage divider described with regards to the FB pin.
Accordingly, the useful control range on the SS pin is similar to the control range of the FB pin and it is between
2.5 V and 4.5 V approximately. During line-undervoltage protection, the PWM follows this pin-capacitor discharge
to achieve soft-stop function

UCC2897A

8.3.1.11 PGND
This pin serves as a dedicated connection to all high-current circuits inside the UCC2897A. The high-current
portion of the controller consists of the two high-current gate drivers, and the various bias connections except
VREF (pin 4). The PGND (pin 11) and GND (pin 6) pins are not connected internally, a low-impedance external
connection between the two ground pins is also required. TI recommends to form a separate ground plane for
the low-current setup components (RDEL, RON, ROFF, CVREF, CF, RSLOPE, CSS and the emitter of the optocoupler in
the feedback circuit). This separate ground plane (GND) should have a single connection to the rest of the
ground of the power converter (PGND) and this connection should be between pin 6 and pin 11 of the controller.
8.3.1.12 AUX
AUX is a high-current gate-drive output for the auxiliary switch to implement the active-clamp operation for the
power stage. The auxiliary output (AUX) of the UCC2897A drives a P-channel device as the clamp switch
therefore it requires an active-low operation (the switch is ON when the output is low).
8.3.1.13 OUT
This high-current output drives an external N-channel MOSFET. The UCC2897A controller uses an active-high
drive signal for the main switch of the converter.
Due to the high-speed and high-drive current capability of these outputs (AUX, OUT) the parasitic inductance of
the external-circuit components connected to these pins should be carefully minimized. A potential way of
avoiding unnecessary parasitic inductances in the gate-drive circuit is to place the controller in close proximity to
the MOSFETs and by ensuring that the outputs (AUX, OUT) and the gates of the MOSFET devices are
connected by wide overlapping traces. TI recommends connecting a 10-kΩ resistor from this pin to PGND pin to
reduce a possible parasitic effect from layout.
8.3.1.14 VDD
The VDD rail is the primary bias for the internal high-current gate drivers, the internal 5-V bias regulator and for
parts of the undervoltage-lockout circuit. To reduce switching noise on the bias rail, a good-quality ceramic
capacitor (CHF) must be placed very closely between the VDD pin and PGND (pin 11) to provide adequate
filtering. The recommended CHF value is 1-μF for most applications but the value might be affected by the
properties of the external-MOSFET transistors used in the power stage.
In addition to the low-impedance high-frequency filtering, the bias rail of the controller requires a larger value
energy-storage capacitor (CBIAS) connected parallel to CHF. The energy-storage capacitor must provide the hold-
up time to operate the UCC2897A (including gate-drive power requirements) during start up. In steady-state
operation the controller must be powered from a bootstrap winding off the power transformer or by an auxiliary-
bias supply. In case of an independent-auxiliary-bias supply, the energy storage is provided by the output
capacitance of the bias supply. The capacitor values are also determined by the capacitor values connected to
VREF. The capacitance on VREF and VDD should be in a minimum ratio of 1:10.

UCC2897A

8.3.1.15 LINEUV
This input monitors the incoming-power source to provide an accurate undervoltage-lockout function with user-
programmable hysteresis for the power supply controlled by the UCC2897A. The unique property of the
UCC2897A is to use only one pin to implement these functions without sacrificing on performance. The input
voltage of the power supply is scaled to the precise 1.27-V threshold of the undervoltage-lockout comparator by
an external-resistor divider (RIN1, RIN2 in ). Once the input threshold of the line monitor is exceeded, an internal-
current source gets connected to the LINEUV pin. The current generator is programmed by the RDEL resistor
connected to pin 1 of the controller. The actual current level is given in Equation 8.
V 1
IHYST = REF ´ ´ 0.05
2 RDEL (8)
As this current flows through RIN2 of the input divider, the undervoltage-lockout hysteresis is a function of IHYST
and RIN2 allowing accurate programming of the hysteresis of the line-monitoring circuit. When LINEUV is
detected, PWM follows VSS capacitor discharge and soft-stop function is provided. The soft-start capacitor starts
discharging when the soft-start capacitor voltage reaches 2.5 V. Both OUT and AUX stop switching while the
soft-start capacitor continues discharging until the voltage reaches 0.5 V when the soft start is resumed on the
assumption of all other soft-start conditions are met.
For more information on how to program the line-monitoring function refer to the of this datasheet.
8.3.1.16 VIN
The UCC2897A controller is equipped with a high-voltage N-channel-JFET startup device to initiate operation
from the input-power source of the converter in applications where the input voltage does not exceed the 110-V
maximum rating of the startup transistor. In these applications, the VIN pin connects directly to the positive
terminal of the input-power source. The internal-JFET startup transistor provides charge-current for the energy-
storage capacitor (CBIAS) connected across the VDD (pin 14) and PGND (pin 11) terminals. Note that the startup
device turns off immediately when the voltage on the VDD pin exceeds approximately 12.7 V, the undervoltage-
lockout threshold of the controller for turn-on. The JFET is also disabled at all times when the high-current gate
drivers are switching to protect against excessive-power dissipation and current through the device. For
dependable start-up, VDD must not be loaded by more than 4 mA.
For more information on biasing the UCC2897A, refer to the and sections of this datasheet.
8.3.1.17 LINEOV
This input monitors the incoming-power source to provide an accurate-overvoltage protection with user-
programmable hysteresis for the power supply controlled by the controller. The circuit implementation of the
overvoltage-protection function is identical to the technique used for monitoring the input-power rail for
undervoltage lockout. The circuit implements an accurate threshold and hysteresis using only one pin. The input
voltage of the power supply is scaled to the precise 1.27-V threshold of the overvoltage-protection comparator by
an external-resistor divider (RIN3, RIN4 in ). Once the input threshold of the line monitor is exceeded, an internal-
current source gets connected to the LINEOV pin. The current generator is programmed by the RDEL resistor
connected to pin 1 of the controller. The actual current level is given in Equation 9.
V 1
2 RDEL (9)
As this current flows through RIN4 of the input divider, the overvoltage-protection hysteresis is a function of IHYST
and RIN4 allowing accurate programming of the hysteresis of the line-monitoring circuit.
For more information on how to program the overvoltage protection, refer to the of this datasheet.

UCC2897A

8.3.2 JFET Control and UVLO
The UCC2897A controller includes a high-voltage JFET startup-transistor. The steady-state power-consumption
of the of the control circuit which also includes the gate-drive power-loss of the two power switches of an active-
clamp converter exceeds the current and thermal capabilities of the device. Thus the JFET should only be used
for initial start-up of the control circuitry and to provide keep-alive power during stand-by mode when the gate-
drive outputs are not switching. Accordingly, the startup device is managed by the control algorithm implemented
on board the UCC2897A. The following timing diagram in Figure 19 illustrates the operation of the JFET startup
device.
V ON
V IN
12.7V
10.0V 8V <VDD < 10V 8.0V
V DD Bootstrap bias
JFET OFF OFF OFF
ENABLE
(See diagram on p.6)
SS/SD
OFF OFF SWITCHING OFF

OUTPUTs
SWITCHING UDG--03148
Values are typical in the drawing.
Figure 19. JFET Control Startup and Shutdown
During initial power-up the JFET is on and charges the CBIAS and CHF capacitors connected to the VDD pin. The
undervoltage lockout-circuit of the controller monitors the VDD pin to ensure proper biasing before the operation
is enabled. When the VDD voltage reaches approximately 12.7 V (UVLO turnon threshold) the UVLO circuit
enables the rest of the controller. At that time, the JFET turns off and 5 V appears on the VREF terminal.
Switching waveforms might not appear at the gate-drive outputs unless all other conditions of proper operation
are met. These conditions are:
• The voltage on the CS pin is below the current limit threshold
• The control voltage is above the zero duty-cycle boundary (VFB > 2.5 V).
• The input voltage is in the valid operating range (VVON < VVIN < VVOFF.
– The line under or overvoltage protections are not activated.

UCC2897A

As the controller starts operation it draws bias power from the CBIAS capacitor until the bootstrap winding takes
over (referring to Figure 25 and Figure 26). During this time, VDD voltage is falling rapidly as the JFET is off but
the bootstrap voltage is still not sufficient to power the control circuits. It is imperative to store enough energy in
CBIAS to prevent the bias voltage from dipping below the turnoff threshold of the UVLO circuit during the startup-
time interval. Otherwise the power supply goes through several cycles of retry attempts before steady-state
operation is established.
During normal operation the bias voltage is determined by the bootstrap bias design. The UCC2897A tolerates a
wide range of bias voltages between the minimum-operating voltage (UVLO turn-off threshold) and the
maximum-operating voltage as defined in the .
In applications where the power supply enters standby in response to an external command, the bias voltage of
the controller must be kept alive to react intelligently to the control signal. In standby mode, switching action is
suspended for an undefined period of time and the bootstrap power is unavailable to bias the controller. Without
an alternate power source the bias voltage collapses and the controller initiates a re-start sequence. To avoid
this situation, the onboard JFET of the UCC2897A controller keeps the VDD bias alive as long as the gate-drive
outputs remain inactive. As shown in the timing diagram in Figure 19, the JFET turns on when VDD = 10 V and
charges the CBIAS capacitor to approximately 12.7 V. At that time the JFET turns off and VDD gradually
decreases to 10 V then the procedure repeats. When the power supply is enabled again, the controller is fully
biased and ready to initiate the soft-start sequence. As soon as the gate-drive pulses appear the JFET turn off
and bias is provided by the bootstrap bias generator.
During power down the situation is different as the switching action continues until the VDD bias voltage drops
below the UVLO turn-off threshold of the controller (approximately 8 V). At that time the UCC2897A shuts down
and turns off the 5-V bias rail and returning to startup state when the JFET device is turned on and the CBIAS
capacitor starts charging again. In case the input voltage of the converter is re-established, the UCC2897A
attempts to restart the converter.

UCC2897A

8.3.3 Line Undervoltage Protection
As shown in Figure 20, when the input power-source is removed, the power supply is turned off by the line-
undervoltage protection because the bootstrap winding keeps the VDD bias up as long as switching takes place
in the power stage. As the input voltage of the power supply decreases gradually toward the line-cutoff voltage,
the operating duty cycle of the converter must compensate for the lower input voltage. At minimum input-voltage
the duty cycle nears the maximum value (DMAX). Under these conditions the voltage across the clamp capacitor
approaches the highest value since the transformer must be reset in a relatively short time. The timing diagram
in Figure 20 highlights that in the instance when the converter stops switching the clamp-capacitor voltage might
be at the maximum level. Since the only load of the clamp capacitor is the power transformer, this high voltage
could linger across the clamp capacitor for a long time when the converter is off. With this high voltage present
across the clamp capacitor a soft start would be very dangerous, due to the narrow duty cycle of the main switch
and the long on-time of the clamp switch. This could cause the power transformer to saturate during the next
soft-start cycle.
VOFF
VIN
V CLAMP, MAX
VCLAMP
VSS
TSW
OUT
AUX
Figure 20. Line Undervoltage Shutdown Waveforms, P-Channel
To eliminate this potential hazard the UCC2897A controller, discharge the clamp capacitor during power down
safely. The OUT and the AUX output continues switching while the soft-start capacitor CSS is being slowly
discharged. the function of soft stop is achieved because the AUX pulse-width gradually increases as the clamp
voltage decreases, while never applying the high voltage across the transformer for extended period of time.

UCC2897A

8.3.4 Line Overvoltage Protection
When the line-overvoltage protection is triggered in the UCC2897A controller, the gate-drive signals are
immediately disabled. At the same time, the slow discharge of CSS initiates. While the soft-start capacitor
discharges the gate-drive signals remain disabled. Once VSS = 0.5 V and the overvoltage disappears from the
input of the power supply, operation resumes through a regular soft start of the converter as it is demonstrated in
Figure 21. The pulses of OUT and AUX stop if one of three conditions is met:
1. VDD reaches UVLO off
2. VSS reaches below 2.5 V
3. FB voltage is below 2.5 V
VOVP
VOVH
VIN
VSS
OUT
AUX
Figure 21. Line Overvoltage Sequence, P-Channel

UCC2897A

8.3.5 Pulse Skipping
During output-load current-transients or light-load conditions most PWM controllers must be able to skip some
number of PWM pulses. In an active-clamp topology where the clamp switch is driven complementary to the
main switch, the skipping of pulses applies the clamp voltage across the transformer continuously. Since
operating conditions might require skipping several switching-cycles on the main transistor, saturating the
transformer is very likely if the AUX output remains on.
D = 0 Boundary 2.5 V
FB
TSW
OUT
AUX
Figure 22. Pulse Skipping Operation, P-Channel
To overcome this problem, the UCC2897A family incorporates pulse skipping for both outputs in the controller.
As shown in Figure 22, when a pulse is skipped at the main output (OUT) because the feedback signal demands
zero duty-ratio, the corresponding output pulse on the AUX output is omitted as well. This operation prevents
reverse saturation of the power transformer and preserves the clamp-capacitor voltage level during pulse-
skipping operation.

UCC2897A

8.3.6 Synchronization
The UCC2897A has a bi-directional synchronization pin. In the stand-alone operation the SYNC pin is driven by
the internal oscillator of the UCC2897A which provides an approximately 5-V amplitude square-wave output. This
signal synchronizes other PWM controllers or circuits requiring a constant frequency time-base. The
synchronization output of the UCC2897A is generated when the internal-timing capacitor reaches the peak value.
Therefore, the synchronization waveform does not coincide with the turnon of the main gate-driver output as it is
usually implemented in PWM controllers.
The operation of the oscillator and other relevant waveforms in free-running and synchronized mode are shown
in Figure 23.
SYNC
CT
DMAX
OUT
AUX
Figure 23. A Synchronization Waveform for SYNC Input, P-Channel
The most critical and unique feature of the oscillator is to limit the maximum-operating duty-cycle of the
converter, which is achieved by accurately controlling the charge and discharge intervals of the on-board timing
capacitor. The maximum on-time of the OUT pin, which is also the maximum duty-cycle of the active-clamp
converter, is limited by the charging-interval of the timing capacitor. While the capacitor is reset to the initial
voltage level, OUT is ensured to be off.
When synchronization is used, the rising edge of the signal terminates the charging period and initiates the
discharge of the timing capacitor. Once the timing-capacitor voltage reaches the predefined valley-voltage, a new
charge period starts automatically. This method of synchronization leaves the charge and discharge slopes of the
timing-waveform unaffected thus maintains the maximum duty-cycle of the converter, independent of the
operation mode.
Although the synchronization circuit is level sensitive, the actual synchronization event occurs at the rising-edge
of the waveform, allowing the synchronizing pulse-width to vary significantly while certain limitations are
observed. The minimum pulse-width should be sufficient to ensure reliable triggering of the internal-oscillator
circuitry, therefore it is greater than approximately 50 nanoseconds. The other limiting factor is to keep it shorter
than Equation 10.
(1 – DMAX) × TSYNC
where
• TSYNC is the period of the synchronization frequency (10)
When a pulse wider than that of Equation 10 is connected to the SYNC input, the oscillator is unable to maintain
the maximum duty-cycle, originally set by the timing-resistor ratio (RON, ROFF). Furthermore, the timing-capacitor
waveform has a flat portion as highlighted by the vertical marker in the timing diagram. During this flat portion of
the waveform, both outputs are off, but this state is not compatible with the operation of active-clamp power
converters. Therefore, this operating mode is not recommended.
Note that both outputs of the UCC2897A controller are off if the synchronization signal stays continuously high.
When both UCC2897A outputs are synchronized by tying their SYNC pins together, they operate in-phase. It is
possible to set different maximum duty-cycle limits for both UCC2897A outputs and still synchronize them by a
simple connection between their respective SYNC terminals.

UCC2897A

8.3.7 Gate Drive Connection
The low-side P-channel gate-drive circuit involves a level shifter using a capacitor and a diode which ensures
that the gate-drive amplitude of the auxiliary switch is independent of the actual duty-cycle of the converter.
Detailed analysis and design examples of these and many similar gate-drive solutions are given in Design and
Application Guide for High Speed MOSFET Gate Drive Circuits, SLUP169.
+VIN
CCLAMP
QAUX
QMAIN
AUX
Figure 24. Low-Side P-Channel

UCC2897A

8.3.8 Bootstrap Biasing
Many converters use a bootstrap circuit to generate bias power during steady-state operation. The popularity of
this solution is justified by the simplicity and high-efficiency of the circuit. Usually, bias power is derived from the
main transformer by adding an additional dedicated winding to the structure. Using a flyback converter as shown
in Figure 25, a bootstrap winding provides a quasi-regulated bias voltage for the primary-side control circuits. The
voltage on the VDD pin is equal to the output voltage times the turns-ratio between the output and the bootstrap-
winding in the transformer. Because the output is regulated, the bias rail is regulated as well.
While the same arrangement is used in a forward-type converter, the bootstrap winding off the main-power
transformer is unable to provide a quasi-regulated voltage. In the forward converter, the voltage across the
bootstrap-winding equals the input voltage times the turns-ratio. Accordingly the bias voltage would vary with the
input voltage and exceeds the maximum-operating voltage of the control circuits at high line. A linear regulator
limits and regulates the bias voltage if the power dissipation is acceptable. Another possible solution for the
forward converter is to generate the bias voltage from the output inductor as shown in Figure 26.
Bootstrap Bias 1
+VIN
LOAD
VIN
VDD
CIN
UCC2897A CBIAS
Synchronous
GND Rectifier
QMAIN
Control
--VIN
Figure 25. Bootstrap Bias 1, Flyback Example

UCC2897A

This solution uses the regulated output voltage across the output inductor during the freewheeling period to
generate a quasi-regulated bias for the control circuits.
Bootstrap Bias 2
+VIN
LOAD
VIN
VDD
CIN
UCC2897A
CBIAS
QMAIN
Synchronous
GND Rectifier
Control
--VIN
Figure 26. Bootstrap Bias 2, Forward Example
This solution uses the regulated output voltage across the output inductor during the freewheeling period to
generate a quasi-regulated bias for the control circuits.
Both of the illustrated solutions provide reliable bias-power during normal operation. Note that in both cases, the
bias voltages are proportional to the output voltage. This nature of the bootstrap bias-supply causes the
converter to operate in a hiccup mode under significant overload or under short-circuit conditions as the
bootstrap winding is not able to hold the bias rail above the undervoltage lockout-threshold of the controller.
Another biasing solution, based on the active circuit, is shown on the previous page with components Q10, C18,
R19, D10 and D12. Such a circuit is used in the applications where the allowed biasing-capacitor size is limited
to optimize the board space utilization.

UCC2897A
8.4 Device Functional Modes

The UCC2897A uses a high voltage JFET to provide the start-up current for the controller until a bootstrap-type
rail becomes available on VDD pin. The JFET will be turned off after the VDD pin voltage exceeds the UVLO
threshold. Then the device enters normal operation mode. If the line voltage is abnormal, the device enters line
under voltage or line over voltage mode. During light load or load transient, the device may enter pulse skipping
mode if the feedback voltage FB is less than a certain threshold. Figure 27 shows the mode transition diagram.
Line undervoltage
UVLO, JFET on
protection
Line overvoltage
Normal operation
protection
Pulse skipping
Figure 27. Mode Transition Diagram

UCC2897A
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

The UCC2897A offers a highly integrated solution for active clamp PWM converters. In order to make the part
easier to use, TI has prepared an extensive set of materials to demonstrate the features of the device.
The UCC2897A family offers a highly integrated feature-set and excellent accuracy to control an active-clamp
forward or active-clamp flyback power-converter.
9.2 Typical Application

In order to take advantage of all the benefits integrated in these controllers, the following procedure simplifies the
setup to avoid unnecessary iterations in the design procedure. Refer to Figure 28 setup diagrams for component
names.
RIN2 RIN1
+VIN
RIN4 RIN3
UCC2897A
1 VIN N/C 20
2 N/C LINEOV 19 CBIAS

RDEL
3 RDEL LINEUV 18
RON CHF
4 RON VDD 17
POWER STAGE
ROFF
5 ROFF PVDD 16
CVREF
6 VREF OUT 15
ROT
7 SYNC AUX 14
8 GND PGND 13 --VIN

CF
9 CS SS/SD 12
RSLOPE
10 RSLOPE FB 11
CSS
RF
RVREF ISOLATED FEEDBACK
Figure 28. UCC2897A Typical Application

UCC2897A
Typical Application (continued)

9.2.1 Design Requirements
The required design is an active clamp reset forward converter providing a 3.3-V regulated output at 30 A of load
current, operating from a 48-V input. The design operates over the full 36-V to 72-V telecom input range, and is
able to fully regulate down to zero load current.
Table 1. Design Requirements

Input Characteristics
Input voltage range 36 48 72 V
No load input current VIN = 36 V, IOUT = 0 A 75 100 mA
Input undervoltage limit 35 V
Input overvoltage limit 73 V
Max input current VIN = 36 V, IOUT = 30 A 3 3.25 A
Input voltage ripple VIN = 72 V, IOUT = 30 A 1.5 1.75 VPP
Output Characteristics
Output voltage 36 V < VIN < 72 V, 0 A < IOUT < 30 A 3.25 3.3 3.35 V
Output voltage regulation Line reg (36 V < VIN < 72 V, IOUT = 0 A) 0.00% 0.01%
Load reg (0 A < IOUT < 30 A, VIN = 48 V) 0.06% 0.10%
Output voltage ripple VIN = 48 V, IOUT = 30 A 30 35 mVPP
Output load current 36 V < VIN < 72 V 0 30 A
Output current limit 32 A
Short circuit protection Not provided
Systems Characteristics
Switching frequency 225 250 265 kHz
Control loop bandwidth 36 V < VIN < 72 V, IOUT = 10 A 5 7 kHz
Phase margin 50 60 degrees
Peak efficiency VIN = 36 V 93%
Full load efficiency VIN = 48 V, IOUT = 30 A 91%

UCC2897A
9.2.2 Detailed Design Procedure

Before the controller design begins, the power-stage design must be completed. From the power-stage design
the following operating parameters are required to complete the setup procedure of the controller:
• Switching frequency (fSW)
• Maximum operating duty cycle (DMAX)
• Soft-start duration (tSS)
• Gate-drive power requirements of the external-power MOSFETs (QG(main), QG(aux))
• Bias method and voltage for steady-state operation (bootstrap or bias supply)
• Gate-drive turn-on delay (tDEL)
• Turnon input-voltage threshold (VON)
• Minimum-operating input voltage (VOFF where VIN(OFF) < VIN(on)
• Maximum-operating input voltage (VOVP)
• Overvoltage-protection hysteresis (VOVH)
• The down slope of the output-inductor current-waveform reflected across the primary-side current-sense
resistor (dVL / dt)
9.2.2.1 Oscillator
The two timing elements of the oscillator are calculated from fSW and DMAX by the Equation 11 and Equation 12.
t ON + tDEL
RON =
æsö
36.1´ 10-12 ´ ç ÷
èWø (11)
t OFF - tDEL - 170 ´ 10-9 ´ (s )
ROFF =
æsö
15 ´ 10-12 ´ ç ÷
èWø
where
• DMAX is a dimensionless number between 0 and 1. (12)
9.2.2.2 Soft Start

Once RON is defined, the charge current of the soft-start capacitor is calculated with Equation 13.
V 1
ISS = 0.43 ´ REF ´
2 RON (13)
During soft start, CSS charges from 0 to 5 V by the calculated ISS current. The actual control range of the soft-
start capacitor voltage is between 2.5 and 4.5 V. Therefore, the soft-start capacitor value must be based on this
narrower control range and the required startup time (tSS) according to Equation 14.
ISS ´ t SS
CSS =
4.5 V - 2.5 V (14)
Note that tSS defines a time interval to reach the maximum-current capability of the converter and not the time
required to ramp the output voltage from 0 V to the nominal regulated level. Using an open-loop start-up scheme
does not allow accurate control over the ramp-up time of the output voltage. In addition to the ISS and CSS values,
the time required to reach the nominal output voltage of the converter is a function of the maximum-output
current (current limit), the output capacitance of the converter and the actual load conditions. If it is critical to
implement a tightly-controlled ramp-up time at the output of the converter, the soft start must be implemented
using a closed-loop technique. Closed-loop soft-start implements with the error amplifier of the voltage regulation
loop when the voltage reference is ramped from 0 V to the final steady-state value during the required tSS
startup-time interval.

UCC2897A
9.2.2.3 VDD Bypass Requirements

First, the high-frequency filter capacitor is calculated based on the gate-charge parameters of the external
MOSFETs. If the basic switching-frequency ripple is kept below 0.1-V across CHF, this value is approximated with
Equation 15.
QG(m ain) + QG(aux)
CHF =
0.1 V
(15)
The energy storage requirements are defined primarily by the startup-time (tSS), turnon (approximately 12.7 V),
and turnoff (approximately 8 V) thresholds of the undervoltage-lockout circuit-monitoring of the controller for the
VDD pin. In addition, the bias-current consumption of the entire primary-side control circuit (IDD + IEXT) must be
known. This power consumption is estimated with Equation 16.
PBIAS = [IDD + IEXT + (QG(main) + QG(aux) × fSW)] × VDD (16)
During start-up (tSS), this power is provided by CBIAS while the voltage must remain above the UVLO turn-off
threshold. This relationship is expressed with Equation 17.
PBIAS × tSS < ½ × CBIAS × (12.72 – 82) (17)
Rearranging the equation yields the minimum value for CBIAS as shown in Equation 18.
2 ´ PBIAS ´ t SS
CBIAS >
(
12.72 - 82 ) (18)
Equation 19 may yield a big capacitance value that is not feasible in some applications, such as an additional
energy-storage circuit. A smaller footprint is designed to ease the space demand. Refer to the Application Note
for such a design.
9.2.2.4 Delay Programming

From the power-stage design, the required turn-on delay (tDEL) of the gate-drive signals is defined. The
corresponding RDEL resistor value to implement this delay is given by Equation 19 and Equation 20.
9
RDEL t DEL1 15 u10 9.01u1010
(19)
or
9
RDEL tDEL 2 15 u10 9.01u1010
(20)
9.2.2.5 Input Voltage Monitoring

The input-voltage monitoring functions is governed by the following two expressions (see Equation 21 and
Equation 22) of the voltage at the LINEUV pi.
RIN2
VLINEUV = VON ´ at turn on, and
RIN1 + RIN2 (21)
RIN2 R ´ RIN2
VLINEUV = VOFF ´ + IHYST ´ IN1 at turn off.
RIN1 + RIN2 RIN1 + RIN2 (22)
Since VON and VOFF are given by the power-supply specification, VLINEUV equals the 1.27-V threshold of the line
monitor and IHYST is already defined in Equation 23.
V 1
2 RDEL (23)
The two unknown, RIN1 and RIN2 are fully determined (see Equation 24 and Equation 25).
V - VOFF
RIN1 = ON
IHYST (24)
1.27 V
RIN2 = ´ RIN1
VON - 1.27 V (25)
UCC2897A
9.2.2.6 Current Sense and Slope Compensation

The UCC2897A offers onboard user-programmable slope-compensation. The programming of the correct
amount of slope compensation is accomplished by the appropriate selection of two external resistors, RF and
RSLOPE.
First, the current-sense filter-resistor value (RF) must be calculated based on the desired filtering of the current-
sense signal. The filter consists of two components, CF and RF. The CF filter capacitor is connected between the
CS pin and the GND pin. While the value of CF is selected freely as the first step of the filter design, the value of
CF is minimized to avoid filtering the slope compensation current exiting the CS pin. The recommended range for
the filter capacitance is between 50 pF and 270 pF. The value of the filter resistor is calculated from the filter
capacitance and the desired filter corner frequency fF.
1
RF =
2p ´ fF ´ CF (26)
After RF is defined, RSLOPE is calculated. The amount of slope compensation is defined by the stability
requirements of the inner-peak current-loop of the control algorithm and is measured by the number m. When the
slope of the applied compensation ramp equals the down-slope of the output-inductor current waveform reflected
across the primary-side current-sense resistor (dVL / dt), m = 1. The minimum value of m is 0.5 to prevent
current-loop instability. The best current-mode performance is achieved around m = 1. The increase of m moves
the control closer to the voltage-mode control operation.
In the UCC2897A controllers, slope compensation is implemented by sourcing a linearly-increasing current at the
CS pin. When this current passes through the current-sense filter resistor (RF), the current converts to a slope-
compensation ramp which is characterized by (dVS / dt). The (dVS / dt) of the slope-compensation current is
defined by RSLOPE according to Equation 27.
dlS 5´2 V
=
dt t ON ´ RSLOPE
where
• 2 V is the peak-to-peak ramp amplitude of the internal oscillator waveform
• 5 is the multiplication factor of the internal current mirror (27)
The voltage equivalent of the compensation ramp (dVS / dt) is obtained easily by multiplying with RF. After
introducing the application specific m and (dVL / dt) values, Equation 28 is rearranged for RSLOPE.
5 ´ 2 V ´ RF
RSLOPE =
æ dV ö
t ON ´ m ´ ç L ÷
è dt ø (28)
+VIN
Load
Bootstrap
Bias CCLAMP
VIN
VDD
QAUX Synchronous
Drive
AUX Rectifier
Connection Control
CIN
UCC2897A
QMAIN
OUT
CBIAS
CS
ROT
RCS
GND FB
Secondary--Side
Error Amplifier
--VIN and Isolation
Figure 29. Active Clamp Forward Converter

UCC2897A
9.2.3 Application Curves
100 3.35
90
VO U T - O u tpu t V o ltag e - V
3.33
Ð - Efficiency - %
80
3.31
70
3.29
60
3.27
50
36.0 V 48.0 V 72.0 V 36.0 V 48.0 V 72.0 V

40 3.25
0 5 10 15 20 25 30 0 5 10 15 20 25 30
IOUT - Load Current - A IOUT - Load Current - A
Figure 30. UCC2897A-EVM Efficiency Figure 31. Line and Load Regulation
Figure 32. 10-A Load with 5-A Transient

UCC2897A
10 Power Supply Recommendations

VDD pin is the power supply for the device. There should be a 1-µF capacitor directly from VDD to PGND. VREF
pin provides the supply rail for internal logic, it should be by-passed to GND as close as possible to the device
using a 0.1-µF capacitor. PVDD pin is the supply pin for the power devices, it should be by-passed to PGND
using a 10-µF capacitor.
11 Layout
11.1 Layout Guidelines

• Connection of Two Grounds: GND (analog ground) and PGND (power ground). Two grounds should be
connected using a net tie right between GND pin and PGND pin at IC, and there should be only this
connection between two grounds.
• The bypass capacitors to the VDD pin and VREF pin should be as close as possible to the device GND.
• The timing configuration pins RDEL, RTON, RTOFF, and RSLOPE are connected to the device GND as
close as possible.
• PGND should serve as the current return for the high current output drivers OUT and AUX. The current path
should be as short as possible.
• Connect PVDD and VDD using a 0ohm resistor right at IC of these two pins.
11.2 Layout Example
Figure 33. Layout Example Top Layer

UCC2897A
Layout Example (continued)
Figure 34. Layout Example Bottom Layer

UCC2897A
12 Device and Documentation Support
12.1 Documentation Support

12.1.1 Related Documentation
1. Evaluation Module: UCC2891EVM, 48-V to 3.3-V, 30-A Forward Converter with Active Clamp Reset.
(SLUU407).
2. User’s Guide: Using the UCC2897AEVM, 48-V to 3.3-V Forward Converter with Active Clamp Reset
(SLUU357).
3. Application Note: Understanding and Designing an Active Clamp Current Mode Controlled Converter
(SLUA535).
4. Power Supply Design Seminar Topic: Design Considerations for Active Clamp and Reset Technique, D.
Dalal, SEM1100-Topic 3 (SLUP112).
5. Power Supply Design Seminar Topic: Active Clamp and Reset Technique Enhances Forward Converter
Performance, B. Andreycak, SEM1000-Topic 3 (SLUP108).
6. Power Supply Design Seminar Topic: Design and Application Guide for High Speed MOSFET Gate Drive
Circuits, L. Balogh, SEM1400-Topic 2 (SLUP169).
7. Datasheet: UCC3580, Single Ended Active-Clamp/Reset PWM Controller (SLUS292).
8. Evaluation Module: UCC3580EVM, Flyback Converters, Active Clamp vs. Hard-Switched (SLUU085).
9. Reference Designs: Highly Efficient 100W Isolated Power Supply Reference Design Using UCC3580-1.
Texas Instruments Hardware Reference Design Number PMP206.
10. Reference Designs: Active Clamp Forward Reference Design using UCC3580-1. Texas Instruments
Hardware Reference Design Number PMP368
11. Application Note: Method of Providing Hiccup Operation for UCC2897AEVM (SLUA532)
12. Application Note: External Slope Compensation for UCC2897A in Some Special Applications (SLUA548)
12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TrueDrive, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

UCC2897A
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
UCC2897APW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 UCC2897A
UCC2897APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 UCC2897A
UCC2897ARGPR ACTIVE QFN RGP 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2897A
UCC2897ARGPT ACTIVE QFN RGP 20 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2897A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC2897APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
UCC2897ARGPR QFN RGP 20 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
UCC2897ARGPT QFN RGP 20 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
Pack Materials-Page 1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC2897APWR TSSOP PW 20 2000 356.0 356.0 35.0
UCC2897ARGPR QFN RGP 20 3000 356.0 356.0 35.0
UCC2897ARGPT QFN RGP 20 250 210.0 185.0 35.0
TUBE
T - Tube
height L - Tube length
W - Tube
width
B - Alignment groove width

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
UCC2897APW PW TSSOP 20 70 530 10.2 3600 3.5
PACKAGE OUTLINE
PW0020A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
6.6 C
TYP PLANE
A 6.2
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
6.6 5.85
6.4
NOTE 3
10
11
0.30
20X
4.5 0.19 1.2 MAX
B
4.3
NOTE 4 0.1 C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE 0.15
0.05
0.75
0.50
0 -8
DETAIL A
A 20
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A TSSOP - 1.2 mm max height
20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20
SYMM
18X (0.65)
10 11
(5.8)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING
EXPOSED METAL EXPOSED METAL
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A TSSOP - 1.2 mm max height
20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20
SYMM
18X (0.65)
10 11
(5.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RGP 20 VQFN - 1 mm max height
4 x 4, 0.5 mm pitch VERY THIN QUAD FLATPACK
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224735/A
www.ti.com
PACKAGE OUTLINE
RGP0020D VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
B 4.1 A
3.9
(0.1) TYP
4.1
3.9
PIN 1 INDEX AREA
LEAD DETAIL "A"

OPTION
C
1 MAX
SEATING PLANE
0.05 0.08 C
0.00 2.8
2.6
2 (0.2) TYP
6 10
LEAD DETAIL "A"

16X 0.5
5
11
21 SYMM
2
15
20X 0.5
1
0.3
PIN 1 IDENTIFICATION
(OPTIONAL) 16
20
SYMM
20X 0.30
0.18
0.1 C A B
0.05 C
4219028/A 12/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
(3.8)
( 2.7)
(2)
20 16
20X (0.6)
20X (0.24)
1 15
16X (0.5)
SYMM
21
(2) (3.8)
(1.1)
5
(R0.05) TYP 11
(Ø0.2) VIA
TYP
6 10
(1.1)
SYMM
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX 0.07 MIN
ALL AROUND METAL ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK METAL UNDER
OPENING SOLDER MASK
NON SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED
SOLDER MASK DETAILS 4219028/A 12/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
(3.8)
(2)
SYMM
20 16
20X (0.6) 21
20X (0.24)
1 15
16X (0.5)
SYMM
(2) (3.8)
(0.695)
5 11
(R0.05) TYP
METAL
6 10 TYP
4X ( 1.19)
(0.695)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
77% PRINTED COVERAGE BY AREA
SCALE: 20X
4219028/A 12/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
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UCC2897A Advanced Current-Mode Active-Clamp PWM Controller

Typical Application Diagram

Changes from Revision F (November 2017) to Revision G Page

• Changed Modified Typical Application diagram .................................................................................................................... 1

Changes from Revision E (April 2015) to Revision F Page

Changes from Revision D (July 2009) to Revision E Page

2 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated

Product Folder Links: UCC2897A

CYCLE-BY- 110-V HV JFET PART NUMBER

6 Pin Configuration and Functions

Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 3

4 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated

Product Folder Links: UCC2897A

Pin Functions (continued)

7.2 ESD Ratings

7.3 Recommended Operating Conditions

Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 5

7.4 Thermal Information

7.5 Electrical Characteristics

(1) Set VDD above the start threshold before setting at 12 V.

Product Folder Links: UCC2897A

Electrical Characteristics (continued)

7.6 Timing Requirements

Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 7

8 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated

Product Folder Links: UCC2897A

7.7 Typical Characteristics

IDD -- Supply Current -- mA

External VDD Current -- mA 15

Figure 5. Typical Startup Current Available From VDD vs.

Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 9

Typical Characteristics (continued)

fSW -- Switching Frequency -- Hz

DMAX -- Maximum Duty Cycle -- %

0.4 Cycle-by-Cycle Current Limit 2.20

10 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated

Product Folder Links: UCC2897A

Typical Characteristics (continued)

Rise Time 700

tDEL -- Delay Time -- ns

OUT to AUX tDEL -- Delay Time -- μs

Figure 18. Reference Voltage vs. Temperature

Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 11

8.2 Functional Block Diagram

Copyright © 2017, Texas Instruments Incorporated

12 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated

Product Folder Links: UCC2897A

8.3 Feature Description

Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 13

Feature Description (continued)

14 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated

Product Folder Links: UCC2897A

Feature Description (continued)

Copyright © 2008–2020, Texas Instruments Incorporated Submit Documentation Feedback 15

Feature Description (continued)

16 Submit Documentation Feedback Copyright © 2008–2020, Texas Instruments Incorporated

Product Folder Links: UCC2897A