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Digital Logic Design Lab Final Exam Firs

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Digital Logic Design Lab Final Exam Firs

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amrh23001
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Digital Logic Design Lab - A final exam

Department of Computer Information Systems First semester 2011/2012


School of Information Technology
_______________________ :‫اسم الطالب‬
Al-Balqa Applied University
Salt, Jordan ____________________ :‫موعد المختبر‬

‫) ديانا طهراوي‬5( ،‫) اسماء الختوم‬4( ،‫) كرم غنيمات‬3( ،‫) وفاء ضبابات‬2( ،‫) سليمان بني أحمد‬1( :‫ضع دائرة حول اسم مدرسك‬

1B 2 3 4 5 6 7 8 9 10

11 12 13 14 15 16 17 18 19 20

9. The red light on the LED indicates to result = 0.


Question 1: Multiple choice questions (20 points) a. True
b. False
1. The output of a logic gate can be one of two _____.
a. Inputs 10. The output of an AND gate with three inputs, A, B, and
b. Gates C, is HIGH when
c. States a. A = 1, B = 1, C = 0
b. A = 0, B = 0, C = 0
d. none
c. A = 1, B = 1, C = 1
d. A = 1, B = 0, C = 1
2. Full adder is constructed by using …………….
a. Two Half Adder& one OR gate 11. The Boolean expression for a 3-input AND gate is
b. Two OR gate &one HA a. X = AB
c. One HA & two OR gate b. X = ABC
d. One OR gate & one HA c. X = A + B + C
d. X = AB + C
3. A half adder gives……………. Output(s)
a. 1
b. 2 12. Logic states can only be ___ or 0.
a. 3
c. 3
b. 2
d. none of the above
c.1
d.0
4. A full adder gives……….. Output(s)
a. 1
b. 2 13.The output of a ____ gate is only 1 when all of its inputs
c. 3 are 1.
a. NOR
d. non of this
b. XOR
c. AND
5. The output of Half adder is in the form of.
d. NOT
a. Sum
b. carry
c. sum & carry 14. A NAND gate is equivalent to an AND gate plus a ….
d. none of these gate put together.
a. NOR
6. Logic 0 is represented by GND practically b. NOT
a. True c. XOR
b. False d. none

7. A'B' = (AB)' 15. Half adder circuit is ______.


a. True a. Half of an AND gate
b. False b. A circuit to add two bits together
c. Half of a NAND gate
8. AB = (A' + B')' d. none of above
a. True
b. False

Page 1 of 2
16. Which logic gate does the truth table shown in figure 1
have?
a. A two-input AND gate. Figures
b. A two-input OR gate.
c. An exclusive OR gate.
d. An exclusive NOR gate.

17. What Boolean expression describes the output X of the


arrangement shown in figure 2?
a. X = A + B + C
b. X = A.(B + C)
c. X = (A.B) + C
d. X = A + (B.C)

18. In the Karnaugh map shown in figure 3, which of the


loops shown represents a legal grouping?
a. x Figure 1
b. y
c. z
d. w

19. Half adder consists of. …… and …..Gates


a. EX-OR, AND
b. EX-OR, OR
c. EX-OR, NOT
d. None of the above
Figure 2
20. In half adder EX-OR gate output is …………
a. Carry
b. Remainder
c. Sum
d. None of the above

Question 2 (10 points): Write the simplified Boolean


expression that is represented by the K-Map shown in
figure 3.

Figure 3
Question 3 (20 points): Redraw the circuit shown in
figure 2 using NAND gates only.

Page 2 of 2

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