Department of Electronics and Communication Engineering

VLSI Design Lab

LIST OF EXPERIMENTS

Cycle-1

Synthesize the following experiments using Xilinx software:

1. 2 to 4 and 3 to 8 decoder
2. 8 to 3 Encoder and 4 to 2 priority Encoder
3. 8 to 1 multiplexer and 1 to 8 Demultiplexer
4. Flip-flops(SR,JK,D,T)
5. 4-bit shift register
6. 4-bit counter
7. 4-bit Universal Shift Register

Cycle-2

Design layouts for the following experiments using Microwind /Mentor Graphics software:

8. Basic logic gates

9. Universal gates
10. AOI logic
11. Boolean expression (SOP and POS Forms)
12. CMOS inverter
 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

1(a) 2 To 4 Decoder

Aim: To design a 2-to-4 decoder using VHDL and verify its operation using
Xilinx Vivado software.

Software used: VIVADO 2018.1.

Hardware required: NEXYS Artix-7.

Theory: The name “Decoder” means to translate or decode coded information

from one format into another, so a digital decoder transforms a set of digital
input signals into an equivalent decimal code at its output

A decoder is a combinational circuit that converts binary information from n

input lines to a maximum of m=2n unique output lines.

2-to-4 Binary Decoder

The 2-to-4line binary decoder depicted above consists of an array of four AND
gates. The 2 binary inputs labelled A and B are decoded into one of 4 outputs
q3q2q1q0, hence the description of 2-to-4 binary decoder. Each output represents
one of the minterms of the 2 input variables.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

a1a0 q3q2q1q0
00 0001
01 0010
10 0100
11 1000

The binary inputs a1 and a0 determine which output line from q0 to q3 is

“HIGH” at logic level “1” while the remaining outputs are held “LOW” at logic
“0” so only one output can be active (HIGH) at any one time.Therefore,
whichever output line is “HIGH” identifies the binary code present at the input,
in other words it “decodes” the binary input.

Procedure:

 Double click on VIVADO 2018.1 software

 Click on create project in Quick start menu and create new project
Quick start  Create projectnextRTL projectAdd sources(Create file select file
type as VHDL File name)ok and next Add constraints(create file select file type as
XDL File name)ok and next)  below window will be open. select default parts and
click on next finish.
 Create inputs and outputs in define module according to the project.
 Then in Sources window source file (file name.vhd), click on that and add the logic in
.vhd file window.
 Project manager simulation (run behavioural simulation).
 In the objects window  give input valuesRight click on input force constant
force value.
 Click on run for ten microseconds or Shift+F2 and observe the output waveforms.
 RTL analysis open elaborated design click on ok
Then schematic output will be displayed
 Click on Run SYNTHESIS in Project Manager windowLaunch Run window 
Change No of jobs as “4” Click on OKIf NO ERRORS Synthesis Completed Window
will be opened
 Project ManagerRun IMPLEMENTATIONClick on OK then
IMPLEMENTATION Completed Window will be opened Click on Cancel
 Click on LAYOUT in File Menu then I/O PlanningAll ports window will be open in the
downside Select Scalar PortsAssign Outputs & Inputs as per kit port number.
 Connect the KIT and switch on the power supply Click on SAVE in File Menu  Save
constraints tab will be open then click on Ok.
 Project ManagerRunIMPLEMENTATIONClick on OKIMPLEMENTATION
Completed Window will be opened.
Aditya Institute of Technology and Management, Tekkali
 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

 Project ManagerClick on Generate Bit streamClickOn OK Launch Runs tab will
be opened Click on OK Bit Stream generation completed tab will be opened Open
hardware Manger  Click on OKhardware Manger tab will open then click on Open
TargetAuto Connect Click on Program deviceProgram device will Opened  Click
On Program Program will be dumped into the KIT  Yellow LED will Glow.
 Verify the Program by using switches and led’s on the KIT

Code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY decoder2x4 IS
port (a: in std_logic_vector(1 downto 0);
q:out std_logic_vector(3 downto 0));
END decoder2x4;
ARCHITECTURE behavioral OF decoder2x4 IS
BEGIN
process(a)
begin
case(a) is
when "00" => q <= "0001";
when "01" => q<= "0010";
when "10" => q<= "0100";
when "11" => q<= "1000";
when others => q<= "0000";
end case;

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

end process;
end behavioural;

Simulation Results:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

NETLIST:

set_property IOSTANDARD LVCMOS33 [get_ports {a[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {a[0]}]

set_property PACKAGE_PIN V10 [get_ports {a[0]}]

set_property PACKAGE_PIN U11 [get_ports {a[1]}]

set_property PACKAGE_PIN V11 [get_ports {q[0]}]

Aditya Institute of Technology and Management, Tekkali
 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

set_property PACKAGE_PIN V12 [get_ports {q[1]}]

set_property PACKAGE_PIN V14 [get_ports {q[2]}]

set_property PACKAGE_PIN V15 [get_ports {q[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {q[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {q[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {q[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {q[0]}]

Result: 2-to-4 decoder is designed by VHDL code and verified its operation by
using Xilinx Vivado software.

1(b).3 To 8 Decoder
Aim:To design a 3-to-8 decoder using VHDL and verify its operation using
Xilinx Vivado software.

Software used: VIVADO 2018.1.

Hardware required: NEXYS Artix-7.

Theory:A decoder is a combinational logic circuit that is used to change the

code into a set of signals. It is the reverse process of an encoder. A decoder
circuit takes multiple inputs and gives multiple outputs. A decoder circuit takes
binary data of n inputs into 2n unique output. The 3 to 8 decoder has three inputs
like a2, a1 & a0 and 8 outputs from d7 – d0.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

a3a2a1 d7d6d5d4d3d2d1d0
000 00000001
001 00000010
010 00000100
011 00001000
100 0001000
101 00100000
01000000
110
111 10000000

Code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

USE ieee.std_logic_arith.all;
ENTITY decoder3to8 IS
port (a:in std_logic_vector(2 downto 0);
d:out std_logic_vector(7 downto 0));
END ENTITY decoder3to8;
ARCHITECTURE behavioral OF decoder3to8 IS
BEGIN
process(a)
begin
case(a) is
when "000" =>d<= "00000001";
when "001" =>d<= "00000010";
when "010" =>d <= "00000100";
when "011" =>d <= "00001000";
when "100" =>d <= "00010000";
when "101" =>d<= "00100000";
when "110" =>d <= "01000000";
when "111" =>d <= "10000000";
when others =>d <= "00000000";
end case;
end process;
END behavioral;

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Simulation Results:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

NETLIST:

set_property PACKAGE_PIN J15 [get_ports {a[2]}]

set_property PACKAGE_PIN L16 [get_ports {a[1]}]

set_property PACKAGE_PIN M13 [get_ports {a[0]}]

set_property PACKAGE_PIN V11 [get_ports {d[0]}]

set_property PACKAGE_PIN V12 [get_ports {d[1]}]

set_property PACKAGE_PIN V14 [get_ports {d[2]}]

set_property PACKAGE_PIN V15 [get_ports {d[3]}]

set_property PACKAGE_PIN T16 [get_ports {d[4]}]

set_property PACKAGE_PIN U14 [get_ports {d[5]}]

set_property PACKAGE_PIN T15 [get_ports {d[6]}]

set_property PACKAGE_PIN V16 [get_ports {d[7]}]

Result:3-to-8 decoder is designed by VHDL code and verified its operation by

using Xilinx Vivado software.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

2(a)8-To-3 Encoder
Aim:To design a 8-to-3 encoder using VHDL and verify its operation using
Xilinx Vivado software.
Software used: VIVADO 2018.1.
Hardware required: NEXYS Artix-7.
Theory: An Encoder is a combinational circuit that performs the reverse
operation of Decoder.It has maximum of 2^n input lines and ‘n’ output lines,
hence it encodes the information from 2^n inputs into an n-bit code. It will
produce a binary code equivalent to the input, which is active High. Therefore,
the encoder encodes 2^n input lines with ‘n’ bits.
The 8 to 3 Encoder or octal to Binary encoder consists of 8 inputs: D7 to D0
and 3 outputs: A, B & C. Each input line corresponds to each octal digit and
three outputs generate corresponding binary code.
The figure below shows the logic symbol of octal to binary encoder:

Where A= D(4) + D(5) + D(6) + D(7);

B = D(2) + D(3) + D(6) + D(7);
C = D(1) + D(3) + D(5) + D(7);

Procedure:

 Double click on VIVADO 2018.1 software

 Click on create project in Quick start menu and create new project
Quick start  Create projectnextRTL projectAdd sources(Create file select file
type as VHDL File name)ok and next Add constraints(create file select file type as
XDL File name)ok and next)  one window will be opened. select default parts and
click on next finish.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

 Create inputs and outputs in define module according to the project.

 Then in Sources window source file (file name.vhd), click on that and add the logic in
.vhd file window.
 Project manager simulation (run behavioural simulation).
 In the objects window  give input valuesRight click on input force constant
force value.
 Click on run for ten microseconds or Shift+F2 and observe the output waveforms.
 RTL analysis open elaborated design click on ok
Then schematic output will be displayed
 Click on Run SYNTHESIS in Project Manager windowLaunch Run window 
Change No of jobs as “4” Click on OKIf NO ERRORS Synthesis Completed Window
will be opened
 Project ManagerRunIMPLEMENTATIONClick on OK then
IMPLEMENTATION Completed Window will be opened Click on Cancel
 Click on LAYOUT in File Menu then I/O PlanningAll ports window will be open in the
downside Select Scalar PortsAssign Outputs & Inputs as per kit port number.
 Connect the KIT and switch on the power supply Click on SAVE in File Menu  Save
constraints tab will be open then click on Ok.
 Project ManagerRunIMPLEMENTATIONClick on OKIMPLEMENTATION
Completed Window will be opened.
 Project ManagerClick on Generate Bit streamClickOn OK Launch Runs tab will
be opened Click on OK Bit Stream generation completed tab will be opened Open
hardware Manger  Click on OKhardware Manger tab will open then click on Open
TargetAuto Connect Click on Program deviceProgram device will Opened  Click
On Program Program will be dumped into the KIT  Yellow LED will Glow.
 Verify the Program by using switches and led’s on the KIT

Code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY encoder8to3 IS
port(D : in std_logic_vector( 7 downto 0);
A,B,C : out std_logic);
END ENTITY encoder 8to3;
ARCHITECTURE behavioral OF encoder8to3 IS
BEGIN

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

process(D)
begin
A<=D(4) or D(5) or D(6) or D(7);
B<=D(2) or D(3) or D(6) or D(7);
C<=D(1) or D(3) or D(5) or D(7);
end process;
end behavioral;

Simulation results:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

NETLIST:

set_property IOSTANDARD LVCMOS33 [get_ports {D[0]}]

set_property PACKAGE_PIN J15 [get_ports {D[0]}]

set_property PACKAGE_PIN L16 [get_ports {D[1]}]

set_property PACKAGE_PIN M13 [get_ports {D[2]}]

set_property PACKAGE_PIN R15 [get_ports {D[3]}]

Aditya Institute of Technology and Management, Tekkali
 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

set_property PACKAGE_PIN R17 [get_ports {D[4]}]

set_property PACKAGE_PIN T18 [get_ports {D[5]}]

set_property PACKAGE_PIN U18 [get_ports {D[6]}]

set_property PACKAGE_PIN R13 [get_ports {D[7]}]

set_property PACKAGE_PIN V11 [get_ports A]

set_property PACKAGE_PIN V12 [get_ports B]

set_property PACKAGE_PIN V14 [get_ports C]

Result:8-to-3 encoder is designed by VHDL code and verified its operation by

using Xilinx Vivado software.

2(b) 4-to-2 parity encoder

Aim: To design a 4-to-2 parity encoder using VHDL and verify its operation
using Xilinx Vivado software.
Software required: VIVADO 2018.1.
Hardware required: NEXYS Artix-7.
Theory: One of the main disadvantages of standard digital encoders is that they
can generate the wrong output code when there is more than one input present at
logic level “1”. For example, if we make inputs D1 and D2 HIGH at logic “1”
both at the same time, the resulting output is neither at “01” or at “10” but will
be at “11” which is an output binary number that is different to the actual input
present. Also, an output code of all logic “0”s can be generated when all of its
inputs are at “0” OR when input D0 is equal to one.
One simple way to overcome this problem is to “Prioritise” the level of each
input pin. So, if there is more than one input at logic level “1” at the same time,
the actual output code would only correspond to the input with the highest
designated priority. Then this type of digital encoder is known commonly as
a Priority Encoder or P-encoder for short.
In 2 to 4 parity encoder if d3=1 irrespective of other inputs Y=11, if d3=0 and
d2=1 then Y=10 if d3=0,d2=0 and d1=1 then Y=01,if d3=0,d2=0,d1=0 and
d0=1 then Y=00,if all the inputs are 0’s then v=0 indicates invalid state.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Code:
Library ieee;
USE ieee.std_logic_1164.all;
Entity priority4to2 is
Port(D:in std_logic_vector(3 downto 0);
Q:out std_logic_vector(1 downto 0);
V:out std_logic);
End priority4to2;
Architecture behavioral of priority4to2 is
Begin
Process(D)
Begin
If(D(3)=’1’) then Q<=”11”;v<=’1’;
elsif(D(2)=’1’) then Q<=”10”;v<=’1’;
elsif(D(1)=’1’) then Q<=”01”;v<=’1’;
elsif(D(0)=’1’) then Q<=”00”;v<=’1’;
else v<=’0’
end if;
end process;

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

end behavioral;
Simulation Results:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

NETLIST:

set_property IOSTANDARD LVCMOS33 [get_ports {D[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {D[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Q[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Q[0]}]
set_property PACKAGE_PIN V10 [get_ports {D[3]}]
set_property PACKAGE_PIN U11 [get_ports {D[2]}]
set_property PACKAGE_PIN U12 [get_ports {D[1]}]
set_property PACKAGE_PIN H6 [get_ports {D[0]}]
set_property PACKAGE_PIN V11 [get_ports {Q[1]}]
set_property PACKAGE_PIN V12 [get_ports {Q[0]}]

Result:4-to-2 parity encoder is designed by VHDL code and verified its

operation by using Xilinx Vivado software.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

3(a)8 X 1 MULTIPLEXER
Aim: To design an 8X1 multiplexer using VHDL and verify its operation using
Xilinx Vivado software.

Software used:VIVADO 2018.1.

Hardware required: NEXYS Artix-7.

Theory:The multiplexer or MUX is a digital switch, also called a data

selector. It has 2n inputs, n selection lines, and one output

8-to-1 Multiplexer

An 8-to-1 multiplexer consists of eight data inputs D0 through D7, three input
select lines S0 through S2, and a single output line Y. Depending on the select
lines combinations, the multiplexer selects the inputs.

The below figure shows the block diagram of an 8-to-1 multiplexer with enable
input that can enable or disable the multiplexer. Since the number of data bits
given to the MUX are eight, then 3 bits (2 3 = 8) are needed to select one of the
eight data bits.

S2 S1 S0 Y
0 0 0 D0

0 0 1 D1

0 1 0 D2

0 1 1 D3

1 0 0 D4

1 0 1 D5

1 1 0 D6

1 1 1 D7

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

From the above truth table, the Boolean equation for the output is given as:

Y = S01 S11 S21 D0 + S01 S11 S2 D1 + S01 S1 S21 D2 + S01 S1 S2 D3 +

S01 S11 S2 D4 + S0 S11 S2 D5 + S0 S1 S21 D6 + S0 S1 S2 D7

Procedure:

 Double click on VIVADO 2018.1 software

 Click on create project in Quick start menu and create new project
Quick start  Create projectnextRTL projectAdd sources(Create file select file
type as VHDL File name)ok and next Add constraints(create file select file type as
XDL File name)ok and next)  one window will be opened. select default parts and
click on next finish.
Create inputs and outputs in define module according to the project.
 Then in Sources window source file (file name.vhd), click on that and add the logic in
.vhd file window.
 Project manager simulation (run behavioural simulation).
 In the objects window  give input valuesRight click on input force constant
force value.
 Click on run for ten microseconds or Shift+F2 and observe the output waveforms.
 RTL analysis open elaborated design click on ok Then schematic output will be
displayed
 Click on Run SYNTHESIS in Project Manager windowLaunch Run window 
Change No of jobs as “4” Click on OKIf NO ERRORS Synthesis Completed Window
will be opened

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

 Project ManagerRun IMPLEMENTATIONClick on OK then

IMPLEMENTATION Completed Window will be opened Click on Cancel
 Click on LAYOUT in File Menu then I/O PlanningAll ports window will be open in the
downside Select Scalar PortsAssign Outputs & Inputs as per kit port number.
 Connect the KIT and switch on the power supply Click on SAVE in File Menu  Save
constraints tab will be open then click on Ok.
 Project ManagerRun IMPLEMENTATIONClick on OKIMPLEMENTATION
Completed Window will be opened.
 Project ManagerClick on Generate Bit streamClick On OK Launch Runs tab will
be opened Click on OK Bit Stream generation completed tab will be opened Open
hardware Manger  Click on OKhardware Manger tab will open then click on Open
TargetAuto Connect Click on Program deviceProgram device will Opened  Click
On Program Program will be dumped into the KIT  Yellow LED will Glow.
 Verify the Program by using switches and led’s on the KIT

Code:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity mux8to1 is

Port ( D : in STD_LOGIC_VECTOR (7 downto 0);

S: in STD_LOGIC_VECTOR (2 downto 0);

Z : out STD_LOGIC);

end mux8to1;

architecture Behavioral of mux8to1 is

begin

process(S,D)

begin

case(S) is

when "000" => Z <= D(0);

when "001" => Z <= D(1);

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

when "010" => Z <= D(2);

when "011" => Z <= D(3);

when "100" => Z <= D(4);

when "101" => Z <= D(5);

when "110" => Z <= D(6);

when "111" => Z <= D(7);

when others => Z <= 'U';

end case;

end process;

end Behavioral;

Simulation results:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

NETLIST:

set_property IOSTANDARD LVCMOS33 [get_ports {d[7]}]

set_property IOSTANDARD LVCMOS33 [get_ports {d[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {d[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {d[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {d[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {d[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {d[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {d[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s[0]}]
Aditya Institute of Technology and Management, Tekkali
 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

set_property PACKAGE_PIN V10 [get_ports {d[7]}]

set_property PACKAGE_PIN U11 [get_ports {d[6]}]
set_property PACKAGE_PIN U12 [get_ports {d[5]}]
set_property PACKAGE_PIN H6 [get_ports {d[4]}]
set_property PACKAGE_PIN T13 [get_ports {d[3]}]
set_property PACKAGE_PIN R16 [get_ports {d[2]}]
set_property PACKAGE_PIN U8 [get_ports {d[1]}]
set_property PACKAGE_PIN T8 [get_ports {d[0]}]
set_property PACKAGE_PIN R13 [get_ports {s[2]}]
set_property PACKAGE_PIN U18 [get_ports {s[1]}]
set_property PACKAGE_PIN T18 [get_ports {s[0]}]

Result: 8X1 multiplexer is designed by VHDL code and verified its operation
by using Xilinx Vivado software.

3b) 1 to 8 Demultiplexer
Aim: To design 1X8 demultiplexer using VHDL and verify its operation using
Xilinx Vivado software.

Software used: VIVADO 2018.1.

Hardware required: NEXYS Artix-7.

Theory: A Demultiplexer is a combinational logic circuit that

receives the information on a single input line and transmits the same
information over one of ‘2n’ possible output lines, the output lines are
selected by the n selection lines. Demultiplexers are called Data
Distributors.

1-to-8 Demultiplexer: The below figure shows the block diagram of a 1-to-
8 demultiplexer that consists of single input D, three select inputs S2, S1 and
S0, and eight outputs from Y0 to Y7.It is also called a 3-to-8 demultiplexer
due to its three select input lines and 8 output lines. It distributes one input line
to one of 8 output lines depending on the combination of select inputs.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

From this truth table, the Boolean expressions for all the outputs can be written
as follows.

Y0 = S21 S11 S01 D

Y1 = S21 S11 S0 D

Y2 = S21 S1 S01 D

Y3 = S21 S1 S0 D

Y4 = S2 S11 S01 D

Y5 = S2 S11 S0 D

Y6 = S2 S1 S01 D

Y7 = S2 S1 S0 D

From these obtained equations, the logic diagram of this demultiplexer can be
implemented by using eight 4-input AND gates and three NOT gates as shown
in below figure. Different combinations of the select lines activates one AND
gate at given time, such that data input will appear at the corresponding output.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Code:

Library ieee;
USE ieee.std_logic_1164.all;
Entity Demux1to8 is
Port(S: in std_logic_vector(2 downto 0);
D: out std_logic_vector(7 downto 0);
Y: in std_logic);
End Demux1to8;
Architecture behavioral of Demux1to8 is
Begin
Process(S,Y)

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Begin
D(0)<= not S(2) and not S(1) and not S(0) and Y ;
D(1)<=not S(2) and not S(1) and S(0) and Y ;
D(2)<=not S(2) and S(1) and not S(0) and Y ;
D(3)<=not S(2) and S(1) and S(0) and Y;
D(4)<= S(2) and not S(1) and not S(0) and Y;
D(5)<=S(2) and not S(1) and S(0) and Y;
D(6)<=S(2) and S(1) and not S(0) and Y;
D(7)<=S(2) and S(1) and S(0) and Y;
end process;
end behavioral;

Simulation Results:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

NETLIST:

set_property IOSTANDARD LVCMOS33 [get_ports {D[7]}]

set_property IOSTANDARD LVCMOS33 [get_ports {D[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {S[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {S[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {S[0]}]
set_property PACKAGE_PIN V12 [get_ports {D[6]}]
set_property PACKAGE_PIN V14 [get_ports {D[5]}]
set_property PACKAGE_PIN V15 [get_ports {D[4]}]
set_property PACKAGE_PIN T16 [get_ports {D[3]}]
set_property PACKAGE_PIN U14 [get_ports {D[2]}]
set_property PACKAGE_PIN T15 [get_ports {D[1]}]
set_property PACKAGE_PIN V16 [get_ports {D[0]}]
set_property PACKAGE_PIN V10 [get_ports {S[2]}]
set_property PACKAGE_PIN V11 [get_ports {D[7]}]
set_property PACKAGE_PIN U11 [get_ports {S[1]}]
set_property PACKAGE_PIN U12 [get_ports {S[0]}]

Result: 1X8 demultiplexer is designed by VHDL code and verified its

operation by using Xilinx Vivado software.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

4. S-R Flip flop, J-K flip flop, D Flip flop & T Flip flop
Aim: To design S-R Flip flop, J-K flip flop, D Flip flop & T Flip flops using
VHDL and verify its operation using Xilinx Vivado software.

Software Required:VIVADO 2018.1.

Hardware required: NEXYS Artix-7. .

Theory:

1) SR Flip-Flop
Flip flop is a memory element which stores 1 bit of information
A basic NAND gate SR flip-flop circuit provides feedback from both of its
outputs back to its opposing inputs and is commonly used in memory circuits to
store a single data bit. Then the SR flip-flop actually has three
inputs, Set, Reset and its current output Q relating to it’s current state or history.
The term “Flip-flop” relates to the actual operation of the device, as it can be
“flipped” into one logic Set state or “flopped” back into the opposing logic
Reset state.

Logic diagram:

Truth table:

S R Qout state
0 0 Qin No change
0 1 0 Reset

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

1 0 1 Set
1 1 X Invalid

2) J-K Flip flop:

The JK flip flop is basically a gated SR flip-flop with the addition of a clock
input circuitry that prevents the illegal or invalid output condition that can occur
when both inputs S and R are equal to logic level “1”. Due to this additional
clocked input, a JK flip-flop has four possible input combinations, “logic 1”,
“logic 0”, “no change” and “toggle”.

Truth table:

J K Qout State
0 0 Qin No change
0 1 0 Reset
1 0 1 Set
1 1 Q in 1 Toggle

3) D-Flip Flop:
We connect the inverter between the Set and Reset inputs for producing another
type of flip flop circuit called D flip flop, Delay flip flop, D-type Bistable, D-
type flip flop.

The D flip flop is the most important flip flop from other clocked types. It
ensures that at the same time, both the inputs, i.e., S and R, are never equal to 1.
The Delay flip-flop is designed using a gated SR flip-flop with an inverter
connected between the inputs allowing for a single input D(Data).

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Truth table

4) T Flip flop:
In T flip flop, "T" defines the term "Toggle". In SR Flip Flop, we provide only a
single input called "Toggle" or "Trigger" input to avoid an intermediate state
occurrence. Now, this flip-flop work as a Toggle switch. The next output state is
changed with the complement of the present state output. This process is known
as "Toggling"'.

We can construct the "T Flip Flop" by making changes in the "JK Flip Flop".
The "T Flip Flop" has only one input, which is constructed by connecting the
input of JK flip flop. This single input is called T. In simple words, we can
construct the "T Flip Flop" by converting a "JK Flip Flop". Sometimes the
"TFlip Flop" is referred to as single input "JK Flip Flop".

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Logic diagram:

Truth table

T Qout
0 Qin
1 Qin1

Procedure:

 Double click on VIVADO 2018.1 software

 Click on create project in Quick start menu and create new project
Quick start  Create projectnextRTL projectAdd sources(Create file select file
type as VHDL File name)ok and next Add constraints(create file select file type as
XDL File name)ok and next)  one window will be opened. select default parts and
click on next finish.
 Create inputs and outputs in define module according to the project.
 Then in Sources window source file (file name.vhd), click on that and add the logic in
.vhd file window.
 Project manager simulation (run behavioural simulation).
 In the objects window  give input valuesRight click on input force constant
force value.
 Click on run for ten microseconds or Shift+F2 and observe the output waveforms.
 RTL analysis open elaborated design click on ok
Then schematic output will be displayed
 Click on Run SYNTHESIS in Project Manager windowLaunch Run window 
Change No of jobs as “4” Click on OKIf NO ERRORS Synthesis Completed Window
will be opened
Aditya Institute of Technology and Management, Tekkali
 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

 Project ManagerRun IMPLEMENTATIONClick on OK then

IMPLEMENTATION Completed Window will be opened Click on Cancel
 Click on LAYOUT in File Menu then I/O PlanningAll ports window will be open in the
downside Select Scalar PortsAssign Outputs & Inputs as per kit port number.
 Connect the KIT and switch on the power supply Click on SAVE in File Menu  Save
constraints tab will be open then click on Ok.
 Project ManagerRun IMPLEMENTATIONClick on OKIMPLEMENTATION
Completed Window will be opened.
 Project ManagerClick on Generate Bit streamClick On OK Launch Runs tab will
be opened Click on OK Bit Stream generation completed tab will be opened Open
hardware Manger  Click on OKhardware Manger tab will open then click on Open
TargetAuto Connect Click on Program deviceProgram device will Opened  Click
On Program Program will be dumped into the KIT  Yellow LED will Glow.
 Verify the Program by using switches and led’s on the KIT

Code: (D- Flip-flop)

library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(Clk, D,: in std_logic;
QOUT : out std_logic);
end dff;
architecture behaviouarl of dff is
begin
process (Clk)
begin
if (Clk'event and Clk='1') then
QOUT <= D;
end if;
end process;
end behaviouarl;

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

------SR FLIPFLOP----
library ieee;
use ieee.std_logic_1164.all;
entity srff is
port(Clk,S,R,QIN : in std_logic;
QOUT : out std_logic);
end srff;
architecture behaviouarl of srff is
BEGIN
process (Clk,S,R,QIN)
begin
if (Clk'event and Clk='1') then
QOUT <= S OR ((NOT R) AND QIN);
end if;
end process;
end behaviouarl;

------JK FLIPFLOP----
library ieee;
use ieee. std_logic_1164.all;
entity JK_FF is
PORT( J,K,CLK: in std_logic;
QOUT: out std_logic);
end JK_FF;
Architecture behavioral of JK_FF is
begin
Aditya Institute of Technology and Management, Tekkali
 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

PROCESS(CLK)
begin
if (Clk'event and Clk='1') then
QOUT <= J AND (NOT QIN) OR ((NOT K) AND QIN);
end if;
end process;
end behavioral;

--------T- Flip-flop ----

library ieee;
use ieee.std_logic_1164.all;
entity Tff is
port(Clk, T,QIN : in std_logic;
QOUT : out std_logic);
end Tff;
architecture behavioral of Tff is
begin
process (Clk)
begin
if (Clk'event and Clk='1') then
QOUT <= T XOR QIN;
end if;
end process;
end behavioral;

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Simulation Results:
S-R Flip flop

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

NETLIST:

set_property IOSTANDARD LVCMOS33 [get_ports Clk]

set_property IOSTANDARD LVCMOS33 [get_ports QIN]

set_property IOSTANDARD LVCMOS33 [get_ports QOUT]

set_property IOSTANDARD LVCMOS33 [get_ports R]

set_property IOSTANDARD LVCMOS33 [get_ports S]

set_property PACKAGE_PIN V10 [get_ports Clk]

set_property PACKAGE_PIN U11 [get_ports QIN]

set_property PACKAGE_PIN U12 [get_ports R]

set_property PACKAGE_PIN H6 [get_ports S]

set_property PACKAGE_PIN V11 [get_ports QOUT]

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

JK FF

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

NETLIST:

set_property IOSTANDARD LVCMOS33 [get_ports CLK]

set_property IOSTANDARD LVCMOS33 [get_ports J]

set_property IOSTANDARD LVCMOS33 [get_ports K]

set_property IOSTANDARD LVCMOS33 [get_ports Q]

set_property IOSTANDARD LVCMOS33 [get_ports QB]

set_property PACKAGE_PIN V10 [get_ports CLK]

set_property PACKAGE_PIN U11 [get_ports J]

set_property PACKAGE_PIN U12 [get_ports K]

set_property PACKAGE_PIN V11 [get_ports Q]

set_property PACKAGE_PIN V12 [get_ports QB]

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

T FF

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

NETLIST:

set_property IOSTANDARD LVCMOS33 [get_ports Clk]

set_property IOSTANDARD LVCMOS33 [get_ports QOUT]

set_property IOSTANDARD LVCMOS33 [get_ports QIN]

set_property IOSTANDARD LVCMOS33 [get_ports T]

set_property PACKAGE_PIN V10 [get_ports Clk]

set_property PACKAGE_PIN U11 [get_ports QIN]

set_property PACKAGE_PIN V11 [get_ports QOUT]

set_property PACKAGE_PIN U12 [get_ports T]

D FF

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

NETLIST:

set_property IOSTANDARD LVCMOS33 [get_ports Clk]

set_property IOSTANDARD LVCMOS33 [get_ports D]

set_property IOSTANDARD LVCMOS33 [get_ports QOUT]

set_property PACKAGE_PIN V10 [get_ports Clk]

set_property PACKAGE_PIN U11 [get_ports D]

set_property PACKAGE_PIN V11 [get_ports QOUT]

Result: The S-R, J-K, T & D flip-flops are designed by VHDL code and
verified their operation by using Xilinx Vivado software.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

5. Shift Register
Aim: To design Shift register using VHDL and verify its operation using Xilinx
Vivado software.

Software required: VIVADO 2018.1

Hardware required: NEXYS Artix-7.

Theory: This sequential device loads the data present on its inputs and then moves or
“shifts” it to its output once every clock cycle, hence the name Shift Register.
A shift register basically consists of several single bit “D-Type Data Latches”, one for
each data bit, either a logic “0” or a “1”, connected together in a serial type daisy-
chain arrangement so that the output from one data latch becomes the input of the next
latch and so on.
Data bits may be fed in or out of a shift register serially, that is one after the other
from either the left or the right direction, or all together at the same time in a parallel
configuration.
Shift Registers are used for data storage or for the movement of data and are therefore
commonly used inside calculators or computers to store data such as two binary
numbers before they are added together, or to convert the data from either a serial to
parallel or parallel to serial format. The individual data latches that make up a single
shift register are all driven by a common clock (Clk) signal making them synchronous
devices.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Procedure:

 Double click on VIVADO 2018.1 software

 Click on create project in Quick start menu and create new project
Quick start  Create projectnextRTL projectAdd sources(Create file select file
type as VHDL File name)ok and next Add constraints(create file select file type as
XDL File name)ok and next)  one window will be opened. select default parts and
click on next finish.
 Create inputs and outputs in define module according to the project.
 Then in Sources window source file (file name.vhd), click on that and add the logic in
.vhd file window.
 Project manager simulation (run behavioural simulation).
 In the objects window  give input valuesRight click on input force constant
force value.
 Click on run for ten microseconds or Shift+F2 and observe the output waveforms.
 RTL analysis open elaborated design click on ok
Then schematic output will be displayed
 Click on Run SYNTHESIS in Project Manager windowLaunch Run window 
Change No of jobs as “4” Click on OKIf NO ERRORS Synthesis Completed Window
will be opened
 Project ManagerRun IMPLEMENTATIONClick on OK then
IMPLEMENTATION Completed Window will be opened Click on Cancel
 Click on LAYOUT in File Menu then I/O PlanningAll ports window will be open in the
downside Select Scalar PortsAssign Outputs & Inputs as per kit port number.
 Connect the KIT and switch on the power supply Click on SAVE in File Menu  Save
constraints tab will be open then click on Ok.
 Project ManagerRun IMPLEMENTATIONClick on OKIMPLEMENTATION
Completed Window will be opened.
 Project ManagerClick on Generate Bit streamClick On OK Launch Runs tab will
be opened Click on OK Bit Stream generation completed tab will be opened Open

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

hardware Manger  Click on OKhardware Manger tab will open then click on Open
TargetAuto Connect Click on Program deviceProgram device will Opened  Click
On Program Program will be dumped into the KIT  Yellow LED will Glow.
 Verify the Program by using switches and led’s on the KIT

Code: (Shift register synthesis)

library ieee;

use ieee.std_logic_1164.all;

entity shift_register is

port(CLK : in std_logic;

s0 : out std_logic_vector(3 downto 0);

si,sel : in std_logic;

di : in std_logic_vector(3 downto 0));

end shift_register;

architecture behavioural of shift_register is

signal tmp: std_logic_vector(3 downto 0);

signal cnt_clk : integer;

signal clk_mhz : std_logic;

begin

process(clk_mhz,sel)

begin

if(clk_mhz'event and clk_mhz='1') then

case sel is

when '0'=>tmp <= si & tmp(3 downto 1);

when '1'=>tmp <= di;

when others =>

end case;

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

end if;

end process;

s0 <=tmp;

SEC1_DELAY : process(clk)

begin

if(rising_edge(clk)) then

if(cnt_clk<50000000) then

cnt_clk <= cnt_clk + 1;

else

cnt_clk <=0;

clk_mhz <=not clk_mhz;

end if;

end if;

end process SEC1_DELAY;

end behavioural;

Shift register (simulation)

library ieee;

use ieee.std_logic_1164.all;

entity shift_registers is

port(CLK : in std_logic;

s0 : out std_logic_vector(3 downto 0);

si,sel : in std_logic;

di : in std_logic_vector(3 downto 0));

end shift_registers;

architecture behavioural of shift_registers is

signal tmp: std_logic_vector(3 downto 0);

Aditya Institute of Technology and Management, Tekkali
 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

begin

process(CLK,sel)

begin

if(CLK'event and CLK='1') then

case sel is

when '0'=>tmp <= si & tmp(3 downto 1);

when '1'=>tmp <= di;

when others =>

end case;

end if;

end process;

s0 <=tmp;

end behavioural;

Simulation Results:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

NETLIST:

set_property PACKAGE_PIN J15 [get_ports {di[3]}]

set_property PACKAGE_PIN L16 [get_ports {di[2]}]

set_property PACKAGE_PIN M13 [get_ports {di[1]}]

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

set_property PACKAGE_PIN R15 [get_ports {di[0]}]

set_property PACKAGE_PIN E3 [get_ports CLK]

set_property PACKAGE_PIN U8 [get_ports sel]

set_property PACKAGE_PIN T8 [get_ports si]

set_property PACKAGE_PIN H17 [get_ports {s0[3]}]

set_property PACKAGE_PIN K15 [get_ports {s0[2]}]

set_property PACKAGE_PIN J13 [get_ports {s0[1]}]

set_property PACKAGE_PIN N14 [get_ports {s0[0]}]

Result: Shift register is designed by VHDL code and verified its operation by using
Xilinx Vivado software.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

6. 4-Bit Counter
Aim: To design a 4-bit counter using VHDL and verify its operation using
Xilinx Vivado software.

Software required: VIVADO 2018.1

Hardware required: NEXYS Artix-7.

Theory: In the asynchronous 4- bit up counter, the flip flops are connected in
toggle mode, so when the clock input is connected to the first flip flop FF0, then
its output after one clock pulse will become 20. The rising edge of the Q output
of each flip flop triggers the clock input of its next flip flop.

Let us assume that the 4 Q outputs of the flip flops are initially 0000. When the
rising edge of the clock pulse is applied to the FF0, then the output Q0 will
change to logic 1 and the next clock pulse will change the Q0 output to logic 0.
This means the output state of the clock pulse toggles (changes from 0 to1) for
one cycle.

As the Q’ of FF0 is connected to the clock input of FF1, then the clock input of
second flip flop will become 1. This makes the output of FF1 to be high

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Truth Table:

Procedure:

 Double click on VIVADO 2018.1 software

 Click on create project in Quick start menu and create new project
Quick start  Create projectnextRTL projectAdd sources(Create file select file
type as VHDL File name)ok and next Add constraints(create file select file type as
XDL File name)ok and next)  one window will be opened. select default parts and
click on next finish.
 Create inputs and outputs in define module according to the project.
 Then in Sources window source file (file name.vhd), click on that and add the logic in
.vhd file window.
 Project manager simulation (run behavioural simulation).
 In the objects window  give input valuesRight click on input force constant
force value.
 Click on run for ten microseconds or Shift+F2 and observe the output waveforms.
 RTL analysis open elaborated design click on ok

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Then schematic output will be displayed

 Click on Run SYNTHESIS in Project Manager windowLaunch Run window 
Change No of jobs as “4” Click on OKIf NO ERRORS Synthesis Completed Window
will be opened
 Project ManagerRun IMPLEMENTATIONClick on OK then
IMPLEMENTATION Completed Window will be opened Click on Cancel
 Click on LAYOUT in File Menu then I/O PlanningAll ports window will be open in the
downside Select Scalar PortsAssign Outputs & Inputs as per kit port number.
 Connect the KIT and switch on the power supply Click on SAVE in File Menu  Save
constraints tab will be open then click on Ok.
 Project ManagerRun IMPLEMENTATIONClick on OKIMPLEMENTATION
Completed Window will be opened.
 Project ManagerClick on Generate Bit streamClick On OK Launch Runs tab will
be opened Click on OK Bit Stream generation completed tab will be opened Open
hardware Manger  Click on OKhardware Manger tab will open then click on Open
TargetAuto Connect Click on Program deviceProgram device will Opened  Click
On Program Program will be dumped into the KIT  Yellow LED will Glow.
 Verify the Program by using switches and led’s on the KIT

Code: (Synthesis)
library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity counter4 is

port(CLK, CLR : in std_logic;

Q : out unsigned(3 downto 0));

end counter4;

architecture behavioural of counter4 is

signal tmp: unsigned(3 downto 0);

signal cnt_clk : integer :=0;

signal clk_mhz : std_logic:='0';

begin

process (clk_mhz)
Aditya Institute of Technology and Management, Tekkali
 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

begin

if (clk_mhz'event and clk_mhz='1') then

if (CLR='1') then

tmp <= "0000";

else

tmp <= tmp + 1;

end if;

end if;

end process;

clk_1sec:process(CLK)

begin

if(rising_edge(CLK)) then

if(cnt_clk<50000000) then

cnt_clk <= cnt_clk + 1;

else

cnt_clk <=0;

clk_mhz <=not clk_mhz;

end if;

end if;

end process clk_1sec;

Q <= tmp;

end behavioural;

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

code (Simulation)
library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity counter4 is

port(CLK, CLR : in std_logic;

Q : out unsigned(3 downto 0));

end counter4;

architecture behavioural of counter4 is

signal tmp: unsigned(3 downto 0);

begin

process (CLK)

begin

if (CLK'event and CLK='1') then

if (CLR='1') then

tmp <= "0000";

else

tmp <= tmp + 1;

end if;

end if;

end process;

Q <= tmp;

End behavioural;

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Simulation Results:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

NETLIST:

set_property PACKAGE_PIN E3 [get_ports CLK]

set_property PACKAGE_PIN J15 [get_ports CLR]

set_property PACKAGE_PIN H17 [get_ports {Q[3]}]

set_property PACKAGE_PIN K15 [get_ports {Q[2]}]

set_property PACKAGE_PIN J13 [get_ports {Q[1]}]

set_property PACKAGE_PIN N14 [get_ports {Q[0]}]

Result:4 bit counter is designed by VHDL code and verified its operation by using
Xilinx Vivado software.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

7. Universal Shift Register

Aim: To design a Universal Shift register using VHDL and verify its operation using Xilinx
Vivado software.

Software required: VIVADO 2018.1.

Hardware required: NEXYS Artix-7. .

Theory: A register that can store the data and /shifts the data towards the right and
left along with the parallel load capability is known as a universal shift register. It can
be used to perform input/output operations in both serial and parallel modes.
Unidirectional shift registers and bidirectional shift registers are combined together to
get the design of the universal shift register. It is also known as a parallel-in-parallel-
out shift register or shift register with the parallel load.
Universal shift registers are capable of performing 3 operations as listed below.

 Parallel load operation – stores the data in parallel as well as the data in parallel
 Shift left operation – stores the data and transfers the data shifting towards left in
the serial path
 Shift right operation – stores the data and transfers the data by shifting towards
right in the serial path.
Hence, Universal shift registers can perform input/output operations with both serial
and parallel loads.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Procedure:

 Double click on VIVADO 2018.1 software

 Click on create project in Quick start menu and create new project
Quick start  Create projectnextRTL projectAdd sources(Create file select file
type as VHDL File name)ok and next Add constraints(create file select file type as
XDL File name)ok and next)  one window will be opened. select default parts and
click on next finish.
 Create inputs and outputs in define module according to the project.
 Then in Sources window source file (file name.vhd), click on that and add the logic in
.vhd file window.
 Project manager simulation (run behavioural simulation).
 In the objects window  give input valuesRight click on input force constant
force value.
 Click on run for ten microseconds or Shift+F2 and observe the output waveforms.
 RTL analysis open elaborated design click on ok
Then schematic output will be displayed
 Click on Run SYNTHESIS in Project Manager windowLaunch Run window 
Change No of jobs as “4” Click on OKIf NO ERRORS Synthesis Completed Window
will be opened
 Project ManagerRun IMPLEMENTATIONClick on OK then
IMPLEMENTATION Completed Window will be opened Click on Cancel
 Click on LAYOUT in File Menu then I/O PlanningAll ports window will be open in the
downside Select Scalar PortsAssign Outputs & Inputs as per kit port number.
 Connect the KIT and switch on the power supply Click on SAVE in File Menu  Save
constraints tab will be open then click on Ok.
 Project ManagerRun IMPLEMENTATIONClick on OKIMPLEMENTATION
Completed Window will be opened.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

 Project ManagerClick on Generate Bit streamClick On OK Launch Runs tab will
be opened Click on OK Bit Stream generation completed tab will be opened Open
hardware Manger  Click on OKhardware Manger tab will open then click on Open
TargetAuto Connect Click on Program deviceProgram device will Opened  Click
On Program Program will be dumped into the KIT  Yellow LED will Glow.
 Verify the Program by using switches and led’s on the KIT

Code: (Universal Shift register simulation)

library ieee;

use ieee.std_logic_1164.all;

entity USR is

port(CLK : in std_logic;

s0 : out std_logic_vector(3 downto 0);

si : in std_logic;

sel:instd_logic_vector(1 downto 0);

di : in std_logic_vector(3 downto 0));

end USR;

architecture behavioural of USR is

signal tmp: std_logic_vector(3 downto 0);

begin

process(CLK,sel)

begin

if(CLK'event and CLK='1') then

case sel is

when "00"=>tmp<= di;

when "01"=>tmp<= si&tmp(3 downto 1);

when "10"=>tmp<= tmp(2 downto 0)&si ;

when "11"=>tmp<= tmp(3 downto 0);

when others =>

end case;
Aditya Institute of Technology and Management, Tekkali
 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

end if;

end process;

s0 <=tmp;

end behavioural;

(Universal shift register synthesis)

library ieee;

use ieee.std_logic_1164.all;

entity USR is

port(CLK : in std_logic;

s0 : out std_logic_vector(3 downto 0);

si : in std_logic;

sel:instd_logic_vector(1 downto 0);

di : in std_logic_vector(3 downto 0));

end USR;

architecture behavioural of USR is

signal tmp: std_logic_vector(3 downto 0);

signal cnt_clk : integer;

signal clk_mhz :std_logic;

begin

process(clk_mhz,sel)

begin

if(clk_mhz'event and clk_mhz='1') then

case sel is

when "00"=>tmp<= di;

when "01"=>tmp<= si&tmp(3 downto 1);

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

when "10"=>tmp<= tmp(2 downto 0)&si ;

when "11"=>tmp<= tmp;

when others =>

end case;

end if;

end process;

s0 <=tmp;

SEC1_DELAY : process(clk)

begin

if(rising_edge(clk)) then

if(cnt_clk<50000000) then

cnt_clk<= cnt_clk + 1;

else

cnt_clk<=0;

clk_mhz<=not clk_mhz;

end if;

end if;

end process SEC1_DELAY;

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Simulation Results:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

NETLIST:

set_property PACKAGE_PIN E3 [get_ports CLK]

set_property PACKAGE_PIN J5 [get_ports reset]

set_property PACKAGE_PIN L16 [get_ports sel]

set_property PACKAGE_PIN U8 [get_ports {di[3]}]

set_property PACKAGE_PIN T8 [get_ports {di[2]}]

set_property PACKAGE_PIN R13 [get_ports {di[1]}]

set_property PACKAGE_PIN U18 [get_ports {di[0]}]

set_property PACKAGE_PIN T16 [get_ports {s0[3]}]

set_property PACKAGE_PIN U14 [get_ports {s0[2]}]

set_property PACKAGE_PIN T15 [get_ports {s0[1]}]

set_property PACKAGE_PIN U16 [get_ports {s0[0]}]

Result: Universal Shift register is designed by VHDL code and verified its operation by
using Xilinx Vivado software.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Introduction to Microwind

In this lab an important VLSI tool Microwind is studied. The main objective of this
lab is to understand the features of this software and practice layout and simulation of simple
devices like MOSFETS and inverter.

Microwind is a windows based VLSI tool designed specially for designing and simulating
microelectronic circuits at layout level. The tool features full editing facilities, e.g. copy, cut,
paste, duplicate, and move operations. This software also provides various views of the
layout such as 2D cross section, 3D process viewer, etc. The software is capable of providing
limited simulation facilities as well as by building layouts of some basic devices.

In the next section we will discover the important features of software in detail.

2. Microwind Editor

This is the main window of the Microwind. You may cut, past, duplicate, generate matrix of
layout, use the layout editor to insert contacts, MOS devices, pads, complex contacts and path
in one single click.

Figure 1: Microwind Editor window

Palette Menu

The palette is located on the right side of the screen. A little tick indicates the current layer.
The selected layer by default is a polysilicon (PO). The list of layers is given in figure 2.

 If you remove the tick on the right side of the layer, the layer is switched to protected
mode. The Cut, Stretch and Copy commands no longer affect that layer.
 Use "View->Protect all" to protect all layers. The ticks are erased.
Aditya Institute of Technology and Management, Tekkali
 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

 Use "View->Unprotect all" to remove the protection. All layers can be edited.

Figure 2: Palette Menu Window

Navigator Menu

Select view->Navigator window

This menu gives the information about capacitance, resistance, inductance, node name,
device properties and detailed electrical properties. Navigator window is shown in fig: 3

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Figure 3: Navigator Window

Design Rule Checker

The design rule checker (DRC) scans all the design and verifies that all the minimum design
rules are respected. Click on the icon above or on Analysis ->Design Rule Checker to run
the DRC. The errors are highlighted in the display window, with an appropriate message
giving the nature of the error. Details about the position and type of the errors appear on the
screen.

Simulation Results

The "Run Simulation" icon or the command Simulate -> Start Simulation both gives access
to the automatic extraction and analog simulation of the layout.

 Click on Voltage vs Time to obtain the transient analysis of all visible signals. The
delay between the selected start node and selected stop node is computed at VDD/2.
You can change the selected start node in the node list, in the right upper menu of the
window. You can do the same for the selected stop node.
 Click on Voltage and Currents so as to make all voltage curves appear in the lower
window, and the VDD, the VSS and the desired MOS currents appear in the upper
window. In that mode, the dissipated power within the simulation is also displayed.
 Click on Voltage vs. Voltage to obtain transfer characteristics between the X-axis
selected node and the Y-axis selected node. Initially the start node is the first clock or

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

pulse of the node list, and the stop node is the first varying node. This mode is useful
for the computing of the Inverter characteristics (commutation point), the DC
response of the operational amplifier, or for the Schmitt trigger to see the hysteresis
phenomenon. The first simulation computes the value of the stop node for start node
varying from 0 to VDD. The second click on “Simulate” computes the same for start
node varying from VDD to 0.
 Click on Frequency & Voltages so as to make all voltage curves appear in the lower
window, and to plot the variation of the switching frequency of one selected signal.
This mode is very useful for monitoring the output signal of oscillators.

Etching Process Problem

Design Rules
Minimum width of PolySi and diffusion line 2
Minimum width of Metal line 3 as metal lines run over a more uneven surface than other
conducting layers to ensure their continuity

Design Rules:

PolySi – PolySi space 2

Metal - Metal space 2
Diffusion – Diffusion 3 To avoid the possibility of their associated regions overlapping and
conducting current

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Diffusion – PolySi  To prevent the lines overlapping to form unwanted capacitor

Metal lines can pass over both diffusion and polySi without electrical effect. Where no
separation is specified, metal lines can overlap or cross

Metal Vs PolySi/Diffusion
 Metal lines can pass over both diffusion and polySi without electrical effect
 It is recommended practice to leave  between a metal edge and a polySi or diffusion
line to which it is not electrically connected

 poly-poly spacing 2
 diff-diff spacing 3
 (depletion regions tend to spread outward)
 metal-metal spacing 2
 diff-poly spacing 

PolySi extends in the gate region…

The polySi of the gate extends 2 beyond the gate area on to the field oxide to prevent the
drain and source from shorting.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Depletion Transistor

We need depletion implant

An implant surrounding the Transistor by 2
Ensures that no part of the transistor
remains in the enhancement mode

A separation of 2 from the

gate of an enhancement transistor
avoids affecting the device.

Implants are separated by

2 to prevent them from merging

Butting Contact
The gate and source of a depletion device can be connected by a method known as butting
contact. Here metal makes contact to both the diffusion forming the source of the depletion
transistor and to the polySi forming this device’s gate.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Advantage:

No buried contact mask required and avoids associated processing.

Buried Contact
It is a preferred method. The buried contact window defines the area where oxide is to be
removed so that polySi connects directly to diffusion.
Contact Area must be a min. of 2*2 to ensure adequate contact area.

The buried contact window surrounds this contact by  in all directions to avoid any part of
this area forming a transistor.
Separated from its related transistor gate by  to prevent gate area from being reduced.

Here gate length is depend upon the alignment of the buried contact mask relative to the
polySi and therefore vary by .

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Contact Cut
Metal connects to polySi/diffusion by contact cut.
Contact area: 2l*2l
Metal and polySi or diffusion must overlap this contact area by l so that the two desired
conductors encompass the contact area despite any mis-alignment between conducting layers
and the contact hole

Contact cut – any gate: 2l apart

Why? No contact to any part of the gate.

Contact cut – contact cut: 2l apart

Why? To prevent holes from merging.

Rules for CMOS layout

Similar to those for NMOS except No
1. Depletion implant
2. Buried contact

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

Additional rules
1. Definition of n-well area
2. Threshold implant of two types of transistor
3. Definition of source and drains regions for t NMOS and PMOS.
To ensure the separation of the PMOS and NMOS devices,
n-well supporting PMOS is 6l away from the active area of NMOS transistor.

Why?
Avoids overlap of
the associated regions

N-well must completely

surround the PMOS
device’s active area by 2l

The threshold implant

mask covers all n-well
and surrounds the n-well by l

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

The p+ diffusion mask

defines the areas to
receive a p+ diffusion.

It is coincident with the

threshold mask s
urrounding the PMOS
transistor but excludes t
he n-well region to be
connected to the supply.

A p+ diffusion is required to effect the ground

connection to the substrate. Thus mask also
defines this substrate region. It surrounds the
conducting material of this contact by l.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

EXP – 08 BASIC LOGIC GATES

AIM: Design the two-input CMOS INVERTER layout by using the micro wind V2.6
software and check that whether the design satisfies the CMOS design rules (or) not,
draw the output characteristics, finding the relations between parameters and list out
the layers which are used in that particular design.

LAYOUT DESIGNING:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

VOLTAGE VS TIME CHARACTERISTICS:

VOLTAGE VS VOLTAGE CHARACTERISTICS:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

VOLTAGE VS CURRENT CHARACTERISTICS:

CHARACTERISTICS OF LEVEL-3: ID Vs VD (NMOS)

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

CHARACTERISTICS OF LEVEL-3: ID Vs VD (PMOS)

CHARACTERISTICS OF LEVEL-3 ID Vs VG (NMOS):

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

CHARACTERISTICS OF LEVEL-3: ID Vs VG (PMOS):

PROPERTIES OF VDD:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

PROPERTIES OF VSS:

PROPERTIES OF INPUT(A):

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

PROPERTIES OF OUTPUT(S1):

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

SIMULATION PARAMETERS:

CIRCUIT CMOS Inverter.MSK

* IC Technology: CMOS 0.12µm - 6 Metal
VDD 1 0 DC 1.20
VA 6 0 PULSE(0.00 1.20 0.23N 0.03N 0.03N 0.23N 0.50N)
* List of nodes
* "N2" corresponds to n°2
* "s1" corresponds to n°3
* "A" corresponds to n°6
* MOS devices
MN1 0 6 3 0 N1 W= 0.60U L= 0.12U
MP1 1 6 3 2 P1 W= 0.60U L= 0.12U
C2 2 0 0.475fF
C3 3 0 0.435fF
C4 1 0 0.190fF
C6 6 0 0.181fF
* n-MOS Model 3 :
* low leakage
.MODEL N1 NMOS LEVEL=3 VTO=0.40 U0=0.060 TOX= 3.5E-9
+LD =0.000U THETA=0.500 GAMMA=0.400
+PHI=0.200 KAPPA=0.060 VMAX=120.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
* p-MOS Model 3:
* low leakage
.MODEL P1 PMOS LEVEL=3 VTO=-0.45 U0=0.020 TOX= 3.5E-9
+LD =0.000U THETA=0.300 GAMMA=0.400
+PHI=0.200 KAPPA=0.060 VMAX=110.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
* Transient analysis
.TEMP 27.0
.TRAN 0.50PS 5.00N
.PROBE
.END

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

LAYER LIST OF CMOS INVERTER GATE LAYOUT:

LAYER THICK (m) HIGHT (m)

METAL-6 0.70 6.60
VIA-5 0.50 6.10
METAL-5 0.70 5.40
VIA-4 0.50 4.70
METAL-4 0.50 4.20
VIA-3 0.50 3.70
METAL-3 0.50 3.20
VIA-2 0.50 2.70
METAL-2 0.50 2.20
VIA-1 0.50 1.70
METAL-1 0.50 1.20
POLYSILICON 0.20 0.01
POLY-2 0.20 0.22
CONTACT 1.20 0.00
N-DIFFUSION 0.40 0.00
P-DIFFUSION 0.40 0.00
N-WELL 1.00 0.00

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

CMOS INVERTER NAVIGATOR:

W L
DEVICES W (m) L (m) TYPE
(Lambda) (Lambda)
N-1 1.60 0.120 10 02 Low leakage
N-2 1.60 0.120 10 02 Low leakage
P-1 1.60 0.120 10 02 Low leakage
P-2 1.60 0.120 10 02 Low leakage

PRECAUTIONS:

01. Leakage current must always low.

02. Layout must satisfy all the CMOS design rules.
03. Output value must be taken without a parallax error.

RESULT:

Design of the layout completed based on the CMOS design rules and lambda based
design rules. The characteristics of the CMOS INVERTER are taken and the relations
between the internal parameters are also drawn above.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

EXP – 09 UNIVERSAL GATES

AIM:
Design the two-input CMOS NAND gate layout by using the micro wind V2.6
software and check that whether the design satisfies the CMOS design rules (or) not, draw the
output characteristics, finding the relations between parameters and list out the layers which
are used in that particular design.

LAYOUT DESIGNING:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

VOLTAGE VS TIME RELATIONSHIP:

VOLTAGE VS CURRENT RELATIONSHIP:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

CHARACTERISTICS OF LEVEL-3 ID Vs VD (NMOS):

CHARACTERISTICS OF LEVEL-3 ID Vs VD (PMOS):

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

CHARACTERISTICS OF LEVEL-3 ID Vs VG (NMOS):

CHARACTERISTICS OF LEVEL-3 ID Vs VG (PMOS):

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

PROPERTIES OF VDD:

PROPERTIES OF VSS :

PROPERTIES OF INPUT (A)

Aditya Institute of Technology and Management, Tekkali
 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

PROPERTIES OF INPUT (B):

PROPERTIES OF OUTPUT :
Aditya Institute of Technology and Management, Tekkali
 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

SIMULATION PARAMETERS:
Aditya Institute of Technology and Management, Tekkali
 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

CIRCUIT NAND.MSK
* IC Technology: CMOS 0.12µm - 6 Metal
VDD 1 0 DC 1.20
VB 7 0 PULSE(0.00 1.20 0.48N 0.03N 0.03N 0.48N 1.00N)
VA 8 0 PULSE(0.00 1.20 0.23N 0.03N 0.03N 0.23N 0.50N)
* List of nodes
* "N2" corresponds to n°2
* "O/P" corresponds to n°4
* "N5" corresponds to n°5
* "B" corresponds to n°7
* "A" corresponds to n°8
* MOS devices
MN1 5 7 4 0 N1 W= 0.60U L= 0.12U
MN2 0 8 5 0 N1 W= 0.60U L= 0.12U
MP1 4 7 1 2 P1 W= 0.60U L= 0.12U
MP2 1 8 4 2 P1 W= 0.60U L= 0.12U
C2 2 0 1.242fF
C3 1 0 0.464fF
C4 4 0 0.516fF
C5 5 0 0.206fF
C7 7 0 0.147fF
C8 8 0 0.228fF
* n-MOS Model 3 :
* low leakage
.MODEL N1 NMOS LEVEL=3 VTO=0.40 U0=0.060 TOX= 3.5E-9
+LD =0.000U THETA=0.500 GAMMA=0.400
+PHI=0.200 KAPPA=0.060 VMAX=120.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
* p-MOS Model 3:
* low leakage
.MODEL P1 PMOS LEVEL=3 VTO=-0.45 U0=0.020 TOX= 3.5E-9
+LD =0.000U THETA=0.300 GAMMA=0.400
+PHI=0.200 KAPPA=0.060 VMAX=110.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
* Transient analysis
.TEMP 27.0
.TRAN 0.30PS 5.00N
.PROBE
.END

LAYER LIST OF CMOS NAND GATE LAYOUT:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

LAYER THICK (m) HIGHT (m)

METAL-6 0.70 6.60
VIA-5 0.50 6.10
METAL-5 0.70 5.40
VIA-4 0.50 4.70
METAL-4 0.50 4.20
VIA-3 0.50 3.70
METAL-3 0.50 3.20
VIA-2 0.50 2.70
METAL-2 0.50 2.20
VIA-1 0.50 1.70
METAL-1 0.50 1.20
POLYSILICON 0.20 0.01
POLY-2 0.20 0.22
CONTACT 1.20 0.00
N-DIFFUSION 0.40 0.00
P-DIFFUSION 0.40 0.00
N-WELL 1.00 0.00

TWO INPUT NAND GATE NAVIGATOR:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

W L
DEVICES W (m) L (m) TYPE
(Lambda) (Lambda)
N-1 1.60 0.120 10 02 Low leakage
N-2 1.60 0.120 10 02 Low leakage
P-1 1.60 0.120 10 02 Low leakage
P-2 1.60 0.120 10 02 Low leakage

PRECAUTIONS:

01. Leakage current must always low.

02. Layout must satisfy all the CMOS design rules.
03. Output value must be taken without a parallax error.

RESULT:

Design of the layout completed based on the CMOS design rules and lambda based
design rules. The characteristics of the two input NAND GATE are taken and the relations
between the internal parameters are also drawn above.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

EXP – 9B TWO INPUT CMOS NOR GATE

AIM: Design the two-input CMOS NOR gate layout by using the micro wind V2.6
software and check that whether the design satisfies the CMOS design rules (or) not,
draw the output characteristics, finding the relations between parameters and list out
the layers which are used in that particular design.

LAYOUT DESIGN:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

VOLTAGE VS TIME RELATIONSHIP

VOLTAGE VS VOLTAGE RELATIONSHIP:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

VOLTAGE VS CURRENT RELATIONSHIP:

CHARACTERISTICS OF LEVEL-3 ID VS VD (NMOS):

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

CHARACTERISTICS OF LEVEL-3 ID VS VD (PMOS):

CHARACTERISTICS OF LEVEL-3 ID VS VG (NMOS):

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

CHARACTERISTICS OF LEVEL-3 ID VS VG (PMOS):

PROPERTIES OF VDD :

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

PROPERTIES OF VSS :

PROPERTIES OF INPUT (A) :

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

PROPERTIES OF INPUT (B) :

PROPERTIES OF OUTPUT :

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

SIMULATION PARAMETERS:

CIRCUIT NOR.MSK
* IC Technology: CMOS 0.12µm - 6 Metal
VDD 1 0 DC 1.20
VA 7 0 PULSE(0.00 1.20 0.98N 0.03N 0.02N 0.97N 2.00N)
VB 8 0 PULSE(0.00 1.20 1.97N 0.02N 0.03N 1.98N 4.00N)
* List of nodes
* "N2" corresponds to n°2
* "o/p" corresponds to n°3
* "N4" corresponds to n°4
* "A" corresponds to n°7
* "B" corresponds to n°8
* MOS devices
MN1 3 8 0 0 N1 W= 0.60U L= 0.12U
MN2 0 7 3 0 N1 W= 0.60U L= 0.12U
MP1 4 8 3 2 P1 W= 0.60U L= 0.12U
MP2 1 7 4 2 P1 W= 0.60U L= 0.12U
C2 2 0 0.634fF
C3 3 0 0.491fF
C4 4 0 0.195fF
C5 1 0 0.187fF
C7 7 0 0.233fF
C8 8 0 0.207fF
* n-MOS Model 3 :
* low leakage
.MODEL N1 NMOS LEVEL=3 VTO=0.40 U0=0.060 TOX= 3.5E-9
+LD =0.000U THETA=0.500 GAMMA=0.400
+PHI=0.200 KAPPA=0.060 VMAX=120.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
* p-MOS Model 3:
* low leakage
.MODEL P1 PMOS LEVEL=3 VTO=-0.45 U0=0.020 TOX= 3.5E-9
+LD =0.000U THETA=0.300 GAMMA=0.400
+PHI=0.200 KAPPA=0.060 VMAX=110.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
* Transient analysis
.TEMP 27.0
.TRAN 0.30PS 10.00N
.PROBE
.END

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

LAYER LIST OF TWO INPUT NOR GATE LAYOUT:

LAYER THICK (m) HIGHT (m)

METAL-6 0.70 6.60
VIA-5 0.50 6.10
METAL-5 0.70 5.40
VIA-4 0.50 4.70
METAL-4 0.50 4.20
VIA-3 0.50 3.70
METAL-3 0.50 3.20
VIA-2 0.50 2.70
METAL-2 0.50 2.20
VIA-1 0.50 1.70
METAL-1 0.50 1.20
POLYSILICON 0.20 0.01
POLY-2 0.20 0.22
CONTACT 1.20 0.00
N-DIFFUSION 0.40 0.00
P-DIFFUSION 0.40 0.00
N-WELL 1.00 0.00

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

TWO INPUT NAND GATE NAVIGATOR:

W L
DEVICES W (m) L (m) TYPE
(Lambda) (Lambda)
N-1 1.60 0.120 10 02 Low leakage
N-2 1.60 0.120 10 02 Low leakage
P-1 1.60 0.120 10 02 Low leakage
P-2 1.60 0.120 10 02 Low leakage

PRECAUTIONS:

01. Leakage current must always low.

02. Layout must satisfy all the CMOS design rules.
03. Output value taken without a parallax error.

RESULT:

Design of the layout completed based on the CMOS design rules and lambda based
design rules. The characteristics of the two input CMOS NOR GATE are taken and the
relations between the internal parameters are also drawn above.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

EXP – 10 AND-OR INVERTER CIRCUIT

AIM: Design the two-input AND-OR Inverter circuit layout by using the micro wind
V2.6 software and check that whether the design satisfies the CMOS design rules
(or) not, draw the output characteristics, finding the relations between parameters
and list out the layers which are used in that particular design.

LAYOUT DESIGN:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

VOLTAGE VS TIME RELATIONSHIP:

VOLTAGE VS CURRENT RELATIONSHIP:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

VOLTAGE VS VOLTAGE RELATIONSHIP:

CHARACTERISTICS OF LEVEL-3 ID VS VD (NMOS):

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

CHARACTERISTICS OF LEVEL-3 ID VS VD (PMOS):

CHARACTERISTICS OF LEVEL-3 ID VS VG (NMOS):

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

CHARACTERISTICS OF LEVEL-3 ID VS VG (PMOS):

PROPERTIES OF VDD :

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

PROPERTIES OF VSS :

PROPERTIES OF INPUT (A) :

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

PROPERTIES OF INPUT (B) :

PROPERTIES OF INPUT (C) :

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

PROPERTIES OF INPUT (D) :

PROPERTIES OF OUTPUT :

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

SIMULATION PARAMETER:

CIRCUIT AND-OR.MSK
* IC Technology: CMOS 0.12µm - 6 Metal
VDD 1 0 DC 1.20
VD 8 0 PULSE(0.00 1.20 1.97N 0.02N 0.03N 1.98N 4.00N)
VA 9 0 PULSE(0.00 1.20 0.23N 0.03N 0.03N 0.23N 0.50N)
VB 10 0 PULSE(0.00 1.20 0.48N 0.03N 0.03N 0.48N 1.00N)
VC 11 0 PULSE(0.00 1.20 0.98N 0.03N 0.02N 0.97N 2.00N)
* List of nodes
* "N2" corresponds to n°2
* "O/P" corresponds to n°3
* "N6" corresponds to n°6
* "N7" corresponds to n°7
* "D" corresponds to n°8
* "A" corresponds to n°9
* "B" corresponds to n°10
* "C" corresponds to n°11
* MOS devices
MN1 6 8 0 0 N1 W= 0.60U L= 0.12U
MN2 3 11 6 0 N1 W= 0.60U L= 0.12U
MN3 7 10 3 0 N1 W= 0.60U L= 0.12U
MN4 0 9 7 0 N1 W= 0.60U L= 0.12U
MP1 1 10 3 2 P1 W= 0.60U L= 0.12U
MP2 3 9 1 2 P1 W= 0.60U L= 0.12U
C2 2 0 1.361fF
C3 3 0 1.205fF
C4 1 0 0.207fF
C6 6 0 0.206fF
C7 7 0 0.206fF
C8 8 0 0.181fF
C9 9 0 0.184fF
C10 10 0 0.153fF
C11 11 0 0.144fF
* n-MOS Model 3 :
* low leakage
.MODEL N1 NMOS LEVEL=3 VTO=0.40 U0=0.060 TOX= 3.5E-9
+LD =0.000U THETA=0.500 GAMMA=0.400
+PHI=0.200 KAPPA=0.060 VMAX=120.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
* p-MOS Model 3:
* low leakage
.MODEL P1 PMOS LEVEL=3 VTO=-0.45 U0=0.020 TOX= 3.5E-9
+LD =0.000U THETA=0.300 GAMMA=0.400
+PHI=0.200 KAPPA=0.060 VMAX=110.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
* Transient analysis
.TEMP 27.0
.TRAN 0.30PS 2.00N
.PROBE
.END

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

LAYER LIST OF AND-OR-INVERTER GATE LAYOUT:

LAYER THICK (m) HIGHT (m)

METAL-6 0.70 6.60
VIA-5 0.50 6.10
METAL-5 0.70 5.40
VIA-4 0.50 4.70
METAL-4 0.50 4.20
VIA-3 0.50 3.70
METAL-3 0.50 3.20
VIA-2 0.50 2.70
METAL-2 0.50 2.20
VIA-1 0.50 1.70
METAL-1 0.50 1.20
POLYSILICON 0.20 0.01
POLY-2 0.20 0.22
CONTACT 1.20 0.00
N-DIFFUSION 0.40 0.00
P-DIFFUSION 0.40 0.00
N-WELL 1.00 0.00

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

TWO INPUT NAND GATE NAVIGATOR:

W L
DEVICES W (m) L (m) TYPE
(Lambda) (Lambda)
N-1 1.60 0.120 10 02 Low leakage
N-2 1.60 0.120 10 02 Low leakage
P-1 1.60 0.120 10 02 Low leakage
P-2 1.60 0.120 10 02 Low leakage

PRECAUTIONS:

01. Leakage current must always low.

02. Layout must satisfy all the CMOS design rules.
03. Output value must be taken without a parallax error.

RESULT:

Design of the layout completed based on the CMOS design rules and lambda based
design rules. The characteristics of the AND-OR-INVERTER CIRCUIT are taken and the
relations between the internal parameters are also drawn above.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

EXP – 11 OR-AND-INVERTER CIRCUIT

AIM: Design the two-input OR-AND- INVERTER circuit layout by using the micro wind
V2.6 software and check that whether the design satisfies the CMOS design rules (or) not,
draw the output characteristics, finding the relations between parameters and list out the
layers which are used in that particular design.

LAYOUT DESIGN:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

VOLTAGE VS TIME RELATIONSHIP:

VOLTAGE VS CURRENT RELATIONSHIP:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

VOLTAGE VS VOLTAGE RELATIONSHIP:

CHRACTERISTICS OF LEVEL-3 ID VS VD (NMOS):

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

CHRACTERISTICS OF LEVEL-3 ID VS VD (PMOS):

CHRACTERISTICS OF LEVEL-3 ID VS VG (NMOS):

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

CHRACTERISTICS OF LEVEL-3 ID VS VG (PMOS):

PROPERTIES OF VDD:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

PROPERTIES OF VSS:

PROPERTIES INPUT (A):

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

PROPERTIES INPUT (B):

PROPERTIES INPUT (C):

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

PROPERTIES INPUT (D):

PROPERTIES OUTPUT :

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

SIMULATION PARAMETERS:

CIRCUIT AND-OR.MSK
* IC Technology: CMOS 0.12µm - 6 Metal
VDD 1 0 DC 1.20
VD 8 0 PULSE(0.00 1.20 1.97N 0.02N 0.03N 1.98N 4.00N)
VB 9 0 PULSE(0.00 1.20 0.48N 0.03N 0.03N 0.48N 1.00N)
VA 10 0 PULSE(0.00 1.20 0.23N 0.03N 0.03N 0.23N 0.50N)
VC 11 0 PULSE(0.00 1.20 0.98N 0.03N 0.02N 0.97N 2.00N)
* List of nodes
* "N2" corresponds to n°2
* "N4" corresponds to n°4
* "O/P" corresponds to n°5
* "N6" corresponds to n°6
* "D" corresponds to n°8
* "B" corresponds to n°9
* "A" corresponds to n°10
* "C" corresponds to n°11
* MOS devices
MN1 0 9 5 0 N1 W= 0.60U L= 0.12U
MN2 5 10 0 0 N1 W= 0.60U L= 0.12U
MP1 4 8 1 2 P1 W= 0.60U L= 0.12U
MP2 5 11 4 2 P1 W= 0.60U L= 0.12U
MP3 6 9 5 2 P1 W= 0.60U L= 0.12U
MP4 1 10 6 2 P1 W= 0.60U L= 0.12U
C2 2 0 1.191fF
C3 1 0 0.501fF
C4 4 0 0.195fF
C5 5 0 1.204fF
C6 6 0 0.195fF
C8 8 0 0.161fF
C9 9 0 0.153fF
C10 10 0 0.184fF
C11 11 0 0.141fF
* n-MOS Model 3 :
* low leakage
.MODEL N1 NMOS LEVEL=3 VTO=0.40 U0=0.060 TOX= 3.5E-9
+LD =0.000U THETA=0.500 GAMMA=0.400
+PHI=0.200 KAPPA=0.060 VMAX=120.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
* p-MOS Model 3:
* low leakage
.MODEL P1 PMOS LEVEL=3 VTO=-0.45 U0=0.020 TOX= 3.5E-9
+LD =0.000U THETA=0.300 GAMMA=0.400
+PHI=0.200 KAPPA=0.060 VMAX=110.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
* Transient analysis
.TEMP 27.0
.TRAN 0.30PS 5.00N
.PROBE
.END

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

LAYER LIST OF OR-AND-INVERTER GATE LAYOUT:

LAYER THICK (m) HIGHT (m)

METAL-6 0.70 6.60
VIA-5 0.50 6.10
METAL-5 0.70 5.40
VIA-4 0.50 4.70
METAL-4 0.50 4.20
VIA-3 0.50 3.70
METAL-3 0.50 3.20
VIA-2 0.50 2.70
METAL-2 0.50 2.20
VIA-1 0.50 1.70
METAL-1 0.50 1.20
POLYSILICON 0.20 0.01
POLY-2 0.20 0.22
CONTACT 1.20 0.00
N-DIFFUSION 0.40 0.00
P-DIFFUSION 0.40 0.00
N-WELL 1.00 0.00

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

TWO INPUT NAND GATE NAVIGATOR:

W L
DEVICES W (m) L (m) TYPE
(Lambda) (Lambda)
N-1 1.60 0.120 10 02 Low leakage
N-2 1.60 0.120 10 02 Low leakage
P-1 1.60 0.120 10 02 Low leakage
P-2 1.60 0.120 10 02 Low leakage

PRECAUTIONS:

01. Leakage current must always low.

02. Layout must satisfy all the CMOS design rules.
03. Output value must be taken without a parallax error.

RESULT:

Design of the layout completed based on the CMOS design rules and lambda based
design rules. The characteristics of the OR- AND-INVERTER CIRCUIT are taken and the
relations between the internal parameters are also drawn above.

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

EXP – 12 CMOS INVERTER

AIM: Design the two-input CMOS INVERTER layout by using the micro wind V2.6
software and check that whether the design satisfies the CMOS design rules (or) not,
draw the output characteristics, finding the relations between parameters and list out
the layers which are used in that particular design.

LAYOUT DESIGNING:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

VOLTAGE VS TIME CHARACTERISTICS:

VOLTAGE VS VOLTAGE CHARACTERISTICS:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

VOLTAGE VS CURRENT CHARACTERISTICS:

CHARACTERISTICS OF LEVEL-3: ID Vs VD (NMOS)

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

CHARACTERISTICS OF LEVEL-3: ID Vs VD (PMOS)

CHARACTERISTICS OF LEVEL-3 ID Vs VG (NMOS):

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

CHARACTERISTICS OF LEVEL-3: ID Vs VG (PMOS):

PROPERTIES OF VDD:

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

PROPERTIES OF VSS:

PROPERTIES OF INPUT(A):

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

PROPERTIES OF OUTPUT(S1):

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

SIMULATION PARAMETERS:

CIRCUIT CMOS Inverter.MSK

* IC Technology: CMOS 0.12µm - 6 Metal
VDD 1 0 DC 1.20
VA 6 0 PULSE(0.00 1.20 0.23N 0.03N 0.03N 0.23N 0.50N)
* List of nodes
* "N2" corresponds to n°2
* "s1" corresponds to n°3
* "A" corresponds to n°6
* MOS devices
MN1 0 6 3 0 N1 W= 0.60U L= 0.12U
MP1 1 6 3 2 P1 W= 0.60U L= 0.12U
C2 2 0 0.475fF
C3 3 0 0.435fF
C4 1 0 0.190fF
C6 6 0 0.181fF
* n-MOS Model 3 :
* low leakage
.MODEL N1 NMOS LEVEL=3 VTO=0.40 U0=0.060 TOX= 3.5E-9
+LD =0.000U THETA=0.500 GAMMA=0.400
+PHI=0.200 KAPPA=0.060 VMAX=120.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
* p-MOS Model 3:
* low leakage
.MODEL P1 PMOS LEVEL=3 VTO=-0.45 U0=0.020 TOX= 3.5E-9
+LD =0.000U THETA=0.300 GAMMA=0.400
+PHI=0.200 KAPPA=0.060 VMAX=110.00K
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
* Transient analysis
.TEMP 27.0
.TRAN 0.50PS 5.00N
.PROBE
.END

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

LAYER LIST OF CMOS INVERTER GATE LAYOUT:

LAYER THICK (m) HIGHT (m)

METAL-6 0.70 6.60
VIA-5 0.50 6.10
METAL-5 0.70 5.40
VIA-4 0.50 4.70
METAL-4 0.50 4.20
VIA-3 0.50 3.70
METAL-3 0.50 3.20
VIA-2 0.50 2.70
METAL-2 0.50 2.20
VIA-1 0.50 1.70
METAL-1 0.50 1.20
POLYSILICON 0.20 0.01
POLY-2 0.20 0.22
CONTACT 1.20 0.00
N-DIFFUSION 0.40 0.00
P-DIFFUSION 0.40 0.00
N-WELL 1.00 0.00

Aditya Institute of Technology and Management, Tekkali

 Department of Electronics and Communication Engineering Digital System Design Lab (AR18)

CMOS INVERTER NAVIGATOR:

W L
DEVICES W (m) L (m) TYPE
(Lambda) (Lambda)
N-1 1.60 0.120 10 02 Low leakage
N-2 1.60 0.120 10 02 Low leakage
P-1 1.60 0.120 10 02 Low leakage
P-2 1.60 0.120 10 02 Low leakage

PRECAUTIONS:

01. Leakage current must always low.

02. Layout must satisfy all the CMOS design rules.
03. Output value must be taken without a parallax error.

RESULT:

Design of the layout completed based on the CMOS design rules and lambda based
design rules. The characteristics of the CMOS INVERTER are taken and the relations
between the internal parameters are also drawn above.

Aditya Institute of Technology and Management, Tekkali