TMS320F28003x Real-Time

Microcontrollers

Technical Reference Manual

Literature Number: SPRUIW9B

OCTOBER 2021 – REVISED JUNE 2023
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Table of Contents

Read This First.........................................................................................................................................................................87

About This Manual................................................................................................................................................................. 87
Notational Conventions.......................................................................................................................................................... 87
Glossary................................................................................................................................................................................. 87
Related Documentation From Texas Instruments.................................................................................................................. 87
Support Resources................................................................................................................................................................ 87
Trademarks............................................................................................................................................................................ 88
1 C2000™ Microcontrollers Software Support......................................................................................................................89
1.1 Introduction...................................................................................................................................................................... 90
1.2 C2000Ware Structure.......................................................................................................................................................90
1.3 Documentation................................................................................................................................................................. 90
1.4 Devices............................................................................................................................................................................ 90
1.5 Libraries........................................................................................................................................................................... 90
1.6 Code Composer Studio™ Integrated Development Environment (IDE).......................................................................... 90
1.7 SysConfig and PinMUX Tool............................................................................................................................................ 91
2 C28x Processor.....................................................................................................................................................................93
2.1 Introduction...................................................................................................................................................................... 94
2.2 C28X Related Collateral...................................................................................................................................................94
2.3 Features........................................................................................................................................................................... 94
2.4 Floating-Point Unit............................................................................................................................................................94
2.5 Trigonometric Math Unit (TMU)........................................................................................................................................95
2.6 VCRC Unit........................................................................................................................................................................95
3 System Control and Interrupts............................................................................................................................................ 97
3.1 Introduction...................................................................................................................................................................... 98
3.1.1 SYSCTL Related Collateral....................................................................................................................................... 98
3.1.2 LOCK Protection on System Configuration Registers............................................................................................... 98
3.1.3 EALLOW Protection.................................................................................................................................................. 98
3.2 Power Management......................................................................................................................................................... 99
3.3 Device Identification and Configuration Registers........................................................................................................... 99
3.4 Resets.............................................................................................................................................................................. 99
3.4.1 Reset Sources........................................................................................................................................................... 99
3.4.2 External Reset (XRS).............................................................................................................................................. 100
3.4.3 Simulate External Reset (SIMRESET. XRS)........................................................................................................... 100
3.4.4 Power-On Reset (POR)...........................................................................................................................................100
3.4.5 Brown-Out-Reset (BOR)..........................................................................................................................................100
3.4.6 Debugger Reset (SYSRS).......................................................................................................................................101
3.4.7 Simulate CPU Reset (SIMRESET. CPU1RS)..........................................................................................................101
3.4.8 Watchdog Reset (WDRS)........................................................................................................................................101
3.4.9 Hardware BIST Reset (HWBISTRS)....................................................................................................................... 101
3.4.10 NMI Watchdog Reset (NMIWDRS)........................................................................................................................101
3.4.11 DCSM Safe Code Copy Reset (SCCRESET)........................................................................................................101
3.5 Peripheral Interrupts.......................................................................................................................................................102
3.5.1 Interrupt Concepts................................................................................................................................................... 102
3.5.2 Interrupt Architecture............................................................................................................................................... 102
3.5.3 Interrupt Entry Sequence.........................................................................................................................................103
3.5.4 Configuring and Using Interrupts.............................................................................................................................104
3.5.5 PIE Channel Mapping..............................................................................................................................................106
3.5.6 Vector Tables........................................................................................................................................................... 108
3.6 Exceptions and Non-Maskable Interrupts.......................................................................................................................114
3.6.1 Configuring and Using NMIs.................................................................................................................................... 114

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3.6.2 Emulation Considerations........................................................................................................................................ 114

3.6.3 NMI Sources............................................................................................................................................................ 114
3.6.4 CRC Fail.................................................................................................................................................................. 115
3.6.5 ERAD NMI............................................................................................................................................................... 115
3.6.6 Illegal Instruction Trap (ITRAP)................................................................................................................................115
3.6.7 Error Pin...................................................................................................................................................................115
3.7 Clocking..........................................................................................................................................................................116
3.7.1 Clock Sources..........................................................................................................................................................117
3.7.2 Derived Clocks........................................................................................................................................................ 120
3.7.3 Device Clock Domains............................................................................................................................................ 120
3.7.4 XCLKOUT................................................................................................................................................................121
3.7.5 Clock Connectivity................................................................................................................................................... 122
3.7.6 Clock Source and PLL Setup.................................................................................................................................. 123
3.7.7 Using an External Crystal or Resonator.................................................................................................................. 123
3.7.8 Using an External Oscillator.................................................................................................................................... 123
3.7.9 Choosing PLL Settings............................................................................................................................................ 124
3.7.10 System Clock Setup.............................................................................................................................................. 124
3.7.11 SYS PLL Bypass....................................................................................................................................................125
3.7.12 Clock (OSCCLK) Failure Detection....................................................................................................................... 125
3.8 32-Bit CPU Timers 0/1/2................................................................................................................................................ 128
3.9 Watchdog Timer............................................................................................................................................................. 129
3.9.1 Servicing the Watchdog Timer.................................................................................................................................130
3.9.2 Minimum Window Check......................................................................................................................................... 130
3.9.3 Watchdog Reset or Watchdog Interrupt Mode.........................................................................................................131
3.9.4 Watchdog Operation in Low Power Modes............................................................................................................. 131
3.9.5 Emulation Considerations........................................................................................................................................131
3.10 Low Power Modes........................................................................................................................................................132
3.10.1 Clock-Gating Low-Power Modes........................................................................................................................... 132
3.10.2 IDLE.......................................................................................................................................................................132
3.10.3 STANDBY.............................................................................................................................................................. 133
3.10.4 HALT......................................................................................................................................................................133
3.10.5 Flash Power-down Considerations........................................................................................................................134
3.11 Memory Controller Module........................................................................................................................................... 135
3.11.1 Dedicated RAM (Mx RAM).....................................................................................................................................135
3.11.2 Local Shared RAM (LSx RAM).............................................................................................................................. 135
3.11.3 Global Shared RAM (GSx RAM)............................................................................................................................136
3.11.4 CLA-CPU Message RAM.......................................................................................................................................136
3.11.5 CLA-DMA Message RAM...................................................................................................................................... 136
3.11.6 Access Arbitration.................................................................................................................................................. 136
3.11.7 Access Protection.................................................................................................................................................. 138
3.11.8 Memory Error Detection and Correction, and Error Handling................................................................................ 139
3.11.9 Application Test Hooks for Error Detection and Correction....................................................................................141
3.11.10 RAM Initialization................................................................................................................................................. 141
3.12 JTAG............................................................................................................................................................................ 142
3.13 Live Firmware Update.................................................................................................................................................. 142
3.13.1 LFU Background....................................................................................................................................................142
3.13.2 LFU Switchover Steps........................................................................................................................................... 142
3.13.3 Device Features Supporting LFU.......................................................................................................................... 143
3.13.4 LFU Switchover..................................................................................................................................................... 146
3.13.5 LFU Resources......................................................................................................................................................146
3.14 System Control Register Configuration Restrictions.................................................................................................... 147
3.15 Software....................................................................................................................................................................... 148
3.15.1 INTERRUPT Examples......................................................................................................................................... 148
3.15.2 SYSCTL Examples................................................................................................................................................150
3.15.3 TIMER Examples...................................................................................................................................................151
3.15.4 LPM Examples...................................................................................................................................................... 151
3.15.5 MEMCFG Examples..............................................................................................................................................153
3.15.6 WATCHDOG Examples.........................................................................................................................................154
3.16 System Control Registers............................................................................................................................................ 155
3.16.1 SYSCTRL Base Address Table............................................................................................................................. 155
3.16.2 ACCESS_PROTECTION_REGS Registers..........................................................................................................156

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3.16.3 CLK_CFG_REGS Registers..................................................................................................................................184

3.16.4 CPU_SYS_REGS Registers................................................................................................................................. 205
3.16.5 CPUTIMER_REGS Registers............................................................................................................................... 251
3.16.6 DEV_CFG_REGS Registers................................................................................................................................. 258
3.16.7 DMA_CLA_SRC_SEL_REGS Registers...............................................................................................................288
3.16.8 MEM_CFG_REGS Registers................................................................................................................................ 295
3.16.9 MEMORY_ERROR_REGS Registers................................................................................................................... 347
3.16.10 NMI_INTRUPT_REGS Registers........................................................................................................................ 369
3.16.11 PERIPH_AC_REGS Registers............................................................................................................................ 386
3.16.12 PIE_CTRL_REGS Registers............................................................................................................................... 433
3.16.13 SYNC_SOC_REGS Registers............................................................................................................................ 473
3.16.14 SYS_STATUS_REGS Registers......................................................................................................................... 479
3.16.15 TEST_ERROR_REGS Registers........................................................................................................................ 486
3.16.16 UID_REGS Registers.......................................................................................................................................... 490
3.16.17 WD_REGS Registers.......................................................................................................................................... 499
3.16.18 XINT_REGS Registers........................................................................................................................................ 506
3.16.19 LFU_REGS Registers......................................................................................................................................... 515
3.16.20 Register to Driverlib Function Mapping............................................................................................................... 527
4 ROM Code and Peripheral Booting...................................................................................................................................547
4.1 Introduction.................................................................................................................................................................... 548
4.2 ROM Related Collateral................................................................................................................................................. 548
4.3 Device Boot Sequence...................................................................................................................................................549
4.4 Device Boot Modes........................................................................................................................................................ 549
4.4.1 Default Boot Modes................................................................................................................................................. 549
4.4.2 Custom Boot Modes................................................................................................................................................ 550
4.5 Device Boot Configurations............................................................................................................................................550
4.5.1 Configuring Boot Mode Pins....................................................................................................................................551
4.5.2 Configuring Boot Mode Table Options.....................................................................................................................553
4.5.3 Boot Mode Example Use Cases..............................................................................................................................554
4.6 Device Boot Flow Diagrams...........................................................................................................................................555
4.6.1 Boot Flow.................................................................................................................................................................555
4.6.2 Emulation Boot Flow................................................................................................................................................557
4.6.3 Standalone Boot Flow ............................................................................................................................................ 558
4.7 Device Reset and Exception Handling...........................................................................................................................559
4.7.1 Reset Causes and Handling....................................................................................................................................559
4.7.2 Exceptions and Interrupts Handling.........................................................................................................................559
4.8 Boot ROM Description................................................................................................................................................... 560
4.8.1 Boot ROM Configuration Registers......................................................................................................................... 560
4.8.2 Entry Points............................................................................................................................................................. 561
4.8.3 Wait Points...............................................................................................................................................................562
4.8.4 Secure Flash Boot................................................................................................................................................... 562
4.8.5 Live Firmware Update (LFU) Flash Boot................................................................................................................. 565
4.8.6 Memory Maps..........................................................................................................................................................566
4.8.7 ROM Tables.............................................................................................................................................................567
4.8.8 Boot Modes and Loaders........................................................................................................................................ 567
4.8.9 GPIO Assignments.................................................................................................................................................. 583
4.8.10 Secure ROM Function APIs.................................................................................................................................. 585
4.8.11 Clock Initializations................................................................................................................................................ 586
4.8.12 Boot Status Information......................................................................................................................................... 586
4.8.13 ROM Version......................................................................................................................................................... 588
4.9 Application Notes for Using the Bootloaders..................................................................................................................588
4.9.1 Bootloader Data Stream Structure.......................................................................................................................... 588
Example 4-2. Data Stream Structure 8-bit........................................................................................................................590
4.9.2 The C2000 Hex Utility..............................................................................................................................................590
Example 4-3. HEX2000.exe Command Syntax................................................................................................................591
4.10 Software....................................................................................................................................................................... 592
4.10.1 BOOT Examples....................................................................................................................................................592
5 Dual Code Security Module (DCSM)................................................................................................................................. 593
5.1 Introduction.................................................................................................................................................................... 594
5.1.1 DCSM Related Collateral........................................................................................................................................ 594
5.2 Functional Description....................................................................................................................................................594

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5.2.1 CSM Passwords...................................................................................................................................................... 595

5.2.2 Emulation Code Security Logic (ECSL)...................................................................................................................597
5.2.3 CPU Secure Logic................................................................................................................................................... 597
5.2.4 Password Lock........................................................................................................................................................ 597
5.2.5 JTAGLOCK.............................................................................................................................................................. 598
5.2.6 Link Pointer and Zone Select.................................................................................................................................. 598
5.2.7 C Code Example to Get Zone Select Block Addr for Zone1....................................................................................601
5.3 Flash and OTP Erase/Program......................................................................................................................................601
5.4 Secure Copy Code.........................................................................................................................................................601
5.5 SecureCRC.................................................................................................................................................................... 602
5.6 CSM Impact on Other On-Chip Resources....................................................................................................................603
5.7 Incorporating Code Security in User Applications..........................................................................................................604
5.7.1 Environments That Require Security Unlocking...................................................................................................... 604
5.7.2 CSM Password Match Flow.................................................................................................................................... 604
5.7.3 C Code Example to Unsecure C28x Zone1............................................................................................................ 606
5.7.4 C Code Example to Resecure C28x Zone1............................................................................................................ 606
5.7.5 Environments That Require ECSL Unlocking..........................................................................................................606
5.7.6 ECSL Password Match Flow................................................................................................................................... 606
5.7.7 ECSL Disable Considerations for any Zone............................................................................................................ 608
5.7.8 Device Unique ID.....................................................................................................................................................608
5.8 Software......................................................................................................................................................................... 609
5.8.1 DCSM Examples..................................................................................................................................................... 609
5.9 DCSM Registers............................................................................................................................................................ 609
5.9.1 DCSM Base Address Table..................................................................................................................................... 609
5.9.2 DCSM_Z1_REGS Registers................................................................................................................................... 610
5.9.3 DCSM_Z2_REGS Registers................................................................................................................................... 655
5.9.4 DCSM_COMMON_REGS Registers.......................................................................................................................691
5.9.5 DCSM_Z1_OTP Registers...................................................................................................................................... 707
5.9.6 DCSM_Z2_OTP Registers...................................................................................................................................... 724
6 Flash Module.......................................................................................................................................................................735
6.1 Introduction to Flash and OTP Memory......................................................................................................................... 736
6.1.1 FLASH Related Collateral....................................................................................................................................... 736
6.1.2 Features.................................................................................................................................................................. 736
6.1.3 Flash Tools.............................................................................................................................................................. 737
6.1.4 Default Flash Configuration..................................................................................................................................... 737
6.2 Flash Bank, OTP, and Pump.......................................................................................................................................... 737
6.3 Flash Module Controller (FMC)......................................................................................................................................738
6.4 Flash and OTP Power-Down Modes and Wakeup.........................................................................................................738
6.5 Active Grace Period....................................................................................................................................................... 740
6.6 Flash and OTP Performance......................................................................................................................................... 740
6.7 Flash Read Interface......................................................................................................................................................741
6.7.1 C28x-FMC Flash Read Interface.............................................................................................................................741
6.8 Flash Erase and Program.............................................................................................................................................. 743
6.8.1 Erase....................................................................................................................................................................... 743
6.8.2 Program...................................................................................................................................................................743
6.8.3 Verify........................................................................................................................................................................744
6.9 Error Correction Code (ECC) Protection........................................................................................................................744
6.9.1 Single-Bit Data Error................................................................................................................................................746
6.9.2 Uncorrectable Error................................................................................................................................................. 747
6.9.3 SECDED Logic Correctness Check........................................................................................................................ 747
6.10 Reserved Locations Within Flash and OTP................................................................................................................. 748
6.11 Migrating an Application from RAM to Flash................................................................................................................ 748
6.12 Procedure to Change the Flash Control Registers...................................................................................................... 749
6.13 Software....................................................................................................................................................................... 750
6.13.1 FLASH Examples.................................................................................................................................................. 750
6.14 Flash Registers............................................................................................................................................................ 752
6.14.1 FLASH Base Address Table.................................................................................................................................. 752
6.14.2 FLASH_CTRL_REGS Registers........................................................................................................................... 753
6.14.3 FLASH_ECC_REGS Registers............................................................................................................................. 763
6.14.4 FLASH Registers to Driverlib Functions................................................................................................................ 785
7 Control Law Accelerator (CLA)..........................................................................................................................................789

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7.1 Introduction.................................................................................................................................................................... 790

7.1.1 Features.................................................................................................................................................................. 790
7.1.2 CLA Related Collateral............................................................................................................................................ 790
7.1.3 Block Diagram......................................................................................................................................................... 791
7.2 CLA Interface................................................................................................................................................................. 792
7.2.1 CLA Memory............................................................................................................................................................792
7.2.2 CLA Memory Bus.................................................................................................................................................... 793
7.2.3 Shared Peripherals and EALLOW Protection..........................................................................................................793
7.2.4 CLA Tasks and Interrupt Vectors............................................................................................................................. 794
7.3 CLA and CPU Arbitration............................................................................................................................................... 798
7.3.1 CLA Message RAM................................................................................................................................................. 798
7.3.2 Peripheral Registers (ePWM, HRPWM, Comparator).............................................................................................798
7.4 CLA Configuration and Debug....................................................................................................................................... 799
7.4.1 Building a CLA Application...................................................................................................................................... 799
7.4.2 Typical CLA Initialization Sequence........................................................................................................................ 799
7.4.3 Debugging CLA Code..............................................................................................................................................800
7.4.4 CLA Illegal Opcode Behavior.................................................................................................................................. 802
7.4.5 Resetting the CLA................................................................................................................................................... 803
7.5 Pipeline.......................................................................................................................................................................... 803
7.5.1 Pipeline Overview....................................................................................................................................................803
7.5.2 CLA Pipeline Alignment...........................................................................................................................................804
7.5.3 Parallel Instructions................................................................................................................................................. 808
7.5.4 CLA Task Execution Latency...................................................................................................................................808
7.6 Software......................................................................................................................................................................... 809
7.6.1 CLA Examples.........................................................................................................................................................809
7.7 Instruction Set................................................................................................................................................................ 813
7.7.1 Instruction Descriptions........................................................................................................................................... 813
7.7.2 Addressing Modes and Encoding............................................................................................................................814
7.7.3 Instructions.............................................................................................................................................................. 816
7.8 CLA Registers................................................................................................................................................................ 932
7.8.1 CLA Base Address Table.........................................................................................................................................932
7.8.2 CLA_ONLY_REGS Registers..................................................................................................................................934
7.8.3 CLA_SOFTINT_REGS Registers............................................................................................................................942
7.8.4 CLA_REGS Registers............................................................................................................................................. 946
7.8.5 CLA Registers to Driverlib Functions.......................................................................................................................993
8 Dual-Clock Comparator (DCC)...........................................................................................................................................997
8.1 Introduction.................................................................................................................................................................... 998
8.1.1 Features.................................................................................................................................................................. 998
8.1.2 Block Diagram......................................................................................................................................................... 998
8.2 Module Operation...........................................................................................................................................................999
8.2.1 Configuring DCC Counters....................................................................................................................................1000
8.2.2 Single-Shot Measurement Mode........................................................................................................................... 1001
8.2.3 Continuous Monitoring Mode.................................................................................................................................1002
8.2.4 Error Conditions.....................................................................................................................................................1003
8.3 Interrupts...................................................................................................................................................................... 1005
8.4 Software....................................................................................................................................................................... 1006
8.4.1 DCC Examples...................................................................................................................................................... 1006
8.5 DCC Registers............................................................................................................................................................. 1007
8.5.1 DCC Base Address Table......................................................................................................................................1008
8.5.2 DCC_REGS Registers.......................................................................................................................................... 1009
8.5.3 DCC Registers to Driverlib Functions....................................................................................................................1019
9 Background CRC-32 (BGCRC)........................................................................................................................................ 1021
9.1 Introduction.................................................................................................................................................................. 1022
9.1.1 BGCRC Related Collateral.................................................................................................................................... 1022
9.1.2 Features................................................................................................................................................................ 1022
9.1.3 Block Diagram....................................................................................................................................................... 1022
9.1.4 Memory Wait States and Memory Map................................................................................................................. 1023
9.2 Functional Description..................................................................................................................................................1024
9.2.1 Data Read Unit...................................................................................................................................................... 1024
9.2.2 CRC-32 Compute Unit...........................................................................................................................................1024
9.2.3 CRC Notification Unit.............................................................................................................................................1025

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9.2.4 Operating Modes................................................................................................................................................... 1026

9.2.5 BGCRC Watchdog.................................................................................................................................................1026
9.2.6 Hardware and Software Faults Protection.............................................................................................................1026
9.3 Application of the BGCRC............................................................................................................................................1026
9.3.1 Software Configuration.......................................................................................................................................... 1027
9.3.2 Decision on Error Response Severity....................................................................................................................1028
9.3.3 Decision of Controller for CLA_CRC..................................................................................................................... 1028
9.3.4 Execution of Time Critical Code from Wait-Stated Memories................................................................................1028
9.3.5 BGCRC Execution.................................................................................................................................................1028
9.3.6 Debug/Error Response for BGCRC Errors............................................................................................................1030
9.3.7 BGCRC Golden CRC-32 Value Computation........................................................................................................1031
9.4 Software....................................................................................................................................................................... 1032
9.4.1 BGCRC Examples.................................................................................................................................................1032
9.5 BGCRC Registers........................................................................................................................................................ 1033
9.5.1 BGCRC Base Address Table.................................................................................................................................1033
9.5.2 BGCRC_REGS Registers..................................................................................................................................... 1034
9.5.3 BGCRC Registers to Driverlib Functions...............................................................................................................1060
10 General-Purpose Input/Output (GPIO)..........................................................................................................................1063
10.1 Introduction................................................................................................................................................................ 1064
10.1.1 GPIO Related Collateral...................................................................................................................................... 1066
10.2 Configuration Overview..............................................................................................................................................1067
10.3 Digital Inputs on ADC Pins (AIOs)............................................................................................................................. 1067
10.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)....................................................................................................1068
10.5 Digital General-Purpose I/O Control.......................................................................................................................... 1068
10.6 Input Qualification...................................................................................................................................................... 1071
10.6.1 No Synchronization (Asynchronous Input).......................................................................................................... 1071
10.6.2 Synchronization to SYSCLKOUT Only................................................................................................................1071
10.6.3 Qualification Using a Sampling Window..............................................................................................................1071
10.7 GPIO and Peripheral Muxing..................................................................................................................................... 1074
10.7.1 GPIO Muxing....................................................................................................................................................... 1075
10.7.2 Peripheral Muxing................................................................................................................................................1078
10.8 Internal Pullup Configuration Requirements.............................................................................................................. 1079
10.9 Software..................................................................................................................................................................... 1080
10.9.1 GPIO Examples...................................................................................................................................................1080
10.9.2 LED Examples.....................................................................................................................................................1080
10.10 GPIO Registers........................................................................................................................................................ 1081
10.10.1 GPIO Base Address Table.................................................................................................................................1081
10.10.2 GPIO_CTRL_REGS Registers..........................................................................................................................1082
10.10.3 GPIO_DATA_REGS Registers.......................................................................................................................... 1174
10.10.4 GPIO_DATA_READ_REGS Registers.............................................................................................................. 1197
10.10.5 GPIO Registers to Driverlib Functions...............................................................................................................1200
11 Crossbar (X-BAR)........................................................................................................................................................... 1205
11.1 Input X-BAR and CLB Input X-BAR ...........................................................................................................................1206
11.1.1 CLB Input X-BAR................................................................................................................................................. 1208
11.2 ePWM, CLB, and GPIO Output X-BAR...................................................................................................................... 1209
11.2.1 ePWM X-BAR...................................................................................................................................................... 1209
11.2.2 CLB X-BAR.......................................................................................................................................................... 1211
11.2.3 GPIO Output X-BAR............................................................................................................................................ 1214
11.2.4 CLB Output X-BAR.............................................................................................................................................. 1216
11.2.5 X-BAR Flags........................................................................................................................................................ 1217
11.3 XBAR Registers..........................................................................................................................................................1219
11.3.1 XBAR Base Address Table.................................................................................................................................. 1219
11.3.2 INPUT_XBAR_REGS Registers.......................................................................................................................... 1220
11.3.3 XBAR_REGS Registers.......................................................................................................................................1240
11.3.4 EPWM_XBAR_REGS Registers..........................................................................................................................1267
11.3.5 CLB_XBAR_REGS Registers..............................................................................................................................1360
11.3.6 OUTPUT_XBAR_REGS Registers...................................................................................................................... 1453
11.3.7 Register to Driverlib Function Mapping................................................................................................................1554
12 Direct Memory Access (DMA)........................................................................................................................................1561
12.1 Introduction................................................................................................................................................................ 1562
12.1.1 Features.............................................................................................................................................................. 1562

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12.1.2 Block Diagram..................................................................................................................................................... 1563

12.2 Architecture................................................................................................................................................................ 1564
12.2.1 Peripheral Interrupt Event Trigger Sources......................................................................................................... 1564
12.2.2 DMA Bus............................................................................................................................................................. 1569
12.3 Address Pointer and Transfer Control........................................................................................................................1569
12.4 Pipeline Timing and Throughput................................................................................................................................ 1575
12.5 CPU and CLA Arbitration........................................................................................................................................... 1576
12.6 Channel Priority..........................................................................................................................................................1577
12.6.1 Round-Robin Mode............................................................................................................................................. 1577
12.6.2 Channel 1 High-Priority Mode............................................................................................................................. 1578
12.7 Overrun Detection Feature.........................................................................................................................................1578
12.8 Software..................................................................................................................................................................... 1579
12.8.1 DMA Examples....................................................................................................................................................1579
12.9 DMA Registers........................................................................................................................................................... 1579
12.9.1 DMA Base Address Table....................................................................................................................................1579
12.9.2 DMA_REGS Registers........................................................................................................................................ 1580
12.9.3 DMA_CH_REGS Registers................................................................................................................................. 1585
12.9.4 DMA Registers to Driverlib Functions..................................................................................................................1612
13 Embedded Real-time Analysis and Diagnostic (ERAD).............................................................................................. 1615
13.1 Introduction................................................................................................................................................................ 1616
13.1.1 ERAD Related Collateral..................................................................................................................................... 1616
13.2 Enhanced Bus Comparator Unit................................................................................................................................ 1617
13.2.1 Enhanced Bus Comparator Unit Operations....................................................................................................... 1617
13.2.2 Event Masking and Exporting..............................................................................................................................1618
13.3 System Event Counter Unit........................................................................................................................................1619
13.3.1 System Event Counter Modes.............................................................................................................................1619
13.3.2 Reset on Event.................................................................................................................................................... 1624
13.3.3 Operation Conditions...........................................................................................................................................1624
13.4 ERAD Ownership, Initialization and Reset.................................................................................................................1624
13.5 ERAD Programming Sequence................................................................................................................................. 1625
13.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence....................................................... 1625
13.5.2 Timer and Counter Programming Sequence....................................................................................................... 1626
13.6 Cyclic Redundancy Check Unit..................................................................................................................................1626
13.6.1 CRC Unit Qualifier............................................................................................................................................... 1627
13.6.2 CRC Unit Programming Sequence......................................................................................................................1628
13.7 Program Counter Trace..............................................................................................................................................1628
13.7.1 Functional Block Diagram....................................................................................................................................1629
13.7.2 Trace Qualification Modes................................................................................................................................... 1630
13.7.3 Trace Memory......................................................................................................................................................1633
13.7.4 Trace Input Signal Conditioning...........................................................................................................................1634
13.7.5 PC Trace Software Operation..............................................................................................................................1635
13.7.6 Trace Operation in Debug Mode......................................................................................................................... 1635
13.8 Software..................................................................................................................................................................... 1636
13.8.1 ERAD Registers to Driverlib Functions................................................................................................................1636
13.8.2 ERAD Examples..................................................................................................................................................1637
13.9 ERAD Registers......................................................................................................................................................... 1646
13.9.1 ERAD Base Address Table..................................................................................................................................1646
13.9.2 ERAD_GLOBAL_REGS Registers......................................................................................................................1647
13.9.3 ERAD_HWBP_REGS Registers......................................................................................................................... 1668
13.9.4 ERAD_COUNTER_REGS Registers.................................................................................................................. 1675
13.9.5 ERAD_CRC_GLOBAL_REGS Registers............................................................................................................ 1686
13.9.6 ERAD_CRC_REGS Registers............................................................................................................................ 1689
13.9.7 ERAD Registers to Driverlib Functions................................................................................................................1692
14 Host Interface Controller (HIC)...................................................................................................................................... 1695
14.1 Introduction................................................................................................................................................................ 1696
14.1.1 HIC Related Collateral.........................................................................................................................................1696
14.1.2 Features.............................................................................................................................................................. 1696
14.1.3 Block Diagram..................................................................................................................................................... 1696
14.2 Functional Description................................................................................................................................................1698
14.2.1 Memory Map........................................................................................................................................................1698
14.2.2 Connections.........................................................................................................................................................1699

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14.2.3 Interrupts and Triggers........................................................................................................................................ 1700

14.3 Operation................................................................................................................................................................... 1702
14.3.1 Mailbox Access Mode Overview..........................................................................................................................1702
14.3.2 Direct Access Mode Overview.............................................................................................................................1704
14.3.3 Controlling Reads and Writes.............................................................................................................................. 1706
14.3.4 Data Lines, Data Width, Data Packing and Unpacking....................................................................................... 1708
14.3.5 Address Translation............................................................................................................................................. 1711
14.3.6 Access Errors...................................................................................................................................................... 1712
14.3.7 Security................................................................................................................................................................1712
14.3.8 HIC Usage........................................................................................................................................................... 1713
14.4 Usage Scenarious for Reduced Number of Pins....................................................................................................... 1713
14.5 Software..................................................................................................................................................................... 1714
14.5.1 HIC Examples......................................................................................................................................................1714
14.6 HIC Registers.............................................................................................................................................................1715
14.6.1 HIC Base Address Table..................................................................................................................................... 1715
14.6.2 HIC_CFG_REGS Registers................................................................................................................................ 1716
14.6.3 HIC Registers to Driverlib Functions................................................................................................................... 1785
15 Analog Subsystem......................................................................................................................................................... 1789
15.1 Introduction................................................................................................................................................................ 1790
15.1.1 Features.............................................................................................................................................................. 1790
15.1.2 Block Diagram..................................................................................................................................................... 1790
15.2 Optimizing Power-Up Time........................................................................................................................................ 1795
15.3 Digital Inputs on ADC Pins (AIOs)............................................................................................................................. 1796
15.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)....................................................................................................1796
15.5 Analog Pins and Internal Connections....................................................................................................................... 1797
15.6 Lock Registers........................................................................................................................................................... 1800
15.7 Analog Subsystem Registers..................................................................................................................................... 1800
15.7.1 ASBSYS Base Address Table............................................................................................................................. 1800
15.7.2 ANALOG_SUBSYS_REGS Registers.................................................................................................................1801
15.7.3 ASYSCTL Registers to Driverlib Functions......................................................................................................... 1815
16 Analog-to-Digital Converter (ADC)................................................................................................................................1817
16.1 Introduction................................................................................................................................................................ 1818
16.1.1 ADC Related Collateral....................................................................................................................................... 1818
16.1.2 Features.............................................................................................................................................................. 1819
16.1.3 Block Diagram..................................................................................................................................................... 1820
16.2 ADC Configurability....................................................................................................................................................1821
16.2.1 Clock Configuration............................................................................................................................................. 1821
16.2.2 Resolution............................................................................................................................................................1821
16.2.3 Voltage Reference............................................................................................................................................... 1822
16.2.4 Signal Mode.........................................................................................................................................................1823
16.2.5 Expected Conversion Results............................................................................................................................. 1823
16.2.6 Interpreting Conversion Results.......................................................................................................................... 1823
16.3 SOC Principle of Operation........................................................................................................................................1824
16.3.1 SOC Configuration.............................................................................................................................................. 1825
16.3.2 Trigger Operation.................................................................................................................................................1825
16.3.3 ADC Acquisition (Sample and Hold) Window......................................................................................................1825
16.3.4 ADC Input Models............................................................................................................................................... 1825
16.3.5 Channel Selection............................................................................................................................................... 1826
16.4 SOC Configuration Examples.................................................................................................................................... 1827
16.4.1 Single Conversion from ePWM Trigger............................................................................................................... 1827
16.4.2 Oversampled Conversion from ePWM Trigger....................................................................................................1827
16.4.3 Multiple Conversions from CPU Timer Trigger.................................................................................................... 1828
16.4.4 Software Triggering of SOCs...............................................................................................................................1829
16.5 ADC Conversion Priority............................................................................................................................................ 1829
16.6 Burst Mode.................................................................................................................................................................1832
16.6.1 Burst Mode Example........................................................................................................................................... 1832
16.6.2 Burst Mode Priority Example............................................................................................................................... 1833
16.7 EOC and Interrupt Operation..................................................................................................................................... 1834
16.7.1 Interrupt Overflow................................................................................................................................................ 1835
16.7.2 Continue to Interrupt Mode..................................................................................................................................1835
16.7.3 Early Interrupt Configuration Mode......................................................................................................................1836

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16.8 Post-Processing Blocks............................................................................................................................................. 1837

16.8.1 PPB Offset Correction......................................................................................................................................... 1838
16.8.2 PPB Error Calculation..........................................................................................................................................1838
16.8.3 PPB Limit Detection and Zero-Crossing Detection..............................................................................................1838
16.8.4 PPB Sample Delay Capture................................................................................................................................ 1840
16.9 Opens/Shorts Detection Circuit (OSDETECT)...........................................................................................................1841
16.9.1 Implementation.................................................................................................................................................... 1842
16.9.2 Detecting an Open Input Pin............................................................................................................................... 1842
16.9.3 Detecting a Shorted Input Pin..............................................................................................................................1842
16.10 Power-Up Sequence................................................................................................................................................ 1843
16.11 ADC Calibration........................................................................................................................................................1843
16.11.1 ADC Zero Offset Calibration.............................................................................................................................. 1843
16.12 ADC Timings............................................................................................................................................................ 1844
16.12.1 ADC Timing Diagrams....................................................................................................................................... 1844
16.13 Additional Information.............................................................................................................................................. 1847
16.13.1 Ensuring Synchronous Operation......................................................................................................................1847
16.13.2 Choosing an Acquisition Window Duration........................................................................................................1850
16.13.3 Achieving Simultaneous Sampling.................................................................................................................... 1852
16.13.4 Result Register Mapping................................................................................................................................... 1852
16.13.5 Internal Temperature Sensor............................................................................................................................. 1852
16.13.6 Designing an External Reference Circuit...........................................................................................................1853
16.13.7 ADC-DAC Loopback Testing............................................................................................................................. 1853
16.13.8 Internal Test Mode............................................................................................................................................. 1854
16.13.9 ADC Gain Balancing..........................................................................................................................................1854
16.14 Software................................................................................................................................................................... 1855
16.14.1 ADC Examples.................................................................................................................................................. 1855
16.15 ADC Registers......................................................................................................................................................... 1860
16.15.1 ADC Base Address Table.................................................................................................................................. 1860
16.15.2 ADC_RESULT_REGS Registers.......................................................................................................................1861
16.15.3 ADC_REGS Registers.......................................................................................................................................1883
16.15.4 ADC Registers to Driverlib Functions................................................................................................................ 1996
17 Buffered Digital-to-Analog Converter (DAC)................................................................................................................2001
17.1 Introduction................................................................................................................................................................ 2002
17.1.1 DAC Related Collateral....................................................................................................................................... 2002
17.1.2 Features.............................................................................................................................................................. 2002
17.1.3 Block Diagram..................................................................................................................................................... 2003
17.2 Using the DAC........................................................................................................................................................... 2003
17.2.1 Initialization Sequence.........................................................................................................................................2004
17.2.2 DAC Offset Adjustment........................................................................................................................................2004
17.2.3 EPWMSYNCPER Signal..................................................................................................................................... 2004
17.3 Lock Registers........................................................................................................................................................... 2004
17.4 Software..................................................................................................................................................................... 2005
17.4.1 DAC Examples.................................................................................................................................................... 2005
17.5 DAC Registers........................................................................................................................................................... 2006
17.5.1 DAC Base Address Table.................................................................................................................................... 2006
17.5.2 DAC_REGS Registers.........................................................................................................................................2007
17.5.3 DAC Registers to Driverlib Functions.................................................................................................................. 2014
18 Comparator Subsystem (CMPSS)................................................................................................................................. 2017
18.1 Introduction................................................................................................................................................................ 2018
18.1.1 CMPSS Related Collateral.................................................................................................................................. 2018
18.1.2 Features.............................................................................................................................................................. 2018
18.1.3 Block Diagram..................................................................................................................................................... 2019
18.2 Comparator................................................................................................................................................................ 2019
18.3 Reference DAC.......................................................................................................................................................... 2020
18.4 Ramp Generator........................................................................................................................................................ 2021
18.4.1 Ramp Generator Overview..................................................................................................................................2021
18.4.2 Ramp Generator Behavior...................................................................................................................................2022
18.4.3 Ramp Generator Behavior at Corner Cases....................................................................................................... 2023
18.5 Digital Filter................................................................................................................................................................ 2024
18.5.1 Filter Initialization Sequence................................................................................................................................2025
18.6 Using the CMPSS...................................................................................................................................................... 2025

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18.6.1 LATCHCLR, EPWMSYNCPER and EPWMBLANK Signals ...............................................................................2025

18.6.2 Synchronizer, Digital Filter, and Latch Delays..................................................................................................... 2025
18.6.3 Calibrating the CMPSS........................................................................................................................................2026
18.6.4 Enabling and Disabling the CMPSS Clock.......................................................................................................... 2026
18.7 Software..................................................................................................................................................................... 2027
18.7.1 CMPSS Examples............................................................................................................................................... 2027
18.8 CMPSS Registers...................................................................................................................................................... 2028
18.8.1 CMPSS Base Address Table...............................................................................................................................2028
18.8.2 CMPSS_REGS Registers................................................................................................................................... 2029
18.8.3 CMPSS Registers to Driverlib Functions.............................................................................................................2053
19 Sigma Delta Filter Module (SDFM)................................................................................................................................ 2057
19.1 Introduction................................................................................................................................................................ 2058
19.1.1 SDFM Related Collateral.....................................................................................................................................2058
19.1.2 Features.............................................................................................................................................................. 2059
19.1.3 Block Diagram..................................................................................................................................................... 2060
19.2 Configuring Device Pins.............................................................................................................................................2062
19.3 Input Qualification...................................................................................................................................................... 2063
19.4 Input Control Unit....................................................................................................................................................... 2064
19.5 SDFM Clock Control.................................................................................................................................................. 2064
19.6 Sinc Filter................................................................................................................................................................... 2065
19.6.1 Data Rate and Latency of the Sinc Filter.............................................................................................................2067
19.7 Data (Primary) Filter Unit........................................................................................................................................... 2067
19.7.1 32-bit or 16-bit Data Filter Output Representation...............................................................................................2068
19.7.2 Data FIFO............................................................................................................................................................2068
19.7.3 SDSYNC Event................................................................................................................................................... 2070
19.8 Comparator (Secondary) Filter Unit........................................................................................................................... 2072
19.8.1 Higher Threshold (HLT) Comparators ................................................................................................................ 2074
19.8.2 Lower Threshold (LLT) Comparators ..................................................................................................................2074
19.8.3 Digital Filter..........................................................................................................................................................2075
19.9 Theoretical SDFM Filter Output................................................................................................................................. 2076
19.10 Interrupt Unit............................................................................................................................................................ 2078
19.10.1 SDFM (SDyERR) Interrupt Sources ................................................................................................................. 2078
19.10.2 Data Ready (DRINT) Interrupt Sources.............................................................................................................2079
19.11 Software................................................................................................................................................................... 2081
19.11.1 SDFM Examples................................................................................................................................................ 2081
19.12 SDFM Registers.......................................................................................................................................................2084
19.12.1 SDFM Base Address Table............................................................................................................................... 2084
19.12.2 SDFM_REGS Registers.................................................................................................................................... 2085
19.12.3 SDFM Registers to Driverlib Functions............................................................................................................. 2179
20 Enhanced Pulse Width Modulator (ePWM)...................................................................................................................2185
20.1 Introduction................................................................................................................................................................ 2186
20.1.1 EPWM Related Collateral....................................................................................................................................2187
20.1.2 Submodule Overview.......................................................................................................................................... 2188
20.2 Configuring Device Pins.............................................................................................................................................2193
20.3 ePWM Modules Overview..........................................................................................................................................2193
20.4 Time-Base (TB) Submodule.......................................................................................................................................2195
20.4.1 Purpose of the Time-Base Submodule................................................................................................................2195
20.4.2 Controlling and Monitoring the Time-Base Submodule....................................................................................... 2196
20.4.3 Calculating PWM Period and Frequency.............................................................................................................2198
20.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules..................................................................... 2204
20.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules............................................... 2204
20.4.6 Time-Base Counter Modes and Timing Waveforms............................................................................................ 2205
20.4.7 Global Load......................................................................................................................................................... 2208
20.5 Counter-Compare (CC) Submodule...........................................................................................................................2210
20.5.1 Purpose of the Counter-Compare Submodule.................................................................................................... 2210
20.5.2 Controlling and Monitoring the Counter-Compare Submodule............................................................................ 2211
20.5.3 Operational Highlights for the Counter-Compare Submodule............................................................................. 2212
20.5.4 Count Mode Timing Waveforms.......................................................................................................................... 2213
20.6 Action-Qualifier (AQ) Submodule...............................................................................................................................2216
20.6.1 Purpose of the Action-Qualifier Submodule........................................................................................................ 2216
20.6.2 Action-Qualifier Submodule Control and Status Register Definitions..................................................................2217

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20.6.3 Action-Qualifier Event Priority..............................................................................................................................2219

20.6.4 AQCTLA and AQCTLB Shadow Mode Operations............................................................................................. 2220
20.6.5 Configuration Requirements for Common Waveforms........................................................................................ 2222
20.7 Dead-Band Generator (DB) Submodule.................................................................................................................... 2229
20.7.1 Purpose of the Dead-Band Submodule...............................................................................................................2229
20.7.2 Dead-band Submodule Additional Operating Modes.......................................................................................... 2230
20.7.3 Operational Highlights for the Dead-Band Submodule........................................................................................2232
20.8 PWM Chopper (PC) Submodule................................................................................................................................ 2236
20.8.1 Purpose of the PWM Chopper Submodule......................................................................................................... 2236
20.8.2 Operational Highlights for the PWM Chopper Submodule.................................................................................. 2236
20.8.3 Waveforms...........................................................................................................................................................2237
20.9 Trip-Zone (TZ) Submodule.........................................................................................................................................2240
20.9.1 Purpose of the Trip-Zone Submodule..................................................................................................................2240
20.9.2 Operational Highlights for the Trip-Zone Submodule.......................................................................................... 2241
20.9.3 Generating Trip Event Interrupts......................................................................................................................... 2244
20.10 Event-Trigger (ET) Submodule................................................................................................................................ 2246
20.10.1 Operational Overview of the ePWM Event-Trigger Submodule........................................................................ 2247
20.11 Digital Compare (DC) Submodule............................................................................................................................ 2251
20.11.1 Purpose of the Digital Compare Submodule......................................................................................................2253
20.11.2 Enhanced Trip Action Using CMPSS.................................................................................................................2253
20.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis............................................................................ 2253
20.11.4 Operation Highlights of the Digital Compare Submodule.................................................................................. 2254
20.12 ePWM Crossbar (X-BAR)........................................................................................................................................ 2260
20.13 Applications to Power Topologies............................................................................................................................ 2261
20.13.1 Overview of Multiple Modules............................................................................................................................2261
20.13.2 Key Configuration Capabilities.......................................................................................................................... 2262
20.13.3 Controlling Multiple Buck Converters With Independent Frequencies.............................................................. 2263
20.13.4 Controlling Multiple Buck Converters With Same Frequencies......................................................................... 2265
20.13.5 Controlling Multiple Half H-Bridge (HHB) Converters........................................................................................2267
20.13.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)...................................................................... 2269
20.13.7 Practical Applications Using Phase Control Between PWM Modules............................................................... 2271
20.13.8 Controlling a 3-Phase Interleaved DC/DC Converter........................................................................................ 2272
20.13.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter.................................................................. 2275
20.13.10 Controlling a Peak Current Mode Controlled Buck Module............................................................................. 2277
20.13.11 Controlling H-Bridge LLC Resonant Converter................................................................................................2278
20.14 Register Lock Protection.......................................................................................................................................... 2279
20.15 High-Resolution Pulse Width Modulator (HRPWM)................................................................................................. 2280
20.15.1 Operational Description of HRPWM.................................................................................................................. 2282
20.15.2 SFO Library Software - SFO_TI_Build_V8.lib................................................................................................... 2303
20.16 Software................................................................................................................................................................... 2306
20.16.1 EPWM Examples...............................................................................................................................................2306
20.16.2 HRPWM Examples............................................................................................................................................2310
20.17 ePWM Registers...................................................................................................................................................... 2313
20.17.1 EPWM Base Address Table.............................................................................................................................. 2313
20.17.2 EPWM_REGS Registers................................................................................................................................... 2314
20.17.3 Register to Driverlib Function Mapping............................................................................................................. 2437
21 Enhanced Capture (eCAP)............................................................................................................................................. 2449
21.1 Introduction................................................................................................................................................................ 2450
21.1.1 Features.............................................................................................................................................................. 2450
21.1.2 ECAP Related Collateral..................................................................................................................................... 2450
21.2 Description................................................................................................................................................................. 2451
21.3 Configuring Device Pins for the eCAP....................................................................................................................... 2451
21.4 Capture and APWM Operating Mode........................................................................................................................ 2455
21.5 Capture Mode Description......................................................................................................................................... 2457
21.5.1 Event Prescaler................................................................................................................................................... 2458
21.5.2 Edge Polarity Select and Qualifier.......................................................................................................................2458
21.5.3 Continuous/One-Shot Control............................................................................................................................. 2459
21.5.4 32-Bit Counter and Phase Control.......................................................................................................................2460
21.5.5 CAP1-CAP4 Registers........................................................................................................................................ 2460
21.5.6 eCAP Synchronization.........................................................................................................................................2461
21.5.7 Interrupt Control...................................................................................................................................................2462

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21.5.8 DMA Interrupt...................................................................................................................................................... 2464

21.5.9 Shadow Load and Lockout Control..................................................................................................................... 2464
21.5.10 APWM Mode Operation.....................................................................................................................................2464
21.6 Application of the eCAP Module................................................................................................................................ 2466
21.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger.................................................................... 2466
21.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger.................................................2467
21.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger..................................................................2468
21.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger.............................................. 2469
21.7 Application of the APWM Mode................................................................................................................................. 2470
21.7.1 Example 1 - Simple PWM Generation (Independent Channels)......................................................................... 2470
21.8 Software..................................................................................................................................................................... 2471
21.8.1 ECAP Examples.................................................................................................................................................. 2471
21.9 eCAP Registers..........................................................................................................................................................2472
21.9.1 ECAP Base Address Table..................................................................................................................................2472
21.9.2 ECAP_REGS Registers...................................................................................................................................... 2473
21.9.3 ECAP Registers to Driverlib Functions................................................................................................................2491
22 High Resolution Capture (HRCAP)................................................................................................................................2495
22.1 Introduction................................................................................................................................................................ 2496
22.1.1 HRCAP Related Collateral.................................................................................................................................. 2496
22.1.2 Features.............................................................................................................................................................. 2496
22.1.3 Description...........................................................................................................................................................2496
22.2 Operational Details.....................................................................................................................................................2496
22.2.1 HRCAP Clocking................................................................................................................................................. 2498
22.2.2 HRCAP Initialization Sequence........................................................................................................................... 2498
22.2.3 HRCAP Interrupts................................................................................................................................................2498
22.2.4 HRCAP Calibration..............................................................................................................................................2499
22.3 Known Exceptions......................................................................................................................................................2500
22.4 Software..................................................................................................................................................................... 2501
22.4.1 HRCAP Examples............................................................................................................................................... 2501
22.5 HRCAP Registers...................................................................................................................................................... 2501
22.5.1 HRCAP Base Address Table............................................................................................................................... 2501
22.5.2 HRCAP_REGS Registers....................................................................................................................................2502
22.5.3 HRCAP Registers to Driverlib Functions............................................................................................................. 2512
23 Enhanced Quadrature Encoder Pulse (eQEP)............................................................................................................. 2515
23.1 Introduction................................................................................................................................................................ 2516
23.1.1 EQEP Related Collateral..................................................................................................................................... 2518
23.2 Configuring Device Pins.............................................................................................................................................2518
23.3 Description................................................................................................................................................................. 2519
23.3.1 EQEP Inputs........................................................................................................................................................2519
23.3.2 Functional Description......................................................................................................................................... 2522
23.3.3 eQEP Memory Map............................................................................................................................................. 2523
23.4 Quadrature Decoder Unit (QDU)................................................................................................................................2524
23.4.1 Position Counter Input Modes............................................................................................................................. 2524
23.4.2 eQEP Input Polarity Selection............................................................................................................................. 2527
23.4.3 Position-Compare Sync Output........................................................................................................................... 2527
23.5 Position Counter and Control Unit (PCCU)................................................................................................................ 2527
23.5.1 Position Counter Operating Modes..................................................................................................................... 2527
23.5.2 Position Counter Latch........................................................................................................................................ 2530
23.5.3 Position Counter Initialization.............................................................................................................................. 2532
23.5.4 eQEP Position-compare Unit...............................................................................................................................2533
23.6 eQEP Edge Capture Unit........................................................................................................................................... 2535
23.7 eQEP Watchdog.........................................................................................................................................................2539
23.8 eQEP Unit Timer Base............................................................................................................................................... 2539
23.9 QMA Module.............................................................................................................................................................. 2540
23.9.1 Modes of Operation............................................................................................................................................. 2541
23.9.2 Interrupt and Error Generation............................................................................................................................ 2542
23.10 eQEP Interrupt Structure..........................................................................................................................................2543
23.11 Software................................................................................................................................................................... 2544
23.11.1 EQEP Examples................................................................................................................................................ 2544
23.12 eQEP Registers....................................................................................................................................................... 2547
23.12.1 EQEP Base Address Table................................................................................................................................2547

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23.12.2 EQEP_REGS Registers.................................................................................................................................... 2548

23.12.3 EQEP Registers to Driverlib Functions..............................................................................................................2584
24 Serial Peripheral Interface (SPI).................................................................................................................................... 2587
24.1 Introduction................................................................................................................................................................ 2588
24.1.1 Features.............................................................................................................................................................. 2588
24.1.2 SPI Related Collateral......................................................................................................................................... 2588
24.1.3 Block Diagram..................................................................................................................................................... 2589
24.2 System-Level Integration........................................................................................................................................... 2590
24.2.1 SPI Module Signals............................................................................................................................................. 2590
24.2.2 Configuring Device Pins...................................................................................................................................... 2591
24.2.3 SPI Interrupts.......................................................................................................................................................2591
24.2.4 DMA Support....................................................................................................................................................... 2593
24.3 SPI Operation.............................................................................................................................................................2594
24.3.1 Introduction to Operation..................................................................................................................................... 2594
24.3.2 Master Mode........................................................................................................................................................2595
24.3.3 Slave Mode..........................................................................................................................................................2596
24.3.4 Data Format.........................................................................................................................................................2598
24.3.5 Baud Rate Selection............................................................................................................................................2599
24.3.6 SPI Clocking Schemes........................................................................................................................................ 2600
24.3.7 SPI FIFO Description...........................................................................................................................................2601
24.3.8 SPI DMA Transfers..............................................................................................................................................2602
24.4 Programming Procedure............................................................................................................................................ 2603
24.4.1 Initialization Upon Reset......................................................................................................................................2603
24.4.2 Configuring the SPI............................................................................................................................................. 2603
24.4.3 Data Transfer Example........................................................................................................................................2604
24.5 Software..................................................................................................................................................................... 2605
24.5.1 SPI Examples...................................................................................................................................................... 2605
24.6 SPI Registers............................................................................................................................................................. 2607
24.6.1 SPI Base Address Table......................................................................................................................................2607
24.6.2 SPI_REGS Registers.......................................................................................................................................... 2608
24.6.3 SPI Registers to Driverlib Functions....................................................................................................................2626
25 Serial Communications Interface (SCI)........................................................................................................................ 2629
25.1 Introduction................................................................................................................................................................ 2630
25.1.1 Features.............................................................................................................................................................. 2630
25.1.2 SCI Related Collateral......................................................................................................................................... 2631
25.1.3 Block Diagram..................................................................................................................................................... 2631
25.2 Architecture................................................................................................................................................................ 2631
25.3 SCI Module Signal Summary..................................................................................................................................... 2631
25.4 Configuring Device Pins.............................................................................................................................................2633
25.5 Multiprocessor and Asynchronous Communication Modes....................................................................................... 2633
25.6 SCI Programmable Data Format................................................................................................................................2634
25.7 SCI Multiprocessor Communication...........................................................................................................................2635
25.7.1 Recognizing the Address Byte............................................................................................................................ 2635
25.7.2 Controlling the SCI TX and RX Features.............................................................................................................2635
25.7.3 Receipt Sequence............................................................................................................................................... 2635
25.8 Idle-Line Multiprocessor Mode................................................................................................................................... 2636
25.8.1 Idle-Line Mode Steps...........................................................................................................................................2636
25.8.2 Block Start Signal................................................................................................................................................ 2636
25.8.3 Wake-Up Temporary (WUT) Flag........................................................................................................................ 2637
25.8.4 Receiver Operation..............................................................................................................................................2637
25.9 Address-Bit Multiprocessor Mode.............................................................................................................................. 2638
25.9.1 Sending an Address............................................................................................................................................ 2638
25.10 SCI Communication Format.....................................................................................................................................2639
25.10.1 Receiver Signals in Communication Modes...................................................................................................... 2639
25.10.2 Transmitter Signals in Communication Modes.................................................................................................. 2640
25.11 SCI Port Interrupts....................................................................................................................................................2641
25.12 SCI Baud Rate Calculations.....................................................................................................................................2641
25.13 SCI Enhanced Features...........................................................................................................................................2642
25.13.1 SCI FIFO Description........................................................................................................................................ 2642
25.13.2 SCI Auto-Baud...................................................................................................................................................2644
25.13.3 Autobaud-Detect Sequence.............................................................................................................................. 2644

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25.14 Software................................................................................................................................................................... 2645

25.14.1 SCI Examples....................................................................................................................................................2645
25.15 SCI Registers........................................................................................................................................................... 2646
25.15.1 SCI Base Address Table....................................................................................................................................2647
25.15.2 SCI_REGS Registers........................................................................................................................................ 2648
25.15.3 SCI Registers to Driverlib Functions..................................................................................................................2667
26 Inter-Integrated Circuit Module (I2C).............................................................................................................................2671
26.1 Introduction................................................................................................................................................................ 2672
26.1.1 I2C Related Collateral......................................................................................................................................... 2672
26.1.2 Features.............................................................................................................................................................. 2673
26.1.3 Features Not Supported...................................................................................................................................... 2673
26.1.4 Functional Overview............................................................................................................................................ 2674
26.1.5 Clock Generation.................................................................................................................................................2675
26.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)....................................................................................... 2676
26.2 Configuring Device Pins.............................................................................................................................................2677
26.3 I2C Module Operational Details................................................................................................................................. 2677
26.3.1 Input and Output Voltage Levels......................................................................................................................... 2677
26.3.2 Data Validity.........................................................................................................................................................2677
26.3.3 Operating Modes................................................................................................................................................. 2677
26.3.4 I2C Module START and STOP Conditions.......................................................................................................... 2681
26.3.5 Non-repeat Mode versus Repeat Mode.............................................................................................................. 2682
26.3.6 Serial Data Formats.............................................................................................................................................2682
26.3.7 Clock Synchronization......................................................................................................................................... 2685
26.3.8 Arbitration............................................................................................................................................................ 2686
26.3.9 Digital Loopback Mode........................................................................................................................................ 2687
26.3.10 NACK Bit Generation.........................................................................................................................................2688
26.4 Interrupt Requests Generated by the I2C Module..................................................................................................... 2689
26.4.1 Basic I2C Interrupt Requests...............................................................................................................................2689
26.4.2 I2C FIFO Interrupts..............................................................................................................................................2692
26.5 Resetting or Disabling the I2C Module.......................................................................................................................2692
26.6 Software..................................................................................................................................................................... 2693
26.6.1 I2C Examples...................................................................................................................................................... 2693
26.7 I2C Registers............................................................................................................................................................. 2696
26.7.1 I2C Base Address Table...................................................................................................................................... 2696
26.7.2 I2C_REGS Registers...........................................................................................................................................2697
26.7.3 I2C Registers to Driverlib Functions.................................................................................................................... 2720
27 Power Management Bus Module (PMBus)................................................................................................................... 2723
27.1 Introduction................................................................................................................................................................ 2724
27.1.1 PMBUS Related Collateral.................................................................................................................................. 2724
27.1.2 Features.............................................................................................................................................................. 2724
27.1.3 Block Diagram..................................................................................................................................................... 2725
27.2 Configuring Device Pins.............................................................................................................................................2725
27.3 Slave Mode Operation............................................................................................................................................... 2726
27.3.1 Configuration....................................................................................................................................................... 2726
27.3.2 Message Handling...............................................................................................................................................2726
27.4 Master Mode Operation............................................................................................................................................. 2736
27.4.1 Configuration....................................................................................................................................................... 2736
27.4.2 Message Handling...............................................................................................................................................2736
27.5 PMBus Registers....................................................................................................................................................... 2746
27.5.1 PMBUS Base Address Table...............................................................................................................................2746
27.5.2 PMBUS_REGS Registers................................................................................................................................... 2747
27.5.3 PMBUS Registers to Driverlib Functions.............................................................................................................2766
28 Controller Area Network (CAN)..................................................................................................................................... 2769
28.1 Introduction................................................................................................................................................................ 2770
28.1.1 DCAN Related Collateral.....................................................................................................................................2770
28.1.2 Features.............................................................................................................................................................. 2770
28.1.3 Block Diagram..................................................................................................................................................... 2771
28.2 Functional Description................................................................................................................................................2772
28.2.1 Configuring Device Pins...................................................................................................................................... 2772
28.2.2 Address/Data Bus Bridge.................................................................................................................................... 2773
28.3 Operating Modes........................................................................................................................................................2774

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28.3.1 Initialization..........................................................................................................................................................2774
28.3.2 CAN Message Transfer (Normal Operation)....................................................................................................... 2775
28.3.3 Test Modes.......................................................................................................................................................... 2776
28.4 Multiple Clock Source................................................................................................................................................ 2780
28.5 Interrupt Functionality.................................................................................................................................................2781
28.5.1 Message Object Interrupts.................................................................................................................................. 2781
28.5.2 Status Change Interrupts.....................................................................................................................................2781
28.5.3 Error Interrupts.................................................................................................................................................... 2781
28.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts.............................................. 2781
28.5.5 Interrupt Topologies............................................................................................................................................. 2782
28.6 DMA Functionality...................................................................................................................................................... 2783
28.7 Parity Check Mechanism........................................................................................................................................... 2783
28.7.1 Behavior on Parity Error...................................................................................................................................... 2783
28.8 Debug Mode...............................................................................................................................................................2784
28.9 Module Initialization....................................................................................................................................................2784
28.10 Configuration of Message Objects........................................................................................................................... 2785
28.10.1 Configuration of a Transmit Object for Data Frames......................................................................................... 2785
28.10.2 Configuration of a Transmit Object for Remote Frames.................................................................................... 2785
28.10.3 Configuration of a Single Receive Object for Data Frames...............................................................................2785
28.10.4 Configuration of a Single Receive Object for Remote Frames..........................................................................2786
28.10.5 Configuration of a FIFO Buffer...........................................................................................................................2786
28.11 Message Handling....................................................................................................................................................2786
28.11.1 Message Handler Overview...............................................................................................................................2787
28.11.2 Receive/Transmit Priority...................................................................................................................................2787
28.11.3 Transmission of Messages in Event Driven CAN Communication.................................................................... 2787
28.11.4 Updating a Transmit Object............................................................................................................................... 2788
28.11.5 Changing a Transmit Object.............................................................................................................................. 2788
28.11.6 Acceptance Filtering of Received Messages..................................................................................................... 2789
28.11.7 Reception of Data Frames................................................................................................................................. 2789
28.11.8 Reception of Remote Frames............................................................................................................................ 2789
28.11.9 Reading Received Messages............................................................................................................................ 2789
28.11.10 Requesting New Data for a Receive Object.................................................................................................... 2790
28.11.11 Storing Received Messages in FIFO Buffers................................................................................................... 2790
28.11.12 Reading from a FIFO Buffer.............................................................................................................................2790
28.12 CAN Bit Timing.........................................................................................................................................................2792
28.12.1 Bit Time and Bit Rate.........................................................................................................................................2792
28.12.2 Configuration of the CAN Bit Timing..................................................................................................................2797
28.13 Message Interface Register Sets............................................................................................................................. 2801
28.13.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)....................................................................................2801
28.13.2 Message Interface Register Set 3 (IF3).............................................................................................................2802
28.14 Message RAM..........................................................................................................................................................2803
28.14.1 Structure of Message Objects........................................................................................................................... 2803
28.14.2 Addressing Message Objects in RAM............................................................................................................... 2806
28.14.3 Message RAM Representation in Debug Mode................................................................................................ 2807
28.15 Software................................................................................................................................................................... 2808
28.15.1 CAN Examples.................................................................................................................................................. 2808
28.16 CAN Registers..........................................................................................................................................................2811
28.16.1 CAN Base Address Table.................................................................................................................................. 2811
28.16.2 CAN_REGS Registers.......................................................................................................................................2812
28.16.3 CAN Registers to Driverlib Functions................................................................................................................ 2868
29 Modular Controller Area Network (MCAN)................................................................................................................... 2873
29.1 MCAN Introduction.....................................................................................................................................................2874
29.1.1 MCAN Related Collateral.................................................................................................................................... 2874
29.1.2 MCAN Features...................................................................................................................................................2875
29.2 MCAN Environment................................................................................................................................................... 2875
29.3 CAN Network Basics..................................................................................................................................................2876
29.4 MCAN Integration.......................................................................................................................................................2877
29.5 MCAN Functional Description.................................................................................................................................... 2879
29.5.1 Module Clocking Requirements...........................................................................................................................2880
29.5.2 Interrupt Requests............................................................................................................................................... 2880
29.5.3 Operating Modes................................................................................................................................................. 2881

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29.5.4 Transmitter Delay Compensation........................................................................................................................ 2884

29.5.5 Restricted Operation Mode..................................................................................................................................2886
29.5.6 Bus Monitoring Mode...........................................................................................................................................2887
29.5.7 Disabled Automatic Retransmission (DAR) Mode...............................................................................................2888
29.5.8 Clock Stop Mode................................................................................................................................................. 2888
29.5.9 Test Modes.......................................................................................................................................................... 2892
29.5.10 Timestamp Generation...................................................................................................................................... 2893
29.5.11 Timeout Counter................................................................................................................................................ 2894
29.5.12 Safety................................................................................................................................................................ 2895
29.5.13 Rx Handling....................................................................................................................................................... 2897
29.5.14 Tx Handling....................................................................................................................................................... 2903
29.5.15 FIFO Acknowledge Handling.............................................................................................................................2907
29.5.16 Message RAM................................................................................................................................................... 2907
29.6 Software..................................................................................................................................................................... 2918
29.6.1 MCAN Examples................................................................................................................................................. 2918
29.7 MCAN Registers........................................................................................................................................................ 2921
29.7.1 MCAN Base Address Table................................................................................................................................. 2921
29.7.2 MCANSS_REGS Registers.................................................................................................................................2922
29.7.3 MCAN_REGS Registers......................................................................................................................................2935
29.7.4 MCAN_ERROR_REGS Registers.......................................................................................................................3012
29.7.5 MCAN Registers to Driverlib Functions............................................................................................................... 3037
30 Local Interconnect Network (LIN)..................................................................................................................................3043
30.1 Introduction................................................................................................................................................................ 3044
30.1.1 SCI Features....................................................................................................................................................... 3044
30.1.2 LIN Features........................................................................................................................................................3045
30.1.3 LIN Related Collateral......................................................................................................................................... 3045
30.1.4 Block Diagram..................................................................................................................................................... 3046
30.2 Serial Communications Interface Module.................................................................................................................. 3049
30.2.1 SCI Communication Formats.............................................................................................................................. 3049
30.2.2 SCI Interrupts...................................................................................................................................................... 3059
30.2.3 SCI DMA Interface...............................................................................................................................................3063
30.2.4 SCI Configurations.............................................................................................................................................. 3064
30.2.5 SCI Low-Power Mode..........................................................................................................................................3066
30.3 Local Interconnect Network Module...........................................................................................................................3067
30.3.1 LIN Communication Formats...............................................................................................................................3067
30.3.2 LIN Interrupts.......................................................................................................................................................3086
30.3.3 Servicing LIN Interrupts....................................................................................................................................... 3086
30.3.4 LIN DMA Interface............................................................................................................................................... 3087
30.3.5 LIN Configurations...............................................................................................................................................3087
30.4 Low-Power Mode....................................................................................................................................................... 3089
30.4.1 Entering Sleep Mode........................................................................................................................................... 3090
30.4.2 Wakeup................................................................................................................................................................3090
30.4.3 Wakeup Timeouts................................................................................................................................................ 3091
30.5 Emulation Mode......................................................................................................................................................... 3091
30.6 Software..................................................................................................................................................................... 3092
30.6.1 LIN Examples...................................................................................................................................................... 3092
30.7 SCI/LIN Registers...................................................................................................................................................... 3094
30.7.1 LIN Base Address Table...................................................................................................................................... 3094
30.7.2 LIN_REGS Registers...........................................................................................................................................3095
30.7.3 LIN Registers to Driverlib Functions.................................................................................................................... 3149
31 Fast Serial Interface (FSI)...............................................................................................................................................3155
31.1 Introduction................................................................................................................................................................ 3156
31.1.1 FSI Related Collateral......................................................................................................................................... 3156
31.1.2 FSI Features........................................................................................................................................................3156
31.2 System-level Integration.............................................................................................................................................3157
31.2.1 CPU Interface...................................................................................................................................................... 3157
31.2.2 Signal Description................................................................................................................................................3159
31.2.3 FSI Interrupts.......................................................................................................................................................3160
31.2.4 CLA Task Triggering............................................................................................................................................ 3162
31.2.5 DMA Interface......................................................................................................................................................3162
31.2.6 External Frame Trigger Mux................................................................................................................................ 3162

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31.3 FSI Functional Description......................................................................................................................................... 3164

31.3.1 FSI Functional Description.................................................................................................................................. 3164
31.3.2 FSI Transmitter Module....................................................................................................................................... 3165
31.3.3 FSI Receiver Module........................................................................................................................................... 3171
31.3.4 Frame Format......................................................................................................................................................3177
31.3.5 Flush Sequence...................................................................................................................................................3181
31.3.6 Internal Loopback................................................................................................................................................ 3181
31.3.7 CRC Generation.................................................................................................................................................. 3182
31.3.8 ECC Module........................................................................................................................................................ 3182
31.3.9 Tag Matching....................................................................................................................................................... 3183
31.3.10 User Data Filtering (UDATA Matching).............................................................................................................. 3183
31.3.11 TDM Configurations........................................................................................................................................... 3183
31.3.12 FSI Trigger Generation...................................................................................................................................... 3186
31.3.13 FSI-SPI Compatibility Mode.............................................................................................................................. 3188
31.4 FSI Programing Guide............................................................................................................................................... 3192
31.4.1 Establishing the Communication Link..................................................................................................................3192
31.4.2 Register Protection.............................................................................................................................................. 3194
31.4.3 Emulation Mode...................................................................................................................................................3194
31.5 Software..................................................................................................................................................................... 3195
31.5.1 FSI Examples...................................................................................................................................................... 3195
31.6 FSI Registers............................................................................................................................................................. 3203
31.6.1 FSI Base Address Table...................................................................................................................................... 3203
31.6.2 FSI_TX_REGS Registers.................................................................................................................................... 3204
31.6.3 FSI_RX_REGS Registers....................................................................................................................................3231
31.6.4 FSI Registers to Driverlib Functions.................................................................................................................... 3278
32 Configurable Logic Block (CLB)....................................................................................................................................3283
32.1 Introduction................................................................................................................................................................ 3284
32.1.1 CLB Related Collateral........................................................................................................................................ 3284
32.2 Description................................................................................................................................................................. 3284
32.2.1 CLB Clock............................................................................................................................................................3286
32.3 CLB Input/Output Connection.................................................................................................................................... 3287
32.3.1 Overview..............................................................................................................................................................3287
32.3.2 CLB Input Selection.............................................................................................................................................3287
32.3.3 CLB Output Selection.......................................................................................................................................... 3295
32.3.4 CLB Output Signal Multiplexer............................................................................................................................ 3297
32.4 CLB Tile......................................................................................................................................................................3299
32.4.1 Static Switch Block.............................................................................................................................................. 3299
32.4.2 Counter Block...................................................................................................................................................... 3302
32.4.3 FSM Block........................................................................................................................................................... 3306
32.4.4 LUT4 Block.......................................................................................................................................................... 3307
32.4.5 Output LUT Block................................................................................................................................................ 3308
32.4.6 Asynchronous Output Conditioning (AOC) Block................................................................................................ 3308
32.4.7 High Level Controller (HLC).................................................................................................................................3311
32.5 CPU Interface.............................................................................................................................................................3315
32.5.1 Register Description............................................................................................................................................ 3315
32.5.2 Non-Memory Mapped Registers..........................................................................................................................3316
32.6 DMA Access...............................................................................................................................................................3316
32.7 CLB Data Export Through SPI RX Buffer...................................................................................................................3317
32.8 Software..................................................................................................................................................................... 3318
32.8.1 CLB Examples.....................................................................................................................................................3318
32.9 CLB Registers............................................................................................................................................................ 3323
32.9.1 CLB Base Address Table.....................................................................................................................................3323
32.9.2 CLB_LOGIC_CONFIG_REGS Registers............................................................................................................ 3324
32.9.3 CLB_LOGIC_CONTROL_REGS Registers........................................................................................................ 3376
32.9.4 CLB_DATA_EXCHANGE_REGS Registers........................................................................................................ 3408
32.9.5 CLB Registers to Driverlib Functions...................................................................................................................3410
33 Advanced Encryption Standard (AES) Accelerator.....................................................................................................3415
33.1 Introduction................................................................................................................................................................ 3416
33.1.1 AES Block Diagram............................................................................................................................................. 3416
33.1.2 AES Algorithm..................................................................................................................................................... 3419
33.2 AES Operating Modes............................................................................................................................................... 3420

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33.2.1 GCM Operation................................................................................................................................................... 3420

33.2.2 CCM Operation....................................................................................................................................................3421
33.2.3 XTS Operation.....................................................................................................................................................3422
33.2.4 ECB Feedback Mode.......................................................................................................................................... 3423
33.2.5 CBC Feedback Mode.......................................................................................................................................... 3424
33.2.6 CTR and ICM Feedback Modes.......................................................................................................................... 3425
33.2.7 CFB Mode........................................................................................................................................................... 3426
33.2.8 F8 Mode.............................................................................................................................................................. 3427
33.2.9 F9 Operation........................................................................................................................................................3428
33.2.10 CBC-MAC Operation......................................................................................................................................... 3429
33.3 Extended and Combined Modes of Operations......................................................................................................... 3430
33.3.1 GCM Protocol Operation..................................................................................................................................... 3430
33.3.2 CCM Protocol Operation..................................................................................................................................... 3430
33.3.3 Hardware Requests.............................................................................................................................................3430
33.4 AES Module Programming Guide.............................................................................................................................. 3431
33.4.1 AES Low-Level Programming Models.................................................................................................................3431
33.5 Software..................................................................................................................................................................... 3436
33.5.1 AES Examples.....................................................................................................................................................3436
33.6 AES Registers............................................................................................................................................................3437
33.6.1 AES Base Address Table.................................................................................................................................... 3437
33.6.2 AES_REGS Registers......................................................................................................................................... 3438
33.6.3 AES_SS_REGS Registers.................................................................................................................................. 3482
33.6.4 Register to Driverlib Function Mapping............................................................................................................... 3485
34 Embedded Pattern Generator (EPG).............................................................................................................................3489
34.1 Introduction................................................................................................................................................................ 3490
34.1.1 EPG Related Collateral....................................................................................................................................... 3490
34.1.2 Features.............................................................................................................................................................. 3490
34.1.3 EPG Block Diagram.............................................................................................................................................3491
34.2 Clock Generator Modules.......................................................................................................................................... 3493
34.2.1 DCLK (50% duty cycle clock).............................................................................................................................. 3493
34.2.2 Clock Stop........................................................................................................................................................... 3494
34.3 Signal Generator Module........................................................................................................................................... 3495
34.4 EPG Peripheral Signal Mux Selection........................................................................................................................3498
34.5 EPG Example Use Cases.......................................................................................................................................... 3500
34.5.1 EPG Example: Synchronous Clocks with Offset................................................................................................. 3500
34.5.2 EPG Example: Serial Data Bit Stream (LSB first)............................................................................................... 3501
34.5.3 EPG Example: Serial Data Bit Stream (MSB first).............................................................................................. 3502
34.6 EPG Interrupt............................................................................................................................................................. 3503
34.7 Software..................................................................................................................................................................... 3504
34.7.1 EPG Examples.................................................................................................................................................... 3504
34.8 EPG Registers........................................................................................................................................................... 3505
34.8.1 EPG Base Address Table.................................................................................................................................... 3505
34.8.2 EPG_REGS Registers.........................................................................................................................................3506
34.8.3 EPG_MUX_REGS Registers...............................................................................................................................3532
34.8.4 EPG Registers to Driverlib Functions.................................................................................................................. 3537
35 Revision History............................................................................................................................................................. 3539

List of Figures
Figure 3-1. Device Interrupt Architecture.................................................................................................................................102
Figure 3-2. Interrupt Propagation Path.................................................................................................................................... 103
Figure 3-3. Clocking System.................................................................................................................................................... 116
Figure 3-4. System PLL........................................................................................................................................................... 117
Figure 3-5. AUXCLKIN.............................................................................................................................................................118
Figure 3-6. Single-ended 3.3V External Clock......................................................................................................................... 119
Figure 3-7. External Crystal..................................................................................................................................................... 119
Figure 3-8. External Resonator................................................................................................................................................120
Figure 3-9. Missing Clock Detection Logic.............................................................................................................................. 126
Figure 3-10. CPU Timers......................................................................................................................................................... 128
Figure 3-11. CPU Timer Interrupt Signals and Output Signal.................................................................................................. 128
Figure 3-12. Watchdog Timer Module......................................................................................................................................129
Figure 3-13. Memory Architecture........................................................................................................................................... 135

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Figure 3-14. Arbitration Scheme on Global Shared Memories................................................................................................ 137

Figure 3-15. Arbitration Scheme on Local Shared Memories..................................................................................................137
Figure 3-16. Simplified LFU Representation............................................................................................................................143
Figure 3-17. PIE Vector Table Swap........................................................................................................................................144
Figure 3-18. LS0/LS1 RAM Memory Swap..............................................................................................................................145
Figure 3-19. NMAVFLG Register............................................................................................................................................. 158
Figure 3-20. NMAVSET Register............................................................................................................................................. 160
Figure 3-21. NMAVCLR Register.............................................................................................................................................162
Figure 3-22. NMAVINTEN Register......................................................................................................................................... 164
Figure 3-23. NMCPURDAVADDR Register............................................................................................................................. 166
Figure 3-24. NMCPUWRAVADDR Register............................................................................................................................ 167
Figure 3-25. NMCPUFAVADDR Register................................................................................................................................ 168
Figure 3-26. NMDMAWRAVADDR Register............................................................................................................................ 169
Figure 3-27. NMCLA1RDAVADDR Register............................................................................................................................170
Figure 3-28. NMCLA1WRAVADDR Register........................................................................................................................... 171
Figure 3-29. NMCLA1FAVADDR Register............................................................................................................................... 172
Figure 3-30. NMDMARDAVADDR Register.............................................................................................................................173
Figure 3-31. MAVFLG Register................................................................................................................................................174
Figure 3-32. MAVSET Register................................................................................................................................................175
Figure 3-33. MAVCLR Register............................................................................................................................................... 176
Figure 3-34. MAVINTEN Register............................................................................................................................................177
Figure 3-35. MCPUFAVADDR Register................................................................................................................................... 178
Figure 3-36. MCPUWRAVADDR Register............................................................................................................................... 179
Figure 3-37. MDMAWRAVADDR Register...............................................................................................................................180
Figure 3-38. MHICWRAVADDR_y Register.............................................................................................................................181
Figure 3-39. NMHICRDAVADDR Register...............................................................................................................................182
Figure 3-40. NMHICWRAVADDR Register..............................................................................................................................183
Figure 3-41. CLKCFGLOCK1 Register....................................................................................................................................186
Figure 3-42. CLKSRCCTL1 Register.......................................................................................................................................188
Figure 3-43. CLKSRCCTL2 Register.......................................................................................................................................190
Figure 3-44. CLKSRCCTL3 Register.......................................................................................................................................191
Figure 3-45. SYSPLLCTL1 Register........................................................................................................................................192
Figure 3-46. SYSPLLMULT Register....................................................................................................................................... 193
Figure 3-47. SYSPLLSTS Register......................................................................................................................................... 194
Figure 3-48. SYSCLKDIVSEL Register................................................................................................................................... 195
Figure 3-49. AUXCLKDIVSEL Register...................................................................................................................................196
Figure 3-50. XCLKOUTDIVSEL Register................................................................................................................................ 197
Figure 3-51. LOSPCP Register............................................................................................................................................... 198
Figure 3-52. MCDCR Register.................................................................................................................................................199
Figure 3-53. X1CNT Register.................................................................................................................................................. 201
Figure 3-54. XTALCR Register................................................................................................................................................ 202
Figure 3-55. XTALCR2 Register.............................................................................................................................................. 203
Figure 3-56. CLKFAILCFG Register........................................................................................................................................ 204
Figure 3-57. CPUSYSLOCK1 Register................................................................................................................................... 207
Figure 3-58. CPUSYSLOCK2 Register................................................................................................................................... 210
Figure 3-59. PIEVERRADDR Register.................................................................................................................................... 211
Figure 3-60. PCLKCR0 Register............................................................................................................................................. 212
Figure 3-61. PCLKCR2 Register............................................................................................................................................. 214
Figure 3-62. PCLKCR3 Register............................................................................................................................................. 216
Figure 3-63. PCLKCR4 Register............................................................................................................................................. 217
Figure 3-64. PCLKCR6 Register............................................................................................................................................. 218
Figure 3-65. PCLKCR7 Register............................................................................................................................................. 219
Figure 3-66. PCLKCR8 Register............................................................................................................................................. 220
Figure 3-67. PCLKCR9 Register............................................................................................................................................. 221
Figure 3-68. PCLKCR10 Register........................................................................................................................................... 222
Figure 3-69. PCLKCR13 Register........................................................................................................................................... 223
Figure 3-70. PCLKCR14 Register........................................................................................................................................... 224
Figure 3-71. PCLKCR16 Register........................................................................................................................................... 225
Figure 3-72. PCLKCR17 Register........................................................................................................................................... 226
Figure 3-73. PCLKCR18 Register........................................................................................................................................... 227
Figure 3-74. PCLKCR19 Register........................................................................................................................................... 228

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Figure 3-75. PCLKCR20 Register........................................................................................................................................... 229

Figure 3-76. PCLKCR21 Register........................................................................................................................................... 230
Figure 3-77. PCLKCR25 Register........................................................................................................................................... 231
Figure 3-78. PCLKCR26 Register........................................................................................................................................... 232
Figure 3-79. PCLKCR27 Register........................................................................................................................................... 233
Figure 3-80. SIMRESET Register............................................................................................................................................234
Figure 3-81. LPMCR Register................................................................................................................................................. 235
Figure 3-82. GPIOLPMSEL0 Register.....................................................................................................................................236
Figure 3-83. GPIOLPMSEL1 Register.....................................................................................................................................239
Figure 3-84. TMR2CLKCTL Register...................................................................................................................................... 242
Figure 3-85. RESCCLR Register.............................................................................................................................................243
Figure 3-86. RESC Register.................................................................................................................................................... 245
Figure 3-87. MCANWAKESTATUS Register........................................................................................................................... 247
Figure 3-88. MCANWAKESTATUSCLR Register.................................................................................................................... 248
Figure 3-89. CLKSTOPREQ Register......................................................................................................................................249
Figure 3-90. CLKSTOPACK Register...................................................................................................................................... 250
Figure 3-91. TIM Register........................................................................................................................................................252
Figure 3-92. PRD Register...................................................................................................................................................... 253
Figure 3-93. TCR Register.......................................................................................................................................................254
Figure 3-94. TPR Register.......................................................................................................................................................256
Figure 3-95. TPRH Register.................................................................................................................................................... 257
Figure 3-96. PARTIDL Register............................................................................................................................................... 260
Figure 3-97. PARTIDH Register...............................................................................................................................................261
Figure 3-98. REVID Register................................................................................................................................................... 262
Figure 3-99. FUSEERR Register.............................................................................................................................................263
Figure 3-100. SOFTPRES0 Register.......................................................................................................................................264
Figure 3-101. SOFTPRES2 Register.......................................................................................................................................265
Figure 3-102. SOFTPRES3 Register.......................................................................................................................................267
Figure 3-103. SOFTPRES4 Register.......................................................................................................................................268
Figure 3-104. SOFTPRES6 Register.......................................................................................................................................269
Figure 3-105. SOFTPRES7 Register.......................................................................................................................................270
Figure 3-106. SOFTPRES8 Register.......................................................................................................................................271
Figure 3-107. SOFTPRES9 Register.......................................................................................................................................272
Figure 3-108. SOFTPRES10 Register.....................................................................................................................................273
Figure 3-109. SOFTPRES13 Register.....................................................................................................................................274
Figure 3-110. SOFTPRES14 Register..................................................................................................................................... 275
Figure 3-111. SOFTPRES16 Register..................................................................................................................................... 276
Figure 3-112. SOFTPRES17 Register..................................................................................................................................... 277
Figure 3-113. SOFTPRES18 Register..................................................................................................................................... 278
Figure 3-114. SOFTPRES19 Register..................................................................................................................................... 279
Figure 3-115. SOFTPRES20 Register..................................................................................................................................... 280
Figure 3-116. SOFTPRES21 Register..................................................................................................................................... 281
Figure 3-117. SOFTPRES25 Register..................................................................................................................................... 282
Figure 3-118. SOFTPRES26 Register..................................................................................................................................... 283
Figure 3-119. SOFTPRES27 Register..................................................................................................................................... 284
Figure 3-120. TAP_STATUS Register......................................................................................................................................285
Figure 3-121. ECAPTYPE Register.........................................................................................................................................286
Figure 3-122. SDFMTYPE Register........................................................................................................................................ 287
Figure 3-123. CLA1TASKSRCSELLOCK Register..................................................................................................................289
Figure 3-124. DMACHSRCSELLOCK Register.......................................................................................................................290
Figure 3-125. CLA1TASKSRCSEL1 Register..........................................................................................................................291
Figure 3-126. CLA1TASKSRCSEL2 Register..........................................................................................................................292
Figure 3-127. DMACHSRCSEL1 Register.............................................................................................................................. 293
Figure 3-128. DMACHSRCSEL2 Register.............................................................................................................................. 294
Figure 3-129. DxLOCK Register..............................................................................................................................................297
Figure 3-130. DxCOMMIT Register......................................................................................................................................... 298
Figure 3-131. DxACCPROT0 Register.................................................................................................................................... 299
Figure 3-132. DxTEST Register.............................................................................................................................................. 300
Figure 3-133. DxINIT Register.................................................................................................................................................301
Figure 3-134. DxINITDONE Register...................................................................................................................................... 302
Figure 3-135. DxRAMTEST_LOCK Register...........................................................................................................................303

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Figure 3-136. LSxLOCK Register............................................................................................................................................ 304

Figure 3-137. LSxCOMMIT Register....................................................................................................................................... 306
Figure 3-138. LSxMSEL Register............................................................................................................................................ 308
Figure 3-139. LSxCLAPGM Register.......................................................................................................................................310
Figure 3-140. LSxACCPROT0 Register.................................................................................................................................. 312
Figure 3-141. LSxACCPROT1 Register.................................................................................................................................. 314
Figure 3-142. LSxTEST Register.............................................................................................................................................316
Figure 3-143. LSxINIT Register............................................................................................................................................... 318
Figure 3-144. LSxINITDONE Register.....................................................................................................................................320
Figure 3-145. LSxRAMTEST_LOCK Register.........................................................................................................................322
Figure 3-146. GSxLOCK Register........................................................................................................................................... 323
Figure 3-147. GSxCOMMIT Register...................................................................................................................................... 325
Figure 3-148. GSxACCPROT0 Register................................................................................................................................. 327
Figure 3-149. GSxTEST Register............................................................................................................................................329
Figure 3-150. GSxINIT Register.............................................................................................................................................. 331
Figure 3-151. GSxINITDONE Register....................................................................................................................................333
Figure 3-152. GSxRAMTEST_LOCK Register........................................................................................................................ 335
Figure 3-153. MSGxLOCK Register........................................................................................................................................ 336
Figure 3-154. MSGxCOMMIT Register................................................................................................................................... 337
Figure 3-155. MSGxTEST Register.........................................................................................................................................339
Figure 3-156. MSGxINIT Register........................................................................................................................................... 341
Figure 3-157. MSGxINITDONE Register.................................................................................................................................342
Figure 3-158. MSGxRAMTEST_LOCK Register..................................................................................................................... 343
Figure 3-159. ROM_LOCK Register........................................................................................................................................344
Figure 3-160. ROM_TEST Register........................................................................................................................................ 345
Figure 3-161. ROM_FORCE_ERROR Register...................................................................................................................... 346
Figure 3-162. UCERRFLG Register........................................................................................................................................ 349
Figure 3-163. UCERRSET Register........................................................................................................................................ 350
Figure 3-164. UCERRCLR Register........................................................................................................................................ 351
Figure 3-165. UCCPUREADDR Register................................................................................................................................ 352
Figure 3-166. UCDMAREADDR Register................................................................................................................................353
Figure 3-167. UCCLA1READDR Register...............................................................................................................................354
Figure 3-168. UCHICAREADDR Register............................................................................................................................... 355
Figure 3-169. CERRFLG Register...........................................................................................................................................356
Figure 3-170. CERRSET Register...........................................................................................................................................357
Figure 3-171. CERRCLR Register...........................................................................................................................................358
Figure 3-172. CCPUREADDR Register...................................................................................................................................359
Figure 3-173. CDMAREADDR Register.................................................................................................................................. 360
Figure 3-174. CCLA1READDR Register................................................................................................................................. 361
Figure 3-175. CERRCNT Register.......................................................................................................................................... 362
Figure 3-176. CERRTHRES Register......................................................................................................................................363
Figure 3-177. CEINTFLG Register.......................................................................................................................................... 364
Figure 3-178. CEINTCLR Register.......................................................................................................................................... 365
Figure 3-179. CEINTSET Register.......................................................................................................................................... 366
Figure 3-180. CEINTEN Register............................................................................................................................................ 367
Figure 3-181. CHICREADDR Register.................................................................................................................................... 368
Figure 3-182. NMICFG Register..............................................................................................................................................370
Figure 3-183. NMIFLG Register.............................................................................................................................................. 371
Figure 3-184. NMIFLGCLR Register....................................................................................................................................... 373
Figure 3-185. NMIFLGFRC Register....................................................................................................................................... 375
Figure 3-186. NMIWDCNT Register........................................................................................................................................ 377
Figure 3-187. NMIWDPRD Register........................................................................................................................................378
Figure 3-188. NMISHDFLG Register.......................................................................................................................................379
Figure 3-189. ERRORSTS Register........................................................................................................................................ 381
Figure 3-190. ERRORSTSCLR Register.................................................................................................................................382
Figure 3-191. ERRORSTSFRC Register.................................................................................................................................383
Figure 3-192. ERRORCTL Register........................................................................................................................................ 384
Figure 3-193. ERRORLOCK Register..................................................................................................................................... 385
Figure 3-194. ADCA_AC Register........................................................................................................................................... 388
Figure 3-195. ADCB_AC Register........................................................................................................................................... 389
Figure 3-196. ADCC_AC Register...........................................................................................................................................390

SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023 TMS320F28003x Real-Time Microcontrollers 23

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Figure 3-197. CMPSS1_AC Register...................................................................................................................................... 391

Figure 3-198. CMPSS2_AC Register...................................................................................................................................... 392
Figure 3-199. CMPSS3_AC Register...................................................................................................................................... 393
Figure 3-200. CMPSS4_AC Register...................................................................................................................................... 394
Figure 3-201. DACA_AC Register........................................................................................................................................... 395
Figure 3-202. DACB_AC Register........................................................................................................................................... 396
Figure 3-203. EPWM1_AC Register........................................................................................................................................397
Figure 3-204. EPWM2_AC Register........................................................................................................................................398
Figure 3-205. EPWM3_AC Register........................................................................................................................................399
Figure 3-206. EPWM4_AC Register........................................................................................................................................400
Figure 3-207. EPWM5_AC Register........................................................................................................................................401
Figure 3-208. EPWM6_AC Register........................................................................................................................................402
Figure 3-209. EPWM7_AC Register........................................................................................................................................403
Figure 3-210. EPWM8_AC Register........................................................................................................................................404
Figure 3-211. EQEP1_AC Register......................................................................................................................................... 405
Figure 3-212. EQEP2_AC Register......................................................................................................................................... 406
Figure 3-213. ECAP1_AC Register......................................................................................................................................... 407
Figure 3-214. ECAP2_AC Register......................................................................................................................................... 408
Figure 3-215. ECAP3_AC Register......................................................................................................................................... 409
Figure 3-216. SDFM1_AC Register.........................................................................................................................................410
Figure 3-217. SDFM2_AC Register......................................................................................................................................... 411
Figure 3-218. CLB1_AC Register............................................................................................................................................ 412
Figure 3-219. CLB2_AC Register............................................................................................................................................ 413
Figure 3-220. CLB3_AC Register............................................................................................................................................ 414
Figure 3-221. CLB4_AC Register............................................................................................................................................ 415
Figure 3-222. SCIA_AC Register.............................................................................................................................................416
Figure 3-223. SCIB_AC Register.............................................................................................................................................417
Figure 3-224. SPIA_AC Register.............................................................................................................................................418
Figure 3-225. SPIB_AC Register.............................................................................................................................................419
Figure 3-226. I2CA_AC Register............................................................................................................................................. 420
Figure 3-227. I2CB_AC Register............................................................................................................................................. 421
Figure 3-228. PMBUS_A_AC Register....................................................................................................................................422
Figure 3-229. LIN_A_AC Register........................................................................................................................................... 423
Figure 3-230. LIN_B_AC Register........................................................................................................................................... 424
Figure 3-231. DCANA_AC Register........................................................................................................................................ 425
Figure 3-232. MCANA_AC Register........................................................................................................................................ 426
Figure 3-233. FSIATX_AC Register.........................................................................................................................................427
Figure 3-234. FSIARX_AC Register........................................................................................................................................ 428
Figure 3-235. HRPWM_A_AC Register...................................................................................................................................429
Figure 3-236. HIC_A_AC Register.......................................................................................................................................... 430
Figure 3-237. AESA_AC Register........................................................................................................................................... 431
Figure 3-238. PERIPH_AC_LOCK Register............................................................................................................................432
Figure 3-239. PIECTRL Register.............................................................................................................................................435
Figure 3-240. PIEACK Register...............................................................................................................................................436
Figure 3-241. PIEIER1 Register.............................................................................................................................................. 437
Figure 3-242. PIEIFR1 Register.............................................................................................................................................. 438
Figure 3-243. PIEIER2 Register.............................................................................................................................................. 440
Figure 3-244. PIEIFR2 Register.............................................................................................................................................. 441
Figure 3-245. PIEIER3 Register.............................................................................................................................................. 443
Figure 3-246. PIEIFR3 Register.............................................................................................................................................. 444
Figure 3-247. PIEIER4 Register.............................................................................................................................................. 446
Figure 3-248. PIEIFR4 Register.............................................................................................................................................. 447
Figure 3-249. PIEIER5 Register.............................................................................................................................................. 449
Figure 3-250. PIEIFR5 Register.............................................................................................................................................. 450
Figure 3-251. PIEIER6 Register.............................................................................................................................................. 452
Figure 3-252. PIEIFR6 Register.............................................................................................................................................. 453
Figure 3-253. PIEIER7 Register.............................................................................................................................................. 455
Figure 3-254. PIEIFR7 Register.............................................................................................................................................. 456
Figure 3-255. PIEIER8 Register.............................................................................................................................................. 458
Figure 3-256. PIEIFR8 Register.............................................................................................................................................. 459
Figure 3-257. PIEIER9 Register.............................................................................................................................................. 461

24 TMS320F28003x Real-Time Microcontrollers SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023

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Figure 3-258. PIEIFR9 Register.............................................................................................................................................. 462

Figure 3-259. PIEIER10 Register............................................................................................................................................ 464
Figure 3-260. PIEIFR10 Register............................................................................................................................................ 465
Figure 3-261. PIEIER11 Register.............................................................................................................................................467
Figure 3-262. PIEIFR11 Register.............................................................................................................................................468
Figure 3-263. PIEIER12 Register............................................................................................................................................ 470
Figure 3-264. PIEIFR12 Register............................................................................................................................................ 471
Figure 3-265. SYNCSELECT Register.................................................................................................................................... 474
Figure 3-266. ADCSOCOUTSELECT Register....................................................................................................................... 476
Figure 3-267. SYNCSOCLOCK Register................................................................................................................................ 478
Figure 3-268. SYS_ERR_INT_FLG Register.......................................................................................................................... 480
Figure 3-269. SYS_ERR_INT_CLR Register.......................................................................................................................... 481
Figure 3-270. SYS_ERR_INT_SET Register.......................................................................................................................... 482
Figure 3-271. SYS_ERR_MASK Register............................................................................................................................... 484
Figure 3-272. CPU_RAM_TEST_ERROR_STS Register....................................................................................................... 487
Figure 3-273. CPU_RAM_TEST_ERROR_STS_CLR Register.............................................................................................. 488
Figure 3-274. CPU_RAM_TEST_ERROR_ADDR Register.................................................................................................... 489
Figure 3-275. UID_PSRAND0 Register...................................................................................................................................491
Figure 3-276. UID_PSRAND1 Register...................................................................................................................................492
Figure 3-277. UID_PSRAND2 Register...................................................................................................................................493
Figure 3-278. UID_PSRAND3 Register...................................................................................................................................494
Figure 3-279. UID_PSRAND4 Register...................................................................................................................................495
Figure 3-280. UID_PSRAND5 Register...................................................................................................................................496
Figure 3-281. UID_UNIQUE Register......................................................................................................................................497
Figure 3-282. UID_CHECKSUM Register............................................................................................................................... 498
Figure 3-283. SCSR Register.................................................................................................................................................. 500
Figure 3-284. WDCNTR Register............................................................................................................................................ 501
Figure 3-285. WDKEY Register...............................................................................................................................................502
Figure 3-286. WDCR Register.................................................................................................................................................503
Figure 3-287. WDWCR Register............................................................................................................................................. 505
Figure 3-288. XINT1CR Register.............................................................................................................................................507
Figure 3-289. XINT2CR Register.............................................................................................................................................508
Figure 3-290. XINT3CR Register.............................................................................................................................................509
Figure 3-291. XINT4CR Register.............................................................................................................................................510
Figure 3-292. XINT5CR Register............................................................................................................................................. 511
Figure 3-293. XINT1CTR Register.......................................................................................................................................... 512
Figure 3-294. XINT2CTR Register.......................................................................................................................................... 513
Figure 3-295. XINT3CTR Register.......................................................................................................................................... 514
Figure 3-296. LFUConfig Register...........................................................................................................................................516
Figure 3-297. LFUStatus Register........................................................................................................................................... 517
Figure 3-298. SWConfig1_SYSRSn Register..........................................................................................................................518
Figure 3-299. SWConfig2_SYSRSn Register..........................................................................................................................519
Figure 3-300. SWConfig1_XRSn Register.............................................................................................................................. 520
Figure 3-301. SWConfig2_XRSn Register.............................................................................................................................. 521
Figure 3-302. SWConfig1_PORESETn Register.....................................................................................................................522
Figure 3-303. SWConfig2_PORESETn Register.....................................................................................................................523
Figure 3-304. LFU_LOCK Register......................................................................................................................................... 524
Figure 3-305. LFU_COMMIT Register.....................................................................................................................................525
Figure 4-1. Device Boot Flow.................................................................................................................................................. 556
Figure 4-2. Emulation Boot Flow............................................................................................................................................. 557
Figure 4-3. CPU Standalone Boot Flow...................................................................................................................................558
Figure 4-4. Overview of SCI Bootloader Operation................................................................................................................. 568
Figure 4-5. Overview of SCI Boot Function............................................................................................................................. 569
Figure 4-6. Overview of SPI Bootloader Operation................................................................................................................. 570
Figure 4-7. Data Transfer from EEPROM Flow....................................................................................................................... 572
Figure 4-8. EEPROM Device at Address 0x50........................................................................................................................573
Figure 4-9. Overview of I2C Boot Function..............................................................................................................................574
Figure 4-10. Random Read..................................................................................................................................................... 575
Figure 4-11. Sequential Read.................................................................................................................................................. 575
Figure 4-12. Overview of Parallel GPIO Bootloader Operation............................................................................................... 576
Figure 4-13. Parallel GPIO Bootloader Handshake Protocol...................................................................................................577

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Figure 4-14. Overview of Parallel GPIO Boot Function........................................................................................................... 577

Figure 4-15. Parallel GPIO Mode - Host Transfer Flow........................................................................................................... 578
Figure 4-16. 8-Bit Parallel GetWord Function.......................................................................................................................... 579
Figure 4-17. Overview of CAN-A Bootloader Operation.......................................................................................................... 580
Figure 5-1. Storage of Zone-Select Bits in OTP...................................................................................................................... 599
Figure 5-2. Location of Zone-Select Block Based on Link-Pointer.......................................................................................... 600
Figure 5-3. CSM Password Match Flow (PMF)....................................................................................................................... 605
Figure 5-4. ECSL Password Match Flow (PMF)......................................................................................................................607
Figure 5-5. Z1_LINKPOINTER Register..................................................................................................................................612
Figure 5-6. Z1_OTPSECLOCK Register................................................................................................................................. 613
Figure 5-7. Z1_JLM_ENABLE Register...................................................................................................................................614
Figure 5-8. Z1_LINKPOINTERERR Register.......................................................................................................................... 615
Figure 5-9. Z1_GPREG1 Register...........................................................................................................................................616
Figure 5-10. Z1_GPREG2 Register.........................................................................................................................................617
Figure 5-11. Z1_GPREG3 Register......................................................................................................................................... 618
Figure 5-12. Z1_GPREG4 Register.........................................................................................................................................619
Figure 5-13. Z1_CSMKEY0 Register.......................................................................................................................................620
Figure 5-14. Z1_CSMKEY1 Register.......................................................................................................................................621
Figure 5-15. Z1_CSMKEY2 Register.......................................................................................................................................622
Figure 5-16. Z1_CSMKEY3 Register.......................................................................................................................................623
Figure 5-17. Z1_CR Register...................................................................................................................................................624
Figure 5-18. Z1_GRABSECT1R Register............................................................................................................................... 626
Figure 5-19. Z1_GRABSECT2R Register............................................................................................................................... 629
Figure 5-20. Z1_GRABSECT3R Register............................................................................................................................... 632
Figure 5-21. Z1_GRABRAM1R Register................................................................................................................................. 635
Figure 5-22. Z1_EXEONLYSECT1R Register......................................................................................................................... 637
Figure 5-23. Z1_EXEONLYSECT2R Register......................................................................................................................... 642
Figure 5-24. Z1_EXEONLYRAM1R Register...........................................................................................................................645
Figure 5-25. Z1_JTAGKEY0 Register......................................................................................................................................647
Figure 5-26. Z1_JTAGKEY1 Register......................................................................................................................................648
Figure 5-27. Z1_JTAGKEY2 Register......................................................................................................................................649
Figure 5-28. Z1_JTAGKEY3 Register......................................................................................................................................650
Figure 5-29. Z1_CMACKEY0 Register.................................................................................................................................... 651
Figure 5-30. Z1_CMACKEY1 Register.................................................................................................................................... 652
Figure 5-31. Z1_CMACKEY2 Register.................................................................................................................................... 653
Figure 5-32. Z1_CMACKEY3 Register.................................................................................................................................... 654
Figure 5-33. Z2_LINKPOINTER Register................................................................................................................................657
Figure 5-34. Z2_OTPSECLOCK Register............................................................................................................................... 658
Figure 5-35. Z2_LINKPOINTERERR Register........................................................................................................................ 659
Figure 5-36. Z2_GPREG1 Register.........................................................................................................................................660
Figure 5-37. Z2_GPREG2 Register.........................................................................................................................................661
Figure 5-38. Z2_GPREG3 Register.........................................................................................................................................662
Figure 5-39. Z2_GPREG4 Register.........................................................................................................................................663
Figure 5-40. Z2_CSMKEY0 Register.......................................................................................................................................664
Figure 5-41. Z2_CSMKEY1 Register.......................................................................................................................................665
Figure 5-42. Z2_CSMKEY2 Register.......................................................................................................................................666
Figure 5-43. Z2_CSMKEY3 Register.......................................................................................................................................667
Figure 5-44. Z2_CR Register...................................................................................................................................................668
Figure 5-45. Z2_GRABSECT1R Register............................................................................................................................... 670
Figure 5-46. Z2_GRABSECT2R Register............................................................................................................................... 673
Figure 5-47. Z2_GRABSECT3R Register............................................................................................................................... 676
Figure 5-48. Z2_GRABRAM1R Register................................................................................................................................. 679
Figure 5-49. Z2_EXEONLYSECT1R Register......................................................................................................................... 681
Figure 5-50. Z2_EXEONLYSECT2R Register......................................................................................................................... 686
Figure 5-51. Z2_EXEONLYRAM1R Register...........................................................................................................................689
Figure 5-52. FLSEM Register.................................................................................................................................................. 692
Figure 5-53. SECTSTAT1 Register..........................................................................................................................................693
Figure 5-54. SECTSTAT2 Register..........................................................................................................................................696
Figure 5-55. SECTSTAT3 Register..........................................................................................................................................699
Figure 5-56. RAMSTAT1 Register........................................................................................................................................... 702
Figure 5-57. SECERRSTAT Register...................................................................................................................................... 704

26 TMS320F28003x Real-Time Microcontrollers SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023

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Figure 5-58. SECERRCLR Register........................................................................................................................................705

Figure 5-59. SECERRFRC Register........................................................................................................................................706
Figure 5-60. Z1OTP_LINKPOINTER1 Register...................................................................................................................... 708
Figure 5-61. Z1OTP_LINKPOINTER2 Register...................................................................................................................... 709
Figure 5-62. Z1OTP_LINKPOINTER3 Register...................................................................................................................... 710
Figure 5-63. Z1OTP_JLM_ENABLE Register..........................................................................................................................711
Figure 5-64. Z1OTP_GPREG1 Register................................................................................................................................. 712
Figure 5-65. Z1OTP_GPREG2 Register................................................................................................................................. 713
Figure 5-66. Z1OTP_GPREG3 Register................................................................................................................................. 714
Figure 5-67. Z1OTP_GPREG4 Register................................................................................................................................. 715
Figure 5-68. Z1OTP_PSWDLOCK Register............................................................................................................................716
Figure 5-69. Z1OTP_CRCLOCK Register...............................................................................................................................717
Figure 5-70. Z1OTP_JTAGPSWDH0 Register........................................................................................................................ 718
Figure 5-71. Z1OTP_JTAGPSWDH1 Register........................................................................................................................ 719
Figure 5-72. Z1OTP_CMACKEY0 Register.............................................................................................................................720
Figure 5-73. Z1OTP_CMACKEY1 Register.............................................................................................................................721
Figure 5-74. Z1OTP_CMACKEY2 Register.............................................................................................................................722
Figure 5-75. Z1OTP_CMACKEY3 Register.............................................................................................................................723
Figure 5-76. Z2OTP_LINKPOINTER1 Register...................................................................................................................... 725
Figure 5-77. Z2OTP_LINKPOINTER2 Register...................................................................................................................... 726
Figure 5-78. Z2OTP_LINKPOINTER3 Register...................................................................................................................... 727
Figure 5-79. Z2OTP_GPREG1 Register................................................................................................................................. 728
Figure 5-80. Z2OTP_GPREG2 Register................................................................................................................................. 729
Figure 5-81. Z2OTP_GPREG3 Register................................................................................................................................. 730
Figure 5-82. Z2OTP_GPREG4 Register................................................................................................................................. 731
Figure 5-83. Z2OTP_PSWDLOCK Register............................................................................................................................732
Figure 5-84. Z2OTP_CRCLOCK Register...............................................................................................................................733
Figure 6-1. FMC Interface with Core, Bank, and Pump...........................................................................................................738
Figure 6-2. Flash Prefetch Mode............................................................................................................................................. 742
Figure 6-3. ECC Logic Inputs and Outputs..............................................................................................................................745
Figure 6-4. FRDCNTL Register............................................................................................................................................... 754
Figure 6-5. FBAC Register...................................................................................................................................................... 755
Figure 6-6. FBFALLBACK Register......................................................................................................................................... 756
Figure 6-7. FBPRDY Register................................................................................................................................................. 757
Figure 6-8. FPAC1 Register.....................................................................................................................................................758
Figure 6-9. FPAC2 Register.....................................................................................................................................................759
Figure 6-10. FMSTAT Register................................................................................................................................................ 760
Figure 6-11. FRD_INTF_CTRL Register..................................................................................................................................762
Figure 6-12. ECC_ENABLE Register...................................................................................................................................... 765
Figure 6-13. SINGLE_ERR_ADDR_LOW Register.................................................................................................................766
Figure 6-14. SINGLE_ERR_ADDR_HIGH Register................................................................................................................ 767
Figure 6-15. UNC_ERR_ADDR_LOW Register...................................................................................................................... 768
Figure 6-16. UNC_ERR_ADDR_HIGH Register..................................................................................................................... 769
Figure 6-17. ERR_STATUS Register.......................................................................................................................................770
Figure 6-18. ERR_POS Register.............................................................................................................................................772
Figure 6-19. ERR_STATUS_CLR Register..............................................................................................................................773
Figure 6-20. ERR_CNT Register............................................................................................................................................. 774
Figure 6-21. ERR_THRESHOLD Register.............................................................................................................................. 775
Figure 6-22. ERR_INTFLG Register........................................................................................................................................776
Figure 6-23. ERR_INTCLR Register....................................................................................................................................... 777
Figure 6-24. FDATAH_TEST Register..................................................................................................................................... 778
Figure 6-25. FDATAL_TEST Register......................................................................................................................................779
Figure 6-26. FADDR_TEST Register.......................................................................................................................................780
Figure 6-27. FECC_TEST Register......................................................................................................................................... 781
Figure 6-28. FECC_CTRL Register.........................................................................................................................................782
Figure 6-29. FOUTH_TEST Register...................................................................................................................................... 783
Figure 6-30. FOUTL_TEST Register....................................................................................................................................... 784
Figure 6-31. FECC_STATUS Register.....................................................................................................................................785
Figure 7-1. CLA (Type 2) Block Diagram.................................................................................................................................791
Figure 7-2. _MVECTBGRNDACTIVE Register....................................................................................................................... 935
Figure 7-3. _MPSACTL Register............................................................................................................................................. 936

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Figure 7-4. _MPSA1 Register..................................................................................................................................................937

Figure 7-5. _MPSA2 Register..................................................................................................................................................938
Figure 7-6. SOFTINTEN Register............................................................................................................................................939
Figure 7-7. SOFTINTFRC Register......................................................................................................................................... 941
Figure 7-8. SOFTINTEN Register............................................................................................................................................943
Figure 7-9. SOFTINTFRC Register......................................................................................................................................... 945
Figure 7-10. MVECT1 Register............................................................................................................................................... 948
Figure 7-11. MVECT2 Register................................................................................................................................................949
Figure 7-12. MVECT3 Register............................................................................................................................................... 950
Figure 7-13. MVECT4 Register............................................................................................................................................... 951
Figure 7-14. MVECT5 Register............................................................................................................................................... 952
Figure 7-15. MVECT6 Register............................................................................................................................................... 953
Figure 7-16. MVECT7 Register............................................................................................................................................... 954
Figure 7-17. MVECT8 Register............................................................................................................................................... 955
Figure 7-18. MCTL Register.................................................................................................................................................... 956
Figure 7-19. _MVECTBGRNDACTIVE Register..................................................................................................................... 957
Figure 7-20. SOFTINTEN Register..........................................................................................................................................958
Figure 7-21. _MSTSBGRND Register..................................................................................................................................... 960
Figure 7-22. _MCTLBGRND Register..................................................................................................................................... 961
Figure 7-23. _MVECTBGRND Register.................................................................................................................................. 962
Figure 7-24. MIFR Register..................................................................................................................................................... 963
Figure 7-25. MIOVF Register...................................................................................................................................................967
Figure 7-26. MIFRC Register...................................................................................................................................................970
Figure 7-27. MICLR Register...................................................................................................................................................972
Figure 7-28. MICLROVF Register........................................................................................................................................... 974
Figure 7-29. MIER Register..................................................................................................................................................... 976
Figure 7-30. MIRUN Register.................................................................................................................................................. 979
Figure 7-31. _MPC Register.................................................................................................................................................... 981
Figure 7-32. _MAR0 Register.................................................................................................................................................. 982
Figure 7-33. _MAR1 Register.................................................................................................................................................. 983
Figure 7-34. _MSTF Register.................................................................................................................................................. 984
Figure 7-35. _MR0 Register.................................................................................................................................................... 987
Figure 7-36. _MR1 Register.................................................................................................................................................... 988
Figure 7-37. _MR2 Register.................................................................................................................................................... 989
Figure 7-38. _MR3 Register.................................................................................................................................................... 990
Figure 7-39. _MPSACTL Register........................................................................................................................................... 991
Figure 7-40. _MPSA1 Register................................................................................................................................................992
Figure 7-41. _MPSA2 Register................................................................................................................................................993
Figure 8-1. DCC Module Overview..........................................................................................................................................998
Figure 8-2. DCC Operation......................................................................................................................................................999
Figure 8-3. Counter Relationship...........................................................................................................................................1003
Figure 8-4. Clock1 Slower Than Clock0 - Results in an Error and Stops Counting...............................................................1003
Figure 8-5. Clock1 Faster Than Clock0 - Results in an Error and Stops Counting............................................................... 1004
Figure 8-6. Clock1 Not Present - Results in an Error and Stops Counting............................................................................1004
Figure 8-7. Clock0 Not Present - Results in an Error and Stops Counting............................................................................1005
Figure 8-8. DCCGCTRL Register.......................................................................................................................................... 1010
Figure 8-9. DCCCNTSEED0 Register................................................................................................................................... 1011
Figure 8-10. DCCVALIDSEED0 Register.............................................................................................................................. 1012
Figure 8-11. DCCCNTSEED1 Register................................................................................................................................. 1013
Figure 8-12. DCCSTATUS Register.......................................................................................................................................1014
Figure 8-13. DCCCNT0 Register...........................................................................................................................................1015
Figure 8-14. DCCVALID0 Register........................................................................................................................................ 1016
Figure 8-15. DCCCNT1 Register...........................................................................................................................................1017
Figure 8-16. DCCCLKSRC1 Register....................................................................................................................................1018
Figure 8-17. DCCCLKSRC0 Register....................................................................................................................................1019
Figure 9-1. BGCRC Block Diagram....................................................................................................................................... 1022
Figure 9-2. BGCRC Memory Map......................................................................................................................................... 1023
Figure 9-3. BGCRC NMI........................................................................................................................................................1025
Figure 9-4. BGCRC Interrupt................................................................................................................................................. 1025
Figure 9-5. BGCRC Execution Sequence Flow.....................................................................................................................1027
Figure 9-6. BGCRC Execution Sequence Example.............................................................................................................. 1029

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Figure 9-7. BGCRC_EN Register.......................................................................................................................................... 1036

Figure 9-8. BGCRC_CTRL1 Register....................................................................................................................................1037
Figure 9-9. BGCRC_CTRL2 Register....................................................................................................................................1038
Figure 9-10. BGCRC_START_ADDR Register..................................................................................................................... 1039
Figure 9-11. BGCRC_SEED Register....................................................................................................................................1040
Figure 9-12. BGCRC_GOLDEN Register..............................................................................................................................1041
Figure 9-13. BGCRC_RESULT Register............................................................................................................................... 1042
Figure 9-14. BGCRC_CURR_ADDR Register...................................................................................................................... 1043
Figure 9-15. BGCRC_WD_CFG Register............................................................................................................................. 1044
Figure 9-16. BGCRC_WD_MIN Register.............................................................................................................................. 1045
Figure 9-17. BGCRC_WD_MAX Register............................................................................................................................. 1046
Figure 9-18. BGCRC_WD_CNT Register..............................................................................................................................1047
Figure 9-19. BGCRC_NMIFLG Register............................................................................................................................... 1048
Figure 9-20. BGCRC_NMICLR Register............................................................................................................................... 1049
Figure 9-21. BGCRC_NMIFRC Register............................................................................................................................... 1050
Figure 9-22. BGCRC_INTEN Register.................................................................................................................................. 1051
Figure 9-23. BGCRC_INTFLG Register................................................................................................................................ 1052
Figure 9-24. BGCRC_INTCLR Register................................................................................................................................ 1054
Figure 9-25. BGCRC_INTFRC Register................................................................................................................................1055
Figure 9-26. BGCRC_LOCK Register................................................................................................................................... 1056
Figure 9-27. BGCRC_COMMIT Register.............................................................................................................................. 1058
Figure 10-1. GPIO Logic for a Single Pin.............................................................................................................................. 1065
Figure 10-2. Input Qualification Using a Sampling Window...................................................................................................1071
Figure 10-3. Input Qualifier Clock Cycles.............................................................................................................................. 1074
Figure 10-4. GPACTRL Register........................................................................................................................................... 1085
Figure 10-5. GPAQSEL1 Register......................................................................................................................................... 1086
Figure 10-6. GPAQSEL2 Register......................................................................................................................................... 1088
Figure 10-7. GPAMUX1 Register...........................................................................................................................................1090
Figure 10-8. GPAMUX2 Register...........................................................................................................................................1091
Figure 10-9. GPADIR Register...............................................................................................................................................1092
Figure 10-10. GPAPUD Register........................................................................................................................................... 1094
Figure 10-11. GPAINV Register............................................................................................................................................. 1096
Figure 10-12. GPAODR Register...........................................................................................................................................1098
Figure 10-13. GPAAMSEL Register.......................................................................................................................................1100
Figure 10-14. GPAGMUX1 Register...................................................................................................................................... 1102
Figure 10-15. GPAGMUX2 Register...................................................................................................................................... 1103
Figure 10-16. GPACSEL1 Register........................................................................................................................................1104
Figure 10-17. GPACSEL2 Register........................................................................................................................................1105
Figure 10-18. GPACSEL3 Register........................................................................................................................................1106
Figure 10-19. GPACSEL4 Register........................................................................................................................................1107
Figure 10-20. GPALOCK Register......................................................................................................................................... 1108
Figure 10-21. GPACR Register.............................................................................................................................................. 1110
Figure 10-22. GPBCTRL Register..........................................................................................................................................1112
Figure 10-23. GPBQSEL1 Register....................................................................................................................................... 1113
Figure 10-24. GPBQSEL2 Register....................................................................................................................................... 1115
Figure 10-25. GPBMUX1 Register......................................................................................................................................... 1117
Figure 10-26. GPBMUX2 Register......................................................................................................................................... 1118
Figure 10-27. GPBDIR Register.............................................................................................................................................1119
Figure 10-28. GPBPUD Register........................................................................................................................................... 1121
Figure 10-29. GPBINV Register.............................................................................................................................................1123
Figure 10-30. GPBODR Register...........................................................................................................................................1125
Figure 10-31. GPBGMUX1 Register...................................................................................................................................... 1127
Figure 10-32. GPBGMUX2 Register...................................................................................................................................... 1128
Figure 10-33. GPBCSEL1 Register....................................................................................................................................... 1129
Figure 10-34. GPBCSEL2 Register....................................................................................................................................... 1130
Figure 10-35. GPBCSEL3 Register....................................................................................................................................... 1131
Figure 10-36. GPBCSEL4 Register....................................................................................................................................... 1132
Figure 10-37. GPBLOCK Register......................................................................................................................................... 1133
Figure 10-38. GPBCR Register..............................................................................................................................................1135
Figure 10-39. GPHCTRL Register......................................................................................................................................... 1137
Figure 10-40. GPHQSEL1 Register....................................................................................................................................... 1138

SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023 TMS320F28003x Real-Time Microcontrollers 29

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Figure 10-41. GPHQSEL2 Register....................................................................................................................................... 1140

Figure 10-42. GPHMUX1 Register.........................................................................................................................................1142
Figure 10-43. GPHMUX2 Register.........................................................................................................................................1144
Figure 10-44. GPHPUD Register........................................................................................................................................... 1145
Figure 10-45. GPHINV Register.............................................................................................................................................1150
Figure 10-46. GPHAMSEL Register...................................................................................................................................... 1154
Figure 10-47. GPHGMUX1 Register......................................................................................................................................1160
Figure 10-48. GPHGMUX2 Register......................................................................................................................................1162
Figure 10-49. GPHCSEL1 Register....................................................................................................................................... 1163
Figure 10-50. GPHCSEL2 Register....................................................................................................................................... 1164
Figure 10-51. GPHCSEL3 Register....................................................................................................................................... 1165
Figure 10-52. GPHCSEL4 Register....................................................................................................................................... 1166
Figure 10-53. GPHLOCK Register.........................................................................................................................................1167
Figure 10-54. GPHCR Register............................................................................................................................................. 1171
Figure 10-55. GPADAT Register............................................................................................................................................ 1175
Figure 10-56. GPASET Register............................................................................................................................................ 1177
Figure 10-57. GPACLEAR Register....................................................................................................................................... 1179
Figure 10-58. GPATOGGLE Register.................................................................................................................................... 1181
Figure 10-59. GPBDAT Register............................................................................................................................................1183
Figure 10-60. GPBSET Register............................................................................................................................................1185
Figure 10-61. GPBCLEAR Register.......................................................................................................................................1187
Figure 10-62. GPBTOGGLE Register....................................................................................................................................1189
Figure 10-63. GPHDAT Register............................................................................................................................................1191
Figure 10-64. GPADAT_R Register....................................................................................................................................... 1198
Figure 10-65. GPBDAT_R Register....................................................................................................................................... 1199
Figure 10-66. GPHDAT_R Register.......................................................................................................................................1200
Figure 11-1. Input X-BAR.......................................................................................................................................................1206
Figure 11-2. ePWM X-BAR Architecture - Single Output.......................................................................................................1209
Figure 11-3. CLB X-BAR Architecture - Single Output...........................................................................................................1211
Figure 11-4. GPIO to CLB Tile Connections.......................................................................................................................... 1212
Figure 11-5. GPIO Output X-BAR Architecture......................................................................................................................1214
Figure 11-6. ePWM and Output X-BARs Sources................................................................................................................. 1218
Figure 11-7. INPUT1SELECT Register..................................................................................................................................1222
Figure 11-8. INPUT2SELECT Register..................................................................................................................................1223
Figure 11-9. INPUT3SELECT Register..................................................................................................................................1224
Figure 11-10. INPUT4SELECT Register................................................................................................................................1225
Figure 11-11. INPUT5SELECT Register................................................................................................................................1226
Figure 11-12. INPUT6SELECT Register................................................................................................................................1227
Figure 11-13. INPUT7SELECT Register................................................................................................................................1228
Figure 11-14. INPUT8SELECT Register................................................................................................................................1229
Figure 11-15. INPUT9SELECT Register................................................................................................................................1230
Figure 11-16. INPUT10SELECT Register..............................................................................................................................1231
Figure 11-17. INPUT11SELECT Register..............................................................................................................................1232
Figure 11-18. INPUT12SELECT Register..............................................................................................................................1233
Figure 11-19. INPUT13SELECT Register..............................................................................................................................1234
Figure 11-20. INPUT14SELECT Register..............................................................................................................................1235
Figure 11-21. INPUT15SELECT Register..............................................................................................................................1236
Figure 11-22. INPUT16SELECT Register..............................................................................................................................1237
Figure 11-23. INPUTSELECTLOCK Register........................................................................................................................1238
Figure 11-24. XBARFLG1 Register........................................................................................................................................1241
Figure 11-25. XBARFLG2 Register........................................................................................................................................1244
Figure 11-26. XBARFLG3 Register........................................................................................................................................1248
Figure 11-27. XBARFLG4 Register........................................................................................................................................1252
Figure 11-28. XBARCLR1 Register....................................................................................................................................... 1256
Figure 11-29. XBARCLR2 Register....................................................................................................................................... 1258
Figure 11-30. XBARCLR3 Register....................................................................................................................................... 1261
Figure 11-31. XBARCLR4 Register....................................................................................................................................... 1264
Figure 11-32. TRIP4MUX0TO15CFG Register......................................................................................................................1269
Figure 11-33. TRIP4MUX16TO31CFG Register....................................................................................................................1272
Figure 11-34. TRIP5MUX0TO15CFG Register......................................................................................................................1275
Figure 11-35. TRIP5MUX16TO31CFG Register....................................................................................................................1278

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Figure 11-36. TRIP7MUX0TO15CFG Register......................................................................................................................1281

Figure 11-37. TRIP7MUX16TO31CFG Register....................................................................................................................1284
Figure 11-38. TRIP8MUX0TO15CFG Register......................................................................................................................1287
Figure 11-39. TRIP8MUX16TO31CFG Register....................................................................................................................1290
Figure 11-40. TRIP9MUX0TO15CFG Register......................................................................................................................1293
Figure 11-41. TRIP9MUX16TO31CFG Register....................................................................................................................1296
Figure 11-42. TRIP10MUX0TO15CFG Register....................................................................................................................1299
Figure 11-43. TRIP10MUX16TO31CFG Register..................................................................................................................1302
Figure 11-44. TRIP11MUX0TO15CFG Register....................................................................................................................1305
Figure 11-45. TRIP11MUX16TO31CFG Register..................................................................................................................1308
Figure 11-46. TRIP12MUX0TO15CFG Register....................................................................................................................1311
Figure 11-47. TRIP12MUX16TO31CFG Register..................................................................................................................1314
Figure 11-48. TRIP4MUXENABLE Register.......................................................................................................................... 1317
Figure 11-49. TRIP5MUXENABLE Register.......................................................................................................................... 1322
Figure 11-50. TRIP7MUXENABLE Register.......................................................................................................................... 1327
Figure 11-51. TRIP8MUXENABLE Register.......................................................................................................................... 1332
Figure 11-52. TRIP9MUXENABLE Register.......................................................................................................................... 1337
Figure 11-53. TRIP10MUXENABLE Register........................................................................................................................ 1342
Figure 11-54. TRIP11MUXENABLE Register........................................................................................................................ 1347
Figure 11-55. TRIP12MUXENABLE Register........................................................................................................................ 1352
Figure 11-56. TRIPOUTINV Register.....................................................................................................................................1357
Figure 11-57. TRIPLOCK Register........................................................................................................................................ 1359
Figure 11-58. AUXSIG0MUX0TO15CFG Register................................................................................................................ 1362
Figure 11-59. AUXSIG0MUX16TO31CFG Register.............................................................................................................. 1365
Figure 11-60. AUXSIG1MUX0TO15CFG Register................................................................................................................ 1368
Figure 11-61. AUXSIG1MUX16TO31CFG Register.............................................................................................................. 1371
Figure 11-62. AUXSIG2MUX0TO15CFG Register................................................................................................................ 1374
Figure 11-63. AUXSIG2MUX16TO31CFG Register.............................................................................................................. 1377
Figure 11-64. AUXSIG3MUX0TO15CFG Register................................................................................................................ 1380
Figure 11-65. AUXSIG3MUX16TO31CFG Register.............................................................................................................. 1383
Figure 11-66. AUXSIG4MUX0TO15CFG Register................................................................................................................ 1386
Figure 11-67. AUXSIG4MUX16TO31CFG Register.............................................................................................................. 1389
Figure 11-68. AUXSIG5MUX0TO15CFG Register................................................................................................................ 1392
Figure 11-69. AUXSIG5MUX16TO31CFG Register.............................................................................................................. 1395
Figure 11-70. AUXSIG6MUX0TO15CFG Register................................................................................................................ 1398
Figure 11-71. AUXSIG6MUX16TO31CFG Register.............................................................................................................. 1401
Figure 11-72. AUXSIG7MUX0TO15CFG Register................................................................................................................ 1404
Figure 11-73. AUXSIG7MUX16TO31CFG Register.............................................................................................................. 1407
Figure 11-74. AUXSIG0MUXENABLE Register.....................................................................................................................1410
Figure 11-75. AUXSIG1MUXENABLE Register.....................................................................................................................1415
Figure 11-76. AUXSIG2MUXENABLE Register.....................................................................................................................1420
Figure 11-77. AUXSIG3MUXENABLE Register.....................................................................................................................1425
Figure 11-78. AUXSIG4MUXENABLE Register.....................................................................................................................1430
Figure 11-79. AUXSIG5MUXENABLE Register.....................................................................................................................1435
Figure 11-80. AUXSIG6MUXENABLE Register.....................................................................................................................1440
Figure 11-81. AUXSIG7MUXENABLE Register.....................................................................................................................1445
Figure 11-82. AUXSIGOUTINV Register............................................................................................................................... 1450
Figure 11-83. AUXSIGLOCK Register................................................................................................................................... 1452
Figure 11-84. OUTPUT1MUX0TO15CFG Register............................................................................................................... 1455
Figure 11-85. OUTPUT1MUX16TO31CFG Register............................................................................................................. 1458
Figure 11-86. OUTPUT2MUX0TO15CFG Register............................................................................................................... 1461
Figure 11-87. OUTPUT2MUX16TO31CFG Register............................................................................................................. 1464
Figure 11-88. OUTPUT3MUX0TO15CFG Register............................................................................................................... 1467
Figure 11-89. OUTPUT3MUX16TO31CFG Register............................................................................................................. 1470
Figure 11-90. OUTPUT4MUX0TO15CFG Register............................................................................................................... 1473
Figure 11-91. OUTPUT4MUX16TO31CFG Register............................................................................................................. 1476
Figure 11-92. OUTPUT5MUX0TO15CFG Register............................................................................................................... 1479
Figure 11-93. OUTPUT5MUX16TO31CFG Register............................................................................................................. 1482
Figure 11-94. OUTPUT6MUX0TO15CFG Register............................................................................................................... 1485
Figure 11-95. OUTPUT6MUX16TO31CFG Register............................................................................................................. 1488
Figure 11-96. OUTPUT7MUX0TO15CFG Register............................................................................................................... 1491

SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023 TMS320F28003x Real-Time Microcontrollers 31

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Figure 11-97. OUTPUT7MUX16TO31CFG Register............................................................................................................. 1494

Figure 11-98. OUTPUT8MUX0TO15CFG Register............................................................................................................... 1497
Figure 11-99. OUTPUT8MUX16TO31CFG Register............................................................................................................. 1500
Figure 11-100. OUTPUT1MUXENABLE Register................................................................................................................. 1503
Figure 11-101. OUTPUT2MUXENABLE Register................................................................................................................. 1508
Figure 11-102. OUTPUT3MUXENABLE Register................................................................................................................. 1513
Figure 11-103. OUTPUT4MUXENABLE Register................................................................................................................. 1518
Figure 11-104. OUTPUT5MUXENABLE Register................................................................................................................. 1523
Figure 11-105. OUTPUT6MUXENABLE Register................................................................................................................. 1528
Figure 11-106. OUTPUT7MUXENABLE Register................................................................................................................. 1533
Figure 11-107. OUTPUT8MUXENABLE Register................................................................................................................. 1538
Figure 11-108. OUTPUTLATCH Register.............................................................................................................................. 1543
Figure 11-109. OUTPUTLATCHCLR Register.......................................................................................................................1545
Figure 11-110. OUTPUTLATCHFRC Register.......................................................................................................................1547
Figure 11-111. OUTPUTLATCHENABLE Register................................................................................................................ 1549
Figure 11-112. OUTPUTINV Register....................................................................................................................................1551
Figure 11-113. OUTPUTLOCK Register................................................................................................................................ 1553
Figure 12-1. DMA Block Diagram.......................................................................................................................................... 1563
Figure 12-2. DMA Trigger Architecture.................................................................................................................................. 1565
Figure 12-3. Peripheral Interrupt Trigger Input Diagram........................................................................................................1566
Figure 12-4. DMA State Diagram.......................................................................................................................................... 1574
Figure 12-5. 3-Stage Pipeline DMA Transfer.........................................................................................................................1575
Figure 12-6. 3-stage Pipeline with One Read Stall................................................................................................................1575
Figure 12-7. Overrun Detection Logic....................................................................................................................................1578
Figure 12-8. DMACTRL Register...........................................................................................................................................1581
Figure 12-9. DEBUGCTRL Register......................................................................................................................................1582
Figure 12-10. PRIORITYCTRL1 Register..............................................................................................................................1583
Figure 12-11. PRIORITYSTAT Register.................................................................................................................................1584
Figure 12-12. MODE Register............................................................................................................................................... 1587
Figure 12-13. CONTROL Register........................................................................................................................................ 1589
Figure 12-14. BURST_SIZE Register....................................................................................................................................1591
Figure 12-15. BURST_COUNT Register............................................................................................................................... 1592
Figure 12-16. SRC_BURST_STEP Register.........................................................................................................................1593
Figure 12-17. DST_BURST_STEP Register......................................................................................................................... 1594
Figure 12-18. TRANSFER_SIZE Register.............................................................................................................................1595
Figure 12-19. TRANSFER_COUNT Register........................................................................................................................1596
Figure 12-20. SRC_TRANSFER_STEP Register..................................................................................................................1597
Figure 12-21. DST_TRANSFER_STEP Register.................................................................................................................. 1598
Figure 12-22. SRC_WRAP_SIZE Register............................................................................................................................1599
Figure 12-23. SRC_WRAP_COUNT Register.......................................................................................................................1600
Figure 12-24. SRC_WRAP_STEP Register.......................................................................................................................... 1601
Figure 12-25. DST_WRAP_SIZE Register............................................................................................................................ 1602
Figure 12-26. DST_WRAP_COUNT Register....................................................................................................................... 1603
Figure 12-27. DST_WRAP_STEP Register...........................................................................................................................1604
Figure 12-28. SRC_BEG_ADDR_SHADOW Register.......................................................................................................... 1605
Figure 12-29. SRC_ADDR_SHADOW Register.................................................................................................................... 1606
Figure 12-30. SRC_BEG_ADDR_ACTIVE Register..............................................................................................................1607
Figure 12-31. SRC_ADDR_ACTIVE Register....................................................................................................................... 1608
Figure 12-32. DST_BEG_ADDR_SHADOW Register...........................................................................................................1609
Figure 12-33. DST_ADDR_SHADOW Register.................................................................................................................... 1610
Figure 12-34. DST_BEG_ADDR_ACTIVE Register.............................................................................................................. 1611
Figure 12-35. DST_ADDR_ACTIVE Register........................................................................................................................1612
Figure 13-1. ERAD Overview................................................................................................................................................ 1616
Figure 13-2. EBC Units Event Masking................................................................................................................................. 1618
Figure 13-3. System Event Counter Inputs............................................................................................................................1620
Figure 13-4. Event Masking and Exporting for CRC Qualifiers............................................................................................. 1627
Figure 13-5. PC Trace Operation...........................................................................................................................................1629
Figure 13-6. PC Trace Block Diagram................................................................................................................................... 1630
Figure 13-7. Trace Qualifier Input Conditioning Circuit..........................................................................................................1634
Figure 13-8. GLBL_EVENT_STAT Register.......................................................................................................................... 1648
Figure 13-9. GLBL_HALT_STAT Register............................................................................................................................. 1650

32 TMS320F28003x Real-Time Microcontrollers SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023

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Figure 13-10. GLBL_ENABLE Register.................................................................................................................................1652

Figure 13-11. GLBL_CTM_RESET Register......................................................................................................................... 1654
Figure 13-12. GLBL_NMI_CTL Register............................................................................................................................... 1655
Figure 13-13. GLBL_OWNER Register................................................................................................................................. 1657
Figure 13-14. GLBL_EVENT_AND_MASK Register............................................................................................................. 1658
Figure 13-15. GLBL_EVENT_OR_MASK Register............................................................................................................... 1662
Figure 13-16. GLBL_AND_EVENT_INT_MASK Register..................................................................................................... 1666
Figure 13-17. GLBL_OR_EVENT_INT_MASK Register....................................................................................................... 1667
Figure 13-18. HWBP_MASK Register................................................................................................................................... 1669
Figure 13-19. HWBP_REF Register...................................................................................................................................... 1670
Figure 13-20. HWBP_CLEAR Register................................................................................................................................. 1671
Figure 13-21. HWBP_CNTL Register....................................................................................................................................1672
Figure 13-22. HWBP_STATUS Register................................................................................................................................1674
Figure 13-23. CTM_CNTL Register.......................................................................................................................................1676
Figure 13-24. CTM_STATUS Register...................................................................................................................................1678
Figure 13-25. CTM_REF Register......................................................................................................................................... 1679
Figure 13-26. CTM_COUNT Register................................................................................................................................... 1680
Figure 13-27. CTM_MAX_COUNT Register..........................................................................................................................1681
Figure 13-28. CTM_INPUT_SEL Register.............................................................................................................................1682
Figure 13-29. CTM_CLEAR Register.................................................................................................................................... 1683
Figure 13-30. CTM_INPUT_SEL_2 Register.........................................................................................................................1684
Figure 13-31. CTM_INPUT_COND Register.........................................................................................................................1685
Figure 13-32. CRC_GLOBAL_CTRL Register...................................................................................................................... 1687
Figure 13-33. CRC_CURRENT Register...............................................................................................................................1690
Figure 13-34. CRC_SEED Register...................................................................................................................................... 1691
Figure 13-35. CRC_QUALIFIER Register............................................................................................................................. 1692
Figure 14-1. HIC Block Diagram............................................................................................................................................1697
Figure 14-2. HIC Memory Map.............................................................................................................................................. 1698
Figure 14-3. HIC Connections............................................................................................................................................... 1699
Figure 14-4. HIC Host to Device Interrupt Sources............................................................................................................... 1700
Figure 14-5. HIC Device to Host Interrupt Sources............................................................................................................... 1701
Figure 14-6. HIC Mailbox Access Mode Diagram..................................................................................................................1702
Figure 14-7. HIC Direct Access Mode Diagram.....................................................................................................................1704
Figure 14-8. Read/Write Access in Single-Pin Mode.............................................................................................................1706
Figure 14-9. Read/Write Access in Dual-Pin Mode............................................................................................................... 1707
Figure 14-10. HICREV Register............................................................................................................................................ 1719
Figure 14-11. HICGCR Register............................................................................................................................................ 1720
Figure 14-12. HICLOCK Register.......................................................................................................................................... 1721
Figure 14-13. HICMODECR Register....................................................................................................................................1722
Figure 14-14. HICPINPOLCR Register................................................................................................................................. 1724
Figure 14-15. HICBASESEL Register................................................................................................................................... 1725
Figure 14-16. HICHOSTCR Register.....................................................................................................................................1726
Figure 14-17. HICERRADDR Register.................................................................................................................................. 1728
Figure 14-18. HICH2DTOKEN Register................................................................................................................................ 1730
Figure 14-19. HICD2HTOKEN Register................................................................................................................................ 1731
Figure 14-20. HICDBADDR0 Register...................................................................................................................................1732
Figure 14-21. HICDBADDR1 Register...................................................................................................................................1733
Figure 14-22. HICDBADDR2 Register...................................................................................................................................1734
Figure 14-23. HICDBADDR3 Register...................................................................................................................................1735
Figure 14-24. HICDBADDR4 Register...................................................................................................................................1736
Figure 14-25. HICDBADDR5 Register...................................................................................................................................1737
Figure 14-26. HICDBADDR6 Register...................................................................................................................................1738
Figure 14-27. HICDBADDR7 Register...................................................................................................................................1739
Figure 14-28. HICH2DINTEN Register..................................................................................................................................1740
Figure 14-29. HICH2DINTFLG Register................................................................................................................................1741
Figure 14-30. HICH2DINTCLR Register................................................................................................................................1742
Figure 14-31. HICH2DINTFRC Register............................................................................................................................... 1743
Figure 14-32. HICD2HINTEN Register..................................................................................................................................1744
Figure 14-33. HICD2HINTFLG Register................................................................................................................................1746
Figure 14-34. HICD2HINTCLR Register................................................................................................................................1748
Figure 14-35. HICD2HINTFRC Register............................................................................................................................... 1750

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Figure 14-36. HICACCVIOADDR Register............................................................................................................................1752

Figure 14-37. HICCOMMIT Register..................................................................................................................................... 1753
Figure 14-38. H2D_BUF0 Register........................................................................................................................................1754
Figure 14-39. H2D_BUF1 Register........................................................................................................................................1755
Figure 14-40. H2D_BUF2 Register........................................................................................................................................1756
Figure 14-41. H2D_BUF3 Register........................................................................................................................................1757
Figure 14-42. H2D_BUF4 Register........................................................................................................................................1758
Figure 14-43. H2D_BUF5 Register........................................................................................................................................1759
Figure 14-44. H2D_BUF6 Register........................................................................................................................................1760
Figure 14-45. H2D_BUF7 Register........................................................................................................................................1761
Figure 14-46. H2D_BUF8 Register........................................................................................................................................1762
Figure 14-47. H2D_BUF9 Register........................................................................................................................................1763
Figure 14-48. H2D_BUF10 Register......................................................................................................................................1764
Figure 14-49. H2D_BUF11 Register...................................................................................................................................... 1765
Figure 14-50. H2D_BUF12 Register......................................................................................................................................1766
Figure 14-51. H2D_BUF13 Register......................................................................................................................................1767
Figure 14-52. H2D_BUF14 Register......................................................................................................................................1768
Figure 14-53. H2D_BUF15 Register......................................................................................................................................1769
Figure 14-54. D2H_BUF0 Register........................................................................................................................................1770
Figure 14-55. D2H_BUF1 Register........................................................................................................................................1771
Figure 14-56. D2H_BUF2 Register........................................................................................................................................1772
Figure 14-57. D2H_BUF3 Register........................................................................................................................................1773
Figure 14-58. D2H_BUF4 Register........................................................................................................................................1774
Figure 14-59. D2H_BUF5 Register........................................................................................................................................1775
Figure 14-60. D2H_BUF6 Register........................................................................................................................................1776
Figure 14-61. D2H_BUF7 Register........................................................................................................................................1777
Figure 14-62. D2H_BUF8 Register........................................................................................................................................1778
Figure 14-63. D2H_BUF9 Register........................................................................................................................................1779
Figure 14-64. D2H_BUF10 Register......................................................................................................................................1780
Figure 14-65. D2H_BUF11 Register...................................................................................................................................... 1781
Figure 14-66. D2H_BUF12 Register......................................................................................................................................1782
Figure 14-67. D2H_BUF13 Register......................................................................................................................................1783
Figure 14-68. D2H_BUF14 Register......................................................................................................................................1784
Figure 14-69. D2H_BUF15 Register......................................................................................................................................1785
Figure 15-1. Analog Subsystem Block Diagram (100-Pin QFP)............................................................................................1791
Figure 15-2. Analog Subsystem Block Diagram (80-Pin QFP)..............................................................................................1792
Figure 15-3. Analog Subsystem Block Diagram (64-Pin QFP)..............................................................................................1793
Figure 15-4. Analog Subsystem Block Diagram (48-Pin QFP)..............................................................................................1794
Figure 15-5. Analog Group Connections............................................................................................................................... 1795
Figure 15-6. CONFIGLOCK Register.................................................................................................................................... 1803
Figure 15-7. TSNSCTL Register............................................................................................................................................1804
Figure 15-8. ANAREFCTL Register.......................................................................................................................................1805
Figure 15-9. VMONCTL Register.......................................................................................................................................... 1806
Figure 15-10. CMPHPMXSEL Register.................................................................................................................................1807
Figure 15-11. CMPLPMXSEL Register..................................................................................................................................1808
Figure 15-12. CMPHNMXSEL Register.................................................................................................................................1809
Figure 15-13. CMPLNMXSEL Register................................................................................................................................. 1810
Figure 15-14. ADCDACLOOPBACK Register....................................................................................................................... 1811
Figure 15-15. LOCK Register................................................................................................................................................ 1812
Figure 15-16. AGPIOCTRLA Register...................................................................................................................................1814
Figure 16-1. ADC Module Block Diagram..............................................................................................................................1820
Figure 16-2. SOC Block Diagram.......................................................................................................................................... 1824
Figure 16-3. Single-Ended Input Model................................................................................................................................. 1825
Figure 16-4. Round Robin Priority Example.......................................................................................................................... 1830
Figure 16-5. High Priority Example........................................................................................................................................1831
Figure 16-6. Burst Priority Example.......................................................................................................................................1833
Figure 16-7. ADC EOC Interrupts..........................................................................................................................................1834
Figure 16-8. ADC PPB Block Diagram.................................................................................................................................. 1837
Figure 16-9. ADC PPB Interrupt Event.................................................................................................................................. 1839
Figure 16-10. Opens/Shorts Detection Circuit....................................................................................................................... 1841
Figure 16-11. Input Circuit Equivalent with OSDETECT Enabled..........................................................................................1842

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Figure 16-12. ADC Timings for 12-bit Mode in Early Interrupt Mode.....................................................................................1845
Figure 16-13. ADC Timings for 12-bit Mode in Late Interrupt Mode...................................................................................... 1846
Figure 16-14. Example: Basic Synchronous Operation.........................................................................................................1847
Figure 16-15. Example: Synchronous Operation with Multiple Trigger Sources................................................................... 1848
Figure 16-16. Example: Synchronous Operation with Uneven SOC Numbers..................................................................... 1849
Figure 16-17. Example: Asynchronous Operation with Uneven SOC Numbers – Trigger Overflow..................................... 1849
Figure 16-18. Example: Synchronous Equivalent Operation with Non-Overlapping Conversions........................................ 1850
Figure 16-19. ADC Reference System.................................................................................................................................. 1853
Figure 16-20. CMPSS to ADC Loopback Connection........................................................................................................... 1853
Figure 16-21. ADCRESULT0 Register...................................................................................................................................1863
Figure 16-22. ADCRESULT1 Register...................................................................................................................................1864
Figure 16-23. ADCRESULT2 Register...................................................................................................................................1865
Figure 16-24. ADCRESULT3 Register...................................................................................................................................1866
Figure 16-25. ADCRESULT4 Register...................................................................................................................................1867
Figure 16-26. ADCRESULT5 Register...................................................................................................................................1868
Figure 16-27. ADCRESULT6 Register...................................................................................................................................1869
Figure 16-28. ADCRESULT7 Register...................................................................................................................................1870
Figure 16-29. ADCRESULT8 Register...................................................................................................................................1871
Figure 16-30. ADCRESULT9 Register...................................................................................................................................1872
Figure 16-31. ADCRESULT10 Register.................................................................................................................................1873
Figure 16-32. ADCRESULT11 Register.................................................................................................................................1874
Figure 16-33. ADCRESULT12 Register.................................................................................................................................1875
Figure 16-34. ADCRESULT13 Register.................................................................................................................................1876
Figure 16-35. ADCRESULT14 Register.................................................................................................................................1877
Figure 16-36. ADCRESULT15 Register.................................................................................................................................1878
Figure 16-37. ADCPPB1RESULT Register........................................................................................................................... 1879
Figure 16-38. ADCPPB2RESULT Register........................................................................................................................... 1880
Figure 16-39. ADCPPB3RESULT Register........................................................................................................................... 1881
Figure 16-40. ADCPPB4RESULT Register........................................................................................................................... 1882
Figure 16-41. ADCCTL1 Register..........................................................................................................................................1886
Figure 16-42. ADCCTL2 Register..........................................................................................................................................1888
Figure 16-43. ADCBURSTCTL Register............................................................................................................................... 1889
Figure 16-44. ADCINTFLG Register......................................................................................................................................1891
Figure 16-45. ADCINTFLGCLR Register.............................................................................................................................. 1893
Figure 16-46. ADCINTOVF Register..................................................................................................................................... 1894
Figure 16-47. ADCINTOVFCLR Register.............................................................................................................................. 1895
Figure 16-48. ADCINTSEL1N2 Register............................................................................................................................... 1896
Figure 16-49. ADCINTSEL3N4 Register............................................................................................................................... 1898
Figure 16-50. ADCSOCPRICTL Register..............................................................................................................................1900
Figure 16-51. ADCINTSOCSEL1 Register............................................................................................................................ 1902
Figure 16-52. ADCINTSOCSEL2 Register............................................................................................................................ 1904
Figure 16-53. ADCSOCFLG1 Register..................................................................................................................................1906
Figure 16-54. ADCSOCFRC1 Register................................................................................................................................. 1910
Figure 16-55. ADCSOCOVF1 Register................................................................................................................................. 1915
Figure 16-56. ADCSOCOVFCLR1 Register.......................................................................................................................... 1918
Figure 16-57. ADCSOC0CTL Register..................................................................................................................................1921
Figure 16-58. ADCSOC1CTL Register..................................................................................................................................1923
Figure 16-59. ADCSOC2CTL Register..................................................................................................................................1925
Figure 16-60. ADCSOC3CTL Register..................................................................................................................................1927
Figure 16-61. ADCSOC4CTL Register..................................................................................................................................1929
Figure 16-62. ADCSOC5CTL Register..................................................................................................................................1931
Figure 16-63. ADCSOC6CTL Register..................................................................................................................................1933
Figure 16-64. ADCSOC7CTL Register..................................................................................................................................1935
Figure 16-65. ADCSOC8CTL Register..................................................................................................................................1937
Figure 16-66. ADCSOC9CTL Register..................................................................................................................................1939
Figure 16-67. ADCSOC10CTL Register................................................................................................................................1941
Figure 16-68. ADCSOC11CTL Register................................................................................................................................ 1943
Figure 16-69. ADCSOC12CTL Register................................................................................................................................1945
Figure 16-70. ADCSOC13CTL Register................................................................................................................................1947
Figure 16-71. ADCSOC14CTL Register................................................................................................................................1949
Figure 16-72. ADCSOC15CTL Register................................................................................................................................1951

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Figure 16-73. ADCEVTSTAT Register...................................................................................................................................1953

Figure 16-74. ADCEVTCLR Register.................................................................................................................................... 1956
Figure 16-75. ADCEVTSEL Register.....................................................................................................................................1958
Figure 16-76. ADCEVTINTSEL Register...............................................................................................................................1960
Figure 16-77. ADCOSDETECT Register...............................................................................................................................1962
Figure 16-78. ADCCOUNTER Register.................................................................................................................................1963
Figure 16-79. ADCREV Register........................................................................................................................................... 1964
Figure 16-80. ADCOFFTRIM Register.................................................................................................................................. 1965
Figure 16-81. ADCPPB1CONFIG Register........................................................................................................................... 1966
Figure 16-82. ADCPPB1STAMP Register............................................................................................................................. 1968
Figure 16-83. ADCPPB1OFFCAL Register........................................................................................................................... 1969
Figure 16-84. ADCPPB1OFFREF Register...........................................................................................................................1970
Figure 16-85. ADCPPB1TRIPHI Register............................................................................................................................. 1971
Figure 16-86. ADCPPB1TRIPLO Register............................................................................................................................ 1972
Figure 16-87. ADCPPB2CONFIG Register........................................................................................................................... 1973
Figure 16-88. ADCPPB2STAMP Register............................................................................................................................. 1975
Figure 16-89. ADCPPB2OFFCAL Register........................................................................................................................... 1976
Figure 16-90. ADCPPB2OFFREF Register...........................................................................................................................1977
Figure 16-91. ADCPPB2TRIPHI Register............................................................................................................................. 1978
Figure 16-92. ADCPPB2TRIPLO Register............................................................................................................................ 1979
Figure 16-93. ADCPPB3CONFIG Register........................................................................................................................... 1980
Figure 16-94. ADCPPB3STAMP Register............................................................................................................................. 1982
Figure 16-95. ADCPPB3OFFCAL Register........................................................................................................................... 1983
Figure 16-96. ADCPPB3OFFREF Register...........................................................................................................................1984
Figure 16-97. ADCPPB3TRIPHI Register............................................................................................................................. 1985
Figure 16-98. ADCPPB3TRIPLO Register............................................................................................................................ 1986
Figure 16-99. ADCPPB4CONFIG Register........................................................................................................................... 1987
Figure 16-100. ADCPPB4STAMP Register........................................................................................................................... 1989
Figure 16-101. ADCPPB4OFFCAL Register......................................................................................................................... 1990
Figure 16-102. ADCPPB4OFFREF Register.........................................................................................................................1991
Figure 16-103. ADCPPB4TRIPHI Register........................................................................................................................... 1992
Figure 16-104. ADCPPB4TRIPLO Register.......................................................................................................................... 1993
Figure 16-105. ADCINTCYCLE Register...............................................................................................................................1994
Figure 16-106. ADCINLTRIM2 Register................................................................................................................................ 1995
Figure 16-107. ADCINLTRIM3 Register................................................................................................................................ 1996
Figure 17-1. DAC Module Block Diagram..............................................................................................................................2003
Figure 17-2. DACREV Register............................................................................................................................................. 2008
Figure 17-3. DACCTL Register..............................................................................................................................................2009
Figure 17-4. DACVALA Register............................................................................................................................................2010
Figure 17-5. DACVALS Register............................................................................................................................................2011
Figure 17-6. DACOUTEN Register........................................................................................................................................2012
Figure 17-7. DACLOCK Register...........................................................................................................................................2013
Figure 17-8. DACTRIM Register............................................................................................................................................2014
Figure 18-1. CMPSS Module Block Diagram........................................................................................................................ 2019
Figure 18-2. Comparator Block Diagram............................................................................................................................... 2019
Figure 18-3. Reference DAC Block Diagram.........................................................................................................................2020
Figure 18-4. Ramp Generator Block Diagram....................................................................................................................... 2022
Figure 18-5. Ramp Generator Behavior................................................................................................................................ 2023
Figure 18-6. Digital Filter Behavior........................................................................................................................................ 2024
Figure 18-7. COMPCTL Register.......................................................................................................................................... 2031
Figure 18-8. COMPHYSCTL Register................................................................................................................................... 2033
Figure 18-9. COMPSTS Register.......................................................................................................................................... 2034
Figure 18-10. COMPSTSCLR Register................................................................................................................................. 2035
Figure 18-11. COMPDACCTL Register................................................................................................................................. 2036
Figure 18-12. DACHVALS Register....................................................................................................................................... 2038
Figure 18-13. DACHVALA Register....................................................................................................................................... 2039
Figure 18-14. RAMPMAXREFA Register.............................................................................................................................. 2040
Figure 18-15. RAMPMAXREFS Register.............................................................................................................................. 2041
Figure 18-16. RAMPDECVALA Register............................................................................................................................... 2042
Figure 18-17. RAMPDECVALS Register............................................................................................................................... 2043
Figure 18-18. RAMPSTS Register.........................................................................................................................................2044

36 TMS320F28003x Real-Time Microcontrollers SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023

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Figure 18-19. DACLVALS Register........................................................................................................................................2045

Figure 18-20. DACLVALA Register........................................................................................................................................2046
Figure 18-21. RAMPDLYA Register.......................................................................................................................................2047
Figure 18-22. RAMPDLYS Register.......................................................................................................................................2048
Figure 18-23. CTRIPLFILCTL Register................................................................................................................................. 2049
Figure 18-24. CTRIPLFILCLKCTL Register.......................................................................................................................... 2050
Figure 18-25. CTRIPHFILCTL Register.................................................................................................................................2051
Figure 18-26. CTRIPHFILCLKCTL Register..........................................................................................................................2052
Figure 18-27. COMPLOCK Register..................................................................................................................................... 2053
Figure 19-1. Sigma Delta Filter Module (SDFM) CPU Interface............................................................................................2058
Figure 19-2. Sigma Delta Filter Module (SDFM) Block Diagram........................................................................................... 2060
Figure 19-3. Block Diagram of One Filter Module................................................................................................................. 2061
Figure 19-4. Input Qualification on SD-Cx and SD-Dx.......................................................................................................... 2063
Figure 19-5. Different Modulator Modes Supported...............................................................................................................2064
Figure 19-6. SDFM Clock Control..........................................................................................................................................2065
Figure 19-7. Simplified Sinc Filter Architecture......................................................................................................................2065
Figure 19-8. Z-Transform of Sinc Filter of Order N................................................................................................................ 2066
Figure 19-9. Frequency Response of Different Sinc Filters................................................................................................... 2066
Figure 19-10. SDSYNC Event............................................................................................................................................... 2070
Figure 19-11. Comparator Unit Structure...............................................................................................................................2073
Figure 19-12. Digital Filter..................................................................................................................................................... 2075
Figure 19-13. SDFM Error (SD_ERR) Interrupt Sources.......................................................................................................2078
Figure 19-14. SDFM Data Ready (SDy_DRINTx) Interrupt...................................................................................................2079
Figure 19-15. SDIFLG Register............................................................................................................................................. 2088
Figure 19-16. SDIFLGCLR Register......................................................................................................................................2091
Figure 19-17. SDCTL Register.............................................................................................................................................. 2093
Figure 19-18. SDMFILEN Register........................................................................................................................................2094
Figure 19-19. SDSTATUS Register....................................................................................................................................... 2095
Figure 19-20. SDCTLPARM1 Register.................................................................................................................................. 2096
Figure 19-21. SDDFPARM1 Register.................................................................................................................................... 2097
Figure 19-22. SDDPARM1 Register...................................................................................................................................... 2098
Figure 19-23. SDFLT1CMPH1 Register................................................................................................................................ 2099
Figure 19-24. SDFLT1CMPL1 Register................................................................................................................................. 2100
Figure 19-25. SDCPARM1 Register...................................................................................................................................... 2101
Figure 19-26. SDDATA1 Register.......................................................................................................................................... 2103
Figure 19-27. SDDATFIFO1 Register.................................................................................................................................... 2104
Figure 19-28. SDCDATA1 Register....................................................................................................................................... 2105
Figure 19-29. SDFLT1CMPH2 Register................................................................................................................................ 2106
Figure 19-30. SDFLT1CMPHZ Register................................................................................................................................ 2107
Figure 19-31. SDFIFOCTL1 Register.................................................................................................................................... 2108
Figure 19-32. SDSYNC1 Register......................................................................................................................................... 2109
Figure 19-33. SDFLT1CMPL2 Register................................................................................................................................. 2110
Figure 19-34. SDCTLPARM2 Register...................................................................................................................................2111
Figure 19-35. SDDFPARM2 Register.................................................................................................................................... 2112
Figure 19-36. SDDPARM2 Register.......................................................................................................................................2113
Figure 19-37. SDFLT2CMPH1 Register.................................................................................................................................2114
Figure 19-38. SDFLT2CMPL1 Register................................................................................................................................. 2115
Figure 19-39. SDCPARM2 Register.......................................................................................................................................2116
Figure 19-40. SDDATA2 Register.......................................................................................................................................... 2118
Figure 19-41. SDDATFIFO2 Register.................................................................................................................................... 2119
Figure 19-42. SDCDATA2 Register....................................................................................................................................... 2120
Figure 19-43. SDFLT2CMPH2 Register................................................................................................................................ 2121
Figure 19-44. SDFLT2CMPHZ Register................................................................................................................................ 2122
Figure 19-45. SDFIFOCTL2 Register.................................................................................................................................... 2123
Figure 19-46. SDSYNC2 Register......................................................................................................................................... 2124
Figure 19-47. SDFLT2CMPL2 Register................................................................................................................................. 2125
Figure 19-48. SDCTLPARM3 Register.................................................................................................................................. 2126
Figure 19-49. SDDFPARM3 Register.................................................................................................................................... 2127
Figure 19-50. SDDPARM3 Register...................................................................................................................................... 2128
Figure 19-51. SDFLT3CMPH1 Register................................................................................................................................ 2129
Figure 19-52. SDFLT3CMPL1 Register................................................................................................................................. 2130

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Figure 19-53. SDCPARM3 Register...................................................................................................................................... 2131

Figure 19-54. SDDATA3 Register.......................................................................................................................................... 2133
Figure 19-55. SDDATFIFO3 Register.................................................................................................................................... 2134
Figure 19-56. SDCDATA3 Register....................................................................................................................................... 2135
Figure 19-57. SDFLT3CMPH2 Register................................................................................................................................ 2136
Figure 19-58. SDFLT3CMPHZ Register................................................................................................................................ 2137
Figure 19-59. SDFIFOCTL3 Register.................................................................................................................................... 2138
Figure 19-60. SDSYNC3 Register......................................................................................................................................... 2139
Figure 19-61. SDFLT3CMPL2 Register................................................................................................................................. 2140
Figure 19-62. SDCTLPARM4 Register.................................................................................................................................. 2141
Figure 19-63. SDDFPARM4 Register.................................................................................................................................... 2142
Figure 19-64. SDDPARM4 Register...................................................................................................................................... 2143
Figure 19-65. SDFLT4CMPH1 Register................................................................................................................................ 2144
Figure 19-66. SDFLT4CMPL1 Register................................................................................................................................. 2145
Figure 19-67. SDCPARM4 Register...................................................................................................................................... 2146
Figure 19-68. SDDATA4 Register.......................................................................................................................................... 2148
Figure 19-69. SDDATFIFO4 Register.................................................................................................................................... 2149
Figure 19-70. SDCDATA4 Register....................................................................................................................................... 2150
Figure 19-71. SDFLT4CMPH2 Register................................................................................................................................ 2151
Figure 19-72. SDFLT4CMPHZ Register................................................................................................................................ 2152
Figure 19-73. SDFIFOCTL4 Register.................................................................................................................................... 2153
Figure 19-74. SDSYNC4 Register......................................................................................................................................... 2154
Figure 19-75. SDFLT4CMPL2 Register................................................................................................................................. 2155
Figure 19-76. SDCOMP1CTL Register................................................................................................................................. 2156
Figure 19-77. SDCOMP1EVT2FLTCTL Register.................................................................................................................. 2157
Figure 19-78. SDCOMP1EVT2FLTCLKCTL Register........................................................................................................... 2158
Figure 19-79. SDCOMP1EVT1FLTCTL Register.................................................................................................................. 2159
Figure 19-80. SDCOMP1EVT1FLTCLKCTL Register........................................................................................................... 2160
Figure 19-81. SDCOMP1LOCK Register.............................................................................................................................. 2161
Figure 19-82. SDCOMP2CTL Register................................................................................................................................. 2162
Figure 19-83. SDCOMP2EVT2FLTCTL Register.................................................................................................................. 2163
Figure 19-84. SDCOMP2EVT2FLTCLKCTL Register........................................................................................................... 2164
Figure 19-85. SDCOMP2EVT1FLTCTL Register.................................................................................................................. 2165
Figure 19-86. SDCOMP2EVT1FLTCLKCTL Register........................................................................................................... 2166
Figure 19-87. SDCOMP2LOCK Register.............................................................................................................................. 2167
Figure 19-88. SDCOMP3CTL Register................................................................................................................................. 2168
Figure 19-89. SDCOMP3EVT2FLTCTL Register.................................................................................................................. 2169
Figure 19-90. SDCOMP3EVT2FLTCLKCTL Register........................................................................................................... 2170
Figure 19-91. SDCOMP3EVT1FLTCTL Register.................................................................................................................. 2171
Figure 19-92. SDCOMP3EVT1FLTCLKCTL Register........................................................................................................... 2172
Figure 19-93. SDCOMP3LOCK Register.............................................................................................................................. 2173
Figure 19-94. SDCOMP4CTL Register................................................................................................................................. 2174
Figure 19-95. SDCOMP4EVT2FLTCTL Register.................................................................................................................. 2175
Figure 19-96. SDCOMP4EVT2FLTCLKCTL Register........................................................................................................... 2176
Figure 19-97. SDCOMP4EVT1FLTCTL Register.................................................................................................................. 2177
Figure 19-98. SDCOMP4EVT1FLTCLKCTL Register........................................................................................................... 2178
Figure 19-99. SDCOMP4LOCK Register.............................................................................................................................. 2179
Figure 20-1. Multiple ePWM Modules....................................................................................................................................2189
Figure 20-2. Submodules and Signal Connections for an ePWM Module.............................................................................2190
Figure 20-3. ePWM Modules and Critical Internal Signal Interconnects............................................................................... 2192
Figure 20-4. Time-Base Submodule...................................................................................................................................... 2195
Figure 20-5. Time-Base Submodule Signals and Registers.................................................................................................. 2196
Figure 20-6. Time-Base Frequency and Period.....................................................................................................................2198
Figure 20-7. Time-Base Counter Synchronization Scheme...................................................................................................2200
Figure 20-8. ePWM External SYNC Output...........................................................................................................................2201
Figure 20-9. Time-Base Up-Count Mode Waveforms............................................................................................................2205
Figure 20-10. Time-Base Down-Count Mode Waveforms..................................................................................................... 2206
Figure 20-11. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event....... 2206
Figure 20-12. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event............2207
Figure 20-13. Global Load: Signals and Registers................................................................................................................ 2208
Figure 20-14. One-Shot Sync Mode...................................................................................................................................... 2209

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Figure 20-15. Counter-Compare Submodule........................................................................................................................ 2210

Figure 20-16. Detailed View of the Counter-Compare Submodule........................................................................................2211
Figure 20-17. Counter-Compare Event Waveforms in Up-Count Mode................................................................................ 2214
Figure 20-18. Counter-Compare Events in Down-Count Mode.............................................................................................2214
Figure 20-19. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event....................................................................................................................................................... 2215
Figure 20-20. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event.................................................................................................................................................................................. 2215
Figure 20-21. Action-Qualifier Submodule.............................................................................................................................2216
Figure 20-22. Action-Qualifier Submodule Inputs and Outputs............................................................................................. 2217
Figure 20-23. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs..........................................................2218
Figure 20-24. AQCTL[SHDWAQAMODE]............................................................................................................................. 2221
Figure 20-25. AQCTL[SHDWAQBMODE]............................................................................................................................. 2221
Figure 20-26. Up-Down Count Mode Symmetrical Waveform...............................................................................................2223
Figure 20-27. Up, Single Edge Asymmetric Waveform, with Independent Modulation on EPWMxA and EPWMxB—
Active High......................................................................................................................................................................... 2224
Figure 20-28. Up, Single Edge Asymmetric Waveform with Independent Modulation on EPWMxA and EPWMxB—
Active Low..........................................................................................................................................................................2225
Figure 20-29. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA..................2226
Figure 20-30. Up-Down Count, Dual-Edge Symmetric Waveform, with Independent Modulation on EPWMxA and
EPWMxB — Active Low.....................................................................................................................................................2226
Figure 20-31. Up-Down Count, Dual-Edge Symmetric Waveform, with Independent Modulation on EPWMxA and
EPWMxB — Complementary.............................................................................................................................................2227
Figure 20-32. Up-Down Count, Dual-Edge Asymmetric Waveform, with Independent Modulation on EPWMxA—Active
Low.....................................................................................................................................................................................2227
Figure 20-33. Up-Down Count, PWM Waveform Generation Utilizing T1 and T2 Events..................................................... 2228
Figure 20-34. Dead_Band Submodule.................................................................................................................................. 2229
Figure 20-35. Configuration Options for the Dead-Band Submodule.................................................................................... 2232
Figure 20-36. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)..................................................................... 2234
Figure 20-37. PWM Chopper Submodule..............................................................................................................................2236
Figure 20-38. PWM Chopper Submodule Operational Details.............................................................................................. 2237
Figure 20-39. Simple PWM Chopper Submodule Waveforms Showing Chopping Action Only............................................ 2237
Figure 20-40. PWM Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses........... 2238
Figure 20-41. PWM Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses 2239
Figure 20-42. Trip-Zone Submodule......................................................................................................................................2240
Figure 20-43. Trip-Zone Submodule Mode Control Logic......................................................................................................2244
Figure 20-44. Trip-Zone Submodule Interrupt Logic..............................................................................................................2245
Figure 20-45. Event-Trigger Submodule................................................................................................................................2246
Figure 20-46. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs...................................................... 2247
Figure 20-47. Event-Trigger Interrupt Generator................................................................................................................... 2249
Figure 20-48. Event-Trigger SOCA Pulse Generator............................................................................................................ 2250
Figure 20-49. Event-Trigger SOCB Pulse Generator............................................................................................................ 2250
Figure 20-50. Digital-Compare Submodule High-Level Block Diagram.................................................................................2251
Figure 20-51. GPIO MUX-to-Trip Input Connectivity............................................................................................................. 2252
Figure 20-52. DCxEVT1 Event Triggering............................................................................................................................. 2255
Figure 20-53. DCxEVT2 Event Triggering............................................................................................................................. 2256
Figure 20-54. Event Filtering................................................................................................................................................. 2256
Figure 20-55. Blanking Window Timing Diagram...................................................................................................................2257
Figure 20-56. Valley Switching...............................................................................................................................................2259
Figure 20-57. ePWM X-BAR..................................................................................................................................................2260
Figure 20-58. Simplified ePWM Module................................................................................................................................ 2261
Figure 20-59. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave .................................................... 2262
Figure 20-60. Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 ............................................................. 2263
Figure 20-61. Buck Waveforms for Control of Four Buck Stages (Note: Only three bucks shown here).............................. 2264
Figure 20-62. Control of Four Buck Stages. (Note: FPWM2 = N x FPWM1).............................................................................. 2265
Figure 20-63. Buck Waveforms for Control of Four Buck Stages (Note: FPWM2 = FPWM1).................................................... 2266
Figure 20-64. Control of Two Half-H Bridge Stages (FPWM2 = N x FPWM1)............................................................................ 2267
Figure 20-65. Half-H Bridge Waveforms for Control of Two Half-H Bridge Stages (Note: Here FPWM2 = FPWM1)................. 2268
Figure 20-66. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control..........................................2269
Figure 20-67. 3-Phase Inverter Waveforms for Control of Dual 3-Phase Inverter Stages (Only One Inverter Shown)......... 2270
Figure 20-68. Configuring Two PWM Modules for Phase Control......................................................................................... 2271

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Figure 20-69. Timing Waveforms Associated with Phase Control Between Two Modules....................................................2272
Figure 20-70. Control of 3-Phase Interleaved DC/DC Converter.......................................................................................... 2273
Figure 20-71. 3-Phase Interleaved DC/DC Converter Waveforms for Control of 3-Phase Interleaved DC/DC Converter....2274
Figure 20-72. Control of Full-H Bridge Stage (FPWM2 = FPWM1)............................................................................................ 2275
Figure 20-73. ZVS Full-H Bridge Waveforms........................................................................................................................ 2276
Figure 20-74. Peak Current Mode Control of Buck Converter...............................................................................................2277
Figure 20-75. Peak Current Mode Control Waveforms for Control of Buck Converter.......................................................... 2277
Figure 20-76. Control of Two Resonant Converter Stages....................................................................................................2278
Figure 20-77. H-Bridge LLC Resonant Converter PWM Waveforms.....................................................................................2278
Figure 20-78. HRPWM Block Diagram.................................................................................................................................. 2280
Figure 20-79. Resolution Calculations for Conventionally Generated PWM......................................................................... 2281
Figure 20-80. Operating Logic Using MEP............................................................................................................................ 2282
Figure 20-81. HRPWM Extension Registers and Memory Configuration.............................................................................. 2283
Figure 20-82. HRPWM System Interface.............................................................................................................................. 2284
Figure 20-83. HRPWM and HRCAL Source Clock................................................................................................................2285
Figure 20-84. Required PWM Waveform for a Requested Duty = 40.5%..............................................................................2288
Figure 20-85. Low % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)............................................................ 2291
Figure 20-86. High % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)............................................................2292
Figure 20-87. Up-Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1)..........................................................2292
Figure 20-88. Up-Down Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1)................................................2292
Figure 20-89. Simple Buck Controlled Converter Using a Single PWM................................................................................ 2299
Figure 20-90. PWM Waveform Generated for Simple Buck Controlled Converter................................................................ 2299
Figure 20-91. Simple Reconstruction Filter for a PWM-based DAC......................................................................................2301
Figure 20-92. PWM Waveform Generated for the PWM DAC Function................................................................................ 2301
Figure 20-93. TBCTL Register...............................................................................................................................................2317
Figure 20-94. TBCTL2 Register.............................................................................................................................................2319
Figure 20-95. EPWMSYNCINSEL Register.......................................................................................................................... 2320
Figure 20-96. TBCTR Register.............................................................................................................................................. 2321
Figure 20-97. TBSTS Register.............................................................................................................................................. 2322
Figure 20-98. EPWMSYNCOUTEN Register........................................................................................................................ 2323
Figure 20-99. TBCTL3 Register.............................................................................................................................................2325
Figure 20-100. CMPCTL Register......................................................................................................................................... 2326
Figure 20-101. CMPCTL2 Register....................................................................................................................................... 2328
Figure 20-102. DBCTL Register............................................................................................................................................ 2330
Figure 20-103. DBCTL2 Register.......................................................................................................................................... 2333
Figure 20-104. AQCTL Register............................................................................................................................................ 2334
Figure 20-105. AQTSRCSEL Register.................................................................................................................................. 2336
Figure 20-106. PCCTL Register............................................................................................................................................ 2337
Figure 20-107. VCAPCTL Register....................................................................................................................................... 2338
Figure 20-108. VCNTCFG Register.......................................................................................................................................2340
Figure 20-109. HRCNFG Register.........................................................................................................................................2342
Figure 20-110. HRPWR Register...........................................................................................................................................2344
Figure 20-111. HRMSTEP Register....................................................................................................................................... 2345
Figure 20-112. HRCNFG2 Register....................................................................................................................................... 2346
Figure 20-113. HRPCTL Register.......................................................................................................................................... 2347
Figure 20-114. TRREM Register............................................................................................................................................2349
Figure 20-115. GLDCTL Register.......................................................................................................................................... 2350
Figure 20-116. GLDCFG Register......................................................................................................................................... 2352
Figure 20-117. EPWMXLINK Register...................................................................................................................................2354
Figure 20-118. AQCTLA Register.......................................................................................................................................... 2356
Figure 20-119. AQCTLA2 Register........................................................................................................................................ 2358
Figure 20-120. AQCTLB Register..........................................................................................................................................2359
Figure 20-121. AQCTLB2 Register........................................................................................................................................2361
Figure 20-122. AQSFRC Register......................................................................................................................................... 2362
Figure 20-123. AQCSFRC Register...................................................................................................................................... 2363
Figure 20-124. DBREDHR Register...................................................................................................................................... 2364
Figure 20-125. DBRED Register........................................................................................................................................... 2365
Figure 20-126. DBFEDHR Register.......................................................................................................................................2366
Figure 20-127. DBFED Register............................................................................................................................................2367
Figure 20-128. TBPHS Register............................................................................................................................................ 2368
Figure 20-129. TBPRDHR Register.......................................................................................................................................2369

40 TMS320F28003x Real-Time Microcontrollers SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023

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Figure 20-130. TBPRD Register............................................................................................................................................2370

Figure 20-131. CMPA Register.............................................................................................................................................. 2371
Figure 20-132. CMPB Register..............................................................................................................................................2372
Figure 20-133. CMPC Register............................................................................................................................................. 2373
Figure 20-134. CMPD Register............................................................................................................................................. 2374
Figure 20-135. GLDCTL2 Register........................................................................................................................................2375
Figure 20-136. SWVDELVAL Register...................................................................................................................................2376
Figure 20-137. TZSEL Register.............................................................................................................................................2377
Figure 20-138. TZDCSEL Register........................................................................................................................................2379
Figure 20-139. TZCTL Register.............................................................................................................................................2380
Figure 20-140. TZCTL2 Register...........................................................................................................................................2381
Figure 20-141. TZCTLDCA Register..................................................................................................................................... 2383
Figure 20-142. TZCTLDCB Register..................................................................................................................................... 2385
Figure 20-143. TZEINT Register........................................................................................................................................... 2387
Figure 20-144. TZFLG Register.............................................................................................................................................2388
Figure 20-145. TZCBCFLG Register..................................................................................................................................... 2390
Figure 20-146. TZOSTFLG Register..................................................................................................................................... 2391
Figure 20-147. TZCLR Register............................................................................................................................................ 2392
Figure 20-148. TZCBCCLR Register.....................................................................................................................................2393
Figure 20-149. TZOSTCLR Register..................................................................................................................................... 2394
Figure 20-150. TZFRC Register............................................................................................................................................ 2395
Figure 20-151. ETSEL Register.............................................................................................................................................2396
Figure 20-152. ETPS Register...............................................................................................................................................2399
Figure 20-153. ETFLG Register............................................................................................................................................ 2402
Figure 20-154. ETCLR Register............................................................................................................................................ 2403
Figure 20-155. ETFRC Register............................................................................................................................................ 2404
Figure 20-156. ETINTPS Register.........................................................................................................................................2405
Figure 20-157. ETSOCPS Register.......................................................................................................................................2406
Figure 20-158. ETCNTINITCTL Register.............................................................................................................................. 2407
Figure 20-159. ETCNTINIT Register..................................................................................................................................... 2408
Figure 20-160. DCTRIPSEL Register....................................................................................................................................2409
Figure 20-161. DCACTL Register.......................................................................................................................................... 2411
Figure 20-162. DCBCTL Register..........................................................................................................................................2413
Figure 20-163. DCFCTL Register..........................................................................................................................................2415
Figure 20-164. DCCAPCTL Register.....................................................................................................................................2417
Figure 20-165. DCFOFFSET Register.................................................................................................................................. 2419
Figure 20-166. DCFOFFSETCNT Register........................................................................................................................... 2420
Figure 20-167. DCFWINDOW Register.................................................................................................................................2421
Figure 20-168. DCFWINDOWCNT Register..........................................................................................................................2422
Figure 20-169. BLANKPULSEMIXSEL Register................................................................................................................... 2423
Figure 20-170. DCCAP Register........................................................................................................................................... 2425
Figure 20-171. DCAHTRIPSEL Register...............................................................................................................................2426
Figure 20-172. DCALTRIPSEL Register................................................................................................................................2428
Figure 20-173. DCBHTRIPSEL Register...............................................................................................................................2430
Figure 20-174. DCBLTRIPSEL Register................................................................................................................................2432
Figure 20-175. EPWMLOCK Register................................................................................................................................... 2434
Figure 20-176. HWVDELVAL Register.................................................................................................................................. 2435
Figure 20-177. VCNTVAL Register........................................................................................................................................2436
Figure 21-1. Capture and APWM Modes of Operation..........................................................................................................2455
Figure 21-2. Counter Compare and PRD Effects on the eCAP Output in APWM Mode....................................................... 2456
Figure 21-3. eCAP Block Diagram.........................................................................................................................................2457
Figure 21-4. Event Prescale Control......................................................................................................................................2458
Figure 21-5. Prescale Function Waveforms...........................................................................................................................2458
Figure 21-6. Details of the Continuous/One-shot Block.........................................................................................................2459
Figure 21-7. Details of the Counter and Synchronization Block............................................................................................ 2461
Figure 21-8. eCAP Synchronization Scheme........................................................................................................................ 2461
Figure 21-9. Interrupts in eCAP Module................................................................................................................................ 2463
Figure 21-10. PWM Waveform Details Of APWM Mode Operation.......................................................................................2464
Figure 21-11. Time-Base Frequency and Period Calculation................................................................................................ 2465
Figure 21-12. Capture Sequence for Absolute Time-stamp and Rising-Edge Detect........................................................... 2466
Figure 21-13. Capture Sequence for Absolute Time-stamp with Rising- and Falling-Edge Detect....................................... 2467

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Figure 21-14. Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect....................................................... 2468
Figure 21-15. Capture Sequence for Delta Mode Time-stamp with Rising- and Falling-Edge Detect...................................2469
Figure 21-16. PWM Waveform Details of APWM Mode Operation....................................................................................... 2470
Figure 21-17. TSCTR Register.............................................................................................................................................. 2475
Figure 21-18. CTRPHS Register........................................................................................................................................... 2476
Figure 21-19. CAP1 Register.................................................................................................................................................2477
Figure 21-20. CAP2 Register.................................................................................................................................................2478
Figure 21-21. CAP3 Register.................................................................................................................................................2479
Figure 21-22. CAP4 Register.................................................................................................................................................2480
Figure 21-23. ECCTL0 Register............................................................................................................................................ 2481
Figure 21-24. ECCTL1 Register............................................................................................................................................ 2482
Figure 21-25. ECCTL2 Register............................................................................................................................................ 2484
Figure 21-26. ECEINT Register.............................................................................................................................................2486
Figure 21-27. ECFLG Register.............................................................................................................................................. 2488
Figure 21-28. ECCLR Register..............................................................................................................................................2489
Figure 21-29. ECFRC Register..............................................................................................................................................2490
Figure 21-30. ECAPSYNCINSEL Register............................................................................................................................2491
Figure 22-1. HRCAP Operations Block Diagram...................................................................................................................2497
Figure 22-2. HRCAP Calibration............................................................................................................................................2498
Figure 22-3. HRCTL Register................................................................................................................................................ 2503
Figure 22-4. HRINTEN Register............................................................................................................................................ 2504
Figure 22-5. HRFLG Register................................................................................................................................................2505
Figure 22-6. HRCLR Register................................................................................................................................................2506
Figure 22-7. HRFRC Register............................................................................................................................................... 2507
Figure 22-8. HRCALPRD Register........................................................................................................................................ 2508
Figure 22-9. HRSYSCLKCTR Register................................................................................................................................. 2509
Figure 22-10. HRSYSCLKCAP Register............................................................................................................................... 2510
Figure 22-11. HRCLKCTR Register....................................................................................................................................... 2511
Figure 22-12. HRCLKCAP Register...................................................................................................................................... 2512
Figure 23-1. Optical Encoder Disk.........................................................................................................................................2516
Figure 23-2. QEP Encoder Output Signal for Forward/Reverse Movement.......................................................................... 2516
Figure 23-3. Index Pulse Example.........................................................................................................................................2517
Figure 23-4. Using eQEP to Decode Signals from SinCos Transducer.................................................................................2520
Figure 23-5. Functional Block Diagram of the eQEP Peripheral........................................................................................... 2522
Figure 23-6. Functional Block Diagram of Decoder Unit....................................................................................................... 2524
Figure 23-7. Quadrature Decoder State Machine..................................................................................................................2525
Figure 23-8. Quadrature-clock and Direction Decoding........................................................................................................ 2526
Figure 23-9. Position Counter Reset by Index Pulse for 1000-Line Encoder (QPOSMAX = 3999 or 0xF9F)....................... 2528
Figure 23-10. Position Counter Underflow/Overflow (QPOSMAX = 4)..................................................................................2529
Figure 23-11. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1)..................................................................2531
Figure 23-12. Strobe Event Latch (QEPCTL[SEL] = 1)......................................................................................................... 2531
Figure 23-13. Latching Position Counter on ADCSOCA/ADCSOCB event...........................................................................2532
Figure 23-14. eQEP Position-compare Unit.......................................................................................................................... 2533
Figure 23-15. eQEP Position-compare Event Generation Points..........................................................................................2534
Figure 23-16. eQEP Position-compare Sync Output Pulse Stretcher................................................................................... 2534
Figure 23-17. eQEP Edge Capture Unit................................................................................................................................ 2536
Figure 23-18. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)...............................................2537
Figure 23-19. eQEP Edge Capture Unit - Timing Details...................................................................................................... 2537
Figure 23-20. eQEP Watchdog Timer....................................................................................................................................2539
Figure 23-21. eQEP Unit Timer Base.................................................................................................................................... 2539
Figure 23-22. QMA Module Block Diagram........................................................................................................................... 2540
Figure 23-23. QMA Mode-1................................................................................................................................................... 2541
Figure 23-24. QMA Mode-2................................................................................................................................................... 2542
Figure 23-25. eQEP Interrupt Generation..............................................................................................................................2543
Figure 23-26. QPOSCNT Register........................................................................................................................................ 2550
Figure 23-27. QPOSINIT Register.........................................................................................................................................2551
Figure 23-28. QPOSMAX Register........................................................................................................................................2552
Figure 23-29. QPOSCMP Register........................................................................................................................................2553
Figure 23-30. QPOSILAT Register........................................................................................................................................ 2554
Figure 23-31. QPOSSLAT Register....................................................................................................................................... 2555
Figure 23-32. QPOSLAT Register......................................................................................................................................... 2556

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Figure 23-33. QUTMR Register.............................................................................................................................................2557

Figure 23-34. QUPRD Register............................................................................................................................................. 2558
Figure 23-35. QWDTMR Register......................................................................................................................................... 2559
Figure 23-36. QWDPRD Register..........................................................................................................................................2560
Figure 23-37. QDECCTL Register.........................................................................................................................................2561
Figure 23-38. QEPCTL Register............................................................................................................................................2563
Figure 23-39. QCAPCTL Register......................................................................................................................................... 2565
Figure 23-40. QPOSCTL Register.........................................................................................................................................2566
Figure 23-41. QEINT Register............................................................................................................................................... 2567
Figure 23-42. QFLG Register................................................................................................................................................ 2569
Figure 23-43. QCLR Register................................................................................................................................................ 2571
Figure 23-44. QFRC Register................................................................................................................................................2573
Figure 23-45. QEPSTS Register........................................................................................................................................... 2575
Figure 23-46. QCTMR Register.............................................................................................................................................2576
Figure 23-47. QCPRD Register............................................................................................................................................. 2577
Figure 23-48. QCTMRLAT Register.......................................................................................................................................2578
Figure 23-49. QCPRDLAT Register.......................................................................................................................................2579
Figure 23-50. REV Register...................................................................................................................................................2580
Figure 23-51. QEPSTROBESEL Register.............................................................................................................................2581
Figure 23-52. QMACTRL Register........................................................................................................................................ 2582
Figure 23-53. QEPSRCSEL Register.................................................................................................................................... 2583
Figure 24-1. SPI CPU Interface............................................................................................................................................. 2589
Figure 24-2. SPI Interrupt Flags and Enable Logic Generation.............................................................................................2592
Figure 24-3. SPI DMA Trigger Diagram.................................................................................................................................2593
Figure 24-4. SPI Master/Slave Connection........................................................................................................................... 2594
Figure 24-5. SPI Module Master Configuration..................................................................................................................... 2596
Figure 24-6. SPI Module Slave Configuration....................................................................................................................... 2597
Figure 24-7. SPICLK Signal Options..................................................................................................................................... 2600
Figure 24-8. SPI: SPICLK-LSPCLK Characteristic when (BRR + 1) is Odd, BRR > 3, and CLKPOLARITY = 1.................. 2601
Figure 24-9. Five Bits per Character......................................................................................................................................2604
Figure 24-10. SPICCR Register............................................................................................................................................ 2609
Figure 24-11. SPICTL Register.............................................................................................................................................. 2611
Figure 24-12. SPISTS Register............................................................................................................................................. 2613
Figure 24-13. SPIBRR Register.............................................................................................................................................2615
Figure 24-14. SPIRXEMU Register....................................................................................................................................... 2616
Figure 24-15. SPIRXBUF Register........................................................................................................................................ 2617
Figure 24-16. SPITXBUF Register........................................................................................................................................ 2618
Figure 24-17. SPIDAT Register............................................................................................................................................. 2619
Figure 24-18. SPIFFTX Register........................................................................................................................................... 2620
Figure 24-19. SPIFFRX Register...........................................................................................................................................2622
Figure 24-20. SPIFFCT Register........................................................................................................................................... 2624
Figure 24-21. SPIPRI Register.............................................................................................................................................. 2625
Figure 25-1. SCI CPU Interface.............................................................................................................................................2630
Figure 25-2. Serial Communications Interface (SCI) Module Block Diagram........................................................................2632
Figure 25-3. Typical SCI Data Frame Formats...................................................................................................................... 2634
Figure 25-4. Idle-Line Multiprocessor Communication Format..............................................................................................2636
Figure 25-5. Double-Buffered WUT and TXSHF................................................................................................................... 2637
Figure 25-6. Address-Bit Multiprocessor Communication Format......................................................................................... 2638
Figure 25-7. SCI Asynchronous Communications Format.................................................................................................... 2639
Figure 25-8. SCI RX Signals in Communication Modes........................................................................................................ 2639
Figure 25-9. SCI TX Signals in Communications Mode........................................................................................................ 2640
Figure 25-10. SCI FIFO Interrupt Flags and Enable Logic.................................................................................................... 2643
Figure 25-11. SCICCR Register.............................................................................................................................................2649
Figure 25-12. SCICTL1 Register........................................................................................................................................... 2651
Figure 25-13. SCIHBAUD Register....................................................................................................................................... 2653
Figure 25-14. SCILBAUD Register........................................................................................................................................ 2654
Figure 25-15. SCICTL2 Register........................................................................................................................................... 2655
Figure 25-16. SCIRXST Register.......................................................................................................................................... 2657
Figure 25-17. SCIRXEMU Register....................................................................................................................................... 2659
Figure 25-18. SCIRXBUF Register........................................................................................................................................2660
Figure 25-19. SCITXBUF Register........................................................................................................................................ 2661

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Figure 25-20. SCIFFTX Register........................................................................................................................................... 2662

Figure 25-21. SCIFFRX Register...........................................................................................................................................2664
Figure 25-22. SCIFFCT Register...........................................................................................................................................2666
Figure 25-23. SCIPRI Register.............................................................................................................................................. 2667
Figure 26-1. Multiple I2C Modules Connected...................................................................................................................... 2672
Figure 26-2. I2C Module Conceptual Block Diagram............................................................................................................ 2675
Figure 26-3. Clocking Diagram for the I2C Module............................................................................................................... 2675
Figure 26-4. Roles of the Clock Divide-Down Values (ICCL and ICCH)................................................................................2676
Figure 26-5. Bit Transfer on the I2C bus................................................................................................................................2677
Figure 26-6. I2C Slave TX / RX Flowchart.............................................................................................................................2679
Figure 26-7. I2C Master TX / RX Flowchart...........................................................................................................................2680
Figure 26-8. I2C Module START and STOP Conditions........................................................................................................2681
Figure 26-9. I2C Module Data Transfer (7-Bit Addressing with 8-bit Data Configuration Shown)......................................... 2682
Figure 26-10. I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR).............................................................. 2683
Figure 26-11. I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR).............................................................2683
Figure 26-12. I2C Module Free Data Format (FDF = 1 in I2CMDR)......................................................................................2684
Figure 26-13. Repeated START Condition (in This Case, 7-Bit Addressing Format)............................................................ 2684
Figure 26-14. Synchronization of Two I2C Clock Generators During Arbitration...................................................................2685
Figure 26-15. Arbitration Procedure Between Two Master-Transmitters...............................................................................2686
Figure 26-16. Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit.....................................................2687
Figure 26-17. Enable Paths of the I2C Interrupt Requests....................................................................................................2690
Figure 26-18. Backwards Compatibility Mode and Forward Compatibility Bit, Slave Transmitter......................................... 2691
Figure 26-19. I2C_FIFO_interrupt......................................................................................................................................... 2692
Figure 26-20. I2COAR Register.............................................................................................................................................2699
Figure 26-21. I2CIER Register.............................................................................................................................................. 2700
Figure 26-22. I2CSTR Register............................................................................................................................................. 2701
Figure 26-23. I2CCLKL Register........................................................................................................................................... 2705
Figure 26-24. I2CCLKH Register...........................................................................................................................................2706
Figure 26-25. I2CCNT Register............................................................................................................................................. 2707
Figure 26-26. I2CDRR Register.............................................................................................................................................2708
Figure 26-27. I2CSAR Register............................................................................................................................................. 2709
Figure 26-28. I2CDXR Register.............................................................................................................................................2710
Figure 26-29. I2CMDR Register.............................................................................................................................................2711
Figure 26-30. I2CISRC Register............................................................................................................................................2714
Figure 26-31. I2CEMDR Register..........................................................................................................................................2715
Figure 26-32. I2CPSC Register............................................................................................................................................. 2716
Figure 26-33. I2CFFTX Register........................................................................................................................................... 2717
Figure 26-34. I2CFFRX Register........................................................................................................................................... 2719
Figure 27-1. PMBus Module Block Diagram..........................................................................................................................2725
Figure 27-2. Quick Command Message................................................................................................................................ 2727
Figure 27-3. Send Byte Message With and Without PEC..................................................................................................... 2727
Figure 27-4. Receive Byte Message With and Without PEC.................................................................................................2728
Figure 27-5. Write Byte and Write Word Messages With and Without PEC..........................................................................2728
Figure 27-6. Read Byte and Read Word Messages With and Without PEC......................................................................... 2729
Figure 27-7. Process Call Message With and Without PEC..................................................................................................2730
Figure 27-8. Block Write Message With and Without PEC.................................................................................................... 2730
Figure 27-9. Block Read Message With and Without PEC....................................................................................................2731
Figure 27-10. Block Write-Block Read Process Call Message With and Without PEC......................................................... 2732
Figure 27-11. Alert Response Message.................................................................................................................................2732
Figure 27-12. Extended Command Write Byte and Write Word Messages With and Without PEC...................................... 2733
Figure 27-13. Extended Command Read Byte and Read Word Messages With and Without PEC......................................2734
Figure 27-14. Group Command Message With and Without PEC........................................................................................ 2735
Figure 27-15. Quick Command Message.............................................................................................................................. 2736
Figure 27-16. Send Byte Message With and Without PEC................................................................................................... 2737
Figure 27-17. Receive Byte Message With and Without PEC...............................................................................................2737
Figure 27-18. Write Byte and Write Word Messages With and Without PEC........................................................................2738
Figure 27-19. Read Byte and Read Word Messages With and Without PEC....................................................................... 2739
Figure 27-20. Process Call Message With and Without PEC................................................................................................2740
Figure 27-21. Block Write Message With and Without PEC.................................................................................................. 2741
Figure 27-22. Block Read Message With and Without PEC..................................................................................................2742
Figure 27-23. Block Write-Block Read Process Call Message With and Without PEC......................................................... 2743

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Figure 27-24. Alert Response Message................................................................................................................................ 2743

Figure 27-25. Extended Command Write Byte and Write Word Messages With and Without PEC...................................... 2744
Figure 27-26. Extended Command Read Byte and Read Word Messages With and Without PEC......................................2745
Figure 27-27. Group Command Message With and Without PEC........................................................................................ 2746
Figure 27-28. PMBMC Register.............................................................................................................................................2748
Figure 27-29. PMBTXBUF Register...................................................................................................................................... 2749
Figure 27-30. PMBRXBUF Register...................................................................................................................................... 2750
Figure 27-31. PMBACK Register...........................................................................................................................................2751
Figure 27-32. PMBSTS Register........................................................................................................................................... 2752
Figure 27-33. PMBINTM Register......................................................................................................................................... 2754
Figure 27-34. PMBSC Register............................................................................................................................................. 2756
Figure 27-35. PMBHSA Register...........................................................................................................................................2758
Figure 27-36. PMBCTRL Register.........................................................................................................................................2759
Figure 27-37. PMBTIMCTL Register..................................................................................................................................... 2761
Figure 27-38. PMBTIMCLK Register..................................................................................................................................... 2762
Figure 27-39. PMBTIMSTSETUP Register........................................................................................................................... 2763
Figure 27-40. PMBTIMBIDLE Register..................................................................................................................................2764
Figure 27-41. PMBTIMLOWTIMOUT Register...................................................................................................................... 2765
Figure 27-42. PMBTIMHIGHTIMOUT Register..................................................................................................................... 2766
Figure 28-1. CAN Block Diagram.......................................................................................................................................... 2771
Figure 28-2. CAN_MUX.........................................................................................................................................................2776
Figure 28-3. CAN Core in Silent Mode.................................................................................................................................. 2777
Figure 28-4. CAN Core in Loopback Mode............................................................................................................................2778
Figure 28-5. CAN Core in External Loopback Mode............................................................................................................. 2779
Figure 28-6. CAN Core in Loopback Combined with Silent Mode.........................................................................................2780
Figure 28-7. CAN Interrupt Topology 1.................................................................................................................................. 2782
Figure 28-8. CAN Interrupt Topology 2.................................................................................................................................. 2782
Figure 28-9. Initialization of a Transmit Object...................................................................................................................... 2785
Figure 28-10. Initialization of a Single Receive Object for Data Frames............................................................................... 2785
Figure 28-11. Initialization of a Single Receive Object for Remote Frames...........................................................................2786
Figure 28-12. CPU Handling of a FIFO Buffer (Interrupt Driven)...........................................................................................2791
Figure 28-13. Bit Timing.........................................................................................................................................................2792
Figure 28-14. Propagation Time Segment.............................................................................................................................2793
Figure 28-15. Synchronization on Late and Early Edges...................................................................................................... 2795
Figure 28-16. Filtering of Short Dominant Spikes..................................................................................................................2796
Figure 28-17. Structure of the CAN Core's CAN Protocol Controller.....................................................................................2798
Figure 28-18. Data Transfer Between IF1 / IF2 Registers and Message RAM..................................................................... 2802
Figure 28-19. Structure of a Message Object........................................................................................................................2803
Figure 28-20. Message RAM Representation in Debug Mode.............................................................................................. 2807
Figure 28-21. CAN_CTL Register..........................................................................................................................................2814
Figure 28-22. CAN_ES Register............................................................................................................................................2817
Figure 28-23. CAN_ERRC Register...................................................................................................................................... 2819
Figure 28-24. CAN_BTR Register......................................................................................................................................... 2820
Figure 28-25. CAN_INT Register...........................................................................................................................................2822
Figure 28-26. CAN_TEST Register....................................................................................................................................... 2823
Figure 28-27. CAN_PERR Register...................................................................................................................................... 2825
Figure 28-28. CAN_RAM_INIT Register................................................................................................................................2826
Figure 28-29. CAN_GLB_INT_EN Register.......................................................................................................................... 2827
Figure 28-30. CAN_GLB_INT_FLG Register........................................................................................................................ 2828
Figure 28-31. CAN_GLB_INT_CLR Register........................................................................................................................ 2829
Figure 28-32. CAN_ABOTR Register.................................................................................................................................... 2830
Figure 28-33. CAN_TXRQ_X Register.................................................................................................................................. 2831
Figure 28-34. CAN_TXRQ_21 Register................................................................................................................................ 2832
Figure 28-35. CAN_NDAT_X Register...................................................................................................................................2833
Figure 28-36. CAN_NDAT_21 Register................................................................................................................................. 2834
Figure 28-37. CAN_IPEN_X Register....................................................................................................................................2835
Figure 28-38. CAN_IPEN_21 Register.................................................................................................................................. 2836
Figure 28-39. CAN_MVAL_X Register...................................................................................................................................2837
Figure 28-40. CAN_MVAL_21 Register................................................................................................................................. 2838
Figure 28-41. CAN_IP_MUX21 Register............................................................................................................................... 2839
Figure 28-42. CAN_IF1CMD Register................................................................................................................................... 2840

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Figure 28-43. CAN_IF1MSK Register................................................................................................................................... 2843

Figure 28-44. CAN_IF1ARB Register....................................................................................................................................2844
Figure 28-45. CAN_IF1MCTL Register................................................................................................................................. 2846
Figure 28-46. CAN_IF1DATA Register.................................................................................................................................. 2848
Figure 28-47. CAN_IF1DATB Register.................................................................................................................................. 2849
Figure 28-48. CAN_IF2CMD Register................................................................................................................................... 2850
Figure 28-49. CAN_IF2MSK Register................................................................................................................................... 2853
Figure 28-50. CAN_IF2ARB Register....................................................................................................................................2854
Figure 28-51. CAN_IF2MCTL Register................................................................................................................................. 2856
Figure 28-52. CAN_IF2DATA Register.................................................................................................................................. 2858
Figure 28-53. CAN_IF2DATB Register.................................................................................................................................. 2859
Figure 28-54. CAN_IF3OBS Register....................................................................................................................................2860
Figure 28-55. CAN_IF3MSK Register................................................................................................................................... 2862
Figure 28-56. CAN_IF3ARB Register....................................................................................................................................2863
Figure 28-57. CAN_IF3MCTL Register................................................................................................................................. 2864
Figure 28-58. CAN_IF3DATA Register.................................................................................................................................. 2866
Figure 28-59. CAN_IF3DATB Register.................................................................................................................................. 2867
Figure 28-60. CAN_IF3UPD Register....................................................................................................................................2868
Figure 29-1. MCAN Module Overview................................................................................................................................... 2874
Figure 29-2. MCAN Typical Bus Wiring................................................................................................................................. 2875
Figure 29-3. MCAN Integration..............................................................................................................................................2877
Figure 29-4. MCAN Block Diagram....................................................................................................................................... 2879
Figure 29-5. CAN FD Frame..................................................................................................................................................2882
Figure 29-6. CAN Bit Timing.................................................................................................................................................. 2884
Figure 29-7. Transmitter Delay Measurement....................................................................................................................... 2885
Figure 29-8. Connection of Signals in Bus Monitoring Mode.................................................................................................2887
Figure 29-9. Clock Stop Request...........................................................................................................................................2888
Figure 29-10. Power Down Entry...........................................................................................................................................2889
Figure 29-11. Auto Wakeup Enabled Exit from Power Down................................................................................................ 2891
Figure 29-12. External Loop Back Mode............................................................................................................................... 2892
Figure 29-13. Internal Loop Back Mode................................................................................................................................ 2893
Figure 29-14. External Timestamp Counter Interrupt............................................................................................................ 2894
Figure 29-15. Standard Message ID Filter Path.................................................................................................................... 2899
Figure 29-16. Extended Message ID Filter Path....................................................................................................................2900
Figure 29-17. Rx FIFO Status................................................................................................................................................2901
Figure 29-18. Rx FIFO Overflow Handling............................................................................................................................ 2902
Figure 29-19. Mixed Dedicated Tx Buffers /Tx FIFO (example)............................................................................................ 2906
Figure 29-20. Mixed Dedicated Tx Buffers /Tx Queue (example)..........................................................................................2906
Figure 29-21. Message RAM Configuration.......................................................................................................................... 2908
Figure 29-22. Rx Buffer/Rx FIFO Element Structure............................................................................................................. 2909
Figure 29-23. Tx Buffer Element Structure............................................................................................................................ 2911
Figure 29-24. Tx Event FIFO Element Structure................................................................................................................... 2913
Figure 29-25. Standard Message ID Filter Element Structure...............................................................................................2914
Figure 29-26. Extended Message ID Filter Element Structure.............................................................................................. 2916
Figure 29-27. MCANSS_PID Register...................................................................................................................................2924
Figure 29-28. MCANSS_CTRL Register............................................................................................................................... 2925
Figure 29-29. MCANSS_STAT Register................................................................................................................................ 2926
Figure 29-30. MCANSS_ICS Register...................................................................................................................................2927
Figure 29-31. MCANSS_IRS Register...................................................................................................................................2928
Figure 29-32. MCANSS_IECS Register................................................................................................................................ 2929
Figure 29-33. MCANSS_IE Register..................................................................................................................................... 2930
Figure 29-34. MCANSS_IES Register...................................................................................................................................2931
Figure 29-35. MCANSS_EOI Register.................................................................................................................................. 2932
Figure 29-36. MCANSS_EXT_TS_PRESCALER Register................................................................................................... 2933
Figure 29-37. MCANSS_EXT_TS_UNSERVICED_INTR_CNTR Register........................................................................... 2934
Figure 29-38. MCAN_CREL Register....................................................................................................................................2937
Figure 29-39. MCAN_ENDN Register................................................................................................................................... 2938
Figure 29-40. MCAN_DBTP Register....................................................................................................................................2939
Figure 29-41. MCAN_TEST Register.................................................................................................................................... 2941
Figure 29-42. MCAN_RWD Register..................................................................................................................................... 2942
Figure 29-43. MCAN_CCCR Register................................................................................................................................... 2943

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Figure 29-44. MCAN_NBTP Register....................................................................................................................................2946

Figure 29-45. MCAN_TSCC Register....................................................................................................................................2948
Figure 29-46. MCAN_TSCV Register....................................................................................................................................2949
Figure 29-47. MCAN_TOCC Register................................................................................................................................... 2950
Figure 29-48. MCAN_TOCV Register....................................................................................................................................2951
Figure 29-49. MCAN_ECR Register......................................................................................................................................2952
Figure 29-50. MCAN_PSR Register...................................................................................................................................... 2953
Figure 29-51. MCAN_TDCR Register................................................................................................................................... 2956
Figure 29-52. MCAN_IR Register..........................................................................................................................................2957
Figure 29-53. MCAN_IE Register.......................................................................................................................................... 2960
Figure 29-54. MCAN_ILS Register........................................................................................................................................ 2962
Figure 29-55. MCAN_ILE Register........................................................................................................................................ 2965
Figure 29-56. MCAN_GFC Register......................................................................................................................................2966
Figure 29-57. MCAN_SIDFC Register...................................................................................................................................2967
Figure 29-58. MCAN_XIDFC Register...................................................................................................................................2968
Figure 29-59. MCAN_XIDAM Register.................................................................................................................................. 2969
Figure 29-60. MCAN_HPMS Register................................................................................................................................... 2970
Figure 29-61. MCAN_NDAT1 Register.................................................................................................................................. 2971
Figure 29-62. MCAN_NDAT2 Register.................................................................................................................................. 2974
Figure 29-63. MCAN_RXF0C Register..................................................................................................................................2977
Figure 29-64. MCAN_RXF0S Register..................................................................................................................................2978
Figure 29-65. MCAN_RXF0A Register..................................................................................................................................2979
Figure 29-66. MCAN_RXBC Register................................................................................................................................... 2980
Figure 29-67. MCAN_RXF1C Register..................................................................................................................................2981
Figure 29-68. MCAN_RXF1S Register..................................................................................................................................2982
Figure 29-69. MCAN_RXF1A Register..................................................................................................................................2983
Figure 29-70. MCAN_RXESC Register................................................................................................................................. 2984
Figure 29-71. MCAN_TXBC Register....................................................................................................................................2986
Figure 29-72. MCAN_TXFQS Register................................................................................................................................. 2988
Figure 29-73. MCAN_TXESC Register................................................................................................................................. 2989
Figure 29-74. MCAN_TXBRP Register................................................................................................................................. 2990
Figure 29-75. MCAN_TXBAR Register................................................................................................................................. 2993
Figure 29-76. MCAN_TXBCR Register................................................................................................................................. 2995
Figure 29-77. MCAN_TXBTO Register..................................................................................................................................2997
Figure 29-78. MCAN_TXBCF Register..................................................................................................................................2999
Figure 29-79. MCAN_TXBTIE Register.................................................................................................................................3001
Figure 29-80. MCAN_TXBCIE Register................................................................................................................................ 3005
Figure 29-81. MCAN_TXEFC Register..................................................................................................................................3009
Figure 29-82. MCAN_TXEFS Register..................................................................................................................................3010
Figure 29-83. MCAN_TXEFA Register.................................................................................................................................. 3011
Figure 29-84. MCANERR_REV Register.............................................................................................................................. 3014
Figure 29-85. MCANERR_VECTOR Register....................................................................................................................... 3015
Figure 29-86. MCANERR_STAT Register............................................................................................................................. 3016
Figure 29-87. MCANERR_WRAP_REV Register..................................................................................................................3017
Figure 29-88. MCANERR_CTRL Register............................................................................................................................ 3018
Figure 29-89. MCANERR_ERR_CTRL1 Register.................................................................................................................3020
Figure 29-90. MCANERR_ERR_CTRL2 Register.................................................................................................................3021
Figure 29-91. MCANERR_ERR_STAT1 Register..................................................................................................................3022
Figure 29-92. MCANERR_ERR_STAT2 Register..................................................................................................................3024
Figure 29-93. MCANERR_ERR_STAT3 Register..................................................................................................................3025
Figure 29-94. MCANERR_SEC_EOI Register...................................................................................................................... 3026
Figure 29-95. MCANERR_SEC_STATUS Register...............................................................................................................3027
Figure 29-96. MCANERR_SEC_ENABLE_SET Register..................................................................................................... 3028
Figure 29-97. MCANERR_SEC_ENABLE_CLR Register..................................................................................................... 3029
Figure 29-98. MCANERR_DED_EOI Register...................................................................................................................... 3030
Figure 29-99. MCANERR_DED_STATUS Register...............................................................................................................3031
Figure 29-100. MCANERR_DED_ENABLE_SET Register................................................................................................... 3032
Figure 29-101. MCANERR_DED_ENABLE_CLR Register...................................................................................................3033
Figure 29-102. MCANERR_AGGR_ENABLE_SET Register................................................................................................ 3034
Figure 29-103. MCANERR_AGGR_ENABLE_CLR Register................................................................................................3035
Figure 29-104. MCANERR_AGGR_STATUS_SET Register.................................................................................................3036

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Figure 29-105. MCANERR_AGGR_STATUS_CLR Register................................................................................................ 3037

Figure 30-1. SCI Block Diagram............................................................................................................................................ 3047
Figure 30-2. SCI/LIN Block Diagram..................................................................................................................................... 3048
Figure 30-3. Typical SCI Data Frame Formats...................................................................................................................... 3049
Figure 30-4. Asynchronous Communication Bit Timing.........................................................................................................3050
Figure 30-5. Superfractional Divider Example....................................................................................................................... 3053
Figure 30-6. Idle-Line Multiprocessor Communication Format..............................................................................................3055
Figure 30-7. Address-Bit Multiprocessor Communication Format......................................................................................... 3056
Figure 30-8. Receive Buffers................................................................................................................................................. 3057
Figure 30-9. Transmit Buffers................................................................................................................................................ 3058
Figure 30-10. General Interrupt Scheme............................................................................................................................... 3059
Figure 30-11. Interrupt Generation for Given Flags............................................................................................................... 3060
Figure 30-12. LIN Protocol Message Frame Format: Master Header and Response........................................................... 3068
Figure 30-13. Header 3 Fields: Synch Break, Synch, and ID................................................................................................ 3068
Figure 30-14. Response Format of LIN Message Frame...................................................................................................... 3069
Figure 30-15. Message Header in Terms of Tbit ................................................................................................................... 3072
Figure 30-16. ID Field............................................................................................................................................................ 3073
Figure 30-17. Measurements for Synchronization.................................................................................................................3075
Figure 30-18. Synchronization Validation Process and Baud Rate Adjustment.................................................................... 3076
Figure 30-19. Optional Embedded Checksum in Response for Extended Frames............................................................... 3077
Figure 30-20. Checksum Compare and Send for Extended Frames.....................................................................................3078
Figure 30-21. TXRX Error Detector....................................................................................................................................... 3080
Figure 30-22. Classic Checksum Generation at Transmitting Node......................................................................................3081
Figure 30-23. LIN 2.0-Compliant Checksum Generation at Transmitting Node.................................................................... 3081
Figure 30-24. ID Reception, Filtering, and Validation............................................................................................................ 3082
Figure 30-25. LIN Message Frame Showing LIN Interrupt Timing and Sequence................................................................ 3086
Figure 30-26. Wakeup Signal Generation..............................................................................................................................3090
Figure 30-27. SCIGCR0 Register.......................................................................................................................................... 3097
Figure 30-28. SCIGCR1 Register.......................................................................................................................................... 3098
Figure 30-29. SCIGCR2 Register.......................................................................................................................................... 3103
Figure 30-30. SCISETINT Register....................................................................................................................................... 3105
Figure 30-31. SCICLEARINT Register.................................................................................................................................. 3109
Figure 30-32. SCISETINTLVL Register................................................................................................................................. 3112
Figure 30-33. SCICLEARINTLVL Register............................................................................................................................ 3115
Figure 30-34. SCIFLR Register..............................................................................................................................................3118
Figure 30-35. SCIINTVECT0 Register...................................................................................................................................3126
Figure 30-36. SCIINTVECT1 Register...................................................................................................................................3127
Figure 30-37. SCIFORMAT Register..................................................................................................................................... 3128
Figure 30-38. BRSR Register................................................................................................................................................ 3129
Figure 30-39. SCIED Register............................................................................................................................................... 3131
Figure 30-40. SCIRD Register...............................................................................................................................................3132
Figure 30-41. SCITD Register............................................................................................................................................... 3133
Figure 30-42. SCIPIO0 Register............................................................................................................................................3134
Figure 30-43. SCIPIO2 Register............................................................................................................................................3135
Figure 30-44. LINCOMP Register..........................................................................................................................................3136
Figure 30-45. LINRD0 Register............................................................................................................................................. 3137
Figure 30-46. LINRD1 Register............................................................................................................................................. 3138
Figure 30-47. LINMASK Register.......................................................................................................................................... 3139
Figure 30-48. LINID Register.................................................................................................................................................3140
Figure 30-49. LINTD0 Register..............................................................................................................................................3141
Figure 30-50. LINTD1 Register..............................................................................................................................................3142
Figure 30-51. MBRSR Register............................................................................................................................................. 3143
Figure 30-52. IODFTCTRL Register......................................................................................................................................3144
Figure 30-53. LIN_GLB_INT_EN Register............................................................................................................................ 3147
Figure 30-54. LIN_GLB_INT_FLG Register.......................................................................................................................... 3148
Figure 30-55. LIN_GLB_INT_CLR Register.......................................................................................................................... 3149
Figure 31-1. FSI Transmitter (FSITX) CPU Interface.............................................................................................................3157
Figure 31-2. FSI Receiver (FSIRX) CPU Interface with CLB.................................................................................................3158
Figure 31-3. FSI Transmitter Block Diagram......................................................................................................................... 3165
Figure 31-4. FSI Transmitter Core Block Diagram.................................................................................................................3166
Figure 31-5. FSI Receiver Block Diagram............................................................................................................................. 3171

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Figure 31-6. FSI Receiver Core Block Diagram.................................................................................................................... 3172

Figure 31-7. Delay Line Control Circuit..................................................................................................................................3175
Figure 31-8. Flush Sequence Signals....................................................................................................................................3181
Figure 31-9. FSI with Internal Loopback................................................................................................................................3181
Figure 31-10. FSI Multi-Slave TDM Configuration.................................................................................................................3184
Figure 31-11. FSI Transmitter Multi-Slave TDM Multiplexing................................................................................................ 3184
Figure 31-12. Generated Signals for FSI Multi-Slave TDM Configuration.............................................................................3185
Figure 31-13. TDM Signal Selection......................................................................................................................................3185
Figure 31-14. RX_TRIGx FSI Trigger.................................................................................................................................... 3186
Figure 31-15. FSITX as SPI Master, Transmit Only.............................................................................................................. 3189
Figure 31-16. FSIRX as SPI Slave, Receive Only.................................................................................................................3190
Figure 31-17. FSITX and FSIRX as SPI Master, Full Duplex................................................................................................ 3191
Figure 31-18. Point to Point Connection................................................................................................................................3192
Figure 31-19. TX_MASTER_CTRL Register......................................................................................................................... 3206
Figure 31-20. TX_CLK_CTRL Register................................................................................................................................. 3207
Figure 31-21. TX_OPER_CTRL_LO Register....................................................................................................................... 3208
Figure 31-22. TX_OPER_CTRL_HI Register........................................................................................................................ 3210
Figure 31-23. TX_FRAME_CTRL Register............................................................................................................................3211
Figure 31-24. TX_FRAME_TAG_UDATA Register................................................................................................................ 3212
Figure 31-25. TX_BUF_PTR_LOAD Register....................................................................................................................... 3213
Figure 31-26. TX_BUF_PTR_STS Register.......................................................................................................................... 3214
Figure 31-27. TX_PING_CTRL Register............................................................................................................................... 3215
Figure 31-28. TX_PING_TAG Register..................................................................................................................................3216
Figure 31-29. TX_PING_TO_REF Register...........................................................................................................................3217
Figure 31-30. TX_PING_TO_CNT Register.......................................................................................................................... 3218
Figure 31-31. TX_INT_CTRL Register.................................................................................................................................. 3219
Figure 31-32. TX_DMA_CTRL Register................................................................................................................................ 3221
Figure 31-33. TX_LOCK_CTRL Register.............................................................................................................................. 3222
Figure 31-34. TX_EVT_STS Register................................................................................................................................... 3223
Figure 31-35. TX_EVT_CLR Register................................................................................................................................... 3224
Figure 31-36. TX_EVT_FRC Register................................................................................................................................... 3225
Figure 31-37. TX_USER_CRC Register................................................................................................................................3226
Figure 31-38. TX_ECC_DATA Register.................................................................................................................................3227
Figure 31-39. TX_ECC_VAL Register................................................................................................................................... 3228
Figure 31-40. TX_DLYLINE_CTRL Register......................................................................................................................... 3229
Figure 31-41. TX_BUF_BASE_y Register.............................................................................................................................3230
Figure 31-42. RX_MASTER_CTRL Register.........................................................................................................................3233
Figure 31-43. RX_OPER_CTRL Register............................................................................................................................. 3235
Figure 31-44. RX_FRAME_INFO Register............................................................................................................................3236
Figure 31-45. RX_FRAME_TAG_UDATA Register................................................................................................................3237
Figure 31-46. RX_DMA_CTRL Register................................................................................................................................3238
Figure 31-47. RX_EVT_STS Register................................................................................................................................... 3239
Figure 31-48. RX_CRC_INFO Register.................................................................................................................................3242
Figure 31-49. RX_EVT_CLR Register...................................................................................................................................3243
Figure 31-50. RX_EVT_FRC Register...................................................................................................................................3245
Figure 31-51. RX_BUF_PTR_LOAD Register.......................................................................................................................3248
Figure 31-52. RX_BUF_PTR_STS Register..........................................................................................................................3249
Figure 31-53. RX_FRAME_WD_CTRL Register................................................................................................................... 3250
Figure 31-54. RX_FRAME_WD_REF Register..................................................................................................................... 3251
Figure 31-55. RX_FRAME_WD_CNT Register..................................................................................................................... 3252
Figure 31-56. RX_PING_WD_CTRL Register.......................................................................................................................3253
Figure 31-57. RX_PING_TAG Register................................................................................................................................. 3254
Figure 31-58. RX_PING_WD_REF Register......................................................................................................................... 3255
Figure 31-59. RX_PING_WD_CNT Register.........................................................................................................................3256
Figure 31-60. RX_INT1_CTRL Register................................................................................................................................3257
Figure 31-61. RX_INT2_CTRL Register................................................................................................................................3260
Figure 31-62. RX_LOCK_CTRL Register..............................................................................................................................3263
Figure 31-63. RX_ECC_DATA Register................................................................................................................................ 3264
Figure 31-64. RX_ECC_VAL Register................................................................................................................................... 3265
Figure 31-65. RX_ECC_SEC_DATA Register....................................................................................................................... 3266
Figure 31-66. RX_ECC_LOG Register..................................................................................................................................3267

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Figure 31-67. RX_FRAME_TAG_CMP Register................................................................................................................... 3268

Figure 31-68. RX_PING_TAG_CMP Register....................................................................................................................... 3269
Figure 31-69. RX_TRIG_CTRL_0 Register........................................................................................................................... 3270
Figure 31-70. RX_TRIG_WIDTH_0 Register.........................................................................................................................3271
Figure 31-71. RX_DLYLINE_CTRL Register......................................................................................................................... 3272
Figure 31-72. RX_TRIG_CTRL_1 Register........................................................................................................................... 3273
Figure 31-73. RX_TRIG_CTRL_2 Register........................................................................................................................... 3274
Figure 31-74. RX_TRIG_CTRL_3 Register........................................................................................................................... 3275
Figure 31-75. RX_VIS_1 Register......................................................................................................................................... 3276
Figure 31-76. RX_UDATA_FILTER Register......................................................................................................................... 3277
Figure 31-77. RX_BUF_BASE_y Register............................................................................................................................ 3278
Figure 32-1. Block Diagram of the CLB Subsystem in the Device........................................................................................ 3285
Figure 32-2. Block Diagram of a CLB Tile and CPU Interface...............................................................................................3285
Figure 32-3. CLB Clocking.....................................................................................................................................................3286
Figure 32-4. GPIO to CLB Tile Connections..........................................................................................................................3287
Figure 32-5. CLB Input Mux and Filter...................................................................................................................................3288
Figure 32-6. CLB Input Synchronization Example.................................................................................................................3288
Figure 32-7. CLB Input Pipelining Example...........................................................................................................................3289
Figure 32-8. CLB Outputs......................................................................................................................................................3296
Figure 32-9. CLB Output Signal Multiplexer.......................................................................................................................... 3297
Figure 32-10. CLB Tile Submodules......................................................................................................................................3299
Figure 32-11. Counter Block.................................................................................................................................................. 3302
Figure 32-12. LFSR Modes................................................................................................................................................... 3305
Figure 32-13. FSM Block....................................................................................................................................................... 3306
Figure 32-14. FSM LUT Block............................................................................................................................................... 3307
Figure 32-15. LUT4 Block......................................................................................................................................................3307
Figure 32-16. Output LUT Block............................................................................................................................................ 3308
Figure 32-17. AOC Block.......................................................................................................................................................3309
Figure 32-18. AOC Block and The CLB TILE........................................................................................................................ 3310
Figure 32-19. High Level Controller Block............................................................................................................................. 3311
Figure 32-20. CLB Control of SPI RX Buffer..........................................................................................................................3317
Figure 32-21. CLB_COUNT_RESET Register...................................................................................................................... 3326
Figure 32-22. CLB_COUNT_MODE_1 Register................................................................................................................... 3327
Figure 32-23. CLB_COUNT_MODE_0 Register................................................................................................................... 3328
Figure 32-24. CLB_COUNT_EVENT Register...................................................................................................................... 3329
Figure 32-25. CLB_FSM_EXTRA_IN0 Register....................................................................................................................3330
Figure 32-26. CLB_FSM_EXTERNAL_IN0 Register.............................................................................................................3331
Figure 32-27. CLB_FSM_EXTERNAL_IN1 Register.............................................................................................................3332
Figure 32-28. CLB_FSM_EXTRA_IN1 Register....................................................................................................................3333
Figure 32-29. CLB_LUT4_IN0 Register.................................................................................................................................3334
Figure 32-30. CLB_LUT4_IN1 Register.................................................................................................................................3335
Figure 32-31. CLB_LUT4_IN2 Register.................................................................................................................................3336
Figure 32-32. CLB_LUT4_IN3 Register.................................................................................................................................3337
Figure 32-33. CLB_FSM_LUT_FN1_0 Register....................................................................................................................3338
Figure 32-34. CLB_FSM_LUT_FN2 Register........................................................................................................................3339
Figure 32-35. CLB_LUT4_FN1_0 Register........................................................................................................................... 3340
Figure 32-36. CLB_LUT4_FN2 Register............................................................................................................................... 3341
Figure 32-37. CLB_FSM_NEXT_STATE_0 Register.............................................................................................................3342
Figure 32-38. CLB_FSM_NEXT_STATE_1 Register.............................................................................................................3343
Figure 32-39. CLB_FSM_NEXT_STATE_2 Register.............................................................................................................3344
Figure 32-40. CLB_MISC_CONTROL Register.................................................................................................................... 3345
Figure 32-41. CLB_OUTPUT_LUT_0 Register..................................................................................................................... 3348
Figure 32-42. CLB_OUTPUT_LUT_1 Register..................................................................................................................... 3349
Figure 32-43. CLB_OUTPUT_LUT_2 Register..................................................................................................................... 3350
Figure 32-44. CLB_OUTPUT_LUT_3 Register..................................................................................................................... 3351
Figure 32-45. CLB_OUTPUT_LUT_4 Register..................................................................................................................... 3352
Figure 32-46. CLB_OUTPUT_LUT_5 Register..................................................................................................................... 3353
Figure 32-47. CLB_OUTPUT_LUT_6 Register..................................................................................................................... 3354
Figure 32-48. CLB_OUTPUT_LUT_7 Register..................................................................................................................... 3355
Figure 32-49. CLB_HLC_EVENT_SEL Register................................................................................................................... 3356
Figure 32-50. CLB_COUNT_MATCH_TAP_SEL Register.................................................................................................... 3357

50 TMS320F28003x Real-Time Microcontrollers SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023

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Figure 32-51. CLB_OUTPUT_COND_CTRL_0 Register...................................................................................................... 3358

Figure 32-52. CLB_OUTPUT_COND_CTRL_1 Register...................................................................................................... 3360
Figure 32-53. CLB_OUTPUT_COND_CTRL_2 Register...................................................................................................... 3362
Figure 32-54. CLB_OUTPUT_COND_CTRL_3 Register...................................................................................................... 3364
Figure 32-55. CLB_OUTPUT_COND_CTRL_4 Register...................................................................................................... 3366
Figure 32-56. CLB_OUTPUT_COND_CTRL_5 Register...................................................................................................... 3368
Figure 32-57. CLB_OUTPUT_COND_CTRL_6 Register...................................................................................................... 3370
Figure 32-58. CLB_OUTPUT_COND_CTRL_7 Register...................................................................................................... 3372
Figure 32-59. CLB_MISC_ACCESS_CTRL Register............................................................................................................3374
Figure 32-60. CLB_SPI_DATA_CTRL_HI Register............................................................................................................... 3375
Figure 32-61. CLB_LOAD_EN Register................................................................................................................................ 3378
Figure 32-62. CLB_LOAD_ADDR Register........................................................................................................................... 3379
Figure 32-63. CLB_LOAD_DATA Register............................................................................................................................ 3380
Figure 32-64. CLB_INPUT_FILTER Register........................................................................................................................ 3381
Figure 32-65. CLB_IN_MUX_SEL_0 Register.......................................................................................................................3383
Figure 32-66. CLB_LCL_MUX_SEL_1 Register....................................................................................................................3385
Figure 32-67. CLB_LCL_MUX_SEL_2 Register....................................................................................................................3386
Figure 32-68. CLB_BUF_PTR Register.................................................................................................................................3387
Figure 32-69. CLB_GP_REG Register.................................................................................................................................. 3388
Figure 32-70. CLB_OUT_EN Register.................................................................................................................................. 3390
Figure 32-71. CLB_GLBL_MUX_SEL_1 Register................................................................................................................. 3391
Figure 32-72. CLB_GLBL_MUX_SEL_2 Register................................................................................................................. 3392
Figure 32-73. CLB_PRESCALE_CTRL Register.................................................................................................................. 3393
Figure 32-74. CLB_INTR_TAG_REG Register......................................................................................................................3394
Figure 32-75. CLB_LOCK Register....................................................................................................................................... 3395
Figure 32-76. CLB_HLC_INSTR_READ_PTR Register........................................................................................................3396
Figure 32-77. CLB_HLC_INSTR_VALUE Register................................................................................................................3397
Figure 32-78. CLB_DBG_OUT_2 Register............................................................................................................................3398
Figure 32-79. CLB_DBG_R0 Register...................................................................................................................................3399
Figure 32-80. CLB_DBG_R1 Register...................................................................................................................................3400
Figure 32-81. CLB_DBG_R2 Register...................................................................................................................................3401
Figure 32-82. CLB_DBG_R3 Register...................................................................................................................................3402
Figure 32-83. CLB_DBG_C0 Register...................................................................................................................................3403
Figure 32-84. CLB_DBG_C1 Register...................................................................................................................................3404
Figure 32-85. CLB_DBG_C2 Register...................................................................................................................................3405
Figure 32-86. CLB_DBG_OUT Register................................................................................................................................3406
Figure 32-87. CLB_PUSH_y Register................................................................................................................................... 3409
Figure 32-88. CLB_PULL_y Register.................................................................................................................................... 3410
Figure 33-1. AES Block Diagram...........................................................................................................................................3416
Figure 33-2. AES - GCM Operation.......................................................................................................................................3420
Figure 33-3. AES - CCM Operation....................................................................................................................................... 3421
Figure 33-4. AES - XTS Operation........................................................................................................................................ 3422
Figure 33-5. AES - ECB Feedback Mode..............................................................................................................................3423
Figure 33-6. AES - CBC Feedback Mode..............................................................................................................................3424
Figure 33-7. AES Encryption With CTR/ICM Mode............................................................................................................... 3425
Figure 33-8. AES - CFB Feedback Mode.............................................................................................................................. 3426
Figure 33-9. AES - F8 Mode..................................................................................................................................................3427
Figure 33-10. AES - F9 Operation......................................................................................................................................... 3428
Figure 33-11. AES - CBC-MAC Authentication Mode............................................................................................................3429
Figure 33-12. AES Polling Mode........................................................................................................................................... 3433
Figure 33-13. AES Interrupt Service......................................................................................................................................3435
Figure 33-14. AES_KEY2_6 Register....................................................................................................................................3440
Figure 33-15. AES_KEY2_7 Register....................................................................................................................................3441
Figure 33-16. AES_KEY2_4 Register....................................................................................................................................3442
Figure 33-17. AES_KEY2_5 Register....................................................................................................................................3443
Figure 33-18. AES_KEY2_2 Register....................................................................................................................................3444
Figure 33-19. AES_KEY2_3 Register....................................................................................................................................3445
Figure 33-20. AES_KEY2_0 Register....................................................................................................................................3446
Figure 33-21. AES_KEY2_1 Register....................................................................................................................................3447
Figure 33-22. AES_KEY1_6 Register....................................................................................................................................3448
Figure 33-23. AES_KEY1_7 Register....................................................................................................................................3449

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Figure 33-24. AES_KEY1_4 Register....................................................................................................................................3450

Figure 33-25. AES_KEY1_5 Register....................................................................................................................................3451
Figure 33-26. AES_KEY1_2 Register....................................................................................................................................3452
Figure 33-27. AES_KEY1_3 Register....................................................................................................................................3453
Figure 33-28. AES_KEY1_0 Register....................................................................................................................................3454
Figure 33-29. AES_KEY1_1 Register....................................................................................................................................3455
Figure 33-30. AES_IV_IN_OUT_0 Register.......................................................................................................................... 3456
Figure 33-31. AES_IV_IN_OUT_1 Register.......................................................................................................................... 3457
Figure 33-32. AES_IV_IN_OUT_2 Register.......................................................................................................................... 3458
Figure 33-33. AES_IV_IN_OUT_3 Register.......................................................................................................................... 3459
Figure 33-34. AES_CTRL Register....................................................................................................................................... 3460
Figure 33-35. AES_C_LENGTH_0 Register..........................................................................................................................3464
Figure 33-36. AES_C_LENGTH_1 Register..........................................................................................................................3465
Figure 33-37. AES_AUTH_LENGTH Register...................................................................................................................... 3466
Figure 33-38. AES_DATA_IN_OUT_0 Register.....................................................................................................................3467
Figure 33-39. AES_DATA_IN_OUT_1 Register.....................................................................................................................3468
Figure 33-40. AES_DATA_IN_OUT_2 Register.....................................................................................................................3469
Figure 33-41. AES_DATA_IN_OUT_3 Register.....................................................................................................................3470
Figure 33-42. AES_TAG_OUT_0 Register............................................................................................................................ 3471
Figure 33-43. AES_TAG_OUT_1 Register............................................................................................................................ 3472
Figure 33-44. AES_TAG_OUT_2 Register............................................................................................................................ 3473
Figure 33-45. AES_TAG_OUT_3 Register............................................................................................................................ 3474
Figure 33-46. AES_REV Register......................................................................................................................................... 3475
Figure 33-47. AES_SYSCONFIG Register............................................................................................................................3476
Figure 33-48. AES_SYSSTATUS Register............................................................................................................................ 3478
Figure 33-49. AES_IRQSTATUS Register.............................................................................................................................3479
Figure 33-50. AES_IRQENABLE Register............................................................................................................................ 3480
Figure 33-51. AES_DIRTY_BITS Register............................................................................................................................ 3481
Figure 33-52. AES_GLB_INT_FLG Register.........................................................................................................................3483
Figure 33-53. AES_GLB_INT_CLR Register.........................................................................................................................3484
Figure 34-1. EPG Overview Block Diagram.......................................................................................................................... 3491
Figure 34-2. EPG Detailed Block Diagram............................................................................................................................ 3492
Figure 34-3. EPG Clock Generator........................................................................................................................................3493
Figure 34-4. EPG Clock Stop................................................................................................................................................ 3494
Figure 34-5. EPG Signal Generator Detailed Overview........................................................................................................ 3496
Figure 34-6. EPG Peripheral Signal Muxing..........................................................................................................................3499
Figure 34-7. EPG Interrupt.................................................................................................................................................... 3503
Figure 34-8. GCTL0 Register................................................................................................................................................ 3508
Figure 34-9. GCTL1 Register................................................................................................................................................ 3509
Figure 34-10. GCTL2 Register.............................................................................................................................................. 3510
Figure 34-11. GCTL3 Register...............................................................................................................................................3512
Figure 34-12. EPGLOCK Register.........................................................................................................................................3515
Figure 34-13. EPGCOMMIT Register....................................................................................................................................3516
Figure 34-14. GINTSTS Register.......................................................................................................................................... 3517
Figure 34-15. GINTEN Register............................................................................................................................................ 3518
Figure 34-16. GINTCLR Register.......................................................................................................................................... 3519
Figure 34-17. GINTFRC Register.......................................................................................................................................... 3520
Figure 34-18. CLKDIV0_CTL0 Register................................................................................................................................ 3521
Figure 34-19. CLKDIV0_CLKOFFSET Register....................................................................................................................3522
Figure 34-20. CLKDIV1_CTL0 Register................................................................................................................................ 3523
Figure 34-21. CLKDIV1_CLKOFFSET Register....................................................................................................................3524
Figure 34-22. SIGGEN0_CTL0 Register............................................................................................................................... 3525
Figure 34-23. SIGGEN0_CTL1 Register............................................................................................................................... 3527
Figure 34-24. SIGGEN0_DATA0 Register............................................................................................................................. 3528
Figure 34-25. SIGGEN0_DATA1 Register............................................................................................................................. 3529
Figure 34-26. SIGGEN0_DATA0_ACTIVE Register.............................................................................................................. 3530
Figure 34-27. SIGGEN0_DATA1_ACTIVE Register.............................................................................................................. 3531
Figure 34-28. EPGMXSEL0 Register.................................................................................................................................... 3533
Figure 34-29. EPGMXSELLOCK Register............................................................................................................................ 3536
Figure 34-30. EPGMXSELCOMMIT Register........................................................................................................................3537

52 TMS320F28003x Real-Time Microcontrollers SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023

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List of Tables
Table 1-1. C2000Ware Root Directories.................................................................................................................................... 90
Table 2-1. TMU Supported Instructions..................................................................................................................................... 95
Table 3-1. Access to EALLOW-Protected Registers..................................................................................................................99
Table 3-2. Reset Signals............................................................................................................................................................99
Table 3-3. Pie Channel Mapping..............................................................................................................................................106
Table 3-4. CPU Interrupt Vectors............................................................................................................................................. 108
Table 3-5. PIE Interrupt Vectors...............................................................................................................................................109
Table 3-6. ALT Modes.............................................................................................................................................................. 120
Table 3-7. Clock Connections Sorted by Clock Domain.......................................................................................................... 122
Table 3-8. Clock Source (OSCCLK) Failure Detection............................................................................................................ 125
Table 3-9. Example Watchdog Key Sequences.......................................................................................................................130
Table 3-10. Effect of Clock-Gating Low-Power Modes on the Device..................................................................................... 132
Table 3-11. Local Shared RAM................................................................................................................................................ 136
Table 3-12. Global Shared RAM.............................................................................................................................................. 136
Table 3-13. Error Handling in Different Scenarios....................................................................................................................140
Table 3-14. Mapping of ECC Bits in Read Data from ECC Address Map................................................................................141
Table 3-15. System Control Registers Impacted..................................................................................................................... 147
Table 3-16. SYSCTRL Base Address Table............................................................................................................................ 155
Table 3-17. ACCESS_PROTECTION_REGS Registers......................................................................................................... 156
Table 3-18. ACCESS_PROTECTION_REGS Access Type Codes.........................................................................................156
Table 3-19. NMAVFLG Register Field Descriptions................................................................................................................. 158
Table 3-20. NMAVSET Register Field Descriptions................................................................................................................. 160
Table 3-21. NMAVCLR Register Field Descriptions.................................................................................................................162
Table 3-22. NMAVINTEN Register Field Descriptions............................................................................................................. 164
Table 3-23. NMCPURDAVADDR Register Field Descriptions................................................................................................. 166
Table 3-24. NMCPUWRAVADDR Register Field Descriptions................................................................................................ 167
Table 3-25. NMCPUFAVADDR Register Field Descriptions.................................................................................................... 168
Table 3-26. NMDMAWRAVADDR Register Field Descriptions................................................................................................ 169
Table 3-27. NMCLA1RDAVADDR Register Field Descriptions................................................................................................170
Table 3-28. NMCLA1WRAVADDR Register Field Descriptions............................................................................................... 171
Table 3-29. NMCLA1FAVADDR Register Field Descriptions................................................................................................... 172
Table 3-30. NMDMARDAVADDR Register Field Descriptions.................................................................................................173
Table 3-31. MAVFLG Register Field Descriptions....................................................................................................................174
Table 3-32. MAVSET Register Field Descriptions....................................................................................................................175
Table 3-33. MAVCLR Register Field Descriptions................................................................................................................... 176
Table 3-34. MAVINTEN Register Field Descriptions................................................................................................................177
Table 3-35. MCPUFAVADDR Register Field Descriptions....................................................................................................... 178
Table 3-36. MCPUWRAVADDR Register Field Descriptions................................................................................................... 179
Table 3-37. MDMAWRAVADDR Register Field Descriptions...................................................................................................180
Table 3-38. MHICWRAVADDR_y Register Field Descriptions.................................................................................................181
Table 3-39. NMHICRDAVADDR Register Field Descriptions...................................................................................................182
Table 3-40. NMHICWRAVADDR Register Field Descriptions..................................................................................................183
Table 3-41. CLK_CFG_REGS Registers................................................................................................................................. 184
Table 3-42. CLK_CFG_REGS Access Type Codes................................................................................................................ 184
Table 3-43. CLKCFGLOCK1 Register Field Descriptions........................................................................................................186
Table 3-44. CLKSRCCTL1 Register Field Descriptions...........................................................................................................188
Table 3-45. CLKSRCCTL2 Register Field Descriptions...........................................................................................................190
Table 3-46. CLKSRCCTL3 Register Field Descriptions...........................................................................................................191
Table 3-47. SYSPLLCTL1 Register Field Descriptions............................................................................................................192
Table 3-48. SYSPLLMULT Register Field Descriptions........................................................................................................... 193
Table 3-49. SYSPLLSTS Register Field Descriptions............................................................................................................. 194
Table 3-50. SYSCLKDIVSEL Register Field Descriptions....................................................................................................... 195
Table 3-51. AUXCLKDIVSEL Register Field Descriptions.......................................................................................................196
Table 3-52. XCLKOUTDIVSEL Register Field Descriptions.................................................................................................... 197
Table 3-53. LOSPCP Register Field Descriptions................................................................................................................... 198
Table 3-54. MCDCR Register Field Descriptions.....................................................................................................................199
Table 3-55. X1CNT Register Field Descriptions...................................................................................................................... 201
Table 3-56. XTALCR Register Field Descriptions.................................................................................................................... 202
Table 3-57. XTALCR2 Register Field Descriptions.................................................................................................................. 203

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Table 3-58. CLKFAILCFG Register Field Descriptions............................................................................................................ 204

Table 3-59. CPU_SYS_REGS Registers.................................................................................................................................205
Table 3-60. CPU_SYS_REGS Access Type Codes................................................................................................................ 205
Table 3-61. CPUSYSLOCK1 Register Field Descriptions....................................................................................................... 207
Table 3-62. CPUSYSLOCK2 Register Field Descriptions....................................................................................................... 210
Table 3-63. PIEVERRADDR Register Field Descriptions........................................................................................................ 211
Table 3-64. PCLKCR0 Register Field Descriptions................................................................................................................. 212
Table 3-65. PCLKCR2 Register Field Descriptions................................................................................................................. 214
Table 3-66. PCLKCR3 Register Field Descriptions................................................................................................................. 216
Table 3-67. PCLKCR4 Register Field Descriptions................................................................................................................. 217
Table 3-68. PCLKCR6 Register Field Descriptions................................................................................................................. 218
Table 3-69. PCLKCR7 Register Field Descriptions................................................................................................................. 219
Table 3-70. PCLKCR8 Register Field Descriptions................................................................................................................. 220
Table 3-71. PCLKCR9 Register Field Descriptions................................................................................................................. 221
Table 3-72. PCLKCR10 Register Field Descriptions............................................................................................................... 222
Table 3-73. PCLKCR13 Register Field Descriptions............................................................................................................... 223
Table 3-74. PCLKCR14 Register Field Descriptions............................................................................................................... 224
Table 3-75. PCLKCR16 Register Field Descriptions............................................................................................................... 225
Table 3-76. PCLKCR17 Register Field Descriptions............................................................................................................... 226
Table 3-77. PCLKCR18 Register Field Descriptions............................................................................................................... 227
Table 3-78. PCLKCR19 Register Field Descriptions............................................................................................................... 228
Table 3-79. PCLKCR20 Register Field Descriptions............................................................................................................... 229
Table 3-80. PCLKCR21 Register Field Descriptions............................................................................................................... 230
Table 3-81. PCLKCR25 Register Field Descriptions............................................................................................................... 231
Table 3-82. PCLKCR26 Register Field Descriptions............................................................................................................... 232
Table 3-83. PCLKCR27 Register Field Descriptions............................................................................................................... 233
Table 3-84. SIMRESET Register Field Descriptions................................................................................................................234
Table 3-85. LPMCR Register Field Descriptions..................................................................................................................... 235
Table 3-86. GPIOLPMSEL0 Register Field Descriptions.........................................................................................................236
Table 3-87. GPIOLPMSEL1 Register Field Descriptions.........................................................................................................239
Table 3-88. TMR2CLKCTL Register Field Descriptions.......................................................................................................... 242
Table 3-89. RESCCLR Register Field Descriptions.................................................................................................................243
Table 3-90. RESC Register Field Descriptions........................................................................................................................ 245
Table 3-91. MCANWAKESTATUS Register Field Descriptions............................................................................................... 247
Table 3-92. MCANWAKESTATUSCLR Register Field Descriptions........................................................................................ 248
Table 3-93. CLKSTOPREQ Register Field Descriptions..........................................................................................................249
Table 3-94. CLKSTOPACK Register Field Descriptions.......................................................................................................... 250
Table 3-95. CPUTIMER_REGS Registers...............................................................................................................................251
Table 3-96. CPUTIMER_REGS Access Type Codes.............................................................................................................. 251
Table 3-97. TIM Register Field Descriptions............................................................................................................................252
Table 3-98. PRD Register Field Descriptions.......................................................................................................................... 253
Table 3-99. TCR Register Field Descriptions...........................................................................................................................254
Table 3-100. TPR Register Field Descriptions.........................................................................................................................256
Table 3-101. TPRH Register Field Descriptions...................................................................................................................... 257
Table 3-102. DEV_CFG_REGS Registers...............................................................................................................................258
Table 3-103. DEV_CFG_REGS Access Type Codes.............................................................................................................. 258
Table 3-104. PARTIDL Register Field Descriptions................................................................................................................. 260
Table 3-105. PARTIDH Register Field Descriptions.................................................................................................................261
Table 3-106. REVID Register Field Descriptions..................................................................................................................... 262
Table 3-107. FUSEERR Register Field Descriptions...............................................................................................................263
Table 3-108. SOFTPRES0 Register Field Descriptions...........................................................................................................264
Table 3-109. SOFTPRES2 Register Field Descriptions...........................................................................................................265
Table 3-110. SOFTPRES3 Register Field Descriptions........................................................................................................... 267
Table 3-111. SOFTPRES4 Register Field Descriptions........................................................................................................... 268
Table 3-112. SOFTPRES6 Register Field Descriptions........................................................................................................... 269
Table 3-113. SOFTPRES7 Register Field Descriptions........................................................................................................... 270
Table 3-114. SOFTPRES8 Register Field Descriptions........................................................................................................... 271
Table 3-115. SOFTPRES9 Register Field Descriptions........................................................................................................... 272
Table 3-116. SOFTPRES10 Register Field Descriptions......................................................................................................... 273
Table 3-117. SOFTPRES13 Register Field Descriptions......................................................................................................... 274
Table 3-118. SOFTPRES14 Register Field Descriptions......................................................................................................... 275

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Table 3-119. SOFTPRES16 Register Field Descriptions......................................................................................................... 276

Table 3-120. SOFTPRES17 Register Field Descriptions.........................................................................................................277
Table 3-121. SOFTPRES18 Register Field Descriptions.........................................................................................................278
Table 3-122. SOFTPRES19 Register Field Descriptions.........................................................................................................279
Table 3-123. SOFTPRES20 Register Field Descriptions.........................................................................................................280
Table 3-124. SOFTPRES21 Register Field Descriptions.........................................................................................................281
Table 3-125. SOFTPRES25 Register Field Descriptions.........................................................................................................282
Table 3-126. SOFTPRES26 Register Field Descriptions.........................................................................................................283
Table 3-127. SOFTPRES27 Register Field Descriptions.........................................................................................................284
Table 3-128. TAP_STATUS Register Field Descriptions..........................................................................................................285
Table 3-129. ECAPTYPE Register Field Descriptions.............................................................................................................286
Table 3-130. SDFMTYPE Register Field Descriptions............................................................................................................ 287
Table 3-131. DMA_CLA_SRC_SEL_REGS Registers............................................................................................................ 288
Table 3-132. DMA_CLA_SRC_SEL_REGS Access Type Codes............................................................................................288
Table 3-133. CLA1TASKSRCSELLOCK Register Field Descriptions......................................................................................289
Table 3-134. DMACHSRCSELLOCK Register Field Descriptions...........................................................................................290
Table 3-135. CLA1TASKSRCSEL1 Register Field Descriptions..............................................................................................291
Table 3-136. CLA1TASKSRCSEL2 Register Field Descriptions..............................................................................................292
Table 3-137. DMACHSRCSEL1 Register Field Descriptions.................................................................................................. 293
Table 3-138. DMACHSRCSEL2 Register Field Descriptions.................................................................................................. 294
Table 3-139. MEM_CFG_REGS Registers..............................................................................................................................295
Table 3-140. MEM_CFG_REGS Access Type Codes............................................................................................................. 295
Table 3-141. DxLOCK Register Field Descriptions..................................................................................................................297
Table 3-142. DxCOMMIT Register Field Descriptions............................................................................................................. 298
Table 3-143. DxACCPROT0 Register Field Descriptions........................................................................................................ 299
Table 3-144. DxTEST Register Field Descriptions.................................................................................................................. 300
Table 3-145. DxINIT Register Field Descriptions.....................................................................................................................301
Table 3-146. DxINITDONE Register Field Descriptions.......................................................................................................... 302
Table 3-147. DxRAMTEST_LOCK Register Field Descriptions...............................................................................................303
Table 3-148. LSxLOCK Register Field Descriptions................................................................................................................ 304
Table 3-149. LSxCOMMIT Register Field Descriptions........................................................................................................... 306
Table 3-150. LSxMSEL Register Field Descriptions................................................................................................................ 308
Table 3-151. LSxCLAPGM Register Field Descriptions...........................................................................................................310
Table 3-152. LSxACCPROT0 Register Field Descriptions...................................................................................................... 312
Table 3-153. LSxACCPROT1 Register Field Descriptions...................................................................................................... 314
Table 3-154. LSxTEST Register Field Descriptions.................................................................................................................316
Table 3-155. LSxINIT Register Field Descriptions................................................................................................................... 318
Table 3-156. LSxINITDONE Register Field Descriptions.........................................................................................................320
Table 3-157. LSxRAMTEST_LOCK Register Field Descriptions.............................................................................................322
Table 3-158. GSxLOCK Register Field Descriptions............................................................................................................... 323
Table 3-159. GSxCOMMIT Register Field Descriptions.......................................................................................................... 325
Table 3-160. GSxACCPROT0 Register Field Descriptions..................................................................................................... 327
Table 3-161. GSxTEST Register Field Descriptions................................................................................................................329
Table 3-162. GSxINIT Register Field Descriptions.................................................................................................................. 331
Table 3-163. GSxINITDONE Register Field Descriptions........................................................................................................333
Table 3-164. GSxRAMTEST_LOCK Register Field Descriptions............................................................................................ 335
Table 3-165. MSGxLOCK Register Field Descriptions............................................................................................................ 336
Table 3-166. MSGxCOMMIT Register Field Descriptions....................................................................................................... 337
Table 3-167. MSGxTEST Register Field Descriptions.............................................................................................................339
Table 3-168. MSGxINIT Register Field Descriptions............................................................................................................... 341
Table 3-169. MSGxINITDONE Register Field Descriptions.....................................................................................................342
Table 3-170. MSGxRAMTEST_LOCK Register Field Descriptions......................................................................................... 343
Table 3-171. ROM_LOCK Register Field Descriptions............................................................................................................344
Table 3-172. ROM_TEST Register Field Descriptions............................................................................................................ 345
Table 3-173. ROM_FORCE_ERROR Register Field Descriptions.......................................................................................... 346
Table 3-174. MEMORY_ERROR_REGS Registers.................................................................................................................347
Table 3-175. MEMORY_ERROR_REGS Access Type Codes................................................................................................ 347
Table 3-176. UCERRFLG Register Field Descriptions............................................................................................................ 349
Table 3-177. UCERRSET Register Field Descriptions............................................................................................................ 350
Table 3-178. UCERRCLR Register Field Descriptions............................................................................................................ 351
Table 3-179. UCCPUREADDR Register Field Descriptions.................................................................................................... 352

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Table 3-180. UCDMAREADDR Register Field Descriptions....................................................................................................353

Table 3-181. UCCLA1READDR Register Field Descriptions...................................................................................................354
Table 3-182. UCHICAREADDR Register Field Descriptions................................................................................................... 355
Table 3-183. CERRFLG Register Field Descriptions...............................................................................................................356
Table 3-184. CERRSET Register Field Descriptions...............................................................................................................357
Table 3-185. CERRCLR Register Field Descriptions...............................................................................................................358
Table 3-186. CCPUREADDR Register Field Descriptions.......................................................................................................359
Table 3-187. CDMAREADDR Register Field Descriptions...................................................................................................... 360
Table 3-188. CCLA1READDR Register Field Descriptions..................................................................................................... 361
Table 3-189. CERRCNT Register Field Descriptions.............................................................................................................. 362
Table 3-190. CERRTHRES Register Field Descriptions..........................................................................................................363
Table 3-191. CEINTFLG Register Field Descriptions.............................................................................................................. 364
Table 3-192. CEINTCLR Register Field Descriptions.............................................................................................................. 365
Table 3-193. CEINTSET Register Field Descriptions.............................................................................................................. 366
Table 3-194. CEINTEN Register Field Descriptions................................................................................................................ 367
Table 3-195. CHICREADDR Register Field Descriptions........................................................................................................ 368
Table 3-196. NMI_INTRUPT_REGS Registers....................................................................................................................... 369
Table 3-197. NMI_INTRUPT_REGS Access Type Codes.......................................................................................................369
Table 3-198. NMICFG Register Field Descriptions..................................................................................................................370
Table 3-199. NMIFLG Register Field Descriptions.................................................................................................................. 371
Table 3-200. NMIFLGCLR Register Field Descriptions........................................................................................................... 373
Table 3-201. NMIFLGFRC Register Field Descriptions........................................................................................................... 375
Table 3-202. NMIWDCNT Register Field Descriptions............................................................................................................ 377
Table 3-203. NMIWDPRD Register Field Descriptions............................................................................................................378
Table 3-204. NMISHDFLG Register Field Descriptions...........................................................................................................379
Table 3-205. ERRORSTS Register Field Descriptions............................................................................................................ 381
Table 3-206. ERRORSTSCLR Register Field Descriptions.....................................................................................................382
Table 3-207. ERRORSTSFRC Register Field Descriptions.....................................................................................................383
Table 3-208. ERRORCTL Register Field Descriptions............................................................................................................ 384
Table 3-209. ERRORLOCK Register Field Descriptions......................................................................................................... 385
Table 3-210. PERIPH_AC_REGS Registers........................................................................................................................... 386
Table 3-211. PERIPH_AC_REGS Access Type Codes........................................................................................................... 387
Table 3-212. ADCA_AC Register Field Descriptions............................................................................................................... 388
Table 3-213. ADCB_AC Register Field Descriptions............................................................................................................... 389
Table 3-214. ADCC_AC Register Field Descriptions...............................................................................................................390
Table 3-215. CMPSS1_AC Register Field Descriptions.......................................................................................................... 391
Table 3-216. CMPSS2_AC Register Field Descriptions.......................................................................................................... 392
Table 3-217. CMPSS3_AC Register Field Descriptions.......................................................................................................... 393
Table 3-218. CMPSS4_AC Register Field Descriptions.......................................................................................................... 394
Table 3-219. DACA_AC Register Field Descriptions............................................................................................................... 395
Table 3-220. DACB_AC Register Field Descriptions............................................................................................................... 396
Table 3-221. EPWM1_AC Register Field Descriptions............................................................................................................397
Table 3-222. EPWM2_AC Register Field Descriptions............................................................................................................398
Table 3-223. EPWM3_AC Register Field Descriptions............................................................................................................399
Table 3-224. EPWM4_AC Register Field Descriptions............................................................................................................400
Table 3-225. EPWM5_AC Register Field Descriptions............................................................................................................401
Table 3-226. EPWM6_AC Register Field Descriptions............................................................................................................402
Table 3-227. EPWM7_AC Register Field Descriptions............................................................................................................403
Table 3-228. EPWM8_AC Register Field Descriptions............................................................................................................404
Table 3-229. EQEP1_AC Register Field Descriptions............................................................................................................. 405
Table 3-230. EQEP2_AC Register Field Descriptions............................................................................................................. 406
Table 3-231. ECAP1_AC Register Field Descriptions............................................................................................................. 407
Table 3-232. ECAP2_AC Register Field Descriptions............................................................................................................. 408
Table 3-233. ECAP3_AC Register Field Descriptions............................................................................................................. 409
Table 3-234. SDFM1_AC Register Field Descriptions.............................................................................................................410
Table 3-235. SDFM2_AC Register Field Descriptions............................................................................................................. 411
Table 3-236. CLB1_AC Register Field Descriptions................................................................................................................ 412
Table 3-237. CLB2_AC Register Field Descriptions................................................................................................................ 413
Table 3-238. CLB3_AC Register Field Descriptions................................................................................................................ 414
Table 3-239. CLB4_AC Register Field Descriptions................................................................................................................ 415
Table 3-240. SCIA_AC Register Field Descriptions.................................................................................................................416

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Table 3-241. SCIB_AC Register Field Descriptions.................................................................................................................417

Table 3-242. SPIA_AC Register Field Descriptions.................................................................................................................418
Table 3-243. SPIB_AC Register Field Descriptions.................................................................................................................419
Table 3-244. I2CA_AC Register Field Descriptions................................................................................................................. 420
Table 3-245. I2CB_AC Register Field Descriptions................................................................................................................. 421
Table 3-246. PMBUS_A_AC Register Field Descriptions........................................................................................................422
Table 3-247. LIN_A_AC Register Field Descriptions............................................................................................................... 423
Table 3-248. LIN_B_AC Register Field Descriptions............................................................................................................... 424
Table 3-249. DCANA_AC Register Field Descriptions............................................................................................................ 425
Table 3-250. MCANA_AC Register Field Descriptions............................................................................................................ 426
Table 3-251. FSIATX_AC Register Field Descriptions.............................................................................................................427
Table 3-252. FSIARX_AC Register Field Descriptions............................................................................................................ 428
Table 3-253. HRPWM_A_AC Register Field Descriptions.......................................................................................................429
Table 3-254. HIC_A_AC Register Field Descriptions.............................................................................................................. 430
Table 3-255. AESA_AC Register Field Descriptions............................................................................................................... 431
Table 3-256. PERIPH_AC_LOCK Register Field Descriptions................................................................................................432
Table 3-257. PIE_CTRL_REGS Registers.............................................................................................................................. 433
Table 3-258. PIE_CTRL_REGS Access Type Codes..............................................................................................................433
Table 3-259. PIECTRL Register Field Descriptions.................................................................................................................435
Table 3-260. PIEACK Register Field Descriptions...................................................................................................................436
Table 3-261. PIEIER1 Register Field Descriptions.................................................................................................................. 437
Table 3-262. PIEIFR1 Register Field Descriptions.................................................................................................................. 438
Table 3-263. PIEIER2 Register Field Descriptions.................................................................................................................. 440
Table 3-264. PIEIFR2 Register Field Descriptions.................................................................................................................. 441
Table 3-265. PIEIER3 Register Field Descriptions.................................................................................................................. 443
Table 3-266. PIEIFR3 Register Field Descriptions.................................................................................................................. 444
Table 3-267. PIEIER4 Register Field Descriptions.................................................................................................................. 446
Table 3-268. PIEIFR4 Register Field Descriptions.................................................................................................................. 447
Table 3-269. PIEIER5 Register Field Descriptions.................................................................................................................. 449
Table 3-270. PIEIFR5 Register Field Descriptions.................................................................................................................. 450
Table 3-271. PIEIER6 Register Field Descriptions.................................................................................................................. 452
Table 3-272. PIEIFR6 Register Field Descriptions.................................................................................................................. 453
Table 3-273. PIEIER7 Register Field Descriptions.................................................................................................................. 455
Table 3-274. PIEIFR7 Register Field Descriptions.................................................................................................................. 456
Table 3-275. PIEIER8 Register Field Descriptions.................................................................................................................. 458
Table 3-276. PIEIFR8 Register Field Descriptions.................................................................................................................. 459
Table 3-277. PIEIER9 Register Field Descriptions.................................................................................................................. 461
Table 3-278. PIEIFR9 Register Field Descriptions.................................................................................................................. 462
Table 3-279. PIEIER10 Register Field Descriptions................................................................................................................ 464
Table 3-280. PIEIFR10 Register Field Descriptions................................................................................................................ 465
Table 3-281. PIEIER11 Register Field Descriptions.................................................................................................................467
Table 3-282. PIEIFR11 Register Field Descriptions.................................................................................................................468
Table 3-283. PIEIER12 Register Field Descriptions................................................................................................................ 470
Table 3-284. PIEIFR12 Register Field Descriptions................................................................................................................ 471
Table 3-285. SYNC_SOC_REGS Registers............................................................................................................................473
Table 3-286. SYNC_SOC_REGS Access Type Codes........................................................................................................... 473
Table 3-287. SYNCSELECT Register Field Descriptions........................................................................................................ 474
Table 3-288. ADCSOCOUTSELECT Register Field Descriptions........................................................................................... 476
Table 3-289. SYNCSOCLOCK Register Field Descriptions.................................................................................................... 478
Table 3-290. SYS_STATUS_REGS Registers.........................................................................................................................479
Table 3-291. SYS_STATUS_REGS Access Type Codes........................................................................................................ 479
Table 3-292. SYS_ERR_INT_FLG Register Field Descriptions.............................................................................................. 480
Table 3-293. SYS_ERR_INT_CLR Register Field Descriptions.............................................................................................. 481
Table 3-294. SYS_ERR_INT_SET Register Field Descriptions.............................................................................................. 482
Table 3-295. SYS_ERR_MASK Register Field Descriptions................................................................................................... 484
Table 3-296. TEST_ERROR_REGS Registers....................................................................................................................... 486
Table 3-297. TEST_ERROR_REGS Access Type Codes.......................................................................................................486
Table 3-298. CPU_RAM_TEST_ERROR_STS Register Field Descriptions........................................................................... 487
Table 3-299. CPU_RAM_TEST_ERROR_STS_CLR Register Field Descriptions.................................................................. 488
Table 3-300. CPU_RAM_TEST_ERROR_ADDR Register Field Descriptions........................................................................ 489
Table 3-301. UID_REGS Registers......................................................................................................................................... 490

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Table 3-302. UID_REGS Access Type Codes.........................................................................................................................490

Table 3-303. UID_PSRAND0 Register Field Descriptions.......................................................................................................491
Table 3-304. UID_PSRAND1 Register Field Descriptions.......................................................................................................492
Table 3-305. UID_PSRAND2 Register Field Descriptions.......................................................................................................493
Table 3-306. UID_PSRAND3 Register Field Descriptions.......................................................................................................494
Table 3-307. UID_PSRAND4 Register Field Descriptions.......................................................................................................495
Table 3-308. UID_PSRAND5 Register Field Descriptions.......................................................................................................496
Table 3-309. UID_UNIQUE Register Field Descriptions..........................................................................................................497
Table 3-310. UID_CHECKSUM Register Field Descriptions................................................................................................... 498
Table 3-311. WD_REGS Registers.......................................................................................................................................... 499
Table 3-312. WD_REGS Access Type Codes......................................................................................................................... 499
Table 3-313. SCSR Register Field Descriptions...................................................................................................................... 500
Table 3-314. WDCNTR Register Field Descriptions................................................................................................................ 501
Table 3-315. WDKEY Register Field Descriptions...................................................................................................................502
Table 3-316. WDCR Register Field Descriptions.....................................................................................................................503
Table 3-317. WDWCR Register Field Descriptions................................................................................................................. 505
Table 3-318. XINT_REGS Registers....................................................................................................................................... 506
Table 3-319. XINT_REGS Access Type Codes.......................................................................................................................506
Table 3-320. XINT1CR Register Field Descriptions.................................................................................................................507
Table 3-321. XINT2CR Register Field Descriptions.................................................................................................................508
Table 3-322. XINT3CR Register Field Descriptions.................................................................................................................509
Table 3-323. XINT4CR Register Field Descriptions.................................................................................................................510
Table 3-324. XINT5CR Register Field Descriptions................................................................................................................. 511
Table 3-325. XINT1CTR Register Field Descriptions.............................................................................................................. 512
Table 3-326. XINT2CTR Register Field Descriptions.............................................................................................................. 513
Table 3-327. XINT3CTR Register Field Descriptions.............................................................................................................. 514
Table 3-328. LFU_REGS Registers.........................................................................................................................................515
Table 3-329. LFU_REGS Access Type Codes........................................................................................................................ 515
Table 3-330. LFUConfig Register Field Descriptions...............................................................................................................516
Table 3-331. LFUStatus Register Field Descriptions............................................................................................................... 517
Table 3-332. SWConfig1_SYSRSn Register Field Descriptions..............................................................................................518
Table 3-333. SWConfig2_SYSRSn Register Field Descriptions..............................................................................................519
Table 3-334. SWConfig1_XRSn Register Field Descriptions.................................................................................................. 520
Table 3-335. SWConfig2_XRSn Register Field Descriptions.................................................................................................. 521
Table 3-336. SWConfig1_PORESETn Register Field Descriptions.........................................................................................522
Table 3-337. SWConfig2_PORESETn Register Field Descriptions.........................................................................................523
Table 3-338. LFU_LOCK Register Field Descriptions............................................................................................................. 524
Table 3-339. LFU_COMMIT Register Field Descriptions.........................................................................................................525
Table 3-340. CPUTIMER Registers to Driverlib Functions...................................................................................................... 527
Table 3-341. DCSM Registers to Driverlib Functions.............................................................................................................. 527
Table 3-342. MEMCFG Registers to Driverlib Functions......................................................................................................... 531
Table 3-343. NMI Registers to Driverlib Functions.................................................................................................................. 535
Table 3-344. PIE Registers to Driverlib Functions................................................................................................................... 536
Table 3-345. SYSCTL Registers to Driverlib Functions........................................................................................................... 537
Table 3-346. WWD Registers to Driverlib Functions................................................................................................................545
Table 3-347. XINT Registers to Driverlib Functions.................................................................................................................546
Table 4-1. Boot System Overview............................................................................................................................................548
Table 4-2. ROM Memory..........................................................................................................................................................548
Table 4-3. Device Boot ROM Sequence.................................................................................................................................. 549
Table 4-4. Device Default Boot Modes.................................................................................................................................... 549
Table 4-5. Custom Boot Modes............................................................................................................................................... 550
Table 4-6. BOOTPIN-CONFIG Bit Fields.................................................................................................................................551
Table 4-7. Standalone Boot Mode Select Pin Decoding.......................................................................................................... 552
Table 4-8. BOOTDEF Bit Fields...............................................................................................................................................553
Table 4-9. Zero Boot Pin Boot Table Result.............................................................................................................................554
Table 4-10. One Boot Pin Boot Table Result........................................................................................................................... 554
Table 4-11. Three Boot Pins Boot Table Result....................................................................................................................... 555
Table 4-12. Boot ROM Reset Causes and Actions..................................................................................................................559
Table 4-13. Boot ROM Exceptions and Actions.......................................................................................................................559
Table 4-14. Boot ROM Registers............................................................................................................................................. 560
Table 4-15. DCSM Z1/Z2 GPREG2 Bit Fields......................................................................................................................... 561

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Table 4-16. Flash Entry Point Addresses.................................................................................................................................561

Table 4-17. RAM Entry Point Address..................................................................................................................................... 562
Table 4-18. Wait Boot Options................................................................................................................................................. 562
Table 4-19. Wait Point Addresses............................................................................................................................................562
Table 4-20. Secure Flash Boot Details.................................................................................................................................... 563
Table 4-21. Secure Flash Tag and Key Details........................................................................................................................563
Table 4-22. Secure Flash Authentication Failure Actions........................................................................................................ 564
Table 4-23. Secure Flash on all CPUs Recommended Flow...................................................................................................564
Table 4-24. LFU Application Image Format............................................................................................................................. 565
Table 4-25. LFU Entry Point Addresses...................................................................................................................................565
Table 4-26. Boot ROM Memory Map....................................................................................................................................... 566
Table 4-27. Secure ROM Memory Map................................................................................................................................... 566
Table 4-28. CLA Data ROM Memory Map............................................................................................................................... 566
Table 4-29. Reserved RAM Memory Map................................................................................................................................567
Table 4-30. ROM Symbol Tables............................................................................................................................................. 567
Table 4-31. Boot Mode Availability...........................................................................................................................................567
Table 4-32. Wait Boot Options................................................................................................................................................. 568
Table 4-33. SPI 8-Bit Data Stream...........................................................................................................................................570
Table 4-34. I2C 8-Bit Data Stream...........................................................................................................................................575
Table 4-35. Parallel GPIO Boot 8-Bit Data Stream.................................................................................................................. 576
Table 4-36. Bit-Rate Value for Internal Oscillators................................................................................................................... 580
Table 4-37. CAN 8-Bit Data Stream.........................................................................................................................................581
Table 4-38. CAN-FD 8-Bit Data Stream...................................................................................................................................582
Table 4-39. SCI Boot Options.................................................................................................................................................. 583
Table 4-40. CAN Boot Options.................................................................................................................................................583
Table 4-41. CAN-FD Boot Options...........................................................................................................................................583
Table 4-42. I2C Boot Options...................................................................................................................................................583
Table 4-43. SPI Boot Options.................................................................................................................................................. 583
Table 4-44. Parallel Boot Options............................................................................................................................................ 584
Table 4-45. Secure Copy Code Function.................................................................................................................................585
Table 4-46. Secure CRC Calculation Function........................................................................................................................ 585
Table 4-47. Secure CRC Calculation Function........................................................................................................................ 586
Table 4-48. CPU Boot Clock Sources......................................................................................................................................586
Table 4-49. CPU Clock State After Boot.................................................................................................................................. 586
Table 4-50. Boot Status Address............................................................................................................................................. 587
Table 4-51. Boot Status Bit Fields............................................................................................................................................587
Table 4-52. Boot Mode and MPOST Status Addresses...........................................................................................................588
Table 4-53. Boot ROM Version Information............................................................................................................................. 588
Table 4-54. LSB/MSB Loading Sequence in 8-Bit Data Stream.............................................................................................. 589
Table 4-55. Boot Loader Options............................................................................................................................................. 591
Table 5-1. RAM/Flash Status................................................................................................................................................... 595
Table 5-2. Security Levels........................................................................................................................................................595
Table 5-3. Default Value of ZxOTP (Programmed by TI)......................................................................................................... 596
Table 5-4. DCSM Base Address Table.................................................................................................................................... 609
Table 5-5. DCSM_Z1_REGS Registers...................................................................................................................................610
Table 5-6. DCSM_Z1_REGS Access Type Codes.................................................................................................................. 610
Table 5-7. Z1_LINKPOINTER Register Field Descriptions......................................................................................................612
Table 5-8. Z1_OTPSECLOCK Register Field Descriptions..................................................................................................... 613
Table 5-9. Z1_JLM_ENABLE Register Field Descriptions.......................................................................................................614
Table 5-10. Z1_LINKPOINTERERR Register Field Descriptions............................................................................................ 615
Table 5-11. Z1_GPREG1 Register Field Descriptions............................................................................................................. 616
Table 5-12. Z1_GPREG2 Register Field Descriptions.............................................................................................................617
Table 5-13. Z1_GPREG3 Register Field Descriptions.............................................................................................................618
Table 5-14. Z1_GPREG4 Register Field Descriptions.............................................................................................................619
Table 5-15. Z1_CSMKEY0 Register Field Descriptions...........................................................................................................620
Table 5-16. Z1_CSMKEY1 Register Field Descriptions...........................................................................................................621
Table 5-17. Z1_CSMKEY2 Register Field Descriptions...........................................................................................................622
Table 5-18. Z1_CSMKEY3 Register Field Descriptions...........................................................................................................623
Table 5-19. Z1_CR Register Field Descriptions.......................................................................................................................624
Table 5-20. Z1_GRABSECT1R Register Field Descriptions................................................................................................... 626
Table 5-21. Z1_GRABSECT2R Register Field Descriptions................................................................................................... 629

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Table 5-22. Z1_GRABSECT3R Register Field Descriptions................................................................................................... 632

Table 5-23. Z1_GRABRAM1R Register Field Descriptions..................................................................................................... 635
Table 5-24. Z1_EXEONLYSECT1R Register Field Descriptions............................................................................................. 637
Table 5-25. Z1_EXEONLYSECT2R Register Field Descriptions............................................................................................. 642
Table 5-26. Z1_EXEONLYRAM1R Register Field Descriptions...............................................................................................645
Table 5-27. Z1_JTAGKEY0 Register Field Descriptions..........................................................................................................647
Table 5-28. Z1_JTAGKEY1 Register Field Descriptions..........................................................................................................648
Table 5-29. Z1_JTAGKEY2 Register Field Descriptions..........................................................................................................649
Table 5-30. Z1_JTAGKEY3 Register Field Descriptions..........................................................................................................650
Table 5-31. Z1_CMACKEY0 Register Field Descriptions........................................................................................................ 651
Table 5-32. Z1_CMACKEY1 Register Field Descriptions........................................................................................................ 652
Table 5-33. Z1_CMACKEY2 Register Field Descriptions........................................................................................................ 653
Table 5-34. Z1_CMACKEY3 Register Field Descriptions........................................................................................................ 654
Table 5-35. DCSM_Z2_REGS Registers.................................................................................................................................655
Table 5-36. DCSM_Z2_REGS Access Type Codes................................................................................................................ 655
Table 5-37. Z2_LINKPOINTER Register Field Descriptions....................................................................................................657
Table 5-38. Z2_OTPSECLOCK Register Field Descriptions................................................................................................... 658
Table 5-39. Z2_LINKPOINTERERR Register Field Descriptions............................................................................................ 659
Table 5-40. Z2_GPREG1 Register Field Descriptions.............................................................................................................660
Table 5-41. Z2_GPREG2 Register Field Descriptions.............................................................................................................661
Table 5-42. Z2_GPREG3 Register Field Descriptions.............................................................................................................662
Table 5-43. Z2_GPREG4 Register Field Descriptions.............................................................................................................663
Table 5-44. Z2_CSMKEY0 Register Field Descriptions...........................................................................................................664
Table 5-45. Z2_CSMKEY1 Register Field Descriptions...........................................................................................................665
Table 5-46. Z2_CSMKEY2 Register Field Descriptions...........................................................................................................666
Table 5-47. Z2_CSMKEY3 Register Field Descriptions...........................................................................................................667
Table 5-48. Z2_CR Register Field Descriptions.......................................................................................................................668
Table 5-49. Z2_GRABSECT1R Register Field Descriptions................................................................................................... 670
Table 5-50. Z2_GRABSECT2R Register Field Descriptions................................................................................................... 673
Table 5-51. Z2_GRABSECT3R Register Field Descriptions................................................................................................... 676
Table 5-52. Z2_GRABRAM1R Register Field Descriptions..................................................................................................... 679
Table 5-53. Z2_EXEONLYSECT1R Register Field Descriptions............................................................................................. 681
Table 5-54. Z2_EXEONLYSECT2R Register Field Descriptions............................................................................................. 686
Table 5-55. Z2_EXEONLYRAM1R Register Field Descriptions...............................................................................................689
Table 5-56. DCSM_COMMON_REGS Registers.................................................................................................................... 691
Table 5-57. DCSM_COMMON_REGS Access Type Codes....................................................................................................691
Table 5-58. FLSEM Register Field Descriptions...................................................................................................................... 692
Table 5-59. SECTSTAT1 Register Field Descriptions..............................................................................................................693
Table 5-60. SECTSTAT2 Register Field Descriptions..............................................................................................................696
Table 5-61. SECTSTAT3 Register Field Descriptions..............................................................................................................699
Table 5-62. RAMSTAT1 Register Field Descriptions............................................................................................................... 702
Table 5-63. SECERRSTAT Register Field Descriptions.......................................................................................................... 704
Table 5-64. SECERRCLR Register Field Descriptions............................................................................................................705
Table 5-65. SECERRFRC Register Field Descriptions............................................................................................................706
Table 5-66. DCSM_Z1_OTP Registers....................................................................................................................................707
Table 5-67. DCSM_Z1_OTP Access Type Codes................................................................................................................... 707
Table 5-68. Z1OTP_LINKPOINTER1 Register Field Descriptions.......................................................................................... 708
Table 5-69. Z1OTP_LINKPOINTER2 Register Field Descriptions.......................................................................................... 709
Table 5-70. Z1OTP_LINKPOINTER3 Register Field Descriptions.......................................................................................... 710
Table 5-71. Z1OTP_JLM_ENABLE Register Field Descriptions..............................................................................................711
Table 5-72. Z1OTP_GPREG1 Register Field Descriptions..................................................................................................... 712
Table 5-73. Z1OTP_GPREG2 Register Field Descriptions..................................................................................................... 713
Table 5-74. Z1OTP_GPREG3 Register Field Descriptions..................................................................................................... 714
Table 5-75. Z1OTP_GPREG4 Register Field Descriptions..................................................................................................... 715
Table 5-76. Z1OTP_PSWDLOCK Register Field Descriptions................................................................................................716
Table 5-77. Z1OTP_CRCLOCK Register Field Descriptions...................................................................................................717
Table 5-78. Z1OTP_JTAGPSWDH0 Register Field Descriptions............................................................................................ 718
Table 5-79. Z1OTP_JTAGPSWDH1 Register Field Descriptions............................................................................................ 719
Table 5-80. Z1OTP_CMACKEY0 Register Field Descriptions.................................................................................................720
Table 5-81. Z1OTP_CMACKEY1 Register Field Descriptions.................................................................................................721
Table 5-82. Z1OTP_CMACKEY2 Register Field Descriptions.................................................................................................722

60 TMS320F28003x Real-Time Microcontrollers SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023

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Table 5-83. Z1OTP_CMACKEY3 Register Field Descriptions.................................................................................................723

Table 5-84. DCSM_Z2_OTP Registers....................................................................................................................................724
Table 5-85. DCSM_Z2_OTP Access Type Codes................................................................................................................... 724
Table 5-86. Z2OTP_LINKPOINTER1 Register Field Descriptions.......................................................................................... 725
Table 5-87. Z2OTP_LINKPOINTER2 Register Field Descriptions.......................................................................................... 726
Table 5-88. Z2OTP_LINKPOINTER3 Register Field Descriptions.......................................................................................... 727
Table 5-89. Z2OTP_GPREG1 Register Field Descriptions..................................................................................................... 728
Table 5-90. Z2OTP_GPREG2 Register Field Descriptions..................................................................................................... 729
Table 5-91. Z2OTP_GPREG3 Register Field Descriptions..................................................................................................... 730
Table 5-92. Z2OTP_GPREG4 Register Field Descriptions..................................................................................................... 731
Table 5-93. Z2OTP_PSWDLOCK Register Field Descriptions................................................................................................732
Table 5-94. Z2OTP_CRCLOCK Register Field Descriptions...................................................................................................733
Table 6-1. FLASH Base Address Table................................................................................................................................... 752
Table 6-2. FLASH_CTRL_REGS Registers.............................................................................................................................753
Table 6-3. FLASH_CTRL_REGS Access Type Codes............................................................................................................ 753
Table 6-4. FRDCNTL Register Field Descriptions................................................................................................................... 754
Table 6-5. FBAC Register Field Descriptions.......................................................................................................................... 755
Table 6-6. FBFALLBACK Register Field Descriptions............................................................................................................. 756
Table 6-7. FBPRDY Register Field Descriptions..................................................................................................................... 757
Table 6-8. FPAC1 Register Field Descriptions.........................................................................................................................758
Table 6-9. FPAC2 Register Field Descriptions.........................................................................................................................759
Table 6-10. FMSTAT Register Field Descriptions.................................................................................................................... 760
Table 6-11. FRD_INTF_CTRL Register Field Descriptions......................................................................................................762
Table 6-12. FLASH_ECC_REGS Registers............................................................................................................................ 763
Table 6-13. FLASH_ECC_REGS Access Type Codes............................................................................................................763
Table 6-14. ECC_ENABLE Register Field Descriptions.......................................................................................................... 765
Table 6-15. SINGLE_ERR_ADDR_LOW Register Field Descriptions.....................................................................................766
Table 6-16. SINGLE_ERR_ADDR_HIGH Register Field Descriptions.................................................................................... 767
Table 6-17. UNC_ERR_ADDR_LOW Register Field Descriptions.......................................................................................... 768
Table 6-18. UNC_ERR_ADDR_HIGH Register Field Descriptions......................................................................................... 769
Table 6-19. ERR_STATUS Register Field Descriptions...........................................................................................................770
Table 6-20. ERR_POS Register Field Descriptions.................................................................................................................772
Table 6-21. ERR_STATUS_CLR Register Field Descriptions..................................................................................................773
Table 6-22. ERR_CNT Register Field Descriptions................................................................................................................. 774
Table 6-23. ERR_THRESHOLD Register Field Descriptions.................................................................................................. 775
Table 6-24. ERR_INTFLG Register Field Descriptions............................................................................................................776
Table 6-25. ERR_INTCLR Register Field Descriptions........................................................................................................... 777
Table 6-26. FDATAH_TEST Register Field Descriptions......................................................................................................... 778
Table 6-27. FDATAL_TEST Register Field Descriptions..........................................................................................................779
Table 6-28. FADDR_TEST Register Field Descriptions...........................................................................................................780
Table 6-29. FECC_TEST Register Field Descriptions............................................................................................................. 781
Table 6-30. FECC_CTRL Register Field Descriptions.............................................................................................................782
Table 6-31. FOUTH_TEST Register Field Descriptions.......................................................................................................... 783
Table 6-32. FOUTL_TEST Register Field Descriptions........................................................................................................... 784
Table 6-33. FECC_STATUS Register Field Descriptions.........................................................................................................785
Table 6-34. FLASH Registers to Driverlib Functions............................................................................................................... 785
Table 7-1. Configuration Options............................................................................................................................................. 794
Table 7-2. Pipeline Behavior of the MDEBUGSTOP1 Instruction............................................................................................ 800
Table 7-3. Write Followed by Read - Read Occurs First..........................................................................................................804
Table 7-4. Write Followed by Read - Write Occurs First.......................................................................................................... 804
Table 7-5. ADC to CLA Early Interrupt Response....................................................................................................................807
Table 7-6. Operand Nomenclature...........................................................................................................................................813
Table 7-7. INSTRUCTION dest, source1, source2 Short Description..................................................................................... 814
Table 7-8. Addressing Modes.................................................................................................................................................. 815
Table 7-9. Shift Field Encoding................................................................................................................................................ 815
Table 7-10. Operand Encoding................................................................................................................................................ 816
Table 7-11. Condition Field Encoding...................................................................................................................................... 816
Table 7-12. Pipeline Activity for MBCNDD, Branch Not Taken................................................................................................ 832
Table 7-13. Pipeline Activity for MBCNDD, Branch Taken.......................................................................................................832
Table 7-14. Pipeline Activity for MCCNDD, Call Not Taken..................................................................................................... 837
Table 7-15. Pipeline Activity for MCCNDD, Call Taken............................................................................................................838

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Table 7-16. Pipeline Activity for MMOV16 MARx, MRa , #16I................................................................................................. 872
Table 7-17. Pipeline Activity for MMOV16 MAR0/MAR1, mem16........................................................................................... 875
Table 7-18. Pipeline Activity for MMOVI16 MAR0/MAR1, #16I............................................................................................... 891
Table 7-19. Pipeline Activity for MRCNDD, Return Not Taken.................................................................................................914
Table 7-20. Pipeline Activity for MRCNDD, Return Taken....................................................................................................... 914
Table 7-21. Pipeline Activity for MSTOP.................................................................................................................................. 916
Table 7-22. CLA Base Address Table...................................................................................................................................... 932
Table 7-23. CLA_ONLY_REGS Registers............................................................................................................................... 934
Table 7-24. CLA_ONLY_REGS Access Type Codes...............................................................................................................934
Table 7-25. _MVECTBGRNDACTIVE Register Field Descriptions......................................................................................... 935
Table 7-26. _MPSACTL Register Field Descriptions............................................................................................................... 936
Table 7-27. _MPSA1 Register Field Descriptions....................................................................................................................937
Table 7-28. _MPSA2 Register Field Descriptions....................................................................................................................938
Table 7-29. SOFTINTEN Register Field Descriptions..............................................................................................................939
Table 7-30. SOFTINTFRC Register Field Descriptions........................................................................................................... 941
Table 7-31. CLA_SOFTINT_REGS Registers......................................................................................................................... 942
Table 7-32. CLA_SOFTINT_REGS Access Type Codes.........................................................................................................942
Table 7-33. SOFTINTEN Register Field Descriptions..............................................................................................................943
Table 7-34. SOFTINTFRC Register Field Descriptions........................................................................................................... 945
Table 7-35. CLA_REGS Registers...........................................................................................................................................946
Table 7-36. CLA_REGS Access Type Codes.......................................................................................................................... 946
Table 7-37. MVECT1 Register Field Descriptions................................................................................................................... 948
Table 7-38. MVECT2 Register Field Descriptions................................................................................................................... 949
Table 7-39. MVECT3 Register Field Descriptions................................................................................................................... 950
Table 7-40. MVECT4 Register Field Descriptions................................................................................................................... 951
Table 7-41. MVECT5 Register Field Descriptions................................................................................................................... 952
Table 7-42. MVECT6 Register Field Descriptions................................................................................................................... 953
Table 7-43. MVECT7 Register Field Descriptions................................................................................................................... 954
Table 7-44. MVECT8 Register Field Descriptions................................................................................................................... 955
Table 7-45. MCTL Register Field Descriptions........................................................................................................................ 956
Table 7-46. _MVECTBGRNDACTIVE Register Field Descriptions......................................................................................... 957
Table 7-47. SOFTINTEN Register Field Descriptions..............................................................................................................958
Table 7-48. _MSTSBGRND Register Field Descriptions......................................................................................................... 960
Table 7-49. _MCTLBGRND Register Field Descriptions......................................................................................................... 961
Table 7-50. _MVECTBGRND Register Field Descriptions...................................................................................................... 962
Table 7-51. MIFR Register Field Descriptions......................................................................................................................... 963
Table 7-52. MIOVF Register Field Descriptions.......................................................................................................................967
Table 7-53. MIFRC Register Field Descriptions.......................................................................................................................970
Table 7-54. MICLR Register Field Descriptions.......................................................................................................................972
Table 7-55. MICLROVF Register Field Descriptions............................................................................................................... 974
Table 7-56. MIER Register Field Descriptions......................................................................................................................... 976
Table 7-57. MIRUN Register Field Descriptions...................................................................................................................... 979
Table 7-58. _MPC Register Field Descriptions........................................................................................................................ 981
Table 7-59. _MAR0 Register Field Descriptions...................................................................................................................... 982
Table 7-60. _MAR1 Register Field Descriptions...................................................................................................................... 983
Table 7-61. _MSTF Register Field Descriptions...................................................................................................................... 984
Table 7-62. _MR0 Register Field Descriptions........................................................................................................................ 987
Table 7-63. _MR1 Register Field Descriptions........................................................................................................................ 988
Table 7-64. _MR2 Register Field Descriptions........................................................................................................................ 989
Table 7-65. _MR3 Register Field Descriptions........................................................................................................................ 990
Table 7-66. _MPSACTL Register Field Descriptions............................................................................................................... 991
Table 7-67. _MPSA1 Register Field Descriptions....................................................................................................................992
Table 7-68. _MPSA2 Register Field Descriptions....................................................................................................................993
Table 7-69. CLA Registers to Driverlib Functions.................................................................................................................... 993
Table 8-1. DCC Base Address Table..................................................................................................................................... 1008
Table 8-2. DCC_REGS Registers..........................................................................................................................................1009
Table 8-3. DCC_REGS Access Type Codes......................................................................................................................... 1009
Table 8-4. DCCGCTRL Register Field Descriptions.............................................................................................................. 1010
Table 8-5. DCCCNTSEED0 Register Field Descriptions....................................................................................................... 1011
Table 8-6. DCCVALIDSEED0 Register Field Descriptions.................................................................................................... 1012
Table 8-7. DCCCNTSEED1 Register Field Descriptions....................................................................................................... 1013

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Table 8-8. DCCSTATUS Register Field Descriptions.............................................................................................................1014

Table 8-9. DCCCNT0 Register Field Descriptions.................................................................................................................1015
Table 8-10. DCCVALID0 Register Field Descriptions............................................................................................................ 1016
Table 8-11. DCCCNT1 Register Field Descriptions............................................................................................................... 1017
Table 8-12. DCCCLKSRC1 Register Field Descriptions........................................................................................................1018
Table 8-13. DCCCLKSRC0 Register Field Descriptions........................................................................................................1019
Table 8-14. DCC Registers to Driverlib Functions................................................................................................................. 1019
Table 9-1. BGCRC Register Groups......................................................................................................................................1027
Table 9-2. Data Address Location Example 1........................................................................................................................1031
Table 9-3. Data Address Location Example 2........................................................................................................................1031
Table 9-4. Data Address Location Example 3........................................................................................................................1031
Table 9-5. BGCRC Base Address Table................................................................................................................................ 1033
Table 9-6. BGCRC_REGS Registers.....................................................................................................................................1034
Table 9-7. BGCRC_REGS Access Type Codes.................................................................................................................... 1034
Table 9-8. BGCRC_EN Register Field Descriptions.............................................................................................................. 1036
Table 9-9. BGCRC_CTRL1 Register Field Descriptions........................................................................................................1037
Table 9-10. BGCRC_CTRL2 Register Field Descriptions......................................................................................................1038
Table 9-11. BGCRC_START_ADDR Register Field Descriptions..........................................................................................1039
Table 9-12. BGCRC_SEED Register Field Descriptions....................................................................................................... 1040
Table 9-13. BGCRC_GOLDEN Register Field Descriptions..................................................................................................1041
Table 9-14. BGCRC_RESULT Register Field Descriptions................................................................................................... 1042
Table 9-15. BGCRC_CURR_ADDR Register Field Descriptions.......................................................................................... 1043
Table 9-16. BGCRC_WD_CFG Register Field Descriptions................................................................................................. 1044
Table 9-17. BGCRC_WD_MIN Register Field Descriptions.................................................................................................. 1045
Table 9-18. BGCRC_WD_MAX Register Field Descriptions................................................................................................. 1046
Table 9-19. BGCRC_WD_CNT Register Field Descriptions..................................................................................................1047
Table 9-20. BGCRC_NMIFLG Register Field Descriptions................................................................................................... 1048
Table 9-21. BGCRC_NMICLR Register Field Descriptions................................................................................................... 1049
Table 9-22. BGCRC_NMIFRC Register Field Descriptions................................................................................................... 1050
Table 9-23. BGCRC_INTEN Register Field Descriptions...................................................................................................... 1051
Table 9-24. BGCRC_INTFLG Register Field Descriptions.................................................................................................... 1052
Table 9-25. BGCRC_INTCLR Register Field Descriptions.................................................................................................... 1054
Table 9-26. BGCRC_INTFRC Register Field Descriptions....................................................................................................1055
Table 9-27. BGCRC_LOCK Register Field Descriptions....................................................................................................... 1056
Table 9-28. BGCRC_COMMIT Register Field Descriptions.................................................................................................. 1058
Table 9-29. BGCRC Registers to Driverlib Functions............................................................................................................ 1060
Table 10-1. GPIO access by different controllers...................................................................................................................1066
Table 10-2. AGPIO Configuration.......................................................................................................................................... 1068
Table 10-3. Sampling Period..................................................................................................................................................1072
Table 10-4. Sampling Frequency........................................................................................................................................... 1072
Table 10-5. Case 1: Three-Sample Sampling Window Width................................................................................................1073
Table 10-6. Case 2: Six-Sample Sampling Window Width.................................................................................................... 1073
Table 10-7. GPIO Muxed Pins............................................................................................................................................... 1075
Table 10-8. GPIO and Peripheral Muxing.............................................................................................................................. 1078
Table 10-9. Peripheral Muxing (Multiple Pins Assigned)....................................................................................................... 1079
Table 10-10. GPIO Base Address Table................................................................................................................................ 1081
Table 10-11. GPIO_CTRL_REGS Registers..........................................................................................................................1082
Table 10-12. GPIO_CTRL_REGS Access Type Codes.........................................................................................................1083
Table 10-13. GPACTRL Register Field Descriptions............................................................................................................. 1085
Table 10-14. GPAQSEL1 Register Field Descriptions........................................................................................................... 1086
Table 10-15. GPAQSEL2 Register Field Descriptions........................................................................................................... 1088
Table 10-16. GPAMUX1 Register Field Descriptions.............................................................................................................1090
Table 10-17. GPAMUX2 Register Field Descriptions.............................................................................................................1091
Table 10-18. GPADIR Register Field Descriptions.................................................................................................................1092
Table 10-19. GPAPUD Register Field Descriptions............................................................................................................... 1094
Table 10-20. GPAINV Register Field Descriptions.................................................................................................................1096
Table 10-21. GPAODR Register Field Descriptions...............................................................................................................1098
Table 10-22. GPAAMSEL Register Field Descriptions...........................................................................................................1100
Table 10-23. GPAGMUX1 Register Field Descriptions.......................................................................................................... 1102
Table 10-24. GPAGMUX2 Register Field Descriptions.......................................................................................................... 1103
Table 10-25. GPACSEL1 Register Field Descriptions............................................................................................................1104

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Table 10-26. GPACSEL2 Register Field Descriptions............................................................................................................1105

Table 10-27. GPACSEL3 Register Field Descriptions............................................................................................................1106
Table 10-28. GPACSEL4 Register Field Descriptions............................................................................................................1107
Table 10-29. GPALOCK Register Field Descriptions............................................................................................................. 1108
Table 10-30. GPACR Register Field Descriptions.................................................................................................................. 1110
Table 10-31. GPBCTRL Register Field Descriptions..............................................................................................................1112
Table 10-32. GPBQSEL1 Register Field Descriptions........................................................................................................... 1113
Table 10-33. GPBQSEL2 Register Field Descriptions........................................................................................................... 1115
Table 10-34. GPBMUX1 Register Field Descriptions............................................................................................................. 1117
Table 10-35. GPBMUX2 Register Field Descriptions............................................................................................................. 1118
Table 10-36. GPBDIR Register Field Descriptions.................................................................................................................1119
Table 10-37. GPBPUD Register Field Descriptions............................................................................................................... 1121
Table 10-38. GPBINV Register Field Descriptions.................................................................................................................1123
Table 10-39. GPBODR Register Field Descriptions...............................................................................................................1125
Table 10-40. GPBGMUX1 Register Field Descriptions.......................................................................................................... 1127
Table 10-41. GPBGMUX2 Register Field Descriptions.......................................................................................................... 1128
Table 10-42. GPBCSEL1 Register Field Descriptions........................................................................................................... 1129
Table 10-43. GPBCSEL2 Register Field Descriptions........................................................................................................... 1130
Table 10-44. GPBCSEL3 Register Field Descriptions........................................................................................................... 1131
Table 10-45. GPBCSEL4 Register Field Descriptions........................................................................................................... 1132
Table 10-46. GPBLOCK Register Field Descriptions............................................................................................................. 1133
Table 10-47. GPBCR Register Field Descriptions..................................................................................................................1135
Table 10-48. GPHCTRL Register Field Descriptions............................................................................................................. 1137
Table 10-49. GPHQSEL1 Register Field Descriptions........................................................................................................... 1138
Table 10-50. GPHQSEL2 Register Field Descriptions........................................................................................................... 1140
Table 10-51. GPHMUX1 Register Field Descriptions.............................................................................................................1142
Table 10-52. GPHMUX2 Register Field Descriptions.............................................................................................................1144
Table 10-53. GPHPUD Register Field Descriptions............................................................................................................... 1145
Table 10-54. GPHINV Register Field Descriptions.................................................................................................................1150
Table 10-55. GPHAMSEL Register Field Descriptions.......................................................................................................... 1154
Table 10-56. GPHGMUX1 Register Field Descriptions..........................................................................................................1160
Table 10-57. GPHGMUX2 Register Field Descriptions..........................................................................................................1162
Table 10-58. GPHCSEL1 Register Field Descriptions........................................................................................................... 1163
Table 10-59. GPHCSEL2 Register Field Descriptions........................................................................................................... 1164
Table 10-60. GPHCSEL3 Register Field Descriptions........................................................................................................... 1165
Table 10-61. GPHCSEL4 Register Field Descriptions........................................................................................................... 1166
Table 10-62. GPHLOCK Register Field Descriptions.............................................................................................................1167
Table 10-63. GPHCR Register Field Descriptions................................................................................................................. 1171
Table 10-64. GPIO_DATA_REGS Registers..........................................................................................................................1174
Table 10-65. GPIO_DATA_REGS Access Type Codes......................................................................................................... 1174
Table 10-66. GPADAT Register Field Descriptions................................................................................................................ 1175
Table 10-67. GPASET Register Field Descriptions................................................................................................................ 1177
Table 10-68. GPACLEAR Register Field Descriptions........................................................................................................... 1179
Table 10-69. GPATOGGLE Register Field Descriptions........................................................................................................ 1181
Table 10-70. GPBDAT Register Field Descriptions................................................................................................................1183
Table 10-71. GPBSET Register Field Descriptions................................................................................................................1185
Table 10-72. GPBCLEAR Register Field Descriptions...........................................................................................................1187
Table 10-73. GPBTOGGLE Register Field Descriptions........................................................................................................1189
Table 10-74. GPHDAT Register Field Descriptions................................................................................................................1191
Table 10-75. GPIO_DATA_READ_REGS Registers..............................................................................................................1197
Table 10-76. GPIO_DATA_READ_REGS Access Type Codes............................................................................................. 1197
Table 10-77. GPADAT_R Register Field Descriptions........................................................................................................... 1198
Table 10-78. GPBDAT_R Register Field Descriptions........................................................................................................... 1199
Table 10-79. GPHDAT_R Register Field Descriptions...........................................................................................................1200
Table 10-80. GPIO Registers to Driverlib Functions.............................................................................................................. 1200
Table 11-1. Input X-BAR Destinations....................................................................................................................................1207
Table 11-2. CLB Input X-BAR Destinations............................................................................................................................1208
Table 11-3. EPWM X-BAR Mux Configuration Table............................................................................................................. 1210
Table 11-4. CLB X-BAR Mux Configuration Table..................................................................................................................1213
Table 11-5. Output X-BAR Mux Configuration Table..............................................................................................................1215
Table 11-6. CLB Output X-BAR Mux Configuration Table......................................................................................................1216

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Table 11-7. XBAR Base Address Table..................................................................................................................................1219

Table 11-8. INPUT_XBAR_REGS Registers......................................................................................................................... 1220
Table 11-9. INPUT_XBAR_REGS Access Type Codes.........................................................................................................1220
Table 11-10. INPUT1SELECT Register Field Descriptions....................................................................................................1222
Table 11-11. INPUT2SELECT Register Field Descriptions....................................................................................................1223
Table 11-12. INPUT3SELECT Register Field Descriptions....................................................................................................1224
Table 11-13. INPUT4SELECT Register Field Descriptions....................................................................................................1225
Table 11-14. INPUT5SELECT Register Field Descriptions....................................................................................................1226
Table 11-15. INPUT6SELECT Register Field Descriptions....................................................................................................1227
Table 11-16. INPUT7SELECT Register Field Descriptions....................................................................................................1228
Table 11-17. INPUT8SELECT Register Field Descriptions....................................................................................................1229
Table 11-18. INPUT9SELECT Register Field Descriptions....................................................................................................1230
Table 11-19. INPUT10SELECT Register Field Descriptions..................................................................................................1231
Table 11-20. INPUT11SELECT Register Field Descriptions..................................................................................................1232
Table 11-21. INPUT12SELECT Register Field Descriptions..................................................................................................1233
Table 11-22. INPUT13SELECT Register Field Descriptions..................................................................................................1234
Table 11-23. INPUT14SELECT Register Field Descriptions..................................................................................................1235
Table 11-24. INPUT15SELECT Register Field Descriptions..................................................................................................1236
Table 11-25. INPUT16SELECT Register Field Descriptions..................................................................................................1237
Table 11-26. INPUTSELECTLOCK Register Field Descriptions............................................................................................1238
Table 11-27. XBAR_REGS Registers.................................................................................................................................... 1240
Table 11-28. XBAR_REGS Access Type Codes....................................................................................................................1240
Table 11-29. XBARFLG1 Register Field Descriptions............................................................................................................1241
Table 11-30. XBARFLG2 Register Field Descriptions............................................................................................................1244
Table 11-31. XBARFLG3 Register Field Descriptions............................................................................................................1248
Table 11-32. XBARFLG4 Register Field Descriptions............................................................................................................1252
Table 11-33. XBARCLR1 Register Field Descriptions........................................................................................................... 1256
Table 11-34. XBARCLR2 Register Field Descriptions........................................................................................................... 1258
Table 11-35. XBARCLR3 Register Field Descriptions........................................................................................................... 1261
Table 11-36. XBARCLR4 Register Field Descriptions........................................................................................................... 1264
Table 11-37. EPWM_XBAR_REGS Registers....................................................................................................................... 1267
Table 11-38. EPWM_XBAR_REGS Access Type Codes...................................................................................................... 1267
Table 11-39. TRIP4MUX0TO15CFG Register Field Descriptions..........................................................................................1269
Table 11-40. TRIP4MUX16TO31CFG Register Field Descriptions........................................................................................1272
Table 11-41. TRIP5MUX0TO15CFG Register Field Descriptions..........................................................................................1275
Table 11-42. TRIP5MUX16TO31CFG Register Field Descriptions........................................................................................1278
Table 11-43. TRIP7MUX0TO15CFG Register Field Descriptions..........................................................................................1281
Table 11-44. TRIP7MUX16TO31CFG Register Field Descriptions........................................................................................1284
Table 11-45. TRIP8MUX0TO15CFG Register Field Descriptions..........................................................................................1287
Table 11-46. TRIP8MUX16TO31CFG Register Field Descriptions........................................................................................1290
Table 11-47. TRIP9MUX0TO15CFG Register Field Descriptions..........................................................................................1293
Table 11-48. TRIP9MUX16TO31CFG Register Field Descriptions........................................................................................1296
Table 11-49. TRIP10MUX0TO15CFG Register Field Descriptions........................................................................................1299
Table 11-50. TRIP10MUX16TO31CFG Register Field Descriptions......................................................................................1302
Table 11-51. TRIP11MUX0TO15CFG Register Field Descriptions........................................................................................1305
Table 11-52. TRIP11MUX16TO31CFG Register Field Descriptions......................................................................................1308
Table 11-53. TRIP12MUX0TO15CFG Register Field Descriptions........................................................................................1311
Table 11-54. TRIP12MUX16TO31CFG Register Field Descriptions......................................................................................1314
Table 11-55. TRIP4MUXENABLE Register Field Descriptions.............................................................................................. 1317
Table 11-56. TRIP5MUXENABLE Register Field Descriptions.............................................................................................. 1322
Table 11-57. TRIP7MUXENABLE Register Field Descriptions.............................................................................................. 1327
Table 11-58. TRIP8MUXENABLE Register Field Descriptions.............................................................................................. 1332
Table 11-59. TRIP9MUXENABLE Register Field Descriptions.............................................................................................. 1337
Table 11-60. TRIP10MUXENABLE Register Field Descriptions............................................................................................ 1342
Table 11-61. TRIP11MUXENABLE Register Field Descriptions............................................................................................ 1347
Table 11-62. TRIP12MUXENABLE Register Field Descriptions............................................................................................ 1352
Table 11-63. TRIPOUTINV Register Field Descriptions.........................................................................................................1357
Table 11-64. TRIPLOCK Register Field Descriptions............................................................................................................ 1359
Table 11-65. CLB_XBAR_REGS Registers........................................................................................................................... 1360
Table 11-66. CLB_XBAR_REGS Access Type Codes...........................................................................................................1360
Table 11-67. AUXSIG0MUX0TO15CFG Register Field Descriptions.................................................................................... 1362

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Table 11-68. AUXSIG0MUX16TO31CFG Register Field Descriptions.................................................................................. 1365

Table 11-69. AUXSIG1MUX0TO15CFG Register Field Descriptions.................................................................................... 1368
Table 11-70. AUXSIG1MUX16TO31CFG Register Field Descriptions.................................................................................. 1371
Table 11-71. AUXSIG2MUX0TO15CFG Register Field Descriptions.................................................................................... 1374
Table 11-72. AUXSIG2MUX16TO31CFG Register Field Descriptions.................................................................................. 1377
Table 11-73. AUXSIG3MUX0TO15CFG Register Field Descriptions.................................................................................... 1380
Table 11-74. AUXSIG3MUX16TO31CFG Register Field Descriptions.................................................................................. 1383
Table 11-75. AUXSIG4MUX0TO15CFG Register Field Descriptions.................................................................................... 1386
Table 11-76. AUXSIG4MUX16TO31CFG Register Field Descriptions.................................................................................. 1389
Table 11-77. AUXSIG5MUX0TO15CFG Register Field Descriptions.................................................................................... 1392
Table 11-78. AUXSIG5MUX16TO31CFG Register Field Descriptions.................................................................................. 1395
Table 11-79. AUXSIG6MUX0TO15CFG Register Field Descriptions.................................................................................... 1398
Table 11-80. AUXSIG6MUX16TO31CFG Register Field Descriptions.................................................................................. 1401
Table 11-81. AUXSIG7MUX0TO15CFG Register Field Descriptions.................................................................................... 1404
Table 11-82. AUXSIG7MUX16TO31CFG Register Field Descriptions.................................................................................. 1407
Table 11-83. AUXSIG0MUXENABLE Register Field Descriptions.........................................................................................1410
Table 11-84. AUXSIG1MUXENABLE Register Field Descriptions.........................................................................................1415
Table 11-85. AUXSIG2MUXENABLE Register Field Descriptions.........................................................................................1420
Table 11-86. AUXSIG3MUXENABLE Register Field Descriptions.........................................................................................1425
Table 11-87. AUXSIG4MUXENABLE Register Field Descriptions.........................................................................................1430
Table 11-88. AUXSIG5MUXENABLE Register Field Descriptions.........................................................................................1435
Table 11-89. AUXSIG6MUXENABLE Register Field Descriptions.........................................................................................1440
Table 11-90. AUXSIG7MUXENABLE Register Field Descriptions.........................................................................................1445
Table 11-91. AUXSIGOUTINV Register Field Descriptions................................................................................................... 1450
Table 11-92. AUXSIGLOCK Register Field Descriptions....................................................................................................... 1452
Table 11-93. OUTPUT_XBAR_REGS Registers................................................................................................................... 1453
Table 11-94. OUTPUT_XBAR_REGS Access Type Codes...................................................................................................1453
Table 11-95. OUTPUT1MUX0TO15CFG Register Field Descriptions................................................................................... 1455
Table 11-96. OUTPUT1MUX16TO31CFG Register Field Descriptions................................................................................. 1458
Table 11-97. OUTPUT2MUX0TO15CFG Register Field Descriptions................................................................................... 1461
Table 11-98. OUTPUT2MUX16TO31CFG Register Field Descriptions................................................................................. 1464
Table 11-99. OUTPUT3MUX0TO15CFG Register Field Descriptions................................................................................... 1467
Table 11-100. OUTPUT3MUX16TO31CFG Register Field Descriptions............................................................................... 1470
Table 11-101. OUTPUT4MUX0TO15CFG Register Field Descriptions................................................................................. 1473
Table 11-102. OUTPUT4MUX16TO31CFG Register Field Descriptions............................................................................... 1476
Table 11-103. OUTPUT5MUX0TO15CFG Register Field Descriptions................................................................................. 1479
Table 11-104. OUTPUT5MUX16TO31CFG Register Field Descriptions............................................................................... 1482
Table 11-105. OUTPUT6MUX0TO15CFG Register Field Descriptions................................................................................. 1485
Table 11-106. OUTPUT6MUX16TO31CFG Register Field Descriptions............................................................................... 1488
Table 11-107. OUTPUT7MUX0TO15CFG Register Field Descriptions................................................................................. 1491
Table 11-108. OUTPUT7MUX16TO31CFG Register Field Descriptions............................................................................... 1494
Table 11-109. OUTPUT8MUX0TO15CFG Register Field Descriptions................................................................................. 1497
Table 11-110. OUTPUT8MUX16TO31CFG Register Field Descriptions............................................................................... 1500
Table 11-111. OUTPUT1MUXENABLE Register Field Descriptions......................................................................................1503
Table 11-112. OUTPUT2MUXENABLE Register Field Descriptions......................................................................................1508
Table 11-113. OUTPUT3MUXENABLE Register Field Descriptions......................................................................................1513
Table 11-114. OUTPUT4MUXENABLE Register Field Descriptions......................................................................................1518
Table 11-115. OUTPUT5MUXENABLE Register Field Descriptions......................................................................................1523
Table 11-116. OUTPUT6MUXENABLE Register Field Descriptions......................................................................................1528
Table 11-117. OUTPUT7MUXENABLE Register Field Descriptions......................................................................................1533
Table 11-118. OUTPUT8MUXENABLE Register Field Descriptions......................................................................................1538
Table 11-119. OUTPUTLATCH Register Field Descriptions.................................................................................................. 1543
Table 11-120. OUTPUTLATCHCLR Register Field Descriptions...........................................................................................1545
Table 11-121. OUTPUTLATCHFRC Register Field Descriptions...........................................................................................1547
Table 11-122. OUTPUTLATCHENABLE Register Field Descriptions....................................................................................1549
Table 11-123. OUTPUTINV Register Field Descriptions........................................................................................................1551
Table 11-124. OUTPUTLOCK Register Field Descriptions....................................................................................................1553
Table 11-125. INPUTXBAR Registers to Driverlib Functions.................................................................................................1554
Table 11-126. XBAR Registers to Driverlib Functions............................................................................................................1554
Table 11-127. EPWMXBAR Registers to Driverlib Functions................................................................................................ 1555
Table 11-128. CLBXBAR Registers to Driverlib Functions.....................................................................................................1556

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Table 11-129. OUTPUTXBAR Registers to Driverlib Functions.............................................................................................1557

Table 12-1. DMA Trigger Source Options.............................................................................................................................. 1566
Table 12-2. BURSTSIZE versus DATASIZE Behavior........................................................................................................... 1571
Table 12-3. DMA Base Address Table................................................................................................................................... 1579
Table 12-4. DMA_REGS Registers........................................................................................................................................1580
Table 12-5. DMA_REGS Access Type Codes....................................................................................................................... 1580
Table 12-6. DMACTRL Register Field Descriptions...............................................................................................................1581
Table 12-7. DEBUGCTRL Register Field Descriptions..........................................................................................................1582
Table 12-8. PRIORITYCTRL1 Register Field Descriptions....................................................................................................1583
Table 12-9. PRIORITYSTAT Register Field Descriptions...................................................................................................... 1584
Table 12-10. DMA_CH_REGS Registers.............................................................................................................................. 1585
Table 12-11. DMA_CH_REGS Access Type Codes.............................................................................................................. 1585
Table 12-12. MODE Register Field Descriptions................................................................................................................... 1587
Table 12-13. CONTROL Register Field Descriptions............................................................................................................ 1589
Table 12-14. BURST_SIZE Register Field Descriptions........................................................................................................1591
Table 12-15. BURST_COUNT Register Field Descriptions................................................................................................... 1592
Table 12-16. SRC_BURST_STEP Register Field Descriptions.............................................................................................1593
Table 12-17. DST_BURST_STEP Register Field Descriptions............................................................................................. 1594
Table 12-18. TRANSFER_SIZE Register Field Descriptions.................................................................................................1595
Table 12-19. TRANSFER_COUNT Register Field Descriptions............................................................................................1596
Table 12-20. SRC_TRANSFER_STEP Register Field Descriptions......................................................................................1597
Table 12-21. DST_TRANSFER_STEP Register Field Descriptions...................................................................................... 1598
Table 12-22. SRC_WRAP_SIZE Register Field Descriptions................................................................................................1599
Table 12-23. SRC_WRAP_COUNT Register Field Descriptions...........................................................................................1600
Table 12-24. SRC_WRAP_STEP Register Field Descriptions.............................................................................................. 1601
Table 12-25. DST_WRAP_SIZE Register Field Descriptions................................................................................................ 1602
Table 12-26. DST_WRAP_COUNT Register Field Descriptions........................................................................................... 1603
Table 12-27. DST_WRAP_STEP Register Field Descriptions...............................................................................................1604
Table 12-28. SRC_BEG_ADDR_SHADOW Register Field Descriptions.............................................................................. 1605
Table 12-29. SRC_ADDR_SHADOW Register Field Descriptions........................................................................................ 1606
Table 12-30. SRC_BEG_ADDR_ACTIVE Register Field Descriptions..................................................................................1607
Table 12-31. SRC_ADDR_ACTIVE Register Field Descriptions........................................................................................... 1608
Table 12-32. DST_BEG_ADDR_SHADOW Register Field Descriptions...............................................................................1609
Table 12-33. DST_ADDR_SHADOW Register Field Descriptions........................................................................................ 1610
Table 12-34. DST_BEG_ADDR_ACTIVE Register Field Descriptions.................................................................................. 1611
Table 12-35. DST_ADDR_ACTIVE Register Field Descriptions............................................................................................1612
Table 12-36. DMA Registers to Driverlib Functions............................................................................................................... 1612
Table 13-1. Event Selector Mux Signals................................................................................................................................ 1621
Table 13-2. CPU Interfaces Monitored by CRC Units............................................................................................................1627
Table 13-3. Event Selector Mux Signals................................................................................................................................ 1631
Table 13-4. Trace Memory Entry Bit Fields............................................................................................................................1633
Table 13-5. ERAD Registers to Driverlib Functions............................................................................................................... 1636
Table 13-6. ERAD Base Address Table................................................................................................................................. 1646
Table 13-7. ERAD_GLOBAL_REGS Registers..................................................................................................................... 1647
Table 13-8. ERAD_GLOBAL_REGS Access Type Codes.....................................................................................................1647
Table 13-9. GLBL_EVENT_STAT Register Field Descriptions.............................................................................................. 1648
Table 13-10. GLBL_HALT_STAT Register Field Descriptions............................................................................................... 1650
Table 13-11. GLBL_ENABLE Register Field Descriptions..................................................................................................... 1652
Table 13-12. GLBL_CTM_RESET Register Field Descriptions............................................................................................. 1654
Table 13-13. GLBL_NMI_CTL Register Field Descriptions................................................................................................... 1655
Table 13-14. GLBL_OWNER Register Field Descriptions..................................................................................................... 1657
Table 13-15. GLBL_EVENT_AND_MASK Register Field Descriptions................................................................................. 1658
Table 13-16. GLBL_EVENT_OR_MASK Register Field Descriptions................................................................................... 1662
Table 13-17. GLBL_AND_EVENT_INT_MASK Register Field Descriptions......................................................................... 1666
Table 13-18. GLBL_OR_EVENT_INT_MASK Register Field Descriptions........................................................................... 1667
Table 13-19. ERAD_HWBP_REGS Registers.......................................................................................................................1668
Table 13-20. ERAD_HWBP_REGS Access Type Codes...................................................................................................... 1668
Table 13-21. HWBP_MASK Register Field Descriptions....................................................................................................... 1669
Table 13-22. HWBP_REF Register Field Descriptions.......................................................................................................... 1670
Table 13-23. HWBP_CLEAR Register Field Descriptions..................................................................................................... 1671
Table 13-24. HWBP_CNTL Register Field Descriptions........................................................................................................1672

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Table 13-25. HWBP_STATUS Register Field Descriptions....................................................................................................1674

Table 13-26. ERAD_COUNTER_REGS Registers................................................................................................................1675
Table 13-27. ERAD_COUNTER_REGS Access Type Codes............................................................................................... 1675
Table 13-28. CTM_CNTL Register Field Descriptions...........................................................................................................1676
Table 13-29. CTM_STATUS Register Field Descriptions.......................................................................................................1678
Table 13-30. CTM_REF Register Field Descriptions............................................................................................................. 1679
Table 13-31. CTM_COUNT Register Field Descriptions....................................................................................................... 1680
Table 13-32. CTM_MAX_COUNT Register Field Descriptions..............................................................................................1681
Table 13-33. CTM_INPUT_SEL Register Field Descriptions.................................................................................................1682
Table 13-34. CTM_CLEAR Register Field Descriptions........................................................................................................ 1683
Table 13-35. CTM_INPUT_SEL_2 Register Field Descriptions.............................................................................................1684
Table 13-36. CTM_INPUT_COND Register Field Descriptions.............................................................................................1685
Table 13-37. ERAD_CRC_GLOBAL_REGS Registers......................................................................................................... 1686
Table 13-38. ERAD_CRC_GLOBAL_REGS Access Type Codes.........................................................................................1686
Table 13-39. CRC_GLOBAL_CTRL Register Field Descriptions.......................................................................................... 1687
Table 13-40. ERAD_CRC_REGS Registers..........................................................................................................................1689
Table 13-41. ERAD_CRC_REGS Access Type Codes......................................................................................................... 1689
Table 13-42. CRC_CURRENT Register Field Descriptions...................................................................................................1690
Table 13-43. CRC_SEED Register Field Descriptions.......................................................................................................... 1691
Table 13-44. CRC_QUALIFIER Register Field Descriptions................................................................................................. 1692
Table 13-45. ERAD Registers to Driverlib Functions............................................................................................................. 1692
Table 14-1. HIC Connections Table....................................................................................................................................... 1699
Table 14-2. Event Trigger (EVTRIG) Sources........................................................................................................................1701
Table 14-3. Address Space View for External Host............................................................................................................... 1705
Table 14-4. Data Packing and Unpacking for Writes............................................................................................................. 1708
Table 14-5. Data Packing and Unpacking for Reads............................................................................................................. 1710
Table 14-6. Address Translation for 8-bit Data Width Mode.................................................................................................. 1711
Table 14-7. Address Translation for 16-bit Data Width Mode................................................................................................ 1711
Table 14-8. HIC Base Address Table.....................................................................................................................................1715
Table 14-9. HIC_CFG_REGS Registers................................................................................................................................1716
Table 14-10. HIC_CFG_REGS Access Type Codes............................................................................................................. 1717
Table 14-11. HICREV Register Field Descriptions.................................................................................................................1719
Table 14-12. HICGCR Register Field Descriptions................................................................................................................1720
Table 14-13. HICLOCK Register Field Descriptions.............................................................................................................. 1721
Table 14-14. HICMODECR Register Field Descriptions........................................................................................................1722
Table 14-15. HICPINPOLCR Register Field Descriptions..................................................................................................... 1724
Table 14-16. HICBASESEL Register Field Descriptions....................................................................................................... 1725
Table 14-17. HICHOSTCR Register Field Descriptions.........................................................................................................1726
Table 14-18. HICERRADDR Register Field Descriptions...................................................................................................... 1728
Table 14-19. HICH2DTOKEN Register Field Descriptions.................................................................................................... 1730
Table 14-20. HICD2HTOKEN Register Field Descriptions.................................................................................................... 1731
Table 14-21. HICDBADDR0 Register Field Descriptions.......................................................................................................1732
Table 14-22. HICDBADDR1 Register Field Descriptions.......................................................................................................1733
Table 14-23. HICDBADDR2 Register Field Descriptions.......................................................................................................1734
Table 14-24. HICDBADDR3 Register Field Descriptions.......................................................................................................1735
Table 14-25. HICDBADDR4 Register Field Descriptions.......................................................................................................1736
Table 14-26. HICDBADDR5 Register Field Descriptions.......................................................................................................1737
Table 14-27. HICDBADDR6 Register Field Descriptions.......................................................................................................1738
Table 14-28. HICDBADDR7 Register Field Descriptions.......................................................................................................1739
Table 14-29. HICH2DINTEN Register Field Descriptions......................................................................................................1740
Table 14-30. HICH2DINTFLG Register Field Descriptions....................................................................................................1741
Table 14-31. HICH2DINTCLR Register Field Descriptions....................................................................................................1742
Table 14-32. HICH2DINTFRC Register Field Descriptions................................................................................................... 1743
Table 14-33. HICD2HINTEN Register Field Descriptions......................................................................................................1744
Table 14-34. HICD2HINTFLG Register Field Descriptions....................................................................................................1746
Table 14-35. HICD2HINTCLR Register Field Descriptions....................................................................................................1748
Table 14-36. HICD2HINTFRC Register Field Descriptions................................................................................................... 1750
Table 14-37. HICACCVIOADDR Register Field Descriptions................................................................................................1752
Table 14-38. HICCOMMIT Register Field Descriptions......................................................................................................... 1753
Table 14-39. H2D_BUF0 Register Field Descriptions............................................................................................................1754
Table 14-40. H2D_BUF1 Register Field Descriptions............................................................................................................1755

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Table 14-41. H2D_BUF2 Register Field Descriptions............................................................................................................1756

Table 14-42. H2D_BUF3 Register Field Descriptions............................................................................................................1757
Table 14-43. H2D_BUF4 Register Field Descriptions............................................................................................................1758
Table 14-44. H2D_BUF5 Register Field Descriptions............................................................................................................1759
Table 14-45. H2D_BUF6 Register Field Descriptions............................................................................................................1760
Table 14-46. H2D_BUF7 Register Field Descriptions............................................................................................................1761
Table 14-47. H2D_BUF8 Register Field Descriptions............................................................................................................1762
Table 14-48. H2D_BUF9 Register Field Descriptions............................................................................................................1763
Table 14-49. H2D_BUF10 Register Field Descriptions..........................................................................................................1764
Table 14-50. H2D_BUF11 Register Field Descriptions.......................................................................................................... 1765
Table 14-51. H2D_BUF12 Register Field Descriptions..........................................................................................................1766
Table 14-52. H2D_BUF13 Register Field Descriptions..........................................................................................................1767
Table 14-53. H2D_BUF14 Register Field Descriptions..........................................................................................................1768
Table 14-54. H2D_BUF15 Register Field Descriptions..........................................................................................................1769
Table 14-55. D2H_BUF0 Register Field Descriptions............................................................................................................1770
Table 14-56. D2H_BUF1 Register Field Descriptions............................................................................................................1771
Table 14-57. D2H_BUF2 Register Field Descriptions............................................................................................................1772
Table 14-58. D2H_BUF3 Register Field Descriptions............................................................................................................1773
Table 14-59. D2H_BUF4 Register Field Descriptions............................................................................................................1774
Table 14-60. D2H_BUF5 Register Field Descriptions............................................................................................................1775
Table 14-61. D2H_BUF6 Register Field Descriptions............................................................................................................1776
Table 14-62. D2H_BUF7 Register Field Descriptions............................................................................................................1777
Table 14-63. D2H_BUF8 Register Field Descriptions............................................................................................................1778
Table 14-64. D2H_BUF9 Register Field Descriptions............................................................................................................1779
Table 14-65. D2H_BUF10 Register Field Descriptions..........................................................................................................1780
Table 14-66. D2H_BUF11 Register Field Descriptions.......................................................................................................... 1781
Table 14-67. D2H_BUF12 Register Field Descriptions..........................................................................................................1782
Table 14-68. D2H_BUF13 Register Field Descriptions..........................................................................................................1783
Table 14-69. D2H_BUF14 Register Field Descriptions..........................................................................................................1784
Table 14-70. D2H_BUF15 Register Field Descriptions..........................................................................................................1785
Table 14-71. HIC Registers to Driverlib Functions.................................................................................................................1785
Table 15-1. AGPIO Configuration.......................................................................................................................................... 1796
Table 15-2. Analog Pins and Internal Connections................................................................................................................1797
Table 15-3. Analog Signal Descriptions................................................................................................................................. 1798
Table 15-4. Reference Summary........................................................................................................................................... 1799
Table 15-5. ASBSYS Base Address Table.............................................................................................................................1800
Table 15-6. ANALOG_SUBSYS_REGS Registers................................................................................................................ 1801
Table 15-7. ANALOG_SUBSYS_REGS Access Type Codes............................................................................................... 1801
Table 15-8. CONFIGLOCK Register Field Descriptions........................................................................................................ 1803
Table 15-9. TSNSCTL Register Field Descriptions................................................................................................................1804
Table 15-10. ANAREFCTL Register Field Descriptions.........................................................................................................1805
Table 15-11. VMONCTL Register Field Descriptions.............................................................................................................1806
Table 15-12. CMPHPMXSEL Register Field Descriptions.....................................................................................................1807
Table 15-13. CMPLPMXSEL Register Field Descriptions..................................................................................................... 1808
Table 15-14. CMPHNMXSEL Register Field Descriptions.....................................................................................................1809
Table 15-15. CMPLNMXSEL Register Field Descriptions..................................................................................................... 1810
Table 15-16. ADCDACLOOPBACK Register Field Descriptions........................................................................................... 1811
Table 15-17. LOCK Register Field Descriptions.................................................................................................................... 1812
Table 15-18. AGPIOCTRLA Register Field Descriptions.......................................................................................................1814
Table 15-19. ASYSCTL Registers to Driverlib Functions.......................................................................................................1815
Table 16-1. ADC Options and Configuration Levels.............................................................................................................. 1821
Table 16-2. Analog to 12-bit Digital Formulas........................................................................................................................1823
Table 16-3. 12-Bit Digital-to-Analog Formulas....................................................................................................................... 1823
Table 16-4. Channel Selection of Input Pins..........................................................................................................................1826
Table 16-5. Example Requirements for Multiple Signal Sampling......................................................................................... 1828
Table 16-6. Example Connections for Multiple Signal Sampling........................................................................................... 1828
Table 16-7. DETECTCFG Settings........................................................................................................................................ 1841
Table 16-8. ADC Timing Parameter Descriptions.................................................................................................................. 1844
Table 16-9. ADC Timings in 12-bit Mode............................................................................................................................... 1846
Table 16-10. ADC Base Address Table................................................................................................................................. 1860
Table 16-11. ADC_RESULT_REGS Registers...................................................................................................................... 1861

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Table 16-12. ADC_RESULT_REGS Access Type Codes......................................................................................................1861

Table 16-13. ADCRESULT0 Register Field Descriptions.......................................................................................................1863
Table 16-14. ADCRESULT1 Register Field Descriptions.......................................................................................................1864
Table 16-15. ADCRESULT2 Register Field Descriptions.......................................................................................................1865
Table 16-16. ADCRESULT3 Register Field Descriptions.......................................................................................................1866
Table 16-17. ADCRESULT4 Register Field Descriptions.......................................................................................................1867
Table 16-18. ADCRESULT5 Register Field Descriptions.......................................................................................................1868
Table 16-19. ADCRESULT6 Register Field Descriptions.......................................................................................................1869
Table 16-20. ADCRESULT7 Register Field Descriptions.......................................................................................................1870
Table 16-21. ADCRESULT8 Register Field Descriptions.......................................................................................................1871
Table 16-22. ADCRESULT9 Register Field Descriptions.......................................................................................................1872
Table 16-23. ADCRESULT10 Register Field Descriptions.....................................................................................................1873
Table 16-24. ADCRESULT11 Register Field Descriptions.....................................................................................................1874
Table 16-25. ADCRESULT12 Register Field Descriptions.....................................................................................................1875
Table 16-26. ADCRESULT13 Register Field Descriptions.....................................................................................................1876
Table 16-27. ADCRESULT14 Register Field Descriptions.....................................................................................................1877
Table 16-28. ADCRESULT15 Register Field Descriptions.....................................................................................................1878
Table 16-29. ADCPPB1RESULT Register Field Descriptions............................................................................................... 1879
Table 16-30. ADCPPB2RESULT Register Field Descriptions............................................................................................... 1880
Table 16-31. ADCPPB3RESULT Register Field Descriptions............................................................................................... 1881
Table 16-32. ADCPPB4RESULT Register Field Descriptions............................................................................................... 1882
Table 16-33. ADC_REGS Registers...................................................................................................................................... 1883
Table 16-34. ADC_REGS Access Type Codes..................................................................................................................... 1884
Table 16-35. ADCCTL1 Register Field Descriptions..............................................................................................................1886
Table 16-36. ADCCTL2 Register Field Descriptions..............................................................................................................1888
Table 16-37. ADCBURSTCTL Register Field Descriptions................................................................................................... 1889
Table 16-38. ADCINTFLG Register Field Descriptions..........................................................................................................1891
Table 16-39. ADCINTFLGCLR Register Field Descriptions.................................................................................................. 1893
Table 16-40. ADCINTOVF Register Field Descriptions......................................................................................................... 1894
Table 16-41. ADCINTOVFCLR Register Field Descriptions.................................................................................................. 1895
Table 16-42. ADCINTSEL1N2 Register Field Descriptions................................................................................................... 1896
Table 16-43. ADCINTSEL3N4 Register Field Descriptions................................................................................................... 1898
Table 16-44. ADCSOCPRICTL Register Field Descriptions..................................................................................................1900
Table 16-45. ADCINTSOCSEL1 Register Field Descriptions................................................................................................ 1902
Table 16-46. ADCINTSOCSEL2 Register Field Descriptions................................................................................................ 1904
Table 16-47. ADCSOCFLG1 Register Field Descriptions......................................................................................................1906
Table 16-48. ADCSOCFRC1 Register Field Descriptions..................................................................................................... 1910
Table 16-49. ADCSOCOVF1 Register Field Descriptions..................................................................................................... 1915
Table 16-50. ADCSOCOVFCLR1 Register Field Descriptions.............................................................................................. 1918
Table 16-51. ADCSOC0CTL Register Field Descriptions......................................................................................................1921
Table 16-52. ADCSOC1CTL Register Field Descriptions......................................................................................................1923
Table 16-53. ADCSOC2CTL Register Field Descriptions......................................................................................................1925
Table 16-54. ADCSOC3CTL Register Field Descriptions......................................................................................................1927
Table 16-55. ADCSOC4CTL Register Field Descriptions......................................................................................................1929
Table 16-56. ADCSOC5CTL Register Field Descriptions......................................................................................................1931
Table 16-57. ADCSOC6CTL Register Field Descriptions......................................................................................................1933
Table 16-58. ADCSOC7CTL Register Field Descriptions......................................................................................................1935
Table 16-59. ADCSOC8CTL Register Field Descriptions......................................................................................................1937
Table 16-60. ADCSOC9CTL Register Field Descriptions......................................................................................................1939
Table 16-61. ADCSOC10CTL Register Field Descriptions....................................................................................................1941
Table 16-62. ADCSOC11CTL Register Field Descriptions.................................................................................................... 1943
Table 16-63. ADCSOC12CTL Register Field Descriptions....................................................................................................1945
Table 16-64. ADCSOC13CTL Register Field Descriptions....................................................................................................1947
Table 16-65. ADCSOC14CTL Register Field Descriptions....................................................................................................1949
Table 16-66. ADCSOC15CTL Register Field Descriptions....................................................................................................1951
Table 16-67. ADCEVTSTAT Register Field Descriptions.......................................................................................................1953
Table 16-68. ADCEVTCLR Register Field Descriptions........................................................................................................ 1956
Table 16-69. ADCEVTSEL Register Field Descriptions.........................................................................................................1958
Table 16-70. ADCEVTINTSEL Register Field Descriptions...................................................................................................1960
Table 16-71. ADCOSDETECT Register Field Descriptions...................................................................................................1962
Table 16-72. ADCCOUNTER Register Field Descriptions.....................................................................................................1963

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Table 16-73. ADCREV Register Field Descriptions............................................................................................................... 1964

Table 16-74. ADCOFFTRIM Register Field Descriptions...................................................................................................... 1965
Table 16-75. ADCPPB1CONFIG Register Field Descriptions............................................................................................... 1966
Table 16-76. ADCPPB1STAMP Register Field Descriptions................................................................................................. 1968
Table 16-77. ADCPPB1OFFCAL Register Field Descriptions............................................................................................... 1969
Table 16-78. ADCPPB1OFFREF Register Field Descriptions...............................................................................................1970
Table 16-79. ADCPPB1TRIPHI Register Field Descriptions................................................................................................. 1971
Table 16-80. ADCPPB1TRIPLO Register Field Descriptions................................................................................................ 1972
Table 16-81. ADCPPB2CONFIG Register Field Descriptions............................................................................................... 1973
Table 16-82. ADCPPB2STAMP Register Field Descriptions................................................................................................. 1975
Table 16-83. ADCPPB2OFFCAL Register Field Descriptions............................................................................................... 1976
Table 16-84. ADCPPB2OFFREF Register Field Descriptions...............................................................................................1977
Table 16-85. ADCPPB2TRIPHI Register Field Descriptions................................................................................................. 1978
Table 16-86. ADCPPB2TRIPLO Register Field Descriptions................................................................................................ 1979
Table 16-87. ADCPPB3CONFIG Register Field Descriptions............................................................................................... 1980
Table 16-88. ADCPPB3STAMP Register Field Descriptions................................................................................................. 1982
Table 16-89. ADCPPB3OFFCAL Register Field Descriptions............................................................................................... 1983
Table 16-90. ADCPPB3OFFREF Register Field Descriptions...............................................................................................1984
Table 16-91. ADCPPB3TRIPHI Register Field Descriptions................................................................................................. 1985
Table 16-92. ADCPPB3TRIPLO Register Field Descriptions................................................................................................ 1986
Table 16-93. ADCPPB4CONFIG Register Field Descriptions............................................................................................... 1987
Table 16-94. ADCPPB4STAMP Register Field Descriptions................................................................................................. 1989
Table 16-95. ADCPPB4OFFCAL Register Field Descriptions............................................................................................... 1990
Table 16-96. ADCPPB4OFFREF Register Field Descriptions...............................................................................................1991
Table 16-97. ADCPPB4TRIPHI Register Field Descriptions................................................................................................. 1992
Table 16-98. ADCPPB4TRIPLO Register Field Descriptions................................................................................................ 1993
Table 16-99. ADCINTCYCLE Register Field Descriptions.....................................................................................................1994
Table 16-100. ADCINLTRIM2 Register Field Descriptions.................................................................................................... 1995
Table 16-101. ADCINLTRIM3 Register Field Descriptions.................................................................................................... 1996
Table 16-102. ADC Registers to Driverlib Functions............................................................................................................. 1996
Table 17-1. DAC Supported Gain Mode Combinations......................................................................................................... 2003
Table 17-2. DAC Base Address Table................................................................................................................................... 2006
Table 17-3. DAC_REGS Registers........................................................................................................................................ 2007
Table 17-4. DAC_REGS Access Type Codes....................................................................................................................... 2007
Table 17-5. DACREV Register Field Descriptions................................................................................................................. 2008
Table 17-6. DACCTL Register Field Descriptions..................................................................................................................2009
Table 17-7. DACVALA Register Field Descriptions................................................................................................................2010
Table 17-8. DACVALS Register Field Descriptions................................................................................................................2011
Table 17-9. DACOUTEN Register Field Descriptions............................................................................................................2012
Table 17-10. DACLOCK Register Field Descriptions.............................................................................................................2013
Table 17-11. DACTRIM Register Field Descriptions.............................................................................................................. 2014
Table 17-12. DAC Registers to Driverlib Functions............................................................................................................... 2014
Table 18-1. CMPSS Base Address Table.............................................................................................................................. 2028
Table 18-2. CMPSS_REGS Registers...................................................................................................................................2029
Table 18-3. CMPSS_REGS Access Type Codes.................................................................................................................. 2029
Table 18-4. COMPCTL Register Field Descriptions.............................................................................................................. 2031
Table 18-5. COMPHYSCTL Register Field Descriptions....................................................................................................... 2033
Table 18-6. COMPSTS Register Field Descriptions.............................................................................................................. 2034
Table 18-7. COMPSTSCLR Register Field Descriptions....................................................................................................... 2035
Table 18-8. COMPDACCTL Register Field Descriptions.......................................................................................................2036
Table 18-9. DACHVALS Register Field Descriptions............................................................................................................. 2038
Table 18-10. DACHVALA Register Field Descriptions........................................................................................................... 2039
Table 18-11. RAMPMAXREFA Register Field Descriptions...................................................................................................2040
Table 18-12. RAMPMAXREFS Register Field Descriptions.................................................................................................. 2041
Table 18-13. RAMPDECVALA Register Field Descriptions................................................................................................... 2042
Table 18-14. RAMPDECVALS Register Field Descriptions................................................................................................... 2043
Table 18-15. RAMPSTS Register Field Descriptions.............................................................................................................2044
Table 18-16. DACLVALS Register Field Descriptions............................................................................................................2045
Table 18-17. DACLVALA Register Field Descriptions............................................................................................................2046
Table 18-18. RAMPDLYA Register Field Descriptions...........................................................................................................2047
Table 18-19. RAMPDLYS Register Field Descriptions...........................................................................................................2048

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Table 18-20. CTRIPLFILCTL Register Field Descriptions..................................................................................................... 2049

Table 18-21. CTRIPLFILCLKCTL Register Field Descriptions.............................................................................................. 2050
Table 18-22. CTRIPHFILCTL Register Field Descriptions.....................................................................................................2051
Table 18-23. CTRIPHFILCLKCTL Register Field Descriptions..............................................................................................2052
Table 18-24. COMPLOCK Register Field Descriptions......................................................................................................... 2053
Table 18-25. CMPSS Registers to Driverlib Functions.......................................................................................................... 2053
Table 19-1. Modulator Clock Modes...................................................................................................................................... 2064
Table 19-2. Order of Sinc Filter..............................................................................................................................................2066
Table 19-3. Peak Data Values for Different DOSR/Filter Combinations................................................................................ 2067
Table 19-4. Shift Control Bit Configuration Settings...............................................................................................................2068
Table 19-5. SDSYNCx.SYNCSEL......................................................................................................................................... 2070
Table 19-6. Number of Incorrect Samples Tabulated.............................................................................................................2071
Table 19-7. Peak Data Values for Different OSR/Filter Combinations................................................................................... 2072
Table 19-8. SDFM Data-Ready Interrupt (SDy_DRINTx) Output Selection...........................................................................2080
Table 19-9. SDFM Base Address Table.................................................................................................................................2084
Table 19-10. SDFM_REGS Registers................................................................................................................................... 2085
Table 19-11. SDFM_REGS Access Type Codes................................................................................................................... 2087
Table 19-12. SDIFLG Register Field Descriptions................................................................................................................. 2088
Table 19-13. SDIFLGCLR Register Field Descriptions..........................................................................................................2091
Table 19-14. SDCTL Register Field Descriptions.................................................................................................................. 2093
Table 19-15. SDMFILEN Register Field Descriptions............................................................................................................2094
Table 19-16. SDSTATUS Register Field Descriptions........................................................................................................... 2095
Table 19-17. SDCTLPARM1 Register Field Descriptions...................................................................................................... 2096
Table 19-18. SDDFPARM1 Register Field Descriptions........................................................................................................ 2097
Table 19-19. SDDPARM1 Register Field Descriptions.......................................................................................................... 2098
Table 19-20. SDFLT1CMPH1 Register Field Descriptions.................................................................................................... 2099
Table 19-21. SDFLT1CMPL1 Register Field Descriptions..................................................................................................... 2100
Table 19-22. SDCPARM1 Register Field Descriptions.......................................................................................................... 2101
Table 19-23. SDDATA1 Register Field Descriptions.............................................................................................................. 2103
Table 19-24. SDDATFIFO1 Register Field Descriptions........................................................................................................ 2104
Table 19-25. SDCDATA1 Register Field Descriptions........................................................................................................... 2105
Table 19-26. SDFLT1CMPH2 Register Field Descriptions.................................................................................................... 2106
Table 19-27. SDFLT1CMPHZ Register Field Descriptions.................................................................................................... 2107
Table 19-28. SDFIFOCTL1 Register Field Descriptions........................................................................................................ 2108
Table 19-29. SDSYNC1 Register Field Descriptions............................................................................................................. 2109
Table 19-30. SDFLT1CMPL2 Register Field Descriptions..................................................................................................... 2110
Table 19-31. SDCTLPARM2 Register Field Descriptions.......................................................................................................2111
Table 19-32. SDDFPARM2 Register Field Descriptions........................................................................................................ 2112
Table 19-33. SDDPARM2 Register Field Descriptions...........................................................................................................2113
Table 19-34. SDFLT2CMPH1 Register Field Descriptions.....................................................................................................2114
Table 19-35. SDFLT2CMPL1 Register Field Descriptions..................................................................................................... 2115
Table 19-36. SDCPARM2 Register Field Descriptions...........................................................................................................2116
Table 19-37. SDDATA2 Register Field Descriptions.............................................................................................................. 2118
Table 19-38. SDDATFIFO2 Register Field Descriptions........................................................................................................ 2119
Table 19-39. SDCDATA2 Register Field Descriptions........................................................................................................... 2120
Table 19-40. SDFLT2CMPH2 Register Field Descriptions.................................................................................................... 2121
Table 19-41. SDFLT2CMPHZ Register Field Descriptions.................................................................................................... 2122
Table 19-42. SDFIFOCTL2 Register Field Descriptions........................................................................................................ 2123
Table 19-43. SDSYNC2 Register Field Descriptions............................................................................................................. 2124
Table 19-44. SDFLT2CMPL2 Register Field Descriptions..................................................................................................... 2125
Table 19-45. SDCTLPARM3 Register Field Descriptions...................................................................................................... 2126
Table 19-46. SDDFPARM3 Register Field Descriptions........................................................................................................ 2127
Table 19-47. SDDPARM3 Register Field Descriptions.......................................................................................................... 2128
Table 19-48. SDFLT3CMPH1 Register Field Descriptions.................................................................................................... 2129
Table 19-49. SDFLT3CMPL1 Register Field Descriptions..................................................................................................... 2130
Table 19-50. SDCPARM3 Register Field Descriptions.......................................................................................................... 2131
Table 19-51. SDDATA3 Register Field Descriptions.............................................................................................................. 2133
Table 19-52. SDDATFIFO3 Register Field Descriptions........................................................................................................ 2134
Table 19-53. SDCDATA3 Register Field Descriptions........................................................................................................... 2135
Table 19-54. SDFLT3CMPH2 Register Field Descriptions.................................................................................................... 2136
Table 19-55. SDFLT3CMPHZ Register Field Descriptions.................................................................................................... 2137

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Table 19-56. SDFIFOCTL3 Register Field Descriptions........................................................................................................ 2138

Table 19-57. SDSYNC3 Register Field Descriptions............................................................................................................. 2139
Table 19-58. SDFLT3CMPL2 Register Field Descriptions..................................................................................................... 2140
Table 19-59. SDCTLPARM4 Register Field Descriptions...................................................................................................... 2141
Table 19-60. SDDFPARM4 Register Field Descriptions........................................................................................................ 2142
Table 19-61. SDDPARM4 Register Field Descriptions.......................................................................................................... 2143
Table 19-62. SDFLT4CMPH1 Register Field Descriptions.................................................................................................... 2144
Table 19-63. SDFLT4CMPL1 Register Field Descriptions..................................................................................................... 2145
Table 19-64. SDCPARM4 Register Field Descriptions.......................................................................................................... 2146
Table 19-65. SDDATA4 Register Field Descriptions.............................................................................................................. 2148
Table 19-66. SDDATFIFO4 Register Field Descriptions........................................................................................................ 2149
Table 19-67. SDCDATA4 Register Field Descriptions........................................................................................................... 2150
Table 19-68. SDFLT4CMPH2 Register Field Descriptions.................................................................................................... 2151
Table 19-69. SDFLT4CMPHZ Register Field Descriptions.................................................................................................... 2152
Table 19-70. SDFIFOCTL4 Register Field Descriptions........................................................................................................ 2153
Table 19-71. SDSYNC4 Register Field Descriptions............................................................................................................. 2154
Table 19-72. SDFLT4CMPL2 Register Field Descriptions..................................................................................................... 2155
Table 19-73. SDCOMP1CTL Register Field Descriptions..................................................................................................... 2156
Table 19-74. SDCOMP1EVT2FLTCTL Register Field Descriptions...................................................................................... 2157
Table 19-75. SDCOMP1EVT2FLTCLKCTL Register Field Descriptions............................................................................... 2158
Table 19-76. SDCOMP1EVT1FLTCTL Register Field Descriptions...................................................................................... 2159
Table 19-77. SDCOMP1EVT1FLTCLKCTL Register Field Descriptions............................................................................... 2160
Table 19-78. SDCOMP1LOCK Register Field Descriptions.................................................................................................. 2161
Table 19-79. SDCOMP2CTL Register Field Descriptions..................................................................................................... 2162
Table 19-80. SDCOMP2EVT2FLTCTL Register Field Descriptions...................................................................................... 2163
Table 19-81. SDCOMP2EVT2FLTCLKCTL Register Field Descriptions............................................................................... 2164
Table 19-82. SDCOMP2EVT1FLTCTL Register Field Descriptions...................................................................................... 2165
Table 19-83. SDCOMP2EVT1FLTCLKCTL Register Field Descriptions............................................................................... 2166
Table 19-84. SDCOMP2LOCK Register Field Descriptions.................................................................................................. 2167
Table 19-85. SDCOMP3CTL Register Field Descriptions..................................................................................................... 2168
Table 19-86. SDCOMP3EVT2FLTCTL Register Field Descriptions...................................................................................... 2169
Table 19-87. SDCOMP3EVT2FLTCLKCTL Register Field Descriptions............................................................................... 2170
Table 19-88. SDCOMP3EVT1FLTCTL Register Field Descriptions...................................................................................... 2171
Table 19-89. SDCOMP3EVT1FLTCLKCTL Register Field Descriptions............................................................................... 2172
Table 19-90. SDCOMP3LOCK Register Field Descriptions.................................................................................................. 2173
Table 19-91. SDCOMP4CTL Register Field Descriptions..................................................................................................... 2174
Table 19-92. SDCOMP4EVT2FLTCTL Register Field Descriptions...................................................................................... 2175
Table 19-93. SDCOMP4EVT2FLTCLKCTL Register Field Descriptions............................................................................... 2176
Table 19-94. SDCOMP4EVT1FLTCTL Register Field Descriptions...................................................................................... 2177
Table 19-95. SDCOMP4EVT1FLTCLKCTL Register Field Descriptions............................................................................... 2178
Table 19-96. SDCOMP4LOCK Register Field Descriptions.................................................................................................. 2179
Table 19-97. SDFM Registers to Driverlib Functions.............................................................................................................2179
Table 20-1. Submodule Configuration Parameters................................................................................................................2193
Table 20-2. Key Time-Base Signals.......................................................................................................................................2197
Table 20-3. ePWM SYNC Selection...................................................................................................................................... 2202
Table 20-4. Action-Qualifier Submodule Possible Input Events.............................................................................................2217
Table 20-5. Action-Qualifier Event Priority for Up-Down-Count Mode................................................................................... 2219
Table 20-6. Action-Qualifier Event Priority for Up-Count Mode............................................................................................. 2219
Table 20-7. Action-Qualifier Event Priority for Down-Count Mode.........................................................................................2219
Table 20-8. Behavior if CMPA/CMPB is Greater than the Period.......................................................................................... 2220
Table 20-9. Classical Dead-Band Operating Modes..............................................................................................................2233
Table 20-10. Additional Dead-Band Operating Modes.......................................................................................................... 2233
Table 20-11. Dead-Band Delay Values in μS as a Function of DBFED and DBRED.............................................................2235
Table 20-12. Possible Pulse Width Values for EPWMCLK = 80 MHz....................................................................................2238
Table 20-13. Possible Actions On a Trip Event......................................................................................................................2242
Table 20-14. Lock Bits and Corresponding Registers............................................................................................................2279
Table 20-15. Resolution for PWM and HRPWM.................................................................................................................... 2281
Table 20-16. Relationship Between MEP Steps, PWM Frequency, and Resolution..............................................................2287
Table 20-17. CMPA versus Duty (left), and [CMPA:CMPAHR] versus Duty (right)................................................................2288
Table 20-18. Duty Cycle Range Limitation for Three EPWMCLK/TBCLK Cycles................................................................. 2291
Table 20-19. SFO Library Features....................................................................................................................................... 2303

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Table 20-20. Factor Values.................................................................................................................................................... 2304

Table 20-21. EPWM Base Address Table..............................................................................................................................2313
Table 20-22. EPWM_REGS Registers.................................................................................................................................. 2314
Table 20-23. EPWM_REGS Access Type Codes..................................................................................................................2316
Table 20-24. TBCTL Register Field Descriptions...................................................................................................................2317
Table 20-25. TBCTL2 Register Field Descriptions.................................................................................................................2319
Table 20-26. EPWMSYNCINSEL Register Field Descriptions.............................................................................................. 2320
Table 20-27. TBCTR Register Field Descriptions.................................................................................................................. 2321
Table 20-28. TBSTS Register Field Descriptions.................................................................................................................. 2322
Table 20-29. EPWMSYNCOUTEN Register Field Descriptions............................................................................................ 2323
Table 20-30. TBCTL3 Register Field Descriptions.................................................................................................................2325
Table 20-31. CMPCTL Register Field Descriptions............................................................................................................... 2326
Table 20-32. CMPCTL2 Register Field Descriptions............................................................................................................. 2328
Table 20-33. DBCTL Register Field Descriptions.................................................................................................................. 2330
Table 20-34. DBCTL2 Register Field Descriptions................................................................................................................ 2333
Table 20-35. AQCTL Register Field Descriptions.................................................................................................................. 2334
Table 20-36. AQTSRCSEL Register Field Descriptions........................................................................................................ 2336
Table 20-37. PCCTL Register Field Descriptions.................................................................................................................. 2337
Table 20-38. VCAPCTL Register Field Descriptions............................................................................................................. 2338
Table 20-39. VCNTCFG Register Field Descriptions.............................................................................................................2340
Table 20-40. HRCNFG Register Field Descriptions...............................................................................................................2342
Table 20-41. HRPWR Register Field Descriptions................................................................................................................ 2344
Table 20-42. HRMSTEP Register Field Descriptions............................................................................................................ 2345
Table 20-43. HRCNFG2 Register Field Descriptions.............................................................................................................2346
Table 20-44. HRPCTL Register Field Descriptions................................................................................................................2347
Table 20-45. TRREM Register Field Descriptions................................................................................................................. 2349
Table 20-46. GLDCTL Register Field Descriptions................................................................................................................2350
Table 20-47. GLDCFG Register Field Descriptions............................................................................................................... 2352
Table 20-48. EPWMXLINK Register Field Descriptions........................................................................................................ 2354
Table 20-49. AQCTLA Register Field Descriptions................................................................................................................2356
Table 20-50. AQCTLA2 Register Field Descriptions..............................................................................................................2358
Table 20-51. AQCTLB Register Field Descriptions................................................................................................................2359
Table 20-52. AQCTLB2 Register Field Descriptions..............................................................................................................2361
Table 20-53. AQSFRC Register Field Descriptions............................................................................................................... 2362
Table 20-54. AQCSFRC Register Field Descriptions............................................................................................................ 2363
Table 20-55. DBREDHR Register Field Descriptions............................................................................................................ 2364
Table 20-56. DBRED Register Field Descriptions................................................................................................................. 2365
Table 20-57. DBFEDHR Register Field Descriptions.............................................................................................................2366
Table 20-58. DBFED Register Field Descriptions..................................................................................................................2367
Table 20-59. TBPHS Register Field Descriptions.................................................................................................................. 2368
Table 20-60. TBPRDHR Register Field Descriptions.............................................................................................................2369
Table 20-61. TBPRD Register Field Descriptions..................................................................................................................2370
Table 20-62. CMPA Register Field Descriptions.................................................................................................................... 2371
Table 20-63. CMPB Register Field Descriptions....................................................................................................................2372
Table 20-64. CMPC Register Field Descriptions................................................................................................................... 2373
Table 20-65. CMPD Register Field Descriptions................................................................................................................... 2374
Table 20-66. GLDCTL2 Register Field Descriptions..............................................................................................................2375
Table 20-67. SWVDELVAL Register Field Descriptions.........................................................................................................2376
Table 20-68. TZSEL Register Field Descriptions...................................................................................................................2377
Table 20-69. TZDCSEL Register Field Descriptions..............................................................................................................2379
Table 20-70. TZCTL Register Field Descriptions...................................................................................................................2380
Table 20-71. TZCTL2 Register Field Descriptions.................................................................................................................2381
Table 20-72. TZCTLDCA Register Field Descriptions........................................................................................................... 2383
Table 20-73. TZCTLDCB Register Field Descriptions........................................................................................................... 2385
Table 20-74. TZEINT Register Field Descriptions................................................................................................................. 2387
Table 20-75. TZFLG Register Field Descriptions...................................................................................................................2388
Table 20-76. TZCBCFLG Register Field Descriptions........................................................................................................... 2390
Table 20-77. TZOSTFLG Register Field Descriptions........................................................................................................... 2391
Table 20-78. TZCLR Register Field Descriptions.................................................................................................................. 2392
Table 20-79. TZCBCCLR Register Field Descriptions...........................................................................................................2393
Table 20-80. TZOSTCLR Register Field Descriptions........................................................................................................... 2394

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Table 20-81. TZFRC Register Field Descriptions.................................................................................................................. 2395

Table 20-82. ETSEL Register Field Descriptions...................................................................................................................2396
Table 20-83. ETPS Register Field Descriptions.....................................................................................................................2399
Table 20-84. ETFLG Register Field Descriptions.................................................................................................................. 2402
Table 20-85. ETCLR Register Field Descriptions.................................................................................................................. 2403
Table 20-86. ETFRC Register Field Descriptions.................................................................................................................. 2404
Table 20-87. ETINTPS Register Field Descriptions...............................................................................................................2405
Table 20-88. ETSOCPS Register Field Descriptions.............................................................................................................2406
Table 20-89. ETCNTINITCTL Register Field Descriptions.................................................................................................... 2407
Table 20-90. ETCNTINIT Register Field Descriptions........................................................................................................... 2408
Table 20-91. DCTRIPSEL Register Field Descriptions..........................................................................................................2409
Table 20-92. DCACTL Register Field Descriptions................................................................................................................ 2411
Table 20-93. DCBCTL Register Field Descriptions................................................................................................................2413
Table 20-94. DCFCTL Register Field Descriptions................................................................................................................2415
Table 20-95. DCCAPCTL Register Field Descriptions...........................................................................................................2417
Table 20-96. DCFOFFSET Register Field Descriptions........................................................................................................ 2419
Table 20-97. DCFOFFSETCNT Register Field Descriptions................................................................................................. 2420
Table 20-98. DCFWINDOW Register Field Descriptions.......................................................................................................2421
Table 20-99. DCFWINDOWCNT Register Field Descriptions............................................................................................... 2422
Table 20-100. BLANKPULSEMIXSEL Register Field Descriptions....................................................................................... 2423
Table 20-101. DCCAP Register Field Descriptions............................................................................................................... 2425
Table 20-102. DCAHTRIPSEL Register Field Descriptions...................................................................................................2426
Table 20-103. DCALTRIPSEL Register Field Descriptions....................................................................................................2428
Table 20-104. DCBHTRIPSEL Register Field Descriptions...................................................................................................2430
Table 20-105. DCBLTRIPSEL Register Field Descriptions....................................................................................................2432
Table 20-106. EPWMLOCK Register Field Descriptions....................................................................................................... 2434
Table 20-107. HWVDELVAL Register Field Descriptions...................................................................................................... 2435
Table 20-108. VCNTVAL Register Field Descriptions............................................................................................................2436
Table 20-109. EPWM Registers to Driverlib Functions..........................................................................................................2437
Table 20-110. HRPWM Registers to Driverlib Functions....................................................................................................... 2443
Table 21-1. eCAP Input Selection..........................................................................................................................................2451
Table 21-2. ECAP Base Address Table................................................................................................................................. 2472
Table 21-3. ECAP_REGS Registers......................................................................................................................................2473
Table 21-4. ECAP_REGS Access Type Codes..................................................................................................................... 2473
Table 21-5. TSCTR Register Field Descriptions.................................................................................................................... 2475
Table 21-6. CTRPHS Register Field Descriptions................................................................................................................. 2476
Table 21-7. CAP1 Register Field Descriptions.......................................................................................................................2477
Table 21-8. CAP2 Register Field Descriptions.......................................................................................................................2478
Table 21-9. CAP3 Register Field Descriptions.......................................................................................................................2479
Table 21-10. CAP4 Register Field Descriptions.....................................................................................................................2480
Table 21-11. ECCTL0 Register Field Descriptions.................................................................................................................2481
Table 21-12. ECCTL1 Register Field Descriptions................................................................................................................ 2482
Table 21-13. ECCTL2 Register Field Descriptions................................................................................................................ 2484
Table 21-14. ECEINT Register Field Descriptions.................................................................................................................2486
Table 21-15. ECFLG Register Field Descriptions.................................................................................................................. 2488
Table 21-16. ECCLR Register Field Descriptions..................................................................................................................2489
Table 21-17. ECFRC Register Field Descriptions..................................................................................................................2490
Table 21-18. ECAPSYNCINSEL Register Field Descriptions................................................................................................2491
Table 21-19. ECAP Registers to Driverlib Functions............................................................................................................. 2491
Table 22-1. Scale Factor........................................................................................................................................................2500
Table 22-2. HRCAP Base Address Table.............................................................................................................................. 2501
Table 22-3. HRCAP_REGS Registers................................................................................................................................... 2502
Table 22-4. HRCAP_REGS Access Type Codes.................................................................................................................. 2502
Table 22-5. HRCTL Register Field Descriptions.................................................................................................................... 2503
Table 22-6. HRINTEN Register Field Descriptions................................................................................................................ 2504
Table 22-7. HRFLG Register Field Descriptions....................................................................................................................2505
Table 22-8. HRCLR Register Field Descriptions....................................................................................................................2506
Table 22-9. HRFRC Register Field Descriptions................................................................................................................... 2507
Table 22-10. HRCALPRD Register Field Descriptions.......................................................................................................... 2508
Table 22-11. HRSYSCLKCTR Register Field Descriptions....................................................................................................2509
Table 22-12. HRSYSCLKCAP Register Field Descriptions................................................................................................... 2510

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Table 22-13. HRCLKCTR Register Field Descriptions...........................................................................................................2511

Table 22-14. HRCLKCAP Register Field Descriptions.......................................................................................................... 2512
Table 22-15. HRCAP Registers to Driverlib Functions.......................................................................................................... 2512
Table 23-1. eQEP Input Source Select Table........................................................................................................................ 2521
Table 23-2. EQEP Memory Map............................................................................................................................................ 2523
Table 23-3. Quadrature Decoder Truth Table........................................................................................................................ 2525
Table 23-4. EQEP Base Address Table................................................................................................................................. 2547
Table 23-5. EQEP_REGS Registers......................................................................................................................................2548
Table 23-6. EQEP_REGS Access Type Codes..................................................................................................................... 2548
Table 23-7. QPOSCNT Register Field Descriptions.............................................................................................................. 2550
Table 23-8. QPOSINIT Register Field Descriptions...............................................................................................................2551
Table 23-9. QPOSMAX Register Field Descriptions..............................................................................................................2552
Table 23-10. QPOSCMP Register Field Descriptions............................................................................................................2553
Table 23-11. QPOSILAT Register Field Descriptions.............................................................................................................2554
Table 23-12. QPOSSLAT Register Field Descriptions........................................................................................................... 2555
Table 23-13. QPOSLAT Register Field Descriptions............................................................................................................. 2556
Table 23-14. QUTMR Register Field Descriptions.................................................................................................................2557
Table 23-15. QUPRD Register Field Descriptions................................................................................................................. 2558
Table 23-16. QWDTMR Register Field Descriptions............................................................................................................. 2559
Table 23-17. QWDPRD Register Field Descriptions..............................................................................................................2560
Table 23-18. QDECCTL Register Field Descriptions.............................................................................................................2561
Table 23-19. QEPCTL Register Field Descriptions................................................................................................................2563
Table 23-20. QCAPCTL Register Field Descriptions............................................................................................................. 2565
Table 23-21. QPOSCTL Register Field Descriptions.............................................................................................................2566
Table 23-22. QEINT Register Field Descriptions................................................................................................................... 2567
Table 23-23. QFLG Register Field Descriptions.................................................................................................................... 2569
Table 23-24. QCLR Register Field Descriptions.................................................................................................................... 2571
Table 23-25. QFRC Register Field Descriptions....................................................................................................................2573
Table 23-26. QEPSTS Register Field Descriptions............................................................................................................... 2575
Table 23-27. QCTMR Register Field Descriptions.................................................................................................................2576
Table 23-28. QCPRD Register Field Descriptions................................................................................................................. 2577
Table 23-29. QCTMRLAT Register Field Descriptions...........................................................................................................2578
Table 23-30. QCPRDLAT Register Field Descriptions...........................................................................................................2579
Table 23-31. REV Register Field Descriptions.......................................................................................................................2580
Table 23-32. QEPSTROBESEL Register Field Descriptions.................................................................................................2581
Table 23-33. QMACTRL Register Field Descriptions............................................................................................................ 2582
Table 23-34. QEPSRCSEL Register Field Descriptions........................................................................................................ 2583
Table 23-35. EQEP Registers to Driverlib Functions............................................................................................................. 2584
Table 24-1. SPI Module Signal Summary.............................................................................................................................. 2590
Table 24-2. SPI Interrupt Flag Modes.................................................................................................................................... 2592
Table 24-3. SPI Clocking Scheme Selection Guide...............................................................................................................2600
Table 24-4. SPI Base Address Table..................................................................................................................................... 2607
Table 24-5. SPI_REGS Registers..........................................................................................................................................2608
Table 24-6. SPI_REGS Access Type Codes......................................................................................................................... 2608
Table 24-7. SPICCR Register Field Descriptions.................................................................................................................. 2609
Table 24-8. SPICTL Register Field Descriptions....................................................................................................................2611
Table 24-9. SPISTS Register Field Descriptions................................................................................................................... 2613
Table 24-10. SPIBRR Register Field Descriptions.................................................................................................................2615
Table 24-11. SPIRXEMU Register Field Descriptions............................................................................................................2616
Table 24-12. SPIRXBUF Register Field Descriptions............................................................................................................ 2617
Table 24-13. SPITXBUF Register Field Descriptions............................................................................................................ 2618
Table 24-14. SPIDAT Register Field Descriptions................................................................................................................. 2619
Table 24-15. SPIFFTX Register Field Descriptions............................................................................................................... 2620
Table 24-16. SPIFFRX Register Field Descriptions...............................................................................................................2622
Table 24-17. SPIFFCT Register Field Descriptions............................................................................................................... 2624
Table 24-18. SPIPRI Register Field Descriptions.................................................................................................................. 2625
Table 24-19. SPI Registers to Driverlib Functions................................................................................................................. 2626
Table 25-1. SCI Module Signal Summary..............................................................................................................................2631
Table 25-2. Programming the Data Format Using SCICCR.................................................................................................. 2634
Table 25-3. Asynchronous Baud Register Values for Common SCI Bit Rates...................................................................... 2641
Table 25-4. SCI Interrupt Flags..............................................................................................................................................2643

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Table 25-5. SCI Base Address Table..................................................................................................................................... 2647

Table 25-6. SCI_REGS Registers..........................................................................................................................................2648
Table 25-7. SCI_REGS Access Type Codes......................................................................................................................... 2648
Table 25-8. SCICCR Register Field Descriptions.................................................................................................................. 2649
Table 25-9. SCICTL1 Register Field Descriptions................................................................................................................. 2651
Table 25-10. SCIHBAUD Register Field Descriptions........................................................................................................... 2653
Table 25-11. SCILBAUD Register Field Descriptions............................................................................................................ 2654
Table 25-12. SCICTL2 Register Field Descriptions............................................................................................................... 2655
Table 25-13. SCIRXST Register Field Descriptions.............................................................................................................. 2657
Table 25-14. SCIRXEMU Register Field Descriptions........................................................................................................... 2659
Table 25-15. SCIRXBUF Register Field Descriptions............................................................................................................2660
Table 25-16. SCITXBUF Register Field Descriptions............................................................................................................ 2661
Table 25-17. SCIFFTX Register Field Descriptions............................................................................................................... 2662
Table 25-18. SCIFFRX Register Field Descriptions...............................................................................................................2664
Table 25-19. SCIFFCT Register Field Descriptions...............................................................................................................2666
Table 25-20. SCIPRI Register Field Descriptions.................................................................................................................. 2667
Table 25-21. SCI Registers to Driverlib Functions................................................................................................................. 2667
Table 26-1. Dependency of Delay d on the Divide-Down Value IPSC................................................................................... 2676
Table 26-2. Operating Modes of the I2C Module................................................................................................................... 2678
Table 26-3. Master-Transmitter/Receiver Bus Activity Defined by the RM, STT, and STP Bits of I2CMDR.......................... 2678
Table 26-4. How the MST and FDF Bits of I2CMDR Affect the Role of the TRX Bit of I2CMDR...........................................2684
Table 26-5. Ways to Generate a NACK Bit............................................................................................................................ 2688
Table 26-6. Descriptions of the Basic I2C Interrupt Requests............................................................................................... 2689
Table 26-7. I2C Base Address Table..................................................................................................................................... 2696
Table 26-8. I2C_REGS Registers.......................................................................................................................................... 2697
Table 26-9. I2C_REGS Access Type Codes......................................................................................................................... 2697
Table 26-10. I2COAR Register Field Descriptions.................................................................................................................2699
Table 26-11. I2CIER Register Field Descriptions...................................................................................................................2700
Table 26-12. I2CSTR Register Field Descriptions................................................................................................................. 2701
Table 26-13. I2CCLKL Register Field Descriptions............................................................................................................... 2705
Table 26-14. I2CCLKH Register Field Descriptions...............................................................................................................2706
Table 26-15. I2CCNT Register Field Descriptions................................................................................................................. 2707
Table 26-16. I2CDRR Register Field Descriptions.................................................................................................................2708
Table 26-17. I2CSAR Register Field Descriptions................................................................................................................. 2709
Table 26-18. I2CDXR Register Field Descriptions.................................................................................................................2710
Table 26-19. I2CMDR Register Field Descriptions.................................................................................................................2711
Table 26-20. I2CISRC Register Field Descriptions................................................................................................................2714
Table 26-21. I2CEMDR Register Field Descriptions..............................................................................................................2715
Table 26-22. I2CPSC Register Field Descriptions................................................................................................................. 2716
Table 26-23. I2CFFTX Register Field Descriptions............................................................................................................... 2717
Table 26-24. I2CFFRX Register Field Descriptions............................................................................................................... 2719
Table 26-25. I2C Registers to Driverlib Functions................................................................................................................. 2720
Table 27-1. PMBUS Base Address Table.............................................................................................................................. 2746
Table 27-2. PMBUS_REGS Registers...................................................................................................................................2747
Table 27-3. PMBUS_REGS Access Type Codes.................................................................................................................. 2747
Table 27-4. PMBMC Register Field Descriptions...................................................................................................................2748
Table 27-5. PMBTXBUF Register Field Descriptions............................................................................................................ 2749
Table 27-6. PMBRXBUF Register Field Descriptions............................................................................................................ 2750
Table 27-7. PMBACK Register Field Descriptions.................................................................................................................2751
Table 27-8. PMBSTS Register Field Descriptions................................................................................................................. 2752
Table 27-9. PMBINTM Register Field Descriptions............................................................................................................... 2754
Table 27-10. PMBSC Register Field Descriptions................................................................................................................. 2756
Table 27-11. PMBHSA Register Field Descriptions............................................................................................................... 2758
Table 27-12. PMBCTRL Register Field Descriptions.............................................................................................................2759
Table 27-13. PMBTIMCTL Register Field Descriptions......................................................................................................... 2761
Table 27-14. PMBTIMCLK Register Field Descriptions......................................................................................................... 2762
Table 27-15. PMBTIMSTSETUP Register Field Descriptions............................................................................................... 2763
Table 27-16. PMBTIMBIDLE Register Field Descriptions......................................................................................................2764
Table 27-17. PMBTIMLOWTIMOUT Register Field Descriptions.......................................................................................... 2765
Table 27-18. PMBTIMHIGHTIMOUT Register Field Descriptions......................................................................................... 2766
Table 27-19. PMBUS Registers to Driverlib Functions.......................................................................................................... 2766

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Table 28-1. CAN Register Access from Software.................................................................................................................. 2773

Table 28-2. CAN Register Access from Code Composer Studio™ IDE................................................................................ 2774
Table 28-3. PIE Module Nomenclature for Interrupts.............................................................................................................2781
Table 28-4. Programmable Ranges Required by CAN Protocol............................................................................................2793
Table 28-5. Message Object Field Descriptions.................................................................................................................... 2803
Table 28-6. Message RAM Addressing in Debug Mode........................................................................................................ 2806
Table 28-7. CAN Base Address Table....................................................................................................................................2811
Table 28-8. CAN_REGS Registers........................................................................................................................................ 2812
Table 28-9. CAN_REGS Access Type Codes....................................................................................................................... 2813
Table 28-10. CAN_CTL Register Field Descriptions..............................................................................................................2814
Table 28-11. CAN_ES Register Field Descriptions................................................................................................................ 2817
Table 28-12. CAN_ERRC Register Field Descriptions.......................................................................................................... 2819
Table 28-13. CAN_BTR Register Field Descriptions............................................................................................................. 2820
Table 28-14. CAN_INT Register Field Descriptions...............................................................................................................2822
Table 28-15. CAN_TEST Register Field Descriptions........................................................................................................... 2823
Table 28-16. CAN_PERR Register Field Descriptions.......................................................................................................... 2825
Table 28-17. CAN_RAM_INIT Register Field Descriptions....................................................................................................2826
Table 28-18. CAN_GLB_INT_EN Register Field Descriptions.............................................................................................. 2827
Table 28-19. CAN_GLB_INT_FLG Register Field Descriptions............................................................................................ 2828
Table 28-20. CAN_GLB_INT_CLR Register Field Descriptions............................................................................................ 2829
Table 28-21. CAN_ABOTR Register Field Descriptions........................................................................................................ 2830
Table 28-22. CAN_TXRQ_X Register Field Descriptions...................................................................................................... 2831
Table 28-23. CAN_TXRQ_21 Register Field Descriptions.................................................................................................... 2832
Table 28-24. CAN_NDAT_X Register Field Descriptions.......................................................................................................2833
Table 28-25. CAN_NDAT_21 Register Field Descriptions..................................................................................................... 2834
Table 28-26. CAN_IPEN_X Register Field Descriptions........................................................................................................2835
Table 28-27. CAN_IPEN_21 Register Field Descriptions...................................................................................................... 2836
Table 28-28. CAN_MVAL_X Register Field Descriptions.......................................................................................................2837
Table 28-29. CAN_MVAL_21 Register Field Descriptions..................................................................................................... 2838
Table 28-30. CAN_IP_MUX21 Register Field Descriptions................................................................................................... 2839
Table 28-31. CAN_IF1CMD Register Field Descriptions....................................................................................................... 2840
Table 28-32. CAN_IF1MSK Register Field Descriptions....................................................................................................... 2843
Table 28-33. CAN_IF1ARB Register Field Descriptions........................................................................................................2844
Table 28-34. CAN_IF1MCTL Register Field Descriptions..................................................................................................... 2846
Table 28-35. CAN_IF1DATA Register Field Descriptions...................................................................................................... 2848
Table 28-36. CAN_IF1DATB Register Field Descriptions...................................................................................................... 2849
Table 28-37. CAN_IF2CMD Register Field Descriptions....................................................................................................... 2850
Table 28-38. CAN_IF2MSK Register Field Descriptions....................................................................................................... 2853
Table 28-39. CAN_IF2ARB Register Field Descriptions........................................................................................................2854
Table 28-40. CAN_IF2MCTL Register Field Descriptions..................................................................................................... 2856
Table 28-41. CAN_IF2DATA Register Field Descriptions...................................................................................................... 2858
Table 28-42. CAN_IF2DATB Register Field Descriptions...................................................................................................... 2859
Table 28-43. CAN_IF3OBS Register Field Descriptions........................................................................................................2860
Table 28-44. CAN_IF3MSK Register Field Descriptions....................................................................................................... 2862
Table 28-45. CAN_IF3ARB Register Field Descriptions........................................................................................................2863
Table 28-46. CAN_IF3MCTL Register Field Descriptions..................................................................................................... 2864
Table 28-47. CAN_IF3DATA Register Field Descriptions...................................................................................................... 2866
Table 28-48. CAN_IF3DATB Register Field Descriptions...................................................................................................... 2867
Table 28-49. CAN_IF3UPD Register Field Descriptions........................................................................................................2868
Table 28-50. CAN Registers to Driverlib Functions............................................................................................................... 2868
Table 29-1. MCAN I/O Description.........................................................................................................................................2876
Table 29-2. MCAN Clocks and Resets.................................................................................................................................. 2878
Table 29-3. MCAN Hardware Requests.................................................................................................................................2878
Table 29-4. Steps to Configure MCAN Module......................................................................................................................2881
Table 29-5. CAN FD Frame Description................................................................................................................................ 2882
Table 29-6. DLC Coding in CAN FD...................................................................................................................................... 2883
Table 29-7. Rx Buffer/Rx FIFO Element Size........................................................................................................................ 2901
Table 29-8. Example Filter Configuration for Rx Buffers........................................................................................................2903
Table 29-9. Possible Configurations for Message Transmission........................................................................................... 2903
Table 29-10. Tx Buffer, Tx FIFO, Tx Queue Element Size.....................................................................................................2904
Table 29-11. Rx Buffer/Rx FIFO Element Field Descriptions................................................................................................. 2909

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Table 29-12. Tx Buffer Element Field Descriptions................................................................................................................ 2911

Table 29-13. Tx Event FIFO Element Field Descriptions.......................................................................................................2913
Table 29-14. Standard Message ID Filter Element Field Descriptions.................................................................................. 2915
Table 29-15. Extended Message ID Filter Element Field Descriptions..................................................................................2916
Table 29-16. MCAN Base Address Table.............................................................................................................................. 2921
Table 29-17. MCANSS_REGS Registers.............................................................................................................................. 2922
Table 29-18. MCANSS_REGS Access Type Codes..............................................................................................................2922
Table 29-19. MCANSS_PID Register Field Descriptions.......................................................................................................2924
Table 29-20. MCANSS_CTRL Register Field Descriptions................................................................................................... 2925
Table 29-21. MCANSS_STAT Register Field Descriptions.................................................................................................... 2926
Table 29-22. MCANSS_ICS Register Field Descriptions.......................................................................................................2927
Table 29-23. MCANSS_IRS Register Field Descriptions.......................................................................................................2928
Table 29-24. MCANSS_IECS Register Field Descriptions.................................................................................................... 2929
Table 29-25. MCANSS_IE Register Field Descriptions......................................................................................................... 2930
Table 29-26. MCANSS_IES Register Field Descriptions.......................................................................................................2931
Table 29-27. MCANSS_EOI Register Field Descriptions...................................................................................................... 2932
Table 29-28. MCANSS_EXT_TS_PRESCALER Register Field Descriptions....................................................................... 2933
Table 29-29. MCANSS_EXT_TS_UNSERVICED_INTR_CNTR Register Field Descriptions............................................... 2934
Table 29-30. MCAN_REGS Registers................................................................................................................................... 2935
Table 29-31. MCAN_REGS Access Type Codes.................................................................................................................. 2936
Table 29-32. MCAN_CREL Register Field Descriptions........................................................................................................2937
Table 29-33. MCAN_ENDN Register Field Descriptions....................................................................................................... 2938
Table 29-34. MCAN_DBTP Register Field Descriptions........................................................................................................2939
Table 29-35. MCAN_TEST Register Field Descriptions........................................................................................................ 2941
Table 29-36. MCAN_RWD Register Field Descriptions......................................................................................................... 2942
Table 29-37. MCAN_CCCR Register Field Descriptions....................................................................................................... 2943
Table 29-38. MCAN_NBTP Register Field Descriptions........................................................................................................2946
Table 29-39. MCAN_TSCC Register Field Descriptions........................................................................................................2948
Table 29-40. MCAN_TSCV Register Field Descriptions........................................................................................................2949
Table 29-41. MCAN_TOCC Register Field Descriptions....................................................................................................... 2950
Table 29-42. MCAN_TOCV Register Field Descriptions........................................................................................................2951
Table 29-43. MCAN_ECR Register Field Descriptions..........................................................................................................2952
Table 29-44. MCAN_PSR Register Field Descriptions.......................................................................................................... 2953
Table 29-45. MCAN_TDCR Register Field Descriptions....................................................................................................... 2956
Table 29-46. MCAN_IR Register Field Descriptions..............................................................................................................2957
Table 29-47. MCAN_IE Register Field Descriptions.............................................................................................................. 2960
Table 29-48. MCAN_ILS Register Field Descriptions............................................................................................................ 2962
Table 29-49. MCAN_ILE Register Field Descriptions............................................................................................................ 2965
Table 29-50. MCAN_GFC Register Field Descriptions..........................................................................................................2966
Table 29-51. MCAN_SIDFC Register Field Descriptions.......................................................................................................2967
Table 29-52. MCAN_XIDFC Register Field Descriptions.......................................................................................................2968
Table 29-53. MCAN_XIDAM Register Field Descriptions...................................................................................................... 2969
Table 29-54. MCAN_HPMS Register Field Descriptions....................................................................................................... 2970
Table 29-55. MCAN_NDAT1 Register Field Descriptions...................................................................................................... 2971
Table 29-56. MCAN_NDAT2 Register Field Descriptions...................................................................................................... 2974
Table 29-57. MCAN_RXF0C Register Field Descriptions......................................................................................................2977
Table 29-58. MCAN_RXF0S Register Field Descriptions......................................................................................................2978
Table 29-59. MCAN_RXF0A Register Field Descriptions......................................................................................................2979
Table 29-60. MCAN_RXBC Register Field Descriptions....................................................................................................... 2980
Table 29-61. MCAN_RXF1C Register Field Descriptions......................................................................................................2981
Table 29-62. MCAN_RXF1S Register Field Descriptions......................................................................................................2982
Table 29-63. MCAN_RXF1A Register Field Descriptions......................................................................................................2983
Table 29-64. MCAN_RXESC Register Field Descriptions..................................................................................................... 2984
Table 29-65. MCAN_TXBC Register Field Descriptions........................................................................................................2986
Table 29-66. MCAN_TXFQS Register Field Descriptions..................................................................................................... 2988
Table 29-67. MCAN_TXESC Register Field Descriptions..................................................................................................... 2989
Table 29-68. MCAN_TXBRP Register Field Descriptions..................................................................................................... 2990
Table 29-69. MCAN_TXBAR Register Field Descriptions..................................................................................................... 2993
Table 29-70. MCAN_TXBCR Register Field Descriptions..................................................................................................... 2995
Table 29-71. MCAN_TXBTO Register Field Descriptions......................................................................................................2997
Table 29-72. MCAN_TXBCF Register Field Descriptions......................................................................................................2999

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Table 29-73. MCAN_TXBTIE Register Field Descriptions.....................................................................................................3001

Table 29-74. MCAN_TXBCIE Register Field Descriptions.................................................................................................... 3005
Table 29-75. MCAN_TXEFC Register Field Descriptions......................................................................................................3009
Table 29-76. MCAN_TXEFS Register Field Descriptions......................................................................................................3010
Table 29-77. MCAN_TXEFA Register Field Descriptions...................................................................................................... 3011
Table 29-78. MCAN_ERROR_REGS Registers.................................................................................................................... 3012
Table 29-79. MCAN_ERROR_REGS Access Type Codes................................................................................................... 3012
Table 29-80. MCANERR_REV Register Field Descriptions.................................................................................................. 3014
Table 29-81. MCANERR_VECTOR Register Field Descriptions........................................................................................... 3015
Table 29-82. MCANERR_STAT Register Field Descriptions................................................................................................. 3016
Table 29-83. MCANERR_WRAP_REV Register Field Descriptions......................................................................................3017
Table 29-84. MCANERR_CTRL Register Field Descriptions................................................................................................ 3018
Table 29-85. MCANERR_ERR_CTRL1 Register Field Descriptions.....................................................................................3020
Table 29-86. MCANERR_ERR_CTRL2 Register Field Descriptions.....................................................................................3021
Table 29-87. MCANERR_ERR_STAT1 Register Field Descriptions......................................................................................3022
Table 29-88. MCANERR_ERR_STAT2 Register Field Descriptions......................................................................................3024
Table 29-89. MCANERR_ERR_STAT3 Register Field Descriptions......................................................................................3025
Table 29-90. MCANERR_SEC_EOI Register Field Descriptions.......................................................................................... 3026
Table 29-91. MCANERR_SEC_STATUS Register Field Descriptions...................................................................................3027
Table 29-92. MCANERR_SEC_ENABLE_SET Register Field Descriptions......................................................................... 3028
Table 29-93. MCANERR_SEC_ENABLE_CLR Register Field Descriptions......................................................................... 3029
Table 29-94. MCANERR_DED_EOI Register Field Descriptions.......................................................................................... 3030
Table 29-95. MCANERR_DED_STATUS Register Field Descriptions...................................................................................3031
Table 29-96. MCANERR_DED_ENABLE_SET Register Field Descriptions......................................................................... 3032
Table 29-97. MCANERR_DED_ENABLE_CLR Register Field Descriptions.........................................................................3033
Table 29-98. MCANERR_AGGR_ENABLE_SET Register Field Descriptions...................................................................... 3034
Table 29-99. MCANERR_AGGR_ENABLE_CLR Register Field Descriptions......................................................................3035
Table 29-100. MCANERR_AGGR_STATUS_SET Register Field Descriptions.....................................................................3036
Table 29-101. MCANERR_AGGR_STATUS_CLR Register Field Descriptions.................................................................... 3037
Table 29-102. MCAN Registers to Driverlib Functions.......................................................................................................... 3037
Table 30-1. Superfractional Bit Modulation for SCI Mode (Normal Configuration)................................................................ 3052
Table 30-2. Superfractional Bit Modulation for SCI Mode (Maximum Configuration)............................................................ 3053
Table 30-3. SCI Mode (Minimum Configuration)....................................................................................................................3053
Table 30-4. Comparative Baud Values for Different P Values, Asynchronous Mode.............................................................3054
Table 30-5. SCI/LIN Interrupts............................................................................................................................................... 3061
Table 30-6. SCI Receiver Status Flags..................................................................................................................................3062
Table 30-7. SCI Transmitter Status Flags.............................................................................................................................. 3062
Table 30-8. Response Length Info Using IDBYTE Field Bits [5:4] for LIN Standards Earlier than v1.3................................ 3069
Table 30-9. Response Length with SCIFORMAT[18:16] Programming................................................................................. 3069
Table 30-10. Superfractional Bit Modulation for LIN Master Mode and Slave Mode............................................................. 3071
Table 30-11. Timeout Values in Tbit Units...............................................................................................................................3079
Table 30-12. LIN Base Address Table................................................................................................................................... 3094
Table 30-13. LIN_REGS Registers........................................................................................................................................ 3095
Table 30-14. LIN_REGS Access Type Codes....................................................................................................................... 3095
Table 30-15. SCIGCR0 Register Field Descriptions.............................................................................................................. 3097
Table 30-16. SCIGCR1 Register Field Descriptions.............................................................................................................. 3098
Table 30-17. SCIGCR2 Register Field Descriptions.............................................................................................................. 3103
Table 30-18. SCISETINT Register Field Descriptions........................................................................................................... 3105
Table 30-19. SCICLEARINT Register Field Descriptions...................................................................................................... 3109
Table 30-20. SCISETINTLVL Register Field Descriptions..................................................................................................... 3112
Table 30-21. SCICLEARINTLVL Register Field Descriptions................................................................................................ 3115
Table 30-22. SCIFLR Register Field Descriptions..................................................................................................................3118
Table 30-23. SCIINTVECT0 Register Field Descriptions.......................................................................................................3126
Table 30-24. SCIINTVECT1 Register Field Descriptions.......................................................................................................3127
Table 30-25. SCIFORMAT Register Field Descriptions......................................................................................................... 3128
Table 30-26. BRSR Register Field Descriptions.................................................................................................................... 3129
Table 30-27. SCIED Register Field Descriptions................................................................................................................... 3131
Table 30-28. SCIRD Register Field Descriptions...................................................................................................................3132
Table 30-29. SCITD Register Field Descriptions................................................................................................................... 3133
Table 30-30. SCIPIO0 Register Field Descriptions................................................................................................................3134
Table 30-31. SCIPIO2 Register Field Descriptions................................................................................................................3135

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Table 30-32. LINCOMP Register Field Descriptions..............................................................................................................3136

Table 30-33. LINRD0 Register Field Descriptions................................................................................................................. 3137
Table 30-34. LINRD1 Register Field Descriptions................................................................................................................. 3138
Table 30-35. LINMASK Register Field Descriptions.............................................................................................................. 3139
Table 30-36. LINID Register Field Descriptions.....................................................................................................................3140
Table 30-37. LINTD0 Register Field Descriptions..................................................................................................................3141
Table 30-38. LINTD1 Register Field Descriptions..................................................................................................................3142
Table 30-39. MBRSR Register Field Descriptions................................................................................................................. 3143
Table 30-40. IODFTCTRL Register Field Descriptions..........................................................................................................3144
Table 30-41. LIN_GLB_INT_EN Register Field Descriptions................................................................................................ 3147
Table 30-42. LIN_GLB_INT_FLG Register Field Descriptions.............................................................................................. 3148
Table 30-43. LIN_GLB_INT_CLR Register Field Descriptions.............................................................................................. 3149
Table 30-44. LIN Registers to Driverlib Functions................................................................................................................. 3149
Table 31-1. FSI Receiver Core Signals..................................................................................................................................3159
Table 31-2. FSI Transmitter Core Signals..............................................................................................................................3159
Table 31-3. External Trigger Sources and Their Index.......................................................................................................... 3163
Table 31-4. Basic Frame Structure........................................................................................................................................ 3177
Table 31-5. Frame Types and Their 4-bit Codes................................................................................................................... 3179
Table 31-6. Ping Frame......................................................................................................................................................... 3179
Table 31-7. Error Frame.........................................................................................................................................................3180
Table 31-8. Data Frame......................................................................................................................................................... 3180
Table 31-9. Multi-Lane Frame Format................................................................................................................................... 3180
Table 31-10. RX_TRIGx Trigger Select Signals.....................................................................................................................3186
Table 31-11. FSI-SPI Compatibility Frame Structure............................................................................................................. 3188
Table 31-12. Contents of Data Received by a Standard SPI.................................................................................................3188
Table 31-13. FSI as Master Transmitter, SPI as Slave Receiver........................................................................................... 3189
Table 31-14. SPI as Master Transmitter, FSI as Slave Receiver........................................................................................... 3190
Table 31-15. FSI Base Address Table................................................................................................................................... 3203
Table 31-16. FSI_TX_REGS Registers................................................................................................................................. 3204
Table 31-17. FSI_TX_REGS Access Type Codes.................................................................................................................3204
Table 31-18. TX_MASTER_CTRL Register Field Descriptions............................................................................................. 3206
Table 31-19. TX_CLK_CTRL Register Field Descriptions..................................................................................................... 3207
Table 31-20. TX_OPER_CTRL_LO Register Field Descriptions........................................................................................... 3208
Table 31-21. TX_OPER_CTRL_HI Register Field Descriptions............................................................................................ 3210
Table 31-22. TX_FRAME_CTRL Register Field Descriptions................................................................................................3211
Table 31-23. TX_FRAME_TAG_UDATA Register Field Descriptions.................................................................................... 3212
Table 31-24. TX_BUF_PTR_LOAD Register Field Descriptions........................................................................................... 3213
Table 31-25. TX_BUF_PTR_STS Register Field Descriptions.............................................................................................. 3214
Table 31-26. TX_PING_CTRL Register Field Descriptions................................................................................................... 3215
Table 31-27. TX_PING_TAG Register Field Descriptions......................................................................................................3216
Table 31-28. TX_PING_TO_REF Register Field Descriptions...............................................................................................3217
Table 31-29. TX_PING_TO_CNT Register Field Descriptions.............................................................................................. 3218
Table 31-30. TX_INT_CTRL Register Field Descriptions...................................................................................................... 3219
Table 31-31. TX_DMA_CTRL Register Field Descriptions.................................................................................................... 3221
Table 31-32. TX_LOCK_CTRL Register Field Descriptions.................................................................................................. 3222
Table 31-33. TX_EVT_STS Register Field Descriptions....................................................................................................... 3223
Table 31-34. TX_EVT_CLR Register Field Descriptions....................................................................................................... 3224
Table 31-35. TX_EVT_FRC Register Field Descriptions....................................................................................................... 3225
Table 31-36. TX_USER_CRC Register Field Descriptions....................................................................................................3226
Table 31-37. TX_ECC_DATA Register Field Descriptions.....................................................................................................3227
Table 31-38. TX_ECC_VAL Register Field Descriptions....................................................................................................... 3228
Table 31-39. TX_DLYLINE_CTRL Register Field Descriptions............................................................................................. 3229
Table 31-40. TX_BUF_BASE_y Register Field Descriptions.................................................................................................3230
Table 31-41. FSI_RX_REGS Registers................................................................................................................................. 3231
Table 31-42. FSI_RX_REGS Access Type Codes................................................................................................................ 3232
Table 31-43. RX_MASTER_CTRL Register Field Descriptions.............................................................................................3233
Table 31-44. RX_OPER_CTRL Register Field Descriptions................................................................................................. 3235
Table 31-45. RX_FRAME_INFO Register Field Descriptions................................................................................................3236
Table 31-46. RX_FRAME_TAG_UDATA Register Field Descriptions....................................................................................3237
Table 31-47. RX_DMA_CTRL Register Field Descriptions....................................................................................................3238
Table 31-48. RX_EVT_STS Register Field Descriptions....................................................................................................... 3239

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Table 31-49. RX_CRC_INFO Register Field Descriptions.....................................................................................................3242

Table 31-50. RX_EVT_CLR Register Field Descriptions.......................................................................................................3243
Table 31-51. RX_EVT_FRC Register Field Descriptions.......................................................................................................3245
Table 31-52. RX_BUF_PTR_LOAD Register Field Descriptions...........................................................................................3248
Table 31-53. RX_BUF_PTR_STS Register Field Descriptions..............................................................................................3249
Table 31-54. RX_FRAME_WD_CTRL Register Field Descriptions....................................................................................... 3250
Table 31-55. RX_FRAME_WD_REF Register Field Descriptions......................................................................................... 3251
Table 31-56. RX_FRAME_WD_CNT Register Field Descriptions......................................................................................... 3252
Table 31-57. RX_PING_WD_CTRL Register Field Descriptions...........................................................................................3253
Table 31-58. RX_PING_TAG Register Field Descriptions..................................................................................................... 3254
Table 31-59. RX_PING_WD_REF Register Field Descriptions............................................................................................. 3255
Table 31-60. RX_PING_WD_CNT Register Field Descriptions.............................................................................................3256
Table 31-61. RX_INT1_CTRL Register Field Descriptions....................................................................................................3257
Table 31-62. RX_INT2_CTRL Register Field Descriptions....................................................................................................3260
Table 31-63. RX_LOCK_CTRL Register Field Descriptions..................................................................................................3263
Table 31-64. RX_ECC_DATA Register Field Descriptions.................................................................................................... 3264
Table 31-65. RX_ECC_VAL Register Field Descriptions....................................................................................................... 3265
Table 31-66. RX_ECC_SEC_DATA Register Field Descriptions........................................................................................... 3266
Table 31-67. RX_ECC_LOG Register Field Descriptions......................................................................................................3267
Table 31-68. RX_FRAME_TAG_CMP Register Field Descriptions....................................................................................... 3268
Table 31-69. RX_PING_TAG_CMP Register Field Descriptions........................................................................................... 3269
Table 31-70. RX_TRIG_CTRL_0 Register Field Descriptions............................................................................................... 3270
Table 31-71. RX_TRIG_WIDTH_0 Register Field Descriptions.............................................................................................3271
Table 31-72. RX_DLYLINE_CTRL Register Field Descriptions............................................................................................. 3272
Table 31-73. RX_TRIG_CTRL_1 Register Field Descriptions............................................................................................... 3273
Table 31-74. RX_TRIG_CTRL_2 Register Field Descriptions............................................................................................... 3274
Table 31-75. RX_TRIG_CTRL_3 Register Field Descriptions............................................................................................... 3275
Table 31-76. RX_VIS_1 Register Field Descriptions............................................................................................................. 3276
Table 31-77. RX_UDATA_FILTER Register Field Descriptions............................................................................................. 3277
Table 31-78. RX_BUF_BASE_y Register Field Descriptions................................................................................................ 3278
Table 31-79. FSI Registers to Driverlib Functions................................................................................................................. 3278
Table 32-1. Example CLB Clocking Configuration.................................................................................................................3286
Table 32-2. Global Signals and Mux Selection...................................................................................................................... 3289
Table 32-3. Local Signals and Mux Selection........................................................................................................................ 3293
Table 32-4. CLB Output Signal Multiplexer Table.................................................................................................................. 3297
Table 32-5. Output Table........................................................................................................................................................3300
Table 32-6. Input Table.......................................................................................................................................................... 3301
Table 32-7. Ports Tied Off to Prevent Combinatorial Loops...................................................................................................3301
Table 32-8. Counter Block Operating Modes.........................................................................................................................3304
Table 32-9. HLC Event List.................................................................................................................................................... 3312
Table 32-10. HLC Instruction Address Ranges......................................................................................................................3313
Table 32-11. HLC Instruction Format..................................................................................................................................... 3313
Table 32-12. HLC Instruction Description.............................................................................................................................. 3313
Table 32-13. HLC Register Encoding.................................................................................................................................... 3314
Table 32-14. Non-Memory Mapped Register Addresses.......................................................................................................3316
Table 32-15. CLB to SPI RX Access......................................................................................................................................3317
Table 32-16. CLB Base Address Table.................................................................................................................................. 3323
Table 32-17. CLB_LOGIC_CONFIG_REGS Registers......................................................................................................... 3324
Table 32-18. CLB_LOGIC_CONFIG_REGS Access Type Codes.........................................................................................3325
Table 32-19. CLB_COUNT_RESET Register Field Descriptions.......................................................................................... 3326
Table 32-20. CLB_COUNT_MODE_1 Register Field Descriptions....................................................................................... 3327
Table 32-21. CLB_COUNT_MODE_0 Register Field Descriptions....................................................................................... 3328
Table 32-22. CLB_COUNT_EVENT Register Field Descriptions.......................................................................................... 3329
Table 32-23. CLB_FSM_EXTRA_IN0 Register Field Descriptions........................................................................................3330
Table 32-24. CLB_FSM_EXTERNAL_IN0 Register Field Descriptions.................................................................................3331
Table 32-25. CLB_FSM_EXTERNAL_IN1 Register Field Descriptions.................................................................................3332
Table 32-26. CLB_FSM_EXTRA_IN1 Register Field Descriptions........................................................................................3333
Table 32-27. CLB_LUT4_IN0 Register Field Descriptions.....................................................................................................3334
Table 32-28. CLB_LUT4_IN1 Register Field Descriptions.....................................................................................................3335
Table 32-29. CLB_LUT4_IN2 Register Field Descriptions.....................................................................................................3336
Table 32-30. CLB_LUT4_IN3 Register Field Descriptions.....................................................................................................3337

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Table 32-31. CLB_FSM_LUT_FN1_0 Register Field Descriptions........................................................................................3338

Table 32-32. CLB_FSM_LUT_FN2 Register Field Descriptions............................................................................................3339
Table 32-33. CLB_LUT4_FN1_0 Register Field Descriptions............................................................................................... 3340
Table 32-34. CLB_LUT4_FN2 Register Field Descriptions................................................................................................... 3341
Table 32-35. CLB_FSM_NEXT_STATE_0 Register Field Descriptions.................................................................................3342
Table 32-36. CLB_FSM_NEXT_STATE_1 Register Field Descriptions.................................................................................3343
Table 32-37. CLB_FSM_NEXT_STATE_2 Register Field Descriptions.................................................................................3344
Table 32-38. CLB_MISC_CONTROL Register Field Descriptions........................................................................................ 3345
Table 32-39. CLB_OUTPUT_LUT_0 Register Field Descriptions......................................................................................... 3348
Table 32-40. CLB_OUTPUT_LUT_1 Register Field Descriptions......................................................................................... 3349
Table 32-41. CLB_OUTPUT_LUT_2 Register Field Descriptions......................................................................................... 3350
Table 32-42. CLB_OUTPUT_LUT_3 Register Field Descriptions......................................................................................... 3351
Table 32-43. CLB_OUTPUT_LUT_4 Register Field Descriptions......................................................................................... 3352
Table 32-44. CLB_OUTPUT_LUT_5 Register Field Descriptions......................................................................................... 3353
Table 32-45. CLB_OUTPUT_LUT_6 Register Field Descriptions......................................................................................... 3354
Table 32-46. CLB_OUTPUT_LUT_7 Register Field Descriptions......................................................................................... 3355
Table 32-47. CLB_HLC_EVENT_SEL Register Field Descriptions....................................................................................... 3356
Table 32-48. CLB_COUNT_MATCH_TAP_SEL Register Field Descriptions........................................................................ 3357
Table 32-49. CLB_OUTPUT_COND_CTRL_0 Register Field Descriptions.......................................................................... 3358
Table 32-50. CLB_OUTPUT_COND_CTRL_1 Register Field Descriptions.......................................................................... 3360
Table 32-51. CLB_OUTPUT_COND_CTRL_2 Register Field Descriptions.......................................................................... 3362
Table 32-52. CLB_OUTPUT_COND_CTRL_3 Register Field Descriptions.......................................................................... 3364
Table 32-53. CLB_OUTPUT_COND_CTRL_4 Register Field Descriptions.......................................................................... 3366
Table 32-54. CLB_OUTPUT_COND_CTRL_5 Register Field Descriptions.......................................................................... 3368
Table 32-55. CLB_OUTPUT_COND_CTRL_6 Register Field Descriptions.......................................................................... 3370
Table 32-56. CLB_OUTPUT_COND_CTRL_7 Register Field Descriptions.......................................................................... 3372
Table 32-57. CLB_MISC_ACCESS_CTRL Register Field Descriptions................................................................................3374
Table 32-58. CLB_SPI_DATA_CTRL_HI Register Field Descriptions................................................................................... 3375
Table 32-59. CLB_LOGIC_CONTROL_REGS Registers......................................................................................................3376
Table 32-60. CLB_LOGIC_CONTROL_REGS Access Type Codes..................................................................................... 3376
Table 32-61. CLB_LOAD_EN Register Field Descriptions.................................................................................................... 3378
Table 32-62. CLB_LOAD_ADDR Register Field Descriptions............................................................................................... 3379
Table 32-63. CLB_LOAD_DATA Register Field Descriptions................................................................................................ 3380
Table 32-64. CLB_INPUT_FILTER Register Field Descriptions............................................................................................ 3381
Table 32-65. CLB_IN_MUX_SEL_0 Register Field Descriptions...........................................................................................3383
Table 32-66. CLB_LCL_MUX_SEL_1 Register Field Descriptions........................................................................................3385
Table 32-67. CLB_LCL_MUX_SEL_2 Register Field Descriptions........................................................................................3386
Table 32-68. CLB_BUF_PTR Register Field Descriptions.....................................................................................................3387
Table 32-69. CLB_GP_REG Register Field Descriptions...................................................................................................... 3388
Table 32-70. CLB_OUT_EN Register Field Descriptions...................................................................................................... 3390
Table 32-71. CLB_GLBL_MUX_SEL_1 Register Field Descriptions..................................................................................... 3391
Table 32-72. CLB_GLBL_MUX_SEL_2 Register Field Descriptions..................................................................................... 3392
Table 32-73. CLB_PRESCALE_CTRL Register Field Descriptions...................................................................................... 3393
Table 32-74. CLB_INTR_TAG_REG Register Field Descriptions..........................................................................................3394
Table 32-75. CLB_LOCK Register Field Descriptions........................................................................................................... 3395
Table 32-76. CLB_HLC_INSTR_READ_PTR Register Field Descriptions............................................................................3396
Table 32-77. CLB_HLC_INSTR_VALUE Register Field Descriptions....................................................................................3397
Table 32-78. CLB_DBG_OUT_2 Register Field Descriptions................................................................................................3398
Table 32-79. CLB_DBG_R0 Register Field Descriptions.......................................................................................................3399
Table 32-80. CLB_DBG_R1 Register Field Descriptions.......................................................................................................3400
Table 32-81. CLB_DBG_R2 Register Field Descriptions.......................................................................................................3401
Table 32-82. CLB_DBG_R3 Register Field Descriptions.......................................................................................................3402
Table 32-83. CLB_DBG_C0 Register Field Descriptions.......................................................................................................3403
Table 32-84. CLB_DBG_C1 Register Field Descriptions.......................................................................................................3404
Table 32-85. CLB_DBG_C2 Register Field Descriptions.......................................................................................................3405
Table 32-86. CLB_DBG_OUT Register Field Descriptions....................................................................................................3406
Table 32-87. CLB_DATA_EXCHANGE_REGS Registers..................................................................................................... 3408
Table 32-88. CLB_DATA_EXCHANGE_REGS Access Type Codes.....................................................................................3408
Table 32-89. CLB_PUSH_y Register Field Descriptions....................................................................................................... 3409
Table 32-90. CLB_PULL_y Register Field Descriptions........................................................................................................ 3410
Table 32-91. CLB Registers to Driverlib Functions................................................................................................................ 3410

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Table 33-1. AES Subsystem DMA Interface.......................................................................................................................... 3418

Table 33-2. Key-Block-Round Combinations......................................................................................................................... 3419
Table 33-3. Interrupts and Events..........................................................................................................................................3430
Table 33-4. AES Base Address Table....................................................................................................................................3437
Table 33-5. AES_REGS Registers........................................................................................................................................ 3438
Table 33-6. AES_REGS Access Type Codes........................................................................................................................3439
Table 33-7. AES_KEY2_6 Register Field Descriptions..........................................................................................................3440
Table 33-8. AES_KEY2_7 Register Field Descriptions..........................................................................................................3441
Table 33-9. AES_KEY2_4 Register Field Descriptions..........................................................................................................3442
Table 33-10. AES_KEY2_5 Register Field Descriptions........................................................................................................3443
Table 33-11. AES_KEY2_2 Register Field Descriptions........................................................................................................ 3444
Table 33-12. AES_KEY2_3 Register Field Descriptions........................................................................................................3445
Table 33-13. AES_KEY2_0 Register Field Descriptions........................................................................................................3446
Table 33-14. AES_KEY2_1 Register Field Descriptions........................................................................................................3447
Table 33-15. AES_KEY1_6 Register Field Descriptions........................................................................................................3448
Table 33-16. AES_KEY1_7 Register Field Descriptions........................................................................................................3449
Table 33-17. AES_KEY1_4 Register Field Descriptions........................................................................................................3450
Table 33-18. AES_KEY1_5 Register Field Descriptions........................................................................................................3451
Table 33-19. AES_KEY1_2 Register Field Descriptions........................................................................................................3452
Table 33-20. AES_KEY1_3 Register Field Descriptions........................................................................................................3453
Table 33-21. AES_KEY1_0 Register Field Descriptions........................................................................................................3454
Table 33-22. AES_KEY1_1 Register Field Descriptions........................................................................................................3455
Table 33-23. AES_IV_IN_OUT_0 Register Field Descriptions.............................................................................................. 3456
Table 33-24. AES_IV_IN_OUT_1 Register Field Descriptions.............................................................................................. 3457
Table 33-25. AES_IV_IN_OUT_2 Register Field Descriptions.............................................................................................. 3458
Table 33-26. AES_IV_IN_OUT_3 Register Field Descriptions.............................................................................................. 3459
Table 33-27. AES_CTRL Register Field Descriptions........................................................................................................... 3460
Table 33-28. AES_C_LENGTH_0 Register Field Descriptions..............................................................................................3464
Table 33-29. AES_C_LENGTH_1 Register Field Descriptions..............................................................................................3465
Table 33-30. AES_AUTH_LENGTH Register Field Descriptions.......................................................................................... 3466
Table 33-31. AES_DATA_IN_OUT_0 Register Field Descriptions.........................................................................................3467
Table 33-32. AES_DATA_IN_OUT_1 Register Field Descriptions.........................................................................................3468
Table 33-33. AES_DATA_IN_OUT_2 Register Field Descriptions.........................................................................................3469
Table 33-34. AES_DATA_IN_OUT_3 Register Field Descriptions.........................................................................................3470
Table 33-35. AES_TAG_OUT_0 Register Field Descriptions................................................................................................ 3471
Table 33-36. AES_TAG_OUT_1 Register Field Descriptions................................................................................................ 3472
Table 33-37. AES_TAG_OUT_2 Register Field Descriptions................................................................................................ 3473
Table 33-38. AES_TAG_OUT_3 Register Field Descriptions................................................................................................ 3474
Table 33-39. AES_REV Register Field Descriptions............................................................................................................. 3475
Table 33-40. AES_SYSCONFIG Register Field Descriptions................................................................................................3476
Table 33-41. AES_SYSSTATUS Register Field Descriptions................................................................................................ 3478
Table 33-42. AES_IRQSTATUS Register Field Descriptions.................................................................................................3479
Table 33-43. AES_IRQENABLE Register Field Descriptions................................................................................................ 3480
Table 33-44. AES_DIRTY_BITS Register Field Descriptions................................................................................................ 3481
Table 33-45. AES_SS_REGS Registers................................................................................................................................3482
Table 33-46. AES_SS_REGS Access Type Codes............................................................................................................... 3482
Table 33-47. AES_GLB_INT_FLG Register Field Descriptions.............................................................................................3483
Table 33-48. AES_GLB_INT_CLR Register Field Descriptions.............................................................................................3484
Table 33-49. AES Registers to Driverlib Functions................................................................................................................3485
Table 33-50. AES_SS Registers to Driverlib Functions......................................................................................................... 3487
Table 34-1. SIGGENx Active Register Loading..................................................................................................................... 3495
Table 34-2. EPG Data Input Connections..............................................................................................................................3498
Table 34-3. EPG Base Address Table................................................................................................................................... 3505
Table 34-4. EPG_REGS Registers........................................................................................................................................ 3506
Table 34-5. EPG_REGS Access Type Codes....................................................................................................................... 3506
Table 34-6. GCTL0 Register Field Descriptions.................................................................................................................... 3508
Table 34-7. GCTL1 Register Field Descriptions.................................................................................................................... 3509
Table 34-8. GCTL2 Register Field Descriptions.................................................................................................................... 3510
Table 34-9. GCTL3 Register Field Descriptions.................................................................................................................... 3512
Table 34-10. EPGLOCK Register Field Descriptions.............................................................................................................3515
Table 34-11. EPGCOMMIT Register Field Descriptions........................................................................................................ 3516

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Table 34-12. GINTSTS Register Field Descriptions.............................................................................................................. 3517

Table 34-13. GINTEN Register Field Descriptions................................................................................................................ 3518
Table 34-14. GINTCLR Register Field Descriptions.............................................................................................................. 3519
Table 34-15. GINTFRC Register Field Descriptions.............................................................................................................. 3520
Table 34-16. CLKDIV0_CTL0 Register Field Descriptions.................................................................................................... 3521
Table 34-17. CLKDIV0_CLKOFFSET Register Field Descriptions........................................................................................3522
Table 34-18. CLKDIV1_CTL0 Register Field Descriptions.................................................................................................... 3523
Table 34-19. CLKDIV1_CLKOFFSET Register Field Descriptions........................................................................................3524
Table 34-20. SIGGEN0_CTL0 Register Field Descriptions................................................................................................... 3525
Table 34-21. SIGGEN0_CTL1 Register Field Descriptions................................................................................................... 3527
Table 34-22. SIGGEN0_DATA0 Register Field Descriptions................................................................................................. 3528
Table 34-23. SIGGEN0_DATA1 Register Field Descriptions................................................................................................. 3529
Table 34-24. SIGGEN0_DATA0_ACTIVE Register Field Descriptions.................................................................................. 3530
Table 34-25. SIGGEN0_DATA1_ACTIVE Register Field Descriptions.................................................................................. 3531
Table 34-26. EPG_MUX_REGS Registers............................................................................................................................ 3532
Table 34-27. EPG_MUX_REGS Access Type Codes........................................................................................................... 3532
Table 34-28. EPGMXSEL0 Register Field Descriptions........................................................................................................ 3533
Table 34-29. EPGMXSELLOCK Register Field Descriptions................................................................................................ 3536
Table 34-30. EPGMXSELCOMMIT Register Field Descriptions............................................................................................3537
Table 34-31. EPG Registers to Driverlib Functions............................................................................................................... 3537

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www.ti.com Read This First

Preface
Read This First

About This Manual

This Technical Reference Manual (TRM) details the integration, the environment, the functional description, and
the programming models for each peripheral and subsystem in the device.
The TRM should not be considered a substitute for the data sheet, rather a companion guide that can be used
alongside the device-specific data sheet to understand the details to program the device. The primary purpose
of the TRM is to abstract the programming details of the device from the data sheet. This allows the data sheet
to outline the high-level features of the device without unnecessary information about register descriptions or
programming models.

Note
Texas Instruments is transitioning to use more inclusive terminology. Some language may be different
than what you would expect to see for certain technology areas.

Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers can be shown with the suffix h or the prefix 0x. For example, the following number is
40 hexadecimal (decimal 64): 40h or 0x40.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field
is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties with
default reset value below. A legend explains the notation used for the properties.
– Reserved bits in a register figure can have one of multiple meanings:
• Not implemented on the device
• Reserved for future device expansion
• Reserved for TI testing
• Reserved configurations of the device that are not supported
– Writing nondefault values to the Reserved bits could cause unexpected behavior and should be avoided.
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Related Documentation From Texas Instruments
For a complete listing of related documentation and development-support tools for these devices, visit the Texas
Instruments website at www.ti.com.
Additionally, the TMS320C28x DSP CPU and Instruction Set Reference Guide and the TMS320C28x Floating
Point Unit and Instruction Set Reference Guide must be used in conjunction with this TRM.
Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.

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Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
Trademarks
TI E2E™, C2000™, Code Composer Studio™, and Texas Instruments™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.

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www.ti.com C2000™ Microcontrollers Software Support

Chapter 1
C2000™ Microcontrollers Software Support

This chapter discusses the C2000Ware for the C2000™ microcontrollers. The C2000Ware can be downloaded
from: www.ti.com/tool/C2000WARE

1.1 Introduction.................................................................................................................................................................90
1.2 C2000Ware Structure................................................................................................................................................. 90
1.3 Documentation............................................................................................................................................................90
1.4 Devices........................................................................................................................................................................ 90
1.5 Libraries...................................................................................................................................................................... 90
1.6 Code Composer Studio™ Integrated Development Environment (IDE)................................................................90
1.7 SysConfig and PinMUX Tool......................................................................................................................................91

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1.1 Introduction
C2000Ware for the C2000™ microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device peripheral
examples, C2000Ware provides a solid foundation to begin development and evaluation of your product.
C2000Ware can be downloaded from: www.ti.com/tool/C2000WARE
1.2 C2000Ware Structure
The C2000Ware software package is organized into the following directory structure as shown in Table 1-1.
Table 1-1. C2000Ware Root Directories
Directory Name Description
boards Contains the hardware design schematics, BOM, Gerber files, and documentation for C2000 controlCARDS.
device_support Contains all device-specific support files, bit field headers and device development user's guides.
docs Contains the C2000Ware package user's guides and the HTML index page of all package documentation.
driverlib Contains the device-specific driver library and driver-based peripheral examples.
libraries Contains the device-specific and core libraries.

1.3 Documentation
Within C2000Ware, there is an extensive amount of development documentation ranging from board design
documentation, to library user's guides, to driver API documentation. The "boards" directory contains all the
hardware design, BOM, Gerber files, and more for controlCARDs. To assist with locating the necessary
documentation, an HTML page is provided that contains a full list of all the documents in the C2000Ware
package. Locate this page in the "docs" directory.
1.4 Devices
C2000Ware contains the necessary software and documentation to jumpstart development for C2000™
microcontrollers. Each device includes device-specific common source files, peripheral example projects, bit
field headers, and if available, a device peripheral driver library. Additionally, documentation is provided for each
device on how to set up a CCS project, as well as give an overview of all the included example projects and
assist with troubleshooting. For devices with a driver library, documentation is also included that details all the
peripheral APIs available.
To learn more about C2000™ microcontrollers, visit: www.ti.com/c2000.
1.5 Libraries
The libraries included in C2000Ware range from fixed-point and floating-point math libraries, to specialized DSP
libraries, as well as calibration libraries. Each library includes documentation and examples, where applicable.
Additionally, the Flash API files and boot ROM source code are located in the "libraries" directory.
1.6 Code Composer Studio™ Integrated Development Environment (IDE)
Code Composer Studio™ is an integrated development environment (IDE) that supports TI's microcontroller and
embedded processors portfolio. The Code Composer Studio™ IDE comprises a suite of tools used to develop
and debug embedded applications. The latest version of Code Composer Studio™ IDE can be obtained at:
www.ti.com/ccstudio
All projects and examples in C2000Ware are built for and tested with the Code Composer Studio™ IDE.
Although the Code Composer Studio™ IDE is not included with the C2000Ware installer, Code Composer
Studio™ IDE is easily obtainable in a variety of versions.

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1.7 SysConfig and PinMUX Tool

To help simplify configuration challenges and accelerate software development, Texas Instruments™ created
SysConfig, an intuitive and comprehensive collection of graphical utilities for configuring pins, peripherals,
subsystems, and other components. SysConfig helps you manage, expose, and resolve conflicts visually so that
you have more time to create differentiated applications.
The tool's output includes C header and code files that can be used with C2000Ware examples or used to
configure custom software.
The SysConfig tool automatically selects the pinmux settings that satisfy the entered requirements. The
SysConfig tool is delivered integrated in the Code Composer Studio™ IDE, in the C2000Ware GPIO example,
as a standalone installer, or can be used by way of the cloud tools portal at: dev.ti.com

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Chapter 2
C28x Processor

This chapter contains a short description of the C28x processor and extended instruction sets.
Further information can be found in the following documents:
• TMS320C28x CPU and Instruction Set Reference Guide
• TMS320C28x Extended Instruction Sets Technical Reference Manual
• Accelerators: Enhancing the Capabilities of the C2000 MCU Family Technical Brief
• TMS320C28x FPU Primer Application Report

2.1 Introduction.................................................................................................................................................................94
2.2 C28X Related Collateral............................................................................................................................................. 94
2.3 Features.......................................................................................................................................................................94
2.4 Floating-Point Unit......................................................................................................................................................94
2.5 Trigonometric Math Unit (TMU)................................................................................................................................. 95
2.6 VCRC Unit....................................................................................................................................................................95

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2.1 Introduction
The C28x CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal
processing, reduced instruction set computing (RISC), microcontroller architectures, firmware, and tool sets.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set
Reference Guide.
2.2 C28X Related Collateral

Foundational Materials
• C2000 Academy - C28x
• C2000 C28x Optimization Guide
• C2000 Software Guide
• Enhancing the Computational Performance of the C2000™ Microcontroller Family Application Report

Getting Started Materials

• C2000 Multicore Development User Guide
• C2000Ware - CLAMath
• C2000Ware - FPU Fast RTS
• C2000Ware - FPU Library
• C2000Ware - Fast Integer Division
• C2000Ware - Fixed Point Library
• C2000Ware - IQMath
• C2000Ware - VCU Library
• C2000Ware Libraries Overview
• CRC Engines in C2000 Devices Application Report
• Migrating Software From 8-Bit (Byte) Addressable CPU's to C28x CPU Application Report
• TMS320C28x Extended Instruction Sets Application Report
• TMS320C28x FPU Primer Application Report

Expert Materials
• Fast Integer Division - A Differentiated Offering From C2000 Product Family Application Report
2.3 Features
The CPU features include a modified Harvard architecture and circular addressing. The RISC features
are single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking,
and bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be
performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the
single-cycle instruction operation across the pipeline.
2.4 Floating-Point Unit
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by
adding registers and instructions to support IEEE single-precision floating point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit
registers. The additional floating-point unit registers are the following:
• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)
• Repeat Block Register (RB)
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be used in
high-priority interrupts for fast context save and restore of the floating-point registers.

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Fast Integer Division (FINTDIV) supports Truncated, Modulo and Euclidean division formats without cycle
penalty and provides results in integer and remainder representation.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
2.5 Trigonometric Math Unit (TMU)
The trigonometric math unit (TMU) extends the capabilities of a C28x+FPU by adding instructions and
leveraging existing FPU instructions to speed up the execution of common trigonometric and arithmetic
operations listed in Table 2-1.
Table 2-1. TMU Supported Instructions
Instructions C Equivalent Operation Pipeline Cycles
MPY2PIF32 RaH,RbH a = b * 2pi 2/3
DIV2PIF32 RaH,RbH a = b / 2pi 2/3
DIVF32 RaH,RbH,RcH a = b/c 5
SQRTF32 RaH,RbH a = sqrt(b) 5
SINPUF32 RaH,RbH a = sin(b*2pi) 4
COSPUF32 RaH,RbH a = cos(b*2pi) 4
ATANPUF32 RaH,RbH a = atan(b)/2pi 4
QUADF32 RaH,RbH,RcH,RdH Operation to assist in calculating ATANPU2 5

Exponent instruction IEXP2F32 and logarithmic instruction LOG2F32 have been added to support computation
of floating-point power function for the non-linear proportional integral derivative control (NLPID) component of
the C2000 Digital Control Library. These two added instructions reduce the power function calculations from a
typical of 300 cycles using library emulation to less than 10 cycles.
No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU instructions
use the existing FPU register set (R0H to R7H) to carry out their operations.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
2.6 VCRC Unit
Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity over
large data blocks, communication packets, or code sections. The C28x+VCRC can perform 8-bit, 16-bit, 24-bit,
and 32-bit CRCs. A CRC result register contains the current CRC, which is updated whenever a CRC instruction
is executed.
The following are the CRC polynomials used by the CRC calculation logic of VCRC:
• CRC8 polynomial = 0x07
• CRC16 polynomial1 = 0x8005
• CRC16 polynomial2 = 0x1021
• CRC24 polynomial = 0x5d6dcb
• CRC32 polynomial1 = 0x04c11db7
• CRC32 polynomial2 = 0x1edc6f41
This module can calculate CRCs for a byte of data in a single cycle. The CRC calculation for CRC8, CRC16,
CRC24 and CRC32 is done byte-wise (instead of computing on a complete 16-bit or 32-bit data read by the
C28x core) to match the byte-wise computation requirement mandated by various standards.
The VCRC Unit also allows the user to provide the size (1b-32b) and value of any polynomial to fit custom CRC
requirements. The CRC execution time increases to 3 cycles when using a custom polynomial.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.

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Chapter 3
System Control and Interrupts

The system-level functionality of this microcontroller configures the clocking, resets, and interrupts of the CPU
and peripherals, as well as the operation of the on-chip memories, timers, and security features.

3.1 Introduction.................................................................................................................................................................98
3.2 Power Management....................................................................................................................................................99
3.3 Device Identification and Configuration Registers................................................................................................. 99
3.4 Resets..........................................................................................................................................................................99
3.5 Peripheral Interrupts................................................................................................................................................ 102
3.6 Exceptions and Non-Maskable Interrupts.............................................................................................................. 114
3.7 Clocking.....................................................................................................................................................................116
3.8 32-Bit CPU Timers 0/1/2........................................................................................................................................... 128
3.9 Watchdog Timer........................................................................................................................................................129
3.10 Low Power Modes.................................................................................................................................................. 132
3.11 Memory Controller Module.................................................................................................................................... 135
3.12 JTAG........................................................................................................................................................................ 142
3.13 Live Firmware Update............................................................................................................................................ 142
3.14 System Control Register Configuration Restrictions......................................................................................... 147
3.15 Software.................................................................................................................................................................. 148
3.16 System Control Registers......................................................................................................................................155

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3.1 Introduction
System-level configuration is controlled by a group of submodules that are collectively referred to as the system
control module. The system control module provides the following capabilities:
• System-level resets, including power-on and brownout resets
• Clock source selection and PLL configuration
• Missing clock detection
• Clock-gating low-power modes
• Peripheral interrupt handling
• Non-maskable interrupts for certain fault conditions
• Three 32-bit timers
• Windowed watchdog timer, which can generate an interrupt or a reset
• RAM initialization, write protection, and mastership control
• Flash memory ECC, wait state, and cache configuration
• Dual-zone code security module

3.1.1 SYSCTL Related Collateral

Foundational Materials
• C2000 MCU JTAG Connectivity Debug Application Report

Getting Started Materials

• C28x Interrupt Nesting
• Debugging JTAG
• Enhancing Device Security by Using JTAGLOCK Feature Application Report
• XDS Target Connection Guide

Expert Materials
• C2000 CPU Memory Built-In Self-Test Application Report
• C2000 Memory Power-On Self-Test (M-POST) Application Report
• Live Firmware Update With Device Reset on C2000 MCUs Application Report
• Live Firmware Update Without Device Reset on C2000 MCUs Application Report
• Programming of External Nonvolatile Memory Using SDFlash for TMS320C28x Devices Application Report
• Software Phased-Locked Loop (PLL) Design Using C2000 Microcontrollers Application Report
3.1.2 LOCK Protection on System Configuration Registers
Several system configuration registers are protected from spurious CPU writes by “LOCK” registers. Once these
associated LOCK register bits are set, the respective locked registers can no longer be modified by software.
See the register descriptions for details.
3.1.3 EALLOW Protection
Some registers in the system are protected from spurious CPU writes by the EALLOW protection mechanism.
This uses the special CPU instructions EALLOW and EDIS to enable and disable access to protected registers.
The current protection state is given by the EALLOW bit in the CPU ST1 register, as shown in Table 3-1.
Register protection is enabled by default at startup. While protected, all writes to protected registers by the CPU
are ignored. Only CPU reads, JTAG reads, and JTAG writes are allowed. If protection is disabled by executing
the EALLOW instruction, the CPU is allowed to write freely to protected registers. After modifying registers, the
registers can once again be protected by executing the EDIS instruction to clear the EALLOW bit.
Writes to the clock configuration and peripheral clock enable registers can be disabled until the next reset by
writing to special lock registers.

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Table 3-1. Access to EALLOW-Protected Registers

EALLOW Bit CPU Writes CPU Reads JTAG Writes JTAG Reads
0 Ignored Allowed(1) Allowed Allowed
1 Allowed Allowed Allowed Allowed

(1) The EALLOW bit is overridden by way of the JTAG port, allowing full access of protected registers during debug from the Code
Composer Studio™ IDE interface.

3.2 Power Management

The TMS320F28003x MCU supports both internal and external VREG selectable using the VREGENZ pin to
supply the 1.2v rail. However, not all packages support the external VREG option. For packages that do not
support external VREG, the VREGENZ pin is replaced by GPIO39. For more details, see the TMS320F28003x
data manual.
3.3 Device Identification and Configuration Registers
The device identification registers and configuration registers provide information on the part number, product
family, revision, pin count, qualification status, and feature availability of the device.
All of the device information is part of the DEV_CFG_REGS space. The identification registers are PARTIDL,
PARTIDH, and REVID.
A 256-bit Unique ID (UID) is available in UID_REGS. The 256 bits are separated into these registers:
• UID_PSRAND0-5: 192 bits of pseudo-random data
• UID_UNIQUE: 32-bit unique data; the value in this register will be unique across all devices in the same
PARTIDH
• UID_CHECKSUM: 32-bit Fletcher checksum of UID_PSRAND0-5 and UID_UNIQUE and calculated as either
little- or big-endian during factory testing

3.4 Resets
This section explains the types and effects of the different resets on this device.
3.4.1 Reset Sources
Table 3-2 summarizes the various reset signals and their effect on the device.
Table 3-2. Reset Signals
Reset Source CPU Core Reset Peripherals JTAG / Debug IOs XRS Output
(C28x, FPU, VCU, TMU) Reset Logic Reset
POR Yes Yes Yes Hi-Z Yes
BOR Yes Yes Yes Hi-Z Yes
XRS Pin Yes Yes No Hi-Z -
WDRS Yes Yes No Hi-Z Yes
NMIWDRS Yes Yes No Hi-Z Yes
SYSRS (Debugger Reset) Yes Yes No Hi-Z No
SCCRESET Yes Yes No Hi-Z No
SIMRESET. XRS Yes Yes No Hi-Z Yes
SIMRESET. CPU1RS Yes Yes No Hi-Z No
HWBISTRS Yes No No No No

The resets can be divided into two groups:

• Chip-level resets (XRS, POR, BOR, WDRS, SIMRESET. XRS and NMIWDRS), which reset all or almost all
of the device.
• System resets (SYSRS, SIMRESET. CPU1RS and SCCRESET), which reset a large subset of the device but
maintain some system-level configuration.

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• Special resets (HWBISTRS and TRST), which enable specific device functions.
After a reset, the reset cause register (RESC) is updated with the reset cause. The bits in this register maintain
their state across multiple resets. They can only be cleared by a power-on reset (POR) or by writing ones to the
RESCCLR register. Some are cleared by the boot ROM as part of its start-up routines.
Many peripheral modules have individual resets accessible through the SOFTPRESx registers. For information
about a module's reset state, refer to the chapter for that module.
After any reset, the CPU begins execution from address 0x3FFFC0 (the reset vector), which is in the boot ROM.
After running the boot ROM code, the CPU will typically branch to the start of the Flash memory at address
0x80000. For more information on controlling the boot process, see ROM Code and Peripheral Booting.

Note
After a POR, the boot ROMs will clear the M0/M1, LSx, GSx, and message RAMs to ensure that they
contain valid ECC.

3.4.2 External Reset (XRS)

The external reset (XRS) is the main chip-level reset for the device. It resets the CPU, all peripherals and I/O pin
configurations, and most of the system control registers. There is a dedicated open-drain pin for XRS. This pin
may be used to drive reset pins for other ICs in the application, and may itself be driven by an external source.
The XRS is driven internally during watchdog, NMI, and power-on resets.
The XRSn bit in the RESC register will be set whenever XRS is driven low for any reason. This bit is then
cleared by the boot ROM.
3.4.3 Simulate External Reset (SIMRESET. XRS)
In some cases, a user may need to simulate an external reset (XRS) in software. This can be done by setting
XRSn bit to '1' in SIMRESET register through software. This toggles the XRS pin hence resets the full device
(just like an external reset).
After this reset, SIMRESET_XRSn and XRSn bits in the RESC register will be set. Software can read these bits
to know the cause of reset and clear the status by writing '1' into corresponding bits in the RESCCLR register.
3.4.4 Power-On Reset (POR)
The power-on reset (POR) circuit creates a clean reset throughout the device during power-up, suppressing
glitches on the GPIOs. The XRS pin is held low for the duration of the POR. In most applications, XRS is held
low long enough to reset other system ICs, but some applications may require a longer pulse. In these cases,
the XRS pin can be driven low externally to provide the correct reset duration. A POR resets everything that
XRS does, along with a few other registers – the reset cause register (RESC), the NMI shadow flag register
(NMISHDFLG), and the X1 clock counter register (X1CNT). A POR also resets the debug logic used by the
JTAG port.
After a POR, the POR and XRSn bits in RESC are set. These bits are then cleared by the boot ROM.
3.4.5 Brown-Out-Reset (BOR)
The brown-out-reset (BOR) is an internal supply voltage supervisor (SVS) circuit which monitors the VDDIO
supply for glitches or supply interruptions. If the VDDIO supply voltage drops below operational voltage range,
this circuit forces the XRSn pin low until the fault is removed and the supply voltage returns to the minimum
operational voltage. A BOR resets everything in the same manner as a POR reset.
The BOR circuit is enabled by default and therefore will always be active during power up or after any type of
reset. To disable the BOR circuit, set the BORLVMONDIS bit in the VMONCTL register.

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3.4.6 Debugger Reset (SYSRS)

During development, it is sometimes necessary to reset the CPU and its peripherals without disconnecting the
debugger or disrupting the system-level configuration. To facilitate this, the CPU has its own subsystem reset,
which can be triggered by a debugger using Code Composer Studio™ IDE. This reset (SYSRS) resets the CPU,
its peripherals, many system control registers (including its clock gating and LPM configuration), and all I/O pin
configurations.
The SYSRS does not reset the ICEPick debug module, the device capability registers, the clock source and PLL
configurations, the missing clock detection state, the PIE vector fetch error handler address, the NMI flags, the
analog trims, or anything reset only by a POR (see Section 3.4.4).
3.4.7 Simulate CPU Reset (SIMRESET. CPU1RS)
In some cases, a user may need to simulate the CPU reset (SYSRS) in software. This can be done by setting
CPU1RSn bit to '1' in the SIMRESET register through software. This toggles CPU1.SYSRS signals hence
resetting the CPU (just like the debugger reset).
After this reset, SIMRESET_CPU1RSn bit in the RESC register will be set. Software can read this bit to know
the cause of reset and clear the status by writing '1' into corresponding bit in RESCCLR register.
3.4.8 Watchdog Reset (WDRS)
The device has a watchdog timer that can optionally trigger a reset if it is not serviced by the CPU within a
user-specified amount of time. This watchdog reset (WDRS) produces an XRS that lasts for 512 INTOSC1
cycles.
After a watchdog reset, the WDRSn and XRSn bits in RESC are set.
3.4.9 Hardware BIST Reset (HWBISTRS)
The Hardware Built-In Self-Test (HWBIST) module tests the functionality of the CPU. At the end of the test,
it resets the CPU to return it to a working state. This reset (HWBISTRS) only affects the CPU itself. The
peripherals and system control remain as previously configured. The CPU state is restored in software as part of
a special boot ROM flow. For more information on the HWBIST flow, contact your local TI representative.
After a HWBIST reset, the HWBISTn bit in RESC is set. Software can read this bit to know the cause of reset
and clear the status by writing '1' into corresponding bit in RESCCLR register.
3.4.10 NMI Watchdog Reset (NMIWDRS)
The device has a non-maskable interrupt (NMI) module that detects hardware errors in the system. The NMI
module has a watchdog timer that triggers a reset if the CPU does not respond to an error within a user-specified
amount of time. This NMI watchdog reset (NMIWDRS) produces an XRS that lasts for 512 INTOSC1 cycles.
After an NMI watchdog reset, the NMIWDRSn and XRSn bits in RESC are set.
3.4.11 DCSM Safe Code Copy Reset (SCCRESET)
The device has a dual-zone code security module (DCSM) that blocks read access to certain areas of the
Flash memory. To facilitate CRC checks and copying of CLA code, TI provides ROM functions to securely
access those memory areas. To prevent security breaches, interrupts must be disabled before calling these
functions. If a vector fetch occurs in a safe copy or CRC function, the DCSM triggers a reset. This security reset
(SCCRESET) is similar to a SYSRS. However, the security reset also resets the debug logic to deny access to a
potential attacker.
After a security reset, the SCCRESETn bit in RESC is set.

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3.5 Peripheral Interrupts

This section explains the peripheral interrupt handling on the device. Non-maskable interrupts are covered in
Section 3.6. Software interrupts and emulation interrupts are not covered in this document. For information on
those, see the TMS320C28x CPU and Instruction Set Reference Guide.
3.5.1 Interrupt Concepts
An interrupt is a signal that causes the CPU to pause its current execution and branch to a different piece of
code known as an interrupt service routine (ISR). This is a useful mechanism for handling peripheral events,
and involves less CPU overhead or program complexity than register polling. However, because interrupts are
asynchronous to the program flow, care must be taken to avoid conflicts over resources that are accessed both
in interrupts and in the main program code.
Interrupts propagate to the CPU through a series of flag and enable registers. The flag registers store the
interrupt until it is processed. The enable registers block the propagation of the interrupt. When an interrupt
signal reaches the CPU, the CPU fetches the appropriate ISR address from a list called the vector table.
3.5.2 Interrupt Architecture
The C28x CPU has fourteen peripheral interrupt lines. Two of them (INT13 and INT14) are connected directly
to CPU timers 1 and 2, respectively. The remaining twelve are connected to peripheral interrupt signals through
the enhanced Peripheral Interrupt Expansion module (ePIE, or PIE as a shortened version). The PIE multiplexes
up to sixteen peripheral interrupts into each CPU interrupt line. It also expands the vector table to allow each
interrupt to have its own ISR. This allows the CPU to support a large number of peripherals.
An interrupt path is divided into three stages – the peripheral, the PIE, and the CPU. Each stage has its
own enable and flag registers. This system allows the CPU to handle one interrupt while others are pending,
implement and prioritize nested interrupts in software, and disable interrupts during certain critical tasks.
Figure 3-1 shows the interrupt architecture for this device.
TINT0
TIMER0

LPM Logic LPMINT WAKEINT

WDINT NMI module NMI
WD
ERAD RTOSINT
INPUTXBAR4 XINT1 Control CPU
GPIO0 INPUTXBAR5 XINT2 Control ePIE INT1
Input
to INPUTXBAR6 XINT3 Control to
X-BAR
GPIOx INPUTXBAR13 XINT4 Control INT12
INPUTXBAR14 XINT5 Control

TIMER1 INT13

Peripherals TIMER2 INT14

See ePIE Table

Figure 3-1. Device Interrupt Architecture

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3.5.2.1 Peripheral Stage

Each peripheral has its own unique interrupt configuration, which is described in that peripheral's chapter. Some
peripherals allow multiple events to trigger the same interrupt signal. For example, a communications peripheral
might use the same interrupt to indicate that data has been received or that there has been a transmission error.
The cause of the interrupt can be determined by reading the peripheral's status register. Often, the bits in the
status register must be cleared manually before another interrupt will be generated.
3.5.2.2 PIE Stage
The PIE provides individual flag and enable register bits for each of the peripheral interrupt signals, which are
sometimes called PIE channels. These channels are grouped according to their associated CPU interrupt. Each
PIE group has one 16-bit enable register (PIEIERx), one 16-bit flag register (PIEIFRx), and one bit in the PIE
acknowledge register (PIEACK). The PIEACK register bit acts as a common interrupt mask for the entire PIE
group.
When the CPU receives an interrupt, it fetches the address of the ISR from the PIE. The PIE returns the vector
for the lowest-numbered channel in the group that is both flagged and enabled. This gives lower-numbered
interrupts a higher priority when multiple interrupts are pending.
If no interrupt is both flagged and enabled, the PIE returns the vector for channel 1. This condition will not
happen unless software changes the state of the PIE while an interrupt is propagating. Section 3.5.4 contains
procedures for safely modifying the PIE configuration once interrupts have been enabled.
3.5.2.3 CPU Stage
Like the PIE, the CPU provides flag and enable register bits for each of its interrupts. There is one enable
register (IER) and one flag register (IFR), both of which are internal CPU registers. There is also a global
interrupt mask, which is controlled by the INTM bit in the ST1 register. This mask can be set and cleared using
the CPU's SETC and CLRC instructions. In C code, C2000Ware's DINT and EINT macros can be used for this
purpose.
Writes to IER and INTM are atomic operations. In particular, if INTM is set, the next instruction in the pipeline will
run with interrupts disabled. No software delays are needed.
3.5.3 Interrupt Entry Sequence
Figure 3-2 shows how peripheral interrupts propagate to the CPU.

Figure 3-2. Interrupt Propagation Path

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When a peripheral generates an interrupt (on PIE group x, channel y), it triggers the following sequence of
events:
1. The interrupt is latched in PIEIFRx.y.
2. If PIEIERx.y is set, the interrupt propagates.
3. If PIEACK.x is clear, the interrupt propagates and PIEACK.x is set.
4. The interrupt is latched in IFR.x.
5. If IER.x is set, the interrupt propagates.
6. If INTM is clear, the CPU receives the interrupt.
7. Any instructions in the D2 or later stage of the pipeline are run to completion. Instructions in earlier stages
are flushed.
8. The CPU saves its context on the stack.
9. IFR.x and IER.x are cleared. INTM is set. EALLOW is cleared.
10. The CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared.
11. The CPU branches to the ISR.
The interrupt latency is the time between PIEIFRx.y latching the interrupt and the first ISR instruction entering
the execution stage of the CPU pipeline. The minimum interrupt latency is 14 SYSCLK cycles. Wait states on
the ISR or stack memories will add to the latency. External interrupts add a minimum of two SYSCLK cycles
for GPIO synchronization plus extra time for input qualification (if used). Loops created using the C28x RPT
instruction cannot be interrupted.
3.5.4 Configuring and Using Interrupts
At power-up, no interrupts are enabled by default. The PIEIER and IER registers are cleared and INTM is set.
The application code is responsible for configuring and enabling all peripheral interrupts.
3.5.4.1 Enabling Interrupts
To enable a peripheral interrupt, perform the following steps:
1. Disable interrupts globally (DINT or SETC INTM).
2. Enable the PIE by setting the ENPIE bit of the PIECTRL register.
3. Write the ISR vector for each interrupt to the appropriate location in the PIE vector table, which can be found
in Table 3-3. Note that the vector table is EALLOW-protected.
4. Set the appropriate PIEIERx bit for each interrupt. The PIE group and channel assignments can be found in
Table 3-3.
5. Set the CPU IER bit for any PIE group containing enabled interrupts.
6. Enable the interrupt in the peripheral.
7. Enable interrupts globally (EINT or CLRC INTM).
Step 4 does not apply to the Timer1 and Timer2 interrupts, which connect directly to the CPU.
3.5.4.2 Handling Interrupts
ISRs are similar to normal functions, but must do the following:
1. Save and restore the state of certain CPU registers (if used).
2. Clear the PIEACK bit for the interrupt group.
3. Return using the IRET instruction.
Requirements 1 and 3 are handled automatically by the TMS320C28x C compiler if the function is defined
using the __interrupt keyword. For information on this keyword, see the Keywords section of the TMS320C28x
Optimizing C/C++ Compiler v6.2.4 User's Guide. For information on writing assembly code to handle interrupts,
see the Standard Operation for Maskable Interrupts section of the TMS320C28x CPU and Instruction Set
Reference Guide.
The PIEACK bit for the interrupt group must be cleared manually in user code. This is normally done at the end
of the ISR. If the PIEACK bit is not cleared, the CPU will not receive any further interrupts from that group. This
does not apply to the Timer1 and Timer2 interrupts, which do not go through the PIE.

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3.5.4.3 Disabling Interrupts

To disable all interrupts, set the CPU's global interrupt mask via DINT or SETC INTM. It is not necessary to add
NOPs after setting INTM or modifying IER – the next instruction will execute with interrupts disabled.
Individual interrupts can be disabled using the PIEIERx registers, but care must be taken to avoid race
conditions. If an interrupt signal is already propagating when the PIEIER write completes, it may reach the
CPU and trigger a spurious interrupt condition. To avoid this, use the following procedure:
1. Disable interrupts globally (DINT or SETC INTM).
2. Clear the PIEIER bit for the interrupt.
3. Wait 5 cycles to make sure that any propagating interrupt has reached the CPU IFR register.
4. Clear the CPU IFR bit for the interrupt's PIE group.
5. Clear the PIEACK bit for the interrupt's PIE group.
6. Enable interrupts globally (EINT or CLRC INTM).
Interrupt groups can be disabled using the CPU IER register. This cannot cause a race condition, so no special
procedure is needed.
PIEIFR bits must never be cleared in software since the read/modify/write operation may cause incoming
interrupts to be lost. The only safe way to clear a PIEIFR bit is to have the CPU take the interrupt. The following
procedure can be used to bypass the normal ISR:
1. Disable interrupts globally (DINT or SETC INTM).
2. Modify the PIE vector table to map the PIEIFR bit's interrupt vector to an empty ISR. This ISR will only
contain a return from interrupt instruction (IRET).
3. Disable the interrupt in the peripheral registers.
4. Enable interrupts globally (EINT or CLRC INTM).
5. Wait for the pending interrupt to be serviced by the empty ISR.
6. Disable interrupts globally.
7. Modify the PIE vector table to map the interrupt vector back to its original ISR.
8. Clear the PIEACK bit for the interrupt's PIE group.
9. Enable interrupts globally.
3.5.4.4 Nesting Interrupts
By default, interrupts do not nest. It is possible to nest and prioritize interrupts via software control of the
IER and PIEIERx registers. Example code can be found in C2000Ware and documentation is available at
software-dl.ti.com/C2000/docs/c28x_interrupt_nesting/html/index.html.
3.5.4.5 Vector Address Validity Check
There are two copies of the ePIE vector table. The primary vector table is located at addresses 0xD00 - 0xEFF.
The redundant vector table is located at addresses 0x01000D00 - 0x01000EFF. A write to a primary vector
address writes to both tables, while a write to a redundant vector address only writes to the redundant table.
Both tables are read independently.
During a vector fetch, the ePIE performs a hardware comparison of both vector table outputs. If there is a
mismatch between the two vector tables, the CPU branches to the address in the PIEVERRADDR register and
the ePIE sends trip signals to the PWMs. If the PIEVERRADDR register value has not been set, the default boot
ROM handler at address 0x003FFFBE is used.

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3.5.5 PIE Channel Mapping

Table 3-3 shows the PIE group and channel assignments for each peripheral interrupt. Each row is a group, and each column is a channel within that
group. When multiple interrupts are pending, the lowest-numbered channel is the lowest-numbered group is serviced first. Thus, the interrupts at the top
of the table have the highest priority, and the interrupts at the bottom have the lowest priority.
Table 3-3. Pie Channel Mapping
INTx.1 INTx.2 INTx.3 INTx.4 INTx.5 INTx.6 INTx.7 INTx.8 INTx.9 INTx.10 INTx.11 INTx.12 INTx.13 INTx.14 INTx.15 INTx.16
INT1.y ADCA1 ADCB1 ADCC1 XINT1 XINT2 - TIMER0 WAKE / - SYS_ERR - - - - - -
WDOG
INT2.y EPWM1_ EPWM2_ EPWM3_ EPWM4_ EPWM5_ EPWM6_ EPWM7_ EPWM8_ - - - - - - - -
TZ TZ TZ TZ TZ TZ TZ TZ
INT3.y EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 EPWM7 EPWM8 - - - - - - - -
INT4.y ECAP1 ECAP2 ECAP3 - - - - - - - ECAP3INT2 - - - - -
INT5.y EQEP1 EQEP2 - - CLB1 CLB2 CLB3 CLB4 SDFM1 SDFM2 - - SDFM1DR1 SDFM1DR2 SDFM1DR3 SDFM1DR4
INT6.y SPIA_RX SPIA_TX SPIB_RX SPIB_TX - - - - - - - - SDFM2DR1 SDFM2DR2 SDFM2DR3 SDFM2DR4
INT7.y DMA_ DMA_ DMA_ DMA_ DMA_ DMA_ - - - - FSITX_ FSITX_ FSIRX_ FSIRX_ - DCC0
CH1 CH2 CH3 CH4 CH5 CH6 INT1 INT2 INT1 INT2
INT8.y I2CA I2CA_ I2CB I2CB_ - - - - LINA_0 LINA_1 LINB_0 LINB_1 PMBUSA - - DCC1
FIFO FIFO
INT9.y SCIA_RX SCIA_TX SCIB_RX SCIB_TX DCANA_0 DCANA_1 - - MCAN_0 MCAN_1 MCAN_ECC MCAN_ BGCRC_ - - HICA
WAKE CPU
INT10.y ADCA_ ADCA2 ADCA3 ADCA4 ADCB_EVT ADCB2 ADCB3 ADCB4 ADCC_ ADCC2 ADCC3 ADCC4 - - - -
EVT EVT
INT11.y CLA1_1 CLA1_2 CLA1_3 CLA1_4 CLA1_5 CLA1_6 CLA1_7 CLA1_8 - - - - - - - -
INT12.y XINT3 XINT4 XINT5 MPOST FMC - FPU_OVER FPU_ - RAM_ FLASH_ RAM_ACC_ AES_SIN_ BGCRC_ CLA_OVER CLA_
FLOW UNDER CORR_ CORR_ VIOLATION TREQ CLA1 FLOW UNDER
FLOW ERR ERR FLOW

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3.5.5.1 PIE Interrupt Priority

3.5.5.1.1 Channel Priority
For every PIE group, the low number channels in the group have the highest priority. For instance in PIE group
1, channel 1.1 has priority over channel 1.3. If those two enabled interrupts occurred simultaneously, channel
1.1 will be serviced first with channel 1.3 left pending. Once the ISR for channel 1.1 completes and provided
there are no other enabled and pending interrupts for PIE group 1, channel 1.3 will be serviced. However, for the
CPU to service any more interrupts from a PIE group, PIEACK for the group must be cleared. For this specific
example, in order for channel 1.3 to be serviced, channel 1.1’s ISR has to clear PIEACK for group 1.
The following example describes an alternative scenario: channel 1.1 is currently being serviced by the CPU,
channel 1.3 is pending and before channel 1.1’s ISR completes, channel 1.2 which is enabled also comes in.
Since channel 1.2 has a higher priority than channel 1.3, the CPU will service channel 1.2 and channel 1.3 will
still be left pending. Using the steps from the Interrupt Entry Sequence (Section 3.5.3), channel 1.2 interrupt can
happen as late as step 10 (The CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared) and it will still be
serviced ahead of channel 1.3.
3.5.5.1.2 Group Priority
Generally, the lowest channel in the lowest PIE group has the highest priority. An example of this is channels 1.1
and 2.1. Those two channels have the highest priority in their respective groups. If the interrupts for those two
enabled channels happened simultaneously and provided there are no other enabled and pending interrupts,
channel 1.1 will be serviced first by the CPU with channel 2.1 left pending.
However, there are cases where channel priority supersedes group priority. This special case happens
depending on which step the CPU is currently at in the Interrupt Entry Sequence (Section 3.5.3).
The following illustrates an example of this special case.
The CPU is about to service channel 2.3 and is currently going through the steps in the Interrupt Entry Sequence
(Section 3.5.3).
1. As the CPU reaches step 10 (The CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared), two
enabled interrupts: channel 1.1 and channel 2.1 come in.
2. Due to channel priority, channel 2.1 will be serviced ahead of channel 2.3. However, group priority dictates
that channel 1.1 be serviced ahead of channels 2.1 and 2.3.
3. Channel priority supersedes here and channel 2.1 will be serviced ahead of 1.1 and 2.3.
4. After channel 2.1 completes, channel 1.1 is serviced followed by channel 2.3.
Group priority is only guaranteed if no interrupts are currently being serviced, that is, the Interrupt Entry
Sequence (Section 3.5.3) is not executing.

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3.5.6 Vector Tables

Table 3-4 shows the CPU interrupt vector table. The vectors for INT1 – INT12 are not used in this device. The
reset vector is fetched from the boot ROM instead of from this table. All vectors are EALLOW-protected.
Table 3-5 shows the pie vector table.
Table 3-4. CPU Interrupt Vectors
Name Vector ID Address Size (x16) Description Core ePIE Group
Priority Priority
Reset 0 0x0000 0D00 2 Reset is always fetched from location 1 (Highest) -
0x003F_FFC0 in Boot ROM
INT1 1 0x0000 0D02 2 Not used. See PIE Group 1 5 -
INT2 2 0x0000 0D04 2 Not used. See PIE Group 2 6 -
INT3 3 0x0000 0D06 2 Not used. See PIE Group 3 7 -
INT4 4 0x0000 0D08 2 Not used. See PIE Group 4 8 -
INT5 5 0x0000 0D0A 2 Not used. See PIE Group 5 9 -
INT6 6 0x0000 0D0C 2 Not used. See PIE Group 6 10 -
INT7 7 0x0000 0D0E 2 Not used. See PIE Group 7 11 -
INT8 8 0x0000 0D10 2 Not used. See PIE Group 8 12 -
INT9 9 0x0000 0D12 2 Not used. See PIE Group 9 13 -
INT10 10 0x0000 0D14 2 Not used. See PIE Group 10 14 -
INT11 11 0x0000 0D16 2 Not used. See PIE Group 11 15 -
INT12 12 0x0000 0D18 2 Not used. See PIE Group 12 16 -
INT13 13 0x0000 0D1A 2 CPU TIMER1 Interrupt 17 -
INT14 14 0x0000 0D1C 2 CPU TIMER2 Interrupt 18 -
DATALOG 15 0x0000 0D1E 2 CPU Data Logging Interrupt 19 (lowest) -
RTOSINT 16 0x0000 0D20 2 CPU Real-Time OS Interrupt 4 -
RSVD 17 0x0000 0D22 2 Reserved 2 -
NMI 18 0x0000 0D24 2 Non-Maskable Interrupt 3 -
ILLEGAL 19 0x0000 0D26 2 Illegal Instruction (ITRAP) - -
USER 1 20 0x0000 0D28 2 User-Defined Trap - -
USER 2 21 0x0000 0D2A 2 User-Defined Trap - -
USER 3 22 0x0000 0D2C 2 User-Defined Trap - -
USER 4 23 0x0000 0D2E 2 User-Defined Trap - -
USER 5 24 0x0000 0D30 2 User-Defined Trap - -
USER 6 25 0x0000 0D32 2 User-Defined Trap - -
USER 7 26 0x0000 0D34 2 User-Defined Trap - -
USER 8 27 0x0000 0D36 2 User-Defined Trap - -
USER 9 28 0x0000 0D38 2 User-Defined Trap - -
USER 10 29 0x0000 0D3A 2 User-Defined Trap - -
USER 11 30 0x0000 0D3C 2 User-Defined Trap - -
USER 12 31 0x0000 0D3E 2 User-Defined Trap - -

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Table 3-5. PIE Interrupt Vectors

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
Priority
PIE Group 1 Vectors - Muxed into CPU INT1
INT1.1 32 0x0000 0D40 2 ADCA1 interrupt 5 1 (Highest)
INT1.2 33 0x0000 0D42 2 ADCB1 interrupt 5 2
INT1.3 34 0x0000 0D44 2 ADCC1 interrupt 5 3
INT1.4 35 0x0000 0D46 2 XINT1 interrupt 5 4
INT1.5 36 0x0000 0D48 2 XINT2 interrupt 5 5
INT1.6 37 0x0000 0D4A 2 Reserved 5 6
INT1.7 38 0x0000 0D4C 2 TIMER0 interrupt 5 7
INT1.8 39 0x0000 0D4E 2 WAKE interrupt 5 8
INT1.9 128 0x0000 0E00 2 Reserved 5 9
INT1.10 129 0x0000 0E02 2 SYS_ERR interrupt 5 10
INT1.11 130 0x0000 0E04 2 Reserved 5 11
INT1.12 131 0x0000 0E06 2 Reserved 5 12
INT1.13 132 0x0000 0E08 2 Reserved 5 13
INT1.14 133 0x0000 0E0A 2 Reserved 5 14
INT1.15 134 0x0000 0E0C 2 Reserved 5 15
INT1.16 135 0x0000 0E0E 2 Reserved 5 16 (Lowest)
PIE Group 2 Vectors - Muxed into CPU INT2
INT2.1 40 0x0000 0D50 2 EPWM1 trip zone 6 1 (Highest)
interrupt
INT2.2 41 0x0000 0D52 2 EPWM2 trip zone 6 2
interrupt
INT2.3 42 0x0000 0D54 2 EPWM3 trip zone 6 3
interrupt
INT2.4 43 0x0000 0D56 2 EPWM4 trip zone 6 4
interrupt
INT2.5 44 0x0000 0D58 2 EPWM5 trip zone 6 5
interrupt
INT2.6 45 0x0000 0D5A 2 EPWM6 trip zone 6 6
interrupt
INT2.7 46 0x0000 0D5C 2 EPWM7 trip zone 6 7
interrupt
INT2.8 47 0x0000 0D5E 2 EPWM8 trip zone 6 8
interrupt
INT2.9 136 0x0000 0E10 2 Reserved 6 9
INT2.10 137 0x0000 0E12 2 Reserved 6 10
INT2.11 138 0x0000 0E14 2 Reserved 6 11
INT2.12 139 0x0000 0E16 2 Reserved 6 12
INT2.13 140 0x0000 0E18 2 Reserved 6 13
INT2.14 141 0x0000 0E1A 2 Reserved 6 14
INT2.15 142 0x0000 0E1C 2 Reserved 6 15
INT2.16 143 0x0000 0E1E 2 Reserved 6 16 (Lowest)
PIE Group 3 Vectors - Muxed into CPU INT3
INT3.1 48 0x0000 0D60 2 EPWM1 interrupt 7 1 (Highest)
INT3.2 49 0x0000 0D62 2 EPWM2 interrupt 7 2
INT3.3 50 0x0000 0D64 2 EPWM3 interrupt 7 3
INT3.4 51 0x0000 0D66 2 EPWM4 interrupt 7 4

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Table 3-5. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
Priority
INT3.5 52 0x0000 0D68 2 EPWM5 interrupt 7 5
INT3.6 53 0x0000 0D6A 2 EPWM6 interrupt 7 6
INT3.7 54 0x0000 0D6C 2 EPWM7 interrupt 7 7
INT3.8 55 0x0000 0D6E 2 EPWM8 interrupt 7 8
INT3.9 144 0x0000 0E20 2 Reserved 7 9
INT3.10 145 0x0000 0E22 2 Reserved 7 10
INT3.11 146 0x0000 0E24 2 Reserved 7 11
INT3.12 147 0x0000 0E26 2 Reserved 7 12
INT3.13 148 0x0000 0E28 2 Reserved 7 13
INT3.14 149 0x0000 0E2A 2 Reserved 7 14
INT3.15 150 0x0000 0E2C 2 Reserved 7 15
INT3.16 151 0x0000 0E2E 2 Reserved 7 16 (Lowest)
PIE Group 4 Vectors - Muxed into CPU INT4
INT4.1 56 0x0000 0D70 2 ECAP1 interrupt 8 1 (Highest)
INT4.2 57 0x0000 0D72 2 ECAP2 interrupt 8 2
INT4.3 58 0x0000 0D74 2 ECAP3 interrupt 8 3
INT4.4 59 0x0000 0D76 2 Reserved 8 4
INT4.5 60 0x0000 0D78 2 Reserved 8 5
INT4.6 61 0x0000 0D7A 2 Reserved 8 6
INT4.7 62 0x0000 0D7C 2 Reserved 8 7
INT4.8 63 0x0000 0D7E 2 Reserved 8 8
INT4.9 152 0x0000 0E30 2 Reserved 8 9
INT4.10 153 0x0000 0E32 2 Reserved 8 10
INT4.11 154 0x0000 0E34 2 ECAP3 interrupt 2 8 11
INT4.12 155 0x0000 0E36 2 Reserved 8 12
INT4.13 156 0x0000 0E38 2 Reserved 8 13
INT4.14 157 0x0000 0E3A 2 Reserved 8 14
INT4.15 158 0x0000 0E3C 2 Reserved 8 15
INT4.16 159 0x0000 0E3E 2 Reserved 8 16 (Lowest)
PIE Group 5 Vectors - Muxed into CPU INT5
INT5.1 64 0x0000 0D80 2 EQEP1 interrupt 9 1 (Highest)
INT5.2 65 0x0000 0D82 2 EQEP2 interrupt 9 2
INT5.3 66 0x0000 0D84 2 Reserved 9 3
INT5.4 67 0x0000 0D86 2 Reserved 9 4
INT5.5 68 0x0000 0D88 2 CLB1 interrupt 9 5
INT5.6 69 0x0000 0D8A 2 CLB2 interrupt 9 6
INT5.7 70 0x0000 0D8C 2 CLB3 interrupt 9 7
INT5.8 71 0x0000 0D8E 2 CLB4 interrupt 9 8
INT5.9 160 0x0000 0E40 2 SDFM1 interrupt 9 9
INT5.10 161 0x0000 0E42 2 SDFM2 interrupt 9 10
INT5.11 162 0x0000 0E44 2 Reserved 9 11
INT5.12 163 0x0000 0E46 2 Reserved 9 12
INT5.13 164 0x0000 0E48 2 SDFM1DR1 interrupt 9 13
INT5.14 165 0x0000 0E4A 2 SDFM1DR2 interrupt 9 14

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Table 3-5. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
Priority
INT5.15 166 0x0000 0E4C 2 SDFM1DR3 interrupt 9 15
INT5.16 167 0x0000 0E4E 2 SDFM1DR4 interrupt 9 16 (Lowest)
PIE Group 6 Vectors - Muxed into CPU INT6
INT6.1 72 0x0000 0D90 2 SPIA_RX interrupt 10 1 (Highest)
INT6.2 73 0x0000 0D92 2 SPIA_TX interrupt 10 2
INT6.3 74 0x0000 0D94 2 SPIB_RX interrupt 10 3
INT6.4 75 0x0000 0D96 2 SPIB_TX interrupt 10 4
INT6.5 76 0x0000 0D98 2 Reserved 10 5
INT6.6 77 0x0000 0D9A 2 Reserved 10 6
INT6.7 78 0x0000 0D9C 2 Reserved 10 7
INT6.8 79 0x0000 0D9E 2 Reserved 10 8
INT6.9 168 0x0000 0E50 2 Reserved 10 9
INT6.10 169 0x0000 0E52 2 Reserved 10 10
INT6.11 170 0x0000 0E54 2 Reserved 10 11
INT6.12 171 0x0000 0E56 2 Reserved 10 12
INT6.13 172 0x0000 0E58 2 SDFM2DR1 interrupt 10 13
INT6.14 173 0x0000 0E5A 2 SDFM2DR2 interrupt 10 14
INT6.15 174 0x0000 0E5C 2 SDFM2DR3 interrupt 10 15
INT6.16 175 0x0000 0E5E 2 SDFM2DR4 interrupt 10 16 (Lowest)
PIE Group 7 Vectors - Muxed into CPU INT7
INT7.1 80 0x0000 0DA0 2 DMA_CH1 interrupt 11 1 (Highest)
INT7.2 81 0x0000 0DA2 2 DMA_CH2 interrupt 11 2
INT7.3 82 0x0000 0DA4 2 DMA_CH3 interrupt 11 3
INT7.4 83 0x0000 0DA6 2 DMA_CH4 interrupt 11 4
INT7.5 84 0x0000 0DA8 2 DMA_CH5 interrupt 11 5
INT7.6 85 0x0000 0DAA 2 DMA_CH6 interrupt 11 6
INT7.7 86 0x0000 0DAC 2 Reserved 11 7
INT7.8 87 0x0000 0DAE 2 Reserved 11 8
INT7.9 176 0x0000 0E60 2 Reserved 11 9
INT7.10 177 0x0000 0E62 2 Reserved 11 10
INT7.11 178 0x0000 0E64 2 FSITX_INT1 11 11
INT7.12 179 0x0000 0E66 2 FSITX_INT2 11 12
INT7.13 180 0x0000 0E68 2 FSIRX_INT1 11 13
INT7.14 181 0x0000 0E6A 2 FSIRX_INT2 11 14
INT7.15 182 0x0000 0E6C 2 Reserved 11 15
INT7.16 183 0x0000 0E6E 2 DCC0 interrupt 11 16 (Lowest)
PIE Group 8 Vectors - Muxed into CPU INT8
INT8.1 88 0x0000 0DB0 2 I2CA interrupt 12 1 (Highest)
INT8.2 89 0x0000 0DB2 2 I2CA FIFO interrupt 12 2
INT8.3 90 0x0000 0DB4 2 I2CB interrupt 12 3
INT8.4 91 0x0000 0DB6 2 I2CB FIFO interrupt 12 4
INT8.5 92 0x0000 0DB8 2 Reserved 12 5
INT8.6 93 0x0000 0DBA 2 Reserved 12 6
INT8.7 94 0x0000 0DBC 2 Reserved 12 7

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Table 3-5. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
Priority
INT8.8 95 0x0000 0DBE 2 Reserved 12 8
INT8.9 184 0x0000 0E70 2 LINA interrupt 0 12 9
INT8.10 185 0x0000 0E72 2 LINA interrupt 1 12 10
INT8.11 186 0x0000 0E74 2 LINB interrupt 0 12 11
INT8.12 187 0x0000 0E76 2 LINB interrupt 1 12 12
INT8.13 188 0x0000 0E78 2 PMBUSA interrupt 12 13
INT8.14 189 0x0000 0E7A 2 Reserved 12 14
INT8.15 190 0x0000 0E7C 2 Reserved 12 15
INT8.16 191 0x0000 0E7E 2 DCC1 interrupt 12 16 (Lowest)
PIE Group 9 Vectors - Muxed into CPU INT9
INT9.1 96 0x0000 0DC0 2 SCIA RX interrupt 13 1 (Highest)
INT9.2 97 0x0000 0DC2 2 SCIA TX interrupt 13 2
INT9.3 98 0x0000 0DC4 2 SCIB RX interrupt 13 3
INT9.4 99 0x0000 0DC6 2 SCIB TX interrupt 13 4
INT9.5 100 0x0000 0DC8 2 DCANA interrupt 0 13 5
INT9.6 101 0x0000 0DCA 2 DCANA interrupt 1 13 6
INT9.7 102 0x0000 0DCC 2 Reserved 13 7
INT9.8 103 0x0000 0DCE 2 Reserved 13 8
INT9.9 192 0x0000 0E80 2 MCAN interrupt 0 13 9
INT9.10 193 0x0000 0E82 2 MCAN interrupt 1 13 10
INT9.11 194 0x0000 0E84 2 MCAN_ECC interrupt 13 11
INT9.12 195 0x0000 0E86 2 MCAN_WAKE interrupt 13 12
INT9.13 196 0x0000 0E88 2 BGCRC_CPU interrupt 13 13
INT9.14 197 0x0000 0E8A 2 Reserved 13 14
INT9.15 198 0x0000 0E8C 2 Reserved 13 15
INT9.16 199 0x0000 0E8E 2 HICA interrupt 13 16 (Lowest)
PIE Group 10 Vectors - Muxed into CPU INT10
INT10.1 104 0x0000 0DD0 2 ADCA event interrupt 14 1 (Highest)
INT10.2 105 0x0000 0DD2 2 ADCA2 interrupt 14 2
INT10.3 106 0x0000 0DD4 2 ADCA3 interrupt 14 3
INT10.4 107 0x0000 0DD6 2 ADCA4 interrupt 14 4
INT10.5 108 0x0000 0DD8 2 ADCB event interrupt 14 5
INT10.6 109 0x0000 0DDA 2 ADCB2 interrupt 14 6
INT10.7 110 0x0000 0DDC 2 ADCB3 interrupt 14 7
INT10.8 111 0x0000 0DDE 2 ADCB4 interrupt 14 8
INT10.9 200 0x0000 0E90 2 ADCC event interrupt 14 9
INT10.10 201 0x0000 0E92 2 ADCC2 interrupt 14 10
INT10.11 202 0x0000 0E94 2 ADCC3 interrupt 14 11
INT10.12 203 0x0000 0E96 2 ADCC4 interrupt 14 12
INT10.13 204 0x0000 0E98 2 Reserved 14 13
INT10.14 205 0x0000 0E9A 2 Reserved 14 14
INT10.15 206 0x0000 0E9C 2 Reserved 14 15
INT10.16 207 0x0000 0E9E 2 Reserved 14 16 (Lowest)

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Table 3-5. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core Priority ePIE Group
Priority
PIE Group 11 Vectors - Muxed into CPU INT11
INT11.1 112 0x0000 0DE0 2 CLA1_1 interrupt 15 1 (Highest)
INT11.2 113 0x0000 0DE2 2 CLA1_2 interrupt 15 2
INT11.3 114 0x0000 0DE4 2 CLA1_3 interrupt 15 3
INT11.4 115 0x0000 0DE6 2 CLA1_4 interrupt 15 4
INT11.5 116 0x0000 0DE8 2 CLA1_5 interrupt 15 5
INT11.6 117 0x0000 0DEA 2 CLA1_6 interrupt 15 6
INT11.7 118 0x0000 0DEC 2 CLA1_7 interrupt 15 7
INT11.8 119 0x0000 0DEE 2 CLA1_8 interrupt 15 8
INT11.9 208 0x0000 0EA0 2 Reserved 15 9
INT11.10 209 0x0000 0EA2 2 Reserved 15 10
INT11.11 210 0x0000 0EA4 2 Reserved 15 11
INT11.12 211 0x0000 0EA6 2 Reserved 15 12
INT11.13 212 0x0000 0EA8 2 Reserved 15 13
INT11.14 213 0x0000 0EAA 2 Reserved 15 14
INT11.15 214 0x0000 0EAC 2 Reserved 15 15
INT11.16 215 0x0000 0EAE 2 Reserved 15 16 (Lowest)
PIE Group 12 Vectors - Muxed into CPU INT12
INT12.1 120 0x0000 0DF0 2 XINT3 interrupt 16 1 (Highest)
INT12.2 121 0x0000 0DF2 2 XINT4 interrupt 16 2
INT12.3 122 0x0000 0DF4 2 XINT5 interrupt 16 3
INT12.4 123 0x0000 0DF6 2 MPOST interrupt 16 4
INT12.5 124 0x0000 0DF8 2 Flash Wrapper Operation 16 5
done interrupt
INT12.6 125 0x0000 0DFA 2 Reserved 16 6
INT12.7 126 0x0000 0DFC 2 FPU overflow interrupt 16 7
INT12.8 127 0x0000 0DFE 2 FPU underflow interrupt 16 8
INT12.9 216 0x0000 0EB0 2 Reserved 16 9
INT12.10 217 0x0000 0EB2 2 RAM correctable error 16 10
interrupt
INT12.11 218 0x0000 0EB4 2 Flash correctable error 16 11
interrupt
INT12.12 219 0x0000 0EB6 2 RAM access violation 16 12
interrupt
INT12.13 220 0x0000 0EB8 2 AES_SIN_TREQ 16 13
interrupt
INT12.14 221 0x0000 0EBA 2 BGCRC_CLA1 interrupt 16 14
INT12.15 222 0x0000 0EBC 2 CLA OVERFLOW 16 15
interrupt
INT12.16 223 0x0000 0EBE 2 CLA UNDERFLOW 16 16 (Lowest)
interrupt

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3.6 Exceptions and Non-Maskable Interrupts

This section describes system-level error conditions that can trigger a non-maskable interrupt (NMI). The
interrupt allows the application to respond to the error.
3.6.1 Configuring and Using NMIs
An incoming NMI sets a status bit in the NMIFLG register and starts the NMI watchdog counter. This counter
is clocked by the SYSCLK, and if it reaches the value in the NMIWDPRD register, it triggers an NMI watchdog
reset (NMIWDRS). To prevent this, the NMI handler must clear the flag bit using the NMIFLGCLR register. Once
all flag bits are clear, the NMIINT bit in the NMIFLG register may also be cleared to allow future NMIs to be
taken.
The NMI module is enabled by the boot ROM during the startup process. To respond to NMIs, an NMI handler
vector must be written to the PIE vector table.
3.6.2 Emulation Considerations
The NMI watchdog counter behaves as follows under debug conditions:
CPU Suspended When the CPU is suspended, the NMI watchdog counter is suspended.
Run-Free Mode When the CPU is placed in run-free mode, the NMI watchdog counter resumes operation as normal.
Real-Time Single-Step Mode When the CPU is in real-time single-step mode, the NMI watchdog counter is suspended. The counter
remains suspended even within real-time interrupts.
Real-Time Run-Free Mode When the CPU is in real-time run-free mode, the NMI watchdog counter operates as normal.

3.6.3 NMI Sources

There are several types of hardware errors that can trigger an NMI. Additional information about the error is
usually available from the module that detects it.
3.6.3.1 Missing Clock Detection
The missing clock detection logic monitors OSCCLK for failure. If the OSCCLK source stops, the PLL is
bypassed, OSCCLK is connected to INTOSC1, and an NMI is fired to the CPU. For more information on missing
clock detection, see Section 3.7.12.1.
3.6.3.2 RAM Uncorrectable Error
A double-bit ECC data error, or single-bit ECC address error in a RAM read will trigger an NMI. This applies
to CPU and DMA reads. Single-bit ECC data errors do not trigger an NMI, but can optionally trigger a normal
peripheral interrupt. For more information on RAM error detection, see Section 3.11.8.
3.6.3.3 Flash Uncorrectable ECC Error
A double-bit ECC data error or single-bit ECC address error in a Flash read triggers an NMI. Single-bit ECC data
errors do not trigger an NMI, but can optionally trigger a normal peripheral interrupt. For more information on
Flash error detection, see Section 3.11.8.
3.6.3.4 CPU HWBIST Error
If the Hardware Built-in self (HWBIST) module detects a fault in the CPU, an NMI is generated.
3.6.3.5 Software-Forced Error
There is a special NMI source that can only be triggered by writing to the SWERR bit in the NMIFLGFRC
register. Since the SWERR flag is never set by a real hardware fail, it can be used to implement a self-test mode
for the NMI subsystem.

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3.6.4 CRC Fail

A CRC fail result from the Background CRC (BGCRC) module can generate NMI. By default, this NMI is
enabled. To disable this feature, the NMIDIS configuration field in the BGCRC_CTRL1 register has to be written
with "1010".
3.6.5 ERAD NMI
The ERAD module can generate NMI based on different events. This is configurable in the GLBL_NMI_CTL
register.
3.6.6 Illegal Instruction Trap (ITRAP)
If the CPU tries to execute an illegal instruction, it generates a special interrupt called an illegal instruction trap
(ITRAP). This interrupt is non-maskable and has its own vector in the PIE vector table. For more information
about ITRAPs, see the Illegal-Instruction Trap section of the TMS320C28x DSP CPU and Instruction Set
Reference Guide.

Note
A RAM fetch access violation will trigger an ITRAP in addition to the normal peripheral interrupt for
RAM access violations. The CPU will handle the ITRAP first.

3.6.7 Error Pin

A signal called ERRORSTS can be output to GPIO24, GPIO28, GPIO29 or GPIO55. This signal goes low when
any bit is set in the NMI shadow flag register (NMISHDFLG). It can be used to alert an external system to a
problem in the microcontroller. Since the state of ERRORSTS is based on the shadow flags, ERRORSTS will
remain low until the flags are cleared by the CPU or a power-on reset occurs.
All GPIO pins are inputs on power-up. If the state of the chosen ERRORSTS pin during power-up is important,
an external pull-down should be connected to the pin.

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3.7 Clocking
This section explains the clock sources and clock domains on this device, and how to configure them for
application use. Figure 3-3 and Figure 3-4 provide an overview of the device's clocking system.
SYSCLKDIVSEL PLLSYSCLK
Watchdog NMIWD
Timer
SYS
PLLRAWCLK Divider
SYSPLL FPU
INTOSC1 CPUCLK
TMU
OSCCLK Flash
INTOSC2 SYSPLLCLKEN

X1 (XTAL)

OSCCLKSRCSEL
CPU
ePIE Boot ROM
CLA Message RAMs
SYSCLK GPIO DCSM
SYSCLK
Mx RAMs System Control
LSx RAMs WD
GSx RAMs XINT

CPUTIMERs I2C
One per SYSCLK peripheral CLB ADC
ECAP CMPSS
EQEP GPDAC
PCLKCRx EPWM CAN
PERx.SYSCLK
HRCAL MCAN
PMBUS HIC
LIN DCC
FSI HWBIST
SDFM BGCRC
EPG ERAD
AES

One per LSPCLK peripheral

LOSPCP
PCLKCRx
PERx.LSPCLK SCI
LSP LSPCLK
SPI
Divider

CLKSRCCTL2.CANxBCLKSEL

AUXCLKIN (GPIO29)
PERx.SYSCLK CAN Bit Clock

CLKSRCCTL2.MCANxBCLKSEL

CPUSYSCLK / MCAN Bit Clock

PLLRAWCLK

AUXCLKDIVSEL.MCANCLKDIV

Figure 3-3. Clocking System

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SYSPLL

OSCCLK ÷ INTCLK VCOCLK ÷ PLLRAWCLK

VCO
(REFDIV+1) (ODIV+1)

÷
IMULT

B15%%.- +/7.6
fPLLRAWCLK = ×
(4'(&+8 +1) (1&+8+1)

Figure 3-4. System PLL

3.7.1 Clock Sources

All of the clocks in the device are derived from one of four clock sources.
3.7.1.1 Primary Internal Oscillator (INTOSC2)
At power-up, the device is clocked from an on-chip 10-MHz oscillator (INTOSC2). INTOSC2 is the primary
internal clock source and is the default system clock at reset. It is used to run the boot ROM and can be used as
the system clock source for the application. Note that the INTOSC2 frequency tolerance is too loose to meet the
timing requirements for CAN. Use of the CAN modules requires an external oscillator. When INTOSC2 is used
as the system clock source, GPIO19 (X1) and GPIO18 (X2) are available as GPIO pins.
3.7.1.2 Backup Internal Oscillator (INTOSC1)
The device also includes a redundant on-chip 10 MHz oscillator (INTOSC1). INTOSC1 is a backup clock source
that normally only clocks the watchdog timers and missing clock detection circuit (MCD). If MCD is enabled
and a missing system clock is detected, the system PLL is bypassed and all system clocks are connected
to INTOSC1 automatically. INTOSC1 may also be manually selected as the system clock source for debug
purposes.
3.7.1.3 Auxiliary Clock Input (AUXCLKIN)
An additional external clock source is supported on GPIO29 (AUXCLKIN). This must be a single-ended 3.3V
external clock as shown in Figure 3-5 and can be used as the clock source for DCAN and MCAN. Frequency
limits and timing requirements are found in the TMS320F280013x Real-Time Microcontrollers Data Sheet. The
external clock can be connected directly to the GPIO29 pin.

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Microcontroller

GPIO29
VSS (AUXCLKIN)

+3.3 V

VDD Out

3.3-V Oscillator

Gnd

Figure 3-5. AUXCLKIN

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3.7.1.4 External Oscillator (XTAL)

The device supports an external clock source (XTAL), which can be used as the main system and CAN bit clock
source. Frequency limits and timing requirements are found in the TMS320F28003x Real-Time Microcontrollers
Data Sheet. External clock sources use the X1/GPIO19 and X2/GPIO18 pins. After power-up, the X1 and X2 pin
functionality can be enabled by following the procedure in Section 3.7.6.
Three types of external clock sources are supported:
• A single-ended 3.3V external clock. The clock signal should be connected to X1, as shown in Figure 3-6.

Microcontroller

GPIO19 GPIO18*
VSS X1 X2

* Available as a
+3.3 V
GPIO when X1 is
used as a clock

VDD Out

3.3-V Oscillator

Gnd

Figure 3-6. Single-ended 3.3V External Clock

• An external crystal. The crystal should be connected across X1 and X2 with its load capacitors connected to
VSS as shown in Figure 3-7.

Microcontroller

GPIO19 GPIO18
VSS X1 X2

Figure 3-7. External Crystal

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• An external resonator. The resonator should be connected across X1 and X2 with its ground connected to
VSS as shown in Figure 3-8.

Microcontroller

GPIO19 GPIO18
VSS X1 X2

Figure 3-8. External Resonator

Table 3-6. ALT Modes

XTALCR Bit(1)
GPIO19 Available on GPIO18 Available on
OSCOFF SE Operating Mode X1? X2?
0 0 Crystal Mode: Quartz crystal connected to X1/X2 No No
0 1 Single-Ended Mode: External clock on X1 No Yes
1 0 Oscillator off Yes Yes
1 1 Single-Ended Mode: External clock on X1 No Yes

(1) OSCOFF and SE determine the ALT mode of GPIO18 and GPIO19.

3.7.2 Derived Clocks

The clock sources discussed in the previous section can be multiplied (via PLL) and divided down to produce the
desired clock frequencies for the application. This process produces a set of derived clocks, which are described
in this section.
3.7.2.1 Oscillator Clock (OSCCLK)
One of INTOSC2, XTAL, or INTOSC1 must be chosen to be the master reference clock (OSCCLK) for the CPU
and most of the peripherals. OSCCLK may be used directly or fed through the system PLL to reach a higher
frequency. At reset, OSCCLK is the default system clock, and is connected to INTOSC2.
3.7.2.2 System PLL Output Clock (PLLRAWCLK)
The system PLL allows the device to run at its maximum rated operating frequency, and in most applications will
generate the main system clock. This PLL uses OSCCLK as a reference. PLLRAWCLK is the output of the PLL's
voltage-controlled oscillator (VCO). For configuration instructions, see Section 3.7.6.
3.7.3 Device Clock Domains
The device clock domains feed the clock inputs of the various modules in the device. They are connected to the
derived clocks, either directly or through an additional divider.
3.7.3.1 System Clock (PLLSYSCLK)
The NMI watchdog timer has its own clock domain (PLLSYSCLK). Despite the name, PLLSYSCLK may be
connected to the system PLL (PLLRAWCLK) or to OSCCLK. The chosen clock source is run through a
frequency divider, which is configured via the SYSCLKDIVSEL register. PLLSYSCLK is gated in HALT mode.

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3.7.3.2 CPU Clock (CPUCLK)

The CPU has its own clock (CPUCLK) that is used to clock the CPU and Flash wrapper. This clock is identical to
PLLSYSCLK, but is gated when the CPU enters IDLE or HALT mode.
3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
Each peripheral clock has its own independent clock gating which is controlled by the PCLKCRx registers.

Note
Application needs to wait for 5 SYSCLK cycles after enabling clock to the peripherals when using
PCLKCRx.

3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)

The SCI and SPI modules can communicate at bit rates that are much slower than the CPU frequency. These
modules are connected to a shared clock divider, which generates a low-speed peripheral clock (LSPCLK)
derived from SYSCLK. LSPCLK uses a /4 divider by default, but the ratio can be changed via the LOSPCP
register. Each SCI and SPI module's clock (PERx.LSPCLK) can be gated independently via the PCLKCRx
registers.
3.7.3.5 CAN Bit Clock
The required frequency tolerance for the DCAN and MCAN bit clock depends on the bit timing setup and
network configuration, and can be as tight as 0.1%. Since the main system clock (in the form of SYSCLK) may
not be precise enough, the bit clock can also be connected to XTAL, AUXCLKIN and PLLRAWCLK via the
CLKSRCCTL2 register. There is an independent selection for each CAN module. See the CLKSRCCTL2 register
for the valid options for the MCAN and DCAN.
To guarantee correct operation, the frequency of the CAN bit clock must be less than or equal to the SYSCLK
frequency.
3.7.3.6 CPU Timer2 Clock (TIMER2CLK)
CPU timers 0 and 1 are connected to PERx.SYSCLK. Timer 2 is connected to PERx.SYSCLK by default, but
may also be connected to INTOSC1, INTOSC2, or XTAL via the TMR2CLKCTL register. This register also
provides a separate prescale divider for timer 2. If a non-SYSCLK source is used, it must be divided down to no
more than half the SYSCLK frequency.
The main reason to use a non-SYSCLK source would be for internal frequency measurement. In most
applications, timer 2 will run off of SYSCLK.
3.7.4 XCLKOUT
It is sometimes necessary to observe a clock directly for debug and testing purposes. The external clock output
(XCLKOUT) feature supports this by connecting a clock to an external pin, which can be GPIO16 or GPIO18.
The available clock sources are PLLSYSCLK, PLLRAWCLK, SYSCLK, INTOSC1, INTOSC2, and XTAL.
To use XCLKOUT, first select the clock source via the CLKSRCCTL3 register. Next, select the desired output
divider via the XCLKOUTDIVSEL register. Finally, connect GPIO16 or GPIO18 to mux channel 11 using the
GPIO configuration registers.

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3.7.5 Clock Connectivity

Table 3-7 shows the clock connections sorted by the clock domain.
Table 3-7. Clock Connections Sorted by Clock Domain
Clock Domain Module Name
CPUCLK FPU
TMU
Flash
SYSCLK CLA
ePIE
Mx RAMs
LSx RAMs
GSx RAMs
Message RAMs
Boot ROM
GPIO Input Sync and Qual
WD
XINT
DCSM
PLLSYSCLK CPU
NMIWD
PERx.SYSCLK AES
CLB
Timer0 - 2
DCC0 - 1
FSI
ePWM1 - 8
eCAP1 - 3
eQEP1 - 2
ADCA, B, C
GPDACA, B
CMPSS1 - 4
DCAN
MCAN
I2CA - B
PMBUSA
LINA - B
HICA
HWBIST
BGCRC
HRCAL
EPG
SDFM
ERAD
PERx.LSPCLK SCIA - B
SPIA - B
CAN Bit Clock DCAN, MCAN
WDCLK (INTOSC1) Watchdog Timer

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3.7.6 Clock Source and PLL Setup

The needs of the application are what ultimately determine the clock configuration. Specific concerns such
as application performance, power consumption, total system cost, and EMC are beyond the scope of this
document, but they should provide answers to the following questions:
1. What is the desired CPU frequency?
2. Is CAN required?
3. What types of external oscillators or clock sources are available?
If CAN will be used in the appilcation, it is recommended to use an external clock source with a precise
frequency as the reference clock. Otherwise, it may be possible to use only INTOSC2 and avoid the need for
more external components.
3.7.7 Using an External Crystal or Resonator
The X1 and X2 pins double as GPIO19 and GPIO18. At power-up, these pins are in GPIO mode and the on-chip
crystal oscillator is powered off. The following procedure can be used to switch the pins to X1 and X2 mode and
enable the oscillator:
1. Clear the XTALCR.OSCOFF bit.
2. Wait for the crystal to power up. 1ms is the typical wait time but this depends on the crystal that is being
used.
3. Clear the X1 counter by writing a 1 to X1CNT.CLR and keep clearing until the X1 counter value in the
X1CNT register is no longer saturated 2047 (0x7ff).
4. Wait for the X1 counter value in the X1CNT register to reach 2047 (0x7ff).
5. Repeat steps 3-4 three additional times.
6. Select XTAL as the OSCCLK source by writing a 1 to CLKSRCCTL1.OSCCLKSRCSEL.
7. Check the MCLKSTS bit in the MCDCR register. If it's set, the oscillator has not finished powering up, and
more time is required:
a. Clear the missing clock status by writing a 1 to MCDCR.MCLKCLR.
b. Repeat steps 2-7. Do not reset the device. Doing so will power down the oscillator, which requires the
procedure to be restarted from step 1.
c. If the oscillator has not finished powering up in 10 milliseconds, there is a real clock failure.
8. If MCDCR.MCLKSTS is clear, the oscillator startup is a success. The system clock is now derived from
XTAL.
3.7.7.1 X1/X2 Precondition Circuit
The GPIO19/18 alternate functionality on X1/X2 can be used to speed up the start-up time of the crystal by as
much as 30% if needed. This functionality is achieved by preconditioning the load capacitors CL1 and CL2 to a
known state before the XTAL is turned on.
The steps below outline the procedure to precondition X1/X2 before turning on the XTAL:
1. ClkCfgRegs.XTALCR2.bit.XIF = 1; // Precondition X1 to High
2. ClkCfgRegs.XTALCR2.bit.XOF = 1; // Precondition X2 to High
3. ClkCfgRegs.XTALCR2.bit.FEN = 1; // Enable X1/X2 Precondition
4. DEVICE_DELAY_US(1);
5. ClkCfgRegs.XTALCR.bit.OSCOFF = 0; // Removes Precondition and Turns on the XTAL
6. ClkCfgRegs.XTALCR2.bit.FEN = 0; // Disables X1/X2 Precondition
3.7.8 Using an External Oscillator
The procedure for using an external oscillator connected to the X1 pin is similar to the procedure for using a
crystal or resonator:
1. Clear the XTALCR.OSCOFF bit.
2. Set the XTALCR.SE bit to enable single-ended mode.
3. Clear the X1 counter by writing a 1 to X1CNT.CLR and keep clearing until the X1 counter value in the
X1CNT register is no longer saturated 2047 (0x7ff).

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4. Wait for the X1 counter value in the X1CNT register to reach 2047 (0x7ff).
5. Repeat steps 3-4 three additional times.
6. Select XTAL as the OSCCLK source by writing a 1 to CLKSRCCTL1.OSCCLKSRCSEL.
7. Check the MCLKSTS bit in the MCDCR register. If it's set, either the external oscillator or the device has
failed.
8. If MCLKSTS is clear, the switch to the external clock is a success. The system clock is now derived from
XTAL.
3.7.9 Choosing PLL Settings
The equation shown in Figure 3-4 should be used to configure the PLL.
IMULT is the integer value of the multiplier.
REFDIV is the reference divider for the OSCCLK.
ODIV is the output divider of the PLLRAWCLK.
PLLSYSCLKDIV is the system clock divider.
For the permissible values of the multipliers and dividers, see the documentation for their respective registers.
Many combinations of multiplier and divider can produce the same output frequency. However, the product of the
reference clock frequency and the multiplier (known as the VCO frequency) must be in the range specified in the
TMS320F28003x Real-Time Microcontrollers Data Sheet.

Note
The system clock frequency (PLLSYSCLK) may not exceed the limit specified in the TMS320F28003x
Real-Time Microcontrollers Data Sheet. This limit does not allow for oscillator tolerance.

3.7.10 System Clock Setup

Once the application requirements are understood, a specific clock configuration can be determined. The default
configuration is for INTOSC2 to be used as the system clock (PLLSYSCLK) with a divider of 1. The following
procedure should be used to set up the desired application configuration:
Refer to your device SysCtl_setClock() function inside C2000Ware installation for an example.
Recommended sequence to set up the system PLL:
1. Bypass the PLL by clearing SYSPLLCTL1[PLLCLKEN]. Allow at least 60 NOP instructions for this to take
effect.
2. Power down the PLL by writing to SYSPLLCTL1.PLLEN=0 and allow at least 60 NOP instructions for this to
take effect.
3. Select the reference clock source (OSCCLK) by writing to CLKSRCCTL1.OSCCLKSRCSEL. Allow at least
300 NOP instructions for this to take effect.
4. Set the system clock divider to "/1" to ensure the fastest PLL configuration by clearing
SYSCLKDIVSEL[ PLLSYSCLKDIV].
5. Set the IMULT, REFDIV, and ODIV simultaneously by writing 32-bit value in SYSPLLMULT at once. This will
automatically enable the PLL. Be sure the settings for the multiplier and dividers do not violate the frequency
specifications defined in the TMS320F28003x Real-Time Microcontrollers Data Sheet.
6. Wait for PLL to lock by polling for lock status bit to go high, that is, SYSPLLSTS.LOCKS=1
7. Configure DCC with reference clock as OSCCLK and clock under measurement as PLLRAWCLK, and verify
the frequency of the PLL. If the frequency is out of range, do not enable PLLRAWCLK as SYSCLK, stop
here and troubleshoot. Refer to DCC chapter for more information on its configuration and usage.
8. Switch to the PLL as the system clock by setting SYSPLLCTL1[PLLCLKEN].

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Note
1. SYSPLL must be bypassed and powered down manually before changing the OSCCLK source.
2. At least 60 CPU clock cycles delay is needed after bypassing PLL, that is,
SYSPLLCTL1.PLLCLKEN=0.
3. At least 60 CPU clock cycles delay is needed after PLL is powered down, that is,
SYSPLLCTL1.PLLEN=0.
4. At least 300 CPU clock cycles delay is needed after OSSCLK source is changed.
5. PLL SLIP bit is not supported. DCC should be used to check the validity of the PLL clock. This
feature is included as part of SysCtl_setClock() function inside C2000Ware.

3.7.11 SYS PLL Bypass

If the application requires the PLL clock to be bypassed from the system, then it needs to configure
SYSPLLCTL1.PLLCLKEN=0. It takes up to 60 CPU clock cycles before the bypass is effective. In the meantime,
if PLLSYSCLKDIV is reduced to a lower value (for example from /2 to /1 or /4 to /2) the device may be clocked
above the maximum rated frequency and can lead to unpredictable device behavior. Hence, a delay of 60
CPU clock cycles is required after bypassing the PLL from enable state, that is, going from PLLCLKEN=1 to
PLLCLKEN=0.
3.7.12 Clock (OSCCLK) Failure Detection
To achieve safety diagnostic, Missing Clock Detection (MCD) can be used.
Table 3-8 lists the details.
Table 3-8. Clock Source (OSCCLK) Failure Detection
Clock Failure Time for Detection
Clocks Detected Limitations
Detection Circuitry (in Cycles)
Missing Clock Detection (MCD) INTOSC2, XTAL/X1 8192 INTOSC1 cycles Cannot detect INTOSC1 clock failure.

3.7.12.1 Missing Clock Detection

The missing clock detect (MCD) logic detects OSCCLK failure, using INTOSC1 as the reference clock source.
This circuit only detects complete loss of OSCCLK and doesn’t do any detection of frequency drift on the
OSCCLK.
This circuit monitors the OSCLK (primary clock) using the 10 MHz clock provided by the INTOSC1 (secondary
clock) as a backup clock. This circuit functions as below:
1. The primary clock (OSCCLK) clock keeps ticking a 7-bit counter (named as MCDPCNT). This counter is
asynchronously reset with XRSn.
2. The secondary clock (INTOSC1) clock keeps ticking a 13-bit counter (named as MCDSCNT). This counter is
asynchronously reset with XRSn.
3. Each time MCDPCNT overflows, the MCDSCNT counter is reset. Thus, if OSCCLK is present or not slower
than INTOSC1 by a factor of 64, MCDSCNT never overflows.
4. If OSCCLK stops for some reason or is slower than INTOSC1 by at least a factor of 64, the MCDSCNT
overflows and a missing clock condition is detected on OSCCLK.
5. The above check is continuously active, unless the MCD is disabled using MCDCR register (by making the
MCLKOFF bit 1)

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6. If the circuit ever detects a missing OSCCLK, the following occurs:

• The MCDSTS flag is set
• The MCDSCNT counter is frozen to prevent further missing clock detection
• The CLOCKFAIL signal goes high, which generates TRIP events to PWM modules and fires NMIs to
CPU1.NMIWD.
• PLL is forcefully bypassed and OSCCLK source is switched to INTOSC1 (New, System Clock Frequency
= INTOSC1 Freq 10 MHz)/SYSDIV). In the meantime when the clock switches to INTOSC1, the System
runs on PLL limp Clock.
• SYSPLLMULT.IMULT is zeroed out automatically in this case.
• While the MCDSTS bit is set, the OSCCLKSRCSEL bits have no effect and OSCCLK is forcefully
connected to INTOSC1.
• PLLRAWCLK going to the system is switched to INTOSC1 automatically
7. If the MCLKCLR bit is written (this is a W=1 bit), MCDSTS bit is cleared and OSCCLK source is decided
by the OSCCLKSRCSEL bits. Writing to MCLKCLR also clears the MCDPCNT and MCDSCNT counters
to allow the circuit re-evaluate missing clock detection. If user wants to lock the PLL after missing clock
detection, switch the clock source to INTOSC1 (using OSCCLKSRCSEL register), do a MCLKCLR and
re-lock the PLL.
8. The MCD is enabled at power up.
Figure 3-9 shows the missing clock logic functional flow.

Figure 3-9. Missing Clock Detection Logic

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Note
On a complete clock failure when OSCCLK is dead, it can take a maximum time of 8192 INTOSC1
cycles (that is, 0.8192 ms) before the CLOCKFAIL signal goes high, after which:
• NMI is generated
• OSCCLK is switched to INTOSC1
• PWM Trip happens

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3.8 32-Bit CPU Timers 0/1/2

This section describes the three 32-bit CPU timers (TIMER0/1/2) shown in Figure 3-10.
Timer0 and Timer1 can be used in user applications. Timer2 is reserved for real-time operating system uses (for
example, TI-RTOS). If the application is not using an operating system that utilizes this timer, then Timer2 can be
used in the application. timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 3-11.

Figure 3-10. CPU Timers

A. The timer registers are connected to the memory bus of the C28x processor.
B. The CPU Timers are synchronized to SYSCLKOUT.

Figure 3-11. CPU Timer Interrupt Signals and Output Signal

The general operation of a CPU timer is as follows:

• The 32-bit counter register, TIMH:TIM, is loaded with the value in the period register PRDH:PRD
• The counter decrements once every (TPR[TDDRH:TDDR]+1) SYSCLK cycles, where TDDRH:TDDR is the
timer divider.
• When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse.
The registers listed in Section 3.16 are used to configure the timers.

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3.9 Watchdog Timer

The watchdog module consists of an 8-bit counter fed by a prescaled clock (WDCLK, which is connected to
INTOSC1). When the counter reaches its maximum value, the module generates an output pulse 512 WDCLKs
wide. This pulse can generate an interrupt or a reset. The CPU must periodically write a 0x55 + 0xAA sequence
into the watchdog key register to reset the watchdog counter. The counter can also be disabled.
The counter's clock is divided down from WDCLK by two dividers. The prescaler is adjustable from /1 to /64 in
powers of two. The pre-divider defaults to /512 for backwards compatibility, but is adjustable from /2 to /4096 in
powers of two. This allows a wide range of timeout values for safety-critical applications.
Figure 3-12 shows the various functional blocks within the watchdog module.
WDCR.WDPRECLKDIV WDCR.WDPS WDCR.WDDIS

WDCNTR

WDCLK
(INTOSC1) Overflow 1-count
delay
8-bit
WDCLK Watchdog Watchdog
Divider Prescaler Counter

SYSRSn
Clear
Count

WDWCR.MIN
WDKEY (7:0)
Out of Window Watchdog
Watchdog Good Key
Window
Key Detector Detector
WDCR(WDCHK(2:0))
55 + AA

Bad Key

WDRSTn Generate
1 0 1 512-WDCLK Watchdog Time-out
WDINTn Output Pulse

SCSR.WDENINT

Figure 3-12. Watchdog Timer Module

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3.9.1 Servicing the Watchdog Timer

The watchdog counter (WDCNTR) is reset when the proper sequence is written to the WDKEY register before
the 8-bit watchdog counter overflows. The WDCNTR is reset-enabled when a value of 0x55 is written to the
WDKEY. When the next value written to the WDKEY register is 0xAA, then the WDCNTR is reset. Any value
written to the WDKEY other than 0x55 or 0xAA causes no action. Any sequence of 0x55 and 0xAA values can
be written to the WDKEY without causing a system reset; only a write of 0x55 followed by a write of 0xAA to the
WDKEY resets the WDCNTR.
The first action that enables the WDCNTR to be reset is shown in Step 3 in Table 3-9. The WDCNTR is not
actually reset until step 6. Step 8 again re-enables the WDCNTR to be reset and step 9 resets the WDCNTR.
Step 10 again re-enables the WDCNTR to be reset. Writing the wrong key value to the WDKEY in step 11
causes no action, however the WDCNTR is no longer enabled to be reset and the 0xAA in step 12 now has no
effect.
If the watchdog is configured to reset the device, then a WDCR overflow or writing the incorrect value to the
WDCR[WDCHK] bits resets the device and sets the watchdog flag (WDRSn) in the reset cause register (RESC).
After a reset, the program can read the state of this flag to determine whether the reset is caused by the
watchdog. After doing this, the program can clear WDRSn to allow subsequent watchdog resets to be detected.
Watchdog resets are not prevented when the flag is set.
Table 3-9. Example Watchdog Key Sequences
Step Value Written to WDKEY Result
1 0xAA No action
2 0xAA No action
3 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
4 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
5 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
6 0xAA WDCNTR is reset.
7 0xAA No action
8 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
9 0xAA WDCNTR is reset.
10 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
11 0x32 Improper value written to WDKEY.
No action, WDCNTR no longer enabled to be reset by next 0xAA.
12 0xAA No action due to previous invalid value.
13 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
14 0xAA WDCNTR is reset.

3.9.2 Minimum Window Check

To complement the timeout mechanism, the watchdog also contains an optional "windowing" feature that
requires a minimum delay between counter resets. This can help protect against error conditions that bypass
large parts of the normal program flow but still include watchdog handling.
To set the window minimum, write the desired minimum watchdog count to the WDWCR register. This value will
take effect after the next WDKEY sequence. From then on, any attempt to service the watchdog when WDCNTR
is less than WDWCR will trigger a watchdog interrupt or reset. When WDCNTR is greater than or equal to
WDWCR, the watchdog can be serviced normally.
At reset, the window minimum is zero, which disables the windowing feature.

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3.9.3 Watchdog Reset or Watchdog Interrupt Mode

The watchdog can be configured in the SCSR register to either reset the device (WDRST) or assert an interrupt
(WDINT) if the watchdog counter reaches its maximum value. The behavior of each condition is:
• Reset mode:
If the watchdog is configured to reset the device, then the WDRST signal will pull the device reset (XRS) pin
low for 512 OSCCLK cycles when the watchdog counter reaches its maximum value.
• Interrupt mode:
When the watchdog counter expires, it will assert an interrupt by driving the WDINT signal low for 512
OSCCLK cycles. The falling edge of WDINT triggers a WAKEINT interrupt in the PIE if it is enabled. Because
the PIE is edge-triggered, re-enabling the WAKEINT while WDINT is active will not produce a duplicate
interrupt.
To avoid unexpected behavior, software should not change the configuration of the watchdog while WDINT is
active. For example, changing from interrupt mode to reset mode while WDINT is active will immediately
reset the device. Disabling the watchdog while WDINT is active will cause a duplicate interrupt if the
watchdog is later re-enabled. If a debug reset is issued while WDINT is active, the reset cause register
(RESC) will show a watchdog reset. The WDINTS bit in the SCSR register can be read to determine the
current state of WDINT.

3.9.4 Watchdog Operation in Low Power Modes

In IDLE mode, the watchdog interrupt ( WDINT) signal can generate an interrupt to the CPU to take the CPU
out of IDLE mode. As with any other peripheral, the watchdog interrupt will trigger a WAKE interrupt in the PIE
during IDLE mode. User software must determine which peripheral caused the interrupt.
Note: If the watchdog interrupt is used to wake-up from an IDLE low power mode condition, software must make
sure that the WDINT signal goes back high before attempting to reenter the IDLE mode. The WDINT signal will
be held low for 512 OSCCLK cycles when the watchdog interrupt is generated. The current state of WDINT can
be determined by reading the watchdog interrupt status bit (WDINTS) bit in the SCSR register. WDINTS follows
the state of WDINT by two SYSCLKOUT cycles.
In HALT mode, the internal oscillators and watchdog timer are kept active if the user sets
CLKSRCCTL1.WDHALTI = 1. A watchdog reset can wake the system from HALT mode, but a watchdog
interrupt cannot.
3.9.5 Emulation Considerations
The watchdog module behaves as follows under various debug conditions:
CPU Suspended When the CPU is suspended, the watchdog clock (WDCLK) is suspended.
Run-Free Mode When the CPU is placed in run-free mode, then the watchdog module resumes operation as normal.
Real-Time Single-Step Mode When the CPU is in real-time single-step mode, the watchdog clock (WDCLK) is suspended. The
watchdog remains suspended even within real-time interrupts.
Real-Time Run-Free Mode When the CPU is in real-time run-free mode, the watchdog operates as normal.

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3.10 Low Power Modes

This device has HALT, IDLE, and STANDBY as clock-gating low-power modes.
All low-power modes are entered by setting the LPMCR register and executing the IDLE instruction. More
information about this instruction can be found in the TMS320C28x CPU and Instruction Set Reference Guide.
Low-power modes should not be entered into while a Flash program or erase operation is ongoing. Entering
HALT will stop all CPU and peripheral activities. This includes active transmissions and control algorithms. When
preparing to enter HALT mode, the application should ensure that the system is prepared to enter a period of
inactivity.
Before entering HALT mode, check the value of the GPIODAT register of the pin selected for HALT wake-up
(GPIOLPMSEL0/1) prior to entering the low-power mode to ensure that the wake event has not already been
asserted.
3.10.1 Clock-Gating Low-Power Modes
IDLE and HALT modes on this device are similar to those on other C28x devices. Table 3-10 describes the effect
on the system when any of the clock-gating low-power modes are entered.
Table 3-10. Effect of Clock-Gating Low-Power Modes on the Device
Modules/
IDLE STANDBY HALT
Clock Domain
SYSCLK Active Gated Gated
CPUCLK Gated Gated Gated
Clock to modules connected Active Gated Gated
to PERx.SYSCLK
WDCLK Active Active Gated if CLKSRCCTL1.WDHALTI = 0
PLL Powered Powered Software must power down PLL before entering HALT.
INTOSC1 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
INTOSC2 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
Flash(1) Powered Powered Powered
XTAL(2) Powered Powered Powered

(1) The Flash module is not powered down by hardware in any LPM. It may be powered down using software if required by the
application. For more information, see the Flash Module chapter.
(2) The XTAL is not powered down by hardware in any LPM. It may be powered down by software setting the XTALCR.OSCOFF bit to 1.
This can be done at any time during the application if the XTAL is not required.

3.10.2 IDLE
IDLE is a standard feature of the C28x CPU. In this mode, the CPU clock is gated while all peripheral clocks are
left running. IDLE can thus be used to conserve power while a CPU is waiting for peripheral events.
Any enabled interrupt will wake the CPU up from IDLE mode.
To enter IDLE mode, set LPMCR.LPM to 0x0 and execute the IDLE instruction.
The CPU will resume normal operations upon any enabled interrupt event.

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3.10.3 STANDBY
STANDBY is a more aggressive low-power mode that gates both the CPU clock and any peripheral clocks
derived from the CPU's SYSCLK. The watchdog however, is left active. STANDBY is best suited for an
application where the wake-up signal will come from an external system (or CPU subsystem) rather than a
peripheral input.
An NMI (or optionally) a watchdog interrupt or a configured GPIO can wake the CPU from STANDBY mode.
Each GPIO from GPIO0-60 can be configured to wake the CPU when they are driven active low. Upon wakeup,
the CPU receives the WAKEINT interrupt if configured.
To enter STANDBY mode:
1. Set LPMCR.LPM to 0x1.
2. Enable the WAKEINT interrupt in the PIE.
3. For watchdog interrupt wakeup, set LPMCR.WDINTE to 1 and configure the watchdog to generate
interrupts.
4. For GPIO wakeup, set GPIOLPMSEL0 and GPIOLPMSEL1 to connect the chosen GPIOs to the LPM
module, and set LPMCR.QUALSTDBY to select the number of OSCCLK cycles for input qualification.
5. Execute the IDLE instruction to enter STANDBY.
To wake up from STANDBY mode:
1. Configure the desired GPIO to trigger the wakeup.
2. Drive the selected GPIO signal low; it must remain low for the number of OSCCLK cycles specified in the
QUALSTDBY bits in the LPMCR register. If the signal is sampled high during this period, the count restarts.
At the end of the qualification period, the PLL enables the CLKIN to the CPU and the WAKEINT interrupt is
latched in the PIE block.
The CPU is now out of STANDBY mode and can resume normal execution.
3.10.4 HALT
HALT is a global low-power mode that gates almost all system clocks and allows for power-down of oscillators
and analog blocks.
Unlike on other C2000™ devices, HALT mode will not automatically power down the XTAL upon HALT entry.
Additionally, if the XTAL is not powered on, waking up from HALT mode will not automatically power on the
XTAL. The XTALCR.OSCOFF bit has been added to power on and off the XTAL circuitry when not needed
through application software.
For applications that require minimal power consumption during HALT mode, application software should power
off the XTAL prior to entering HALT. If the OSCCLK source is configured to be XTAL, the application should first
switch the OSSCLK source to INTOSC1 or INTOSC2 prior to setting XTALCR.OSCOFF.
GPIO0-60 can be configured to wake up the system from HALT. No other wakeup option is available. However,
the watchdog timer may still be clocked, and can be configured to produce a watchdog reset if a timeout
mechanism is needed. On wakeup, the CPU receives a WAKEINT interrupt.
To enter HALT mode:
1. Enable the WAKEINT interrupt in the PIE .
2. Set LPMCR.LPM to 0x2. Set GPIOLPMSEL0 and GPIOLPMSEL1 to connect the chosen GPIOs to the LPM
module.
3. Set CLKSRCCTL1.WDHALTI to 1 to keep the watchdog timer active and INTOSC1 and INTOSC2 powered
up in HALT.
4. Set CLKSRCCTL1.WDHALTI to 0 to disable the watchdog timer and power down INTOSC1 and INTOSC2 in
HALT.
5. Execute the IDLE instruction to enter HALT.
If an interrupt or NMI is received while the IDLE instruction is in the pipeline, the system will begin executing the
WAKEINT ISR. After HALT wakeup, ISR execution will resume where it left off.

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Note
Before entering HALT mode, if the system PLL is locked (SYSPLL.LOCKS = 1), it must also be
connected to the system clock (PLLCTL1.PLLCLKEN = 1). Otherwise, the device will never wake up.

To wake up from HALT mode:

1. Drive the selected GPIO low for a minimum 5us. This will activate the WAKEINT PIE interrupt.
2. Drive the wake-up GPIO high again to initiate the powering up of the SYSPLL
3. Wait 16us plus 1024 OSCLK cycles to allow the PLLs to lock and the WAKEINT ISR to be latched.
4. Execute the WAKEINT ISR.
The device is now out of HALT mode and can resume normal execution.
3.10.5 Flash Power-down Considerations
The Flash module on this device can be powered down at any time during an application. There are some
considerations that must be made when powering down the Flash.
When the application software powers down the Flash, it must ensure that the function that puts the Flash to
sleep is executed from RAM. Note that there should not be any access to Flash after the Flash is put to sleep
to realize the power savings. If there is an access to Flash, Flash wakeup process (wakeup time depends on
PSLEEP and RWAIT) gets initialized and the application will not realize Flash power savings. For example, if the
application has to execute any code after putting the Flash to sleep and before putting the device in to low power
mode, the application should execute that code from RAM and not from Flash.
PSLEEP and RWAIT can be optimized to reduce the Flash wakeup time for a given SYSCLK frequency.
BootROM configures the best possible PSLEEP value for the 120 MHz operation. However, the application
software can decrease the PSLEEP value to reduce the Flash wakeup time if the application SYSCLK is less
than 120 MHz. This is applicable in the context of an application entering the Halt mode since PLL must be
disabled before entering the Halt mode. In this case, the PSLEEP value can be decreased to get a faster Flash
wakeup upon exit from LPM.
If the Wake ISR is in Flash, it is suggested to optimize the PSLEEP and RWAIT values before entering the LPM,
and after the Flash is in sleep, since application does not get a chance to modify these before Flash is awake
after exiting from LPM. However, after the LPM exit and once the Flash is awake, application should branch to
RAM to restore RWAIT and PSLEEP (as per the application SYSCLK to which PLL will be locked for) and then
proceed with Flash execution to lock the PLL.
If the Wake ISR is in RAM, application can optimize the PSLEEP and RWAIT values in the Wake ISR and then
do a dummy Flash access to initiate the Flash wakeup process. While the Flash is waking up, application can
initialize the PLL lock process. Once the Flash is awake, application can put the PLL in clock path. If the user
does not want to lock the PLL from RAM, PLL can be locked from Flash (this means Flash wakeup and PLL lock
are not done in parallel), but in any case make sure to restore the RWAIT and PSLEEP (as per the application
SYSCLK to which PLL will be locked for) in Wake ISR before proceeding to Flash execution.

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3.11 Memory Controller Module

On this device, the RAMs have different characteristics. These are:
• Dedicated to the CPU: M0, M1 RAMs
• Shared between the CPU and CLA: LSx RAMs
• Shared between the CPU, DMA and HIC: GSx RAMs
• Used to send and receive messages between processors: MSG RAMs
All these RAMs are highly configurable to achieve control for write access and fetch access from different
masters. All the RAMs are enabled with the ECC feature (both data and address). Some of the memories are
secure memory as well. Refer to the Dual Code Security Module (DCSM) chapter for more details. Each RAM
has its own controller which takes care of the access protection/security related checks and ECC features for
that RAM. Figure 3-13 shows the configuration of these RAMs.

LSx RAM GSx RAM

CPU
CPU CPU TO CLA MSGRAM M0/M1
CLA CLA TO CPU MSGRAM RAM
DMA TO CLA MSGRAM
CPU DMA HIC
CLA TO DMA MSGRAM

Figure 3-13. Memory Architecture

3.11.1 Dedicated RAM (Mx RAM)

This device has two dedicated RAM blocks: M0 and M1. M0 and M1 memories are small blocks of memory
which are tightly coupled with the CPU. Only the CPU has access to these memories. No other masters (CLA,
DMA or HIC) have access to these memories.
All dedicated RAMs have ECC and access protection (CPU write protection/CPU fetch protection) feature. Each
type of access protection for each RAM block can be enabled/disabled by configuring the specific bit in the
access protection register, allocated to each subsystem (DxACCPROT).
3.11.2 Local Shared RAM (LSx RAM)
Local shared RAMs (LSx RAMs) are secure memories and have ECC. These memories are shared between
the CPU and CLA but are by default dedicated to the CPU only. CLA access can be enabled by configuring
MSEL_LSx bit field in the LSxMSEL register.
Further, when these memories are shared between the CPU and CLA, the user could choose to use these
memories as CLA program memory by configuring the CLAPGM_LSx bit field in the LSxCLAPGM registers.
CPU access to all memory blocks, which are programmed as CLA program memory, are blocked.
All these RAMs have the access protection (CPU write and CPU fetch) feature. Each type of access protection
for each RAM block can be enabled or disabled by configuring the specific bit in the local shared RAM access
protection registers, mapped to each CPU subsystem. Table 3-11 shows the LSx RAM features.

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Table 3-11. Local Shared RAM

MSEL_LSx CLAPGM_LSx CPUx CPUx.CLA1 Comment
Allowed Access Allowed Access

00 X All - LSx memory is configured as CPU dedicated RAM

01 0 All Data Read LSx memory is shared between CPU and CLA1
Data Write

01 1 Emulation Read Fetch Only LSx memory is CLA1 program memory

Emulation Write Emulation Read
Emulation Write

3.11.3 Global Shared RAM (GSx RAM)

RAM blocks which are accessible from the CPU, DMA and HIC are called global shared RAMs (GSx RAMs).
Table 3-12 shows the features of the GSx RAM.
Table 3-12. Global Shared RAM
CPU (Fetch) CPU (Read) CPU (Write) CPU.DMA CPU.DMA HIC (Read) HIC (Write)
(Read) (Write)
Yes Yes Yes Yes Yes Yes Yes

The shared RAM has different levels of access protection that can be enabled or disabled by configuring specific
bits in the GSxACCPROT registers.
Access protection configuration for the GSx RAM block can be locked by the user to prevent further updates to
this bit field. The user can also choose to permanently lock the configuration to individual bit fields by setting
the specific bit fields in the GSxCOMMIT register (refer to the register description for more details). Once a
configuration is committed for a particular GSx RAM block, it can not be changed further until CPU.SYSRS is
issued.
3.11.4 CLA-CPU Message RAM
These RAM blocks can be used to share data between the CPU and CLA. The CLA has read and write access
to the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA MSGRAM." The CPU
and CLA both have read access to both MSGRAMs.
3.11.5 CLA-DMA Message RAM
These RAMs blocks can be used to share data between CLA and DMA. The CLA has read and write access to
the "CLA to DMA MSGRAM." The DMA has read and write access to the "DMA to CLA MSGRAM." The CLA
and DMA both have read access to both MSGRAMs.
3.11.6 Access Arbitration
For a shared RAM, multiple accesses can happen at any given time. The maximum number of accesses to any
shared RAM at any given time depends on the type of shared RAM. On this device, a combination of a fixed and
round-robin scheme is followed to arbitrate multiple access at any given time.
The following is the order of fixed priority for CPU accesses:
1. Data Write/Program Write
2. Data Read
3. Program Read/Program Fetch
The following is the order of fixed priority for CLA accesses:
1. Data Write
2. Data Read/Program Fetch

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Figure 3-14 represents the arbitration scheme on global shared memories.

Figure 3-15 represents the arbitration scheme on local shared memories.

CPU-DWRITE CPU Round Robin Arbitration

Fixed
CPU-DREAD
Priority
CPU-PREAD/FETCH Arbiter
RR-CPU

CPU.DMA READ/WRITE
RR-CPU.DMA RR-HIC

HIC READ/WRITE

Figure 3-14. Arbitration Scheme on Global Shared Memories

CPU-DWRITE CPU Round Robin Arbitration

Fixed
CPU-DREAD
Priority
CPU-PREAD/FETCH Arbiter
RR-CPU

CLA-DWRITE CLA
Fixed RR-CPU.CLA
Priority
CLA-DREAD Arbiter

Figure 3-15. Arbitration Scheme on Local Shared Memories

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3.11.7 Access Protection

The RAM blocks have different levels of protection. This feature allows the user to enable or disable specific
access to individual RAM blocks from individual masters. There is no protection for read accesses, hence reads
are always allowed from all the masters which have access to that RAM block.
The following sections describe the different kinds of protection available for RAM blocks on this device.

Note
For debug accesses, all the protections are disabled.

Note 1: All access protections are ignored during debug accesses. Write access to a protected memory will go through
when it is done via the debugger, irrespective of the write protection configuration for that memory.

3.11.7.1 CPU Fetch Protection

Fetch accesses from the CPU can be protected by setting the FETCHPROTx bit of the specific register to ‘1.’ If
fetch access is done by the CPU to a memory where CPU fetch protection is enabled, a fetch protection violation
occurs.
If a fetch protection violation occurs, it results in an ITRAP for CPU. A flag gets set in the appropriate access
violation flag register, and the memory address for which the access violation occurred, gets latched into the
appropriate CPU fetch access violation address register.
3.11.7.2 CPU Write Protection
Write accesses from the CPU can be protected by setting the CPUWRPROTx bit of the specific register to ‘1.’ If
write access is done by a CPU to memory where it is protected, a write protection violation occurs.
If a write protection violation occurs, the write gets ignored, a flag gets set in the appropriate access violation flag
register, and the memory address for which the access violation occurred, gets latched into the appropriate CPU
write access violation address register. Also, an access violation interrupt is generated if enabled in the interrupt
enable register.
3.11.7.3 CPU Read Protection
For local shared RAM, if memory is shared between the CPU and its CLA, the CPU will only have access if the
memory is configured as data RAM for the CLA. If it is programmed as program RAM, all the access from the
CPU, including a read, will be blocked and the violation will be considered as a non-master access violation.
If a read protection violation occurs, a flag gets set in the appropriate access violation flag register, and the
memory address for which the access violation occurred, gets latched in the appropriate CPU read access
violation address register. Also, an access violation interrupt is generated, if enabled in the interrupt enable
register.
3.11.7.4 CLA Fetch Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as data RAM for the CLA,
any fetch access from the CLA to that particular LSx RAM results in a CLA fetch protection violation, which is a
non-master access violation.
If a CLA fetch protection violation occurs, it results in a MSTOP, a flag gets set into the appropriate access
violation flag register, and the memory address for which the access violation occurred, gets latched into the
appropriate CLA fetch access violation address register. Also, an access violation interrupt is generated to the
master CPU if enabled in the interrupt enable register.
3.11.7.5 CLA Read Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as program RAM for the
CLA, any data read access from the CLA to that particular LSx RAM results in a CLA read protection violation,
which is a non-master access violation.

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If a CLA read protection violation occurs, a flag gets set into the appropriate access violation flag register, and
the memory address for which the access violation occurred, gets latched into the appropriate CLA read access
violation address register. Also, an access violation interrupt is generated to the master CPU if enabled in the
interrupt enable register.
3.11.7.6 CLA Write Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if it is configured as program RAM for the
CLA, any data write access from the CLA to that particular LSx RAM results in a CLA write protection violation,
which is a non-master access violation. Similarly any data write access from CLA to CPUTOCLA or DMATOCLA
MSGRAM will result in a CLA write protection violation, which is a non-master access violation.
If a CLA write protection violation occurs, write gets ignored, a flag gets set into the appropriate access violation
flag register, and the memory address for which the access violation occurred, gets latched into the appropriate
CLA write access violation address register. Also, an access violation interrupt is generated to the master CPU if
enabled in the interrupt enable register.
3.11.7.7 HIC Write Protection
Write accesses from the HIC can be protected by setting the HICWRPROTx bit of a specific register to ‘1.’ If a
write access is done by the HIC to protected memory, a write protection violation occurs.
If a write access is made to GSx memory by a non-master HIC, it is called a non-master write protection
violation. If a write access is made to a dedicated or shared memory by a master HIC, and HICWRPROTx is set
to ‘1’ for that memory, it is called a master HIC write protection violation.
A flag gets set in the HIC access violation flag register, and the memory address where the violation happened
gets latched in the HIC fetch access violation address register. These are dedicated registers for each
subsystem.

3.11.7.8 DMA Write Protection

Write accesses from the DMA can be protected by setting the DMAWRPROTx bit of a specific register to ‘1.’ If a
write access is done by the DMA to protected memory, a write protection violation occurs.
If a write access is made to GSx memory by a non-master DMA, it is called a non-master write protection
violation. If a write access is made to a dedicated or shared memory by a master DMA, and DMAWRPROTx is
set to ‘1’ for that memory, it is called a master DMA write protection violation.
A flag gets set in the DMA access violation flag register, and the memory address where the violation happened
gets latched in the DMA fetch access violation address register. These are dedicated registers for each
subsystem.
3.11.8 Memory Error Detection and Correction, and Error Handling
These devices have memory error detection and correction features to satisfy safety standards requirements.
These requirements warrant the addition of detection mechanisms for finite dangerous failures.
In this device, all RAMs support error correction code (ECC) protection. The ECC scheme used is Single Error
Correction Double Error Detection (SECDED). ECC will cover the data bits stored in memory as well as address.
ECC calculation is done inside the memory controller module and written into the memory along with the data.
ECC is computed for 16-bit data; hence, for each 32-bit of data, there will be three 7-bit ECC codes, two of which
are for data and a third one for the address.
3.11.8.1 Error Detection and Correction
Error detection is done while reading the data from memory. The error detection is performed for data as well as
address. For ECC memory, along with a single-bit error, a double-bit error also gets detected. These errors are
called correctable and uncorrectable errors. The following are characteristics of these errors:
• Single-bit ECC errors are correctable errors
• Double-bit ECC errors are uncorrectable errors

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• Address ECC errors are also uncorrectable errors

Correctable errors get corrected by the memory controller module and then correct data is given back as read
data to the master. It is also written back into the memory to prevent a double-bit error due to another single-bit
error at the same memory address.
3.11.8.2 Error Handling
For each correctable error, the count in the correctable error count register will increment by one. When the
value in this count register becomes equal to the value configured in the correctable error threshold register, an
interrupt is generated to the CPU, if the interrupt is enabled in the correctable interrupt enable register. The user
needs to configure the correctable error threshold register based on the system requirements. Also, the address
for which the error occurred, gets latched into a register and a flag also gets set in a status register.
If there are uncorrectable errors, an NMI gets generated for the CPU. In this case also, the address for which the
error occurred gets latched into a register, and a flag gets set in a status register.
Table 3-13 summarizes different error situations that can arise. These need to be handled appropriately in the
software, using the status and interrupt indications provided.
Table 3-13. Error Handling in Different Scenarios
Access Type Error Found In Error Type Status Indication Error Notification
Reads Data read from Uncorrectable Yes -CPU/CPU.DMA/ NMI for CPU access
memory Error CPU.CLA1/DMA/CLA Read Error NMI for CPU.DMA access
(Double bit Error Address Register Data returned to CPU/ NMI to CPU for CPU.CLA1 access
for ECC RAMs) CPU.DMA/CPU.CLA1 is incorrect
Reads Data read from Single-bit error for Yes - CPU/CPU.DMA CPU/DMA Read Interrupt when error counter reaches the
memory ECC RAMs Error Address Register Increment single user programmable threshold for single
error counter errors
Reads Address Address error Yes - CPU/CPU.DMA/ NMI to CPU for CPU access
CPU.CLA1/DMA/CLA Read Address NMI to CPU for CPU.DMA access
Error Register Data returned to CPU/ NMI to CPU for CPU.CLA1 access
CPU.DMA/CPU.CLA1 is incorrect

Note
In the case of an uncorrectable error during fetch on the CPU, there is the possibility of getting an
ITRAP before an NMI exception, since garbage instructions enter into the CPU pipeline before the
NMI gets generated.
During debug accesses, correctable as well as uncorrectable errors are masked.

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3.11.9 Application Test Hooks for Error Detection and Correction

Since error detection and correction logic is part of safety critical logic, safety applications may need to ensure
that the logic is always working fine (during run time also). To enable this, a test mode is provided, in which a
user can modify the data bits (without modifying the ECC bits) or ECC bits directly. Using this feature, an ECC
error could be injected into data.

Note
The memory map for ECC bits and data bits are the same. The user must choose a different test
mode to access ECC bits. In test mode, all access to memories (data as well as ECC) should be done
as 32-bit access only.

Table 3-14 shows the bit mapping for the ECC bits when they are read in RAMTEST mode using their respective
addresses.
Table 3-14. Mapping of ECC Bits in Read Data from ECC Address Map
Data Bits Location in Read Data Content (ECC Memory)
6:0 ECC Code for lower 16 bits of data
7 Not Used
14:8 ECC Code for upper 16 bits of data
15 Not Used
22:16 ECC Code for address
31:23 Not Used

3.11.10 RAM Initialization

To ensure that read/fetch from uninitialized RAM locations do not cause ECC errors, the RAM_INIT feature
is provided for each memory block. Using this feature, any RAM block can be initialized with 0x0 data and
respective ECC bits accordingly. This can be initiated by setting the INIT bit to ‘1’ for the specific RAM block in
INIT registers. To check the status of RAM initialization, SW should poll for the INITDONE bit for that RAM block
in the INITDONE register to be set. Unless this bit gets set, no access should be made to that RAM memory
block.

Note
None of the masters should access the memory while initialization is taking place. If memory is
accessed before RAMINITDONE is set, the memory read/write as well as initialization will not happen
correctly.

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3.12 JTAG
Gel files perform certain initialization tasks. This helps the users in a debug environment. However, when
executed standalone (without the emulator connected) the application may not work as expected, since there is
no gel file to perform those initializations. For example, gel file disables watchdog. If user code does not service
the watchdog in the application (or fails to disable it), there will be a difference in how the application behaves
with the debugger and without.
Common tasks performed by the gel files (but not boot-ROM).
On Reset:
• Disable Flash ECC on some devices.
– Disabling ECC only when using Flash API functions, see the Flash API User Guide for details. Otherwise,
TI suggests to always program ECC and enable ECC-check.
• Disable Watchdog
• Enable CLA clock
• Select real-time mode or C28x mode
On Restart:
• Select real-time mode or C28x mode
• Clear IER and IFR
On Target Connect:
• Select real-time mode or C28x mode
3.13 Live Firmware Update
This device includes hardware hooks to streamline firmware updates. These hardware hooks enable seamless
switching from the old firmware to the new firmware without resetting the application.
This section discusses the Live Firmware Update (LFU) and the hardware features present on the device to
support LFU.
3.13.1 LFU Background
End equipment like Server Power Supply (PSU) are high availability systems that need to have minimum
downtime, even during firmware upgrades. Firmware upgrades are essential to add additional functionality,
enhance performance and fix software bugs/vulnerabilities. LFU helps update firmware while the application
is running, thus eliminating downtime (with respect to critical real-time interrupts) and also providing a more
cost-effective alternative compared to manually updating firmware.
LFU has traditionally been implemented in the C2000 family of MCUs using software-only techniques. This
impacts LFU switchover time, which is the time to switchover to new firmware once the transition has begun.
User application code initiates this transition, typically by jumping to an entry point in the new firmware. There,
a compiler provided initialization routine specific to LFU is called. This initializes user-specified data variables.
When execution arrives in main() of the new application, user application code performs minimal initialization to
get the new application running.
3.13.2 LFU Switchover Steps
A simplified representation of the LFU switchover is shown in Figure 3-16, and is described in the following
steps:
1. In typical systems, a host – typically a PC or another MCU, will initiate LFU (depicted as LFU Request) on
the application MCU (in this case, the C2000 MCU) that is executing the real-time control application. This
initiates the Flash Program sequence in the application MCU. This runs as a background process even as
the application MCU continues executing firmware (depicted as Firmware - 1).
2. Since the compiler may move existing PIE vectors and function pointers to new locations between firmware
versions, or PIE vectors or function pointers could get added or removed between firmware versions, user
application code needs to manage these properly and efficiently during LFU. In the absence of Flash

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remapping (where different Flash memory banks can be mapped to the same address), PIE vector table
remapping, that is “swapping” and RAM memory block swapping are features supported on the device.
Without swapping, user application code would need to individually update each PIE vector and each
function pointer, adding valuable cycles to the LFU switchover time. With swapping, prior to LFU switchover,
user application code can populate a different PIE vector table (depicted as PIE Swap Memory Update) and
a different LS RAM region (depicted as LSx Swap Memory Update).
3. When complete, at a suitable time (depicted as LFU Switchover – waiting for appropriate time), user
application code initiates the transition to new firmware. Once the compiler LFU initialization routine
completes and transfers execution to the new application (depicted as Firmware – 2), user application code
needs to perform necessary initialization before the new application can begin running. Since PIE vectors
and function pointers have already been populated in the “swap” locations, all that is required is a PIE vector
table swap and LSx RAM Memory Swap (depicted as PIE Vector Swap, LSx Memory Swap).
LFU switchover ± waiting for PIE vector swap
LFU request appropriate time LSx memory swap

PIE swap LSx swap

Flash program memory update memory update
Compiler LFU
Firmware - 1 Firmware - 2
initialization routine

Figure 3-16. Simplified LFU Representation

3.13.3 Device Features Supporting LFU

The new hardware capabilities implemented in the device to support LFU are:
1. Multi-Bank Flash
2. PIE Vector Table Swap
3. LS0/LS1 RAM Memory Swap

3.13.3.1 Multi-Bank Flash

The device has up to three Flash banks, each of size 128KB. With multiple banks, it is possible to Program/
Erase a bank while other banks are in read mode.
3.13.3.2 PIE Vector Table Swap
The device contains an additional PIE vector table, in addition to the typical PIE vector table that is present.
This allows PIE vector addresses for the new firmware to be populated prior to the LFU switchover. During LFU
switchover, a simple swap operation which activates the PIE vector swap table and deactivates the previously
active PIE vector table is initiated by user application code, and this operation takes just 1 CPU clock cycle. To
initiate the swap, user application code sets LFUConfig.PieVectorSwap = 1. The PIE vector table swap features
are also implemented on a redundant PIE vector table implemented for safety. Therefore, to implement PIE
vector table swap, the sizes of PIE vector memory and redundant PIE vector memory are both doubled.
The changes are summarized in Figure 3-17. In previous devices, PIE vector RAM and redundant PIE vector
RAM are present. In this device, these are duplicated. There are now four physical PIE vector RAM memories
– Block A, Block B, Block C, and Block D. By default, Block A and Block B are active, and are mapped
to addresses 0x0000_0D00-0x0000_0EFF and 0x0100_0D00-0x0100_0EFF respectively. Block C and Block
D are inactive, and are mapped to addresses 0x0100_0900-0x0100_0AFF and 0x0100_0B00-0x0100_0CFF
respectively.
When user application code initiates a PIE vector table swap by setting LFUConfig.PieVectorSwap = 1,
Block C and Block D become active, and are mapped to addresses 0x0000_0D00-0x0000_0EFF and
0x0100_0D00-0x0100_0EFF respectively. Block A and Block B become inactive, and are mapped to addresses
0x0100_0900-0x0100_0AFF and 0x0100_0B00-0x0100_0CFF respectively.

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Thus, note that the active addresses are always 0x0000_0D00-0x0000_0EFF, and 0x0100_0D00-0x0100_0EFF
(for redundancy). The inactive addresses are always 0x0100_0900-0x0100_0AFF, and
0x0100_0B00-0x0100_0CFF (for redundancy). As mentioned above, prior to the LFU switchover, user
application code will need to write to the inactive addresses with the PIE vector locations corresponding to
the new firmware.
The register bit LFUStatus.PieVectorSwap provides the status of Pie Vector Swap.
Writes to addresses 0x0000_0D00-0x0000_0EFF will update both the currently active block and its redundant
counterpart. Writes to addresses 0x0100_0900-0x0100_0AFF will update both the currently inactive block and
its redundant counterpart.
Reads from addresses 0x0000_0D00-0x0000_0EFF will issue reads from both addresses
0x0000_0D00-0x0000_0EFF and the redundant counterpart 0x0100_0D00-0x0100_0EFF. The read values will
be compared, and any data mismatches will generate the same error response as that of the existing PIE vector
fetch mismatch (refer to PIEVERRADDR). On the other hand, a read from or write to the redundant PIE vector
RAM (0x0100_0D00-0x0100_0EFF or 0x0100_0B00-0x0100_0CFF) will impact only the redundant PIE vector
RAM.
Configuration without Configuration before
Configuration after swap
swap capability initiating swap

Redundant Redundant Redundant

PIE vector ram PIE vector ram PIE vector ram PIE vector ram PIE vector ram PIE vector ram
0x0000_0D00 0x0100_0D00 0x0000_0D00 0x0100_0D00 0x0100_0900 0x0100_0B00

Redundant Redundant Redundant

PIE-1 PIE-1 PIE-1
PIE-1 PIE-1 PIE-1
(Block A) (Block A) (Block A)
(Block B) (Block B) (Block B)

0x0000_0EFF 0x0100_0EFF 0x0000_0EFF 0x0100_0EFF 0x0100_0AFF 0x0100_0CFF

0x0100_0900 0x0100_0B00 0x0000_0D00 0x0100_0D00

Redundant Redundant
PIE-2 PIE-2
Inactive vector table which PIE-2 PIE-2
(Block C) (Block C)
can be swapped (Block D) (Block D)

0x0100_0AFF 0x0100_0CFF 0x0000_0EFF 0x0100_0EFF

Active vector table

PIE-1 and PIE-2 are two halves of the same physical memory
Redundant PIE-1 and Redundant PIE-2 are two halved of the same physical memory

Figure 3-17. PIE Vector Table Swap

3.13.3.3 LS0/LS1 RAM Memory Swap

Similar to PIE Vector Table Swap, LS0 and LS1 physical RAM memory blocks can also be swapped. The
memory architecture is similar to PIE vector table swap, and is shown in Figure 3-18. By default, physical Block
1 is assigned to addresses 0x8000-0x87FF (that is, the address range for LS0), and physical Block 2 is assigned
to addresses 0x8800-0x8FFF (that is, the address range for LS1). By configuring LFUConfig.LS01Swap
= 1, user application code can execute a swap, where physical Block 2 is now assigned to addresses
0x8000-0x87FF (that is, the address range for LS0), and physical Block 1 is now assigned to addresses
0x8800-0x8FFF (that is, the address range for LS1).
If physical memory Block 1 contains function pointers for the current firmware, the same relative locations in
physical memory Block 2 can be populated with function pointers for the new firmware prior to LFU switchover.
During LFU switchover, a simple swap operation is initiated by user application code, and this operation takes

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just 1 CPU clock cycle. This allows user application code to always have function pointers in LS0, yet have two
different physical blocks that can map to the LS0 address range.
For example, if current firmware contains 10 function pointers present at the start of Block 1 (LS0 address
space). If the new firmware contains the same 10 function pointers that now need to be updated, user
application code would place these at the start of Block 2 (LS1 address space) prior to LFU switchover. During
LFU switchover, user application code would execute a LS0/LS1 RAM memory swap, where the physical RAM
block previously mapped to the LS1 address space would now be mapped to the LS0 address space, and hence
can be used seamlessly for function pointer addressing for the new firmware.
The register bit LFUStatus.LS01Swap provides the status of LS0/LS1 RAM memory swap.
Logical Normal Mode Swap Mode
Address
0x8000 0x8000
0x0000_8000

Block-1 Block-2
LS0 LS0

0x87FF 0x87FF
0x8800 0x8800

Block-2 Block-1
LS1 LS1

0x0000_8FFF
0x8FFF 0x8FFF

Figure 3-18. LS0/LS1 RAM Memory Swap

Additional points pertaining to LS0/LS1 RAM memory swap are described below:
1. LFU registers can be accessed from both CPU and CLA.
2. Only LS0 and LS1 blocks can be swapped. LS2 to LS7 blocks cannot be swapped.
3. LS0 and LS1 blocks have ECC protection. Address ECC is computed based on the physical address and
hence it will not change based on the memory swap.
4. A number of LSx RAM registers are available to the user application code
to configure options such as master select (LSxMSEL.MSEL_LS0, LSxMSEL.MSEL_LS1),
fetch protect (LSxACCPROT0.FETCHPROT_LS0, LSxACCPROT0.FETCHPROT_LS1), write protect
(LSxACCPROT0.CPUWRPROT_LS0, LSxACCPROT0.CPUWRPROT_LS1), CLA program memory
LSxCLAPGM.CLAPGM_LS0, LSxCLAPGM.CLAPGM_LS1). These register bits indicate the status of the
memory block that is deemed as LS0 (CPU address 0x8000 to 0x87FF) and LS1 (CPU address 0x8800 to
0x8FFF) at any point of time. When a LS0/LS1 RAM memory swap occurs, the corresponding control/status
bits will also automatically swap.
5. It is recommended to service all pending errors (access violation, ECC, parity) associated with memory
before initiating a LS0/LS1 RAM memory swap.
6. LS0/LS1 RAM memory swap shall be initiated only after completion of RAM initialization for both LS0 and
LS1 memories (LSxINITDONE.INITDONE_LS0 = 1 and LSxINITDONE.INITDONE_LS1 = 1).
7. LS0/LS1 RAM memory swap shall not be initiated when RAM-test (LSxTEST.TEST_LS0 = 1 or
LSxTEST.TEST_LS1 = 1) is in progress for LS0 or LS1 blocks.
8. With DCSM security on the device, in general, LS0 and LS1 RAM blocks can be assigned to different
security zones. However, with LS0/LS1 RAM memory swaps, different physical RAM blocks can get mapped
to the same address space. Application software shall therefore ensure that both LS0 and LS1 have the
same security settings (for example, zone, EXE protection), if there is a plan to implement LS0/LS1 RAM
memory swap. Hardware logic is implemented on the device to prevent swap of LS0 and LS1 if the blocks
have different security configurations.
9. In order to prevent security vulnerabilities, LS0/LS1 RAM memory swap will not be allowed if it is initiated by
code from a different zone. For example, (i) If LS0 and LS1 are part of Zone1, swap will not be allowed if
code that initiates the swap resides in Zone2 or unsecure zone; (ii) If LS0 and LS1 are part of Zone2, swap

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will not be allowed if code that initiates the swap resides in Zone1 or unsecure zone; (iii) If LS0 and LS1 are
part of the same zone which is unsecure, swap will be allowed in all cases irrespective of where the code
that initiates the swap resides; (iv) if LS0 and LS1 are part of the same zone and it is unlocked, the swap can
be initiated from code residing anywhere (including from the debugger).
10. Once swap is initiated, it will happen in the next cycle itself, subject to it meeting the security
requirements mentioned above. After initiation of a swap, application software shall check if the swap
was correctly configured by checking the LFUStatus.LS01Swap status register. Consistency between
LFUStatus.LS01Swap and LFUConfig.LS01Swap helps determine if the swap was correctly configured. If
LFUStatus.LS01Swap does not match LFUConfig.LS01Swap, LFUConfig.LS01Swap needs to be cleared by
user application code.
11. Since the logical address accessed by BGCRC will change with LS0/LS1 RAM memory swap, the computed
CRC values for these memories need to be updated after the LS0/LS1 RAM memory swap.

3.13.3.3.1 Applicability to CLA LFU

The device does not support a swap table for the CLA task vectors (MVECTs). CLA LFU is implemented typically
on the CPU side, where the MVECTs are updated sequentially at an appropriate time. The techniques for when
to update the MVECTs will be described in the LFU system reference design guide, but it should be noted here
that the approach is different from the CPU PIE vector table case, where a simple single cycle swap achieves
the switch to the new PIE vector table.
In order for the LS0/LS1 RAM memory swap feature to be useful for CLA LFU switchover, two conditions need to
be satisfied:
• CLA code has to fit into a single LSx block. The MVECT table contains CLA task vectors, whose addresses
correspond to locations in the LSx block. For example, if the current firmware CLA code is present in LS0,
MVECTs will point to various locations in LS0. If the new firmware CLA code is present in LS1, MVECTs will
point to various locations in LS1.
• When switching over from current to new firmware, the MVECTs will need to be updated, unless they reside
at the same relative location in both LS0 and LS1. If that is the case, then simply swapping LS0/LS1 RAM
memory blocks will effectively update the MVECT table, without the need to sequentially update the MVECTs.

3.13.4 LFU Switchover

After the new firmware has been programmed to Flash, user application code will need to determine when it is
appropriate to switchover to the new firmware. The techniques to determine this differ between real-time critical
firmware running on the CPU and CLA, and these techniques are beyond the scope of this document. They will
be described in detail in the LFU system reference design guide.
The device supports two register bits that can be set or reset to indicate that LFU switchover is in progress on
the CPU (LFUConfig.LFU_CPU) and CLA (LFUConfig.LFU_CLA1). These bits do not impact any hardware logic
on the device. For example, LFUConfig.LFU_CPU can be set by user application code at the start of switchover,
and then tested in the initialization code in main(). This can enable only LFU switchover specific initialization
to be performed (for example, PIE vector table swap, LS0/LS1 RAM memory swap), while bypassing all other
initialization that typically happens after a device reset.
3.13.5 LFU Resources
The following are additional LFU resources available.
• Live Firmware Update Without Device Reset on C2000™ MCUs User's Guide
• Live Firmware Update With Device Reset on C2000™ MCUs User's Guide
• Live Firmware Update Reference Design with C2000™ Real-Time MCUs

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3.14 System Control Register Configuration Restrictions

Memory-mapped registers in the System Control operate on INTOSC1 clock domain; hence, any CPU writes
to these registers requires a delay between subsequent writes otherwise a second write can be lost. The
application needs to take this into consideration and add a delay in terms of the number of NOP instructions
after every write to these registers that are mentioned in Table 3-15. The formula to compute delay between
subsequent writes:
Delay (in SYSCLK cycles) = 3 × (FSYSCLK ÷ FINTOSC1) + 9
For Example - For SYSCLK = 100200 MHz
Delay (in SYSCLK cycles) = 3 × (100 MHz ÷ 10 MHz) + 9 = 39 SYSCLK cycles
Table 3-15. System Control Registers Impacted
Registers requiring delay after every write
CLBCLKCTL
PERCLKDIVSEL
SYSCLKDIVSEL
SYSPLLCTL1
SYSPLLMULT
WDCR
XCLKOUTDIVSEL
XTALCR
CLKSRCCTL1
CLKSRCCTL2
CLKSRCCTL3
CPU1TMR2CTL (TMR2CLKCTL)

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3.15 Software
3.15.1 INTERRUPT Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/interrupt
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.1.1 External Interrupts (ExternalInterrupt)
FILE: interrupt_ex1_external.c
This program sets up GPIO0 as XINT1 and GPIO1 as XINT2. Two other GPIO signals are used to trigger the
interrupt (GPIO10 triggers XINT1 and GPIO11 triggers XINT2). The user is required to externally connect these
signals for the program to work properly.
XINT1 input is synced to SYSCLKOUT.
XINT2 has a long qualification - 6 samples at 510*SYSCLKOUT each.
GPIO16 will go high outside of the interrupts and low within the interrupts. This signal can be monitored on a
scope.
Each interrupt is fired in sequence - XINT1 first and then XINT2
External Connections
• Connect GPIO10 to GPIO0. GPIO0 will be assigned to XINT1
• Connect GPIO11 to GPIO1. GPIO1 will be assigned to XINT2
Monitor GPIO16 with an oscilloscope. GPIO16 will be high outside of the ISRs and low within each ISR.
Watch Variables
• xint1Count for the number of times through XINT1 interrupt
• xint2Count for the number of times through XINT2 interrupt
• loopCount for the number of times through the idle loop
3.15.1.2 Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
FILE: interrupt_ex2_with_i2c_sci_spi_loopback.c
This program is used to demonstrate how to handle multiple interrupts when using multiple communication
peripherals like I2C, SCI & SPI Digital Loopback all in a single example. The data transfers would be done with
FIFO Interrupts.
It uses the internal loopback test mode of these modules. Both the TX and RX FIFOs and their interrupts are
used. Other than boot mode pin configuration, no other hardware configuration is required.
A stream of data is sent and then compared to the received stream. The sent data looks like this for I2C and
SCI:
0000 0001
0001 0002
0002 0003
....
00FE 00FF
00FF 0000
etc..
The sent data looks like this for SPI:
0000 0001
0001 0002
0002 0003
....
FFFE FFFF

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FFFF 0000
etc..
This pattern is repeated forever.
External Connections
• None
Watch Variables
• sDatai2cA - Data to send through I2C
• rDatai2cA - Received I2C data
• rDataPoint - Used to keep track of the last position in the receive I2C stream for error checking
• sDataspiA - Data to send through SPI
• rDataspiA - Received SPI data
• rDataPointspiA - Used to keep track of the last position in the receive SPI stream for error checking
• sDatasciA - SCI Data being sent
• rDatasciA - SCI Data received
• rDataPointA - Keep track of where we are in the SCI data stream. This is used to check the incoming data
3.15.1.3 CPU Timer Interrupt Software Prioritization
FILE: interrupt_ex3_sw_prioritization.c
This examples demonstrates the software prioritization of interrupts through CPU Timer Interrupts. Software
prioritization of interrupts is achieved by enabling interrupt nesting.
In this device, hardware priorities for CPU Timer 0, 1 and 2 are set as timer 0 being highest priority and timer 2
being lowest priority. This example configures CPU Timer0, 1, and 2 priority in software with timer 2 priority being
highest and timer 0 being lowest in software and prints a trace for the order of execution.
For most applications, the hardware prioritizing of the interrupts is sufficient. For applications that need custom
prioritizing, this example illustrates how this can be done through software.User specific priorities can be
configured in sw_prioritized_isr_level.h header file.
To enable interrupt nesting, following sequence needs to followed in ISRs. Step 1: Set the global priority: Modify
the IER register to allow CPU interrupts with a higher user priority to be serviced. Note: at this time IER has
already been saved on the stack. Step 2: Set the group priority: (optional) Modify the appropriate PIEIERx
register to allow group interrupts with a higher user set priority to be serviced. Do NOT clear PIEIER register bits
from another group other than that being serviced by this ISR. Doing so can cause erroneous interrupts to occur.
Step 3: Enable interrupts: There are three steps to do this: a. Clear the PIEACK bits b. Wait at least one cycle c.
Clear the INTM bit. Step 4: Run the main part of the ISR Step 5: Set INTM to disable interrupts. Step 6: Restore
PIEIERx (optional depending on step 2) Step 7: Return from ISR
Refer to below link on more details on Interrupt nesting in C28x devices: <C2000Ware>.html
External Connections
• None
Watch Variables
• traceISR - shows the order in which ISRs are executed.
3.15.1.4 EPWM Real-Time Interrupt
FILE: interrupt_ex4_epwm_realtime_interrupt.c
This example configures the ePWM1 Timer and increments a counter each time the ISR is executed. ePWM
interrupt can be configured as time critical to demonstrate real-time mode functionality and real-time interrupt
capability.
The example uses 2 LEDs - LED1 is toggled in the main loop and LED2 is toggled in the EPWM Timer
Interrupt. FREE_SOFT bits and DBGIER.INT3 bit must be set to enable ePWM1 interrupt to be time critical and
operational in real time mode after halt command

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How to run the example?

• Add the watch variables as mentioned below and enable Continuous Refresh.
• Enable real-time mode (Run->Advanced->Enable Silicon Real-time Mode)
• Initially, the DBGIER register is set to 0 and the EPWM emulation mode is set to
EPWM_EMULATION_STOP_AFTER_NEXT_TB (FREE_SOFT = 0)
• When the application is running, you will find both LEDs toggling and the watch variables
EPwm1TimerIntCount, EPwm1Regs.TBCTR getting updated.
• When the application is halted, both LEDs stop toggling and the watch variables remain constant. EPWM
counter is stopped on debugger halt.
• To enable EPWM counter run during debugger halt, set emulation mode as
EPWM_EMULATION_FREE_RUN (FREE_SOFT = 2). You will find EPwm1Regs.TBCTR is running, but
EPwm1TimerIntCount remains constant. This means, the EPWM counter is running, but the ISRs are not
getting serviced.
• To enable real-time interrupts, set DBGIER.INT3 = 1 (EPWM1 interrupt is part of PIE Group 3). You will
find that the EPwm1TimerIntCount is incrementing and the LED starts toggling. The EPWM ISR is getting
serviced even during a debugger halt.
For more details, watch this video : C2000 Real-Time Features
External Connections
• None
Watch Variables
• EPwm1TimerIntCount - EPWM1 ISR counter
• EPwm1Regs.TBCTR.TBCTR - EPWM1 Time Base counter
• EPwm1Regs.TBCTL.FREE_SOFT - Set this to 2 to enable free run
• DBGIER.INT3 - Set to 1 to enable real time interrupt
3.15.2 SYSCTL Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/sysctl
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.2.1 Missing clock detection (MCD)
FILE: sysctl_ex1_missing_clock_detection.c
This example demonstrates the missing clock detection functionality and the way to handle it. Once the MCD is
simulated by disconnecting the OSCCLK to the MCD module an NMI would be generated. This NMI determines
that an MCD was generated due to a clock failure which is handled in the ISR.
Before an MCD the clock frequency would be as per device initialization (120Mhz). Post MCD the frequency
would move to 10Mhz or INTOSC1.
The example also shows how we can lock the PLL after missing clock, detection, by first explicitly switching the
clock source to INTOSC1, resetting the missing clock detect circuit and then re-locking the PLL. Post a re-lock
the clock frequency would be 120Mhz but using the INTOSC1 as clock source.
External Connections
• None.
Watch Variables
• fail - Indicates that a missing clock was either not detected or was not handled correctly.
• mcd_clkfail_isr - Indicates that the missing clock failure caused an NMI to be triggered and called an the ISR
to handle it.
• mcd_detect - Indicates that a missing clock was detected.
• result - Status of a successful handling of missing clock detection

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3.15.2.2 XCLKOUT (External Clock Output) Configuration

FILE: sysctl_ex2_xclkout_config.c
This example demonstrates how to configure the XCLKOUT pin for observing internal clocks through an external
pin, for debugging and testing purposes.
In this example, we are using INTOSC1 as the XCLKOUT clock source and configuring the divider as 8.
Expected frequency of XCLKOUT = (INTOSC1 freq)/8 = 10/8 = 1.25MHz
View the XCLKOUT on GPIO16 using an oscilloscope.
3.15.3 TIMER Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/timer
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.3.1 CPU Timers
FILE: timer_ex1_cputimers.c
This example configures CPU Timer0, 1, and 2 and increments a counter each time the timer asserts an
interrupt.
External Connections
• None
Watch Variables
• cpuTimer0IntCount
• cpuTimer1IntCount
• cpuTimer2IntCount
3.15.4 LPM Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/lpm
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.4.1 Low Power Modes: Device Idle Mode and Wakeup using GPIO
FILE: lpm_ex1_idlewake_gpio.c
This example puts the device into IDLE mode and then wakes up the device from IDLE using XINT1 which
triggers on a falling edge of GPIO0.
The GPIO0 pin must be pulled from high to low by an external agent for wakeup. GPIO0 is configured as an
XINT1 pin to trigger an XINT1 interrupt upon detection of a falling edge.
Initially, pull GPIO0 high externally. To wake device from IDLE mode by triggering an XINT1 interrupt, pull GPIO0
low (falling edge). The wakeup process begins as soon as GPIO0 is held low for the time indicated in the device
datasheet.
GPIO1 is pulled high before entering the IDLE mode and is pulled low when in the external interrupt ISR.
External Connections
• GPIO0 needs to be pulled low to wake up the device.
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.4.2 Low Power Modes: Device Idle Mode and Wakeup using Watchdog
FILE: lpm_ex2_idlewake_watchdog.c
This example puts the device into IDLE mode and then wakes up the device from IDLE using watchdog timer.

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The device wakes up from the IDLE mode when the watchdog timer overflows, triggering an interrupt. A pre
scalar is set for the watchdog timer to change the counter overflow time.
GPIO1 is pulled high before entering the IDLE mode and is pulled low when in the wakeup ISR.
External Connections
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.4.3 Low Power Modes: Device Standby Mode and Wakeup using GPIO
FILE: lpm_ex3_standbywake_gpio.c
This example puts the device into STANDBY mode. If the lowest possible current consumption in STANDBY
mode is desired, the JTAG connector must be removed from the device board while the device is in STANDBY
mode.
This example puts the device into STANDBY mode and then wakes up the device from STANDBY using an LPM
wakeup pin.
The pin GPIO0 is configured as the LPM wakeup pin to trigger a WAKEINT interrupt upon detection of a low
pulse. Initially, pull GPIO0 high externally. To wake device from STANDBY mode, pull GPIO0 low for at least
(2+QUALSTDBY), OSCLKS, then pull it high again.
The example then wakes up the device from STANDBY using GPIO0. GPIO0 wakes the device from STANDBY
mode when a low pulse (signal goes high->low->high)is detected on the pin. This pin must be pulsed by an
external agent for wakeup.
GPIO1 is pulled high before entering the STANDBY mode and is pulled low when in the wakeup ISR.
External Connections
• GPIO0 needs to be pulled low to wake up the device.
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.4.4 Low Power Modes: Device Standby Mode and Wakeup using Watchdog
FILE: lpm_ex4_standbywake_watchdog.c
This example puts the device into STANDBY mode. If the lowest possible current consumption in STANDBY
mode is desired, the JTAG connector must be removed from the device board while the device is in STANDBY
mode.
This example puts the device into STANDBY mode then wakes up the device from STANDBY using watchdog
timer.
The device wakes up from the STANDBY mode when the watchdog timer overflows triggering an interrupt. In the
ISR, the GPIO1 is pulled low. the GPIO1 is toggled to indicate the device is out of STANDBY mode. A pre scalar
is set for the watchdog timer to change the counter overflow time.
GPIO1 is pulled high before entering the STANDBY mode and is pulled low when in the wakeup ISR.
External Connections
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.4.5 Low Power Modes: Halt Mode and Wakeup using GPIO
FILE: lpm_ex5_haltwake_gpio.c
This example puts the device into HALT mode. If the lowest possible current consumption in HALT mode is
desired, the JTAG connector must be removed from the device board while the device is in HALT mode.
For applications that require minimal power consumption during HALT mode, application software should power
off the XTAL prior to entering HALT by setting the XTALCR.OSCOFF bit or by using the driverlib function
SysCtl_turnOffOsc(SYSCTL_OSCSRC_XTAL);. If the OSCCLK source is configured to be XTAL, the application
should first switch the OSSCLK source to INTOSC1 or INTOSC2 prior to setting XTALCR.OSCOFF.

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This example puts the device into HALT mode and then wakes up the device from HALT using an LPM wakeup
pin.
The pin GPIO0 is configured as the LPM wakeup pin to trigger a WAKEINT interrupt upon detection of a low
pulse.The GPIO0 pin must be pulled from high to low by an external agent for wakeup.
GPIO1 is pulled high before entering the STANDBY mode and is pulled low when in the wakeup ISR.
External Connections
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.4.6 Low Power Modes: Halt Mode and Wakeup
FILE: lpm_ex6_haltwake_gpio_watchdog.c
This example puts the device into HALT mode. If the lowest possible current consumption in HALT mode is
desired, the JTAG connector must be removed from the device board while the device is in HALT mode.
For applications that require minimal power consumption during HALT mode, application software should power
off the XTAL prior to entering HALT by setting the XTALCR.OSCOFF bit or by using the driverlib function
SysCtl_turnOffOsc(SYSCTL_OSCSRC_XTAL);. If the OSCCLK source is configured to be XTAL, the application
should first switch the OSSCLK source to INTOSC1 or INTOSC2 prior to setting XTALCR.OSCOFF.
This example puts the device into HALT mode and then wakes up the device from HALT using an LPM wakeup
pin.
The pin GPIO0 is configured as the LPM wakeup pin to trigger a WAKEINT interrupt upon detection of a low
pulse.The GPIO0 pin must be pulled from high to low by an external agent for wakeup.
In this example, the watchdog timer is clocked, and is configured to produce watchdog reset as a timeout
mechanism.
GPIO1 is pulled high before entering the STANDBY mode and is pulled low when in the wakeup ISR.
External Connections
• On device wakeup, the GPIO1 will be low and LED1 will start blinking
3.15.5 MEMCFG Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/memcfg
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.5.1 Correctable & Uncorrectable Memory Error Handling
FILE: memcfg_ex1_error_handling.c
This example demonstrates error handling in case of various erroneous memory read/write operations.
Error handling in case of CPU read/write violations, correctable & uncorrectable memory errors has been
demonstrated.
Test functions used in this example
• generateMasterCPUWrViolation -
– This test configures Memconfig to block CPU writes to GS0 RAM. A write attempt to this memory location
by CPU causes RAM_ACC_VIOL Interrupt
• generateECCMemCorrError
– This test induces single bit ECC error in LS6 RAM. A read from the corrupted memory location causes
INT_RAM_CORR_ERR Interrupt
• generateECCMemUncorrError
– This test induces double bit ECC error in LS7 RAM. A read from the corrupted memory location causes
NMI
• forceNonMasterDMAReadViolation

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– This forces a DMA access violation using MemCfg_forceViolationInterrupt API. This casuses
RAM_ACC_VIOL Interrupt
External Connections
• None
Watch Variables
• testStatusGlobal - Equivalent to TEST_PASS if test finished correctly, else the value is set to TEST_FAIL
• errCountGlobal - Error counter
3.15.6 WATCHDOG Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/watchdog
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.6.1 Watchdog
FILE: watchdog_ex1_service.c
This example shows how to service the watchdog or generate a wakeup interrupt using the watchdog. By default
the example generates a Wake interrupt. To service the watchdog and not generate the interrupt, uncomment
the SysCtl_serviceWatchdog() line in the main for loop.
External Connections
• None.
Watch Variables
• wakeCount - The number of times entered into the watchdog ISR
• loopCount - The number of loops performed while not in ISR

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3.16 System Control Registers

3.16.1 SYSCTRL Base Address Table
Table 3-16. SYSCTRL Base Address Table
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 DMA HIC CLA
Instance Structure Protected

CPUTIMER_REG
CpuTimer0Regs CPUTIMER0_BASE 0x0000_0C00 YES - - - -
S
CPUTIMER_REG
CpuTimer1Regs CPUTIMER1_BASE 0x0000_0C08 YES - - - -
S
CPUTIMER_REG
CpuTimer2Regs CPUTIMER2_BASE 0x0000_0C10 YES - - - -
S
PIE_CTRL_REG
PieCtrlRegs PIECTRL_BASE 0x0000_0CE0 YES - - - -
S
PIE_VECT_TABL
PieVectTable PIEVECTTABLE_BASE 0x0000_0D00 YES - - - -
E
WdRegs WD_REGS WD_BASE 0x0000_7000 YES - - - YES
NMI_INTRUPT_R
NmiIntruptRegs NMI_BASE 0x0000_7060 YES - - - YES
EGS
XintRegs XINT_REGS XINT_BASE 0x0000_7070 YES - - - YES
SYNC_SOC_RE
SyncSocRegs SYNCSOC_BASE 0x0000_7940 YES - - - YES
GS
DMA_CLA_SRC_
DmaClaSrcSelRegs DMACLASRCSEL_BASE 0x0000_7980 YES - - - YES
SEL_REGS
LfuRegs LFU_REGS LFU_BASE 0x0000_7FE0 YES - - YES YES
DEV_CFG_REG
DevCfgRegs DEVCFG_BASE 0x0005_D000 YES - - - YES
S
ClkCfgRegs CLK_CFG_REGS CLKCFG_BASE 0x0005_D200 YES - - - YES
CpuSysRegs CPU_SYS_REGS CPUSYS_BASE 0x0005_D300 YES - - - YES
SYS_STATUS_R
SysStatusRegs SYSSTAT_BASE 0x0005_D400 YES - - - YES
EGS
PERIPH_AC_RE
PeriphAcRegs PERIPHAC_BASE 0x0005_D500 YES - - - YES
GS
MEM_CFG_REG
MemCfgRegs MEMCFG_BASE 0x0005_F400 YES - - - YES
S
ACCESS_PROT ACCESSPROTECTION_B
AccessProtectionRegs 0x0005_F500 YES - - - YES
ECTION_REGS ASE
MEMORY_ERRO
MemoryErrorRegs MEMORYERROR_BASE 0x0005_F540 YES - - - YES
R_REGS
TEST_ERROR_R
TestErrorRegs TESTERROR_BASE 0x0005_F590 YES - - - YES
EGS
UidRegs UID_REGS UID_BASE 0x0007_0200 YES - - - -

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3.16.2 ACCESS_PROTECTION_REGS Registers

Table 3-17 lists the memory-mapped registers for the ACCESS_PROTECTION_REGS registers. All register
offset addresses not listed in Table 3-17 should be considered as reserved locations and the register contents
should not be modified.
Table 3-17. ACCESS_PROTECTION_REGS Registers
Offset Acronym Register Name Write Protection Section
0h NMAVFLG Non-Master Access Violation Flag Register Go
2h NMAVSET Non-Master Access Violation Flag Set Register EALLOW Go
4h NMAVCLR Non-Master Access Violation Flag Clear Register EALLOW Go
6h NMAVINTEN Non-Master Access Violation Interrupt Enable EALLOW Go
Register
8h NMCPURDAVADDR Non-Master CPU Read Access Violation Address Go
Ah NMCPUWRAVADDR Non-Master CPU Write Access Violation Address Go
Ch NMCPUFAVADDR Non-Master CPU Fetch Access Violation Address Go
Eh NMDMAWRAVADDR Non-Master DMA Write Access Violation Address Go
10h NMCLA1RDAVADDR Non-Master CLA1 Read Access Violation Go
Address
12h NMCLA1WRAVADDR Non-Master CLA1 Write Access Violation Address Go
14h NMCLA1FAVADDR Non-Master CLA1 Fetch Access Violation Go
Address
1Ch NMDMARDAVADDR Non-Master DMA Read Access Violation Address Go
20h MAVFLG Master Access Violation Flag Register Go
22h MAVSET Master Access Violation Flag Set Register EALLOW Go
24h MAVCLR Master Access Violation Flag Clear Register EALLOW Go
26h MAVINTEN Master Access Violation Interrupt Enable Register EALLOW Go
28h MCPUFAVADDR Master CPU Fetch Access Violation Address Go
2Ah MCPUWRAVADDR Master CPU Write Access Violation Address Go
2Ch MDMAWRAVADDR Master DMA Write Access Violation Address Go
2Eh + MHICWRAVADDR_y Master HIC Write Access Violation Address Go
formula
3Ch NMHICRDAVADDR Non-Master HIC Read Access Violation Address Go
3Eh NMHICWRAVADDR Non-Master HIC Write Access Violation Address Go

Complex bit access types are encoded to fit into small table cells. Table 3-18 shows the codes that are used for
access types in this section.
Table 3-18. ACCESS_PROTECTION_REGS Access
Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value

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Table 3-18. ACCESS_PROTECTION_REGS Access

Type Codes (continued)
Access Type Code Description
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.2.1 NMAVFLG Register (Offset = 0h) [Reset = 0h]

NMAVFLG is shown in Figure 3-19 and described in Table 3-19.
Return to the Summary Table.
Non-Master Access Violation Flag Register
Figure 3-19. NMAVFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED HICWRITE HICREAD DMAREAD RESERVED RESERVED
R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-19. NMAVFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-13 RESERVED R 0h Reserved
12 HICWRITE R 0h Non Master HIC Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
11 HICREAD R 0h Non Master HIC Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
10 DMAREAD R 0h Non Master DMA Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
9 RESERVED R 0h Reserved
8 RESERVED R 0h Reserved
7 RESERVED R 0h Reserved
6 CLA1FETCH R 0h Non Master CLA1 Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
5 CLA1WRITE R 0h Non Master CLA1 Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
4 CLA1READ R 0h Non Master CLA1 Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

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Table 3-19. NMAVFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
3 DMAWRITE R 0h Non Master DMA Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
2 CPUFETCH R 0h Non Master CPU Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
1 CPUWRITE R 0h Non Master CPU Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
0 CPUREAD R 0h Non Master CPU Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

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3.16.2.2 NMAVSET Register (Offset = 2h) [Reset = 0h]

NMAVSET is shown in Figure 3-20 and described in Table 3-20.
Return to the Summary Table.
Non-Master Access Violation Flag Set Register
Figure 3-20. NMAVSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED HICWRITE HICREAD DMAREAD RESERVED RESERVED
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-20. NMAVSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-13 RESERVED R 0h Reserved
12 HICWRITE R-0/W1S 0h 0: No action.
1: HIC Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
11 HICREAD R-0/W1S 0h 0: No action.
1: HIC Read Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
10 DMAREAD R-0/W1S 0h 0: No action.
1: DMA Read Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R-0/W1S 0h Reserved
6 CLA1FETCH R-0/W1S 0h 0: No action.
1: CLA1 Fetch Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
5 CLA1WRITE R-0/W1S 0h 0: No action.
1: CLA1 Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
4 CLA1READ R-0/W1S 0h 0: No action.
1: CLA1 Read Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn

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Table 3-20. NMAVSET Register Field Descriptions (continued)

Bit Field Type Reset Description
3 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
2 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
0 CPUREAD R-0/W1S 0h 0: No action.
1: CPU Read Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn

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3.16.2.3 NMAVCLR Register (Offset = 4h) [Reset = 0h]

NMAVCLR is shown in Figure 3-21 and described in Table 3-21.
Return to the Summary Table.
Non-Master Access Violation Flag Clear Register
Figure 3-21. NMAVCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED HICWRITE HICREAD DMAREAD RESERVED RESERVED
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-21. NMAVCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-13 RESERVED R 0h Reserved
12 HICWRITE R-0/W1S 0h 0: No action.
1: HIC Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
11 HICREAD R-0/W1S 0h 0: No action.
1: HIC Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
10 DMAREAD R-0/W1S 0h 0: No action.
1: DMA Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R-0/W1S 0h Reserved
6 CLA1FETCH R-0/W1S 0h 0: No action.
1: CLA1 Fetch Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
5 CLA1WRITE R-0/W1S 0h 0: No action.
1: CLA1 Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
4 CLA1READ R-0/W1S 0h 0: No action.
1: CLA1 Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn

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Table 3-21. NMAVCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
2 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
0 CPUREAD R-0/W1S 0h 0: No action.
1: CPU Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn

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3.16.2.4 NMAVINTEN Register (Offset = 6h) [Reset = 0h]

NMAVINTEN is shown in Figure 3-22 and described in Table 3-22.
Return to the Summary Table.
Non-Master Access Violation Interrupt Enable Register
Figure 3-22. NMAVINTEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED HICWRITE HICREAD DMAREAD RESERVED RESERVED
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-22. NMAVINTEN Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-13 RESERVED R 0h Reserved
12 HICWRITE R/W 0h 0: HIC Non Master Write Access Violation Interrupt is disabled.
1: HIC Non Master Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
11 HICREAD R/W 0h 0: HIC Non Master Read Access Violation Interrupt is disabled.
1: HIC Non Master Read Access Violation Interrupt is enabled.
Reset type: SYSRSn
10 DMAREAD R/W 0h 0: DMA Non Master Read Access Violation Interrupt is disabled.
1: DMA Non Master Read Access Violation Interrupt is enabled.
Reset type: SYSRSn
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 CLA1FETCH R/W 0h 0: CLA1 Non Master Fetch Access Violation Interrupt is disabled.
1: CLA1 Non Master Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn
5 CLA1WRITE R/W 0h 0: CLA1 Non Master Write Access Violation Interrupt is disabled.
1: CLA1 Non Master Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
4 CLA1READ R/W 0h 0: CLA1 Non Master Read Access Violation Interrupt is disabled.
1: CLA1 Non Master Read Access Violation Interrupt is enabled.
Reset type: SYSRSn
3 DMAWRITE R/W 0h 0: DMA Non Master Write Access Violation Interrupt is disabled.
1: DMA Non Master Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
2 CPUFETCH R/W 0h 0: CPU Non Master Fetch Access Violation Interrupt is disabled.
1: CPU Non Master Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn

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Table 3-22. NMAVINTEN Register Field Descriptions (continued)

Bit Field Type Reset Description
1 CPUWRITE R/W 0h 0: CPU Non Master Write Access Violation Interrupt is disabled.
1: CPU Non Master Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
0 CPUREAD R/W 0h 0: CPU Non Master Read Access Violation Interrupt is disabled.
1: CPU Non Master Read Access Violation Interrupt is enabled.
Reset type: SYSRSn

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3.16.2.5 NMCPURDAVADDR Register (Offset = 8h) [Reset = 0h]

NMCPURDAVADDR is shown in Figure 3-23 and described in Table 3-23.
Return to the Summary Table.
Non-Master CPU Read Access Violation Address
Figure 3-23. NMCPURDAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCPURDAVADDR
R-0h

Table 3-23. NMCPURDAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCPURDAVADDR R 0h This register captures the address location for which non master
CPU read access violation occurred.
Reset type: SYSRSn

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3.16.2.6 NMCPUWRAVADDR Register (Offset = Ah) [Reset = 0h]

NMCPUWRAVADDR is shown in Figure 3-24 and described in Table 3-24.
Return to the Summary Table.
Non-Master CPU Write Access Violation Address
Figure 3-24. NMCPUWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCPUWRAVADDR
R-0h

Table 3-24. NMCPUWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCPUWRAVADDR R 0h This register captures the address location for which non master
CPU write access violation occurred.
Reset type: SYSRSn

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3.16.2.7 NMCPUFAVADDR Register (Offset = Ch) [Reset = 0h]

NMCPUFAVADDR is shown in Figure 3-25 and described in Table 3-25.
Return to the Summary Table.
Non-Master CPU Fetch Access Violation Address
Figure 3-25. NMCPUFAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCPUFAVADDR
R-0h

Table 3-25. NMCPUFAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCPUFAVADDR R 0h This register captures the address location for which non master
CPU fetch access violation occurred.
Reset type: SYSRSn

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3.16.2.8 NMDMAWRAVADDR Register (Offset = Eh) [Reset = 0h]

NMDMAWRAVADDR is shown in Figure 3-26 and described in Table 3-26.
Return to the Summary Table.
Non-Master DMA Write Access Violation Address
Figure 3-26. NMDMAWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMDMAWRAVADDR
R-0h

Table 3-26. NMDMAWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMDMAWRAVADDR R 0h This register captures the address location for which non master
DMA write access violation occurred.
Reset type: SYSRSn

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3.16.2.9 NMCLA1RDAVADDR Register (Offset = 10h) [Reset = 0h]

NMCLA1RDAVADDR is shown in Figure 3-27 and described in Table 3-27.
Return to the Summary Table.
Non-Master CLA1 Read Access Violation Address
Figure 3-27. NMCLA1RDAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCLA1RDAVADDR
R-0h

Table 3-27. NMCLA1RDAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCLA1RDAVADDR R 0h This register captures the address location for which non master
CLA1 read access violation occurred.
Reset type: SYSRSn

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3.16.2.10 NMCLA1WRAVADDR Register (Offset = 12h) [Reset = 0h]

NMCLA1WRAVADDR is shown in Figure 3-28 and described in Table 3-28.
Return to the Summary Table.
Non-Master CLA1 Write Access Violation Address
Figure 3-28. NMCLA1WRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCLA1WRAVADDR
R-0h

Table 3-28. NMCLA1WRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCLA1WRAVADDR R 0h This register captures the address location for which non master
CLA1 write access violation occurred.
Reset type: SYSRSn

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3.16.2.11 NMCLA1FAVADDR Register (Offset = 14h) [Reset = 0h]

NMCLA1FAVADDR is shown in Figure 3-29 and described in Table 3-29.
Return to the Summary Table.
Non-Master CLA1 Fetch Access Violation Address
Figure 3-29. NMCLA1FAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCLA1FAVADDR
R-0h

Table 3-29. NMCLA1FAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCLA1FAVADDR R 0h This register captures the address location for which non master
CLA1 fetch access violation occurred.
Reset type: SYSRSn

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3.16.2.12 NMDMARDAVADDR Register (Offset = 1Ch) [Reset = 0h]

NMDMARDAVADDR is shown in Figure 3-30 and described in Table 3-30.
Return to the Summary Table.
Non-Master DMA Read Access Violation Address
Figure 3-30. NMDMARDAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMDMARDAVADDR
R-0h

Table 3-30. NMDMARDAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMDMARDAVADDR R 0h This register captures the address location for which non master
DMA read access violation occurred.
Reset type: SYSRSn

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3.16.2.13 MAVFLG Register (Offset = 20h) [Reset = 0h]

MAVFLG is shown in Figure 3-31 and described in Table 3-31.
Return to the Summary Table.
Master Access Violation Flag Register
Figure 3-31. MAVFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED HICAWRITE DMAWRITE CPUWRITE CPUFETCH
R-0h R-0h R-0h R-0h R-0h

Table 3-31. MAVFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 HICAWRITE R 0h Master HICA Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
2 DMAWRITE R 0h Master DMA Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
1 CPUWRITE R 0h Master CPU Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
0 CPUFETCH R 0h Master CPU Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

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3.16.2.14 MAVSET Register (Offset = 22h) [Reset = 0h]

MAVSET is shown in Figure 3-32 and described in Table 3-32.
Return to the Summary Table.
Master Access Violation Flag Set Register
Figure 3-32. MAVSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED HICAWRITE DMAWRITE CPUWRITE CPUFETCH
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-32. MAVSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 HICAWRITE R-0/W1S 0h 0: No action.
1: HICA Write Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
2 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
0 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn

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3.16.2.15 MAVCLR Register (Offset = 24h) [Reset = 0h]

MAVCLR is shown in Figure 3-33 and described in Table 3-33.
Return to the Summary Table.
Master Access Violation Flag Clear Register
Figure 3-33. MAVCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED HICAWRITE DMAWRITE CPUWRITE CPUFETCH
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-33. MAVCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 HICAWRITE R-0/W1S 0h 0: No action.
1: HICA Write Access Violation Flag in MAVFLG register will be
cleared.
Reset type: SYSRSn
2 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in MAVFLG register will be
cleared.
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in MAVFLG register will be
cleared .
Reset type: SYSRSn
0 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in MAVFLG register will be
cleared.
Reset type: SYSRSn

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3.16.2.16 MAVINTEN Register (Offset = 26h) [Reset = 0h]

MAVINTEN is shown in Figure 3-34 and described in Table 3-34.
Return to the Summary Table.
Master Access Violation Interrupt Enable Register
Figure 3-34. MAVINTEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED HICAWRITE DMAWRITE CPUWRITE CPUFETCH
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-34. MAVINTEN Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 HICAWRITE R/W 0h 0: HICA Write Access Violation Interrupt is disabled.
1: HICA Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
2 DMAWRITE R/W 0h 0: DMA Write Access Violation Interrupt is disabled.
1: DMA Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
1 CPUWRITE R/W 0h 0: CPU Write Access Violation Interrupt is disabled.
1: CPU Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
0 CPUFETCH R/W 0h 0: CPU Fetch Access Violation Interrupt is disabled.
1: CPU Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn

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3.16.2.17 MCPUFAVADDR Register (Offset = 28h) [Reset = 0h]

MCPUFAVADDR is shown in Figure 3-35 and described in Table 3-35.
Return to the Summary Table.
Master CPU Fetch Access Violation Address
Figure 3-35. MCPUFAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCPUFAVADDR
R-0h

Table 3-35. MCPUFAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 MCPUFAVADDR R 0h This register captures the address location for which master CPU
fetch access violation occurred.
Reset type: SYSRSn

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3.16.2.18 MCPUWRAVADDR Register (Offset = 2Ah) [Reset = 0h]

MCPUWRAVADDR is shown in Figure 3-36 and described in Table 3-36.
Return to the Summary Table.
Master CPU Write Access Violation Address
Figure 3-36. MCPUWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCPUWRAVADDR
R-0h

Table 3-36. MCPUWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 MCPUWRAVADDR R 0h This register captures the address location for which master CPU
write access violation occurred.
Reset type: SYSRSn

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3.16.2.19 MDMAWRAVADDR Register (Offset = 2Ch) [Reset = 0h]

MDMAWRAVADDR is shown in Figure 3-37 and described in Table 3-37.
Return to the Summary Table.
Master DMA Write Access Violation Address
Figure 3-37. MDMAWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMAWRAVADDR
R-0h

Table 3-37. MDMAWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 MDMAWRAVADDR R 0h This register captures the address location for which master DMA
write access violation occurred.
Reset type: SYSRSn

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3.16.2.20 MHICWRAVADDR_y Register (Offset = 2Eh + formula) [Reset = 0h]

MHICWRAVADDR_y is shown in Figure 3-38 and described in Table 3-38.
Return to the Summary Table.
Master HIC Write Access Violation Address
Offset = 2Eh + (y * 2h); where y = 0h to 1h
Figure 3-38. MHICWRAVADDR_y Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MHICWRAVADDR
R-0h

Table 3-38. MHICWRAVADDR_y Register Field Descriptions

Bit Field Type Reset Description
31-0 MHICWRAVADDR R 0h This register captures the address location for which master HICA
write access violation occurred.
Reset type: SYSRSn

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3.16.2.21 NMHICRDAVADDR Register (Offset = 3Ch) [Reset = 0h]

NMHICRDAVADDR is shown in Figure 3-39 and described in Table 3-39.
Return to the Summary Table.
Non-Master HIC Read Access Violation Address
Figure 3-39. NMHICRDAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMHICRDAVADDR
R-0h

Table 3-39. NMHICRDAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMHICRDAVADDR R 0h This register captures the address location for which non master HIC
read access violation occurred.
Reset type: SYSRSn

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3.16.2.22 NMHICWRAVADDR Register (Offset = 3Eh) [Reset = 0h]

NMHICWRAVADDR is shown in Figure 3-40 and described in Table 3-40.
Return to the Summary Table.
Non-Master HIC Write Access Violation Address
Figure 3-40. NMHICWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMHICWRAVADDR
R-0h

Table 3-40. NMHICWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMHICWRAVADDR R 0h This register captures the address location for which non master HIC
write access violation occurred.
Reset type: SYSRSn

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3.16.3 CLK_CFG_REGS Registers

Table 3-41 lists the memory-mapped registers for the CLK_CFG_REGS registers. All register offset addresses
not listed in Table 3-41 should be considered as reserved locations and the register contents should not be
modified.
Table 3-41. CLK_CFG_REGS Registers
Offset Acronym Register Name Write Protection Section
2h CLKCFGLOCK1 Lock bit for CLKCFG registers EALLOW Go
8h CLKSRCCTL1 Clock Source Control register-1 EALLOW Go
Ah CLKSRCCTL2 Clock Source Control register-2 EALLOW Go
Ch CLKSRCCTL3 Clock Source Control register-3 EALLOW Go
Eh SYSPLLCTL1 SYSPLL Control register-1 EALLOW Go
14h SYSPLLMULT SYSPLL Multiplier register EALLOW Go
16h SYSPLLSTS SYSPLL Status register Go
22h SYSCLKDIVSEL System Clock Divider Select register EALLOW Go
24h AUXCLKDIVSEL Auxillary Clock Divider Select register EALLOW Go
28h XCLKOUTDIVSEL XCLKOUT Divider Select register EALLOW Go
2Ch LOSPCP Low Speed Clock Source Prescalar EALLOW Go
2Eh MCDCR Missing Clock Detect Control Register EALLOW Go
30h X1CNT 10-bit Counter on X1 Clock Go
32h XTALCR XTAL Control Register EALLOW Go
3Ah XTALCR2 XTAL Control Register for pad init EALLOW Go
3Ch CLKFAILCFG Clock Fail cause Configuration EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-42 shows the codes that are used for
access types in this section.
Table 3-42. CLK_CFG_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1C W Write
1C 1 to clear
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables

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Table 3-42. CLK_CFG_REGS Access Type Codes

(continued)
Access Type Code Description
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.3.1 CLKCFGLOCK1 Register (Offset = 2h) [Reset = 0h]

CLKCFGLOCK1 is shown in Figure 3-41 and described in Table 3-43.
Return to the Summary Table.
Lock bit for CLKCFG registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this
register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always
allowed
Figure 3-41. CLKCFGLOCK1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED XTALCR
R-0-0h R/WSonce-0h

15 14 13 12 11 10 9 8
LOSPCP RESERVED RESERVED AUXCLKDIVSE SYSCLKDIVSE RESERVED RESERVED RESERVED
L L
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R-0-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED SYSPLLMULT RESERVED RESERVED SYSPLLCTL1 CLKSRCCTL3 CLKSRCCTL2 CLKSRCCTL1
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-43. CLKCFGLOCK1 Register Field Descriptions

Bit Field Type Reset Description
31-17 RESERVED R-0 0h Reserved
16 XTALCR R/WSonce 0h Common Lock bit for XTALCR & XTAL CR2 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
15 LOSPCP R/WSonce 0h Lock bit for LOSPCP register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
14 RESERVED R/WSonce 0h Reserved
13 RESERVED R/WSonce 0h Reserved
12 AUXCLKDIVSEL R/WSonce 0h Lock bit for AUXCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
11 SYSCLKDIVSEL R/WSonce 0h Lock bit for SYSCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
10 RESERVED R/WSonce 0h Reserved
9 RESERVED R-0 0h Reserved
8 RESERVED R-0 0h Reserved
7 RESERVED R/WSonce 0h Reserved

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Table 3-43. CLKCFGLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
6 SYSPLLMULT R/WSonce 0h Lock bit for SYSPLLMULT register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
5 RESERVED R/WSonce 0h Reserved
4 RESERVED R/WSonce 0h Reserved
3 SYSPLLCTL1 R/WSonce 0h Lock bit for SYSPLLCTL1 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
2 CLKSRCCTL3 R/WSonce 0h Lock bit for CLKSRCCTL3 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
1 CLKSRCCTL2 R/WSonce 0h Lock bit for CLKSRCCTL2 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
0 CLKSRCCTL1 R/WSonce 0h Lock bit for CLKSRCCTL1 register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

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3.16.3.2 CLKSRCCTL1 Register (Offset = 8h) [Reset = 0h]

CLKSRCCTL1 is shown in Figure 3-42 and described in Table 3-44.
Return to the Summary Table.
Clock Source Control register-1
This memory mapped register requires a delay of 45 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 45 NOP instructions.
Figure 3-42. CLKSRCCTL1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WDHALTI RESERVED INTOSC2OFF RESERVED OSCCLKSRCSEL
R-0-0h R/W-0h R/W-0h R/W-0h R-0-0h R/W-0h

Table 3-44. CLKSRCCTL1 Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5 WDHALTI R/W 0h Watchdog HALT Mode Ignore Bit: This bit determines if WD is
functional in the HALT mode or not.
0 = WD is not functional in the HALT mode. Clock to WD is
gated when system enters HALT mode. Additionally, INTOSC1 and
INTOSC2 are powered-down when system enters HALT mode
1 = WD is functional in the HALT mode. Clock to WD is not gated
and INTOSC1/2 are not powered-down when system enters HALT
mode
Reset type: XRSn
4 RESERVED R/W 0h Reserved
3 INTOSC2OFF R/W 0h Internal Oscillator 2 Off Bit: This bit turns oscillator 2 off:
0 = Internal Oscillator 2 On (default on reset)
1 = Internal Oscillator 2 Off
This bit could be used by the user to turn off the internal oscillator 2 if
it is not used.
NOTE: Ensure no resources are using a clock source prior
to disabling it. For example OSCCLKSRCSEL (SYSPLL),
TMR2CLKSRCSEL (CPUTIMER2) and XCLOCKOUT (XCLKOUT).
Reset type: XRSn
2 RESERVED R-0 0h Reserved

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Table 3-44. CLKSRCCTL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 OSCCLKSRCSEL R/W 0h Oscillator Clock Source Select Bit: This bit selects the source for
OSCCLK.
00 = INTOSC2 (default on reset)
01 = External Oscillator (XTAL)
10 = INTOSC1
11 = reserved (default to INTOSC1)
At power-up or after an XRSn, INTOSC2 is selected by default.
Whenever the user changes the clock source using these bits, the
SYSPLLMULT[13:0] register will be forced to zero and the PLL
will be bypassed and powered down. This prevents potential PLL
overshoot. The user will then have to write to the SYSPLLMULT
register to configure the appropriate multiplier.
The user must wait 10 OSCCLK cycles before writing to
SYSPLLMULT or disabling the previous clock source to allow the
change to
complete..
Notes:
[1] INTOSC1 is recommended to be used only after missing clock
detection. If user wants to re-lock the PLL with INTOSC1 (the
back-up clock source) after missing clock is detected, he can do a
MCLKCLR and lock the PLL.
Reset type: XRSn

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3.16.3.3 CLKSRCCTL2 Register (Offset = Ah) [Reset = 0h]

CLKSRCCTL2 is shown in Figure 3-43 and described in Table 3-45.
Return to the Summary Table.
Clock Source Control register-2
This memory mapped register requires a delay of 45 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 45 NOP instructions.
Figure 3-43. CLKSRCCTL2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED
R-0-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED MCANABCLKSEL RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CANABCLKSEL RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-45. CLKSRCCTL2 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17-16 RESERVED R/W 0h Reserved
15-14 RESERVED R/W 0h Reserved
13-12 RESERVED R/W 0h Reserved
11-10 MCANABCLKSEL R/W 0h MCAN Bit Clock Source Select Bit:
00 = CPU1SYSCLK
10 = AUXCLKIN
11 = PLLRAWCLK
Missing clock detect circuit doesnt have any impact on these bits.
Reset type: XRSn
9-8 RESERVED R/W 0h Reserved
7-6 RESERVED R/W 0h Reserved
5-4 RESERVED R/W 0h Reserved
3-2 CANABCLKSEL R/W 0h CANA Bit-Clock Source Select Bit:
00 = PERx.SYSCLK (default on reset)
01 = External Oscillator (XTAL)
10 = AUXCLKIN (from GPIO)
11 = Reserved
Missing clock detect circuit doesnt have any impact on these bits.
Reset type: XRSn
1-0 RESERVED R/W 0h Reserved

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3.16.3.4 CLKSRCCTL3 Register (Offset = Ch) [Reset = 0h]

CLKSRCCTL3 is shown in Figure 3-44 and described in Table 3-46.
Return to the Summary Table.
Clock Source Control register-3
This memory mapped register requires a delay of 45 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 45 NOP instructions.
Figure 3-44. CLKSRCCTL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED XCLKOUTSEL
R-0-0h R/W-0h

Table 3-46. CLKSRCCTL3 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3-0 XCLKOUTSEL R/W 0h XCLKOUT Source Select Bit: This bit selects the source for
XCLKOUT:
0000 = PLLSYSCLK (default on reset)
0001 = PLLCLK
0010 = SYSCLK
0101 = INTOSC1
0110 = INTOSC2
0111 = XTAL
Rest = Reserved
Reset type: SYSRSn

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3.16.3.5 SYSPLLCTL1 Register (Offset = Eh) [Reset = 0h]

SYSPLLCTL1 is shown in Figure 3-45 and described in Table 3-47.
Return to the Summary Table.
SYSPLL Control register-1
This memory mapped register requires a delay of 45 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 45 NOP instructions.
Figure 3-45. SYSPLLCTL1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED PLLCLKEN PLLEN
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-47. SYSPLLCTL1 Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 PLLCLKEN R/W 0h SYSPLL bypassed or included in the PLLSYSCLK path: This bit
decides if the SYSPLL is bypassed when PLLSYSCLK is generated
1 = PLLSYSCLK is fed from the SYSPLL clock output. Users need
to make sure that the PLL is locked before enabling this clock to the
system.
0 = SYSPLL is bypassed. Clock to system is direct feed from
OSCCLK
Reset type: XRSn
0 PLLEN R/W 0h SYSPLL enabled or disabled: This bit decides if the SYSPLL is
enabled or not
1 = SYSPLL is enabled
0 = SYSPLL is powered off. Clock to system is direct feed from
OSCCLK
Reset type: XRSn

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3.16.3.6 SYSPLLMULT Register (Offset = 14h) [Reset = 0h]

SYSPLLMULT is shown in Figure 3-46 and described in Table 3-48.
Return to the Summary Table.
SYSPLL Multiplier register
This memory mapped register requires a delay of 45 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 45 NOP instructions.
Figure 3-46. SYSPLLMULT Register
31 30 29 28 27 26 25 24
RESERVED REFDIV
R-0-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED ODIV
R-0-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R-0-0h R/W-0h

7 6 5 4 3 2 1 0
IMULT
R/W-0h

Table 3-48. SYSPLLMULT Register Field Descriptions

Bit Field Type Reset Description
31-29 RESERVED R-0 0h Reserved
28-24 REFDIV R/W 0h SYSPLL Reference Clock Divider
PLL Reference Divider = REFDIV + 1
Reset type: XRSn
23-21 RESERVED R-0 0h Reserved
20-16 ODIV R/W 0h SYSPLL Output Clock Divider
PLL Output Divider = ODIV + 1
ODIV should be set to 1 or greater to ensure the PLL output meets
duty cycle requirements.
Reset type: XRSn
15-14 RESERVED R-0 0h Reserved
13-12 RESERVED R/W 0h Reserved
11-10 RESERVED R-0 0h Reserved
9-8 RESERVED R/W 0h Reserved
7-0 IMULT R/W 0h SYSPLL Integer Multiplier:
For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1
0000001 Integer Multiplier = 1
0000010 Integer Multiplier = 2
0000011 Integer Multiplier = 3
.......
1111111 Integer Multipler = 127
Note for APLL Multiplier values from 0-3 are invalid, internally those
will be treated to 4.
Reset type: XRSn

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3.16.3.7 SYSPLLSTS Register (Offset = 16h) [Reset = 30h]

SYSPLLSTS is shown in Figure 3-47 and described in Table 3-49.
Return to the Summary Table.
SYSPLL Status register
Figure 3-47. SYSPLLSTS Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED REF_LOSTS RESERVED SLIPS LOCKS
R-0-0h R-1h R-1h W1C-0h R-0h R-0h R-0h

Table 3-49. SYSPLLSTS Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5 RESERVED R 1h Reserved
4 RESERVED R 1h Reserved
3 REF_LOSTS W1C 0h SYSPLL "Reference Lost" Status Bit: This bit indicates whether the
SYSPLL is out of lock range
0 = "Reference Lost" event has not occurred.
1 = "Reference Lost" event has occurred.
Reset type: XRSn
2 RESERVED R 0h Reserved
1 SLIPS R 0h RESERVED: This bit is reserved and the value read should be
ignored. TI recommends using DCC to evaluate SYSPLL Slip status.
Refer to InitSysPll() or SysCtl_setClock() functions inside the latest
example software from C2000Ware for checking SYSPLL Slip status
using DCC.
Reset type: XRSn
0 LOCKS R 0h SYSPLL Lock Status Bit: This bit indicates whether the SYSPLL is
locked or not
0 = SYSPLL is not yet locked
1 = SYSPLL is locked
Reset type: XRSn

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3.16.3.8 SYSCLKDIVSEL Register (Offset = 22h) [Reset = 0h]

SYSCLKDIVSEL is shown in Figure 3-48 and described in Table 3-50.
Return to the Summary Table.
System Clock Divider Select register
This memory mapped register requires a delay of 45 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 45 NOP instructions.
Figure 3-48. SYSCLKDIVSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED PLLSYSCLKDI
V_LSB
R-0-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED PLLSYSCLKDIV
R-0-0h R/W-0h

Table 3-50. SYSCLKDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-9 RESERVED R-0 0h Reserved
8 PLLSYSCLKDIV_LSB R/W 0h This bit is LSB of the Divider that when set
allows the ODD divisions such that the divider
value is {PLLSYSCLKDIV,PLLSYSCLKDIV_LSB}. E.g. if
PLLSYSCLKDIV=0x1, and PLLSYSCLKDIV_LSB=0 then divider of
2 is used else in case PLLSYSCLKDIV_LSB=1 then divider value is
3.
Reset type: XRSn
7-6 RESERVED R-0 0h Reserved
5-0 PLLSYSCLKDIV R/W 0h PLLSYSCLK Divide Select: This bit selects the divider setting for the
PLLSYSCLK.
000000 = /1
000001 = /2
000010 = /4 (default on reset)
000011 = /6
000100 = /8
......
111111 = /126
Reset type: XRSn

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3.16.3.9 AUXCLKDIVSEL Register (Offset = 24h) [Reset = 1301h]

AUXCLKDIVSEL is shown in Figure 3-49 and described in Table 3-51.
Return to the Summary Table.
Auxillary Clock Divider Select register
Figure 3-49. AUXCLKDIVSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MCANCLKDIV RESERVED RESERVED
R-0-0h R/W-13h R-0-0h R/W-1h

Table 3-51. AUXCLKDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-13 RESERVED R-0 0h Reserved
12-8 MCANCLKDIV R/W 13h 00000 = /1
00001 = /2
...
10010 = /19
10011 = /20
101xx = Rsvd
11xxx = Rsvd
Reset type: XRSn
7-3 RESERVED R-0 0h Reserved
2-0 RESERVED R/W 1h Reserved

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3.16.3.10 XCLKOUTDIVSEL Register (Offset = 28h) [Reset = 3h]

XCLKOUTDIVSEL is shown in Figure 3-50 and described in Table 3-52.
Return to the Summary Table.
XCLKOUT Divider Select register
This memory mapped register requires a delay of 45 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 45 NOP instructions.
Figure 3-50. XCLKOUTDIVSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED XCLKOUTDIV
R-0-0h R/W-3h

Table 3-52. XCLKOUTDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1-0 XCLKOUTDIV R/W 3h XCLKOUT Divide Select: This bit selects the divider setting for the
XCLKOUT.
00 = /1
01 = /2
10 = /4
11 = /8 (default on reset)
Reset type: SYSRSn

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3.16.3.11 LOSPCP Register (Offset = 2Ch) [Reset = 2h]

LOSPCP is shown in Figure 3-51 and described in Table 3-53.
Return to the Summary Table.
Low Speed Clock Source Prescalar
Figure 3-51. LOSPCP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LSPCLKDIV
R-0-0h R/W-2h

Table 3-53. LOSPCP Register Field Descriptions

Bit Field Type Reset Description
31-3 RESERVED R-0 0h Reserved
2-0 LSPCLKDIV R/W 2h These bits configure the low-speed peripheral clock (LSPCLK) rate
000,LSPCLK = / 1
001,LSPCLK = / 2
010,LSPCLK = / 4 (default on reset)
011,LSPCLK = / 6
100,LSPCLK = / 8
101,LSPCLK = / 10
110,LSPCLK = / 12
111,LSPCLK = / 14
Note:
[1] This clock is used as strobe for the SCI and SPI modules.
Reset type: SYSRSn

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3.16.3.12 MCDCR Register (Offset = 2Eh) [Reset = 0h]

MCDCR is shown in Figure 3-52 and described in Table 3-54.
Return to the Summary Table.
Missing Clock Detect Control Register
Figure 3-52. MCDCR Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED
R-0-0h R/W-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED SYSREF_LOST SYSREF_LOST SYSREF_LOST OSCOFF MCLKOFF MCLKCLR MCLKSTS
_MCD_EN SCLR S
R-0h R/W-0h R-0/W1S-0h R-0h R/W-0h R/W-0h R-0/W1S-0h R-0h

Table 3-54. MCDCR Register Field Descriptions

Bit Field Type Reset Description
31-10 RESERVED R-0 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R 0h Reserved
6 SYSREF_LOST_MCD_E R/W 0h Control to add "PLL reference clock lost" as cause for MCD
N 0 = "PLL reference clock Lost" does not affect MCD.
1 = Upon "PLL reference clock Lost" MCD is asserted.
Reset type: XRSn
5 SYSREF_LOSTSCLR R-0/W1S 0h Clears the REF_LOST_STS from PLLSTS which is root for MCD
trigger.
0 = No effect on present state of the REF_LOST_STS
1 = Clears the REF_LOST_STS bit to '0'. Bit clears itself after clear
pulse to REF_LOST_STS.
Read always gives '0'.
Reset type: XRSn
4 SYSREF_LOSTS R 0h SYSPLL "Reference Lost" Status Bit: This bit indicates whether the
SYSPLL is out of lock range
0 = "Reference Lost" event has not occurred.
1 = "Reference Lost" event has occurred.
Reset type: XRSn
3 OSCOFF R/W 0h Oscillator Clock Disconnect from MCD Bit:
0 = OSCCLK Connected to OSCCLK Counter in MCD module
1 = OSCCLK Disconnected to OSCCLK Counter in MCD module
Reset type: XRSn
2 MCLKOFF R/W 0h Missing Clock Detect Off Bit:
0 = Missing Clock Detect Circuit Enabled
1 = Missing Clock Detect Circuit Disabled
Reset type: XRSn
1 MCLKCLR R-0/W1S 0h Missing Clock Clear Bit:
Write 1" to this bit to clear MCLKSTS bit and reset the missing clock
detect circuit."
Reset type: XRSn

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Table 3-54. MCDCR Register Field Descriptions (continued)

Bit Field Type Reset Description
0 MCLKSTS R 0h Missing Clock Status Bit:
0 = OSCCLK Is OK
1 = OSCCLK Detected Missing, CLOCKFAILn Generated
Reset type: XRSn

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3.16.3.13 X1CNT Register (Offset = 30h) [Reset = 0h]

X1CNT is shown in Figure 3-53 and described in Table 3-55.
Return to the Summary Table.
10-bit Counter on X1 Clock
Figure 3-53. X1CNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED CLR
R-0-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED X1CNT
R-0-0h R-0h

Table 3-55. X1CNT Register Field Descriptions

Bit Field Type Reset Description
31-17 RESERVED R-0 0h Reserved
16 CLR R/W 0h X1 Counter clear:
A write of '1' to this bit field clears the X1CNT and makes it count
from 0x0 again (provided X1 clock is ticking).
Writes of '0' are ignore to this bit field
Reset type: XRSn
15-11 RESERVED R-0 0h Reserved
10-0 X1CNT R 0h X1 Counter:
- This counter increments on every X1 CLOCKs positive-edge.
- Once it reaches the values of 0x7ff, it freezes
- Before switching from INTOSC2 to X1, application must check this
counter and make sure that it has saturated. This will ensure that the
Crystal connected to X1/X2 is oscillating.
Reset type: XRSn

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3.16.3.14 XTALCR Register (Offset = 32h) [Reset = 5h]

XTALCR is shown in Figure 3-54 and described in Table 3-56.
Return to the Summary Table.
XTAL Control Register
This memory mapped register requires a delay of 45 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 45 NOP instructions.
Figure 3-54. XTALCR Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED SE OSCOFF
R-0-0h R/W-1h R/W-0h R/W-1h

Table 3-56. XTALCR Register Field Descriptions

Bit Field Type Reset Description
31-3 RESERVED R-0 0h Reserved
2 RESERVED R/W 1h Reserved
1 SE R/W 0h Configures XTAL oscillator in single-ended or Crystal mode when
XTAL oscillator is powered up(i.e. OSCOFF = 0)
0 XTAL oscillator in Crystal mode
1 XTAL oscilator in single-ended mode (through X1)
Reset type: XRSn
0 OSCOFF R/W 1h This bit if '1', powers-down the XTAL oscillator macro and hence
doesn't let X2 to be driven by the XTAL oscillator. If a crystal is
connected to X1/X2, user needs to first clear this bit, wait for the
oscillator to power up (using X1CNT) and then only switch the clock
source to X1/X2
Reset type: XRSn

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3.16.3.15 XTALCR2 Register (Offset = 3Ah) [Reset = 3h]

XTALCR2 is shown in Figure 3-55 and described in Table 3-57.
Return to the Summary Table.
XTAL Control Register for pad init
Figure 3-55. XTALCR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FEN XOF XIF
R-0-0h R/W-0h R/W-1h R/W-1h

Table 3-57. XTALCR2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R/W 0h Reserved
15-3 RESERVED R-0 0h Reserved
2 FEN R/W 0h Configures XTAL oscillator pad initilisation.
0 : XOSC pads are not driven through GPIO connection.
1 : XOSC pads are driven through connected GPIO as per XIF &
XOF values.
This register has effect only when XOSC is OFF (no SE , no XTAL
mode).
If this register is set during XOSC off state (XOSCOFF=1 & SE=0)
then upon change of these controls this bit gets reset and rearmed.
Reset type: XRSn
1 XOF R/W 1h Polarity selection to initialise XO /X2 pad of the XOSC before start-
up
This value shall be deposited on the pad before XOSC started
(XOSCOFF=1)
If FEN=0 or XOSC is in XTAL or SE mode
then this value will not be applied to the pad.
Reset type: XRSn
0 XIF R/W 1h Polarity selection to initialise XI /X1 pad of the XOSC before start-up
This value shall be deposited on the pad before XOSC started
(XOSCOFF=1)
If FEN=0 or XOSC is in XTAL or SE mode
then this value will not be applied to the pad.
Reset type: XRSn

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3.16.3.16 CLKFAILCFG Register (Offset = 3Ch) [Reset = 0h]

CLKFAILCFG is shown in Figure 3-56 and described in Table 3-58.
Return to the Summary Table.
Clock Fail cause Configuration
Figure 3-56. CLKFAILCFG Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DCC1_ERROR DCC0_ERROR
_EN _EN
R-0-0h R/W-0h R/W-0h

Table 3-58. CLKFAILCFG Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 DCC1_ERROR_EN R/W 0h This field enables DCC1 Error to cause the clock-fail NMI to get
asserted.
0 : DCC1 Error does not affect Clock fail NMI
1: Occurrence of DCC1 Error triggers Clock fail NMI assertion and
ERROR pin assertion.
Reset type: XRSn
0 DCC0_ERROR_EN R/W 0h This field enables DCC0 Error to cause the clock-fail NMI to get
asserted.
0 : DCC0 Error does not affect Clock fail NMI
1: Occurrence of DCC0 Error triggers Clock fail NMI assertion and
ERROR pin assertion.
Reset type: XRSn

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3.16.4 CPU_SYS_REGS Registers

Table 3-59 lists the memory-mapped registers for the CPU_SYS_REGS registers. All register offset addresses
not listed in Table 3-59 should be considered as reserved locations and the register contents should not be
modified.
Table 3-59. CPU_SYS_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CPUSYSLOCK1 Lock bit for CPUSYS registers EALLOW Go
2h CPUSYSLOCK2 Lock bit for CPUSYS registers EALLOW Go
Ah PIEVERRADDR PIE Vector Fetch Error Address register EALLOW Go
22h PCLKCR0 Peripheral Clock Gating Registers EALLOW Go
26h PCLKCR2 Peripheral Clock Gating Register - ETPWM EALLOW Go
28h PCLKCR3 Peripheral Clock Gating Register - ECAP EALLOW Go
2Ah PCLKCR4 Peripheral Clock Gating Register - EQEP EALLOW Go
2Eh PCLKCR6 Peripheral Clock Gating Register - SDFM EALLOW Go
30h PCLKCR7 Peripheral Clock Gating Register - SCI EALLOW Go
32h PCLKCR8 Peripheral Clock Gating Register - SPI EALLOW Go
34h PCLKCR9 Peripheral Clock Gating Register - I2C EALLOW Go
36h PCLKCR10 Peripheral Clock Gating Register - CAN EALLOW Go
3Ch PCLKCR13 Peripheral Clock Gating Register - ADC EALLOW Go
3Eh PCLKCR14 Peripheral Clock Gating Register - CMPSS EALLOW Go
42h PCLKCR16 Peripheral Clock Gating Register Buf_DAC EALLOW Go
44h PCLKCR17 Peripheral Clock Gating Register - CLB EALLOW Go
46h PCLKCR18 Peripheral Clock Gating Register - FSI EALLOW Go
48h PCLKCR19 Peripheral Clock Gating Register - LIN EALLOW Go
4Ah PCLKCR20 Peripheral Clock Gating Register - PMBUS EALLOW Go
4Ch PCLKCR21 Peripheral Clock Gating Register - DCC EALLOW Go
54h PCLKCR25 Peripheral Clock Gating Register - HIC EALLOW Go
56h PCLKCR26 Peripheral Clock Gating Register - AES EALLOW Go
58h PCLKCR27 Peripheral Clock Gating Register - EPG EALLOW Go
70h SIMRESET Simulated Reset Register Go
76h LPMCR LPM Control Register EALLOW Go
78h GPIOLPMSEL0 GPIO LPM Wakeup select registers EALLOW Go
7Ah GPIOLPMSEL1 GPIO LPM Wakeup select registers EALLOW Go
7Ch TMR2CLKCTL Timer2 Clock Measurement functionality control EALLOW Go
register
7Eh RESCCLR Reset Cause Clear Register Go
80h RESC Reset Cause register Go
98h MCANWAKESTATUS MCAN Wake Status Register Go
9Ah MCANWAKESTATUSCLR MCAN Wake Status Clear Register Go
9Ch CLKSTOPREQ Peripheral Clock Stop Request Register Go
9Eh CLKSTOPACK Peripheral Clock Stop Ackonwledge Register Go

Complex bit access types are encoded to fit into small table cells. Table 3-60 shows the codes that are used for
access types in this section.
Table 3-60. CPU_SYS_REGS Access Type Codes
Access Type Code Description
Read Type

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Table 3-60. CPU_SYS_REGS Access Type Codes

(continued)
Access Type Code Description
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1C W Write
1C 1 to clear
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.4.1 CPUSYSLOCK1 Register (Offset = 0h) [Reset = 0h]

CPUSYSLOCK1 is shown in Figure 3-57 and described in Table 3-61.
Return to the Summary Table.
Lock bit for CPUSYS registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this
register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always
allowed
Figure 3-57. CPUSYSLOCK1 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED PCLKCR22 PCLKCR21 PCLKCR20 PCLKCR19 PCLKCR18 PCLKCR17
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

23 22 21 20 19 18 17 16
GPIOLPMSEL1 GPIOLPMSEL0 LPMCR RESERVED PCLKCR16 RESERVED PCLKCR14 PCLKCR13
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED PCLKCR10 PCLKCR9 PCLKCR8 PCLKCR7 PCLKCR6 RESERVED
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
PCLKCR4 PCLKCR3 PCLKCR2 RESERVED PCLKCR0 PIEVERRADDR RESERVED RESERVED
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-61. CPUSYSLOCK1 Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/WSonce 0h Reserved
30 RESERVED R/WSonce 0h Reserved
29 PCLKCR22 R/WSonce 0h Lock bit for PCLKCR22 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
28 PCLKCR21 R/WSonce 0h Lock bit for PCLKCR21 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
27 PCLKCR20 R/WSonce 0h Lock bit for PCLKCR20 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
26 PCLKCR19 R/WSonce 0h Lock bit for PCLKCR19 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
25 PCLKCR18 R/WSonce 0h Lock bit for PCLKCR18 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
24 PCLKCR17 R/WSonce 0h Lock bit for PCLKCR17 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

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Table 3-61. CPUSYSLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
23 GPIOLPMSEL1 R/WSonce 0h Lock bit for GPIOLPMSEL1 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
22 GPIOLPMSEL0 R/WSonce 0h Lock bit for GPIOLPMSEL0 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
21 LPMCR R/WSonce 0h Lock bit for LPMCR Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
20 RESERVED R/WSonce 0h Reserved
19 PCLKCR16 R/WSonce 0h Lock bit for PCLKCR16 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
18 RESERVED R/WSonce 0h Reserved
17 PCLKCR14 R/WSonce 0h Lock bit for PCLKCR14 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
16 PCLKCR13 R/WSonce 0h Lock bit for PCLKCR13 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
15 RESERVED R/WSonce 0h Reserved
14 RESERVED R/WSonce 0h Reserved
13 PCLKCR10 R/WSonce 0h Lock bit for PCLKCR10 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
12 PCLKCR9 R/WSonce 0h Lock bit for PCLKCR9 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
11 PCLKCR8 R/WSonce 0h Lock bit for PCLKCR8 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
10 PCLKCR7 R/WSonce 0h Lock bit for PCLKCR7 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
9 PCLKCR6 R/WSonce 0h Lock bit for PCLKCR6 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
8 RESERVED R/WSonce 0h Reserved
7 PCLKCR4 R/WSonce 0h Lock bit for PCLKCR4 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
6 PCLKCR3 R/WSonce 0h Lock bit for PCLKCR3 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

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Table 3-61. CPUSYSLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
5 PCLKCR2 R/WSonce 0h Lock bit for PCLKCR2 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
4 RESERVED R/WSonce 0h Reserved
3 PCLKCR0 R/WSonce 0h Lock bit for PCLKCR0 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
2 PIEVERRADDR R/WSonce 0h Lock bit for PIEVERRADDR Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
1 RESERVED R/WSonce 0h Reserved
0 RESERVED R/WSonce 0h Reserved

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3.16.4.2 CPUSYSLOCK2 Register (Offset = 2h) [Reset = 0h]

CPUSYSLOCK2 is shown in Figure 3-58 and described in Table 3-62.
Return to the Summary Table.
Lock bit for CPUSYS registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this
register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always
allowed
Figure 3-58. CPUSYSLOCK2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED PCLKCR27 PCLKCR26 PCLKCR25 RESERVED
R-0-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-62. CPUSYSLOCK2 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 PCLKCR27 R/WSonce 0h Lock bit for PCLKCR27 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
2 PCLKCR26 R/WSonce 0h Lock bit for PCLKCR26 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
1 PCLKCR25 R/WSonce 0h Lock bit for PCLKCR25 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
0 RESERVED R/WSonce 0h Reserved

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3.16.4.3 PIEVERRADDR Register (Offset = Ah) [Reset = 003FFFFFh]

PIEVERRADDR is shown in Figure 3-59 and described in Table 3-63.
Return to the Summary Table.
PIE Vector Fetch Error Address register
Figure 3-59. PIEVERRADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ADDR
R-0-0h R/W-003FFFFFh

Table 3-63. PIEVERRADDR Register Field Descriptions

Bit Field Type Reset Description
31-22 RESERVED R-0 0h Reserved
21-0 ADDR R/W 003FFFFFh This register defines the address of the PIE Vector Fetch Error
handler routine. Its the responsibility of user to initialize this register.
If this register is not initialized, a default error handler at address
0x3fffbe will get executed. Refer to the Boot ROM section for more
details on this register.
Reset type: XRSn

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3.16.4.4 PCLKCR0 Register (Offset = 22h) [Reset = 38h]

PCLKCR0 is shown in Figure 3-60 and described in Table 3-64.
Return to the Summary Table.
Peripheral Clock Gating Registers
Figure 3-60. PCLKCR0 Register
31 30 29 28 27 26 25 24
RESERVED ERAD
R-0-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED TBCLKSYNC RESERVED HRCAL
R-0-0h R/W-0h R/W-0h R-0-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED CLA1BGCRC CPUBGCRC RESERVED
R-0-0h R/W-0h R/W-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED CPUTIMER2 CPUTIMER1 CPUTIMER0 DMA RESERVED CLA1
R-0-0h R/W-1h R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h

Table 3-64. PCLKCR0 Register Field Descriptions

Bit Field Type Reset Description
31-25 RESERVED R-0 0h Reserved
24 ERAD R/W 0h ERAD Clock Enable Bit: When set, this enables the clock to the
ERAD module
1: ERAD clock is enabled
0: ERAD clock is disabled
Reset type: SYSRSn
23-20 RESERVED R-0 0h Reserved
19 RESERVED R/W 0h Reserved
18 TBCLKSYNC R/W 0h EPWM Time Base Clock sync: When set PWM time bases of
all the PWM modules belonging to the same CPU-Subsystem (as
partitioned using their CPUSEL bits) start counting
Reset type: SYSRSn
17 RESERVED R-0 0h Reserved
16 HRCAL R/W 0h HRCAL Clock Enable Bit: When set, this enables the clock to the
HRCAL module
1: HRCAL clock is enabled
0: HRCAL clock is disabled
Reset type: SYSRSn
15 RESERVED R-0 0h Reserved
14 CLA1BGCRC R/W 0h CLA1BGCRC Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
13 CPUBGCRC R/W 0h CPUBGCRC Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
12-6 RESERVED R-0 0h Reserved
5 CPUTIMER2 R/W 1h CPUTIMER2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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Table 3-64. PCLKCR0 Register Field Descriptions (continued)

Bit Field Type Reset Description
4 CPUTIMER1 R/W 1h CPUTIMER1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 CPUTIMER0 R/W 1h CPUTIMER0 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 DMA R/W 0h DMA Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 RESERVED R/W 0h Reserved
0 CLA1 R/W 0h CLA1 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.5 PCLKCR2 Register (Offset = 26h) [Reset = 0h]

PCLKCR2 is shown in Figure 3-61 and described in Table 3-65.
Return to the Summary Table.
Peripheral Clock Gating Register - ETPWM
Figure 3-61. PCLKCR2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-65. PCLKCR2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 EPWM8 R/W 0h EPWM8 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
6 EPWM7 R/W 0h EPWM7 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
5 EPWM6 R/W 0h EPWM6 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 EPWM5 R/W 0h EPWM5 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 EPWM4 R/W 0h EPWM4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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Table 3-65. PCLKCR2 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 EPWM3 R/W 0h EPWM3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 EPWM2 R/W 0h EPWM2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 EPWM1 R/W 0h EPWM1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.6 PCLKCR3 Register (Offset = 28h) [Reset = 0h]

PCLKCR3 is shown in Figure 3-62 and described in Table 3-66.
Return to the Summary Table.
Peripheral Clock Gating Register - ECAP
Figure 3-62. PCLKCR3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED ECAP3 ECAP2 ECAP1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-66. PCLKCR3 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 ECAP3 R/W 0h ECAP3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 ECAP2 R/W 0h ECAP2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 ECAP1 R/W 0h ECAP1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.7 PCLKCR4 Register (Offset = 2Ah) [Reset = 0h]

PCLKCR4 is shown in Figure 3-63 and described in Table 3-67.
Return to the Summary Table.
Peripheral Clock Gating Register - EQEP
Figure 3-63. PCLKCR4 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED EQEP2 EQEP1
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-67. PCLKCR4 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 EQEP2 R/W 0h EQEP2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 EQEP1 R/W 0h EQEP1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.8 PCLKCR6 Register (Offset = 2Eh) [Reset = 0h]

PCLKCR6 is shown in Figure 3-64 and described in Table 3-68.
Return to the Summary Table.
Peripheral Clock Gating Register - SDFM
Figure 3-64. PCLKCR6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESE RESE RESE RESE RESE RESE SD2 SD1
RVED RVED RVED RVED RVED RVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-68. PCLKCR6 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 SD2 R/W 0h SD2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 SD1 R/W 0h SD1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.9 PCLKCR7 Register (Offset = 30h) [Reset = 0h]

PCLKCR7 is shown in Figure 3-65 and described in Table 3-69.
Return to the Summary Table.
Peripheral Clock Gating Register - SCI
Figure 3-65. PCLKCR7 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED SCI_B SCI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-69. PCLKCR7 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 SCI_B R/W 0h SCI_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 SCI_A R/W 0h SCI_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.10 PCLKCR8 Register (Offset = 32h) [Reset = 0h]

PCLKCR8 is shown in Figure 3-66 and described in Table 3-70.
Return to the Summary Table.
Peripheral Clock Gating Register - SPI
Figure 3-66. PCLKCR8 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED SPI_B SPI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-70. PCLKCR8 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 SPI_B R/W 0h SPI_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 SPI_A R/W 0h SPI_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.11 PCLKCR9 Register (Offset = 34h) [Reset = 0h]

PCLKCR9 is shown in Figure 3-67 and described in Table 3-71.
Return to the Summary Table.
Peripheral Clock Gating Register - I2C
Figure 3-67. PCLKCR9 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED I2C_B I2C_A
R-0-0h R/W-0h R/W-0h

Table 3-71. PCLKCR9 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 I2C_B R/W 0h I2C_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 I2C_A R/W 0h I2C_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.12 PCLKCR10 Register (Offset = 36h) [Reset = 0h]

PCLKCR10 is shown in Figure 3-68 and described in Table 3-72.
Return to the Summary Table.
Peripheral Clock Gating Register - CAN
Figure 3-68. PCLKCR10 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED MCAN_A RESERVED RESERVED RESERVED CAN_A
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-72. PCLKCR10 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 MCAN_A R/W 0h MCAN_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 CAN_A R/W 0h CAN_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.13 PCLKCR13 Register (Offset = 3Ch) [Reset = 0h]

PCLKCR13 is shown in Figure 3-69 and described in Table 3-73.
Return to the Summary Table.
Peripheral Clock Gating Register - ADC
Figure 3-69. PCLKCR13 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED ADC_C ADC_B ADC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-73. PCLKCR13 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 ADC_C R/W 0h ADC_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 ADC_B R/W 0h ADC_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 ADC_A R/W 0h ADC_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.14 PCLKCR14 Register (Offset = 3Eh) [Reset = 0h]

PCLKCR14 is shown in Figure 3-70 and described in Table 3-74.
Return to the Summary Table.
Peripheral Clock Gating Register - CMPSS
Figure 3-70. PCLKCR14 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED CMPSS4 CMPSS3 CMPSS2 CMPSS1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-74. PCLKCR14 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 CMPSS4 R/W 0h CMPSS4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 CMPSS3 R/W 0h CMPSS3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 CMPSS2 R/W 0h CMPSS2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 CMPSS1 R/W 0h CMPSS1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.15 PCLKCR16 Register (Offset = 42h) [Reset = 0h]

PCLKCR16 is shown in Figure 3-71 and described in Table 3-75.
Return to the Summary Table.
Peripheral Clock Gating Register Buf_DAC
Figure 3-71. PCLKCR16 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED DAC_B DAC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-75. PCLKCR16 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 DAC_B R/W 0h Buffered_DAC_B Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
16 DAC_A R/W 0h Buffered_DAC_A Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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3.16.4.16 PCLKCR17 Register (Offset = 44h) [Reset = 0h]

PCLKCR17 is shown in Figure 3-72 and described in Table 3-76.
Return to the Summary Table.
Peripheral Clock Gating Register - CLB
Figure 3-72. PCLKCR17 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED CLB4 CLB3 CLB2 CLB1
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-76. PCLKCR17 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 CLB4 R/W 0h CLB4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 CLB3 R/W 0h CLB3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 CLB2 R/W 0h CLB2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 CLB1 R/W 0h CLB1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.17 PCLKCR18 Register (Offset = 46h) [Reset = 0h]

PCLKCR18 is shown in Figure 3-73 and described in Table 3-77.
Return to the Summary Table.
Peripheral Clock Gating Register - FSI
Figure 3-73. PCLKCR18 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED FSIRX_A FSITX_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-77. PCLKCR18 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 FSIRX_A R/W 0h FSIRX_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 FSITX_A R/W 0h FSITX_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.18 PCLKCR19 Register (Offset = 48h) [Reset = 0h]

PCLKCR19 is shown in Figure 3-74 and described in Table 3-78.
Return to the Summary Table.
Peripheral Clock Gating Register - LIN
Figure 3-74. PCLKCR19 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED LIN_B LIN_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-78. PCLKCR19 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 LIN_B R/W 0h LIN_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 LIN_A R/W 0h LIN_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.19 PCLKCR20 Register (Offset = 4Ah) [Reset = 0h]

PCLKCR20 is shown in Figure 3-75 and described in Table 3-79.
Return to the Summary Table.
Peripheral Clock Gating Register - PMBUS
Figure 3-75. PCLKCR20 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED PMBUS_A
R-0-0h R/W-0h R/W-0h

Table 3-79. PCLKCR20 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 RESERVED R/W 0h Reserved
0 PMBUS_A R/W 0h PMBUS_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.20 PCLKCR21 Register (Offset = 4Ch) [Reset = 0h]

PCLKCR21 is shown in Figure 3-76 and described in Table 3-80.
Return to the Summary Table.
Peripheral Clock Gating Register - DCC
Figure 3-76. PCLKCR21 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DCC1 DCC0
R-0-0h R/W-0h R/W-0h

Table 3-80. PCLKCR21 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 DCC1 R/W 0h DCC Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 DCC0 R/W 0h DCC Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.21 PCLKCR25 Register (Offset = 54h) [Reset = 0h]

PCLKCR25 is shown in Figure 3-77 and described in Table 3-81.
Return to the Summary Table.
Peripheral Clock Gating Register - HIC
Figure 3-77. PCLKCR25 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED HICA
R-0-0h R/W-0h

Table 3-81. PCLKCR25 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 HICA R/W 0h HICA Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.22 PCLKCR26 Register (Offset = 56h) [Reset = 0h]

PCLKCR26 is shown in Figure 3-78 and described in Table 3-82.
Return to the Summary Table.
Peripheral Clock Gating Register - AES
Figure 3-78. PCLKCR26 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED AESA
R-0-0h R/W-0h

Table 3-82. PCLKCR26 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 AESA R/W 0h AESA Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.23 PCLKCR27 Register (Offset = 58h) [Reset = 0h]

PCLKCR27 is shown in Figure 3-79 and described in Table 3-83.
Return to the Summary Table.
Peripheral Clock Gating Register - EPG
Figure 3-79. PCLKCR27 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED EPG1
R-0-0h R/W-0h

Table 3-83. PCLKCR27 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 EPG1 R/W 0h EPG1 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.4.24 SIMRESET Register (Offset = 70h) [Reset = 0h]

SIMRESET is shown in Figure 3-80 and described in Table 3-84.
Return to the Summary Table.
Simulated Reset Register
Note: This register exists only on CPU1
Figure 3-80. SIMRESET Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED XRSn CPU1RSn
R-0-0h R-0/W1S-0h R-0/W1S-0h

Table 3-84. SIMRESET Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h Write to this register succeeds only if this field is written with a value
of 0xa5a5
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the KEY
matches). 16-bit writes to the upper or lower half of this register will
be ignored
Reset type: XRSn
15-2 RESERVED R-0 0h Reserved
1 XRSn R-0/W1S 0h Writing a 1 to this field generates a XRSn like reset.
Writing a 0 has no effect.
Note: Writing to this pin will pull the XRSn pin low for 512 INTOSC1
clock cycles.
Reset type: XRSn
0 CPU1RSn R-0/W1S 0h Writing a 1 to this field generates a reset to to CPU1.
Writing a 0 has no effect.
Reset type: XRSn

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3.16.4.25 LPMCR Register (Offset = 76h) [Reset = FCh]

LPMCR is shown in Figure 3-81 and described in Table 3-85.
Return to the Summary Table.
LPM Control Register
Figure 3-81. LPMCR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED
R/W1S-0h R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED
R-0-0h R/W-0h

15 14 13 12 11 10 9 8
WDINTE RESERVED
R/W-0h R-0-0h

7 6 5 4 3 2 1 0
QUALSTDBY LPM
R/W-3Fh R/W-0h

Table 3-85. LPMCR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W1S 0h Reserved
30-18 RESERVED R-0 0h Reserved
17-16 RESERVED R/W 0h Reserved
15 WDINTE R/W 0h When this bit is set to 1, it enables the watchdog interrupt signal to
wake the device from STANDBY mode.
Note:
[1] To use this signal, the user must also enable the WDINTn signal
using the WDENINT bit in the SCSR register. This signal will not
wake the device from HALT mode because the clock to watchdog
module is turned off
Reset type: SYSRSn
14-8 RESERVED R-0 0h Reserved
7-2 QUALSTDBY R/W 3Fh Select number of OSCCLK clock cycles to qualify the selected inputs
when waking the from STANDBY mode:
000000 = 2 OSCCLKs
000001 = 3 OSCCLKs
......
111111 = 65 OSCCLKs
Note: The LPMCR.QUALSTDBY register should be set to a value
greater than the ratio of INTOSC1/PLLSYSCLK to ensure proper
wake up.
Reset type: SYSRSn
1-0 LPM R/W 0h These bits set the low power mode for the device. Takes effect when
CPU executes the IDLE instruction (when IDLE instruction is out of
EXE Phase of the Pipeline)
00: IDLE Mode
01: STANDBY Mode
1x: HALT Mode
Reset type: SYSRSn

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3.16.4.26 GPIOLPMSEL0 Register (Offset = 78h) [Reset = 0h]

GPIOLPMSEL0 is shown in Figure 3-82 and described in Table 3-86.
Return to the Summary Table.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities of the
selected pin.
Figure 3-82. GPIOLPMSEL0 Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-86. GPIOLPMSEL0 Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
30 GPIO30 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
29 GPIO29 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
28 GPIO28 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
27 GPIO27 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
26 GPIO26 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
25 GPIO25 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
24 GPIO24 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
23 GPIO23 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
22 GPIO22 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-86. GPIOLPMSEL0 Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO21 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
20 GPIO20 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
19 GPIO19 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
18 GPIO18 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
17 GPIO17 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
16 GPIO16 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
15 GPIO15 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
14 GPIO14 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
13 GPIO13 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
12 GPIO12 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
11 GPIO11 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
10 GPIO10 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
9 GPIO9 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
8 GPIO8 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
7 GPIO7 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
6 GPIO6 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
5 GPIO5 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
4 GPIO4 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
3 GPIO3 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-86. GPIOLPMSEL0 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 GPIO2 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
1 GPIO1 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
0 GPIO0 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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3.16.4.27 GPIOLPMSEL1 Register (Offset = 7Ah) [Reset = 0h]

GPIOLPMSEL1 is shown in Figure 3-83 and described in Table 3-87.
Return to the Summary Table.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities of the
selected pin.
Figure 3-83. GPIOLPMSEL1 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-87. GPIOLPMSEL1 Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 GPIO60 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
27 GPIO59 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
26 GPIO58 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
25 GPIO57 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
24 GPIO56 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
23 GPIO55 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
22 GPIO54 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
21 GPIO53 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-87. GPIOLPMSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO52 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
19 GPIO51 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
18 GPIO50 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
17 GPIO49 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
16 GPIO48 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
15 GPIO47 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
14 GPIO46 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
13 GPIO45 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
12 GPIO44 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
11 GPIO43 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
10 GPIO42 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
9 GPIO41 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
8 GPIO40 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
7 GPIO39 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
6 RESERVED R/W 0h Reserved
5 GPIO37 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
4 RESERVED R/W 0h Reserved
3 GPIO35 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
2 GPIO34 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
1 GPIO33 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-87. GPIOLPMSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 GPIO32 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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3.16.4.28 TMR2CLKCTL Register (Offset = 7Ch) [Reset = 0h]

TMR2CLKCTL is shown in Figure 3-84 and described in Table 3-88.
Return to the Summary Table.
Timer2 Clock Measurement functionality control register
This memory mapped register requires a delay of 45 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 45 NOP instructions.
Figure 3-84. TMR2CLKCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED TMR2CLKPRESCALE TMR2CLKSRCSEL
R-0-0h R/W-0h R/W-0h

Table 3-88. TMR2CLKCTL Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-3 TMR2CLKPRESCALE R/W 0h CPU Timer 2 Clock Pre-Scale Value: These bits select the pre-scale
value for the selected clock source for CPU Timer 2:
000: /1 (default on reset)
001: /2,
010: /4
011: /8
100: /16
101: spare (defaults to /16)
110: spare (defaults to /16)
111: spare (defaults to /16)
Note:
[1] The CPU Timer2s Clock sync logic detects an input clock edge
when configured for any clock source other than SYSCLK and
generates an appropriate clock pulse to the CPU timer2. If SYSCLK
is approximately the same or less then the input clock source, then
the user would need to configure the pre-scale value such that
SYSCLK is at least twice as fast as the pre-scaled value.
Reset type: SYSRSn
2-0 TMR2CLKSRCSEL R/W 0h CPU Timer 2 Clock Source Select Bit: This bit selects the source for
CPU Timer 2:
000 =SYSCLK Selected (default on reset, pre-scale is bypassed)
001 = INTOSC1
010 = INTOSC2
011 = XTAL
Other values = reserved
Reset type: SYSRSn

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3.16.4.29 RESCCLR Register (Offset = 7Eh) [Reset = 0h]

RESCCLR is shown in Figure 3-85 and described in Table 3-89.
Return to the Summary Table.
Reset Cause Clear Register
Figure 3-85. RESCCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED SIMRESET_XR SIMRESET_CP RESERVED SCCRESETn
Sn U1RSn
R-0-0h W1C-0h W1C-0h R-0-0h W1S-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED HWBISTn RESERVED NMIWDRSn WDRSn XRSn POR
R-0-0h W1S-0h W1S-0h R-0-0h W1S-0h W1S-0h W1S-0h W1S-0h

Table 3-89. RESCCLR Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R-0 0h Reserved
11 SIMRESET_XRSn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
10 SIMRESET_CPU1RSn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
9 RESERVED R-0 0h Reserved
8 SCCRESETn W1S 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
7 RESERVED R-0 0h Reserved
6 RESERVED W1S 0h Reserved
5 HWBISTn W1S 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
4 RESERVED R-0 0h Reserved
3 NMIWDRSn W1S 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn

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Table 3-89. RESCCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
2 WDRSn W1S 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
1 XRSn W1S 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
0 POR W1S 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn

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3.16.4.30 RESC Register (Offset = 80h) [Reset = X]

RESC is shown in Figure 3-86 and described in Table 3-90.
Return to the Summary Table.
Reset Cause register
Figure 3-86. RESC Register
31 30 29 28 27 26 25 24
DCON XRSn_pin_statu RESERVED
s
R-0h R-X R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED SIMRESET_XR SIMRESET_CP RESERVED SCCRESETn
Sn U1RSn
R-0-0h R-0h R-0h R-0-0h R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED HWBISTn RESERVED NMIWDRSn WDRSn XRSn POR
R-0-0h R-0h R-0h R-0-0h R-0h R-0h R-1h R-1h

Table 3-90. RESC Register Field Descriptions

Bit Field Type Reset Description
31 DCON R 0h Reading this bit provides the status of debugger connection to the
C28x CPU.
0 : Debugger is not connected to the C28x CPU
1 : Debugger is connected to the C28x CPU
Notes:
[1] This bit is connected to the DCON o/p signal of the C28x CPU
Reset type: N/A
30 XRSn_pin_status R X Reading this bit provides the current status of the XRSn pin. Reset
value is reflective of the pin status.
Reset type: N/A
29-16 RESERVED R-0 0h Reserved
15-12 RESERVED R-0 0h Reserved
11 SIMRESET_XRSn R 0h If this bit is set, indicates that the device was reset by
SIMRESET_XRSn
Reset type: PORESETn
10 SIMRESET_CPU1RSn R 0h If this bit is set, indicates that the device was reset by
SIMRESET_CPU1RSn
Reset type: PORESETn
9 RESERVED R-0 0h Reserved
8 SCCRESETn R 0h If this bit is set, indicates that the device was reset by SCCRESETn
(fired by DCSM).
Reset type: PORESETn
7 RESERVED R-0 0h Reserved
6 RESERVED R 0h Reserved
5 HWBISTn R 0h If this bit is set, indicates that the device was reset by HWBIST.
Reset type: PORESETn
4 RESERVED R-0 0h Reserved

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Table 3-90. RESC Register Field Descriptions (continued)

Bit Field Type Reset Description
3 NMIWDRSn R 0h If this bit is set, indicates that the device was reset by NMIWDRSn.
Note: To know the exact cause of NMI after the reset, software
needs to read NMISHDFLG registers
Reset type: PORESETn
2 WDRSn R 0h If this bit is set, indicates that the device was reset by WDRSn.
Note:
[1] A bit inside WD module also provides the same information. This
bit is present to keep things consistent. This register is a one-stop
shop for the software to know the reset cause for the C28x core.
Reset type: PORESETn
1 XRSn R 1h If this bit is set, indicates that the device was reset by XRSn.
Reset type: PORESETn
0 POR R 1h If this bit is set, indicates that the device was reset by PORn/BORn.
Reset type: PORESETn

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3.16.4.31 MCANWAKESTATUS Register (Offset = 98h) [Reset = 0h]

MCANWAKESTATUS is shown in Figure 3-87 and described in Table 3-91.
Return to the Summary Table.
MCAN Wake Status Register
Figure 3-87. MCANWAKESTATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED WAKE
R-0h R-0h

Table 3-91. MCANWAKESTATUS Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 WAKE R 0h 0 : wakeup event has not occured.
1 : wakeup event has occured.
Reset type: SYSRSn

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3.16.4.32 MCANWAKESTATUSCLR Register (Offset = 9Ah) [Reset = 0h]

MCANWAKESTATUSCLR is shown in Figure 3-88 and described in Table 3-92.
Return to the Summary Table.
MCAN Wake Status Clear Register
Figure 3-88. MCANWAKESTATUSCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED WAKE
R-0h R-0/W1S-0h

Table 3-92. MCANWAKESTATUSCLR Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 WAKE R-0/W1S 0h 0 : No effect.
1 : Clears WAKE bit of MCANWAKESTATUS register
Reset type: SYSRSn

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3.16.4.33 CLKSTOPREQ Register (Offset = 9Ch) [Reset = 0h]

CLKSTOPREQ is shown in Figure 3-89 and described in Table 3-93.
Return to the Summary Table.
Peripheral Clock Stop Request Register
Note: This register exists only on CPU1
Figure 3-89. CLKSTOPREQ Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED MCAN_A
R-0-0h R-0-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-93. CLKSTOPREQ Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h Write to any of the bits in this register will succeed only if a value of
0x5634 is written to the KEY field.
Reset type: SYSRSn
15-12 RESERVED R-0 0h Reserved
11-9 RESERVED R-0 0h Reserved
8 MCAN_A R/W 0h MCAN_A Clock Stop Request Bit
0: If clock to MCAN_A is turned off, it will be turned on, else no
effect.
1: Clock stop request toMCAN_A
Note: Once set, this bit is cleared when clock to MCAN_A is turned
on as a result of a wakeup event in hardware
Reset type: SYSRSn
7-6 RESERVED R-0 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R-0 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R-0 0h Reserved
0 RESERVED R/W 0h Reserved

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3.16.4.34 CLKSTOPACK Register (Offset = 9Eh) [Reset = 0h]

CLKSTOPACK is shown in Figure 3-90 and described in Table 3-94.
Return to the Summary Table.
Peripheral Clock Stop Ackonwledge Register
Note: This register exists only on CPU1
Figure 3-90. CLKSTOPACK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED MCAN_A
R-0-0h R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R-0h R-0h R-0-0h R-0h R-0-0h R-0h

Table 3-94. CLKSTOPACK Register Field Descriptions

Bit Field Type Reset Description
31-9 RESERVED R-0 0h Reserved
8 MCAN_A R 0h MCAN_A Clock Stop Acknowledge Bit
0: Clock stop request not acknowledged
1: Clock stop acknowledged
Reset type: SYSRSn
7-6 RESERVED R-0 0h Reserved
5 RESERVED R 0h Reserved
4 RESERVED R 0h Reserved
3 RESERVED R-0 0h Reserved
2 RESERVED R 0h Reserved
1 RESERVED R-0 0h Reserved
0 RESERVED R 0h Reserved

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3.16.5 CPUTIMER_REGS Registers

Table 3-95 lists the memory-mapped registers for the CPUTIMER_REGS registers. All register offset addresses
not listed in Table 3-95 should be considered as reserved locations and the register contents should not be
modified.
Table 3-95. CPUTIMER_REGS Registers
Offset Acronym Register Name Write Protection Section
0h TIM CPU-Timer, Counter Register Go
2h PRD CPU-Timer, Period Register Go
4h TCR CPU-Timer, Control Register Go
6h TPR CPU-Timer, Prescale Register Go
7h TPRH CPU-Timer, Prescale Register High Go

Complex bit access types are encoded to fit into small table cells. Table 3-96 shows the codes that are used for
access types in this section.
Table 3-96. CPUTIMER_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
W1C W Write
1C 1 to clear
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.5.1 TIM Register (Offset = 0h) [Reset = FFFFh]

TIM is shown in Figure 3-91 and described in Table 3-97.
Return to the Summary Table.
CPU-Timer, Counter Register
Figure 3-91. TIM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSW LSW
R/W-0h R/W-FFFFh

Table 3-97. TIM Register Field Descriptions

Bit Field Type Reset Description
31-16 MSW R/W 0h CPU-Timer Counter Registers
The TIMH register holds the high 16 bits of the current 32-bit
count of the timer. The TIMH:TIM decrements by one every
(TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer
prescale dividedown value. When the TIMH:TIM decrements to zero,
the TIMH:TIM register is reloaded with the period value contained
in the PRDH:PRD registers. The timer interrupt (TINT) signal is
generated.
Reset type: SYSRSn
15-0 LSW R/W FFFFh CPU-Timer Counter Registers
The TIM register holds the low 16 bits of the current 32-bit
count of the timer. The TIMH:TIM decrements by one every
(TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer
prescale dividedown value. When the TIMH:TIM decrements to zero,
the TIMH:TIM register is reloaded with the period value contained
in the PRDH:PRD registers. The timer interrupt (TINT) signal is
generated.
Reset type: SYSRSn

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3.16.5.2 PRD Register (Offset = 2h) [Reset = FFFFh]

PRD is shown in Figure 3-92 and described in Table 3-98.
Return to the Summary Table.
CPU-Timer, Period Register
Figure 3-92. PRD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSW LSW
R/W-0h R/W-FFFFh

Table 3-98. PRD Register Field Descriptions

Bit Field Type Reset Description
31-16 MSW R/W 0h CPU-Timer Period Registers
The PRDH register holds the high 16 bits of the 32-bit period. When
the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded
with the period value contained in the PRDH:PRD registers, at the
start of the next timer input clock cycle (the output of the prescaler).
The PRDH:PRD contents are also loaded into the TIMH:TIM when
you set the timer reload bit (TRB) in the Timer Control Register
(TCR).
Reset type: SYSRSn
15-0 LSW R/W FFFFh CPU-Timer Period Registers
The PRD register holds the low 16 bits of the 32-bit period. When
the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded
with the period value contained in the PRDH:PRD registers, at the
start of the next timer input clock cycle (the output of the prescaler).
The PRDH:PRD contents are also loaded into the TIMH:TIM when
you set the timer reload bit (TRB) in the Timer Control Register
(TCR).
Reset type: SYSRSn

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3.16.5.3 TCR Register (Offset = 4h) [Reset = 1h]

TCR is shown in Figure 3-93 and described in Table 3-99.
Return to the Summary Table.
CPU-Timer, Control Register
Figure 3-93. TCR Register
15 14 13 12 11 10 9 8
TIF TIE RESERVED FREE SOFT RESERVED
R/W1C-0h R/W-0h R-0h R/W-0h R/W-0h R-0h

7 6 5 4 3 2 1 0
RESERVED TRB TSS RESERVED
R-0h R/W-0h R/W-0h R-1h

Table 3-99. TCR Register Field Descriptions

Bit Field Type Reset Description
15 TIF R/W1C 0h CPU-Timer Overflow Flag.
TIF indicates whether a timer overflow has happened since TIF was
last cleared. TIF is not cleared automatically and does not need to be
cleared to enable the next timer interrupt.
Reset type: SYSRSn
0h (R/W) = The CPU-Timer has not decremented to zero.
Writes of 0 are ignored.
1h (R/W) = This flag gets set when the CPU-timer decrements to
zero.
Writing a 1 to this bit clears the flag.
14 TIE R/W 0h CPU-Timer Interrupt Enable.
Reset type: SYSRSn
0h (R/W) = The CPU-Timer interrupt is disabled.
1h (R/W) = The CPU-Timer interrupt is enabled. If the timer
decrements to zero, and TIE is set, the timer asserts its interrupt
request.
13-12 RESERVED R 0h Reserved
11 FREE R/W 0h If the FREE bit is set to 1, then, upon a software breakpoint, the
timer continues to run. If FREE is 0, then the SOFT bit controls the
emulation behavior.
Reset type: SYSRSn
0h (R/W) = Stop after the next decrement of the TIMH:TIM (hard
stop)
(SOFT bit controls the emulation behavior)
1h (R/W) = Free Run
(SOFT bit is don't care, counter is free running)
10 SOFT R/W 0h If the FREE bit is set to 1, then, upon a software breakpoint, the
timer continues to run (that is, free runs). In this case, SOFT is a
don't care. But if FREE is 0, then SOFT takes effect.
Reset type: SYSRSn
0h (R/W) = Stop after the next decrement of the TIMH:TIM (hard
stop).
(ONLY if FREE=0, if FREE=1 this bit is don't care)
1h (R/W) = Stop after the TIMH:TIM decrements to 0 (soft stop)
In the SOFT STOP mode, the timer generates an interrupt before
shutting down (since reaching 0 is the interrupt causing condition).
(ONLY if FREE=0, if FREE=1 this bit is don't care)
9-6 RESERVED R 0h Reserved

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Table 3-99. TCR Register Field Descriptions (continued)

Bit Field Type Reset Description
5 TRB R/W 0h Timer reload
Reset type: SYSRSn
0h (R/W) = The TRB bit is always read as zero. Writes of 0 are
ignored.
1h (R/W) = When you write a 1 to TRB, the TIMH:TIM is loaded with
the value in the PRDH:PRD,
and the prescaler counter (PSCH:PSC) is loaded with the value in
the timer dividedown
register (TDDRH:TDDR).
4 TSS R/W 0h CPU-Timer stop status bit.
TSS is a 1-bit flag that stops or starts the CPU-timer.
Reset type: SYSRSn
0h (R/W) = Reads of 0 indicate the CPU-timer is running.
To start or restart the CPU-timer, set TSS to 0. At reset, TSS is
cleared to 0 and the
CPU-timer immediately starts.
1h (R/W) = Reads of 1 indicate that the CPU-timer is stopped.
To stop the CPU-timer, set TSS to 1.
3-0 RESERVED R 1h Reserved

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3.16.5.4 TPR Register (Offset = 6h) [Reset = 0h]

TPR is shown in Figure 3-94 and described in Table 3-100.
Return to the Summary Table.
CPU-Timer, Prescale Register
Figure 3-94. TPR Register
15 14 13 12 11 10 9 8
PSC
R-0h

7 6 5 4 3 2 1 0
TDDR
R/W-0h

Table 3-100. TPR Register Field Descriptions

Bit Field Type Reset Description
15-8 PSC R 0h CPU-Timer Prescale Counter.
These bits hold the current prescale count for the timer. For every
timer clock source cycle that the PSCH:PSC value is greater than
0, the PSCH:PSC decrements by one. One timer clock (output
of the timer prescaler) cycle after the PSCH:PSC reaches 0, the
PSCH:PSC is loaded with the contents of the TDDRH:TDDR, and
the timer counter register (TIMH:TIM) decrements by one. The
PSCH:PSC is also reloaded whenever the timer reload bit (TRB)
is set by software. The PSCH:PSC can be checked by reading the
register, but it cannot be set directly. It must get its value from the
timer divide-down register
(TDDRH:TDDR). At reset, the PSCH:PSC is set to 0.
Reset type: SYSRSn
7-0 TDDR R/W 0h CPU-Timer Divide-Down.
Every (TDDRH:TDDR + 1) timer clock source cycles, the timer
counter register (TIMH:TIM) decrements by one. At reset, the
TDDRH:TDDR bits are cleared to 0. To increase the overall timer
count by an integer factor, write this factor minus one to the
TDDRH:TDDR bits. When the prescaler counter (PSCH:PSC)
value is 0, one timer clock source cycle later, the contents
of the TDDRH:TDDR reload the PSCH:PSC, and the TIMH:TIM
decrements by one. TDDRH:TDDR also reloads the PSCH:PSC
whenever the timer reload bit (TRB) is set by software.
Reset type: SYSRSn

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3.16.5.5 TPRH Register (Offset = 7h) [Reset = 0h]

TPRH is shown in Figure 3-95 and described in Table 3-101.
Return to the Summary Table.
CPU-Timer, Prescale Register High
Figure 3-95. TPRH Register
15 14 13 12 11 10 9 8
PSCH
R-0h

7 6 5 4 3 2 1 0
TDDRH
R/W-0h

Table 3-101. TPRH Register Field Descriptions

Bit Field Type Reset Description
15-8 PSCH R 0h See description of TIMERxTPR.
Reset type: SYSRSn
7-0 TDDRH R/W 0h See description of TIMERxTPR.
Reset type: SYSRSn

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3.16.6 DEV_CFG_REGS Registers

Table 3-102 lists the memory-mapped registers for the DEV_CFG_REGS registers. All register offset addresses
not listed in Table 3-102 should be considered as reserved locations and the register contents should not be
modified.
Table 3-102. DEV_CFG_REGS Registers
Offset Acronym Register Name Write Protection Section
8h PARTIDL Lower 32-bit of Device PART Identification Go
Number
Ah PARTIDH Upper 32-bit of Device PART Identification Go
Number
Ch REVID Device Revision Number Go
74h FUSEERR e-Fuse error Status register Go
82h SOFTPRES0 Processing Block Software Reset register EALLOW Go
86h SOFTPRES2 EPWM Software Reset register EALLOW Go
88h SOFTPRES3 ECAP Software Reset register EALLOW Go
8Ah SOFTPRES4 EQEP Software Reset register EALLOW Go
8Eh SOFTPRES6 Sigma Delta Software Reset register EALLOW Go
90h SOFTPRES7 SCI Software Reset register EALLOW Go
92h SOFTPRES8 SPI Software Reset register EALLOW Go
94h SOFTPRES9 I2C Software Reset register EALLOW Go
96h SOFTPRES10 CAN Software Reset register EALLOW Go
9Ch SOFTPRES13 ADC Software Reset register EALLOW Go
9Eh SOFTPRES14 CMPSS Software Reset register EALLOW Go
A2h SOFTPRES16 DAC Software Reset register EALLOW Go
A4h SOFTPRES17 CLB Software Reset register EALLOW Go
A6h SOFTPRES18 FSI Software Reset register EALLOW Go
A8h SOFTPRES19 LIN Software Reset register EALLOW Go
AAh SOFTPRES20 PMBUS Software Reset register EALLOW Go
ACh SOFTPRES21 DCC Software Reset register EALLOW Go
B4h SOFTPRES25 HIC Software Reset register EALLOW Go
B6h SOFTPRES26 AES Software Reset register EALLOW Go
B8h SOFTPRES27 EPG Software Reset register EALLOW Go
130h TAP_STATUS Status of JTAG State machine & Debugger Go
Connect
19Bh ECAPTYPE Configures ECAP Type for the device EALLOW Go
19Ch SDFMTYPE Configures SDFM Type for the device EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-103 shows the codes that are used for
access types in this section.
Table 3-103. DEV_CFG_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write

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Table 3-103. DEV_CFG_REGS Access Type Codes

(continued)
Access Type Code Description
W1C W Write
1C 1 to clear
W1S W Write
1S 1 to set
WOnce W Write
Once Write once
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.6.1 PARTIDL Register (Offset = 8h) [Reset = X]

PARTIDL is shown in Figure 3-96 and described in Table 3-104.
Return to the Summary Table.
Lower 32-bit of Device PART Identification Number
Figure 3-96. PARTIDL Register
31 30 29 28 27 26 25 24
RESERVED RESERVED
R-X R-0h

23 22 21 20 19 18 17 16
FLASH_SIZE
R-X

15 14 13 12 11 10 9 8
RESERVED INSTASPIN RESERVED RESERVED PIN_COUNT
R-0h R-X R-0h R-X R-X

7 6 5 4 3 2 1 0
QUAL RESERVED RESERVED RESERVED
R-X R-0h R-0h R-0h

Table 3-104. PARTIDL Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R X Reserved
27-24 RESERVED R 0h Reserved
23-16 FLASH_SIZE R X 0x7 - 384KB
0x6 - 256KB
0x5 - 128KB
Reset type: PORESETn
15 RESERVED R 0h Reserved
14-13 INSTASPIN R X 1 = InstaSPIN-FOC
2 = NONE
3 = NONE
Reset type: PORESETn
12 RESERVED R 0h Reserved
11 RESERVED R X Reserved
10-8 PIN_COUNT R X 1 = 64 pin (QFP - Q100)
2 = 64 pin (QFP)
3 = 80 pin (QFP)
4 = 48 pin (QFP)
5 = 100 pin (QFP)
Reset type: PORESETn
7-6 QUAL R X 0 = Engineering sample (TMX)
1 = Pilot production (TMP)
2 = Fully qualified (TMS)
Reset type: PORESETn
5 RESERVED R 0h Reserved
4-3 RESERVED R 0h Reserved
2-0 RESERVED R 0h Reserved

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3.16.6.2 PARTIDH Register (Offset = Ah) [Reset = X]

PARTIDH is shown in Figure 3-97 and described in Table 3-105.
Return to the Summary Table.
Upper 32-bit of Device PART Identification Number
Figure 3-97. PARTIDH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEVICE_CLASS_ID PARTNO
R-5h R-X

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAMILY RESERVED RESERVED
R-5h R-0h R-0h

Table 3-105. PARTIDH Register Field Descriptions

Bit Field Type Reset Description
31-24 DEVICE_CLASS_ID R 5h Device class ID
Reset type: PORESETn
23-16 PARTNO R X Part Number Designator
0xFF - F280039x
0xFE - F280038x
0xFD - F280037x
0xFC - F280036x
0xFB - F280035x
0xFA - F280034x
Reset type: PORESETn
15-8 FAMILY R 5h Device Family
Reset type: PORESETn
7-4 RESERVED R 0h Reserved
3-0 RESERVED R 0h Reserved

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3.16.6.3 REVID Register (Offset = Ch) [Reset = 0h]

REVID is shown in Figure 3-98 and described in Table 3-106.
Return to the Summary Table.
Device Revision Number
Figure 3-98. REVID Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED REVID
R-0-0h R-0h

Table 3-106. REVID Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-0 REVID R 0h Device Revision
Reset type: N/A

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3.16.6.4 FUSEERR Register (Offset = 74h) [Reset = 0h]

FUSEERR is shown in Figure 3-99 and described in Table 3-107.
Return to the Summary Table.
e-Fuse error Status register
Figure 3-99. FUSEERR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR ALERR
R-0-0h R-0h R-0h

Table 3-107. FUSEERR Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5 ERR R 0h Efuse Self Test Error Status set by hardware after fuse self test
completes, in case of self test error
0: No error during fuse self test
1: Fuse self test error
Reset type: XRSn
4-0 ALERR R 0h Efuse Autoload Error Status set by hardware after fuse auto load
completes
00000: No error in auto load
Other: Non zero value indicates error in autoload
Note:
[1] 10101 means a single-bit error during autoload. Since this gets
corrected by the ECC mechanism, this value shouldn't be treated as
an error condition.
Reset type: XRSn

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3.16.6.5 SOFTPRES0 Register (Offset = 82h) [Reset = 0h]

SOFTPRES0 is shown in Figure 3-100 and described in Table 3-108.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-100. SOFTPRES0 Register
31 30 29 28 27 26 25 24
RESERVED CPU1_ERAD
R-0-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED CPU1_CLA1BG CPU1_CPUBG RESERVED
CRC CRC
R-0-0h R/W-0h R/W-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED CPU1_CLA1
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-108. SOFTPRES0 Register Field Descriptions

Bit Field Type Reset Description
31-25 RESERVED R-0 0h Reserved
24 CPU1_ERAD R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
23-16 RESERVED R-0 0h Reserved
15 RESERVED R-0 0h Reserved
14 CPU1_CLA1BGCRC R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
13 CPU1_CPUBGCRC R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
12-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 CPU1_CLA1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.6 SOFTPRES2 Register (Offset = 86h) [Reset = 0h]

SOFTPRES2 is shown in Figure 3-101 and described in Table 3-109.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-101. SOFTPRES2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-109. SOFTPRES2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 EPWM8 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
6 EPWM7 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
5 EPWM6 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
4 EPWM5 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
3 EPWM4 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
2 EPWM3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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Table 3-109. SOFTPRES2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 EPWM2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 EPWM1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.7 SOFTPRES3 Register (Offset = 88h) [Reset = 0h]

SOFTPRES3 is shown in Figure 3-102 and described in Table 3-110.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-102. SOFTPRES3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED ECAP3 ECAP2 ECAP1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-110. SOFTPRES3 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 ECAP3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
1 ECAP2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 ECAP1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.8 SOFTPRES4 Register (Offset = 8Ah) [Reset = 0h]

SOFTPRES4 is shown in Figure 3-103 and described in Table 3-111.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-103. SOFTPRES4 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED EQEP2 EQEP1
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-111. SOFTPRES4 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 EQEP2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 EQEP1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.9 SOFTPRES6 Register (Offset = 8Eh) [Reset = 0h]

SOFTPRES6 is shown in Figure 3-104 and described in Table 3-112.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-104. SOFTPRES6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESE RESE RESE RESE RESE RESE SD2 SD1
RVED RVED RVED RVED RVED RVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-112. SOFTPRES6 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 SD2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 SD1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.10 SOFTPRES7 Register (Offset = 90h) [Reset = 0h]

SOFTPRES7 is shown in Figure 3-105 and described in Table 3-113.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-105. SOFTPRES7 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED SCI_B SCI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-113. SOFTPRES7 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 SCI_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 SCI_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.11 SOFTPRES8 Register (Offset = 92h) [Reset = 0h]

SOFTPRES8 is shown in Figure 3-106 and described in Table 3-114.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-106. SOFTPRES8 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED SPI_B SPI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-114. SOFTPRES8 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 SPI_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 SPI_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.12 SOFTPRES9 Register (Offset = 94h) [Reset = 0h]

SOFTPRES9 is shown in Figure 3-107 and described in Table 3-115.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-107. SOFTPRES9 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED I2C_B I2C_A
R-0-0h R/W-0h R/W-0h

Table 3-115. SOFTPRES9 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 I2C_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 I2C_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.13 SOFTPRES10 Register (Offset = 96h) [Reset = X]

SOFTPRES10 is shown in Figure 3-108 and described in Table 3-116.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-108. SOFTPRES10 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED MCAN_A RESERVED RESERVED RESERVED CAN_A
R-X R-X R-X R-X R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-116. SOFTPRES10 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R X Reserved
6 RESERVED R X Reserved
5 RESERVED R X Reserved
4 MCAN_A R X 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 CAN_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.14 SOFTPRES13 Register (Offset = 9Ch) [Reset = 0h]

SOFTPRES13 is shown in Figure 3-109 and described in Table 3-117.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-109. SOFTPRES13 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED ADC_C ADC_B ADC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-117. SOFTPRES13 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 ADC_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
1 ADC_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 ADC_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.15 SOFTPRES14 Register (Offset = 9Eh) [Reset = 0h]

SOFTPRES14 is shown in Figure 3-110 and described in Table 3-118.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-110. SOFTPRES14 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED CMPSS4 CMPSS3 CMPSS2 CMPSS1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-118. SOFTPRES14 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 CMPSS4 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
2 CMPSS3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
1 CMPSS2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 CMPSS1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.16 SOFTPRES16 Register (Offset = A2h) [Reset = 0h]

SOFTPRES16 is shown in Figure 3-111 and described in Table 3-119.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-111. SOFTPRES16 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED DAC_B DAC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-119. SOFTPRES16 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 DAC_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
16 DAC_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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3.16.6.17 SOFTPRES17 Register (Offset = A4h) [Reset = X]

SOFTPRES17 is shown in Figure 3-112 and described in Table 3-120.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-112. SOFTPRES17 Register
31 30 29 28 27 26 25 24
RESERVED
R-X

23 22 21 20 19 18 17 16
RESERVED
R-X

15 14 13 12 11 10 9 8
RESERVED
R-X

7 6 5 4 3 2 1 0
RESERVED CLB4 CLB3 CLB2 CLB1
R-X R/W-0h R/W-0h R-X R-X

Table 3-120. SOFTPRES17 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R X Reserved
3 CLB4 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
2 CLB3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
1 CLB2 R X 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 CLB1 R X 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.18 SOFTPRES18 Register (Offset = A6h) [Reset = X]

SOFTPRES18 is shown in Figure 3-113 and described in Table 3-121.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-113. SOFTPRES18 Register
31 30 29 28 27 26 25 24
RESERVED
R-X

23 22 21 20 19 18 17 16
RESERVED
R-X

15 14 13 12 11 10 9 8
RESERVED
R-X

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED FSIRX_A FSITX_A
R-X R/W-0h R/W-0h R-X R-X

Table 3-121. SOFTPRES18 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R X Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 FSIRX_A R X 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 FSITX_A R X 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.19 SOFTPRES19 Register (Offset = A8h) [Reset = 0h]

SOFTPRES19 is shown in Figure 3-114 and described in Table 3-122.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-114. SOFTPRES19 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED LIN_B LIN_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-122. SOFTPRES19 Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 LIN_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 LIN_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.20 SOFTPRES20 Register (Offset = AAh) [Reset = X]

SOFTPRES20 is shown in Figure 3-115 and described in Table 3-123.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-115. SOFTPRES20 Register
31 30 29 28 27 26 25 24
RESERVED
R-X

23 22 21 20 19 18 17 16
RESERVED
R-X

15 14 13 12 11 10 9 8
RESERVED
R-X

7 6 5 4 3 2 1 0
RESERVED RESERVED PMBUS_A
R-X R-X R-X

Table 3-123. SOFTPRES20 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R X Reserved
1 RESERVED R X Reserved
0 PMBUS_A R X 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.21 SOFTPRES21 Register (Offset = ACh) [Reset = 0h]

SOFTPRES21 is shown in Figure 3-116 and described in Table 3-124.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-116. SOFTPRES21 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DCC1 DCC0
R-0-0h R/W-0h R/W-0h

Table 3-124. SOFTPRES21 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 DCC1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn
0 DCC0 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.22 SOFTPRES25 Register (Offset = B4h) [Reset = 0h]

SOFTPRES25 is shown in Figure 3-117 and described in Table 3-125.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-117. SOFTPRES25 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED HIC_A
R-0-0h R/W-0h

Table 3-125. SOFTPRES25 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 HIC_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.23 SOFTPRES26 Register (Offset = B6h) [Reset = 0h]

SOFTPRES26 is shown in Figure 3-118 and described in Table 3-126.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-118. SOFTPRES26 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED AESA
R-0-0h R/W-0h

Table 3-126. SOFTPRES26 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 AESA R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.24 SOFTPRES27 Register (Offset = B8h) [Reset = 0h]

SOFTPRES27 is shown in Figure 3-119 and described in Table 3-127.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-119. SOFTPRES27 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED EPG1
R-0-0h R/W-0h

Table 3-127. SOFTPRES27 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 EPG1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: SYSRSn

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3.16.6.25 TAP_STATUS Register (Offset = 130h) [Reset = 0h]

TAP_STATUS is shown in Figure 3-120 and described in Table 3-128.
Return to the Summary Table.
Status of JTAG State machine & Debugger Connect
Figure 3-120. TAP_STATUS Register
31 30 29 28 27 26 25 24
DCON RESERVED
R-0h R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
TAP_STATE
R-0h

7 6 5 4 3 2 1 0
TAP_STATE
R-0h

Table 3-128. TAP_STATUS Register Field Descriptions

Bit Field Type Reset Description
31 DCON R 0h DebugConnect indication from IcePick.
Reset type: PORESETn
30-16 RESERVED R-0 0h Reserved
15-0 TAP_STATE R 0h TAP State Vector. With bits representing, Connect coresponding
POTAP* output to the
0:TLR,
1:IDLE,
2:SELECTDR,
3:CAPDR,
4:SHIFTDR,
5:EXIT1DR,
6:PAUSEDR,
7:EXIT2DR,
8:UPDTDR,
9:SLECTIR,
10:CAPIR,
11:SHIFTIR,
12:EXIT1IR,
13:PAUSEIR,
14:EXIT2IR,
15:UPDTIR,
Reset type: PORESETn

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3.16.6.26 ECAPTYPE Register (Offset = 19Bh) [Reset = 0h]

ECAPTYPE is shown in Figure 3-121 and described in Table 3-129.
Return to the Summary Table.
Based on the configuration enables disables features associated with the ECAP type.
Figure 3-121. ECAPTYPE Register
15 14 13 12 11 10 9 8
LOCK RESERVED
R/WSonce-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED TYPE
R-0-0h R/W-0h

Table 3-129. ECAPTYPE Register Field Descriptions

Bit Field Type Reset Description
15 LOCK R/WSonce 0h 1: Write to this register is not allowed.
0: Write to this register is allowed.
Reset type: SYSRSn
14-2 RESERVED R-0 0h Reserved
1-0 TYPE R/W 0h "00,10,11" :
1. No EALLOW protection to ECAP registers.
"01" :
1. ECAP registers are EALLOW protected.
Reset type: SYSRSn

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3.16.6.27 SDFMTYPE Register (Offset = 19Ch) [Reset = 0h]

SDFMTYPE is shown in Figure 3-122 and described in Table 3-130.
Return to the Summary Table.
Based on the configuration enables disables features associated with the SDFM type.
Figure 3-122. SDFMTYPE Register
15 14 13 12 11 10 9 8
LOCK RESERVED
R/WSonce-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED TYPE
R-0-0h R/W-0h

Table 3-130. SDFMTYPE Register Field Descriptions

Bit Field Type Reset Description
15 LOCK R/WSonce 0h 1: Write to this register is not allowed.
0: Write to this register is allowed.
Reset type: SYSRSn
14-2 RESERVED R-0 0h Reserved
1-0 TYPE R/W 0h "00,10,11" :
1. Data Ready conditions combined with the fault conditions on the
SDFM interrupt line.
2. Data ready interrupts from individual filters are not generated.
"01" :
1. Data Ready conditions do not generate the SDFMINT.
2. Each filter generates a separate data ready interrupts.
Reset type: SYSRSn

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3.16.7 DMA_CLA_SRC_SEL_REGS Registers

Table 3-131 lists the memory-mapped registers for the DMA_CLA_SRC_SEL_REGS registers. All register offset
addresses not listed in Table 3-131 should be considered as reserved locations and the register contents should
not be modified.
Table 3-131. DMA_CLA_SRC_SEL_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CLA1TASKSRCSELLOCK CLA1 Task Trigger Source Select Lock Register EALLOW Go
4h DMACHSRCSELLOCK DMA Channel Triger Source Select Lock Register EALLOW Go
6h CLA1TASKSRCSEL1 CLA1 Task Trigger Source Select Register-1 EALLOW Go
8h CLA1TASKSRCSEL2 CLA1 Task Trigger Source Select Register-2 EALLOW Go
16h DMACHSRCSEL1 DMA Channel Trigger Source Select Register-1 EALLOW Go
18h DMACHSRCSEL2 DMA Channel Trigger Source Select Register-2 EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-132 shows the codes that are used for
access types in this section.
Table 3-132. DMA_CLA_SRC_SEL_REGS Access
Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.7.1 CLA1TASKSRCSELLOCK Register (Offset = 0h) [Reset = 0h]

CLA1TASKSRCSELLOCK is shown in Figure 3-123 and described in Table 3-133.
Return to the Summary Table.
CLA1 Task Trigger Source Select Lock Register
Figure 3-123. CLA1TASKSRCSELLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED CLA1TASKSRC CLA1TASKSRC
SEL2 SEL1
R-0-0h R/WSonce-0h R/WSonce-0h

Table 3-133. CLA1TASKSRCSELLOCK Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 CLA1TASKSRCSEL2 R/WSonce 0h CLA1TASKSRCSEL2 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn
0 CLA1TASKSRCSEL1 R/WSonce 0h CLA1TASKSRCSEL1 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn

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3.16.7.2 DMACHSRCSELLOCK Register (Offset = 4h) [Reset = 0h]

DMACHSRCSELLOCK is shown in Figure 3-124 and described in Table 3-134.
Return to the Summary Table.
DMA Channel Triger Source Select Lock Register
Figure 3-124. DMACHSRCSELLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMACHSRCSE DMACHSRCSE
L2 L1
R-0-0h R/WSonce-0h R/WSonce-0h

Table 3-134. DMACHSRCSELLOCK Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 DMACHSRCSEL2 R/WSonce 0h DMACHSRCSEL2 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn
0 DMACHSRCSEL1 R/WSonce 0h DMACHSRCSEL1 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn

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3.16.7.3 CLA1TASKSRCSEL1 Register (Offset = 6h) [Reset = 0h]

CLA1TASKSRCSEL1 is shown in Figure 3-125 and described in Table 3-135.
Return to the Summary Table.
CLA1 Task Trigger Source Select Register-1
Figure 3-125. CLA1TASKSRCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-135. CLA1TASKSRCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-24 TASK4 R/W 0h Selects the Trigger Source for TASK4 of CLA1
Reset type: SYSRSn
23-16 TASK3 R/W 0h Selects the Trigger Source for TASK3 of CLA1
Reset type: SYSRSn
15-8 TASK2 R/W 0h Selects the Trigger Source for TASK2 of CLA1
Reset type: SYSRSn
7-0 TASK1 R/W 0h Selects the Trigger Source for TASK1 of CLA1
Reset type: SYSRSn

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3.16.7.4 CLA1TASKSRCSEL2 Register (Offset = 8h) [Reset = 0h]

CLA1TASKSRCSEL2 is shown in Figure 3-126 and described in Table 3-136.
Return to the Summary Table.
CLA1 Task Trigger Source Select Register-2
Figure 3-126. CLA1TASKSRCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-136. CLA1TASKSRCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-24 TASK8 R/W 0h Selects the Trigger Source for TASK8 of CLA1
Reset type: SYSRSn
23-16 TASK7 R/W 0h Selects the Trigger Source for TASK7 of CLA1
Reset type: SYSRSn
15-8 TASK6 R/W 0h Selects the Trigger Source for TASK6 of CLA1
Reset type: SYSRSn
7-0 TASK5 R/W 0h Selects the Trigger Source for TASK5 of CLA1
Reset type: SYSRSn

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3.16.7.5 DMACHSRCSEL1 Register (Offset = 16h) [Reset = 0h]

DMACHSRCSEL1 is shown in Figure 3-127 and described in Table 3-137.
Return to the Summary Table.
DMA Channel Trigger Source Select Register-1
Figure 3-127. DMACHSRCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH4 CH3 CH2 CH1
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-137. DMACHSRCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-24 CH4 R/W 0h Selects the Trigger and Sync Source CH4 of DMA
Reset type: SYSRSn
23-16 CH3 R/W 0h Selects the Trigger and Sync Source CH3 of DMA
Reset type: SYSRSn
15-8 CH2 R/W 0h Selects the Trigger and Sync Source CH2 of DMA
Reset type: SYSRSn
7-0 CH1 R/W 0h Selects the Trigger and Sync Source CH1 of DMA
Reset type: SYSRSn

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3.16.7.6 DMACHSRCSEL2 Register (Offset = 18h) [Reset = 0h]

DMACHSRCSEL2 is shown in Figure 3-128 and described in Table 3-138.
Return to the Summary Table.
DMA Channel Trigger Source Select Register-2
Figure 3-128. DMACHSRCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CH6 CH5
R-0-0h R/W-0h R/W-0h

Table 3-138. DMACHSRCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 CH6 R/W 0h Selects the Trigger and Sync Source CH6 of DMA
Reset type: SYSRSn
7-0 CH5 R/W 0h Selects the Trigger and Sync Source CH5 of DMA
Reset type: SYSRSn

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3.16.8 MEM_CFG_REGS Registers

Table 3-139 lists the memory-mapped registers for the MEM_CFG_REGS registers. All register offset addresses
not listed in Table 3-139 should be considered as reserved locations and the register contents should not be
modified.
Table 3-139. MEM_CFG_REGS Registers
Offset Acronym Register Name Write Protection Section
0h DxLOCK Dedicated RAM Config Lock Register EALLOW Go
2h DxCOMMIT Dedicated RAM Config Lock Commit Register EALLOW Go
8h DxACCPROT0 Dedicated RAM Config Register EALLOW Go
10h DxTEST Dedicated RAM TEST Register Go
12h DxINIT Dedicated RAM Init Register EALLOW Go
14h DxINITDONE Dedicated RAM InitDone Status Register Go
16h DxRAMTEST_LOCK Lock register to Dx RAM TEST registers Go
20h LSxLOCK Local Shared RAM Config Lock Register EALLOW Go
22h LSxCOMMIT Local Shared RAM Config Lock Commit Register EALLOW Go
24h LSxMSEL Local Shared RAM Master Sel Register EALLOW Go
26h LSxCLAPGM Local Shared RAM Prog/Exe control Register EALLOW Go
28h LSxACCPROT0 Local Shared RAM Config Register 0 EALLOW Go
2Ah LSxACCPROT1 Local Shared RAM Config Register 1 EALLOW Go
30h LSxTEST Local Shared RAM TEST Register Go
32h LSxINIT Local Shared RAM Init Register EALLOW Go
34h LSxINITDONE Local Shared RAM InitDone Status Register Go
36h LSxRAMTEST_LOCK Lock register to LSx RAM TEST registers Go
40h GSxLOCK Global Shared RAM Config Lock Register EALLOW Go
42h GSxCOMMIT Global Shared RAM Config Lock Commit EALLOW Go
Register
48h GSxACCPROT0 Global Shared RAM Config Register 0 EALLOW Go
50h GSxTEST Global Shared RAM TEST Register Go
52h GSxINIT Global Shared RAM Init Register EALLOW Go
54h GSxINITDONE Global Shared RAM InitDone Status Register Go
56h GSxRAMTEST_LOCK Lock register to GSx RAM TEST registers Go
60h MSGxLOCK Message RAM Config Lock Register EALLOW Go
62h MSGxCOMMIT Message RAM Config Lock Commit Register EALLOW Go
70h MSGxTEST Message RAM TEST Register Go
72h MSGxINIT Message RAM Init Register EALLOW Go
74h MSGxINITDONE Message RAM InitDone Status Register Go
76h MSGxRAMTEST_LOCK Lock register for MSGx RAM TEST Register Go
A0h ROM_LOCK ROM Config Lock Register Go
A2h ROM_TEST ROM TEST Register Go
A4h ROM_FORCE_ERROR ROM Force Error register Go

Complex bit access types are encoded to fit into small table cells. Table 3-140 shows the codes that are used for
access types in this section.
Table 3-140. MEM_CFG_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read

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Table 3-140. MEM_CFG_REGS Access Type Codes

(continued)
Access Type Code Description
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.8.1 DxLOCK Register (Offset = 0h) [Reset = 0h]

DxLOCK is shown in Figure 3-129 and described in Table 3-141.
Return to the Summary Table.
Dedicated RAM Config Lock Register
Figure 3-129. DxLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED LOCK_M1 LOCK_M0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-141. DxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 LOCK_M1 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for M1 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed.
1: Write to ACCPROT, TEST, INIT and MSEL fields are blocked.
Reset type: SYSRSn
0 LOCK_M0 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for M0 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed.
1: Write to ACCPROT, TEST, INIT and MSEL fields are blocked.
Reset type: SYSRSn

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3.16.8.2 DxCOMMIT Register (Offset = 2h) [Reset = 0h]

DxCOMMIT is shown in Figure 3-130 and described in Table 3-142.
Return to the Summary Table.
Dedicated RAM Config Lock Commit Register
Figure 3-130. DxCOMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED COMMIT_M1 COMMIT_M0
R-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-142. DxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R/WSonce 0h Reserved
2 RESERVED R/WSonce 0h Reserved
1 COMMIT_M1 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for M1 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed
based on value of lock field in DxLOCK register.
1: Write to ACCPROT, TEST, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
0 COMMIT_M0 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for M0 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed
based on value of lock field in DxLOCK register.
1: Write to ACCPROT, TEST, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn

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3.16.8.3 DxACCPROT0 Register (Offset = 8h) [Reset = 0h]

DxACCPROT0 is shown in Figure 3-131 and described in Table 3-143.
Return to the Summary Table.
Dedicated RAM Config Register
Figure 3-131. DxACCPROT0 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED
R-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED CPUWRPROT_ FETCHPROT_
M1 M1
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CPUWRPROT_ FETCHPROT_
M0 M0
R-0h R/W-0h R/W-0h

Table 3-143. DxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23-18 RESERVED R 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-10 RESERVED R 0h Reserved
9 CPUWRPROT_M1 R/W 0h CPU WR Protection For M1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are block.
Reset type: SYSRSn
8 FETCHPROT_M1 R/W 0h Fetch Protection For M1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved
1 CPUWRPROT_M0 R/W 0h CPU WR Protection For M0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are block.
Reset type: SYSRSn
0 FETCHPROT_M0 R/W 0h Fetch Protection For M0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.16.8.4 DxTEST Register (Offset = 10h) [Reset = 0h]

DxTEST is shown in Figure 3-132 and described in Table 3-144.
Return to the Summary Table.
Dedicated RAM TEST Register
Figure 3-132. DxTEST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED TEST_M1 TEST_M0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-144. DxTEST Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7-6 RESERVED R/W 0h Reserved
5-4 RESERVED R/W 0h Reserved
3-2 TEST_M1 R/W 0h Selects the defferent modes for M1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
1-0 TEST_M0 R/W 0h Selects the defferent modes for M0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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3.16.8.5 DxINIT Register (Offset = 12h) [Reset = 0h]

DxINIT is shown in Figure 3-133 and described in Table 3-145.
Return to the Summary Table.
Dedicated RAM Init Register
Figure 3-133. DxINIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED INIT_M1 INIT_M0
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-145. DxINIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 RESERVED R-0/W1S 0h Reserved
1 INIT_M1 R-0/W1S 0h RAM Initialization control for M1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
0 INIT_M0 R-0/W1S 0h RAM Initialization control for M0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.16.8.6 DxINITDONE Register (Offset = 14h) [Reset = 0h]

DxINITDONE is shown in Figure 3-134 and described in Table 3-146.
Return to the Summary Table.
Dedicated RAM InitDone Status Register
Figure 3-134. DxINITDONE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED INITDONE_M1 INITDONE_M0
R-0h R-0h R-0h R-0h R-0h

Table 3-146. DxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 RESERVED R 0h Reserved
1 INITDONE_M1 R 0h RAM Initialization status for M1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization has completed.
Reset type: SYSRSn
0 INITDONE_M0 R 0h RAM Initialization status for M0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.16.8.7 DxRAMTEST_LOCK Register (Offset = 16h) [Reset = 0h]

DxRAMTEST_LOCK is shown in Figure 3-135 and described in Table 3-147.
Return to the Summary Table.
Lock register to Dx RAM TEST registers
Figure 3-135. DxRAMTEST_LOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESE RESE M1 M0
RVED RVED
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-147. DxRAMTEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-4 RESERVED R 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 M1 R/W 0h 0: Allows writes to DxTEST.TEST_M1 field.
1: Blocks writes to DxTEST.TEST_M1 field
Reset type: SYSRSn
0 M0 R/W 0h 0: Allows writes to DxTEST.TEST_M0 field.
1: Blocks writes to DxTEST.TEST_M0 field
Reset type: SYSRSn

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3.16.8.8 LSxLOCK Register (Offset = 20h) [Reset = 0h]

LSxLOCK is shown in Figure 3-136 and described in Table 3-148.
Return to the Summary Table.
Local Shared RAM Config Lock Register
Figure 3-136. LSxLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
LOCK_LS7 LOCK_LS6 LOCK_LS5 LOCK_LS4 LOCK_LS3 LOCK_LS2 LOCK_LS1 LOCK_LS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-148. LSxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7 LOCK_LS7 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS7
RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed.
1: Write to ACCPROT, TEST, INIT and MSEL fields are blocked.
Reset type: SYSRSn
6 LOCK_LS6 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS6
RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed.
1: Write to ACCPROT, TEST, INIT and MSEL fields are blocked.
Reset type: SYSRSn
5 LOCK_LS5 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS5
RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed.
1: Write to ACCPROT, TEST, INIT and MSEL fields are blocked.
Reset type: SYSRSn
4 LOCK_LS4 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS4
RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed.
1: Write to ACCPROT, TEST, INIT and MSEL fields are blocked.
Reset type: SYSRSn
3 LOCK_LS3 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS3
RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed.
1: Write to ACCPROT, TEST, INIT and MSEL fields are blocked.
Reset type: SYSRSn

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Table 3-148. LSxLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
2 LOCK_LS2 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS2
RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed.
1: Write to ACCPROT, TEST, INIT and MSEL fields are blocked.
Reset type: SYSRSn
1 LOCK_LS1 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS1
RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed.
1: Write to ACCPROT, TEST, INIT and MSEL fields are blocked.
Reset type: SYSRSn
0 LOCK_LS0 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS0
RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed.
1: Write to ACCPROT, TEST, INIT and MSEL fields are blocked.
Reset type: SYSRSn

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3.16.8.9 LSxCOMMIT Register (Offset = 22h) [Reset = 0h]

LSxCOMMIT is shown in Figure 3-137 and described in Table 3-149.
Return to the Summary Table.
Local Shared RAM Config Lock Commit Register
Figure 3-137. LSxCOMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
COMMIT_LS7 COMMIT_LS6 COMMIT_LS5 COMMIT_LS4 COMMIT_LS3 COMMIT_LS2 COMMIT_LS1 COMMIT_LS0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-149. LSxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7 COMMIT_LS7 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS7 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed
based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, TEST, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
6 COMMIT_LS6 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS6 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed
based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, TEST, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
5 COMMIT_LS5 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS5 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed
based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, TEST, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
4 COMMIT_LS4 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS4 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed
based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, TEST, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn

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Table 3-149. LSxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
3 COMMIT_LS3 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS3 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed
based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, TEST, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
2 COMMIT_LS2 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS2 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed
based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, TEST, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
1 COMMIT_LS1 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS1 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed
based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, TEST, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
0 COMMIT_LS0 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS0 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed
based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, TEST, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn

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3.16.8.10 LSxMSEL Register (Offset = 24h) [Reset = 0h]

LSxMSEL is shown in Figure 3-138 and described in Table 3-150.
Return to the Summary Table.
Local Shared RAM Master Sel Register
Figure 3-138. LSxMSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
MSEL_LS7 MSEL_LS6 MSEL_LS5 MSEL_LS4
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
MSEL_LS3 MSEL_LS2 MSEL_LS1 MSEL_LS0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-150. LSxMSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-14 MSEL_LS7 R/W 0h Master Select for LS7 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
13-12 MSEL_LS6 R/W 0h Master Select for LS6 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
11-10 MSEL_LS5 R/W 0h Master Select for LS5 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
9-8 MSEL_LS4 R/W 0h Master Select for LS4 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn

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Table 3-150. LSxMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 MSEL_LS3 R/W 0h Master Select for LS3 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
5-4 MSEL_LS2 R/W 0h Master Select for LS2 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
3-2 MSEL_LS1 R/W 0h Master Select for LS1 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
1-0 MSEL_LS0 R/W 0h Master Select for LS0 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn

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3.16.8.11 LSxCLAPGM Register (Offset = 26h) [Reset = 0h]

LSxCLAPGM is shown in Figure 3-139 and described in Table 3-151.
Return to the Summary Table.
Local Shared RAM Prog/Exe control Register
Figure 3-139. LSxCLAPGM Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
CLAPGM_LS7 CLAPGM_LS6 CLAPGM_LS5 CLAPGM_LS4 CLAPGM_LS3 CLAPGM_LS2 CLAPGM_LS1 CLAPGM_LS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-151. LSxCLAPGM Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7 CLAPGM_LS7 R/W 0h Selects LS7 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
6 CLAPGM_LS6 R/W 0h Selects LS6 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
5 CLAPGM_LS5 R/W 0h Selects LS5 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
4 CLAPGM_LS4 R/W 0h Selects LS4 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
3 CLAPGM_LS3 R/W 0h Selects LS3 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
2 CLAPGM_LS2 R/W 0h Selects LS2 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
1 CLAPGM_LS1 R/W 0h Selects LS1 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn

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Table 3-151. LSxCLAPGM Register Field Descriptions (continued)

Bit Field Type Reset Description
0 CLAPGM_LS0 R/W 0h Selects LS0 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn

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3.16.8.12 LSxACCPROT0 Register (Offset = 28h) [Reset = 0h]

LSxACCPROT0 is shown in Figure 3-140 and described in Table 3-152.
Return to the Summary Table.
Local Shared RAM Config Register 0
Figure 3-140. LSxACCPROT0 Register
31 30 29 28 27 26 25 24
RESERVED CPUWRPROT_ FETCHPROT_L
LS3 S3
R-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED CPUWRPROT_ FETCHPROT_L
LS2 S2
R-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED CPUWRPROT_ FETCHPROT_L
LS1 S1
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CPUWRPROT_ FETCHPROT_L
LS0 S0
R-0h R/W-0h R/W-0h

Table 3-152. LSxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R 0h Reserved
25 CPUWRPROT_LS3 R/W 0h CPU WR Protection For LS3 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_LS3 R/W 0h Fetch Protection For LS3 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-18 RESERVED R 0h Reserved
17 CPUWRPROT_LS2 R/W 0h CPU WR Protection For LS2 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_LS2 R/W 0h Fetch Protection For LS2 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved
9 CPUWRPROT_LS1 R/W 0h CPU WR Protection For LS1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_LS1 R/W 0h Fetch Protection For LS1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved

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Table 3-152. LSxACCPROT0 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 CPUWRPROT_LS0 R/W 0h CPU WR Protection For LS0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_LS0 R/W 0h Fetch Protection For LS0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.16.8.13 LSxACCPROT1 Register (Offset = 2Ah) [Reset = 0h]

LSxACCPROT1 is shown in Figure 3-141 and described in Table 3-153.
Return to the Summary Table.
Local Shared RAM Config Register 1
Figure 3-141. LSxACCPROT1 Register
31 30 29 28 27 26 25 24
RESERVED CPUWRPROT_ FETCHPROT_L
LS7 S7
R-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED CPUWRPROT_ FETCHPROT_L
LS6 S6
R-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED CPUWRPROT_ FETCHPROT_L
LS5 S5
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CPUWRPROT_ FETCHPROT_L
LS4 S4
R-0h R/W-0h R/W-0h

Table 3-153. LSxACCPROT1 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R 0h Reserved
25 CPUWRPROT_LS7 R/W 0h CPU WR Protection For LS7 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_LS7 R/W 0h Fetch Protection For LS7 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-18 RESERVED R 0h Reserved
17 CPUWRPROT_LS6 R/W 0h CPU WR Protection For LS6 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_LS6 R/W 0h Fetch Protection For LS6 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved
9 CPUWRPROT_LS5 R/W 0h CPU WR Protection For LS5 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_LS5 R/W 0h Fetch Protection For LS5 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved

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Table 3-153. LSxACCPROT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 CPUWRPROT_LS4 R/W 0h CPU WR Protection For LS4 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_LS4 R/W 0h Fetch Protection For LS4 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.16.8.14 LSxTEST Register (Offset = 30h) [Reset = 0h]

LSxTEST is shown in Figure 3-142 and described in Table 3-154.
Return to the Summary Table.
Local Shared RAM TEST Register
Figure 3-142. LSxTEST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
TEST_LS7 TEST_LS6 TEST_LS5 TEST_LS4
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
TEST_LS3 TEST_LS2 TEST_LS1 TEST_LS0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-154. LSxTEST Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-14 TEST_LS7 R/W 0h Selects the defferent modes for LS7 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
13-12 TEST_LS6 R/W 0h Selects the defferent modes for LS6 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
11-10 TEST_LS5 R/W 0h Selects the defferent modes for LS5 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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Table 3-154. LSxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
9-8 TEST_LS4 R/W 0h Selects the defferent modes for LS4 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
7-6 TEST_LS3 R/W 0h Selects the defferent modes for LS3 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
5-4 TEST_LS2 R/W 0h Selects the defferent modes for LS2 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
3-2 TEST_LS1 R/W 0h Selects the defferent modes for LS1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
1-0 TEST_LS0 R/W 0h Selects the defferent modes for LS0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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3.16.8.15 LSxINIT Register (Offset = 32h) [Reset = 0h]

LSxINIT is shown in Figure 3-143 and described in Table 3-155.
Return to the Summary Table.
Local Shared RAM Init Register
Figure 3-143. LSxINIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INIT_LS7 INIT_LS6 INIT_LS5 INIT_LS4 INIT_LS3 INIT_LS2 INIT_LS1 INIT_LS0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-155. LSxINIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7 INIT_LS7 R-0/W1S 0h RAM Initialization control for LS7 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
6 INIT_LS6 R-0/W1S 0h RAM Initialization control for LS6 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
5 INIT_LS5 R-0/W1S 0h RAM Initialization control for LS5 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
4 INIT_LS4 R-0/W1S 0h RAM Initialization control for LS4 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
3 INIT_LS3 R-0/W1S 0h RAM Initialization control for LS3 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
2 INIT_LS2 R-0/W1S 0h RAM Initialization control for LS2 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_LS1 R-0/W1S 0h RAM Initialization control for LS1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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Table 3-155. LSxINIT Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INIT_LS0 R-0/W1S 0h RAM Initialization control for LS0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.16.8.16 LSxINITDONE Register (Offset = 34h) [Reset = 0h]

LSxINITDONE is shown in Figure 3-144 and described in Table 3-156.
Return to the Summary Table.
Local Shared RAM InitDone Status Register
Figure 3-144. LSxINITDONE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INITDONE_LS7 INITDONE_LS6 INITDONE_LS5 INITDONE_LS4 INITDONE_LS3 INITDONE_LS2 INITDONE_LS1 INITDONE_LS0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-156. LSxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7 INITDONE_LS7 R 0h RAM Initialization status for LS7 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
6 INITDONE_LS6 R 0h RAM Initialization status for LS6 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
5 INITDONE_LS5 R 0h RAM Initialization status for LS5 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
4 INITDONE_LS4 R 0h RAM Initialization status for LS4 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
3 INITDONE_LS3 R 0h RAM Initialization status for LS3 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
2 INITDONE_LS2 R 0h RAM Initialization status for LS2 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_LS1 R 0h RAM Initialization status for LS1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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Table 3-156. LSxINITDONE Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INITDONE_LS0 R 0h RAM Initialization status for LS0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.16.8.17 LSxRAMTEST_LOCK Register (Offset = 36h) [Reset = 0h]

LSxRAMTEST_LOCK is shown in Figure 3-145 and described in Table 3-157.
Return to the Summary Table.
Lock register to LSx RAM TEST registers
Figure 3-145. LSxRAMTEST_LOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LS7 LS6 LS5 LS4 LS3 LS2 LS1 LS0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-157. LSxRAMTEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-8 RESERVED R 0h Reserved
7 LS7 R/W 0h 0: Allows writes to LSxTEST.TEST_LS7 field.
1: Blocks writes to LSxTEST.TEST_LS7 field.
Reset type: SYSRSn
6 LS6 R/W 0h 0: Allows writes to LSxTEST.TEST_LS6 field.
1: Blocks writes to LSxTEST.TEST_LS6 field.
Reset type: SYSRSn
5 LS5 R/W 0h 0: Allows writes to LSxTEST.TEST_LS5 field.
1: Blocks writes to LSxTEST.TEST_LS5 field.
Reset type: SYSRSn
4 LS4 R/W 0h 0: Allows writes to LSxTEST.TEST_LS4 field.
1: Blocks writes to LSxTEST.TEST_LS4 field.
Reset type: SYSRSn
3 LS3 R/W 0h 0: Allows writes to LSxTEST.TEST_LS3 field.
1: Blocks writes to LSxTEST.TEST_LS3 field.
Reset type: SYSRSn
2 LS2 R/W 0h 0: Allows writes to LSxTEST.TEST_LS2 field.
1: Blocks writes to LSxTEST.TEST_LS2 field.
Reset type: SYSRSn
1 LS1 R/W 0h 0: Allows writes to LSxTEST.TEST_LS1 field.
1: Blocks writes to LSxTEST.TEST_LS1 field.
Reset type: SYSRSn
0 LS0 R/W 0h 0: Allows writes to LSxTEST.TEST_LS0 field.
1: Blocks writes to LSxTEST.TEST_LS0 field.
Reset type: SYSRSn

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3.16.8.18 GSxLOCK Register (Offset = 40h) [Reset = 0h]

GSxLOCK is shown in Figure 3-146 and described in Table 3-158.
Return to the Summary Table.
Global Shared RAM Config Lock Register
Figure 3-146. GSxLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED LOCK_GS3 LOCK_GS2 LOCK_GS1 LOCK_GS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-158. GSxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 LOCK_GS3 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS3 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed.
1: Write to ACCPROT, TEST, INIT and MSEL fields are blocked.
Reset type: SYSRSn
2 LOCK_GS2 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS2 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed.
1: Write to ACCPROT, TEST, INIT and MSEL fields are blocked.
Reset type: SYSRSn
1 LOCK_GS1 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS1 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed.
1: Write to ACCPROT, TEST, INIT and MSEL fields are blocked.
Reset type: SYSRSn

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Table 3-158. GSxLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
0 LOCK_GS0 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS0 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed.
1: Write to ACCPROT, TEST, INIT and MSEL fields are blocked.
Reset type: SYSRSn

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3.16.8.19 GSxCOMMIT Register (Offset = 42h) [Reset = 0h]

GSxCOMMIT is shown in Figure 3-147 and described in Table 3-159.
Return to the Summary Table.
Global Shared RAM Config Lock Commit Register
Figure 3-147. GSxCOMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED COMMIT_GS3 COMMIT_GS2 COMMIT_GS1 COMMIT_GS0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-159. GSxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 RESERVED R/WSonce 0h Reserved
14 RESERVED R/WSonce 0h Reserved
13 RESERVED R/WSonce 0h Reserved
12 RESERVED R/WSonce 0h Reserved
11 RESERVED R/WSonce 0h Reserved
10 RESERVED R/WSonce 0h Reserved
9 RESERVED R/WSonce 0h Reserved
8 RESERVED R/WSonce 0h Reserved
7 RESERVED R/WSonce 0h Reserved
6 RESERVED R/WSonce 0h Reserved
5 RESERVED R/WSonce 0h Reserved
4 RESERVED R/WSonce 0h Reserved
3 COMMIT_GS3 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS3 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed
based on value of lock field in GSxLOCK register.
1: Write to ACCPROT, TEST, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
2 COMMIT_GS2 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS2 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed
based on value of lock field in GSxLOCK register.
1: Write to ACCPROT, TEST, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn

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Table 3-159. GSxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
1 COMMIT_GS1 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS1 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed
based on value of lock field in GSxLOCK register.
1: Write to ACCPROT, TEST, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn
0 COMMIT_GS0 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS0 RAM:
0: Write to ACCPROT, TEST, INIT and MSEL fields are allowed
based on value of lock field in GSxLOCK register.
1: Write to ACCPROT, TEST, INIT and MSEL fields are permanently
blocked.
Reset type: SYSRSn

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3.16.8.20 GSxACCPROT0 Register (Offset = 48h) [Reset = 0h]

GSxACCPROT0 is shown in Figure 3-148 and described in Table 3-160.
Return to the Summary Table.
Global Shared RAM Config Register 0
Figure 3-148. GSxACCPROT0 Register
31 30 29 28 27 26 25 24
RESERVED HICWRPROT_ DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS3 GS3 GS3 GS3
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED HICWRPROT_ DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS2 GS2 GS2 GS2
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED HICWRPROT_ DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS1 GS1 GS1 GS1
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED HICWRPROT_ DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS0 GS0 GS0 GS0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-160. GSxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27 HICWRPROT_GS3 R/W 0h HICA WR Protection For GS0 RAM:
0: HICA Writes are allowed.
1: HICA Writes are blocked.
Reset type: SYSRSn
26 DMAWRPROT_GS3 R/W 0h DMA WR Protection For GS3 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_GS3 R/W 0h CPU WR Protection For GS3 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_GS3 R/W 0h Fetch Protection For GS3 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-20 RESERVED R 0h Reserved
19 HICWRPROT_GS2 R/W 0h HICA WR Protection For GS0 RAM:
0: HICA Writes are allowed.
1: HICA Writes are blocked.
Reset type: SYSRSn
18 DMAWRPROT_GS2 R/W 0h DMA WR Protection For GS2 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

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Table 3-160. GSxACCPROT0 Register Field Descriptions (continued)

Bit Field Type Reset Description
17 CPUWRPROT_GS2 R/W 0h CPU WR Protection For GS2 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_GS2 R/W 0h Fetch Protection For GS2 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-12 RESERVED R 0h Reserved
11 HICWRPROT_GS1 R/W 0h HICA WR Protection For GS0 RAM:
0: HICA Writes are allowed.
1: HICA Writes are blocked.
Reset type: SYSRSn
10 DMAWRPROT_GS1 R/W 0h DMA WR Protection For GS1 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
9 CPUWRPROT_GS1 R/W 0h CPU WR Protection For GS1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_GS1 R/W 0h Fetch Protection For GS1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-4 RESERVED R 0h Reserved
3 HICWRPROT_GS0 R/W 0h HICA WR Protection For GS0 RAM:
0: HICA Writes are allowed.
1: HICA Writes are blocked.
Reset type: SYSRSn
2 DMAWRPROT_GS0 R/W 0h DMA WR Protection For GS0 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_GS0 R/W 0h CPU WR Protection For GS0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_GS0 R/W 0h Fetch Protection For GS0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.16.8.21 GSxTEST Register (Offset = 50h) [Reset = 0h]

GSxTEST is shown in Figure 3-149 and described in Table 3-161.
Return to the Summary Table.
Global Shared RAM TEST Register
Figure 3-149. GSxTEST Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
TEST_GS3 TEST_GS2 TEST_GS1 TEST_GS0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-161. GSxTEST Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 RESERVED R/W 0h Reserved
25-24 RESERVED R/W 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 RESERVED R/W 0h Reserved
17-16 RESERVED R/W 0h Reserved
15-14 RESERVED R/W 0h Reserved
13-12 RESERVED R/W 0h Reserved
11-10 RESERVED R/W 0h Reserved
9-8 RESERVED R/W 0h Reserved
7-6 TEST_GS3 R/W 0h Selects the defferent modes for GS3 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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Table 3-161. GSxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
5-4 TEST_GS2 R/W 0h Selects the defferent modes for GS2 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
3-2 TEST_GS1 R/W 0h Selects the defferent modes for GS1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
1-0 TEST_GS0 R/W 0h Selects the defferent modes for GS0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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3.16.8.22 GSxINIT Register (Offset = 52h) [Reset = 0h]

GSxINIT is shown in Figure 3-150 and described in Table 3-162.
Return to the Summary Table.
Global Shared RAM Init Register
Figure 3-150. GSxINIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED INIT_GS3 INIT_GS2 INIT_GS1 INIT_GS0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-162. GSxINIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 RESERVED R-0/W1S 0h Reserved
14 RESERVED R-0/W1S 0h Reserved
13 RESERVED R-0/W1S 0h Reserved
12 RESERVED R-0/W1S 0h Reserved
11 RESERVED R-0/W1S 0h Reserved
10 RESERVED R-0/W1S 0h Reserved
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R-0/W1S 0h Reserved
6 RESERVED R-0/W1S 0h Reserved
5 RESERVED R-0/W1S 0h Reserved
4 RESERVED R-0/W1S 0h Reserved
3 INIT_GS3 R-0/W1S 0h RAM Initialization control for GS3 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
2 INIT_GS2 R-0/W1S 0h RAM Initialization control for GS2 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_GS1 R-0/W1S 0h RAM Initialization control for GS1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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Table 3-162. GSxINIT Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INIT_GS0 R-0/W1S 0h RAM Initialization control for GS0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.16.8.23 GSxINITDONE Register (Offset = 54h) [Reset = 0h]

GSxINITDONE is shown in Figure 3-151 and described in Table 3-163.
Return to the Summary Table.
Global Shared RAM InitDone Status Register
Figure 3-151. GSxINITDONE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS
3 2 1 0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-163. GSxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 RESERVED R 0h Reserved
14 RESERVED R 0h Reserved
13 RESERVED R 0h Reserved
12 RESERVED R 0h Reserved
11 RESERVED R 0h Reserved
10 RESERVED R 0h Reserved
9 RESERVED R 0h Reserved
8 RESERVED R 0h Reserved
7 RESERVED R 0h Reserved
6 RESERVED R 0h Reserved
5 RESERVED R 0h Reserved
4 RESERVED R 0h Reserved
3 INITDONE_GS3 R 0h RAM Initialization status for GS3 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
2 INITDONE_GS2 R 0h RAM Initialization status for GS2 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_GS1 R 0h RAM Initialization status for GS1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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Table 3-163. GSxINITDONE Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INITDONE_GS0 R 0h RAM Initialization status for GS0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.16.8.24 GSxRAMTEST_LOCK Register (Offset = 56h) [Reset = 0h]

GSxRAMTEST_LOCK is shown in Figure 3-152 and described in Table 3-164.
Return to the Summary Table.
Lock register to GSx RAM TEST registers
Figure 3-152. GSxRAMTEST_LOCK Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED GS3 GS2 GS1 GS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-164. GSxRAMTEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15 RESERVED R/W 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 GS3 R/W 0h 0: Allows writes to GSxTEST.TEST_GS3 field.
1: Blocks writes to GSxTEST.TEST_GS3 field.
Reset type: SYSRSn
2 GS2 R/W 0h 0: Allows writes to GSxTEST.TEST_GS2 field.
1: Blocks writes to GSxTEST.TEST_GS2 field.
Reset type: SYSRSn
1 GS1 R/W 0h 0: Allows writes to GSxTEST.TEST_GS1 field.
1: Blocks writes to GSxTEST.TEST_GS1 field.
Reset type: SYSRSn
0 GS0 R/W 0h 0: Allows writes to GSxTEST.TEST_GS0 field.
1: Blocks writes to GSxTEST.TEST_GS0 field.
Reset type: SYSRSn

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3.16.8.25 MSGxLOCK Register (Offset = 60h) [Reset = 0h]

MSGxLOCK is shown in Figure 3-153 and described in Table 3-165.
Return to the Summary Table.
Message RAM Config Lock Register
Figure 3-153. MSGxLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED LOCK_DMATO LOCK_CLA1TO RESERVED RESERVED LOCK_CLA1TO LOCK_CPUTO RESERVED
CLA1 DMA CPU CLA1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-165. MSGxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 LOCK_DMATOCLA1 R/W 0h Locks the write to access protection, master select, initialization
control and test for DMATOCLA1 RAM:
0: Write to TEST, INIT fields are allowed.
1: Write to TEST, INIT fields are blocked.
Reset type: SYSRSn
5 LOCK_CLA1TODMA R/W 0h Locks the write to access protection, master select, initialization
control and test for CLA1TODMA RAM:
0: Write to TEST, INIT fields are allowed.
1: Write to TEST, INIT fields are blocked.
Reset type: SYSRSn
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 LOCK_CLA1TOCPU R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for CLA1TOCPU RAM:
0: Write to TEST, INIT fields are allowed.
1: Write to TEST, INIT fields are blocked.
Reset type: SYSRSn
1 LOCK_CPUTOCLA1 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for CPUTOCLA1 RAM:
0: Write to TEST, INIT fields are allowed.
1: Write to TEST, INIT fields are blocked.
Reset type: SYSRSn
0 RESERVED R/W 0h Reserved

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3.16.8.26 MSGxCOMMIT Register (Offset = 62h) [Reset = 0h]

MSGxCOMMIT is shown in Figure 3-154 and described in Table 3-166.
Return to the Summary Table.
Message RAM Config Lock Commit Register
Figure 3-154. MSGxCOMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
RESERVED COMMIT_DMA COMMIT_CLA1 RESERVED RESERVED COMMIT_CLA1 COMMIT_CPU RESERVED
TOCLA1 TODMA TOCPU TOCLA1
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-166. MSGxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
11 RESERVED R/WSonce 0h Reserved
10 RESERVED R/WSonce 0h Reserved
9 RESERVED R/WSonce 0h Reserved
8 RESERVED R/WSonce 0h Reserved
7 RESERVED R/WSonce 0h Reserved
6 COMMIT_DMATOCLA1 R/WSonce 0h Locks the write to access protection, master select, initialization
control and test register fields for DMATOCLA1 RAM:
0: Write to TEST, INIT fields are allowed based on value of
corresponding lock field in MSGxLOCK register.
1: Write to TEST, INIT fields are permanently blocked.
Reset type: SYSRSn
5 COMMIT_CLA1TODMA R/WSonce 0h Locks the write to access protection, master select, initialization
control and test register fields for CLA1TODMA RAM:
0: Write to TEST, INIT fields are allowed based on value of
corresponding lock field in MSGxLOCK register.
1: Write to TEST, INIT fields are permanently blocked.
Reset type: SYSRSn
4 RESERVED R/WSonce 0h Reserved
3 RESERVED R/WSonce 0h Reserved
2 COMMIT_CLA1TOCPU R/WSonce 0h Locks the write to access protection, master select, initialization
control and test register fields for CLA1TOCPU RAM:
0: Write to TEST, INIT fields are allowed based on value of
corresponding lock field in MSGxLOCK register.
1: Write to TEST, INIT fields are permanently blocked.
Reset type: SYSRSn

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Table 3-166. MSGxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
1 COMMIT_CPUTOCLA1 R/WSonce 0h Locks the write to access protection, master select, initialization
control and test register fields for CPUTOCLA1 RAM:
0: Write to TEST, INIT fields are allowed based on value of
corresponding lock field in MSGxLOCK register.
1: Write to TEST, INIT fields are permanently blocked.
Reset type: SYSRSn
0 RESERVED R/WSonce 0h Reserved

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3.16.8.27 MSGxTEST Register (Offset = 70h) [Reset = 0h]

MSGxTEST is shown in Figure 3-155 and described in Table 3-167.
Return to the Summary Table.
Message RAM TEST Register
Figure 3-155. MSGxTEST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED TEST_DMATOCLA1 TEST_CLA1TODMA RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED TEST_CLA1TOCPU TEST_CPUTOCLA1 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-167. MSGxTEST Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 RESERVED R/W 0h Reserved
17-16 RESERVED R/W 0h Reserved
15-14 RESERVED R/W 0h Reserved
13-12 TEST_DMATOCLA1 R/W 0h Selects the defferent modes for DMATOCLA1 MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
11-10 TEST_CLA1TODMA R/W 0h Selects the defferent modes for CLA1TODMA MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
9-8 RESERVED R/W 0h Reserved
7-6 RESERVED R/W 0h Reserved

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Table 3-167. MSGxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
5-4 TEST_CLA1TOCPU R/W 0h Selects the defferent modes for CLA1TOCPU MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
3-2 TEST_CPUTOCLA1 R/W 0h Selects the defferent modes for CPUTOCLA1 MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/NMI is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
1-0 RESERVED R/W 0h Reserved

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3.16.8.28 MSGxINIT Register (Offset = 72h) [Reset = 0h]

MSGxINIT is shown in Figure 3-156 and described in Table 3-168.
Return to the Summary Table.
Message RAM Init Register
Figure 3-156. MSGxINIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED INIT_DMATOCL INIT_CLA1TOD RESERVED RESERVED INIT_CLA1TOC INIT_CPUTOCL RESERVED
A1 MA PU A1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-168. MSGxINIT Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
11 RESERVED R-0/W1S 0h Reserved
10 RESERVED R-0/W1S 0h Reserved
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R-0/W1S 0h Reserved
6 INIT_DMATOCLA1 R-0/W1S 0h RAM Initialization control for DMATOCLA1 MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
5 INIT_CLA1TODMA R-0/W1S 0h RAM Initialization control for CLA1TODMA MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
4 RESERVED R-0/W1S 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 INIT_CLA1TOCPU R-0/W1S 0h RAM Initialization control for CLA1TOCPU MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_CPUTOCLA1 R-0/W1S 0h RAM Initialization control for CPUTOCLA1 MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
0 RESERVED R-0/W1S 0h Reserved

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3.16.8.29 MSGxINITDONE Register (Offset = 74h) [Reset = 0h]

MSGxINITDONE is shown in Figure 3-157 and described in Table 3-169.
Return to the Summary Table.
Message RAM InitDone Status Register
Figure 3-157. MSGxINITDONE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED INITDONE_DM INITDONE_CL RESERVED RESERVED INITDONE_CL INITDONE_CP RESERVED
ATOCLA1 A1TODMA A1TOCPU UTOCLA1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-169. MSGxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
11 RESERVED R 0h Reserved
10 RESERVED R 0h Reserved
9 RESERVED R 0h Reserved
8 RESERVED R 0h Reserved
7 RESERVED R 0h Reserved
6 INITDONE_DMATOCLA1 R 0h RAM Initialization status for DMATOCLA1 MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
5 INITDONE_CLA1TODMA R 0h RAM Initialization status for CLA1TODMA MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 INITDONE_CLA1TOCPU R 0h RAM Initialization status for CLA1TOCPU MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_CPUTOCLA1 R 0h RAM Initialization status for CPUTOCLA1 MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
0 RESERVED R 0h Reserved

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3.16.8.30 MSGxRAMTEST_LOCK Register (Offset = 76h) [Reset = 0h]

MSGxRAMTEST_LOCK is shown in Figure 3-158 and described in Table 3-170.
Return to the Summary Table.
Lock register for MSGx RAM TEST Register
Figure 3-158. MSGxRAMTEST_LOCK Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED DMATOCLA1 CLA1TODMA RESERVED RESERVED CLA1TOCPU CPUTOCLA1 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-170. MSGxRAMTEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-12 RESERVED R 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 DMATOCLA1 R/W 0h 0: Allows writes to MSGxTEST.TEST_DMATOCLA1 field
1: Blocks writes to MSGxTEST.TEST_DMATOCLA1 field
Reset type: SYSRSn
5 CLA1TODMA R/W 0h 0: Allows writes to MSGxTEST.TEST_CLA1TODMA field
1: Blocks writes to MSGxTEST.TEST_CLA1TODMA field
Reset type: SYSRSn
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 CLA1TOCPU R/W 0h 0: Allows writes to MSGxTEST.TEST_CLA1TOCPU field
1: Blocks writes to MSGxTEST.TEST_CLA1TOCPU field
Reset type: SYSRSn
1 CPUTOCLA1 R/W 0h 0: Allows writes to MSGxTEST.TEST_CPUTOCLA1 field
1: Blocks writes to MSGxTEST.TEST_CPUTOCLA1 field
Reset type: SYSRSn
0 RESERVED R/W 0h Reserved

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3.16.8.31 ROM_LOCK Register (Offset = A0h) [Reset = 0h]

ROM_LOCK is shown in Figure 3-159 and described in Table 3-171.
Return to the Summary Table.
ROM Config Lock Register
Figure 3-159. ROM_LOCK Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED LOCK_CLAPR LOCK_CLADAT LOCK_SECUR LOCK_BOOTR
OGROM AROM EROM OM
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-171. ROM_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-4 RESERVED R 0h Reserved
3 LOCK_CLAPROGROM R/W 0h Locks write access to test control fields (TEST and
FORCE_ERROR) of CLAPROGROM
0: Write access allowed
1: Write access blocked
Reset type: SYSRSn
2 LOCK_CLADATAROM R/W 0h Locks write access to test control fields (TEST and
FORCE_ERROR) of CLADATAROM
0: Write access allowed
1: Write access blocked
Reset type: SYSRSn
1 LOCK_SECUREROM R/W 0h Locks write access to test control fields (TEST and
FORCE_ERROR) of SECUREROM
0: Write access allowed
1: Write access blocked
Reset type: SYSRSn
0 LOCK_BOOTROM R/W 0h Locks write access to test control fields (TEST and
FORCE_ERROR) of BOOTROM
0: Write access allowed
1: Write access blocked
Reset type: SYSRSn

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3.16.8.32 ROM_TEST Register (Offset = A2h) [Reset = 0h]

ROM_TEST is shown in Figure 3-160 and described in Table 3-172.
Return to the Summary Table.
ROM TEST Register
Figure 3-160. ROM_TEST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
TEST_CLAPROGROM TEST_CLADATAROM TEST_SECUREROM TEST_BOOTROM
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-172. ROM_TEST Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R 0h Reserved
7-6 TEST_CLAPROGROM R/W 0h Selects the different modes for CLAPROGROM:
00: Functional Mode.
01: same as "00" but Parity check on data read is disabled (for
debug)
10: Parity Bits are visible on memory map (for debug)
11: Same as "00" but NMI is not generated on errors, used for
diagnostics. (for diagnostics)
Reset type: SYSRSn
5-4 TEST_CLADATAROM R/W 0h Selects the different modes for CLADATAROM:
00: Functional Mode.
01: same as "00" but Parity check on data read is disabled (for
debug)
10: Parity Bits are visible on memory map (for debug)
11: Same as "00" but NMI is not generated on errors, used for
diagnostics. (for diagnostics)
Reset type: SYSRSn
3-2 TEST_SECUREROM R/W 0h Selects the different modes for SECUREROM:
00: Functional Mode.
01: same as "00" but Parity check on data read is disabled (for
debug)
10: Parity Bits are visible on memory map (for debug)
11: Same as "00" but NMI is not generated on errors, used for
diagnostics. (for diagnostics)
Reset type: SYSRSn
1-0 TEST_BOOTROM R/W 0h Selects the different modes for BOOTROM:
00: Functional Mode.
01: same as "00" but Parity check on data read is disabled (for
debug)
10: Parity Bits are visible on memory map (for debug)
11: Same as "00" but NMI is not generated on errors, used for
diagnostics. (for diagnostics)
Reset type: SYSRSn

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3.16.8.33 ROM_FORCE_ERROR Register (Offset = A4h) [Reset = 0h]

ROM_FORCE_ERROR is shown in Figure 3-161 and described in Table 3-173.
Return to the Summary Table.
ROM Force Error register
Figure 3-161. ROM_FORCE_ERROR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED FORCE_CLAP FORCE_CLAD FORCE_SECU FORCE_BOOT
ROGROM_ER ATAROM_ERR REROM_ERRO ROM_ERROR
ROR OR R
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-173. ROM_FORCE_ERROR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 FORCE_CLAPROGROM_ R/W 0h Force parity error by feeding inverted Parity bit to Parity checking
ERROR logic.
Reset type: SYSRSn
2 FORCE_CLADATAROM_ R/W 0h Force parity error by feeding inverted Parity bit to Parity checking
ERROR logic.
Reset type: SYSRSn
1 FORCE_SECUREROM_E R/W 0h Force parity error by feeding inverted Parity bit to Parity checking
RROR logic.
Reset type: SYSRSn
0 FORCE_BOOTROM_ERR R/W 0h Force parity error by feeding inverted Parity bit to Parity checking
OR logic.
Reset type: SYSRSn

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3.16.9 MEMORY_ERROR_REGS Registers

Table 3-174 lists the memory-mapped registers for the MEMORY_ERROR_REGS registers. All register offset
addresses not listed in Table 3-174 should be considered as reserved locations and the register contents should
not be modified.
Table 3-174. MEMORY_ERROR_REGS Registers
Offset Acronym Register Name Write Protection Section
0h UCERRFLG Uncorrectable Error Flag Register Go
2h UCERRSET Uncorrectable Error Flag Set Register EALLOW Go
4h UCERRCLR Uncorrectable Error Flag Clear Register EALLOW Go
6h UCCPUREADDR Uncorrectable CPU Read Error Address Go
8h UCDMAREADDR Uncorrectable DMA Read Error Address Go
Ah UCCLA1READDR Uncorrectable CLA1 Read Error Address Go
10h UCHICAREADDR Uncorrectable HICA Read Error Address Go
20h CERRFLG Correctable Error Flag Register Go
22h CERRSET Correctable Error Flag Set Register EALLOW Go
24h CERRCLR Correctable Error Flag Clear Register EALLOW Go
26h CCPUREADDR Correctable CPU Read Error Address Go
28h CDMAREADDR Correctable DMA Read Error Address Go
2Ah CCLA1READDR Correctable CLA1 Read Error Address Go
2Eh CERRCNT Correctable Error Count Register Go
30h CERRTHRES Correctable Error Threshold Value Register EALLOW Go
32h CEINTFLG Correctable Error Interrupt Flag Status Register Go
34h CEINTCLR Correctable Error Interrupt Flag Clear Register EALLOW Go
36h CEINTSET Correctable Error Interrupt Flag Set Register EALLOW Go
38h CEINTEN Correctable Error Interrupt Enable Register EALLOW Go
3Ah CHICREADDR Correctable HIC Read Error Address Go

Complex bit access types are encoded to fit into small table cells. Table 3-175 shows the codes that are used for
access types in this section.
Table 3-175. MEMORY_ERROR_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables

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Table 3-175. MEMORY_ERROR_REGS Access Type

Codes (continued)
Access Type Code Description
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.9.1 UCERRFLG Register (Offset = 0h) [Reset = 0h]

UCERRFLG is shown in Figure 3-162 and described in Table 3-176.
Return to the Summary Table.
Uncorrectable Error Flag Register
Figure 3-162. UCERRFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED HICARDERR RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-176. UCERRFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-6 RESERVED R 0h Reserved
5 HICARDERR R 0h HICA Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during HICA read.
Reset type: SYSRSn
4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 CLA1RDERR R 0h CLA1 Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during CLA1 read.
Reset type: SYSRSn
1 DMARDERR R 0h DMA Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during DMA read.
Reset type: SYSRSn
0 CPURDERR R 0h CPU Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during CPU read.
Reset type: SYSRSn

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3.16.9.2 UCERRSET Register (Offset = 2h) [Reset = 0h]

UCERRSET is shown in Figure 3-163 and described in Table 3-177.
Return to the Summary Table.
Uncorrectable Error Flag Set Register
Figure 3-163. UCERRSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED HICARDERR RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0/W1S-0h R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-177. UCERRSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-6 RESERVED R 0h Reserved
5 HICARDERR R-0/W1S 0h 0: No action.
1: HICA Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
4 RESERVED R 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn

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3.16.9.3 UCERRCLR Register (Offset = 4h) [Reset = 0h]

UCERRCLR is shown in Figure 3-164 and described in Table 3-178.
Return to the Summary Table.
Uncorrectable Error Flag Clear Register
Figure 3-164. UCERRCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED HICARDERR RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0/W1S-0h R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-178. UCERRCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-6 RESERVED R 0h Reserved
5 HICARDERR R-0/W1S 0h 0: No action.
1: HICA Read Error Flag in UCERRFLG register will be cleared.
Reset type: SYSRSn
4 RESERVED R 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in UCERRFLG register will be cleared.
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in UCERRFLG register will be cleared .
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in UCERRFLG register will be cleared.
Reset type: SYSRSn

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3.16.9.4 UCCPUREADDR Register (Offset = 6h) [Reset = 0h]

UCCPUREADDR is shown in Figure 3-165 and described in Table 3-179.
Return to the Summary Table.
Uncorrectable CPU Read Error Address
Figure 3-165. UCCPUREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCCPUREADDR
R-0h

Table 3-179. UCCPUREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCCPUREADDR R 0h This register captures the address location for which CPU read/fetch
access resulted in uncorrectable ECC/Parity error.
Reset type: SYSRSn

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3.16.9.5 UCDMAREADDR Register (Offset = 8h) [Reset = 0h]

UCDMAREADDR is shown in Figure 3-166 and described in Table 3-180.
Return to the Summary Table.
Uncorrectable DMA Read Error Address
Figure 3-166. UCDMAREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCDMAREADDR
R-0h

Table 3-180. UCDMAREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCDMAREADDR R 0h This register captures the address location for which DMA read
access resulted in uncorrectable Parity error.
Reset type: SYSRSn

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3.16.9.6 UCCLA1READDR Register (Offset = Ah) [Reset = 0h]

UCCLA1READDR is shown in Figure 3-167 and described in Table 3-181.
Return to the Summary Table.
Uncorrectable CLA1 Read Error Address
Figure 3-167. UCCLA1READDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCCLA1READDR
R-0h

Table 3-181. UCCLA1READDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCCLA1READDR R 0h This register captures the address location for which CLA1 read/
fetch access resulted in uncorrectable Parity error.
Reset type: SYSRSn

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3.16.9.7 UCHICAREADDR Register (Offset = 10h) [Reset = 0h]

UCHICAREADDR is shown in Figure 3-168 and described in Table 3-182.
Return to the Summary Table.
Uncorrectable HICA Read Error Address
Figure 3-168. UCHICAREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCHICAREADDR
R-0h

Table 3-182. UCHICAREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCHICAREADDR R 0h This register captures the address location for which HICA read
access resulted in uncorrectable ECC/Parity error.
Reset type: SYSRSn

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3.16.9.8 CERRFLG Register (Offset = 20h) [Reset = 0h]

CERRFLG is shown in Figure 3-169 and described in Table 3-183.
Return to the Summary Table.
Correctable Error Flag Register
Figure 3-169. CERRFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED HICRDERR RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-183. CERRFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-6 RESERVED R 0h Reserved
5 HICRDERR R 0h HIC Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during HIC read.
Reset type: SYSRSn
4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 CLA1RDERR R 0h CLA1 Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during CLA1 read.
Reset type: SYSRSn
1 DMARDERR R 0h DMA Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during DMA read.
Reset type: SYSRSn
0 CPURDERR R 0h CPU Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during CPU read.
Reset type: SYSRSn

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3.16.9.9 CERRSET Register (Offset = 22h) [Reset = 0h]

CERRSET is shown in Figure 3-170 and described in Table 3-184.
Return to the Summary Table.
Correctable Error Flag Set Register
Figure 3-170. CERRSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED HICRDERR RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-184. CERRSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-6 RESERVED R 0h Reserved
5 HICRDERR R-0/W1S 0h 0: No action.
1: HIC Read Error Flag in CERRFLG register will be set and interrupt
will be generated if enabled..
Reset type: SYSRSn
4 RESERVED R-0/W1S 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn

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3.16.9.10 CERRCLR Register (Offset = 24h) [Reset = 0h]

CERRCLR is shown in Figure 3-171 and described in Table 3-185.
Return to the Summary Table.
Correctable Error Flag Clear Register
Figure 3-171. CERRCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED HICRDERR RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-185. CERRCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-6 RESERVED R 0h Reserved
5 HICRDERR R-0/W1S 0h 0: No action.
1: HIC Read Error Flag in CERRFLG register will be cleared.
Reset type: SYSRSn
4 RESERVED R-0/W1S 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in CERRFLG register will be cleared.
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in CERRFLG register will be cleared .
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in CERRFLG register will be cleared.
Reset type: SYSRSn

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3.16.9.11 CCPUREADDR Register (Offset = 26h) [Reset = 0h]

CCPUREADDR is shown in Figure 3-172 and described in Table 3-186.
Return to the Summary Table.
Correctable CPU Read Error Address
Figure 3-172. CCPUREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCPUREADDR
R-0h

Table 3-186. CCPUREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 CCPUREADDR R 0h This register captures the address location for which CPU read/fetch
access resulted in correctable ECC error.
Reset type: SYSRSn

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3.16.9.12 CDMAREADDR Register (Offset = 28h) [Reset = 0h]

CDMAREADDR is shown in Figure 3-173 and described in Table 3-187.
Return to the Summary Table.
Correctable DMA Read Error Address
Figure 3-173. CDMAREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDMAREADDR
R-0h

Table 3-187. CDMAREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 CDMAREADDR R 0h This register captures the address location for which DMA read
access resulted in correctable ECC error.
Reset type: SYSRSn

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3.16.9.13 CCLA1READDR Register (Offset = 2Ah) [Reset = 0h]

CCLA1READDR is shown in Figure 3-174 and described in Table 3-188.
Return to the Summary Table.
Correctable CLA1 Read Error Address
Figure 3-174. CCLA1READDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCLA1READDR
R-0h

Table 3-188. CCLA1READDR Register Field Descriptions

Bit Field Type Reset Description
31-0 CCLA1READDR R 0h This register captures the address location for which CLA1 read/
fetch access resulted in correctable ECC error.
Reset type: SYSRSn

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3.16.9.14 CERRCNT Register (Offset = 2Eh) [Reset = 0h]

CERRCNT is shown in Figure 3-175 and described in Table 3-189.
Return to the Summary Table.
Correctable Error Count Register
Figure 3-175. CERRCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CERRCNT
R-0h

Table 3-189. CERRCNT Register Field Descriptions

Bit Field Type Reset Description
31-0 CERRCNT R 0h This register holds the count of how many times correctable error
occurred.
Reset type: SYSRSn

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3.16.9.15 CERRTHRES Register (Offset = 30h) [Reset = 0h]

CERRTHRES is shown in Figure 3-176 and described in Table 3-190.
Return to the Summary Table.
Correctable Error Threshold Value Register
Figure 3-176. CERRTHRES Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CERRTHRES
R-0h R/W-0h

Table 3-190. CERRTHRES Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 CERRTHRES R/W 0h When value in CERRCNT register is greater than value configured in
this register, corretable interrupt gets generated, if enabled.
Reset type: SYSRSn

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3.16.9.16 CEINTFLG Register (Offset = 32h) [Reset = 0h]

CEINTFLG is shown in Figure 3-177 and described in Table 3-191.
Return to the Summary Table.
Correctable Error Interrupt Flag Status Register
Figure 3-177. CEINTFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CEINTFLAG
R-0h R-0h

Table 3-191. CEINTFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTFLAG R 0h Total corrected error count exceeded threshold Flag
0: Total correctable errors < Threshold value configured in
CERRTHRES register.
1: Total correctable errors >= Threshold value configured in
CERRTHRES register.
Reset type: SYSRSn

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3.16.9.17 CEINTCLR Register (Offset = 34h) [Reset = 0h]

CEINTCLR is shown in Figure 3-178 and described in Table 3-192.
Return to the Summary Table.
Correctable Error Interrupt Flag Clear Register
Figure 3-178. CEINTCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CEINTCLR
R-0h R-0/W1S-0h

Table 3-192. CEINTCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTCLR R-0/W1S 0h 0: No action.
1: Total corrected error count exceeded flag in CEINTFLG register
will be cleared.
Reset type: SYSRSn

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3.16.9.18 CEINTSET Register (Offset = 36h) [Reset = 0h]

CEINTSET is shown in Figure 3-179 and described in Table 3-193.
Return to the Summary Table.
Correctable Error Interrupt Flag Set Register
Figure 3-179. CEINTSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CEINTSET
R-0h R-0/W1S-0h

Table 3-193. CEINTSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTSET R-0/W1S 0h 0: No action.
1: Total corrected error count exceeded flag in CEINTFLG register
will be set and interrupt will be generated if enabled.
Reset type: SYSRSn

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3.16.9.19 CEINTEN Register (Offset = 38h) [Reset = 0h]

CEINTEN is shown in Figure 3-180 and described in Table 3-194.
Return to the Summary Table.
Correctable Error Interrupt Enable Register
Figure 3-180. CEINTEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CEINTEN
R-0h R/W-0h

Table 3-194. CEINTEN Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTEN R/W 0h 0: Correctable Error Interrupt is disabled.
1: Correctable Error Interrupt is enabled.
Reset type: SYSRSn

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3.16.9.20 CHICREADDR Register (Offset = 3Ah) [Reset = 0h]

CHICREADDR is shown in Figure 3-181 and described in Table 3-195.
Return to the Summary Table.
Correctable HIC Read Error Address
Figure 3-181. CHICREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHICREADDR
R-0h

Table 3-195. CHICREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 CHICREADDR R 0h This register captures the address location for which HIC read
access resulted in correctable ECC error.
Reset type: SYSRSn

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3.16.10 NMI_INTRUPT_REGS Registers

Table 3-196 lists the memory-mapped registers for the NMI_INTRUPT_REGS registers. All register offset
addresses not listed in Table 3-196 should be considered as reserved locations and the register contents should
not be modified.
Table 3-196. NMI_INTRUPT_REGS Registers
Offset Acronym Register Name Write Protection Section
0h NMICFG NMI Configuration Register EALLOW Go
1h NMIFLG NMI Flag Register (SYSRsn Clear) Go
2h NMIFLGCLR NMI Flag Clear Register EALLOW Go
3h NMIFLGFRC NMI Flag Force Register EALLOW Go
4h NMIWDCNT NMI Watchdog Counter Register Go
5h NMIWDPRD NMI Watchdog Period Register EALLOW Go
6h NMISHDFLG NMI Shadow Flag Register Go
7h ERRORSTS Error pin status Go
8h ERRORSTSCLR ERRORSTS clear register EALLOW Go
9h ERRORSTSFRC ERRORSTS force register EALLOW Go
Ah ERRORCTL Error pin control register EALLOW Go
Bh ERRORLOCK Lock register to Error pin registers. EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-197 shows the codes that are used for
access types in this section.
Table 3-197. NMI_INTRUPT_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.10.1 NMICFG Register (Offset = 0h) [Reset = 0h]

NMICFG is shown in Figure 3-182 and described in Table 3-198.
Return to the Summary Table.
NMI Configuration Register
Figure 3-182. NMICFG Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED NMIE
R-0h R/W1S-0h

Table 3-198. NMICFG Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R 0h Reserved
0 NMIE R/W1S 0h When set to 1 any condition will generate an NMI interrupt to the
C28 CPU and kick off the NMI watchdog counter. As part of boot
sequence this bit should be set after the device security related
initialization is complete.
0 NMI disabled
1 NMI enabled
Reset type: SYSRSn

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3.16.10.2 NMIFLG Register (Offset = 1h) [Reset = 0h]

NMIFLG is shown in Figure 3-183 and described in Table 3-199.
Return to the Summary Table.
NMI Flag Register (SYSRsn Clear)
Figure 3-183. NMIFLG Register
15 14 13 12 11 10 9 8
RESERVED CRC_FAIL SWERR RESERVED RESERVED RESERVED RESERVED CLBNMI
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
SYSDBGNMI RESERVED RESERVED CPU1HWBISTE FLUNCERR RAMUNCERR CLOCKFAIL NMIINT
RR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-199. NMIFLG Register Field Descriptions

Bit Field Type Reset Description
15 RESERVED R 0h Reserved
14 CRC_FAIL R 0h 0 Background CRC check on memories has not failed.
1 Background CRC check on memories has failed.
Reset type: SYSRSn
13 SWERR R 0h SW Error Force NMI Flag: This bit indicates if an NMI was forced
through the NMIFLGFRC register. This bit can only be cleared by the
user writing to the respective bit in the NMIFLGCLR register or by an
SYSRSn reset:
0 No SW Error force Generated
1 SW Error NMI is forced by SW.
No further NMI pulses are generated until this flag is cleared by the
user.
Reset type: SYSRSn
12 RESERVED R 0h Reserved
11 RESERVED R 0h Reserved
10 RESERVED R 0h Reserved
9 RESERVED R 0h Reserved
8 CLBNMI R 0h Reconfigurable Logic NMI Flag: This bit indicates if an NMI was
generated by the Reconfigurable Logic. This bit can only be cleared
by the user writing to the corresponding clear bit in the NMIFLGCLR
register or by SYSRSn reset:
0,No Reconfigurable Logic NMI pending
1,Reconfigurable Logic NMI generated
Reset type: SYSRSn
7 SYSDBGNMI R 0h System Debug Module NMI Flag: This bit indicates if an NMI was
generated by the System Debug Module. This bit can only be
cleared by the user writing to the corresponding clear bit in the
NMIFLGCLR register or by SYSRSn reset:
0,No System Debug NMI pending
1,System Debug NMI generated
Reset type: SYSRSn
6 RESERVED R 0h Reserved
5 RESERVED R 0h Reserved

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Table 3-199. NMIFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
4 CPU1HWBISTERR R 0h HW BIST Error NMI Flag: This bit indicates if the time out error or
a signature mismatch error condition during hardware BIST of C28
CPU1 occurred. This bit can only be cleared by the user writing
to the corresponding clear bit in the NMIFLGCLR register or by
SYSRSn reset:
0,No C28 HWBIST error condition pending
1,C28 BIST error condition generated
Reset type: SYSRSn
3 FLUNCERR R 0h Flash Uncorrectable Error NMI Flag: This bit indicates if an
uncorrectable error occurred on a C28 Flash access and that
condition is latched. This bit can only be cleared by the user writing
to the corresponding clear bit in the NMIFLGCLR register or by
SYSRSn reset:
0,No C28 Flash uncorrectable error condition pending
1,C28 Flash uncorrectable error condition generated
Reset type: SYSRSn
2 RAMUNCERR R 0h RAM Uncorrectable Error NMI Flag: This bit indicates if an
uncorrectable error occurred on a RAM access (by any master) and
that condition is latched. This bit can only be cleared by the user
writing to the corresponding clear bit in the NMIFLGCLR register or
by SYSRSn reset:
0,No RAM uncorrectable error condition pending
1,RAM uncorrectable error condition generated
Reset type: SYSRSn
1 CLOCKFAIL R 0h Clock Fail Interrupt Flag: These bits indicates if the CLOCKFAIL
condition is latched. These bits can only be cleared by the user
writing to the respective bit in the NMIFLGCLR register or by
SYSRSn reset:
0,No CLOCKFAIL Condition Pending
1,CLOCKFAIL Condition Generated
Reset type: SYSRSn
0 NMIINT R 0h NMI Interrupt Flag: This bit indicates if an NMI interrupt was
generated. This bit can only be cleared by the user writing to the
respective bit in the NMIFLGCLR register or by SYSRSn reset:
0 No NMI Interrupt Generated
1 NMI Interrupt Generated
No further NMI interrupts pulses are generated until this flag is
cleared by the user.
Reset type: SYSRSn

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3.16.10.3 NMIFLGCLR Register (Offset = 2h) [Reset = 0h]

NMIFLGCLR is shown in Figure 3-184 and described in Table 3-200.
Return to the Summary Table.
NMI Flag Clear Register
Figure 3-184. NMIFLGCLR Register
15 14 13 12 11 10 9 8
RESERVED CRC_FAIL SWERR RESERVED RESERVED RESERVED RESERVED RLNMI
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
SYSDBGNMI RESERVED RESERVED CPU1HWBISTE FLUNCERR RAMUNCERR CLOCKFAIL NMIINT
RR
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-200. NMIFLGCLR Register Field Descriptions

Bit Field Type Reset Description
15 RESERVED R 0h Reserved
14 CRC_FAIL R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
13 SWERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
12 RESERVED R-0/W1S 0h Reserved
11 RESERVED R-0/W1S 0h Reserved
10 RESERVED R-0/W1S 0h Reserved
9 RESERVED R-0/W1S 0h Reserved
8 RLNMI R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
7 SYSDBGNMI R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

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Table 3-200. NMIFLGCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
6 RESERVED R-0/W1S 0h Reserved
5 RESERVED R-0/W1S 0h Reserved
4 CPU1HWBISTERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
3 FLUNCERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
2 RAMUNCERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
1 CLOCKFAIL R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
0 NMIINT R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

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3.16.10.4 NMIFLGFRC Register (Offset = 3h) [Reset = 0h]

NMIFLGFRC is shown in Figure 3-185 and described in Table 3-201.
Return to the Summary Table.
NMI Flag Force Register
Figure 3-185. NMIFLGFRC Register
15 14 13 12 11 10 9 8
RESERVED CRC_FAIL SWERR RESERVED RESERVED RESERVED RESERVED RLNMI
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
SYSDBGNMI RESERVED RESERVED CPU1HWBISTE FLUNCERR RAMUNCERR CLOCKFAIL RESERVED
RR
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0h

Table 3-201. NMIFLGFRC Register Field Descriptions

Bit Field Type Reset Description
15 RESERVED R 0h Reserved
14 CRC_FAIL R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
13 SWERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
12 RESERVED R-0/W1S 0h Reserved
11 RESERVED R-0/W1S 0h Reserved
10 RESERVED R-0/W1S 0h Reserved
9 RESERVED R-0/W1S 0h Reserved
8 RLNMI R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
7 SYSDBGNMI R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
6 RESERVED R-0/W1S 0h Reserved
5 RESERVED R-0/W1S 0h Reserved
4 CPU1HWBISTERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
3 FLUNCERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn

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Table 3-201. NMIFLGFRC Register Field Descriptions (continued)

Bit Field Type Reset Description
2 RAMUNCERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
1 CLOCKFAIL R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
0 RESERVED R 0h Reserved

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3.16.10.5 NMIWDCNT Register (Offset = 4h) [Reset = 0h]

NMIWDCNT is shown in Figure 3-186 and described in Table 3-202.
Return to the Summary Table.
NMI Watchdog Counter Register
Figure 3-186. NMIWDCNT Register
15 14 13 12 11 10 9 8
NMIWDCNT
R-0h

7 6 5 4 3 2 1 0
NMIWDCNT
R-0h

Table 3-202. NMIWDCNT Register Field Descriptions

Bit Field Type Reset Description
15-0 NMIWDCNT R 0h NMI Watchdog Counter: This 16-bit incremental counter will start
incrementing whenever any one of the enabled FAIL flags are set.
If the counter reaches the period value, an NMIRSn signal is fired
which will then resets the system. The counter will reset to zero
when it reaches the period value and will then restart counting if any
of the enabled FAIL flags are set.
If no enabled FAIL flag is set, then the counter will reset to zero and
remain at zero until an enabled FAIL flag is set.
Normally, the software would respond to the NMI interrupt generated
and clear the offending FLAG(s) before the NMI watchdog triggers
a reset. In some situations, the software may decide to allow the
watchdog to reset the device anyway.
The counter is clocked at the SYSCLKOUT rate.
Reset type: SYSRSn

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3.16.10.6 NMIWDPRD Register (Offset = 5h) [Reset = FFFFh]

NMIWDPRD is shown in Figure 3-187 and described in Table 3-203.
Return to the Summary Table.
NMI Watchdog Period Register
Figure 3-187. NMIWDPRD Register
15 14 13 12 11 10 9 8
NMIWDPRD
R/W-FFFFh

7 6 5 4 3 2 1 0
NMIWDPRD
R/W-FFFFh

Table 3-203. NMIWDPRD Register Field Descriptions

Bit Field Type Reset Description
15-0 NMIWDPRD R/W FFFFh NMI Watchdog Period: This 16-bit value contains the period value at
which a reset is generated when the watchdog counter matches. At
reset this value is set at the maximum. The software can decrease
the period value at initialization time.
Writing a PERIOD value that is smaller then the current counter
value will automatically force an NMIRSn and hence reset the
watchdog counter.
Reset type: SYSRSn

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3.16.10.7 NMISHDFLG Register (Offset = 6h) [Reset = 0h]

NMISHDFLG is shown in Figure 3-188 and described in Table 3-204.
Return to the Summary Table.
NMI Shadow Flag Register
Figure 3-188. NMISHDFLG Register
15 14 13 12 11 10 9 8
RESERVED CRC_FAIL SWERR RESERVED RESERVED RESERVED RESERVED RLNMI
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
SYSDBGNMI RESERVED RESERVED CPU1HWBISTE FLUNCERR RAMUNCERR CLOCKFAIL RESERVED
RR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-204. NMISHDFLG Register Field Descriptions

Bit Field Type Reset Description
15 RESERVED R 0h Reserved
14 CRC_FAIL R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: SYSRSn
13 SWERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
12 RESERVED R 0h Reserved
11 RESERVED R 0h Reserved
10 RESERVED R 0h Reserved
9 RESERVED R 0h Reserved
8 RLNMI R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
7 SYSDBGNMI R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn

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Table 3-204. NMISHDFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
6 RESERVED R 0h Reserved
5 RESERVED R 0h Reserved
4 CPU1HWBISTERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
3 FLUNCERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
2 RAMUNCERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
1 CLOCKFAIL R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is resetted only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
0 RESERVED R 0h Reserved

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3.16.10.8 ERRORSTS Register (Offset = 7h) [Reset = 0h]

ERRORSTS is shown in Figure 3-189 and described in Table 3-205.
Return to the Summary Table.
Error pin status
Figure 3-189. ERRORSTS Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED PINSTS ERROR
R-0h R-0h R-0h

Table 3-205. ERRORSTS Register Field Descriptions

Bit Field Type Reset Description
15-2 RESERVED R 0h Reserved
1 PINSTS R 0h 0, Error Pin is 0
1, Error Pin is 1
Reset type: PORESETn
0 ERROR R 0h 0,None of the error sources were triggered.
1, One or more of the error sources triggered, or
ERRORSTS.ERROR was set by a write of 1 to
ERRORSTSFRC.ERROR bit. Once set, the ERROR flag can be
cleared by writing 1 to ERRORSTSCLR.ERROR bit. Following are
the events/triggers which can set this bit:
1. nmi interrupt on C28x
2. Watchdog reset
3. Error on a Pie vector fetch
4. Efuse error
On a read of this bit, the pin Error pin state will be returned.
Reset type: PORESETn

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3.16.10.9 ERRORSTSCLR Register (Offset = 8h) [Reset = 0h]

ERRORSTSCLR is shown in Figure 3-190 and described in Table 3-206.
Return to the Summary Table.
ERRORSTS clear register
Figure 3-190. ERRORSTSCLR Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED ERROR
R-0h R-0/W1S-0h

Table 3-206. ERRORSTSCLR Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R 0h Reserved
0 ERROR R-0/W1S 0h 0,No effect
1, ERRORSTS.ERROR is cleared to 0
Reset type: PORESETn

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3.16.10.10 ERRORSTSFRC Register (Offset = 9h) [Reset = 0h]

ERRORSTSFRC is shown in Figure 3-191 and described in Table 3-207.
Return to the Summary Table.
ERRORSTS force register
Figure 3-191. ERRORSTSFRC Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED ERROR
R-0h R-0/W1S-0h

Table 3-207. ERRORSTSFRC Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R 0h Reserved
0 ERROR R-0/W1S 0h 0,No effect
1, ERRORSTS.ERROR is set to 1
Reset type: PORESETn

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3.16.10.11 ERRORCTL Register (Offset = Ah) [Reset = 0h]

ERRORCTL is shown in Figure 3-192 and described in Table 3-208.
Return to the Summary Table.
Error pin control register
Figure 3-192. ERRORCTL Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED ERRORPOLSE
L
R-0h R/W-0h

Table 3-208. ERRORCTL Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R 0h Reserved
0 ERRORPOLSEL R/W 0h 0, If ERRORSTS.ERROR is 1, Error pin will be driven with a value of
0, else 1.
1, If ERRORSTS.ERROR is 1, Error pin will be driven with a value of
1, else 0.
Reset type: PORESETn

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3.16.10.12 ERRORLOCK Register (Offset = Bh) [Reset = 0h]

ERRORLOCK is shown in Figure 3-193 and described in Table 3-209.
Return to the Summary Table.
Lock register to Error pin registers.
Figure 3-193. ERRORLOCK Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED ERRORCTL
R-0h R/WSonce-0h

Table 3-209. ERRORLOCK Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R 0h Reserved
0 ERRORCTL R/WSonce 0h 0, Writes to ERRORCTL register allowed.
1, Writes to ERRORCTL register is blocked.
Writes of 0 to this bit has no effect. Write of 1 will set this bit, cleared
only on a SYSRSn.
Reset type: SYSRSn

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3.16.11 PERIPH_AC_REGS Registers

Table 3-210 lists the memory-mapped registers for the PERIPH_AC_REGS registers. All register offset
addresses not listed in Table 3-210 should be considered as reserved locations and the register contents should
not be modified.
Table 3-210. PERIPH_AC_REGS Registers
Offset Acronym Register Name Write Protection Section
0h ADCA_AC ADCA Master Access Control Register EALLOW Go
2h ADCB_AC ADCB Master Access Control Register EALLOW Go
4h ADCC_AC ADCC Master Access Control Register EALLOW Go
10h CMPSS1_AC CMPSS1 Master Access Control Register EALLOW Go
12h CMPSS2_AC CMPSS2 Master Access Control Register EALLOW Go
14h CMPSS3_AC CMPSS3 Master Access Control Register EALLOW Go
16h CMPSS4_AC CMPSS4 Master Access Control Register EALLOW Go
28h DACA_AC DACA Master Access Control Register EALLOW Go
2Ah DACB_AC DACB Master Access Control Register EALLOW Go
48h EPWM1_AC EPWM1 Master Access Control Register EALLOW Go
4Ah EPWM2_AC EPWM2 Master Access Control Register EALLOW Go
4Ch EPWM3_AC EPWM3 Master Access Control Register EALLOW Go
4Eh EPWM4_AC EPWM4 Master Access Control Register EALLOW Go
50h EPWM5_AC EPWM5 Master Access Control Register EALLOW Go
52h EPWM6_AC EPWM6 Master Access Control Register EALLOW Go
54h EPWM7_AC EPWM7 Master Access Control Register EALLOW Go
56h EPWM8_AC EPWM8 Master Access Control Register EALLOW Go
70h EQEP1_AC EQEP1 Master Access Control Register EALLOW Go
72h EQEP2_AC EQEP2 Master Access Control Register EALLOW Go
80h ECAP1_AC ECAP1 Master Access Control Register EALLOW Go
82h ECAP2_AC ECAP2 Master Access Control Register EALLOW Go
84h ECAP3_AC ECAP3 Master Access Control Register EALLOW Go
A8h SDFM1_AC SDFM1 Master Access Control Register EALLOW Go
AAh SDFM2_AC SDFM2 Master Access Control Register EALLOW Go
B0h CLB1_AC CLB1 Master Access Control Register EALLOW Go
B2h CLB2_AC CLB2 Master Access Control Register EALLOW Go
B4h CLB3_AC CLB3 Master Access Control Register EALLOW Go
B6h CLB4_AC CLB4 Master Access Control Register EALLOW Go
100h SCIA_AC SCIA Master Access Control Register EALLOW Go
102h SCIB_AC SCIB Master Access Control Register EALLOW Go
110h SPIA_AC SPIA Master Access Control Register EALLOW Go
112h SPIB_AC SPIB Master Access Control Register EALLOW Go
120h I2CA_AC I2CA Master Access Control Register EALLOW Go
122h I2CB_AC I2CB Master Access Control Register EALLOW Go
130h PMBUS_A_AC PMBUSA Master Access Control Register EALLOW Go
138h LIN_A_AC LINA Master Access Control Register EALLOW Go
13Ah LIN_B_AC LINB Master Access Control Register EALLOW Go
140h DCANA_AC DCANA Master Access Control Register EALLOW Go
148h MCANA_AC MCANA Master Access Control Register EALLOW Go
158h FSIATX_AC FSIA Master Access Control Register EALLOW Go
15Ah FSIARX_AC FSIB Master Access Control Register EALLOW Go

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Table 3-210. PERIPH_AC_REGS Registers (continued)

Offset Acronym Register Name Write Protection Section
1AAh HRPWM_A_AC HRPWM Master Access Control Register EALLOW Go
1ACh HIC_A_AC HIC Master Access Control Register EALLOW Go
1AEh AESA_AC AES Master Access Control Register EALLOW Go
1FEh PERIPH_AC_LOCK Lock Register to stop Write access to peripheral EALLOW Go
Access register.

Complex bit access types are encoded to fit into small table cells. Table 3-211 shows the codes that are used for
access types in this section.
Table 3-211. PERIPH_AC_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.11.1 ADCA_AC Register (Offset = 0h) [Reset = FFh]

ADCA_AC is shown in Figure 3-194 and described in Table 3-212.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-194. ADCA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-212. ADCA_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.2 ADCB_AC Register (Offset = 2h) [Reset = FFh]

ADCB_AC is shown in Figure 3-195 and described in Table 3-213.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-195. ADCB_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-213. ADCB_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.3 ADCC_AC Register (Offset = 4h) [Reset = FFh]

ADCC_AC is shown in Figure 3-196 and described in Table 3-214.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-196. ADCC_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-214. ADCC_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.4 CMPSS1_AC Register (Offset = 10h) [Reset = FFh]

CMPSS1_AC is shown in Figure 3-197 and described in Table 3-215.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-197. CMPSS1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-215. CMPSS1_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.5 CMPSS2_AC Register (Offset = 12h) [Reset = FFh]

CMPSS2_AC is shown in Figure 3-198 and described in Table 3-216.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-198. CMPSS2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-216. CMPSS2_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.6 CMPSS3_AC Register (Offset = 14h) [Reset = FFh]

CMPSS3_AC is shown in Figure 3-199 and described in Table 3-217.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-199. CMPSS3_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-217. CMPSS3_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.7 CMPSS4_AC Register (Offset = 16h) [Reset = FFh]

CMPSS4_AC is shown in Figure 3-200 and described in Table 3-218.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-200. CMPSS4_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-218. CMPSS4_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.8 DACA_AC Register (Offset = 28h) [Reset = FFh]

DACA_AC is shown in Figure 3-201 and described in Table 3-219.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-201. DACA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-219. DACA_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.9 DACB_AC Register (Offset = 2Ah) [Reset = FFh]

DACB_AC is shown in Figure 3-202 and described in Table 3-220.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-202. DACB_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-220. DACB_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.10 EPWM1_AC Register (Offset = 48h) [Reset = FFh]

EPWM1_AC is shown in Figure 3-203 and described in Table 3-221.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-203. EPWM1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-221. EPWM1_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.11 EPWM2_AC Register (Offset = 4Ah) [Reset = FFh]

EPWM2_AC is shown in Figure 3-204 and described in Table 3-222.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-204. EPWM2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-222. EPWM2_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.12 EPWM3_AC Register (Offset = 4Ch) [Reset = FFh]

EPWM3_AC is shown in Figure 3-205 and described in Table 3-223.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-205. EPWM3_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-223. EPWM3_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.13 EPWM4_AC Register (Offset = 4Eh) [Reset = FFh]

EPWM4_AC is shown in Figure 3-206 and described in Table 3-224.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-206. EPWM4_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-224. EPWM4_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.14 EPWM5_AC Register (Offset = 50h) [Reset = FFh]

EPWM5_AC is shown in Figure 3-207 and described in Table 3-225.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-207. EPWM5_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-225. EPWM5_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.15 EPWM6_AC Register (Offset = 52h) [Reset = FFh]

EPWM6_AC is shown in Figure 3-208 and described in Table 3-226.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-208. EPWM6_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-226. EPWM6_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.16 EPWM7_AC Register (Offset = 54h) [Reset = FFh]

EPWM7_AC is shown in Figure 3-209 and described in Table 3-227.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-209. EPWM7_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-227. EPWM7_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.17 EPWM8_AC Register (Offset = 56h) [Reset = FFh]

EPWM8_AC is shown in Figure 3-210 and described in Table 3-228.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-210. EPWM8_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-228. EPWM8_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.18 EQEP1_AC Register (Offset = 70h) [Reset = FFh]

EQEP1_AC is shown in Figure 3-211 and described in Table 3-229.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-211. EQEP1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-229. EQEP1_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.19 EQEP2_AC Register (Offset = 72h) [Reset = FFh]

EQEP2_AC is shown in Figure 3-212 and described in Table 3-230.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-212. EQEP2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-230. EQEP2_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.20 ECAP1_AC Register (Offset = 80h) [Reset = FFh]

ECAP1_AC is shown in Figure 3-213 and described in Table 3-231.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-213. ECAP1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-231. ECAP1_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.21 ECAP2_AC Register (Offset = 82h) [Reset = FFh]

ECAP2_AC is shown in Figure 3-214 and described in Table 3-232.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-214. ECAP2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-232. ECAP2_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.22 ECAP3_AC Register (Offset = 84h) [Reset = FFh]

ECAP3_AC is shown in Figure 3-215 and described in Table 3-233.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-215. ECAP3_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-233. ECAP3_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.23 SDFM1_AC Register (Offset = A8h) [Reset = FFh]

SDFM1_AC is shown in Figure 3-216 and described in Table 3-234.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-216. SDFM1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-234. SDFM1_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.24 SDFM2_AC Register (Offset = AAh) [Reset = FFh]

SDFM2_AC is shown in Figure 3-217 and described in Table 3-235.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-217. SDFM2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-235. SDFM2_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.25 CLB1_AC Register (Offset = B0h) [Reset = FFh]

CLB1_AC is shown in Figure 3-218 and described in Table 3-236.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-218. CLB1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC RESERVED CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-236. CLB1_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.26 CLB2_AC Register (Offset = B2h) [Reset = FFh]

CLB2_AC is shown in Figure 3-219 and described in Table 3-237.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-219. CLB2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC RESERVED CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-237. CLB2_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.27 CLB3_AC Register (Offset = B4h) [Reset = FFh]

CLB3_AC is shown in Figure 3-220 and described in Table 3-238.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-220. CLB3_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC RESERVED CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-238. CLB3_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.28 CLB4_AC Register (Offset = B6h) [Reset = FFh]

CLB4_AC is shown in Figure 3-221 and described in Table 3-239.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-221. CLB4_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC RESERVED CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-239. CLB4_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.29 SCIA_AC Register (Offset = 100h) [Reset = CFh]

SCIA_AC is shown in Figure 3-222 and described in Table 3-240.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-222. SCIA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC RESERVED RESERVED CPU1_ACC
R/W-3h R-0-0h R/W-3h R/W-3h

Table 3-240. SCIA_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 RESERVED R-0 0h Reserved
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.30 SCIB_AC Register (Offset = 102h) [Reset = CFh]

SCIB_AC is shown in Figure 3-223 and described in Table 3-241.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-223. SCIB_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC RESERVED RESERVED CPU1_ACC
R/W-3h R-0-0h R/W-3h R/W-3h

Table 3-241. SCIB_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 RESERVED R-0 0h Reserved
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.31 SPIA_AC Register (Offset = 110h) [Reset = FFh]

SPIA_AC is shown in Figure 3-224 and described in Table 3-242.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-224. SPIA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-242. SPIA_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.32 SPIB_AC Register (Offset = 112h) [Reset = FFh]

SPIB_AC is shown in Figure 3-225 and described in Table 3-243.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-225. SPIB_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-243. SPIB_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.33 I2CA_AC Register (Offset = 120h) [Reset = CFh]

I2CA_AC is shown in Figure 3-226 and described in Table 3-244.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-226. I2CA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC RESERVED RESERVED CPU1_ACC
R/W-3h R-0-0h R/W-3h R/W-3h

Table 3-244. I2CA_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 RESERVED R-0 0h Reserved
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.34 I2CB_AC Register (Offset = 122h) [Reset = CFh]

I2CB_AC is shown in Figure 3-227 and described in Table 3-245.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-227. I2CB_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC RESERVED RESERVED CPU1_ACC
R/W-3h R-0-0h R/W-3h R/W-3h

Table 3-245. I2CB_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 RESERVED R-0 0h Reserved
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.35 PMBUS_A_AC Register (Offset = 130h) [Reset = FFh]

PMBUS_A_AC is shown in Figure 3-228 and described in Table 3-246.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-228. PMBUS_A_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-246. PMBUS_A_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.36 LIN_A_AC Register (Offset = 138h) [Reset = FFh]

LIN_A_AC is shown in Figure 3-229 and described in Table 3-247.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-229. LIN_A_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-247. LIN_A_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.37 LIN_B_AC Register (Offset = 13Ah) [Reset = FFh]

LIN_B_AC is shown in Figure 3-230 and described in Table 3-248.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-230. LIN_B_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-248. LIN_B_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.38 DCANA_AC Register (Offset = 140h) [Reset = FFh]

DCANA_AC is shown in Figure 3-231 and described in Table 3-249.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-231. DCANA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC RESERVED CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-249. DCANA_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.39 MCANA_AC Register (Offset = 148h) [Reset = FFh]

MCANA_AC is shown in Figure 3-232 and described in Table 3-250.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-232. MCANA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC RESERVED RESERVED CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-250. MCANA_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 RESERVED R/W 3h Reserved
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.40 FSIATX_AC Register (Offset = 158h) [Reset = FFh]

FSIATX_AC is shown in Figure 3-233 and described in Table 3-251.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-233. FSIATX_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-251. FSIATX_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.41 FSIARX_AC Register (Offset = 15Ah) [Reset = FFh]

FSIARX_AC is shown in Figure 3-234 and described in Table 3-252.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-234. FSIARX_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-252. FSIARX_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.42 HRPWM_A_AC Register (Offset = 1AAh) [Reset = FFh]

HRPWM_A_AC is shown in Figure 3-235 and described in Table 3-253.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-235. HRPWM_A_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
HICA_ACC DMA1_ACC CLA1_ACC CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-253. HRPWM_A_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 HICA_ACC R/W 3h Defines Access control definition for the HICA as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.43 HIC_A_AC Register (Offset = 1ACh) [Reset = FFh]

HIC_A_AC is shown in Figure 3-236 and described in Table 3-254.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-236. HIC_A_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC RESERVED CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-254. HIC_A_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.44 AESA_AC Register (Offset = 1AEh) [Reset = FFh]

AESA_AC is shown in Figure 3-237 and described in Table 3-255.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to perpheral from corresponding connected
master.
Figure 3-237. AESA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC RESERVED CPU1_ACC
R/W-3h R/W-3h R/W-3h R/W-3h

Table 3-255. AESA_AC Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7-6 RESERVED R/W 3h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPU1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.11.45 PERIPH_AC_LOCK Register (Offset = 1FEh) [Reset = 0h]

PERIPH_AC_LOCK is shown in Figure 3-238 and described in Table 3-256.
Return to the Summary Table.
Based on status bit control the Access registers are either RD/WR or RD only.
Figure 3-238. PERIPH_AC_LOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED LOCK_AC_WR
R-0-0h R/WSonce-0h

Table 3-256. PERIPH_AC_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 LOCK_AC_WR R/WSonce 0h Defines Access control definition for the CPU1 as:
1: Access Control registers are Read Only
0: Read/Write Access allowed to Access Control registers.
Writing '1' sets the bit, writing '0' has no effect.
Reset type: SYSRSn

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3.16.12 PIE_CTRL_REGS Registers

Table 3-257 lists the memory-mapped registers for the PIE_CTRL_REGS registers. All register offset addresses
not listed in Table 3-257 should be considered as reserved locations and the register contents should not be
modified.
Table 3-257. PIE_CTRL_REGS Registers
Offset Acronym Register Name Write Protection Section
0h PIECTRL ePIE Control Register Go
1h PIEACK Interrupt Acknowledge Register Go
2h PIEIER1 Interrupt Group 1 Enable Register Go
3h PIEIFR1 Interrupt Group 1 Flag Register Go
4h PIEIER2 Interrupt Group 2 Enable Register Go
5h PIEIFR2 Interrupt Group 2 Flag Register Go
6h PIEIER3 Interrupt Group 3 Enable Register Go
7h PIEIFR3 Interrupt Group 3 Flag Register Go
8h PIEIER4 Interrupt Group 4 Enable Register Go
9h PIEIFR4 Interrupt Group 4 Flag Register Go
Ah PIEIER5 Interrupt Group 5 Enable Register Go
Bh PIEIFR5 Interrupt Group 5 Flag Register Go
Ch PIEIER6 Interrupt Group 6 Enable Register Go
Dh PIEIFR6 Interrupt Group 6 Flag Register Go
Eh PIEIER7 Interrupt Group 7 Enable Register Go
Fh PIEIFR7 Interrupt Group 7 Flag Register Go
10h PIEIER8 Interrupt Group 8 Enable Register Go
11h PIEIFR8 Interrupt Group 8 Flag Register Go
12h PIEIER9 Interrupt Group 9 Enable Register Go
13h PIEIFR9 Interrupt Group 9 Flag Register Go
14h PIEIER10 Interrupt Group 10 Enable Register Go
15h PIEIFR10 Interrupt Group 10 Flag Register Go
16h PIEIER11 Interrupt Group 11 Enable Register Go
17h PIEIFR11 Interrupt Group 11 Flag Register Go
18h PIEIER12 Interrupt Group 12 Enable Register Go
19h PIEIFR12 Interrupt Group 12 Flag Register Go

Complex bit access types are encoded to fit into small table cells. Table 3-258 shows the codes that are used for
access types in this section.
Table 3-258. PIE_CTRL_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value

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Table 3-258. PIE_CTRL_REGS Access Type Codes

(continued)
Access Type Code Description
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.12.1 PIECTRL Register (Offset = 0h) [Reset = 0h]

PIECTRL is shown in Figure 3-239 and described in Table 3-259.
Return to the Summary Table.
ePIE Control Register
Figure 3-239. PIECTRL Register
15 14 13 12 11 10 9 8
PIEVECT
R-0h

7 6 5 4 3 2 1 0
PIEVECT ENPIE
R-0h R/W-0h

Table 3-259. PIECTRL Register Field Descriptions

Bit Field Type Reset Description
15-1 PIEVECT R 0h These bits indicate the vector address of the vector fetched from the
ePIE vector table. The least significant bit of the address is ignored
and only bits 1 to 15 of the address are shown. The vector value
can be read by the user to determine which interrupt generated the
vector fetch.
Note: When a NMI is serviced, the PIEVECT bit-field does not reflect
the vector as it does for other interrupts.
Reset type: SYSRSn
0 ENPIE R/W 0h Enable vector fetching from ePIE block. This bit must be set to 1
for peripheral interrupts to work. All ePIE registers (PIEACK, PIEIFR,
PIEIER) can be accessed even when the ePIE block is disabled.
Reset type: SYSRSn

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3.16.12.2 PIEACK Register (Offset = 1h) [Reset = 0h]

PIEACK is shown in Figure 3-240 and described in Table 3-260.
Return to the Summary Table.
Acknowledge Register
When an interrupt propagates from the ePIE to a CPU interrupt line, the interrupt group's PIEACK bit is set. This
prevents other interrupts in that group from propagating to the CPU while the first interrupt is handled. Writing a
1 to a PIEACK bit clears it and allows another interrupt from the corresponding group to propagate. ISRs for PIE
interrupts should clear the group's PIEACK bit before returning from the interrupt.
Writes of 0 are ignored.
Figure 3-240. PIEACK Register
15 14 13 12 11 10 9 8
RESERVED ACK12 ACK11 ACK10 ACK9
R-0-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h

7 6 5 4 3 2 1 0
ACK8 ACK7 ACK6 ACK5 ACK4 ACK3 ACK2 ACK1
R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h

Table 3-260. PIEACK Register Field Descriptions

Bit Field Type Reset Description
15-12 RESERVED R-0 0h Reserved
11 ACK12 R/W1S 0h Acknowledge PIE Interrupt Group 12
Reset type: SYSRSn
10 ACK11 R/W1S 0h Acknowledge PIE Interrupt Group 11
Reset type: SYSRSn
9 ACK10 R/W1S 0h Acknowledge PIE Interrupt Group 10
Reset type: SYSRSn
8 ACK9 R/W1S 0h Acknowledge PIE Interrupt Group 9
Reset type: SYSRSn
7 ACK8 R/W1S 0h Acknowledge PIE Interrupt Group 8
Reset type: SYSRSn
6 ACK7 R/W1S 0h Acknowledge PIE Interrupt Group 7
Reset type: SYSRSn
5 ACK6 R/W1S 0h Acknowledge PIE Interrupt Group 6
Reset type: SYSRSn
4 ACK5 R/W1S 0h Acknowledge PIE Interrupt Group 5
Reset type: SYSRSn
3 ACK4 R/W1S 0h Acknowledge PIE Interrupt Group 4
Reset type: SYSRSn
2 ACK3 R/W1S 0h Acknowledge PIE Interrupt Group 3
Reset type: SYSRSn
1 ACK2 R/W1S 0h Acknowledge PIE Interrupt Group 2
Reset type: SYSRSn
0 ACK1 R/W1S 0h Acknowledge PIE Interrupt Group 1
Reset type: SYSRSn

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3.16.12.3 PIEIER1 Register (Offset = 2h) [Reset = 0h]

PIEIER1 is shown in Figure 3-241 and described in Table 3-261.
Return to the Summary Table.
Interrupt Group 1 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-241. PIEIER1 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-261. PIEIER1 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 1.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 1.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 1.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 1.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 1.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 1.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 1.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 1.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 1.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 1.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 1.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 1.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 1.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 1.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 1.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 1.1
Reset type: SYSRSn

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3.16.12.4 PIEIFR1 Register (Offset = 3h) [Reset = 0h]

PIEIFR1 is shown in Figure 3-242 and described in Table 3-262.
Return to the Summary Table.
Interrupt Group 1 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-242. PIEIFR1 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-262. PIEIFR1 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 1.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 1.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 1.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 1.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 1.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 1.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 1.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 1.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 1.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 1.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 1.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 1.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 1.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 1.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 1.2
Reset type: SYSRSn

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Table 3-262. PIEIFR1 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 1.1
Reset type: SYSRSn

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3.16.12.5 PIEIER2 Register (Offset = 4h) [Reset = 0h]

PIEIER2 is shown in Figure 3-243 and described in Table 3-263.
Return to the Summary Table.
Interrupt Group 2 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-243. PIEIER2 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-263. PIEIER2 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 2.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 2.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 2.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 2.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 2.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 2.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 2.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 2.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 2.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 2.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 2.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 2.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 2.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 2.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 2.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 2.1
Reset type: SYSRSn

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3.16.12.6 PIEIFR2 Register (Offset = 5h) [Reset = 0h]

PIEIFR2 is shown in Figure 3-244 and described in Table 3-264.
Return to the Summary Table.
Interrupt Group 2 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-244. PIEIFR2 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-264. PIEIFR2 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 2.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 2.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 2.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 2.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 2.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 2.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 2.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 2.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 2.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 2.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 2.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 2.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 2.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 2.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 2.2
Reset type: SYSRSn

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Table 3-264. PIEIFR2 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 2.1
Reset type: SYSRSn

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3.16.12.7 PIEIER3 Register (Offset = 6h) [Reset = 0h]

PIEIER3 is shown in Figure 3-245 and described in Table 3-265.
Return to the Summary Table.
Interrupt Group 3 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-245. PIEIER3 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-265. PIEIER3 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 3.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 3.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 3.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 3.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 3.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 3.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 3.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 3.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 3.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 3.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 3.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 3.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 3.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 3.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 3.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 3.1
Reset type: SYSRSn

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3.16.12.8 PIEIFR3 Register (Offset = 7h) [Reset = 0h]

PIEIFR3 is shown in Figure 3-246 and described in Table 3-266.
Return to the Summary Table.
Interrupt Group 3 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-246. PIEIFR3 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-266. PIEIFR3 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 3.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 3.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 3.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 3.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 3.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 3.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 3.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 3.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 3.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 3.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 3.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 3.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 3.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 3.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 3.2
Reset type: SYSRSn

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Table 3-266. PIEIFR3 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 3.1
Reset type: SYSRSn

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3.16.12.9 PIEIER4 Register (Offset = 8h) [Reset = 0h]

PIEIER4 is shown in Figure 3-247 and described in Table 3-267.
Return to the Summary Table.
Interrupt Group 4 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-247. PIEIER4 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-267. PIEIER4 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 4.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 4.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 4.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 4.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 4.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 4.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 4.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 4.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 4.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 4.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 4.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 4.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 4.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 4.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 4.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 4.1
Reset type: SYSRSn

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3.16.12.10 PIEIFR4 Register (Offset = 9h) [Reset = 0h]

PIEIFR4 is shown in Figure 3-248 and described in Table 3-268.
Return to the Summary Table.
Interrupt Group 4 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-248. PIEIFR4 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-268. PIEIFR4 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 4.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 4.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 4.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 4.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 4.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 4.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 4.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 4.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 4.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 4.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 4.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 4.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 4.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 4.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 4.2
Reset type: SYSRSn

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Table 3-268. PIEIFR4 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 4.1
Reset type: SYSRSn

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3.16.12.11 PIEIER5 Register (Offset = Ah) [Reset = 0h]

PIEIER5 is shown in Figure 3-249 and described in Table 3-269.
Return to the Summary Table.
Interrupt Group 5 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-249. PIEIER5 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-269. PIEIER5 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 5.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 5.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 5.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 5.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 5.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 5.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 5.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 5.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 5.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 5.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 5.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 5.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 5.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 5.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 5.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 5.1
Reset type: SYSRSn

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3.16.12.12 PIEIFR5 Register (Offset = Bh) [Reset = 0h]

PIEIFR5 is shown in Figure 3-250 and described in Table 3-270.
Return to the Summary Table.
Interrupt Group 5 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-250. PIEIFR5 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-270. PIEIFR5 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 5.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 5.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 5.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 5.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 5.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 5.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 5.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 5.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 5.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 5.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 5.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 5.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 5.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 5.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 5.2
Reset type: SYSRSn

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Table 3-270. PIEIFR5 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 5.1
Reset type: SYSRSn

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3.16.12.13 PIEIER6 Register (Offset = Ch) [Reset = 0h]

PIEIER6 is shown in Figure 3-251 and described in Table 3-271.
Return to the Summary Table.
Interrupt Group 6 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-251. PIEIER6 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-271. PIEIER6 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 6.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 6.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 6.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 6.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 6.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 6.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 6.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 6.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 6.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 6.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 6.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 6.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 6.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 6.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 6.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 6.1
Reset type: SYSRSn

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3.16.12.14 PIEIFR6 Register (Offset = Dh) [Reset = 0h]

PIEIFR6 is shown in Figure 3-252 and described in Table 3-272.
Return to the Summary Table.
Interrupt Group 6 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-252. PIEIFR6 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-272. PIEIFR6 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 6.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 6.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 6.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 6.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 6.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 6.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 6.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 6.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 6.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 6.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 6.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 6.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 6.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 6.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 6.2
Reset type: SYSRSn

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Table 3-272. PIEIFR6 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 6.1
Reset type: SYSRSn

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3.16.12.15 PIEIER7 Register (Offset = Eh) [Reset = 0h]

PIEIER7 is shown in Figure 3-253 and described in Table 3-273.
Return to the Summary Table.
Interrupt Group 7 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-253. PIEIER7 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-273. PIEIER7 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 7.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 7.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 7.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 7.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 7.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 7.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 7.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 7.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 7.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 7.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 7.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 7.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 7.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 7.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 7.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 7.1
Reset type: SYSRSn

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3.16.12.16 PIEIFR7 Register (Offset = Fh) [Reset = 0h]

PIEIFR7 is shown in Figure 3-254 and described in Table 3-274.
Return to the Summary Table.
Interrupt Group 7 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-254. PIEIFR7 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-274. PIEIFR7 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 7.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 7.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 7.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 7.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 7.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 7.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 7.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 7.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 7.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 7.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 7.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 7.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 7.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 7.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 7.2
Reset type: SYSRSn

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Table 3-274. PIEIFR7 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 7.1
Reset type: SYSRSn

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3.16.12.17 PIEIER8 Register (Offset = 10h) [Reset = 0h]

PIEIER8 is shown in Figure 3-255 and described in Table 3-275.
Return to the Summary Table.
Interrupt Group 8 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-255. PIEIER8 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-275. PIEIER8 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 8.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 8.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 8.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 8.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 8.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 8.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 8.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 8.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 8.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 8.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 8.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 8.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 8.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 8.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 8.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 8.1
Reset type: SYSRSn

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3.16.12.18 PIEIFR8 Register (Offset = 11h) [Reset = 0h]

PIEIFR8 is shown in Figure 3-256 and described in Table 3-276.
Return to the Summary Table.
Interrupt Group 8 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-256. PIEIFR8 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-276. PIEIFR8 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 8.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 8.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 8.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 8.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 8.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 8.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 8.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 8.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 8.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 8.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 8.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 8.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 8.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 8.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 8.2
Reset type: SYSRSn

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Table 3-276. PIEIFR8 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 8.1
Reset type: SYSRSn

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3.16.12.19 PIEIER9 Register (Offset = 12h) [Reset = 0h]

PIEIER9 is shown in Figure 3-257 and described in Table 3-277.
Return to the Summary Table.
Interrupt Group 9 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-257. PIEIER9 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-277. PIEIER9 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 9.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 9.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 9.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 9.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 9.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 9.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 9.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 9.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 9.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 9.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 9.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 9.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 9.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 9.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 9.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 9.1
Reset type: SYSRSn

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3.16.12.20 PIEIFR9 Register (Offset = 13h) [Reset = 0h]

PIEIFR9 is shown in Figure 3-258 and described in Table 3-278.
Return to the Summary Table.
Interrupt Group 9 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-258. PIEIFR9 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-278. PIEIFR9 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 9.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 9.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 9.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 9.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 9.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 9.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 9.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 9.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 9.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 9.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 9.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 9.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 9.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 9.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 9.2
Reset type: SYSRSn

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Table 3-278. PIEIFR9 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 9.1
Reset type: SYSRSn

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3.16.12.21 PIEIER10 Register (Offset = 14h) [Reset = 0h]

PIEIER10 is shown in Figure 3-259 and described in Table 3-279.
Return to the Summary Table.
Interrupt Group 10 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-259. PIEIER10 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-279. PIEIER10 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 10.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 10.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 10.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 10.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 10.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 10.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 10.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 10.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 10.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 10.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 10.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 10.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 10.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 10.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 10.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 10.1
Reset type: SYSRSn

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3.16.12.22 PIEIFR10 Register (Offset = 15h) [Reset = 0h]

PIEIFR10 is shown in Figure 3-260 and described in Table 3-280.
Return to the Summary Table.
Interrupt Group 10 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-260. PIEIFR10 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-280. PIEIFR10 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 10.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 10.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 10.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 10.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 10.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 10.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 10.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 10.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 10.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 10.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 10.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 10.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 10.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 10.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 10.2
Reset type: SYSRSn

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Table 3-280. PIEIFR10 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 10.1
Reset type: SYSRSn

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3.16.12.23 PIEIER11 Register (Offset = 16h) [Reset = 0h]

PIEIER11 is shown in Figure 3-261 and described in Table 3-281.
Return to the Summary Table.
Interrupt Group 11 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-261. PIEIER11 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-281. PIEIER11 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 11.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 11.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 11.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 11.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 11.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 11.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 11.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 11.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 11.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 11.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 11.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 11.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 11.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 11.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 11.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 11.1
Reset type: SYSRSn

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3.16.12.24 PIEIFR11 Register (Offset = 17h) [Reset = 0h]

PIEIFR11 is shown in Figure 3-262 and described in Table 3-282.
Return to the Summary Table.
Interrupt Group 11 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-262. PIEIFR11 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-282. PIEIFR11 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 11.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 11.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 11.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 11.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 11.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 11.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 11.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 11.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 11.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 11.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 11.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 11.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 11.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 11.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 11.2
Reset type: SYSRSn

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Table 3-282. PIEIFR11 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 11.1
Reset type: SYSRSn

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3.16.12.25 PIEIER12 Register (Offset = 18h) [Reset = 0h]

PIEIER12 is shown in Figure 3-263 and described in Table 3-283.
Return to the Summary Table.
Interrupt Group 12 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-263. PIEIER12 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-283. PIEIER12 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 12.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 12.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 12.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 12.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 12.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 12.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 12.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 12.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 12.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 12.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 12.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 12.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 12.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 12.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 12.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 12.1
Reset type: SYSRSn

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3.16.12.26 PIEIFR12 Register (Offset = 19h) [Reset = 0h]

PIEIFR12 is shown in Figure 3-264 and described in Table 3-284.
Return to the Summary Table.
Interrupt Group 12 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-264. PIEIFR12 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-284. PIEIFR12 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 12.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 12.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 12.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 12.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 12.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 12.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 12.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 12.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 12.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 12.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 12.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 12.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 12.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 12.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 12.2
Reset type: SYSRSn

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Table 3-284. PIEIFR12 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 12.1
Reset type: SYSRSn

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3.16.13 SYNC_SOC_REGS Registers

Table 3-285 lists the memory-mapped registers for the SYNC_SOC_REGS registers. All register offset
addresses not listed in Table 3-285 should be considered as reserved locations and the register contents should
not be modified.
Table 3-285. SYNC_SOC_REGS Registers
Offset Acronym Register Name Write Protection Section
0h SYNCSELECT Sync Input and Output Select Register EALLOW Go
2h ADCSOCOUTSELECT External ADCSOC Select Register EALLOW Go
4h SYNCSOCLOCK SYNCSEL and EXTADCSOC Select Lock register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-286 shows the codes that are used for
access types in this section.
Table 3-286. SYNC_SOC_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.13.1 SYNCSELECT Register (Offset = 0h) [Reset = E003FFFFh]

SYNCSELECT is shown in Figure 3-265 and described in Table 3-287.
Return to the Summary Table.
Sync Input and Output Select Register
Figure 3-265. SYNCSELECT Register
31 30 29 28 27 26 25 24
RESERVED SYNCOUT
R/W-7h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED
R-0-0h R/W-7h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED
R/W-7h R/W-7h R/W-7h R/W-7h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED
R/W-7h R/W-7h R/W-7h

Table 3-287. SYNCSELECT Register Field Descriptions

Bit Field Type Reset Description
31-29 RESERVED R/W 7h Reserved

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Table 3-287. SYNCSELECT Register Field Descriptions (continued)

Bit Field Type Reset Description
28-24 SYNCOUT R/W 0h Select Syncout Source:
00000: EPWM1SYNCOUT selected to drive the SYNCOUT pin.
00001: EPWM2SYNCOUT selected to drive the SYNCOUT pin.
00010: EPWM3SYNCOUT selected to drive the SYNCOUT pin.
00011: EPWM4SYNCOUT selected to drive the SYNCOUT pin.
00100: EPWM5SYNCOUT selected to drive the SYNCOUT pin.
00101: EPWM6SYNCOUT selected to drive the SYNCOUT pin.
00110: EPWM7SYNCOUT selected to drive the SYNCOUT pin.
00111: EPWM8SYNCOUT selected to drive the SYNCOUT pin.
01000: Reserved
01001: Reserved
01010: Reserved
01011: Reserved
01100: Reserved
01101: Reserved
01110: Reserved
01111: Reserved
10000: Reserved
10001: Reserved
10010: Reserved
10011: Reserved
10100: Reserved
10101: Reserved
10110: Reserved
10111: Reserved
11000: ECAP1SYNCOUT selected to drive the SYNCOUT pin.
11001: ECAP2SYNCOUT selected to drive the SYNCOUT pin.
11010: ECAP3SYNCOUT selected to drive the SYNCOUT pin.
11011: Reserved
11100: Reserved
11101: Reserved
11110: Reserved
11111: Reserved
Notes:
[1] Reserved position defaults to 00 selection
Reset type: SYSRSn
23-18 RESERVED R-0 0h Reserved
17-15 RESERVED R/W 7h Reserved
14-12 RESERVED R/W 7h Reserved
11-9 RESERVED R/W 7h Reserved
8-6 RESERVED R/W 7h Reserved
5-3 RESERVED R/W 7h Reserved
2-0 RESERVED R/W 7h Reserved

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3.16.13.2 ADCSOCOUTSELECT Register (Offset = 2h) [Reset = 0h]

ADCSOCOUTSELECT is shown in Figure 3-266 and described in Table 3-288.
Return to the Summary Table.
External ADCSOC Select Register
Figure 3-266. ADCSOCOUTSELECT Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
PWM8SOCBEN PWM7SOCBEN PWM6SOCBEN PWM5SOCBEN PWM4SOCBEN PWM3SOCBEN PWM2SOCBEN PWM1SOCBEN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
PWM8SOCAEN PWM7SOCAEN PWM6SOCAEN PWM5SOCAEN PWM4SOCAEN PWM3SOCAEN PWM2SOCAEN PWM1SOCAEN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-288. ADCSOCOUTSELECT Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R-0 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 PWM8SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
22 PWM7SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
21 PWM6SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
20 PWM5SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
19 PWM4SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
18 PWM3SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn

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Table 3-288. ADCSOCOUTSELECT Register Field Descriptions (continued)

Bit Field Type Reset Description
17 PWM2SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
16 PWM1SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: SYSRSn
15-12 RESERVED R-0 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 PWM8SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
6 PWM7SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
5 PWM6SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
4 PWM5SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
3 PWM4SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
2 PWM3SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
1 PWM2SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn
0 PWM1SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: SYSRSn

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3.16.13.3 SYNCSOCLOCK Register (Offset = 4h) [Reset = 0h]

SYNCSOCLOCK is shown in Figure 3-267 and described in Table 3-289.
Return to the Summary Table.
SYNCSEL and EXTADCSOC Select Lock register
Figure 3-267. SYNCSOCLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ADCSOCOUTS SYNCSELECT
ELECT
R-0-0h R/WSonce-0h R/WSonce-0h

Table 3-289. SYNCSOCLOCK Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 ADCSOCOUTSELECT R/WSonce 0h ADCSOCOUTSELECT Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a
SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn
0 SYNCSELECT R/WSonce 0h SYNCSELECT Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a
SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn

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3.16.14 SYS_STATUS_REGS Registers

Table 3-290 lists the memory-mapped registers for the SYS_STATUS_REGS registers. All register offset
addresses not listed in Table 3-290 should be considered as reserved locations and the register contents should
not be modified.
Table 3-290. SYS_STATUS_REGS Registers
Offset Acronym Register Name Write Protection Section
10h SYS_ERR_INT_FLG Status of interrupts due to multiple different errors Go
in the system.
12h SYS_ERR_INT_CLR SYS_ERR_INT_FLG clear register Go
14h SYS_ERR_INT_SET SYS_ERR_INT_FLG set register EALLOW Go
16h SYS_ERR_MASK SYS_ERR_MASK register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-291 shows the codes that are used for
access types in this section.
Table 3-291. SYS_STATUS_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.14.1 SYS_ERR_INT_FLG Register (Offset = 10h) [Reset = 0h]

SYS_ERR_INT_FLG is shown in Figure 3-268 and described in Table 3-292.
Return to the Summary Table.
Status of interrupts due to multiple different errors in the system.
Figure 3-268. SYS_ERR_INT_FLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED EPG1_INT AES_BUS_ER RESERVED RESERVED
ROR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GINT
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-292. SYS_ERR_INT_FLG Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R 0h Reserved
14 RESERVED R 0h Reserved
13 RESERVED R 0h Reserved
12 RESERVED R 0h Reserved
11 EPG1_INT R 0h 0: EPG1_INT has not fired an interrupt.
1: EPG1_INT has fired an interrupt
Reset type: SYSRSn
10 AES_BUS_ERROR R 0h 0: AES_BUS_ERROR has not fired an interrupt.
1: AES_BUS_ERROR has fired an interrupt
Reset type: SYSRSn
9 RESERVED R 0h Reserved
8 RESERVED R 0h Reserved
7 RESERVED R 0h Reserved
6 RESERVED R 0h Reserved
5 RESERVED R 0h Reserved
4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 RESERVED R 0h Reserved
1 RESERVED R 0h Reserved
0 GINT R 0h Global Interrupt flag:
0: On any of the flags of SYS_ERR_INT_FLG register being set,
SYS_ERR_INT is pulsed and GINT flag would be set
1: No further interrupts would be fired until GINT flag is cleared
Reset type: SYSRSn

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3.16.14.2 SYS_ERR_INT_CLR Register (Offset = 12h) [Reset = 0h]

SYS_ERR_INT_CLR is shown in Figure 3-269 and described in Table 3-293.
Return to the Summary Table.
SYS_ERR_INT_FLG clear register
Figure 3-269. SYS_ERR_INT_CLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED EPG1_INT AES_BUS_ER RESERVED RESERVED
ROR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GINT
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-293. SYS_ERR_INT_CLR Register Field Descriptions

Bit Field Type Reset Description
31-15 RESERVED R 0h Reserved
14 RESERVED R-0/W1S 0h Reserved
13 RESERVED R-0/W1S 0h Reserved
12 RESERVED R-0/W1S 0h Reserved
11 EPG1_INT R-0/W1S 0h 0: No effect
1: EPG1_INT flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn
10 AES_BUS_ERROR R-0/W1S 0h 0: No effect
1: AES_BUS_ERROR flag of SYS_ERR_INT_FLG reister will be
cleared.
Reset type: SYSRSn
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R-0/W1S 0h Reserved
6 RESERVED R-0/W1S 0h Reserved
5 RESERVED R-0/W1S 0h Reserved
4 RESERVED R-0/W1S 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 RESERVED R-0/W1S 0h Reserved
1 RESERVED R-0/W1S 0h Reserved
0 GINT R-0/W1S 0h 0: No effect
1: GINT flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn

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3.16.14.3 SYS_ERR_INT_SET Register (Offset = 14h) [Reset = 0h]

SYS_ERR_INT_SET is shown in Figure 3-270 and described in Table 3-294.
Return to the Summary Table.
SYS_ERR_INT_FLG set register
Figure 3-270. SYS_ERR_INT_SET Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED EPG1_INT AES_BUS_ER RESERVED RESERVED
ROR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0h

Table 3-294. SYS_ERR_INT_SET Register Field Descriptions

Bit Field Type Reset Description
31-24 KEY R-0/W 0h A value of 0xa5 to this field would enable write to the other bit fields
of this register. Any other value written to KEY field would block the
write to the other fields of this register.
Note: Only a 32 bit write to this register will succeed in updating the
fields of this rigister, provided the correct value written to the KEY
field simultaneously
Reset type: SYSRSn
23-16 RESERVED R 0h Reserved
15 RESERVED R 0h Reserved
14 RESERVED R-0/W1S 0h Reserved
13 RESERVED R-0/W1S 0h Reserved
12 RESERVED R-0/W1S 0h Reserved
11 EPG1_INT R-0/W1S 0h 0: No effect
1: EPG1_INT flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
10 AES_BUS_ERROR R-0/W1S 0h 0: No effect
1: AES_BUS_ERROR flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R-0/W1S 0h Reserved
6 RESERVED R-0/W1S 0h Reserved
5 RESERVED R-0/W1S 0h Reserved
4 RESERVED R-0/W1S 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 RESERVED R-0/W1S 0h Reserved
1 RESERVED R-0/W1S 0h Reserved

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Table 3-294. SYS_ERR_INT_SET Register Field Descriptions (continued)

Bit Field Type Reset Description
0 RESERVED R 0h Reserved

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3.16.14.4 SYS_ERR_MASK Register (Offset = 16h) [Reset = 0h]

SYS_ERR_MASK is shown in Figure 3-271 and described in Table 3-295.
Return to the Summary Table.
SYS_ERR_MASK register
Figure 3-271. SYS_ERR_MASK Register
31 30 29 28 27 26 25 24
KEY
R/W-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED EPG1_INT AES_BUS_ER RESERVED RESERVED
ROR
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h

Table 3-295. SYS_ERR_MASK Register Field Descriptions

Bit Field Type Reset Description
31-24 KEY R/W 0h A value of 0xa5 to this field would enable write to the other bit fields
of this register. Any other value written to KEY field would block the
write to the other fields of this register.
Note: Only a 32 bit write to this register will succeed in updating the
fields of this rigister, provided the correct value written to the KEY
field simultaneously
Reset type: SYSRSn
23-16 RESERVED R 0h Reserved
15 RESERVED R 0h Reserved
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 EPG1_INT R/W 0h 0: EPG1_INT flag of SYS_ERR_INT_FLG reister will be set on a
hardware event.
1: EPG1_INT flag of SYS_ERR_INT_FLG reister will not be set on a
hardware event.
Reset type: SYSRSn
10 AES_BUS_ERROR R/W 0h 0: AES_BUS_ERROR flag of SYS_ERR_INT_FLG reister will be set
on a hardware event.
1: AES_BUS_ERROR flag of SYS_ERR_INT_FLG reister will not be
set on a hardware event.
Reset type: SYSRSn
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved

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Table 3-295. SYS_ERR_MASK Register Field Descriptions (continued)

Bit Field Type Reset Description
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R 0h Reserved

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3.16.15 TEST_ERROR_REGS Registers

Table 3-296 lists the memory-mapped registers for the TEST_ERROR_REGS registers. All register offset
addresses not listed in Table 3-296 should be considered as reserved locations and the register contents should
not be modified.
Table 3-296. TEST_ERROR_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CPU_RAM_TEST_ERROR_STS Ram Test: Error Status Register Go
2h CPU_RAM_TEST_ERROR_STS_C Ram Test: Error Status Clear Register Go
LR
4h CPU_RAM_TEST_ERROR_ADDR Ram Test: Error address register Go

Complex bit access types are encoded to fit into small table cells. Table 3-297 shows the codes that are used for
access types in this section.
Table 3-297. TEST_ERROR_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.15.1 CPU_RAM_TEST_ERROR_STS Register (Offset = 0h) [Reset = 0h]

CPU_RAM_TEST_ERROR_STS is shown in Figure 3-272 and described in Table 3-298.
Return to the Summary Table.
Ram Test: Error Status Register
Figure 3-272. CPU_RAM_TEST_ERROR_STS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED UNC_ERROR COR_ERROR
R-0h R-0h R-0h

Table 3-298. CPU_RAM_TEST_ERROR_STS Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 UNC_ERROR R 0h 0: Indicates that there were no "un-correctable errors" generated in
the RAM/ROM test mode.
1: Indicates that "un-correctable errors" wer generated in the
RAM/ROM test mode.
Reset type: SYSRSn
0 COR_ERROR R 0h 0: Indicates that there were no "correctable errors" generated in the
RAM/ROM test mode.
1: Indicates that "correctable errors" wer generated in the RAM/ROM
test mode.
Reset type: SYSRSn

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3.16.15.2 CPU_RAM_TEST_ERROR_STS_CLR Register (Offset = 2h) [Reset = 0h]

CPU_RAM_TEST_ERROR_STS_CLR is shown in Figure 3-273 and described in Table 3-299.
Return to the Summary Table.
Ram Test: Error Status Clear Register
Figure 3-273. CPU_RAM_TEST_ERROR_STS_CLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED UNC_ERROR COR_ERROR
R-0h R-0/W1S-0h R-0/W1S-0h

Table 3-299. CPU_RAM_TEST_ERROR_STS_CLR Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 UNC_ERROR R-0/W1S 0h 0: No effect.
1: Clears the corresponding bit in CPU_RAM_TEST_ERROR_STS
register.
Reset type: SYSRSn
0 COR_ERROR R-0/W1S 0h 0: No effect.
1: Clears the corresponding bit in CPU_RAM_TEST_ERROR_STS
register.
Reset type: SYSRSn

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3.16.15.3 CPU_RAM_TEST_ERROR_ADDR Register (Offset = 4h) [Reset = 0h]

CPU_RAM_TEST_ERROR_ADDR is shown in Figure 3-274 and described in Table 3-300.
Return to the Summary Table.
Ram Test: Error address register
Figure 3-274. CPU_RAM_TEST_ERROR_ADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
R-0h

Table 3-300. CPU_RAM_TEST_ERROR_ADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 ADDR R 0h Address of the location where error was detected in RAM/ROM test
modes.
Reset type: SYSRSn

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3.16.16 UID_REGS Registers

Table 3-301 lists the memory-mapped registers for the UID_REGS registers. All register offset addresses not
listed in Table 3-301 should be considered as reserved locations and the register contents should not be
modified.
Table 3-301. UID_REGS Registers
Offset Acronym Register Name Write Protection Section
0h UID_PSRAND0 UID Psuedo-random 192 bit number Go
2h UID_PSRAND1 UID Psuedo-random 192 bit number Go
4h UID_PSRAND2 UID Psuedo-random 192 bit number Go
6h UID_PSRAND3 UID Psuedo-random 192 bit number Go
8h UID_PSRAND4 UID Psuedo-random 192 bit number Go
Ah UID_PSRAND5 UID Psuedo-random 192 bit number Go
Ch UID_UNIQUE UID Unique 32 bit number Go
Eh UID_CHECKSUM UID Checksum Go

Complex bit access types are encoded to fit into small table cells. Table 3-302 shows the codes that are used for
access types in this section.
Table 3-302. UID_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.16.1 UID_PSRAND0 Register (Offset = 0h) [Reset = X]

UID_PSRAND0 is shown in Figure 3-275 and described in Table 3-303.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-275. UID_PSRAND0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-303. UID_PSRAND0 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.16.16.2 UID_PSRAND1 Register (Offset = 2h) [Reset = X]

UID_PSRAND1 is shown in Figure 3-276 and described in Table 3-304.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-276. UID_PSRAND1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-304. UID_PSRAND1 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.16.16.3 UID_PSRAND2 Register (Offset = 4h) [Reset = X]

UID_PSRAND2 is shown in Figure 3-277 and described in Table 3-305.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-277. UID_PSRAND2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-305. UID_PSRAND2 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.16.16.4 UID_PSRAND3 Register (Offset = 6h) [Reset = X]

UID_PSRAND3 is shown in Figure 3-278 and described in Table 3-306.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-278. UID_PSRAND3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-306. UID_PSRAND3 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.16.16.5 UID_PSRAND4 Register (Offset = 8h) [Reset = X]

UID_PSRAND4 is shown in Figure 3-279 and described in Table 3-307.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-279. UID_PSRAND4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-307. UID_PSRAND4 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.16.16.6 UID_PSRAND5 Register (Offset = Ah) [Reset = X]

UID_PSRAND5 is shown in Figure 3-280 and described in Table 3-308.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-280. UID_PSRAND5 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-308. UID_PSRAND5 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.16.16.7 UID_UNIQUE Register (Offset = Ch) [Reset = X]

UID_UNIQUE is shown in Figure 3-281 and described in Table 3-309.
Return to the Summary Table.
UID Unique 32 bit number
Figure 3-281. UID_UNIQUE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UniqueID
R-X

Table 3-309. UID_UNIQUE Register Field Descriptions

Bit Field Type Reset Description
31-0 UniqueID R X Unique portion of the UID. This identifier will be unique across all
devices with the same PARTIDH.
Reset type: N/A

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3.16.16.8 UID_CHECKSUM Register (Offset = Eh) [Reset = X]

UID_CHECKSUM is shown in Figure 3-282 and described in Table 3-310.
Return to the Summary Table.
Fletcher checksum of UID_PSRAND and UID_UNIQUE registers
Figure 3-282. UID_CHECKSUM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Checksum
R-X

Table 3-310. UID_CHECKSUM Register Field Descriptions

Bit Field Type Reset Description
31-0 Checksum R X Fletcher checksum of UID_PSRANDx and UID_UINIQUE
Reset type: N/A

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3.16.17 WD_REGS Registers

Table 3-311 lists the memory-mapped registers for the WD_REGS registers. All register offset addresses not
listed in Table 3-311 should be considered as reserved locations and the register contents should not be
modified.
Table 3-311. WD_REGS Registers
Offset Acronym Register Name Write Protection Section
22h SCSR System Control & Status Register EALLOW Go
23h WDCNTR Watchdog Counter Register EALLOW Go
25h WDKEY Watchdog Reset Key Register EALLOW Go
29h WDCR Watchdog Control Register EALLOW Go
2Ah WDWCR Watchdog Windowed Control Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-312 shows the codes that are used for
access types in this section.
Table 3-312. WD_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1C W Write
1C 1 to clear
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.17.1 SCSR Register (Offset = 22h) [Reset = 5h]

SCSR is shown in Figure 3-283 and described in Table 3-313.
Return to the Summary Table.
System Control & Status Register
It is recommended to only use 16 bit accesses to write to this register. Use a read-modify-write instruction may
inadvertently clear other bits.
Figure 3-283. SCSR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WDINTS WDENINT WDOVERRIDE
R-0-0h R-1h R/W-0h R/W1C-1h

Table 3-313. SCSR Register Field Descriptions

Bit Field Type Reset Description
15-3 RESERVED R-0 0h Reserved
2 WDINTS R 1h Watchdog Interrupt Status
This bit indicates the state of the active-low watchdog interrupt signal
(synchronized to SYSCLK). If the watchdog interrupt is used to wake
the system from a low-power mode, then that mode should only be
entered while this bit is high. Likewise, this bit must go high before
the watchdog can be safely disabled and re-enabled.
Reset type: SYSRSn
0h (R/W) = The watchdog interrupt signal is active.
1h (R/W) = The watchdog interrupt signal is inactive.
1 WDENINT R/W 0h Watchdog Interrupt Enable/Reset Disable
This bit determines whether the watchdog triggers an interrupt
(WAKE/WDOG) or a reset (WDRS) when the counter expires.
Reset type: SYSRSn
0h (R/W) = Counter expiration triggers a reset. This is the default
state on power-up and after any system reset.
1h (R/W) = Counter expiration triggers an interrupt.
0 WDOVERRIDE R/W1C 1h If this bit is set to 1, the user is allowed to change the state of the
Watchdog disable (WDDIS) bit in the Watchdog Control (WDCR)
register. If the WDOVERRIDE bit is cleared, by writing a 1 the
WDDIS bit cannot be modified by the user. Writing a 0 will have
no effect. If this bit is cleared, then it will remain in this state until a
reset occurs. The current state of this bit is readable by the user.
Reset type: SYSRSn

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3.16.17.2 WDCNTR Register (Offset = 23h) [Reset = 0h]

WDCNTR is shown in Figure 3-284 and described in Table 3-314.
Return to the Summary Table.
Watchdog Counter Register
Figure 3-284. WDCNTR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
WDCNTR
R-0h

Table 3-314. WDCNTR Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R-0 0h Reserved
7-0 WDCNTR R 0h Watchdog Counter
These bits contain the current value of the watchdog counter. This
counter increments with each WDCLK (INTOSC1) cycle. If the
counter overflows, either an interrupt or a reset is generated based
on the value of the WDINTEN bit in the SCSR register. If the correct
value is written to the WDKEY register, this counter is reset to zero.
Reset type: IORSn

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3.16.17.3 WDKEY Register (Offset = 25h) [Reset = 0h]

WDKEY is shown in Figure 3-285 and described in Table 3-315.
Return to the Summary Table.
Watchdog Reset Key Register
Figure 3-285. WDKEY Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
WDKEY
R/W-0h

Table 3-315. WDKEY Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R-0 0h Reserved
7-0 WDKEY R/W 0h Watchdog Counter Reset
Writing 0x55 followed by 0xAA will cause the watchdog counter to
reset to zero, preventing an overflow. Writing other values has no
effect. Reads of this register return the value of the WDCR register.
Reset type: IORSn

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3.16.17.4 WDCR Register (Offset = 29h) [Reset = 0h]

WDCR is shown in Figure 3-286 and described in Table 3-316.
Return to the Summary Table.
Watchdog Control Register
This memory mapped register requires a delay between subsequent writes to the register, otherwise a second
write can be lost. The required delay is 69 SYSCLK cycles for a 200 MHz device, 45 SYSCLK cycles for a
120 MHz device, and 39 SYSCLK cycles for a 100 MHz device. This delay can be realized by adding NOP
instructions corresponding to the required delay cycles.
Figure 3-286. WDCR Register
15 14 13 12 11 10 9 8
RESERVED WDPRECLKDIV
R-0-0h R/W-0h

7 6 5 4 3 2 1 0
WDFLG WDDIS WDCHK WDPS
R/W1S-0h R/W-0h R-0/W-0h R/W-0h

Table 3-316. WDCR Register Field Descriptions

Bit Field Type Reset Description
15-12 RESERVED R-0 0h Reserved
11-8 WDPRECLKDIV R/W 0h Watchdog Clock Pre-divider
These bits determine the watchdog clock pre-divider, which is the
first of the two dividers between INTOSC1 and the watchdog counter
clock (WDCLK). The frequency of WDCLK is given by the formulas:
PREDIVCLK = INTOSC1 / Pre-divider
WDCLK = PREDIVCLK / Prescaler
Reset type: IORSn
0h (R/W) = PREDIVCLK = INTOSC1 / 512
1h (R/W) = PREDIVCLK = INTOSC1 / 1024
2h (R/W) = PREDIVCLK = INTOSC1 / 2048
3h (R/W) = PREDIVCLK = INTOSC1 / 4096
4h (R/W) = Reserved
5h (R/W) = Reserved
6h (R/W) = Reserved
7h (R/W) = Reserved
8h (R/W) = PREDIVCLK = INTOSC1 / 2
9h (R/W) = PREDIVCLK = INTOSC1 / 4
Ah (R/W) = PREDIVCLK = INTOSC1 / 8
Bh (R/W) = PREDIVCLK = INTOSC1 / 16
Ch (R/W) = PREDIVCLK = INTOSC1 / 32
Dh (R/W) = PREDIVCLK = INTOSC1 / 64
Eh (R/W) = PREDIVCLK = INTOSC1 / 128
Fh (R/W) = PREDIVCLK = INTOSC1 / 256
7 WDFLG R/W1S 0h Watchdog reset status flag bit. This bit, if set, indicates a watchdog
reset (WDRSTn) generated the reset condition. If 0, then it was en
external device or power-up reset condition. This bit remains latched
until the user writes a 1 to clear the condition. Writes of 0 will be
ignored.
Reset type: IORSn
6 WDDIS R/W 0h Watchdog Disable
Setting this bit disables the watchdog module. Clearing this bit
enables the watchdog module. This bit can be locked by the
WDOVERRIDE bit in the SCSR register. The watchdog is enabled
on reset.
Reset type: IORSn

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Table 3-316. WDCR Register Field Descriptions (continued)

Bit Field Type Reset Description
5-3 WDCHK R-0/W 0h Watchdog Check Bits
During any write to this register, these bits must be written with the
value 101 (binary). Writing any other value will immediately trigger
the watchdog reset or interrupt.
Reset type: IORSn
2-0 WDPS R/W 0h Watchdog Clock Prescaler
These bits determine the watchdog clock prescaler, which is the
second of the two dividers between INTOSC1 and the watchdog
counter clock (WDCLK). The frequency of WDCLK is given by the
formulas:
PREDIVCLK = INTOSC1 / Pre-divider
WDCLK = PREDIVCLK / Prescaler
The watchdog reset or interrupt pulse is 512 INTOSC1 cycles long,
so the counter period must be longer. To guarantee this, the product
of the prescaler and pre-divider must be greater than or equal to four.
The default prescaler value is 1.
Reset type: IORSn
0h (R/W) = WDCLK = PREDIVCLK / 1
1h (R/W) = WDCLK = PREDIVCLK / 1
2h (R/W) = WDCLK = PREDIVCLK / 2
3h (R/W) = WDCLK = PREDIVCLK / 4
4h (R/W) = WDCLK = PREDIVCLK / 8
5h (R/W) = WDCLK = PREDIVCLK / 16
6h (R/W) = WDCLK = PREDIVCLK / 32
7h (R/W) = WDCLK = PREDIVCLK / 64

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3.16.17.5 WDWCR Register (Offset = 2Ah) [Reset = 0h]

WDWCR is shown in Figure 3-287 and described in Table 3-317.
Return to the Summary Table.
Watchdog Windowed Control Register
Figure 3-287. WDWCR Register
15 14 13 12 11 10 9 8
RESERVED FIRSTKEY
R-0-0h R-0h

7 6 5 4 3 2 1 0
MIN
R/W-0h

Table 3-317. WDWCR Register Field Descriptions

Bit Field Type Reset Description
15-9 RESERVED R-0 0h Reserved
8 FIRSTKEY R 0h This bit indicates if the 1st valid WDKEY (0x55 + 0xAA) got detected
after MIN was configured to a non-zero value
0: First Valid Key after non-zero MIN configuration has not happened
yet
1: First Valid key after non-zero MIN configuration got detected
Notes:
[1] If MIN = 0, this bit is never set
[2] If MIN is changed back to 0x0 from a non-zero value, this bit is
auto-cleared
[3] This bit is added for debug purposes only
Reset type: IORSn
7-0 MIN R/W 0h Watchdog Window Threshold
These bits specify the lower limit of the watchdog counter reset
window. If the counter is reset via the WDKEY register before
the counter value reaches the value in this register, the watchdog
immediately triggers a reset or interrupt.
Reset type: IORSn

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3.16.18 XINT_REGS Registers

Table 3-318 lists the memory-mapped registers for the XINT_REGS registers. All register offset addresses
not listed in Table 3-318 should be considered as reserved locations and the register contents should not be
modified.
Table 3-318. XINT_REGS Registers
Offset Acronym Register Name Write Protection Section
0h XINT1CR XINT1 configuration register Go
1h XINT2CR XINT2 configuration register Go
2h XINT3CR XINT3 configuration register Go
3h XINT4CR XINT4 configuration register Go
4h XINT5CR XINT5 configuration register Go
8h XINT1CTR XINT1 counter register Go
9h XINT2CTR XINT2 counter register Go
Ah XINT3CTR XINT3 counter register Go

Complex bit access types are encoded to fit into small table cells. Table 3-319 shows the codes that are used for
access types in this section.
Table 3-319. XINT_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.18.1 XINT1CR Register (Offset = 0h) [Reset = 0h]

XINT1CR is shown in Figure 3-288 and described in Table 3-320.
Return to the Summary Table.
XINT1 configuration register
Figure 3-288. XINT1CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-320. XINT1CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.18.2 XINT2CR Register (Offset = 1h) [Reset = 0h]

XINT2CR is shown in Figure 3-289 and described in Table 3-321.
Return to the Summary Table.
XINT2 configuration register
Figure 3-289. XINT2CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-321. XINT2CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.18.3 XINT3CR Register (Offset = 2h) [Reset = 0h]

XINT3CR is shown in Figure 3-290 and described in Table 3-322.
Return to the Summary Table.
XINT3 configuration register
Figure 3-290. XINT3CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-322. XINT3CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.18.4 XINT4CR Register (Offset = 3h) [Reset = 0h]

XINT4CR is shown in Figure 3-291 and described in Table 3-323.
Return to the Summary Table.
XINT4 configuration register
Figure 3-291. XINT4CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-323. XINT4CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.18.5 XINT5CR Register (Offset = 4h) [Reset = 0h]

XINT5CR is shown in Figure 3-292 and described in Table 3-324.
Return to the Summary Table.
XINT5 configuration register
Figure 3-292. XINT5CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-324. XINT5CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.18.6 XINT1CTR Register (Offset = 8h) [Reset = 0h]

XINT1CTR is shown in Figure 3-293 and described in Table 3-325.
Return to the Summary Table.
XINT1 counter register
Figure 3-293. XINT1CTR Register
15 14 13 12 11 10 9 8
INTCTR
R-0h

7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-325. XINT1CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until
the next valid interrupt edge is detected. The counter must only be
reset by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.16.18.7 XINT2CTR Register (Offset = 9h) [Reset = 0h]

XINT2CTR is shown in Figure 3-294 and described in Table 3-326.
Return to the Summary Table.
XINT2 counter register
Figure 3-294. XINT2CTR Register
15 14 13 12 11 10 9 8
INTCTR
R-0h

7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-326. XINT2CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until
the next valid interrupt edge is detected. The counter must only be
reset by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.16.18.8 XINT3CTR Register (Offset = Ah) [Reset = 0h]

XINT3CTR is shown in Figure 3-295 and described in Table 3-327.
Return to the Summary Table.
XINT3 counter register
Figure 3-295. XINT3CTR Register
15 14 13 12 11 10 9 8
INTCTR
R-0h

7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-327. XINT3CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until
the next valid interrupt edge is detected. The counter must only be
reset by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.16.19 LFU_REGS Registers

Table 3-328 lists the memory-mapped registers for the LFU_REGS registers. All register offset addresses not
listed in Table 3-328 should be considered as reserved locations and the register contents should not be
modified.
Table 3-328. LFU_REGS Registers
Offset Acronym Register Name Write Protection Section
0h LFUConfig LFU configuration Register EALLOW Go
2h LFUStatus LFU Configuration Status Register Go
10h SWConfig1_SYSRSn Spare registers reset by SYSRSn EALLOW Go
12h SWConfig2_SYSRSn Spare registers reset by SYSRSn EALLOW Go
14h SWConfig1_XRSn Spare registers reset by XRSn EALLOW Go
16h SWConfig2_XRSn Spare registers reset by XRSn EALLOW Go
18h SWConfig1_PORESETn Spare registers reset by PORESETn EALLOW Go
1Ah SWConfig2_PORESETn Spare registers reset by PORESETn EALLOW Go
1Ch LFU_LOCK LFU Lock Configuration Go
1Eh LFU_COMMIT LFU Commit Configuration Go

Complex bit access types are encoded to fit into small table cells. Table 3-329 shows the codes that are used for
access types in this section.
Table 3-329. LFU_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.19.1 LFUConfig Register (Offset = 0h) [Reset = 0h]

LFUConfig is shown in Figure 3-296 and described in Table 3-330.
Return to the Summary Table.
LFU configuration Register
Figure 3-296. LFUConfig Register
31 30 29 28 27 26 25 24
RESERVED
R/W-0h

23 22 21 20 19 18 17 16
RESERVED LS01Swap
R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED PieVectorSwap RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED LFU_CLA1 RESERVED LFU_CPU
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-330. LFUConfig Register Field Descriptions

Bit Field Type Reset Description
31-17 RESERVED R/W 0h Reserved
16 LS01Swap R/W 0h 0: LS0 and LS1 mapped to the original location
1: Location of LS0 and LS1 is swapped.
Reset type: SYSRSn
15-13 RESERVED R/W 0h Reserved
12 PieVectorSwap R/W 0h 0: PIE vector table is mapped to the original location
1: PIE Vector Table is swapped to alternate location
Reset type: SYSRSn
11-9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7-5 RESERVED R/W 0h Reserved
4 LFU_CLA1 R/W 0h 0: No pending LFU Requests
1: LFU Request in progress
This bit is used by compiler/application code for implementing CLA1
LFU
Reset type: SYSRSn
3-1 RESERVED R/W 0h Reserved
0 LFU_CPU R/W 0h 0: No pending LFU Requests
1: LFU Request in progress
This bit is used by compiler/application code for implementing CPU
LFU
Reset type: SYSRSn

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3.16.19.2 LFUStatus Register (Offset = 2h) [Reset = 0h]

LFUStatus is shown in Figure 3-297 and described in Table 3-331.
Return to the Summary Table.
LFU Configuration Status Register
Figure 3-297. LFUStatus Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED LS01Swap
R-0-0h R-0h

15 14 13 12 11 10 9 8
RESERVED PieVectorSwap RESERVED
R-0-0h R-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED
R-0-0h

Table 3-331. LFUStatus Register Field Descriptions

Bit Field Type Reset Description
31-17 RESERVED R-0 0h Reserved
16 LS01Swap R 0h 0: LS0 and LS1 mapped to the original location
1: Location of LS0 and LS1 is swapped.
Note: An initiated LSx swap will become unsucessful if the LS0 and
LS1 memories have different security configurations
Reset type: SYSRSn
15-13 RESERVED R-0 0h Reserved
12 PieVectorSwap R 0h 0: PIE vector table is mapped to the original location
1: PIE Vector Table is swapped to alternate location
Reset type: SYSRSn
11-0 RESERVED R-0 0h Reserved

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3.16.19.3 SWConfig1_SYSRSn Register (Offset = 10h) [Reset = 0h]

SWConfig1_SYSRSn is shown in Figure 3-298 and described in Table 3-332.
Return to the Summary Table.
Spare registers reset by SYSRSn
Figure 3-298. SWConfig1_SYSRSn Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
R/W-0h

Table 3-332. SWConfig1_SYSRSn Register Field Descriptions

Bit Field Type Reset Description
31-0 BITS R/W 0h R/W bits reset by SYSRSn to be used by the application software
Reset type: SYSRSn

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3.16.19.4 SWConfig2_SYSRSn Register (Offset = 12h) [Reset = 0h]

SWConfig2_SYSRSn is shown in Figure 3-299 and described in Table 3-333.
Return to the Summary Table.
Spare registers reset by SYSRSn
Figure 3-299. SWConfig2_SYSRSn Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
R/W-0h

Table 3-333. SWConfig2_SYSRSn Register Field Descriptions

Bit Field Type Reset Description
31-0 BITS R/W 0h R/W bits reset by SYSRSn to be used by the application software
Reset type: SYSRSn

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3.16.19.5 SWConfig1_XRSn Register (Offset = 14h) [Reset = 0h]

SWConfig1_XRSn is shown in Figure 3-300 and described in Table 3-334.
Return to the Summary Table.
Spare registers reset by XRSn
Figure 3-300. SWConfig1_XRSn Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
R/W-0h

Table 3-334. SWConfig1_XRSn Register Field Descriptions

Bit Field Type Reset Description
31-0 BITS R/W 0h R/W bits reset by XRSn to be used by the application software
Reset type: XRSn

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3.16.19.6 SWConfig2_XRSn Register (Offset = 16h) [Reset = 0h]

SWConfig2_XRSn is shown in Figure 3-301 and described in Table 3-335.
Return to the Summary Table.
Spare registers reset by XRSn
Figure 3-301. SWConfig2_XRSn Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
R/W-0h

Table 3-335. SWConfig2_XRSn Register Field Descriptions

Bit Field Type Reset Description
31-0 BITS R/W 0h R/W bits reset by XRSn to be used by the application software
Reset type: XRSn

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3.16.19.7 SWConfig1_PORESETn Register (Offset = 18h) [Reset = 0h]

SWConfig1_PORESETn is shown in Figure 3-302 and described in Table 3-336.
Return to the Summary Table.
Spare registers reset by PORESETn
Figure 3-302. SWConfig1_PORESETn Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
R/W-0h

Table 3-336. SWConfig1_PORESETn Register Field Descriptions

Bit Field Type Reset Description
31-0 BITS R/W 0h R/W bits reset by PORESETn to be used by the application software
Reset type: PORESETn

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3.16.19.8 SWConfig2_PORESETn Register (Offset = 1Ah) [Reset = 0h]

SWConfig2_PORESETn is shown in Figure 3-303 and described in Table 3-337.
Return to the Summary Table.
Spare registers reset by PORESETn
Figure 3-303. SWConfig2_PORESETn Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
R/W-0h

Table 3-337. SWConfig2_PORESETn Register Field Descriptions

Bit Field Type Reset Description
31-0 BITS R/W 0h R/W bits reset by PORESETn to be used by the application software
Reset type: PORESETn

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3.16.19.9 LFU_LOCK Register (Offset = 1Ch) [Reset = 0h]

LFU_LOCK is shown in Figure 3-304 and described in Table 3-338.
Return to the Summary Table.
LFU Lock Configuration
Figure 3-304. LFU_LOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED SWConfig2_PO SWConfig1_PO SWConfig2_XR SWConfig1_XR SWConfig2_SY SWConfig1_SY
RESETn RESETn Sn Sn SRSn SRSn
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED LFUConfig
R-0-0h R/W-0h

Table 3-338. LFU_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R-0 0h Reserved
13 SWConfig2_PORESETn R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: SYSRSn
12 SWConfig1_PORESETn R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: SYSRSn
11 SWConfig2_XRSn R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: SYSRSn
10 SWConfig1_XRSn R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: SYSRSn
9 SWConfig2_SYSRSn R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: SYSRSn
8 SWConfig1_SYSRSn R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: SYSRSn
7-1 RESERVED R-0 0h Reserved
0 LFUConfig R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: SYSRSn

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3.16.19.10 LFU_COMMIT Register (Offset = 1Eh) [Reset = 0h]

LFU_COMMIT is shown in Figure 3-305 and described in Table 3-339.
Return to the Summary Table.
LFU Commit Configuration
Figure 3-305. LFU_COMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED SWConfig2_PO SWConfig1_PO SWConfig2_XR SWConfig1_XR SWConfig2_SY SWConfig1_SY
RESETn RESETn Sn Sn SRSn SRSn
R-0-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
RESERVED LFUConfig
R-0-0h R/WSonce-0h

Table 3-339. LFU_COMMIT Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R-0 0h Reserved
13 SWConfig2_PORESETn R/WSonce 0h 0: Register lock configuration is not committed.
1: Register lock configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: SYSRSn
12 SWConfig1_PORESETn R/WSonce 0h 0: Register lock configuration is not committed.
1: Register lock configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: SYSRSn
11 SWConfig2_XRSn R/WSonce 0h 0: Register lock configuration is not committed.
1: Register lock configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: SYSRSn
10 SWConfig1_XRSn R/WSonce 0h 0: Register lock configuration is not committed.
1: Register lock configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: SYSRSn
9 SWConfig2_SYSRSn R/WSonce 0h 0: Register lock configuration is not committed.
1: Register lock configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: SYSRSn
8 SWConfig1_SYSRSn R/WSonce 0h 0: Register lock configuration is not committed.
1: Register lock configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: SYSRSn
7-1 RESERVED R-0 0h Reserved

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Table 3-339. LFU_COMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
0 LFUConfig R/WSonce 0h 0: Register lock configuration is not committed.
1: Register lock configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: SYSRSn

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3.16.20 Register to Driverlib Function Mapping

3.16.20.1 CPUTIMER Registers to Driverlib Functions

Table 3-340. CPUTIMER Registers to Driverlib Functions
File Driverlib Function
TIM
cputimer.h CPUTimer_getTimerCount
PRD
cputimer.h CPUTimer_setPeriod
TCR
cputimer.c CPUTimer_setEmulationMode
cputimer.h CPUTimer_clearOverflowFlag
cputimer.h CPUTimer_disableInterrupt
cputimer.h CPUTimer_enableInterrupt
cputimer.h CPUTimer_reloadTimerCounter
cputimer.h CPUTimer_stopTimer
cputimer.h CPUTimer_resumeTimer
cputimer.h CPUTimer_startTimer
cputimer.h CPUTimer_getTimerOverflowStatus
TPR
cputimer.h CPUTimer_setPreScaler
TPRH
cputimer.h CPUTimer_setPreScaler

3.16.20.2 DCSM Registers to Driverlib Functions

Table 3-341. DCSM Registers to Driverlib Functions
File Driverlib Function
Z1OTP_LINKPOINTER1
-
Z1OTP_LINKPOINTER2
-
Z1OTP_LINKPOINTER3
-
Z1OTP_JLM_ENABLE
-
Z1OTP_GPREG1
-
Z1OTP_GPREG2
-
Z1OTP_GPREG3
-
Z1OTP_GPREG4
-
Z1OTP_PSWDLOCK
-
Z1OTP_CRCLOCK
-

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Table 3-341. DCSM Registers to Driverlib Functions (continued)

File Driverlib Function
Z1OTP_JTAGPSWDH0
-
Z1OTP_JTAGPSWDH1
-
Z1OTP_CMACKEY0
-
Z1OTP_CMACKEY1
-
Z1OTP_CMACKEY2
-
Z1OTP_CMACKEY3
-
Z2OTP_LINKPOINTER1
-
Z2OTP_LINKPOINTER2
-
Z2OTP_LINKPOINTER3
-
Z2OTP_GPREG1
-
Z2OTP_GPREG2
-
Z2OTP_GPREG3
-
Z2OTP_GPREG4
-
Z2OTP_PSWDLOCK
-
Z2OTP_CRCLOCK
-
Z1_LINKPOINTER
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_readZone1CSMPwd
dcsm.h DCSM_getZone1LinkPointerError
Z1_OTPSECLOCK
dcsm.h DCSM_getZone1OTPSecureLockStatus
Z1_JLM_ENABLE
-
Z1_LINKPOINTERERR
dcsm.h DCSM_getZone1LinkPointerError
Z1_GPREG1
-
Z1_GPREG2
-
Z1_GPREG3

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Table 3-341. DCSM Registers to Driverlib Functions (continued)

File Driverlib Function
-
Z1_GPREG4
-
Z1_CSMKEY0
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_writeZone1CSM
Z1_CSMKEY1
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_writeZone1CSM
Z1_CSMKEY2
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_writeZone1CSM
Z1_CSMKEY3
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_writeZone1CSM
Z1_CR
dcsm.h DCSM_secureZone1
dcsm.h DCSM_getZone1CSMSecurityStatus
dcsm.h DCSM_getZone1ControlStatus
Z1_GRABSECT1R
-
Z1_GRABSECT2R
-
Z1_GRABSECT3R
-
Z1_GRABRAM1R
-
Z1_EXEONLYSECT1R
dcsm.c DCSM_getZone1FlashEXEStatus
Z1_EXEONLYSECT2R
dcsm.c DCSM_getZone1FlashEXEStatus
Z1_EXEONLYRAM1R
dcsm.c DCSM_getZone1RAMEXEStatus
Z1_JTAGKEY0
-
Z1_JTAGKEY1
-
Z1_JTAGKEY2
-
Z1_JTAGKEY3
-
Z1_CMACKEY0
-
Z1_CMACKEY1
-

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Table 3-341. DCSM Registers to Driverlib Functions (continued)

File Driverlib Function
Z1_CMACKEY2
-
Z1_CMACKEY3
-
Z2_LINKPOINTER
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_readZone2CSMPwd
dcsm.h DCSM_getZone2LinkPointerError
Z2_OTPSECLOCK
dcsm.h DCSM_getZone2OTPSecureLockStatus
Z2_LINKPOINTERERR
dcsm.h DCSM_getZone2LinkPointerError
Z2_GPREG1
-
Z2_GPREG2
-
Z2_GPREG3
-
Z2_GPREG4
-
Z2_CSMKEY0
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_writeZone2CSM
Z2_CSMKEY1
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_writeZone2CSM
Z2_CSMKEY2
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_writeZone2CSM
Z2_CSMKEY3
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_writeZone2CSM
Z2_CR
dcsm.h DCSM_secureZone2
dcsm.h DCSM_getZone2CSMSecurityStatus
dcsm.h DCSM_getZone2ControlStatus
Z2_GRABSECT1R
-
Z2_GRABSECT2R
-
Z2_GRABSECT3R
-
Z2_GRABRAM1R
-
Z2_EXEONLYSECT1R

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Table 3-341. DCSM Registers to Driverlib Functions (continued)

File Driverlib Function
dcsm.c DCSM_getZone2FlashEXEStatus
Z2_EXEONLYSECT2R
dcsm.c DCSM_getZone2FlashEXEStatus
Z2_EXEONLYRAM1R
dcsm.c DCSM_getZone2RAMEXEStatus
FLSEM
dcsm.c DCSM_claimZoneSemaphore
dcsm.c DCSM_releaseZoneSemaphore
SECTSTAT1
dcsm.h DCSM_getFlashSectorZone
SECTSTAT2
dcsm.h DCSM_getFlashSectorZone
SECTSTAT3
dcsm.h DCSM_getFlashSectorZone
RAMSTAT1
dcsm.h DCSM_getRAMZone
SECERRSTAT
dcsm.h DCSM_getFlashErrorStatus
SECERRCLR
dcsm.h DCSM_clearFlashErrorStatus
SECERRFRC
dcsm.h DCSM_forceFlashErrorStatus

3.16.20.3 MEMCFG Registers to Driverlib Functions

Table 3-342. MEMCFG Registers to Driverlib Functions
File Driverlib Function
DXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
DXCOMMIT
memcfg.c MemCfg_commitConfig
DXACCPROT0
memcfg.c MemCfg_setProtection
DXTEST
memcfg.c MemCfg_setTestMode
DXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
DXINITDONE
memcfg.c MemCfg_getInitStatus
DXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
LSXLOCK
memcfg.c MemCfg_lockConfig

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Table 3-342. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
memcfg.c MemCfg_unlockConfig
LSXCOMMIT
memcfg.c MemCfg_commitConfig
LSXMSEL
memcfg.c MemCfg_setLSRAMControllerSel
LSXCLAPGM
memcfg.h MemCfg_setCLAMemType
LSXACCPROT0
memcfg.c MemCfg_setProtection
LSXACCPROT1
-
LSXTEST
memcfg.c MemCfg_setTestMode
LSXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
LSXINITDONE
memcfg.c MemCfg_getInitStatus
LSXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
GSXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
GSXCOMMIT
memcfg.c MemCfg_commitConfig
GSXACCPROT0
memcfg.c MemCfg_setProtection
GSXTEST
memcfg.c MemCfg_setTestMode
GSXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
GSXINITDONE
memcfg.c MemCfg_getInitStatus
GSXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
MSGXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
MSGXCOMMIT
memcfg.c MemCfg_commitConfig
MSGXTEST
memcfg.c MemCfg_setTestMode

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Table 3-342. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
MSGXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
MSGXINITDONE
memcfg.c MemCfg_getInitStatus
MSGXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
ROM_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
ROM_TEST
memcfg.c MemCfg_setTestMode
ROM_FORCE_ERROR
memcfg.c MemCfg_forceMemError
NMAVFLG
memcfg.h MemCfg_getViolationInterruptStatus
NMAVSET
memcfg.h MemCfg_forceViolationInterrupt
NMAVCLR
memcfg.h MemCfg_clearViolationInterruptStatus
NMAVINTEN
memcfg.h MemCfg_enableViolationInterrupt
memcfg.h MemCfg_disableViolationInterrupt
NMCPURDAVADDR
memcfg.c MemCfg_getViolationAddress
NMCPUWRAVADDR
memcfg.c MemCfg_getViolationAddress
NMCPUFAVADDR
-
NMDMAWRAVADDR
-
NMCLA1RDAVADDR
-
NMCLA1WRAVADDR
-
NMCLA1FAVADDR
-
NMDMARDAVADDR
-
MAVFLG
memcfg.h MemCfg_getViolationInterruptStatus
MAVSET
memcfg.h MemCfg_forceViolationInterrupt
MAVCLR

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Table 3-342. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
memcfg.h MemCfg_clearViolationInterruptStatus
MAVINTEN
memcfg.h MemCfg_enableViolationInterrupt
memcfg.h MemCfg_disableViolationInterrupt
MCPUFAVADDR
memcfg.c MemCfg_getViolationAddress
MCPUWRAVADDR
-
MDMAWRAVADDR
-
MHICWRAVADDR
-
NMHICRDAVADDR
-
NMHICWRAVADDR
-
UCERRFLG
memcfg.h MemCfg_getUncorrErrorStatus
UCERRSET
memcfg.h MemCfg_forceUncorrErrorStatus
UCERRCLR
memcfg.h MemCfg_clearUncorrErrorStatus
UCCPUREADDR
memcfg.c MemCfg_getUncorrErrorAddress
UCDMAREADDR
memcfg.c MemCfg_getUncorrErrorAddress
UCCLA1READDR
-
UCHICAREADDR
-
CERRFLG
memcfg.h MemCfg_getCorrErrorStatus
CERRSET
memcfg.c MemCfg_getCorrErrorAddress
memcfg.h MemCfg_forceCorrErrorStatus
CERRCLR
memcfg.c MemCfg_getCorrErrorAddress
memcfg.h MemCfg_clearCorrErrorStatus
CCPUREADDR
memcfg.c MemCfg_getCorrErrorAddress
CDMAREADDR
-
CCLA1READDR
-
CERRCNT

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Table 3-342. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
memcfg.h MemCfg_getCorrErrorCount
CERRTHRES
memcfg.h MemCfg_setCorrErrorThreshold
CEINTFLG
memcfg.h MemCfg_getCorrErrorInterruptStatus
CEINTCLR
memcfg.h MemCfg_clearCorrErrorInterruptStatus
CEINTSET
memcfg.h MemCfg_forceCorrErrorInterrupt
CEINTEN
memcfg.h MemCfg_enableCorrErrorInterrupt
memcfg.h MemCfg_disableCorrErrorInterrupt
CHICREADDR
-
CPU_RAM_TEST_ERROR_STS
memcfg.h MemCfg_getDiagErrorStatus
memcfg.h MemCfg_clearDiagErrorStatus
CPU_RAM_TEST_ERROR_STS_CLR
memcfg.h MemCfg_clearDiagErrorStatus
CPU_RAM_TEST_ERROR_ADDR
memcfg.h MemCfg_getDiagErrorAddress

3.16.20.4 NMI Registers to Driverlib Functions

Table 3-343. NMI Registers to Driverlib Functions
File Driverlib Function
CFG
sysctl.h SysCtl_enableNMIGlobalInterrupt
FLG
sysctl.h SysCtl_getNMIStatus
sysctl.h SysCtl_getNMIFlagStatus
sysctl.h SysCtl_isNMIFlagSet
sysctl.h SysCtl_clearNMIStatus
sysctl.h SysCtl_clearAllNMIFlags
sysctl.h SysCtl_forceNMIFlags
FLGCLR
sysctl.h SysCtl_clearNMIStatus
sysctl.h SysCtl_clearAllNMIFlags
FLGFRC
sysctl.h SysCtl_forceNMIFlags
WDCNT
sysctl.h SysCtl_getNMIWatchdogCounter
WDPRD
sysctl.h SysCtl_setNMIWatchdogPeriod
sysctl.h SysCtl_getNMIWatchdogPeriod
SHDFLG

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Table 3-343. NMI Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.h SysCtl_getNMIShadowFlagStatus
sysctl.h SysCtl_isNMIShadowFlagSet
ERRORSTS
sysctl.h SysCtl_isErrorTriggered
sysctl.h SysCtl_getErrorPinStatus
sysctl.h SysCtl_forceError
sysctl.h SysCtl_clearError
ERRORSTSCLR
sysctl.h SysCtl_clearError
ERRORSTSFRC
sysctl.h SysCtl_forceError
ERRORCTL
sysctl.h SysCtl_selectErrPinPolarity
ERRORLOCK
sysctl.h SysCtl_lockErrControl

3.16.20.5 PIE Registers to Driverlib Functions

Table 3-344. PIE Registers to Driverlib Functions
File Driverlib Function
CTRL
interrupt.c Interrupt_initModule
interrupt.c Interrupt_defaultHandler
interrupt.h Interrupt_enablePIE
interrupt.h Interrupt_disablePIE
ACK
interrupt.c Interrupt_disable
interrupt.h Interrupt_clearACKGroup
IER1
interrupt.c Interrupt_initModule
interrupt.c Interrupt_enable
interrupt.c Interrupt_disable
IFR1
interrupt.c Interrupt_initModule
IER2
interrupt.c Interrupt_initModule
IFR2
interrupt.c Interrupt_initModule
IER3
interrupt.c Interrupt_initModule
IFR3
interrupt.c Interrupt_initModule
IER4
interrupt.c Interrupt_initModule
IFR4
interrupt.c Interrupt_initModule

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Table 3-344. PIE Registers to Driverlib Functions (continued)

File Driverlib Function
IER5
interrupt.c Interrupt_initModule
IFR5
interrupt.c Interrupt_initModule
IER6
interrupt.c Interrupt_initModule
IFR6
interrupt.c Interrupt_initModule
IER7
interrupt.c Interrupt_initModule
IFR7
interrupt.c Interrupt_initModule
IER8
interrupt.c Interrupt_initModule
IFR8
interrupt.c Interrupt_initModule
IER9
interrupt.c Interrupt_initModule
IFR9
interrupt.c Interrupt_initModule
IER10
interrupt.c Interrupt_initModule
IFR10
interrupt.c Interrupt_initModule
IER11
interrupt.c Interrupt_initModule
IFR11
interrupt.c Interrupt_initModule
IER12
interrupt.c Interrupt_initModule
IFR12
interrupt.c Interrupt_initModule

3.16.20.6 SYSCTL Registers to Driverlib Functions

Table 3-345. SYSCTL Registers to Driverlib Functions
File Driverlib Function
PARTIDL
sysctl.c SysCtl_getDeviceParametric
PARTIDH
sysctl.c SysCtl_getDeviceParametric
REVID
sysctl.h SysCtl_getDeviceRevision
FUSEERR
sysctl.h SysCtl_getEfuseError
SOFTPRES0

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Table 3-345. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.h SysCtl_resetPeripheral
SOFTPRES2
- See SOFTPRES0
SOFTPRES3
- See SOFTPRES0
SOFTPRES4
- See SOFTPRES0
SOFTPRES6
- See SOFTPRES0
SOFTPRES7
- See SOFTPRES0
SOFTPRES8
- See SOFTPRES0
SOFTPRES9
- See SOFTPRES0
SOFTPRES10
- See SOFTPRES0
SOFTPRES13
- See SOFTPRES0
SOFTPRES14
- See SOFTPRES0
SOFTPRES16
- See SOFTPRES0
SOFTPRES17
-
SOFTPRES18
-
SOFTPRES19
-
SOFTPRES20
-
SOFTPRES21
-
SOFTPRES25
-
SOFTPRES26
-
SOFTPRES27
-
TAP_STATUS
-
ECAPTYPE
sysctl.c SysCtl_configureType
sysctl.c SysCtl_isConfigTypeLocked
SDFMTYPE

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Table 3-345. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.c SysCtl_configureType
sysctl.c SysCtl_isConfigTypeLocked
CLKCFGLOCK1
sysctl.c SysCtl_lockClkConfig
CLKSRCCTL1
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
sysctl.c SysCtl_selectXTAL
sysctl.c SysCtl_selectXTALSingleEnded
sysctl.c SysCtl_selectOscSource
sysctl.h SysCtl_turnOnOsc
sysctl.h SysCtl_turnOffOsc
sysctl.h SysCtl_enableWatchdogInHalt
sysctl.h SysCtl_disableWatchdogInHalt
CLKSRCCTL2
can.h CAN_selectClockSource
CLKSRCCTL3
sysctl.h SysCtl_selectClockOutSource
SYSPLLCTL1
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
SYSPLLMULT
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
SYSPLLSTS
sysctl.c SysCtl_setClock
SYSCLKDIVSEL
sysctl.c SysCtl_getClock
sysctl.h SysCtl_setPLLSysClk
AUXCLKDIVSEL
sysctl.h SysCtl_setMCANClk
XCLKOUTDIVSEL
sysctl.h SysCtl_setXClk
LOSPCP
sysctl.c SysCtl_getLowSpeedClock
sysctl.h SysCtl_setLowSpeedClock
MCDCR
sysctl.h SysCtl_enableMCD
sysctl.h SysCtl_disableMCD
sysctl.h SysCtl_isMCDClockFailureDetected
sysctl.h SysCtl_resetMCD
sysctl.h SysCtl_connectMCDClockSource
sysctl.h SysCtl_disconnectMCDClockSource
X1CNT
sysctl.c SysCtl_pollX1Counter

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Table 3-345. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.h SysCtl_getExternalOscCounterValue
sysctl.h SysCtl_clearExternalOscCounterValue
XTALCR
sysctl.c SysCtl_setClock
sysctl.c SysCtl_selectXTAL
sysctl.c SysCtl_selectXTALSingleEnded
sysctl.h SysCtl_setExternalOscMode
sysctl.h SysCtl_turnOnOsc
sysctl.h SysCtl_turnOffOsc
XTALCR2
sysctl.c SysCtl_selectXTAL
CLKFAILCFG
-
CPUSYSLOCK1
sysctl.c SysCtl_lockSysConfig
CPUSYSLOCK2
-
PIEVERRADDR
sysctl.h SysCtl_getPIEVErrAddr
PCLKCR0
sysctl.h SysCtl_enablePeripheral
sysctl.h SysCtl_disablePeripheral
PCLKCR2
- See PCLKCR0
PCLKCR3
- See PCLKCR0
PCLKCR4
- See PCLKCR0
PCLKCR6
- See PCLKCR0
PCLKCR7
- See PCLKCR0
PCLKCR8
- See PCLKCR0
PCLKCR9
- See PCLKCR0
PCLKCR10
- See PCLKCR0
PCLKCR13
- See PCLKCR0
PCLKCR14
- See PCLKCR0
PCLKCR16
- See PCLKCR0
PCLKCR17

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Table 3-345. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
-
PCLKCR18
-
PCLKCR19
-
PCLKCR20
-
PCLKCR21
-
PCLKCR25
-
PCLKCR26
-
PCLKCR27
-
SIMRESET
sysctl.h SysCtl_simulateReset
LPMCR
sysctl.h SysCtl_enterIdleMode
sysctl.h SysCtl_enterStandbyMode
sysctl.h SysCtl_enterHaltMode
sysctl.h SysCtl_setStandbyQualificationPeriod
sysctl.h SysCtl_enableWatchdogStandbyWakeup
sysctl.h SysCtl_disableWatchdogStandbyWakeup
GPIOLPMSEL0
sysctl.h SysCtl_enableLPMWakeupPin
sysctl.h SysCtl_disableLPMWakeupPin
GPIOLPMSEL1
sysctl.h SysCtl_enableLPMWakeupPin
sysctl.h SysCtl_disableLPMWakeupPin
TMR2CLKCTL
cputimer.h CPUTimer_selectClockSource
sysctl.h SysCtl_setCputimer2Clk
RESCCLR
sysctl.h SysCtl_clearResetCause
sysctl.h SysCtl_clearWatchdogResetStatus
RESC
sysctl.h SysCtl_getResetCause
sysctl.h SysCtl_clearResetCause
sysctl.h SysCtl_getWatchdogResetStatus
sysctl.h SysCtl_clearWatchdogResetStatus
MCANWAKESTATUS
sysctl.h SysCtl_isMCANWakeStatusSet
sysctl.h SysCtl_clearMCANWakeStatus
MCANWAKESTATUSCLR

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Table 3-345. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.h SysCtl_clearMCANWakeStatus
CLKSTOPREQ
-
CLKSTOPACK
-
CLA1TASKSRCSELLOCK
-
DMACHSRCSELLOCK
-
CLA1TASKSRCSEL1
cla.c CLA_setTriggerSource
CLA1TASKSRCSEL2
cla.c CLA_setTriggerSource
DMACHSRCSEL1
dma.c DMA_configMode
DMACHSRCSEL2
dma.c DMA_configMode
ADCA_AC
-
ADCB_AC
-
ADCC_AC
-
CMPSS1_AC
-
CMPSS2_AC
-
CMPSS3_AC
-
CMPSS4_AC
-
DACA_AC
-
DACB_AC
-
EPWM1_AC
-
EPWM2_AC
-
EPWM3_AC
-
EPWM4_AC
-
EPWM5_AC
-

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Table 3-345. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
EPWM6_AC
-
EPWM7_AC
-
EPWM8_AC
-
EQEP1_AC
-
EQEP2_AC
-
ECAP1_AC
-
ECAP2_AC
-
ECAP3_AC
-
SDFM1_AC
-
SDFM2_AC
-
CLB1_AC
-
CLB2_AC
-
CLB3_AC
-
CLB4_AC
-
SCIA_AC
-
SCIB_AC
-
SPIA_AC
-
SPIB_AC
-
I2CA_AC
-
I2CB_AC
-
PMBUS_A_AC
-
LIN_A_AC
-
LIN_B_AC

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Table 3-345. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
-
DCANA_AC
-
MCANA_AC
-
FSIATX_AC
-
FSIARX_AC
-
HRPWM_A_AC
-
HIC_A_AC
-
AESA_AC
-
PERIPH_AC_LOCK
sysctl.h SysCtl_lockAccessControlRegs
SYNCSELECT
sysctl.h SysCtl_setSyncOutputConfig
ADCSOCOUTSELECT
sysctl.h SysCtl_enableExtADCSOCSource
sysctl.h SysCtl_disableExtADCSOCSource
SYNCSOCLOCK
sysctl.h SysCtl_lockExtADCSOCSelect
sysctl.h SysCtl_lockSyncSelect
LFUCONFIG
sysctl.h SysCtl_setLFUCPU
sysctl.h SysCtl_getLFUCPU
sysctl.h SysCtl_setLFUCLA1
sysctl.h SysCtl_getLFUCLA1
sysctl.h SysCtl_swapPieVectorAndLS01
sysctl.h SysCtl_swapPieVector
sysctl.h SysCtl_swapLS01
LFUSTATUS
sysctl.h SysCtl_isPieVectorSwap
sysctl.h SysCtl_isLS01Swap
SWCONFIG1_SYSRSN
sysctl.h SysCtl_setLFUUserRegister
sysctl.h SysCtl_getLFUUserRegister
SWCONFIG2_SYSRSN
-
SWCONFIG1_XRSN
-
SWCONFIG2_XRSN
-

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Table 3-345. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
SWCONFIG1_PORESETN
-
SWCONFIG2_PORESETN
-
LFU_LOCK
sysctl.h SysCtl_lockLFUConfigRegister
sysctl.h SysCtl_lockLFUUserRegister
sysctl.h SysCtl_unlockLFUConfigRegister
sysctl.h SysCtl_unlockLFUUserRegister
LFU_COMMIT
sysctl.h SysCtl_commitLFUConfigRegister
sysctl.h SysCtl_commitLFUUserRegister
SYS_ERR_INT_FLG
sysctl.h SysCtl_getInterruptStatus
SYS_ERR_INT_CLR
sysctl.h SysCtl_clearInterruptStatus
SYS_ERR_INT_SET
sysctl.h SysCtl_setInterruptStatus
SYS_ERR_MASK
sysctl.h SysCtl_getInterruptStatusMask
sysctl.h SysCtl_setInterruptStatusMask

3.16.20.7 WWD Registers to Driverlib Functions

Table 3-346. WWD Registers to Driverlib Functions
File Driverlib Function
SCSR
sysctl.h SysCtl_setWatchdogMode
sysctl.h SysCtl_isWatchdogInterruptActive
sysctl.h SysCtl_clearWatchdogOverride
WDCNTR
sysctl.h SysCtl_getWatchdogCounterValue
WDKEY
sysctl.h SysCtl_serviceWatchdog
sysctl.h SysCtl_enableWatchdogReset
sysctl.h SysCtl_resetWatchdog
WDCR
sysctl.h SysCtl_resetDevice
sysctl.h SysCtl_disableWatchdog
sysctl.h SysCtl_enableWatchdog
sysctl.h SysCtl_isWatchdogEnabled
sysctl.h SysCtl_setWatchdogPredivider
sysctl.h SysCtl_setWatchdogPrescaler
WDWCR
sysctl.h SysCtl_setWatchdogWindowValue

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3.16.20.8 XINT Registers to Driverlib Functions

Table 3-347. XINT Registers to Driverlib Functions
File Driverlib Function
1CR
gpio.c GPIO_setInterruptPin
gpio.h GPIO_setInterruptType
gpio.h GPIO_getInterruptType
gpio.h GPIO_enableInterrupt
gpio.h GPIO_disableInterrupt
gpio.h GPIO_getInterruptCounter
2CR
- See 1CR
3CR
- See 1CR
4CR
- See 1CR
5CR
- See 1CR
1CTR
gpio.h GPIO_getInterruptCounter
2CTR
-
3CTR
-

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Chapter 4
ROM Code and Peripheral Booting

This chapter explains the boot procedure, the available boot modes, and the various details of the ROM code
including memory maps, initializations, reset handling, and status information.

4.1 Introduction...............................................................................................................................................................548
4.2 ROM Related Collateral............................................................................................................................................548
4.3 Device Boot Sequence.............................................................................................................................................549
4.4 Device Boot Modes.................................................................................................................................................. 549
4.5 Device Boot Configurations.................................................................................................................................... 550
4.6 Device Boot Flow Diagrams.................................................................................................................................... 555
4.7 Device Reset and Exception Handling................................................................................................................... 559
4.8 Boot ROM Description............................................................................................................................................. 560
4.9 Application Notes for Using the Bootloaders........................................................................................................588
4.10 Software.................................................................................................................................................................. 592

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4.1 Introduction
The purpose of this chapter is to explain the boot read-only memory (ROM) code functionality for the CPU core,
including the boot procedure. It also discusses the functions and features of the boot ROM code, and provides
details about the ROM memory-map contents. On every reset, the device executes a boot sequence in the ROM
depending on the reset type and boot configuration. This sequence initializes the device to run the application
code. For the CPU, the boot ROM also contains peripheral bootloaders that can be used to load an application
into RAM. These bootloaders can be disabled for safety or security purposes.
See Table 4-1 for details on available boot features for the C28x CPU. Additionally, Table 4-2 shows the sizes of
the various ROMs on the device.
For details on the security APIs provided, refer to Section 4.8.10.
Various tables are provided in ROM for use in software library, refer to Section 4.8.7 for more details.
Table 4-1. Boot System Overview
Boot Feature CPU
Initial boot process Device reset
Boot mode selection GPIOs
Boot modes supported Flash boot
Secure Flash boot
RAM boot
Live firmware update (LFU) boot
Peripheral boot loaders supported Parallel IO
SCI / Wait
CAN
CAN-FD
I2C
SPI

Table 4-2. ROM Memory

ROM CPU Size
Unsecure boot ROM 64 KB
Secure ROM 48 KB
CLA data ROM 8 KB

4.2 ROM Related Collateral

Foundational Materials
• Bootloading 101 (Video)

Expert Materials
• C2000 Software Controlled Firmware Update Process Application Report

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4.3 Device Boot Sequence

Table 4-3 describes the general boot ROM procedure each time the CPU core is reset.
During boot, boot ROM code updates a boot status location in RAM that details the actions taken during this
process. Refer to Section 4.8.12 for more details.
Table 4-3. Device Boot ROM Sequence
Step CPU Action
After reset, check for HWBIST reset. If it is a HWBIST reset, immediately branch and return to the user application.
1 If it is not a HWBIST reset, then continue boot and check the FUSE error register for any errors and handle
accordingly.
2 Clock configuration and Flash power-up
3 Peripheral trimming and device configuration registers are loaded from OTP.
4 On power-on reset (POR), all RAMs are initialized.
5 Non-maskable interrupt (NMI) handling is enabled and DCSM initialization is performed.
6 Device calibration is performed; trimming the specified peripherals with set OTP values.
7 Determine if polling the GPIO pins are needed for determining the boot mode and, if so, read the boot mode GPIO
pins to determine the boot mode to run.
Based on the boot mode and options, the appropriate boot sequence is executed. Refer to Section 4.6.1 for a flow
8
chart of the boot sequences.

4.4 Device Boot Modes

This section explains the default boot modes, as well as all the available boot modes supported on this device.
The boot ROM uses the boot mode select, general purpose input/output (GPIO) pins to determine the boot mode
configuration.
4.4.1 Default Boot Modes
Table 4-4 shows the boot mode options available for selection by the default boot mode select pins. Users have
the option to program the device to customize the boot modes selectable in the boot-up table as well as the boot
mode select pin GPIOs used.
Table 4-4. Device Default Boot Modes
GPIO24 GPIO32
Boot Mode
(Default boot mode select pin 1) (Default boot mode select pin 0)
Parallel IO 0 0
SCI / Wait Boot(1) 0 1
CAN 1 0
Flash 1 1

(1) SCI boot mode is used as a wait boot mode as long as SCI continues to wait for an 'A' or 'a' during the SCI autobaud lock process.

Refer to Section 4.8.8.1 for functional details of the boot modes.

Refer to Section 4.8.9 for GPIOs used for selecting the boot modes.
Refer to Section 4.5 for details of boot configurations.

Note
All the peripheral boot modes that are supported use the first instance of the peripheral module (SCIA,
SPIA, I2CA, CANA, and so forth). Whenever these boot modes are referred to in this chapter, such as
SCI boot, it is actually referring to the first module instance, which means the SCI boot on the SCIA
port. The same applies to the other peripheral boot modes.

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4.4.2 Custom Boot Modes

Once the user programs a custom boot table in user OTP, an entry in the custom table is used for booting. Users
can customize the boot mode select pins in the end system design by programming the BOOTPIN_CONFIG
location in user OTP. This allows customers to use 0, 1, 2, or 3 boot mode select pins as needed. You can
also customize the boot definition table and indicate which location to boot from by programming the boot mode
definition table in the BOOTDEF location of user OTP. Table 4-5 shows the options for various boot modes.
Table 4-5. Custom Boot Modes
Boot Mode Number Boot Modes
0 Parallel
1 SCI / Wait
2 CAN
3 Flash
4 Wait
5 RAM
6 SPI
7 I2C
10 Secure Flash

4.5 Device Boot Configurations

This section details what boot configurations are available and how to configure them. This device supports from
one boot mode select pins up to three boot mode select pins as well as from one configured boot mode up to
eight configured boot modes.
To change and configure the device from the default settings to custom settings for your application, use the
following process:
1. Determine all the various ways you want application to be able to boot. (For example: Primary boot option of
Flash boot for your main application, secondary boot option of CAN boot for firmware updates, tertiary boot
option of SCI boot for debugging, etc)
2. Based on the number of boot modes needed, determine how many boot mode select pins (BMSPs) are
required to select between your selected boot modes. (For example: Two BMSPs are required to select
between three boot mode options)
3. Assign the required BMSPs to a physical GPIO pin. (For example, BMSP0 to GPIO10, BMSP1 to GPIO51,
and BMSP2 left as default which is disabled). Refer to Section 4.5.1 for all the details on performing these
configurations.
4. Assign the determined boot mode definitions to indexes in your custom boot table that correlate to
the decoded value of the BMSPs. For example, BOOTDEF0=Boot to Flash, BOOTDEF1=CAN Boot,
BOOTDEF2=SCI Boot; all other BOOTDEFx are left as default/nothing). Refer to Section 4.5.2 for all the
details on setting up and configuring the custom boot mode table.
Additionally, Section 4.5.3 provides some example use cases on how to configure the BMSPs and custom boot
tables.

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4.5.1 Configuring Boot Mode Pins

This section explains how the boot mode select pinsARE customized by the user, by programming
the BOOTPIN-CONFIG location (refer to Table 4-6) in the user-configurable dual-zone security module
(DCSM) OTP. The location in the DCSM OTP is Z1-OTP-BOOTPIN-CONFIG or Z2-OTP-BOOTPIN-CONFIG.
When debugging, EMU-BOOTPIN-CONFIG is the emulation equivalent of Z1-OTP-BOOTPIN-CONFIG/Z2-OTP-
BOOTPIN-CONFIG, and can be programmed to experiment with different boot modes without writing to OTP.
The device can be programmed to use zero, one, two or three boot mode select pins as needed.

Note
When using Z2-OTP-BOOTPIN-CONFIG, the configurations programmed in this location take
priority over the configurations in Z1-OTP-BOOTPIN-CONFIG. It is recommended to use Z1-OTP-
BOOTPIN-CONFIG first and then if OTP configurations need to be altered, switch to using Z2-OTP-
BOOTPIN-CONFIG.

Table 4-6. BOOTPIN-CONFIG Bit Fields

Bit Name Description
31:24 Key Write 0x5A to these 8-bits to tell the boot ROM code that the bits in this register are
valid.
23:16 Boot Mode Select Pin 2 (BMSP2) Refer to BMSP0 description.
15:8 Boot Mode Select Pin 1 (BMSP1) Refer to BMSP0 description.
7:0 Boot Mode Select Pin 0 (BMSP0) Set to the GPIO pin to be used during boot (up to 255).
0x0 = GPIO0, 0x01 = GPIO1, and so on.
Writing 0xFF disables this BMSP and this pin is no longer used to select the boot
mode.

Note
GPIO 20, 21, 224 to 253 are analog pins, but digital inputs are possible on these pins provided the
software writes to the GPIOHAMSEL register bits.
The following GPIOs cannot be used as a BMSP. If selected for a particular BMSP, the boot ROM will
automatically select the factory default GPIOs for BMSP0 and BMSP1. Factory default for BMSP2 is
0xFF, which disables the BMSP.
• GPIO 36 and GPIO 38 (Not available on any package)
• GPIO 62 to GPIO 223 (Not available on any package)
• GPIO 20 and GPIO 21 are analog pins on 80-pin package only

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Table 4-7. Standalone Boot Mode Select Pin Decoding

BOOTPIN_CONFIG
BMSP0 BMSP1 BMSP2 Realized Boot Mode
Key
!= 0x5A Don’t Care Don’t Care Don’t Care Boot as defined by the factory default BMSPs
Boot as defined in the boot table for boot mode 0
0xFF 0xFF 0xFF
(All BMSPs disabled)
Boot as defined by the value of BMSP0
Valid GPIO 0xFF 0xFF
(BMSP1 and BMSP2 disabled)
Boot as defined by the value of BMSP1
0xFF Valid GPIO 0xFF
(BMSP0 and BMSP2 disabled)
Boot as defined by the value of BMSP2
0xFF 0xFF Valid GPIO
(BMSP0 and BMSP1 disabled)
Boot as defined by the values of BMSP0 and BMSP1
Valid GPIO Valid GPIO 0xFF
(BMSP2 disabled)
Boot as defined by the values of BMSP0 and BMSP2
Valid GPIO 0xFF Valid GPIO
(BMSP1 disabled)
= 0x5A
Boot as defined by the values of BMSP1 and BMSP2
0xFF Valid GPIO Valid GPIO
(BMSP0 disabled)
Boot as defined by the values of BMSP0, BMSP1, and
Valid GPIO Valid GPIO Valid GPIO
BMSP2
BMSP0 is reset to the factory default BMSP0 GPIO
Invalid GPIO Valid GPIO Valid GPIO Boot as defined by the values of BMSP0, BMSP1, and
BMSP2
BMSP1 is reset to the factory default BMSP1 GPIO
Valid GPIO Invalid GPIO Valid GPIO Boot as defined by the values of BMSP0, BMSP1, and
BMSP2
BMSP2 is reset to the factory default state, which is
Valid GPIO Valid GPIO Invalid GPIO disabled
Boot as defined by the values of BMSP0 and BMSP1

Note
When decoding the boot mode, BMSP0 is the least-significant-bit and BMSP2 is the most-significant-
bit of the boot table index value. It is recommended when disabling BMSPs to start with disabling
BMSP2. For example, in an instance when only using BMSP2 (BMSP1 and BMSP0 are disabled),
then only the boot table indexes of 0 and 4 will be selectable. In the instance when using only BMSP0,
then the selectable boot table indexes are 0 and 1.

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4.5.2 Configuring Boot Mode Table Options

This section explains how to configure the boot definition table, BOOTDEF, for the device and the associated
boot options. The 64-bit location is located in user-configurable DCSM OTP in the Z1-OTP-BOOTDEF-LOW and
Z1-OTP-BOOTDEF-HIGH locations. When debugging, EMU-BOOTDEF-LOW and EMU-BOOTDEF-HIGH are
the emulation equivalents of Z1-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH, and can be programmed
to experiment with different boot mode options without writing to OTP. The range of customization to the boot
definition table depends on how many boot mode select pins (BMSP) are being used. For example, 0 BMSPs
equals to 1 table entry, 1 BMSP equals to 2 table entries, 2 BMSPs equals to 4 table entries, and 3 BMSPs
equals to 8 table entries. Refer to Section 4.5.3 for examples on how to setup the BOOTPIN_CONFIG and
BOOTDEF values.

Note
The locations Z2-OTP-BOOTDEF-LOW and Z2-OTP-BOOTDEF-HIGH will be used instead of Z1-
OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH locations when Z2-OTP-BOOTPIN-CONFIG is
configured. Refer to Section 4.5.1 for more details on BOOTPIN_CONFIG usage.

Table 4-8. BOOTDEF Bit Fields

BOOTDEF Name Byte Position Name Description
Set the boot mode number from Section 4.4.2.
Any unsupported boot mode will cause the
[3:0] BOOT_DEF0 Mode
device to either go to wait boot (debugger
connected) or boot to Flash (standalone).
BOOT_DEF0 7:0 Set alternate / additional boot options. This can
include changing the GPIOs for a particular boot
[7:4] BOOT_DEF0 Options peripheral or specifying a different Flash entry
point. Refer to Section 4.8.9 for valid BOOTDEF
values to set in the table.
BOOT_DEF1 15:8 BOOT_DEF1 Mode/Options
BOOT_DEF2 23:16 BOOT_DEF2 Mode/Options
BOOT_DEF3 31:24 BOOT_DEF3 Mode/Options
BOOT_DEF4 39:32 BOOT_DEF4 Mode/Options Refer to BOOT_DEF0 description.
BOOT_DEF5 47:40 BOOT_DEF5 Mode/Options
BOOT_DEF6 55:48 BOOT_DEF6 Mode/Options
BOOT_DEF7 63:56 BOOT_DEF7 Mode/Options

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4.5.3 Boot Mode Example Use Cases

This section demonstrates some use cases for configuring the boot mode select pins and boot modes.
4.5.3.1 Zero Boot Mode Select Pins
This use case demonstrates a scenario for an application that does not use any boot mode select pins and
always has the device boot to Flash.
1. Program the BOOTPIN_CONFIG location in OTP as follows:
• Set BOOTPIN_CONFIG.BMSP0 to 0xFF
• Set BOOTPIN_CONFIG.BMSP1 to 0xFF
• Set BOOTPIN_CONFIG.BMSP2 to 0xFF
• Set BOOTPIN_CONFIG.KEY to 0x5A for boot ROM to treat these register bits as valid and use the
custom boot table.
2. Program the BOOTDEF location options for the device. This essentially sets up a device-specific boot mode
table. Refer to Section 4.8.9 for valid BOOTDEF values to set in the table.
• Set BOOTDEF.BOOTDEF0 to 0x03 for booting to Flash (entry address option 0). This sets Flash boot to
boot table index 0.
• Refer to Section 4.8.2 for the available Flash entry points.
Table 4-9. Zero Boot Pin Boot Table Result
Boot Mode Table Number Boot Mode

0 Flash Boot (0x03)

4.5.3.2 One Boot Mode Select Pin

This use case demonstrates a scenario for an application using one boot mode select pin to select between
booting to Flash or using CAN boot.
1. Program the BOOTPIN_CONFIG location in OTP as follows:
• Set BOOTPIN_CONFIG.BMSP0 to a user specified GPIO, such as 0x0 for GPIO0
• Set BOOTPIN_CONFIG.BMSP1 to 0xFF
• Set BOOTPIN_CONFIG.BMSP2 to 0xFF
• Set BOOTPIN_CONFIG.KEY to 0x5A for boot ROM to treat these register bits as valid and use the
custom boot table.
2. Program the BOOTDEF location options for the device. This essentially sets up a device-specific boot mode
table. Refer to Section 4.8.9 for valid BOOTDEF values to set in the table.
• Set BOOTDEF.BOOTDEF0 to 0x02 for CAN booting. This sets CAN boot to boot table index 0.
• Set BOOTDEF.BOOTDEF1 to 0x03 for booting to Flash (entry address option 0). This sets Flash boot to
boot table index 1.
Table 4-10. One Boot Pin Boot Table Result
Boot Mode Table Number Boot Mode

0 CAN Boot (0x02)

1 Flash Boot (0x03)

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4.5.3.3 Three Boot Mode Select Pins

This use case demonstrates a scenario for an application using three boot mode select pins to select between
various boot modes in the custom boot table.
1. Program the BOOTPIN_CONFIG location in OTP as follows:
• Set BOOTPIN_CONFIG.BMSP0 to a user specified GPIO, such as 0x0 for GPIO0
• Set BOOTPIN_CONFIG.BMSP1 to a user specified GPIO, such as 0x1 for GPIO1
• Set BOOTPIN_CONFIG.BMSP2 to a user specified GPIO, such as 0x2 for GPIO2
• Set BOOTPIN_CONFIG.KEY to 0x5A for boot ROM to treat these register bits as valid and use the
custom boot table.
2. Program the BOOTDEF location options for the device. This essentially sets up a device-specific boot mode
table. Refer to Section 4.8.9 for valid BOOTDEF values to set in the table.
• Set BOOTDEF.BOOTDEF0 to 0x02 for CAN booting. This sets CAN boot to boot table index 0.
• Set BOOTDEF.BOOTDEF1 to 0x03 for booting to Flash (entry address option 0). This sets Flash boot to
boot table index 1.
• Set BOOTDEF.BOOTDEF2 to 0x24 for booting to wait boot (alternate option). This sets wait boot to boot
table index 2.
• Set BOOTDEF.BOOTDEF3 to 0x66 for SPI booting (alternate GPIO option 3). This sets SPI boot to boot
table index 3.
• Set BOOTDEF.BOOTDEF4 to 0x43 for booting to Flash (entry address option 2). This sets Flash boot to
boot table index 4.
Table 4-11. Three Boot Pins Boot Table Result
Boot Mode Table Number Boot Mode

0 CAN Boot (0x02)

1 Flash Boot (0x03)

2 Wait Boot - Alt (0x24)

3 SPI - Alt3 (0x66)

4 Flash Boot - Alt2 (0x43)

5, 6, 7 Not used in this example

4.6 Device Boot Flow Diagrams

This section details the boot flow diagrams for standalone and emulation boot flows.
4.6.1 Boot Flow
Upon reset, the CPU follows the boot flow shown in Figure 4-1. Depending on whether a JTAG debugger is
connected to the device, the CPU either continues booting following the emulation boot flow or the standalone
boot flow.

Note
BOR follows same flow as POR.

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Security (SCC)
NMI Watchdog HWBIST POR XRS Debugger Watchdog
Reset

Note: Any resets that also cause the XRS reset bit to be set (excluding
CPU Boot Start
POR) will follow the flow relating to an XRS reset.

Set CSTCRET value as application Value All other

Read
HWBIST Reset Cause resets
address Set CSTCRET
No

Value
FUSE Single Bit
is Yes
Error? Error?
Branch to Application zero

Yes
Disable wdg No

Configure Flash pump

Initialize subset of M0RAM
Reset Cause POR or XRS Set Clock Divider to /1 wakeup time and wait
boot stack space to zero
states for 15MHz Timeout

HWBIST, SCC, or
Debugger Reset Wait for
Timeout
Device Configuration
- PARTIDH/L Load
Initialize all of boot ROM stack space
XRS Reset Cause - DCX Load Set pump and bank power mode to Flash Powered up/
in M0RAM to zero
- CPUROM DCx Load active Timeout expired
- Package bonding config

Flash powered up
POR

RAM Initialization (all RAMS) Watchdog Config

(enable/disable via TI OTP)
Delay for
2KB RAMs only

Load VREGCTL.ENMASK from TI

OTP (3 NOPS, min 1uS delay
ERROR_STS Pin Config POR /
DCSM Initialization Reset Cause cJTAG Config needed)
(24/28/29) XRSn

Load PMM Trims (75us blanking)

Load INTOSC Trims (12us)

Lock DC configurations
Enable NMI All other Resets Reset Cause Load APLL Trims and APLL analog
config registers

POR

Capture any single bit flash Enable PLL and switch PLL O/P to
error addresses PBIST Enabled drive sysclk (TI OTP flag)
Verify RAM init
Field in
Is complete
GPREG2
=0x5A
Set flash pump wakeup time and wait
states for 120MHz
RAM Init complete
(delay if not complete)
Disabled
Check Z2/Z1 ROM
GPREG2 key integrity check
with BGCRC Run PBIST Memory Test
Adjust PLL clock as Passed (log staus)
configured in OTP
Any other value RAM Initialization (all RAMs)
(Wait for M0 RAM init)
Failed

Enable pull ups on unbonded IOs

Re-initialize local and global variables
lost during RAMINIT

POR/XRS: Switch sysclk

to bypass and turn off PLL

Device
Calibration (ROM Code)

Clear POR/XRS reset

causes

Disable watchdog (if

enabled via TI OTP)

Wait of RAMInit
Completion (give error
status on timeout)

Is Debugger
Standalone Boot No Yes Emulation Boot
Connected?

Figure 4-1. Device Boot Flow

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4.6.2 Emulation Boot Flow

Figure 4-2 shows the emulation boot flow when JTAG debugger is connected.

Emulation Boot Mode Start

Read EMU boot locations:

BOOTPINCONFIG
EMUBOOTDEF

Emulate Check
Unsupported Wait
Standalone (=0xA5) EMU_BOOTPIN_C
ONFIG_KEY
Key Boot
Boot

(=0x5A)

Get EMU Configurable user boot

mode options

Read Boot Mode Select Pins

from BOOTPINCONFIG and set
GPIO state

Decode Unsupported
BOOTDEF options Boot Wait Boot
for boot mode mode

Supported
Boot mode

Is Flash /
Secure Flash /
LFU Flash Yes
Boot?

No

Start the peripheral loader

Enable
process or set address to branch
Watchdog

Enable
Watchdog

Branch to Application Branch to Flash

Code Entry Point

Figure 4-2. Emulation Boot Flow

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4.6.3 Standalone Boot Flow

Figure 4-3 shows the standalone boot flow when no JTAG debugger is connected to the device.

Standalone Boot Mode Start

Read OTP loaded registers:

Z2-BOOTPINCONFIG

Check
Any
Z2 Read OTP loaded registers:
Other
OTP_BOOTPIN_C Z1-BOOTPINCONFIG
value
ONFIG_KEY

Check
Any
Z1 Read factory default two boot
Other
OTP_BOOTPIN_C mode GPIO pins
(=0x5A) Value
ONFIG_KEY

(=0x5A)
Decode boot mode from pins
Use Z2 registers: Use Z1 registers:
Z2-BOOTPINCONFIG Z1-BOOTPINCONFIG
Z2-BOOTDEF Z1-BOOTDEF

Execute one of the following:

Parallel Boot
SCI Boot
CAN Boot
Flash Boot
Read Boot Mode Select Pins
specified from
BOOTPINCONFIG

Enable
Watchdog

Decode
Unsupported
BOOTDEF table
Boot mode Flash Boot Branch to
for boot mode
Application Code
Parallel Boot
SPI Boot
SCI Boot Supported
CAN Boot Boot mode
CAN-FD Boot
Flash Boot
Secure Flash Boot (C28x AES)
LFU Flash Boot Is Flash
Yes
Boot?

No

Start the peripheral loader Enable

process or set address to branch Watchdog

Enable
Watchdog

Branch to Branch to
Application Code Flash Entry Point

Figure 4-3. CPU Standalone Boot Flow

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4.7 Device Reset and Exception Handling

4.7.1 Reset Causes and Handling
Table 4-12 explains the actions each boot ROM performs upon reset for a specific reset cause.
Table 4-12. Boot ROM Reset Causes and Actions
Reset Source Boot ROM Action
1. Configure Clock Divider
2. Flash Power Up
Power on Reset (POR) 3. Device configuration and trimming
4. RAM Initialization
5. Continue default boot flow
External Reset (XRS) 1. Configure Clock Divider
Includes: 2. Flash Power Up
• Watchdog Reset
3. Device configuration and trimming
• NMI Watchdog Reset
4. Clear RAM for boot stack
• SIMRESET XRS
5. Continue default boot flow
1. Read HWBIST return address
Hardware Built-In Self Test (HWBIST) 2. If set, branch to address
3. If not set, continue boot following "Debugger" boot flow
1. Clear RAM for boot stack
Secure Copy Code (SCC) Reset
2. Continue default boot flow
1. Clear RAM for boot stack
SIMRESET
2. Continue default boot flow
1. Clear RAM for boot stack
Debugger Reset
2. Continue default boot flow

4.7.2 Exceptions and Interrupts Handling

Table 4-13 explains the actions boot ROM performs if any exceptions occur during boot. The exception handling
philosophy in most cases, is to log the error and continue booting to reach the application.
Table 4-13. Boot ROM Exceptions and Actions
Exception Event Source Boot ROM Action Event Logged
Single-bit error in FUSEERR Ignore and continue to boot No
Multi-bit error in FUSEERR Reset the device No
Clock Fail Clear the NMI flag and continue to boot Yes
RAM Uncorrectable Error Perform RAM initialization and reset the Yes(1)
ROM Parity Error device
Flash Uncorrectable Error Reset the device Yes
HWBIST Error Clear the NMI flag and continue to boot Yes
Embedded Real-time Analysis and Diagnostic (ERAD) NMI Clear the NMI flag and continue to boot Yes
RL NMI (CLB) Clear the NMI flag and continue to boot Yes
Software NMI error (Software self test error) Reset the device No
ITRAP Exception Record memory address of where the illegal Yes
instruction was executed and let device reset
Unsupported PIE Interrupts Ignore and continue to boot No

(1) A RAM uncorrectable error or ROM parity error will clear the boot status information stored in RAM because a RAM initialization is
performed to attempt to correct the error. Since the boot status information is erased, this exception can be identified in that a NMIWD
reset occurred and all the RAMs are erased.

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4.8 Boot ROM Description

This section explains the details regarding the device boot ROMs.
4.8.1 Boot ROM Configuration Registers
The boot ROM code involves several memory addresses and registers used during execution. There are two
sets of configurations; one for emulation and one for standalone boot flow. The emulation locations located in
RAM emulate the OTP configurations and can be written to as many times as needed. The user configurable
DCSM OTP locations used in the standalone boot flow program the device OTP and hence can only be written
once. Table 4-14 details these locations. For bit field configuration details for BOOTPIN-CONFIG and BOOTDEF,
see Section 4.5.1 and Section 4.5.2.
Additionally, the boot ROM supports boot configurations from DCSM zone 1 and zone 2 registers. Zone 2
configurations supercede zone 1 configurations, so use zone 1 configurations and use zone 2 as a secondary
option.
Table 4-14. Boot ROM Registers
Boot Flow Register Name Boot ROM Name Register Address User OTP Address
- EMU-BOOTPIN-CONFIG 0x0000 0D00 -
- EMU-GPREG2 0x0000 0D02 -
Emulation - EMU-BOOTDEF-LOW 0x0000 0D04 -
- EMU-BOOTDEF-HIGH 0x0000 0D06 -
Z1-GPREG1 Z1-OTP-BOOTPIN-CONFIG 0x0005 F008 0x0007 8008

Standalone Z1-GPREG2 Z1-OTP-BOOT-GPREG2 0x0005 F00A 0x0007 800A

(Using Z1) Z1-GPREG3 Z1-OTP-BOOTDEF-LOW 0x0005 F00C 0x0007 800C
Z1-GPREG4 Z1-OTP-BOOTDEF-HIGH 0x0005 F00E 0x0007 800E
Z2-GPREG1 Z2-OTP-BOOTPIN-CONFIG 0x0005 F088 0x0007 8208

Standalone Z2-GPREG2 Z2-OTP-BOOT-GPREG2 0x0005 F08A 0x0007 820A

(Using Z2) Z2-GPREG3 Z2-OTP-BOOTDEF-LOW 0x0005 F08C 0x0007 820C
Z2-GPREG4 Z2-OTP-BOOTDEF-HIGH 0x0005 F08E 0x0007 820E

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4.8.1.1 GPREG2 Usage and MPOST Configuration

Table 4-15 explains how the bit field values from the user configurable DCSM OTP location, Z1-OTP-BOOT-
GPREG2 or Z2-OTP-BOOT-GPREG2, are decoded by boot ROM.

Note
Z1-GPREG2 shares ECC with Z1-GPREG1, so users can program both these locations at the same
time in User OTP.

Table 4-15. DCSM Z1/Z2 GPREG2 Bit Fields

Bit Name Description Boot ROM Action
31:24 Key Write 0x5A to indicate to the boot If user sets to 0x5A, boot ROM uses the values in this register. If set
ROM code that the bits in this register to any other value, boot ROM ignores values in this register.
are valid.
23:8 Reserved Reserved No Action
7:6 MPOST(1) 0x0 = Run MPOST with PLL disabled When configured to a valid value, MPOST POR memory self-test is
(10-MHz internal oscillator) run on all device memories
0x1 = Run MPOST with PLL enabled
for 95 MHz
0x2 = Run MPOST with PLL enabled
for 47.5 MHz
0x3 = Disable MPOST
5:4 ERROR_ 0x0 – GPIO24, MUX Option 13 This indicates which GPIO pin is supposed to be used as
STS_PIN ERROR_PIN and boot ROM configures the mux for the pin. The
0x1 – GPIO28, MUX Option 13
configuration ERROR_STS pin mux configuration is locked by the boot ROM, but
0x2 – GPIO29, MUX Option 13 not committed.
0x3 – ERROR_STS function disabled
(default)
3:0 CJTAGNODEID CJTAGNODEID[3:0] Boot ROM takes this values and programs the lower 4 bits of the
CJTAGNODEID register.

(1) If MPOST is configured to run with PLL enabled and the PLL fails to lock, then the MPOST run is skipped. This does not apply, if
MPOST is configured to use INTOSC2 with PLL disabled.

4.8.2 Entry Points

This sections gives details about the entry point addresses for various boot modes. These entry points direct the
boot ROM what address to branch to at the end of booting as per the selected boot mode.
Table 4-16 gives details about the entry point addresses for Flash boot mode.
Table 4-17 gives details about the entry point addresses for RAM boot mode.
Table 4-16. Flash Entry Point Addresses
Packages
Option BOOTDEFx Value Flash Sector Address
Supported
0 0x03 CPU Bank 0 Sector 0 0x0008 0000 All
1 0x23 CPU Bank 0 Sector 8 0x0008 8000 All
2 0x43 CPU Bank 0 End of Sector 15 0x0008 FFF0 All
3 0x63 CPU Bank 1 Sector 0 0x0009 0000 All
4 0x83 CPU Bank 1 End of Sector 7 0x0009 7FF0 All
5 0xA3 CPU Bank 1 End of Sector 15 0x0009 FFF0 All
6 0xC3 CPU Bank 2 Sector 0 0x000A 0000 All
7 0xE3 CPU Bank 2 End of Sector 15 0x000A FFF0 All

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Table 4-17. RAM Entry Point Address

Option BOOTDEFx Value RAM Entry Point Package Supported
0 0x05 0x0000 0000 All

4.8.3 Wait Points

The wait mode puts the CPU in a loop in the boot ROM code and does not branch to the user application
code. The device can enter wait boot mode either through manually being set or because of some issue during
boot up. Using wait boot mode is recommended when using a debugger to avoid any JTAG issues. There is an
ESTOP provided for debugging during Wait boot.
Table 4-18. Wait Boot Options
Option BOOTDEFx Value Watchdog Status Package Supported

0 (default) 0x04 Enabled All

1 0x24 Disabled All

During boot ROM execution, there are situations where the CPU can enter a wait loop in the code. This state
can occur for a variety of reasons. Table 4-19 details the address ranges that the CPU PC register value falls
between if the CPU has entered one of these instances.
Following are the actions for entering wait boot mode:
• Wait boot is set by the user as the boot mode.
• Boot mode is unrecognizable and a debugger is connected to the device.
• The emulation BOOTPIN_CONFIG key isn't equal to 0xA5 or 0x5A.
• An error occurs during emulation boot and the boot mode pins are decoded with a value not recognized as a
valid boot mode.
Table 4-19. Wait Point Addresses
Address Range Description
0x3FB8B9 – 0x3FB8C0 In Wait Boot Mode
0x3FC7D0 – 0x3FC7D8 In SCI Boot waiting on autobaud lock
0x3FEDFE – 0x3FEEC8 In NMI Handler
0x3FEEC9 – 0x3FEEF9 In ITRAP ISR
0x3FCB96 - 0x3FCB9A In Parallel boot waiting for control signal

4.8.4 Secure Flash Boot

Secure Flash boot mode is similar to Flash boot mode in that the boot flow branches to the configured
memory address in Flash except only after the Flash memory contents have been authenticated. The Flash
authentication uses a Cipher-based Message Authentication Protocol (CMAC) to authenticate 16 KB of Flash
starting from the configured Flash entry point address. The CMAC calculation requires a user-defined 128-bit
key programmed in the CPU User OTP Zone 1 Header OTP CMACKEY bit field. Additionally, the user must
calculate the golden CMAC tag based on the 16 KB Flash memory range and store the CMAC tag along with
the user code at a hardcoded address in Flash. During secure Flash boot, the calculated CMAC tag is compared
to the user golden CMAC tag in Flash to determine the pass/fail status of the CMAC authentication. When
authentication passes, boot flow continues and branches to Flash to begin executing the application. When
authentication fails, the device is reset.
For the available secure Flash boot entry address options, refer to Section 4.8.2.
For generating the secure Flash golden CMAC tag for CPU, refer to the TMS320C28x Assembly Language
Tools User’s Guide within section “Using Secure Flash Boot on TMS320F2838x Devices” for instructions.

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Note
Both the CMAC golden signature and CMAC key are stored in the most-significant double format, but
each 32-bit section is in little-endian format.
Key: 2B7E1516 28AED2A6 ABF71588 09CF4F3C
(MSB is 2B and LSB is 3C)
CMACKEY0 = 0x2B7E1516
CMACKEY1 = 0x28AED2A6
CMACKEY2 = 0xABF71588
CMACKEY3 = 0x09CF4F3C

Note
User must make sure that the Flash sector that encompasses the configured Flash entry point and the
first 16 KB of Flash is assigned to Zone 1 for the core setup for secure Flash boot.
Recommended to use device JTAGLOCK when using secure Flash boot.

APIs for CMAC calculation and authentication is provided as part of ROM. Details are available in Section 4.8.10
Table 4-20. Secure Flash Boot Details
Details Location Address
CMAC Signature Address Flash Entry Point Address + 0x2
CMAC Key Address (128-bit key) DCSM Z1 OTP CMACKEY0/1/2/3
Flash Entry Point (Bank 0, Sector 0) 0x0008 0000
Flash Entry Point (Bank 0, Sector 8) 0x0008 8000
Flash Entry Point (Bank 0, End of Sector 15) 0x0008 FFF0
Flash Entry Point (Bank 1, Sector 0) 0x0009 0000
Flash Entry Point (Bank 1, End of Sector 7) 0x0009 7FF0
Flash Entry Point (Bank 1, End of Sector 15) 0x0009 FFF0
Flash Entry Point (Bank 2, Sector 0) 0x000A 0000
Address Range for CMAC Calculation Start: Flash Entry Point Address
End: Flash Entry Point Address + 16 KB

Table 4-21. Secure Flash Tag and Key Details

Name Address Details
CMAC Golden Tag CPU: Located in Flash, offset from the entry point address, by 2 words
(128-bit) Flash Entry Point Address + 0x2 (CPU).
When CMAC calculations are performed, the golden tag location in
memory is considered all 0xFs. Refer to Example 4-1 for an example
regarding linker configuration on CPU.
Lower memory contains the tag's MSW and higher memory contains
the LSW.
Example (on CPU):
Tag = 0x00112233 44556677 8899AABB CCDDEEFF
Address 0x0 = 0x00112233
Address 0x2 = 0x44556677
Address 0x4 = 0x8899AABB
Address 0x6 = 0xCCDDEEFF

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Table 4-21. Secure Flash Tag and Key Details (continued)

Name Address Details
CMAC 128-Bit Key 0x0007 8018 Located in CPU Zone 1 User Header OTP
(CMACKEY0, CMACKEY1, CMACKEY2, CMACKEY3)
CMACKEY0 contains the key's MSW and CMACKEY3 contains the
LSW.
Example:
Key = 0x00112233 44556677 8899AABB CCDDEEFF
CMACKEY0 = 0x00112233
CMACKEY1 = 0x44556677
CMACKEY2 = 0x8899AABB
CMACKEY3 = 0xCCDDEEFF

Table 4-22. Secure Flash Authentication Failure Actions

CPU Action on Failed Authentication
1. Emulation only - Halt debugger (ESTOP)
C28x CPU
2. Wait in endless loop (for device reset due to WD reset)

Table 4-23. Secure Flash on all CPUs Recommended Flow

Step Action
1 Secure Flash boot CPU
Any Flash beyond the first 16 KB from the entry point that is planned for use can be authenticated by
2 the user using a different CMAC golden tag embedded at an address somewhere within the already
authenticated 16 KB of Flash.

Example 4-1. Secure Flash CPU1 Linker File Example

MEMORY
{
/* Code Start branch to _c_int00 */
BEGIN : origin = 0x80000, length = 0x0002
/* User calculated golden CMAC tag for Flash Sector 0 */
GOLDEN_CMAC_TAG : origin = 0x80002, length = 0x0008
/* Flash Sector 0 containing application code */
FLASH_SECTOR_0 : origin = 0x8000A, length = 0x1FF6
.
.
.
}

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4.8.5 Live Firmware Update (LFU) Flash Boot

Live Firmware Update (LFU) boot mode is required to handle the Live Firmware Update feature. In this boot
mode, the boot loader reads the version number from images present in multiple banks and identifies the latest
image. The boot ROM then hands off the execution to the application with the latest version. To support LFU
boot mode each Flash bank containing an application image needs a few fields as shown in Table 4-24.
Table 4-24. LFU Application Image Format
Image Address Offset Content

0x0 Application entry point (32-bit)

0xA Key (32-bit)

Valid Key = 0x5A5A5A5A

0xC Firmware version number (32-bit)

Application entry point: This is the code execution start address of the image stored in Flash.
Key: This 32-bit field determines if this image is valid. The image in a bank is considered valid only if the location
contains the value 0x5A5A5A5A. In case all banks have invalid keys, an error is flagged in boot_status variable
and program jumps to a while loop in standalone boot mode (ESTOP in emulation boot mode).
Firmware version number: This 32-bit field is the version number of the firmware or application. 0xFFFF FFFF
is considered as the initial value and this needs to be decremented after every update. The image with lower
version number is the latest application. If all valid images have same version number, then bank-0 (or the
lowest numbered bank) is chosen.
For example, if bank-0 has invalid Key and bank-1 and bank-2 have valid keys, then the one having lowest
Firmware version number is selected for boot. If both are the same, then bank-1 is selected.
Table 4-25 shows the entry points for LFU boot mode.
Table 4-25. LFU Entry Point Addresses
Option BOOTDEFx Value Bank 0 Bank 1 Bank 2
0 0x0B 0x0008 0000 0x0009 0000 0x000A 0000
1 0x2B 0x0008 8000 0x0009 8000 0x000A 8000
2 0x4B 0x0008 FFF0 0x0009 FFF0 0x000A FFF0
3 0x6B 0x0008 8000 0x0009 0000 0x000A 0000
4 0x8B 0x0008 EFF0 0x0009 7FF0 0x0008 7FF0

For example, if Option 0 with Bank 0 has the application image:

[0008 0000-0008 0001] = Application entry point
[0008 000A-0008 000B] = Key
[0008 000C-0008 000D] = Firmware version number

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4.8.6 Memory Maps

4.8.6.1 Boot ROM Memory Maps
Table 4-26 details the ROM memory maps.
Table 4-26. Boot ROM Memory Map
Memory Origin Address Length (Words)
ROM Signature 0x003F 0000 0x0002
Golden CRC 0x003F 0002 0x0002
Full ROM Checksum 0x003F 0040 0x0042
Version 0x003F 0082 0x0004
IQmath Tables 0x003F 812C 0x1674
FPU32 Fast Tables 0x003F 97A0 0x081A
FPU32 Twiddle Tables 0x003F 9FBA 0x0DF8
Boot Code 0x003F ADB2 0x4000
Interrupt Handlers 0x003F EDB2 0x01AE
CPU Fast Data ROM (InstaSPIN) 0x003F EF60 0x0100
RTS Lib 0x003F F060 0x0098
Full ROM Checksum 0x003F 8380 0x0042
CRC Table 0x003F F0F8 0x0008
Vector Table 0x003F FFBE 0x0042

Table 4-27 details the secure ROM memory maps.

Table 4-27. Secure ROM Memory Map
Memory Origin Address Length
Zone 1 Secure-Copy / CRC Code 0x3F2000 0x0800
Zone 1 Secure Flash Boot 0x3F2800 0x0800
Zone 2 Secure-Copy / CRC Code 0x3F3000 0x0800
Z1 Secure EXE ROM - InstaSPIN 0x3F3800 0x47F0
RESERVED 0x3EFFF0 0x0010

4.8.6.2 CLA Data ROM Memory Maps

Note
In Table 4-28, Load refers to the memory addresses where the CPU can view the data. Run refers to
the CLA memory addresses that the CLA uses to access the data.

Table 4-28. CLA Data ROM Memory Map

Memory Origin Address Length (Words)
FFT Tables (Load) 0x0100 1070 0x0800
Data (Load) 0x0100 1870 0x078A
Version (Load) 0x0100 1FFA 0x0006
FFT Tables (Run) 0x0000 F070 0x0800
Data (Run) 0x0000 F870 0x078A
Version (Run) 0x0000 FFFA 0x0006

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4.8.6.3 Reserved RAM Memory Maps

Table 4-29 details memory usage in RAM that is reserved for boot ROM to use. These memory sections should
be reserved in the user application.
Table 4-29. Reserved RAM Memory Map
Memory Description Origin Address Length (Words)
Boot Status, Boot Mode, MPOST
RAM 0x0000 0002 0x0126
Status, Boot Stack

4.8.7 ROM Tables

Table 4-30 details the boot ROM symbol libraries that can be integrated into an application to use the available
ROM functions and tables.
Table 4-30. ROM Symbol Tables
ROM Symbols Library Name Location
ROM Bootloaders and Functions F28003xCPU_BootROM_Symbols
FPU32 Tables F28003xCPU_BootROM_Symbols Under /libraries/boot_rom in C2000Ware
IQmath F28003xCPU_IQMathROM_Symbols

4.8.8 Boot Modes and Loaders

The available boot modes and bootloaders supported on this device are detailed in this section.
4.8.8.1 Boot Modes
This section details the available boot modes that do not involve a peripheral boot loader. Table 4-31 details the
available boot modes that do not involve a peripheral boot loader.
Table 4-31. Boot Mode Availability
Boot Mode CPU Support
Flash Boot C28x CPU
RAM Boot C28x CPU
Wait Boot C28x CPU
Secure Flash Boot C28x CPU
LFU Flash Boot C28x CPU

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4.8.8.1.1 Flash Boot

Flash boot mode branches to the configured memory address in Flash. Refer to Section 4.8.2 for all the
available Flash address options.
4.8.8.1.2 RAM Boot
RAM boot mode branches to the configured memory address in RAM. Refer to Section 4.8.2 for all the available
RAM address options.
4.8.8.1.3 Wait Boot
Wait boot mode branches to the memory address as mentioned in Section 4.8.3.
Table 4-32. Wait Boot Options
Option BOOTDEFx Value Watchdog Status Package Supported
0 (default) 0x04 Enabled All
1 0x24 Disabled All

4.8.8.2 Bootloaders
This section details the available boot modes that use a peripheral boot loader. For more specific details on the
supported data stream structure used by the following bootloaders, refer to Section 4.9.1.
4.8.8.2.1 SCI Boot Mode
The SCI boot mode asynchronously transfers code from SCI-A to internal memory. This boot mode only
supports an incoming 8-bit data stream and follows the data flow as shown in Figure 4-4.

Figure 4-4. Overview of SCI Bootloader Operation

The device communicates with the external host by communication through the SCI-A peripheral. The autobaud
feature of the SCI port is used to lock baud rates with the host. For this reason the SCI loader is very flexible and
you can use a number of different baud rates to communicate with the device.
After each data transfer, the bootloader echoes back the 8-bit character received to the host. This allows the
host to check that each character was received by the bootloader.

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At higher baud rates, the slew rate of the incoming data bits can be affected by transceiver and connector
performance. While normal serial communications work well, this slew rate can limit reliable auto-baud detection
at higher baud rates (typically beyond 100 kbaud) and cause the auto-baud lock feature to fail. To avoid this, the
following is recommended:
1. Achieve a baud-lock between the host and SCI bootloader using a lower baud rate.
2. Load the incoming application or custom loader at this lower baud rate.
3. The host can then handshake with the loaded application to set the SCI baud rate register to the desired
high baud rate.

Figure 4-5. Overview of SCI Boot Function

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4.8.8.2.2 SPI Boot Mode

The SPI loader expects an SPI-compatible 16-bit or 24-bit addressable serial EEPROM or serial Flash device
to be present on the SPI-A pins as shown in Figure 4-6. The SPI bootloader supports an 8-bit data stream and
does not support a 16-bit data stream.

Figure 4-6. Overview of SPI Bootloader Operation

The SPI boot ROM loader initializes the SPI module to interface to a serial SPI EEPROM or Flash. Devices
of this type include, but are not limited to, the Xicor X25320 (4Kx8) and Xicor X25256 (32Kx8) SPI serial SPI
EEPROMs and the Atmel AT25F1024A serial Flash.
The SPI boot ROM loader initializes the SPI with the following settings: FIFO enabled, 8-bit character, internal
SPICLK master mode and talk mode, clock phase = 1, polarity = 0, using the slowest baud rate.
If the download is to be performed from an SPI port on another device, then that device must be set up to
operate in the slave mode and mimic a serial SPI EEPROM. Immediately after entering the SPI_Boot function,
the pin functions for the SPI pins are set to primary and the SPI is initialized. The initialization is done at the
slowest speed possible. Once the SPI is initialized and the key value read, you can specify a change in baud
rate or low-speed peripheral clock. Table 4-33 shows the 8-bit data stream used by the SPI.
Table 4-33. SPI 8-Bit Data Stream
Byte Contents
1 LSB: AA (KeyValue for memory width = 8-bits)
2 MSB: 08h (KeyValue for memory width = 8-bits)
3 LSB: LOSPCP
4 MSB: SPIBRR
5 LSB: reserved for future use
6 MSB: reserved for future use
... Reserved
17 LSB: reserved for future use
18 MSB: reserved for future use
19 LSB: Upper half (MSW) of Entry point PC[23:16]
20 MSB: Upper half (MSW) of Entry point PC[31:24] (Note: Always 0x00)
21 LSB: Lower half (LSW) of Entry point PC[7:0]
22 MSB: Lower half (LSW) of Entry point PC[15:8]
... ....
... Data for this section.
...
... Blocks of data in the format size/destination address/data as shown in the generic data stream description
... ...
... Data for this section.
n LSB: 00h

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Table 4-33. SPI 8-Bit Data Stream (continued)

Byte Contents
n+1 MSB: 00h - indicates the end of the source

The data transfer is done in "burst" mode from the serial SPI EEPROM. The transfer is carried out entirely in
byte mode (SPI at 8 bits/character). A step-by-step description of the sequence is:
1. The SPI-A port is initialized.
2. The GPIO pin, as defined by SPI option configured from Table 4-43, is used as a chip-select for the serial
SPI EEPROM or Flash.
3. The SPI-A outputs a read command for the serial SPI EEPROM or Flash.
4. The SPI-A sends the serial SPI EEPROM an address 0x0000; that is, the host requires that the EEPROM or
Flash must have the downloadable packet starting at address 0x0000 in the EEPROM or Flash. The loader
is compatible with both 16-bit addresses and 24-bit addresses.
5. The next word fetched must match the key value for an 8-bit data stream (0x08AA). The least-significant
byte (LSB) of this word is the byte read first and the most-significant byte (MSB) is the next byte fetched.
This is true of all word transfers on the SPI. If the key value does not match, then the load is aborted and the
bootloader jumps to Flash.
6. The next two bytes fetched can be used to change the value of the low speed peripheral clock register
(LOSPCP) and the SPI baud rate register (SPIBRR). The first byte read is the LOSPCP value and the
second byte read is the SPIBRR value. The next seven words are reserved for future enhancements. The
SPI bootloader reads these seven words and discards them.
7. The next two words makeup the 32-bit entry point address where execution continues after the boot load
process is complete. This is typically the entry point for the program being downloaded through the SPI port.
8. Multiple blocks of code and data are then copied into memory from the external serial SPI EEPROM through
the SPI port. The blocks of code are organized in the standard data stream structure presented earlier. This
is done until a block size of 0x0000 is encountered. At that point in time the entry point address is returned to
the calling routine that then exits the bootloader and resumes execution at the address specified.

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Figure 4-7. Data Transfer from EEPROM Flow

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4.8.8.2.3 I2C Boot Mode

The I2C bootloader expects an 8-bit wide I2C-compatible EEPROM device to be present at address 0x50 on
the I2C-A bus as shown in Figure 4-8. The EEPROM must adhere to conventional I2C EEPROM protocol, as
described in this section, with a 16-bit base address architecture.

Figure 4-8. EEPROM Device at Address 0x50

If the download is to be performed from a device other than an EEPROM, then that device must be set up to
operate in the slave mode and mimic the I2C EEPROM. Immediately after entering the I2C boot function, the
GPIO pins are configured for I2C-A operation and the I2C is initialized. The following requirements must be met
when booting from the I2C module:
• The input frequency to the device must be in the appropriate range.
• The EEPROM must be at slave address 0x50.

The bit-period prescalers (I2CCLKH and I2CCLKL) are configured by the bootloader to run the I2C at a
50 percent duty cycle at 100-kHz bit rate (standard I2C mode) when the system clock is 10 MHz. These registers
can be modified after receiving the first few bytes from the EEPROM. This allows the communication to be
increased up to a 400-kHz bit rate (fast I2C mode) during the remaining data reads.
Arbitration, bus busy, and slave signals are not checked. Therefore, no other master is allowed to control the
bus during this initialization phase. If the application requires another master during I2C boot mode, that master
must be configured to hold off sending any I2C messages until the application software signals that it is past the
bootloader portion of initialization.
The non-acknowledgment bit is checked only during the first message sent to initialize the EEPROM base
address. This is to make sure that an EEPROM is present at address 0x50 before continuing. If an EEPROM is
not present, the non-acknowledgment bit is not checked during the address phase of the data read messages
(I2C_Get Word). If a non-acknowledgment is received during the data read messages, the I2C bus hangs. Table
4-34 shows the 8-bit data stream used by the I2C.
The I2C EEPROM protocol required by the I2C bootloader is shown in Figure 4-10 and Figure 4-11. The first
communication, which sets the EEPROM address pointer to 0x0000 and reads the KeyValue (0x08AA) from it, is
shown in Figure 4-10. All subsequent reads are shown in Figure 4-11 and are read two bytes at a time.

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Figure 4-9. Overview of I2C Boot Function

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Table 4-34. I2C 8-Bit Data Stream

Byte Contents
1 LSB: AA (KeyValue for memory width = 8 bits)
2 MSB: 08h (KeyValue for memory width = 8 bits)
3 LSB: I2CPSC[7:0]
4 Reserved
5 LSB: I2CCLKH[7:0]
6 MSB: I2CCLKH[15:8]
7 LSB: I2CCLKL[7:0]
8 MSB: I2CCLKL[15:8]
... ...
... Data for this section.
...
17 LSB: Reserved for future use
18 MSB: Reserved for future use
19 LSB: Upper half of entry point PC
20 MSB: Upper half of entry point PC[22:16] (Note: Always 0x00)
21 LSB: Lower half of entry point PC[15:8]
22 MSB: Lower half of entry point PC[7:0]
... ...
... Data for this section.
...
Blocks of data in the format size/destination address/data as shown in the generic data stream description.
... ...
... Data for this section.
n LSB: 00h
n+1 MSB: 00h - indicates the end of the source
RESTART

NO ACK
START

WRITE

READ

STOP
MSB

MSB

ACK
ACK

ACK

ACK
ACK
LSB

LSB

SDA LINE

Device Address Address Device DATA BYTE 1 DATA BYTE 2

Address Pointer, MSB Pointer, LSB Address

Figure 4-10. Random Read

NO ACK
START

READ

STOP
ACK

ACK

SDA LINE

Device DATA BYTE n DATA BYTE n+1

Address

Figure 4-11. Sequential Read

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4.8.8.2.4 Parallel Boot Mode

The parallel general purpose I/O (GPIO) boot mode asynchronously transfers code from host to C28x's internal
memory. Each value is eight bits long and follows the same data flow as outlined in Figure 4-12.

Figure 4-12. Overview of Parallel GPIO Bootloader Operation

The control subsystem communicates with the external host device by polling/driving the Host Control and 28x
control lines. The handshake protocol shown in Figure 4-13 must be used to successfully transfer each word via
GPIO [D0:D7]. This protocol is very robust and allows for a slower or faster host to communicate with the master
subsystem.
Two consecutive 8-bit words are read to form a single 16-bit word. The least significant byte (LSB) is read first
followed by the most significant byte (MSB). In this case, data is read from GPIO[D0:D7].
The 8-bit data stream is shown in Table 4-35.
Table 4-35. Parallel GPIO Boot 8-Bit Data Stream
Bytes GPIO[D0:D7] GPIO[D0:D7] Description
(Byte 1 of 2) (Byte 2 of 2)
1 2 AA 08 0x08AA (KeyValue for memory width = 16 bits)
3 4 00 00 8 reserved words (words 2 - 9)
... ... ... ... ...
17 18 00 00 Last reserved word
19 20 BB 00 Entry point PC[22:16]
21 22 DD CC Entry point PC[15:0] (PC = 0x00BBCCDD)
23 24 NN MM Block size of the first block of data to load = 0xMMNN words
25 26 BB AA Destination address of first block Addr[31:16]
27 28 DD CC Destination address of first block Addr[15:0] (Addr = 0xAABBCCDD)
29 30 BB AA First word of the first block in the source being loaded = 0xAABB
... ...
... Data for this section.
...
. BB AA Last word of the first block of the source being loaded = 0xAABB
. NN MM Block size of the 2nd block to load = 0xMMNN words
. BB AA Destination address of second block Addr[31:16]
. DD CC Destination address of second block Addr[15:0]
. BB AA First word of the second block in the source being loaded
. …
n n+1 BB AA Last word of the last block of the source being loaded
(More sections if required)
n+2 n+3 00 00 Block size of 0000h - indicates end of the source program

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The device first signals the host that the device is ready to begin data transfer by pulling the C28x control pin
low. The host load then initiates the data transfer by pulling the DSP control pin low. The complete protocol is
shown in Figure 4-13.

Figure 4-13. Parallel GPIO Bootloader Handshake Protocol

1. The device indicates the device is ready to start receiving data by pulling the C28x control pin low.
2. The bootloader waits until the host puts data on GPIO [D0:D7]. The host signals to the device that data is
ready by pulling the host control pin low.
3. The device reads the data and signals the host that the read is complete by pulling C28x control high.
4. The bootloader waits until the host acknowledges the device by pulling host control high.
5. The device again indicates the device is ready for more data by pulling the C28x control pin low.
This process is repeated for each data value to be sent.
Figure 4-14 shows an overview of the Parallel GPIO bootloader flow.

Figure 4-14. Overview of Parallel GPIO Boot Function

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Figure 4-15 shows the transfer flow from the host side. The operating speed of the CPU and host are not critical
in this mode as the host waits for the device and the device waits for the host. In this manner, the protocol works
with both a host running faster and a host running slower than the device.

Figure 4-15. Parallel GPIO Mode - Host Transfer Flow

Figure 4-16 shows the flow used to read a single word of data from the parallel port.
• 8-bit data stream
The 8-bit routine, shown in Figure 4-16, discards the upper eight bits of the first read from the port and treats
the lower eight bits masked with D7 in bit position 7 and D6 in bit position six as the least-significant byte
(LSB) of the word to be fetched. The routine then performs a second read to fetch the most-significant byte
(MSB). The routine then performs a second read to fetch the MSB and then combines the MSB and LSB into
a single 16-bit value to be passed back to the calling routine.

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Figure 4-16. 8-Bit Parallel GetWord Function

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4.8.8.2.5 CAN Boot Mode

The CAN bootloader asynchronously transfers code from CAN-A to internal memory as shown in Figure 4-17.
The host can be any CAN node. The communication is first done with 11-bit standard identifiers (with a MSGID
of 0x1) using two bytes per data frame. The host can download a kernel to reconfigure the CAN if higher data
throughput is desired.

Figure 4-17. Overview of CAN-A Bootloader Operation

The bit timing registers are programmed in such a way that a 100-kbps bit rate is achieved with a 20-MHz
external oscillator, as shown in Table 4-36.
Table 4-36. Bit-Rate Value for Internal Oscillators
OSCCLK SYSCLK Bit Rate
20 MHz 10 MHz 100 kbps

The SYSCLKOUT values shown are the reset values with the default PLL setting. The BRP and bit-time values
are hard-coded to 10 and 20, respectively.

Note
The CAN boot loader uses XTAL as the bit clock source and INTOSC2 as the system clock source.

Mailbox 1 is programmed with a standard MSGID of 0x1 for boot-loader communication. The CAN host can
transmit only two bytes at a time, LSB first and MSB next. For example, to transmit the word 0x08AA to
the device, transmit AA first, followed by 08. The program flow of the CAN bootloader is identical to the SCI
bootloader. The data sequence for the CAN bootloader is shown in Table 4-37.

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Table 4-37. CAN 8-Bit Data Stream

Bytes Byte 1 of 2 Byte 2 of 2 Description
1 2 AA 08 0x08AA (KeyValue for memory width = 16 bits)
3 4 00 00 reserved
5 6 00 00 reserved
7 8 00 00 reserved
9 10 00 00 reserved
11 12 00 00 reserved
13 14 00 00 reserved
15 16 00 00 reserved
17 18 00 00 reserved
19 20 BB AA Entry point PC[22:16]
21 22 DD CC Entry point PC[15:0] (PC = 0xAABBCCDD)
23 24 NN MM Block size of the first block of data to load = 0xMMNN words
25 26 BB AA Destination address of first block Addr[31:16]
27 28 DD CC Destination address of the first block Addr[15:0] (Addr =
0xAABBCCDD)
29 30 BB AA First word of the first block in the source being loaded = 0xAABB
... ....
... Data for this section.
...
. BB AA Last word of the first block of the source being loaded = 0xAABB
. NN MM Block size of the second block to load = 0xMMNN words
. BB AA Destination address of the second block Addr[31:16]
. DD CC Destination address of the second block Addr[15:0]
. BB AA First word of the second block in the source being loaded
. …
n n+1 BB AA Last word of the last block of the source being loaded
(More sections if required)
n+2 n+3 00 00 Block size of 0000h - indicates end of the source program

4.8.8.2.6 CAN-FD Boot Mode

The CAN-FD bootloader asynchronously transfers code from CAN-FD to internal memory and follows the same
bootloader execution flow as Section 4.8.8.2.5. The host can be any CAN-FD node. The communication is first
done with 11-bit standard identifiers (with a MSGID of 0x1) using two bytes per data frame. It uses a fixed
64-byte payload size and default bit rate of 1-Mbps for nominal phase and 2-Mbps for data phase. Bit data timing
can be optionally reconfigured after receiving first data segment. It supports same debug boot mode and GOIP
option-0 as CAN bootloader.
Mailbox 1 is programmed with a standard MSGID of 0x1 for boot-loader communication. The CAN-FD host can
transmit only two bytes at a time, LSB first and MSB next. For example, to transmit the word 0x08AA to the
device, transmit AA first, followed by 08. The program flow of the CAN-FD bootloader is identical to the CAN
bootloader. The data sequence for the CAN-FD bootloader is shown in Table 4-38.

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Table 4-38. CAN-FD 8-Bit Data Stream

Bytes Byte 1 of 2 Byte 2 of 2 Description
1 2 AA 08 0x08AA (KeyValue for memory width = 16 bits)
3 4 XX XX 0: Ignored
(for example, BB) (for example, AA) Nonzero: Custom nominal bit register timing [31:16]
5 6 XX XX 0: Ignored
(for example, DD) (for example, CC) Nonzero: Custom nominal bit register timing [15:0]
(NBTR = 0xAABBCCDD)
7 8 XX XX 0: Ignored
(for example, BB) (for example, AA) Nonzero: Custom nominal bit register timing [31:16]
9 10 XX XX 0: Ignored
(for example, DD) (for example, CC) Nonzero: Custom nominal bit register timing [15:0]
(DBTR = 0xAABBCCDD)
11 12 00 00 reserved
13 14 00 00 reserved
15 16 00 00 reserved
17 18 00 00 reserved
19 20 BB AA Entry point PC[22:16]
21 22 DD CC Entry point PC[15:0] (PC = 0xAABBCCDD)
23 24 NN MM Block size of the first block of data to load = 0xMMNN words
25 26 BB AA Destination address of first block Addr[31:16]
27 28 DD CC Destination address of the first block Addr[15:0] (Addr =
0xAABBCCDD)
29 30 BB AA First word of the first block in the source being loaded = 0xAABB
... ....
... Data for this section.
...
. BB AA Last word of the first block of the source being loaded = 0xAABB
. NN MM Block size of the second block to load = 0xMMNN words
. BB AA Destination address of the second block Addr[31:16]
. DD CC Destination address of the second block Addr[15:0]
. BB AA First word of the second block in the source being loaded
. …
n n+1 BB AA Last word of the last block of the source being loaded
(More sections if required)
n+2 n+3 00 00 Block size of 0000h - indicates end of the source program

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4.8.9 GPIO Assignments

This section details the GPIOs and boot option values used for boot mode set in the BOOT_DEF memory
location located at Z1-OTP-BOOTDEF-LOW/ Z2-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH/ Z2-OTP-
BOOTDEF-HIGH. Refer to Section 4.5.2 on how to configure BOOT_DEF. When selecting a boot mode option,
make sure to verify that the necessary pins are available in the pin mux options for the specific device package
being used.
Table 4-39. SCI Boot Options
Option BOOTDEF Value SCITXDA GPIO SCIRXDA GPIO
0 (default) 0x01 GPIO29 GPIO28
1 0x21 GPIO16 GPIO17
2 0x41 GPIO8 GPIO9
3 0x61 GPIO2 GPIO3
4 0x81 GPIO16 GPIO3

Table 4-40. CAN Boot Options

Option BOOTDEF Value CANTXA GPIO CANRXA GPIO
0 (default) 0x02 GPIO4 GPIO5
1 0x22 GPIO32 GPIO33
2 0x42 GPIO2 GPIO3
3 0x62 GPIO13 GPIO12

Table 4-41. CAN-FD Boot Options

Option BOOTDEFx Value CANTXA GPIO CANRXA GPIO
0 0x08 GPIO4 GPIO5
1 0x28 GPIO1 GPIO0
2 0x48 GPIO13 GPIO12

Table 4-42. I2C Boot Options

Option BOOTDEF Value SDAA GPIO SCLA GPIO
0 0x07 GPIO32 GPIO33
1 0x27 GPIO0 GPIO1
2 0x47 GPIO10 GPIO8

Table 4-43. SPI Boot Options

Option BOOTDEF Value SPISIMOA SPISOMIA SPICLKA SPISTEA
0 0x06 GPIO2 GPIO1 GPIO3 GPIO5
1 0x26 GPIO16 GPIO1 GPIO3 GPIO0
2 0x46 GPIO8 GPIO10 GPIO9 GPIO11
3 0x66 GPIO8 GPIO17 GPIO9 GPIO11

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Table 4-44. Parallel Boot Options

Option BOOTDEF Value D0-D7 GPIO C28x (DSP) Control GPIO Host Control GPIO
0 (default) 0x00 D0 - GPIO0 GPIO16 GPIO29
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7
1 0x20 D0 - GPIO0 GPIO16 GPIO11
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7

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4.8.10 Secure ROM Function APIs

There are a few functions that are available within Secure ROM to be called by the application to perform
EXEONLY Flash/RAM tasks in a secure manner.

Note
The application should disable interrupts before calling one of the EXEONLY function APIs.
If a vector fetch request is given by the CPU (C28) while its program counter (PC) is within
the EXEONLY function API code of the Secure ROM, a reset will fire (RSN if from C28). The
consequence of this is if an NMI or ITRAP or Bus Fault occurs while the PC is executing one of
the EXEONLY API functions, the NMI/ITRAP/Fault cannot be serviced because a reset will be fired to
the subsystem.

The secure copy code zone 1 and zone 2 functions allow EXEONLY Flash to be copied to EXEONLY RAM
in a secure manner. The source must be from EXEONLY Flash and the destination to EXEONLY RAM. There is
no support to copy EXEONLY ROM or EXEONLY RAM to RAM. Both Flash and RAM must be set to EXEONLY
and configured for the same zone. Additionally, the copy size must not cross over the Flash sector boundary.
Any violations of these requirements will result in a failure status returned. Upon successful copy of the data, the
number of 16-bit words copied is returned.
Table 4-45. Secure Copy Code Function
CPU Function Prototype Function Parameters Function Return Value
uint16_t SecureCopyCodeZ1(uint32_t size : The number of 16-bit words to 0xXXXX : Returns the number of
size, uint16_t *dst, uint16_t *src) copy 16-bit words copied
uint16_t SecureCopyCodeZ2(uint32_t dst : The destination memory address 0x0000 : Indicates one of the
size, uint16_t *dst, uint16_t *src) in EXEONLY RAM following: Copy length is zero; Copy
CPU (C28x) size crosses over Flash sector
boundary; Flash and RAM don't
src : The source memory address in belong to the same zone; Flash and/or
EXEONLY Flash RAM aren't set to EXEONLY; Error
occurred during data copy

The secure CRC calculation zone 1 and zone 2 functions allow a safety CRC check of EXEONLY memory
in a secure manner. The CRC length provided must be a value from 1 to 8 where 1 represents a CRC size of
32 16-bit words and 8 represents a CRC size of 4096 16-bit words. The source address specifies the starting
address for the CRC and the destination address is the location that the resulting CRC value will be stored. The
source and destination memories must be configured for the same zone. Additionally, the CRC length must not
cross over the Flash sector or RAM block boundary. Any violations of these requirements will result in a failure
status returned. Upon successful CRC, the number of 16-bit words CRC'd is returned.
Table 4-46. Secure CRC Calculation Function
CPU Function Prototype Function Parameters Function Return Value
len_id : A number from 1 to 8 which
uint16_t SecureCRCCalcZ1(uint16_t corresponds to length options of 32, 0xXXXX : Returns the number of
len_id, uint16_t *dst, uint16_t *src) 64, 128, 256, 512, 1024, 2048, or 16-bit words CRC'd
4096 16-bit words
uint16_t SecureCRCCalcZ2(uint16_t dst : The destination memory address 0x0000 : Indicates one of the
size, uint16_t *dst, uint16_t *src) for resulting CRC following: Invalid length option; Source
CPU (C28x) address isn't modulo of length value;
Destination address isn't within secure
RAM; CRC size crosses over Flash
src : The source memory address to sector or RAM block boundary; The
begin CRC calculation source and destination memory don't
belong to the same zone; On CM,
CRCLOCK is enabled

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The CMAC calculate and compare function allows to calculate CMAC signature of a Flash memory block and
compare against a golden signature. This is used in the secure boot mode to authenticate the boot image.
Table 4-47. Secure CRC Calculation Function
CPU Function Prototype Function Parameters Function Return Value
uint32_t
CPU1BROM_calculateCMAC(uint32_t startAddress: Starting address of 0xFFFFFFFFU: Calculated CMAC
memory for which CMAC has to be signature did not match golden
startAddress, uint32_t endAddress, calculated signature (fail)
uint32_t signatureAddress)
endAddress: Ending address of 0xA5A5A5A5U: Memory range
CPU (C28x) memory for which CMAC has to be provided isn't aligned to 128-bit
calculated boundary or length is zero
signatureAddress: Address of
location where golden CMAC 0xE1E1E1E1U: AES Engine timed out
signature is stored
0x00000000U: No Error

4.8.11 Clock Initializations

During boot-up, the boot ROM initializes the device clocking, depending upon the reset source, to assist in faster
boot time response. Clock configurations are performed by the boot ROM code only for POR and XRS reset
types. For all other resets, the boot ROM starts executing with the clocks that were already set up before reset.

Note
CPU performs clock configurations during boot up. If the PLL is used during the boot process, it will be
bypassed by the boot ROM code before branching to the user application.

Table 4-48. CPU Boot Clock Sources

Source Frequency Description
INTOSC2 10 MHz Default clock source
INTOSC1 10 MHz Set as clock source if missing clock is detected at power up or right after
device reset.
SYSPLL 115 MHz, 57.5 MHz Enabled optionally as part of main boot flow or as part of MPOST POR
memory test boot flow. PLL is bypassed and disabled after memory test has
completed. See more details regarding enabling MPOST POR memory test
in Section 4.8.1.1.

Table 4-49. CPU Clock State After Boot

Reset Source Clock State
1. Using INTOSC2
POR/XRS
2. System clock divider set to /1
All other Resets Maintain clocks setup before device reset.

4.8.12 Boot Status Information

Boot ROM keeps a record of the various actions and events that occur during boot ROM execution. The
reason for this is because NMI and other exceptions are enabled by default in the device and must be handled
accordingly. Boot ROM stores the boot status information in a RAM location so that the user application can read
this boot status and take the necessary actions per application’s needs to handle these events.

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4.8.12.1 Booting Status

Boot ROM health and booting status is written to a 32-bit address in M0RAM. This status is cleared on a POR or
XRS reset. The previous status is retained on any other reset. For example, you should clear the status before
performing a debugger device reset in order to view the latest boot ROM actions reflected in the status.
Table 4-50. Boot Status Address
Description Address
Boot ROM Status 0x0000 0002

Table 4-51. Boot Status Bit Fields

Value Description
0x8000 0000 HWBIST reset is handled successfully
0x2000 0000 EFuse Single Bit Error
0x1000 0000 LFU Flash Boot Error
0x0800 0000 Flash Verification Error
0x0400 0000 DCSM initialization LP Error
0x0200 0000 DCSM Initialization Invalid LP
0x0100 0000 SYSPLL enabled successfully
0x0080 0000 HWBIST NMI occurred
0x0040 0000 Missing clock NMI occurred
0x0020 0000 RAM Uncorrectable Error NMI occurred
0x0010 0000 Flash Uncorrectable Error NMI occurred
0x0008 0000 RL NMI occurred
0x0004 0000 ERAD NMI occurred
0x0002 0000 Boot ROM detected a PIE mismatch
0x0001 0000 Boot ROM detected an ITRAP
0x0000 8000 Boot ROM has completed running
0x0000 2000 Boot ROM handled POR
0x0000 1000 Boot ROM handled XRS
0x0000 0800 Boot ROM handled all the resets
0x0000 0400 POR memory test has completed
0x0000 0200 DCSM initialization has completed
0x0000 0100 RAM Initialization Complete
0x0000 000C LFU boot has started
0x0000 000B Wait boot has started
0x0000 000A CAN-FD boot has started
0x0000 0009 CAN boot has started
0x0000 0008 I2C boot has started
0x0000 0007 SPI boot has started
0x0000 0006 SCI boot has started
0x0000 0005 RAM boot has started
0x0000 0004 Parallel boot has started
0x0000 0003 Secure Flash boot has started
0x0000 0002 Flash boot has started
0x0000 0001 Boot ROM has started running

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4.8.12.2 Boot Mode and MPOST (Memory Power On Self-Test) Status

Once the boot mode is decoded during the boot flow, the boot mode value is written to RAM. Additionally when
running the MPOST POR memory test, the test result is written to RAM.
For more information, see the C2000™ Memory Power-On Self-Test (M-POST) Application Report.
Table 4-52. Boot Mode and MPOST Status Addresses
Description Address
Boot Mode 0x0000 0004
MPOST POR Memory Test Result 0x0000 0006

4.8.13 ROM Version

The ROM revision and release date information is stored at the ROM locations specified in Table 4-53. Reading
a revision number value of “0x100” represents version “1.0”, “0x101” represents version “1.1”, and so on.
Reading a revision date value of “0x0119” represents “01/19” or “January 2019”.
Table 4-53. Boot ROM Version Information
Contents Address
Revision Number 0x003F 8044
Revision Date 0x003F 8045
Build Number 0x003F 8046

4.9 Application Notes for Using the Bootloaders

4.9.1 Bootloader Data Stream Structure
This section details the data transfer protocols or stream structures that allow boot data transfer between boot
ROM and host device. This data transfer protocol is compatible to the respective bootloaders on C2000 devices.
Table 4-54 and Example 4-2 show the structure of the data stream incoming to the bootloader. The basic
structure is the same for all the bootloaders and is based on the C54x source data stream generated by
the C54x hex utility. The C28x hex utility (hex2000.exe) has been updated to support this structure. The
hex2000.exe utility is included with the C2000 code generation tools. All values in the data stream structure are
in hex. Refer to Section 4.9.2 for more details on using the C28x hex utility to convert a project to this format.
The first 16-bit word in the data stream is known as the key value. The key value is used to notify the bootloader
the width of the incoming stream: 8 or 16 bits. Note that not all bootloaders accept both 8- and 16-bit streams.
Refer to the detailed information on each loader for the valid data stream width. For an 8-bit data stream, the key
value is 0x08AA; for a 16-bit data stream, the key value is 0x10AA. If a bootloader receives an invalid key value,
then the load is aborted.
The next eight words are used to initialize register values or otherwise enhance the bootloader by passing
values to the bootloader. If a bootloader does not use these values then the values are reserved for future use
and the bootloader simply reads the value and then discards the value. Currently only the SPI and I2C and
parallel bootloaders use these words to initialize registers.
The tenth and eleventh words comprise the 22-bit entry point address. This address is used to initialize the PC
after the boot load is complete. This address is most likely the entry point of the program downloaded by the
bootloader.
The twelfth word in the data stream is the size of the first data block to be transferred. The size of the block is
defined as 8-bit data stream format. For example, to transfer a block of 20 8-bit data values from an 8-bit data
stream, the block size is 0x000A to indicate 10 16-bit words.

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The next two words tell the loader the destination address of the block of data. Following the size and address is
the 16-bit words that makeup that block of data.
This pattern of block size/destination address repeats for each block of data to be transferred. Once all the
blocks have been transferred, a block size of 0x0000 signals to the loader that the transfer is complete. At this
point, the loader returns the entry point address to the calling routine, which cleans up and exits. Execution then
continues at the entry point address as determined by the input data stream contents.
Table 4-54. LSB/MSB Loading Sequence in 8-Bit Data Stream
Contents
Byte LSB (First Byte of 2) MSB (Second Byte of 2)
1 2 LSB: AA (KeyValue for memory width = 8 bits) MSB: 08h (KeyValue for memory width = 8 bits)
3 4 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
5 6 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
7 8 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
... ... ... ...
... ... ... ...
17 18 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
19 20 LSB: Upper half of Entry point PC[23:16] MSB: Upper half of entry point PC[31:24] (Always 0x00)
21 22 LSB: Lower half of Entry point PC[7:0] MSB: Lower half of Entry point PC[15:8]
23 24 LSB: Block size in words of the first block to load. If MSB: block size
the block size is 0, this indicates the end of the source
program;.otherwise, another block follows. For example, a
block size of 0x000A indicates 10 words or 20 bytes in the
block.
25 26 LSB: MSW destination address, first block Addr[23:16] MSB: MSW destination address, first block Addr[31:24]
27 28 LSB: LSW destination address, first block Addr[7:0] MSB: LSW destination address, first block Addr[15:8]
29 30 LSB: First word of the first block being loaded MSB: First word of the first block being loaded
... ... ... ...
... ... ... ...
. . LSB: Last word of the first block to load MSB: Last word of the first block to load
. . LSB: Block size of the second block MSB: Block size of the second block
. . LSB: MSW destination address, second block Addr[23:16] MSB: MSW destination address, second block Addr[31:24]
. . LSB: LSW destination address, second block Addr[7:0] MSB: LSW destination address, second block Addr[15:8]
. . LSB: First word of the second block being loaded MSB: First word of the second block being loaded
... ... ... ...
... ... ... ...
. . LSB: Last word of the second block MSB: Last word of the second block
. . LSB: Block size of the last block MSB: Block size of the last block
. . LSB: MSW of destination address of last block Addr[23:16] MSB: MSW destination address, last block Addr[31:24]
. . LSB: LSW destination address, last block Addr[7:0] MSB: LSW destination address, last block Addr[15:8]
. . LSB: First word of the last block being loaded MSB: First word of the last block being loaded
... ... ... ...
... ... ... ...
. . LSB: Last word of the last block MSB: Last word of the last block
n n+1 LSB: 00h MSB: 00h - indicates the end of the source

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Example 4-2. Data Stream Structure 8-bit

AA 08 ; 0x08AA 8bit key value

00 00 00 00 ; 8 reserved words
00 00 00 00
00 00 00 00
00 00 00 00
3F 00 00 80 ; 0x003F8000 EntryAddr, starting point after boot load completes
05 00 ; 0x0005 First block consists of 5 16-bit words
3F 00 10 90 ; 0x003F9010 First block will be loaded starting at 0x3F9010
01 00 ; Data loaded = 0x0001 0x0002 0x0003 0x0004 0x0005
02 00
03 00
04 00
05 00
02 00 ; 0x0002 - 2nd block consists of 2 16bit words
3F 00 00 80 ; 0x003F8000 2nd block will be loaded starting at 0x3F8000
00 77 ; Data loaded = 0x7700 0x7625
25 76
00 00 ; 0x0000 Size of 0 indicates end of data stream
After load has completed the following memory values will have been initialized as follows:
Location Value
0x3F9010 0x0001
0x3F9011 0x0002
0x3F9012 0x0003
0x3F9013 0x0004
0x3F9014 0x0005
0x3F8000 0x7700
0x3F8001 0x7625
PC Begins execution at 0x3F8000

4.9.2 The C2000 Hex Utility

To use the features of the bootloader, you must generate a data stream and boot table as described in Section
4.9.1. The hex conversion utility tool, included with the 28x code generation tools, can generate the required
data stream including the required boot table. This section describes the hex2000 utility. An example of a file
conversion performed by hex2000 is described in Example 4-3.
The hex utility supports creation of the boot table required for the SCI, SPI, I2C, CAN, and parallel I/O loaders.
That is, the hex utility adds the required information to the file such as the key value, reserved bits, entry point,
address, block start address, block length and terminating value. The contents of the boot table vary slightly
depending on the boot mode and the options selected when running the hex conversion utility. The actual file
format required by the host (ASCII, binary, hex, and so on) differs from one specific application to another and
some additional conversion can be required.
To build the boot table, follow these steps:
1. Assemble or compile the code.
This creates the object files that then are used by the linker to create a single output file.
2. Link the file.
The linker combines all of the object files into a single output file in common object file format (ELF). The
specified linker command file is used by the linker to allocate the code sections to different memory blocks.
Each block of the boot table data corresponds to an initialized section in the ELF file. Uninitialized sections
are not converted by the hex conversion utility. The following options are useful:
• The linker -m option can be used to generate a map file. This map file shows all of the sections that were
created, their location in memory, and their length. The linker can be useful to check this file to make sure
that the initialized sections are where you expect them.
• The linker -w option configures the linker to show, if the linker assigned a section to a memory region
automatically. For example, if you have a section in your code called .TI.ramfunc.

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3. Run the hex conversion utility.

Choose the appropriate options for the desired boot mode and run the hex conversion utility to convert the
ELF file produced by the linker to a boot table.
See the TMS320C28x Assembly Language Tools User's Guide and the TMS320C28x Optimizing C/C++
Compiler User's Guide for more information on the compiling and linking process.
Table 4-55 summarizes the hex conversion utility options available for the bootloader. See the TMS320C28x
Assembly Language Tools User's Guide for a detailed description of the hex2000 operations used to generate a
boot table. Updates are made to support the I2C boot. See the Codegen release notes for the latest information.
Table 4-55. Boot Loader Options
Option Description
-boot Convert all sections into bootable form (use instead of a SECTIONS directive)
-sci8 Specify the source of the bootloader table as the SCI-A port, 8-bit mode
-spi8 Specify the source of the bootloader table as the SPI-A port, 8-bit mode
-gpio8 Specify the source of the bootloader table as the GPIO port, 8-bit mode
-bootorg value Specify the source address of the bootloader table
-lospcp value Specify the initial value for the LOSPCP register. This value is used only for the spi8 boot table format and
ignored for all other formats. If the value is greater than 0x7F, the value is truncated to 0x7F.
-spibrr value Specify the initial value for the SPIBRR register. This value is used only for the spi8 boot table format and
ignored for all other formats. If the value is greater than 0x7F, the value is truncated to 0x7F.
-e value Specify the entry point at which to begin execution after boot loading. The value can be an address or a global
symbol. This value is optional. The entry point can be defined at compile time using the linker -e option to
assign the entry point to a global symbol. The entry point for a C program is normally _c_int00 unless defined
otherwise by the -e linker option.
-i2c8 Specify the source of the bootloader table as the I2C-A port, 8-bit
-i2cpsc value Specify the value for the I2CPSC register. This value is loaded and takes effect after all I2C options are loaded,
prior to reading data from the EEPROM. This value is truncated to the 8 least-significant bits and can be set to
maintain an I2C module clock of 7-12 MHz.
-i2cclkh value Specify the value for the I2CCLKH register. This value is loaded and takes effect after all I2C options are
loaded, prior to reading data from the EEPROM.
-i2cclkl value Specify the value for the I2CCLKL register. This value is loaded and takes effect after all I2C options are
loaded, prior to reading data from the EEPROM.

Example 4-3. HEX2000.exe Command Syntax

C: HEX2000 GPIO34TOG.OUT -boot -gpio8 -a

Where:
- boot Convert all sections into bootable form.
- gpio8 Use the GPIO in 8-bit mode data format. The eCAN
uses the same data format as the GPIO in 8bit mode.
- a Select ASCII-Hex as the output format.

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4.10 Software
4.10.1 BOOT Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/boot
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.

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www.ti.com Dual Code Security Module (DCSM)

Chapter 5
Dual Code Security Module (DCSM)

This chapter explains the Dual Code Security Module.

5.1 Introduction...............................................................................................................................................................594
5.2 Functional Description.............................................................................................................................................594
5.3 Flash and OTP Erase/Program................................................................................................................................601
5.4 Secure Copy Code....................................................................................................................................................601
5.5 SecureCRC................................................................................................................................................................602
5.6 CSM Impact on Other On-Chip Resources.............................................................................................................603
5.7 Incorporating Code Security in User Applications................................................................................................604
5.8 Software.................................................................................................................................................................... 609
5.9 DCSM Registers........................................................................................................................................................609

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5.1 Introduction
The dual code security module (DCSM) is a security feature incorporated in this device. It prevents access and
visibility to on-chip secure memories (and other secure resources) by unauthorized persons. It also prevents
duplication and reverse-engineering of proprietary code. The term “secure” means that access to on-chip secure
memories and resources is blocked. The term “unsecure” means that access is allowed; that is, the contents
of the memory could be read by any means (for example, through a debugging tool such as Code Composer
Studio™ IDE.
The CSM has dual-zone security, Zone1 (Z1) and Zone2 (Z2).
5.1.1 DCSM Related Collateral

Getting Started Materials

• C2000 DCSM Security Tool Application Report
• C2000 Unique Device Number Application Report
• Enhancing Device Security by Using JTAGLOCK Feature Application Report
5.2 Functional Description
The security module restricts the CPU access to on-chip secure memory and resources without interrupting
or stalling CPU execution. When a read occurs to a secure memory location, the read returns a zero value
and CPU execution continues with the next instruction. This, in effect, blocks read and write access to secure
memories through the JTAG port or external peripherals.
The code security mechanism offers protection for two zones, Zone1 (Z1) and Zone2 (Z2). The security
mechanism for both the zones is identical. Each zone has its own dedicated secure resource and allocated
secure resource. The following are different secure resources available on this device:
• OTP: Each zone has its own dedicated secure OTP (USER OTP). This contains the security configurations
for the individual zone. If a zone is secure, its USER OTP content (including CSM passwords) can be read
(execution not allowed) only if the zone is unlocked using the password match flow (PMF).
• RAM: All LSx RAMs can be secure RAM on this device. These RAMs can be allocated to either zone by
configuring the respective GRABRAM locations in the USER OTP.
• Flash Sectors: Flash sectors of each CPU subsystems can be made secure on this device. Each Flash
sector can be allocated to either zone by configuring the respective GRABSECT locations in the bank's
USER OTP.
• Secure ROM: This device also has secure ROM on each CPU subsystem which is EXEONLY-protected.
These ROM contains specific function for the user, provided by TI.
Table 5-1 shows the status of a RAM block/Flash sector based on the configuration in the GRABRAM/
GRABSECT register.
The security of each zone is ensured by its own 128-bit (four 32-bit words) password (CSM password). The
password for each zone is stored in USER OTP. A zone can be unsecured by executing the password match
flow (PMF), described in Section 5.7.4.
There are three types of accesses: data/program reads, JTAG access, and instruction fetches (calls, jumps,
code executions, ISRs). Instruction fetches are never blocked. JTAG accesses are always blocked when a
memory is secure. Data reads to a secure memory are always blocked unless the program is executing from a
memory which belongs to the same zone. Data reads to unsecure memory are always allowed. Table 5-2 shows
the levels of security.

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Table 5-1. RAM/Flash Status

Zone 1 Zone 2
GRABRAMx/GRABSECTx Bits GRABRAMx/GRABSECT Bits Ownership and Accessibility
01 10 RAM block/Flash Sector belongs to Zone1
01 11(2) RAM block/Flash Sector belongs to Zone1
10 01 RAM block/Flash Sector belongs to Zone2
11(1) 01 RAM block/Flash Sector belongs to Zone2
10 10 RAM block/Flash Sector is unsecure
11 11 RAM block/Flash Sector inaccessible if either of the zone
is secure (CSM passwords are programmed). User should
never leave these values default (11) if CSM passwords
are programmed for even one zone.

(1) Zone1 must be unsecure. Assumption in this case is that user is not using Zone1 so none of the fields, including passwords, in Zone1
USER OTP are programmed by user hence Zone1 will always be unsecure.
(2) Zone2 must be unsecure. Assumption in this case is that user is not using Zone2 so none of the fields, including passwords, in Zone2
USER OTP are programmed by user hence Zone2 will always be unsecure.

Note
You should never program any other values in these fields. Failing any of these conditions for a RAM
block/Flash sector makes that RAM block/Flash sector inaccessible.

Table 5-2. Security Levels

PMF Executed With Operating Mode
Correct Password? of the Zone Program Fetch Location Security Description
No Secure Outside secure memory Only instruction fetches by the CPU are
allowed to secure memory. In other words,
code can still be executed, but not read.
No Secure Inside secure memory CPU has full access (except for EXEONLY
memories where read is not allowed). JTAG
port cannot read the secured memory
contents.
Yes Unsecure Anywhere Full access for CPU and JTAG port to secure
memory of that zone.

5.2.1 CSM Passwords

Unlike earlier C2000™ devices, on this device ALL_1 value (0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF) for CSM password for a zone does not unsecure the zone. Instead, if for any zone the CSM
password values get loaded as ALL_1 from USER OTP, the device will be in BLOCKED state. Due to this reason
TI will program a few bits in the second 32-bit password value (ZxOTP_CSMPSWD1) in every zone select
block of each zone with value ‘0’. The default value for this password location is chosen in a manner that the
respective ECC value remains ALL_1. Due to this, the CSMPSWD1 value programmed by TI for every zone
select block is different. See Table 5-3 for ZxOTP_CSMPSWD1 value, programmed by TI on every device. Since
ECC is not programmed, the user will be able to change this value by flipping the bits which are ‘1’ to ‘0’ but
leaving the ones which are already programmed by TI as ‘0’. BOOTROM code will write the default password
value into the KEYx register to unlock the device as part of device initialization sequence.
If the password locations of a zone have all 128 bits as zeros (ALL_0), that zone becomes permanently
secure (LOCKED state), regardless of the contents of the CSMKEYx registers which means the zone cannot
be unlocked using PMF, the password match flow described in Section 5.7.4. Therefore, the user should never
use ALL_0 as password. A password of ALL_0 will prevent debug of secure code or reprogramming the Flash
sectors. CSMKEYx registers are user-accessible registers that are used to unsecure the zones.

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Table 5-3. Default Value of ZxOTP (Programmed by TI)

Zone Select Block Zone1 USER OTP Zone2 USER OTP
Address Value Address Value
JLM_ENABLE 0x00078006 0xffff000f NA NA
(JTAGLOCK)
PSWDLOCK 0x00078010 0xfb7fffff 0x00078210 0x1f7fffff
CRCLOCK 0x00078012 0x7fffffff 0x00078212 0x3fffffff
JTAGPSWDH0 0x00078014 0x4bffffff NA NA
JTAGPSWDH1 0x00078016 0x3fffffff NA NA
Zone_Select_Block0 0x00078022 (CSMPSWD1) 0x4d7fffff 0x00078222 (CSMPSWD1) 0x1f7fffff
Zone_Select_Block0 0x0007803e (JTAGPSWDL1) 0x2bffffff NA NA
Zone_Select_Block1 0x00078042 (CSMPSWD1) 0x5f7fffff 0x00078242 (CSMPSWD1) 0xe57fffff
Zone_Select_Block1 0x0007805e (JTAGPSWDL1) 0x27ffffff NA NA
Zone_Select_Block2 0x00078062 (CSMPSWD1) 0x1dffffff 0x00078262 (CSMPSWD1) 0x4fffffff
Zone_Select_Block2 0x0007807e (JTAGPSWDL1) 0x7b7fffff NA NA
Zone_Select_Block3 0x00078082 (CSMPSWD1) 0xaf7fffff 0x00078282 (CSMPSWD1) 0xe37fffff
Zone_Select_Block3 0x0007809e (JTAGPSWDL1) 0xc9ffffff NA NA
Zone_Select_Block4 0x000780a2 (CSMPSWD1) 0x1bffffff 0x000782a2 (CSMPSWD1) 0x57ffffff
Zone_Select_Block4 0x000780be (JTAGPSWDL1) 0x7d7fffff NA NA
Zone_Select_Block5 0x000780c2 (CSMPSWD1) 0x17ffffff 0x000782c2 (CSMPSWD1) 0x5bffffff
Zone_Select_Block5 0x000780de (JTAGPSWDL1) 0x6f7fffff NA NA
Zone_Select_Block6 0x000780e2 (CSMPSWD1) 0xbd7fffff 0x000782e2 (CSMPSWD1) 0xf17fffff
Zone_Select_Block6 0x000780fe (JTAGPSWDL1) 0x33ffffff NA NA
Zone_Select_Block7 0x00078102 (CSMPSWD1) 0x9f7fffff 0x00078302 (CSMPSWD1) 0x3b7fffff
Zone_Select_Block7 0x0007811e (JTAGPSWDL1) 0x0fffffff NA NA
Zone_Select_Block8 0x00078122 (CSMPSWD1) 0x2bffffff 0x00078322 (CSMPSWD1) 0x8fffffff
Zone_Select_Block8 0x0007813e (JTAGPSWDL1) 0xbb7fffff NA NA
Zone_Select_Block9 0x00078142 (CSMPSWD1) 0x27ffffff 0x00078342 (CSMPSWD1) 0x6bffffff
Zone_Select_Block9 0x0007815e (JTAGPSWDL1) 0x5f7fffff NA NA
Zone_Select_Block10 0x00078162 (CSMPSWD1) 0x7b7fffff 0x00078362 (CSMPSWD1) 0x377fffff
Zone_Select_Block10 0x0007817e (JTAGPSWDL1) 0x1dffffff NA NA
Zone_Select_Block11 0x00078182 (CSMPSWD1) 0xc9ffffff 0x00078382 (CSMPSWD1) 0x9bffffff
Zone_Select_Block11 0x0007819e (JTAGPSWDL1) 0xaf7fffff NA NA
Zone_Select_Block12 0x000781a2 (CSMPSWD1) 0x7d7fffff 0x000783a2 (CSMPSWD1) 0x2f7fffff
Zone_Select_Block12 0x000781be (JTAGPSWDL1) 0x1bffffff NA NA
Zone_Select_Block13 0x000781c2 (CSMPSWD1) 0x6f7fffff 0x000783c2 (CSMPSWD1) 0xcb7fffff
Zone_Select_Block13 0x000781de (JTAGPSWDL1) 0x17ffffff NA NA
Zone_Select_Block14 0x000781e2 (CSMPSWD1) 0x33ffffff 0x000783e2 (CSMPSWD1) 0x97ffffff
Zone_Select_Block14 0x000781fe (JTAGPSWDL1) 0xbd7fffff

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5.2.2 Emulation Code Security Logic (ECSL)

In addition to the CSM, the emulation code security logic (ECSL) has been implemented using a 64-bit password
(part of existing CSM password) for each zone to prevent unauthorized users from stepping through secure
code. A halt in secure code while the emulator is connected will trip the ECSL and break the emulation
connection. To allow emulation of secure code, while maintaining the CSM protection against secure memory
reads, you must write the correct 64-bit password into the CSMKEY (0/1) registers, which matches the password
value stored in the USER OTP of that zone. This will disable the ECSL for the specific zone.
When initially debugging a device with the password locations in OTP programmed (secured), the emulator
takes some time to take control of the CPU. During this time, the CPU will start running and may execute an
instruction that performs an access to a protected ECSL area and if the CPU is halted when the program counter
(PC) is pointing to a secure location, the ECSL will trip and cause the emulator connection to be broken.
The solution to this problem is to use the Wait Boot Mode boot option. In this mode, the CPU will be in a loop
and will not jump to the user application code. Using this BOOTMODE, you can connect to CCS and debug the
code.
5.2.3 CPU Secure Logic
The CPU Secure Logic (CPUSL) on this device prevents a hacker from reading the CPU registers in a watch
window while code is running in a secure zone. All accesses to CPU registers when the PC points to a secure
location are blocked by this logic. The only exception to this is read access to the PC. It is highly recommended
not to write into the CPU register in this case, because proper code execution may get affected. If the CSM is
unlocked using the CSM password match flow, the CPUSL logic also gets disabled.
5.2.4 Password Lock
The password locations in USER OTP for each zone can be locked by programming the zone’s PSWDLOCK
field with any value other than “1111” (0xF) at the PSWDLOCK location in OTP. Until the passwords of a
zone are locked, password locations will not be secure and can be read from the debugger as well as code
running from non-secure memory. This feature can be used by the user to avoid accidental locking of the zone
while programming the Flash sectors during the software development phase. On a fresh device the value for
password lock fields for all zones at the PSWDLOCK location in OTP will be “1111” which means the password
for all zones will be unlocked.

Note
Password unlock only makes password locations non-secure. All other secure memories remains
secure as per security settings. Since password locations are non-secure, anyone can read the
password and make the zone un-secure by running through PMF, user must program PSWDLOCK
locations to lock the password before sending the device in field.

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5.2.5 JTAGLOCK
Sometimes you want to disable the JTAG access on a device to avoid any debug access to it. This can be done
by using the JTAGLOCK feature on this device. You need to follow a two step process to enable the JTAGLOCK
feature (both steps can be performed at the same time).
1. Program the JTAG passwords. This device has a 128-bit JTAG password that needs to be programmed in
Z1 USER OTP. JTAG passwords are split into two parts, JTAGPSWDH and JTAGPSWDL. JTAGPSWDH is
part of Z1 USER OTP header and JTAGPSWDL is part of Z1 Zone Select Block (ZSB). What this means
is program JTAGPSWDH once and change the JTAGPSWDL multiple times, if needed. Code Composer
Studio has an integrated tool that you need to use to unlock the JTAGLOCK on device.
2. After programming the JTAG passwords, you need to enable the JTAGLOCK module (JLM) by programming
bit [3:0] of Z1OTP_JLM_ENABLE with any value other than 0xF. It is recommended to program all four bits
with a value 0x0.
5.2.6 Link Pointer and Zone Select
For each of the two security zones, a dedicated OTP block exists that holds the configuration related to zone’s
security. The following are user programmable configurations:
• ZxOTP_LINKPOINTER1 • ZxOTP_CSMPSWD1
• ZxOTP_LINKPOINTER2 • ZxOTP_CSMPSWD2
• ZxOTP_LINKPOINTER3 • ZxOTP_CSMPSWD3
• Z1OTP_JLM_ENABLE • ZxOTP_GRABSECT1
• ZxOTP_GPREG1 • ZxOTP_GRABSECT2
• ZxOTP_GPREG2 • ZxOTP_GRABSECT3
• ZxOTP_GPREG3 • ZxOTP_GRABRAM1
• ZxOTP_GPREG4 • ZxOTP_GRABRAM2
• ZxOTP_PSWDLOCK • ZxOTP_GRABRAM3
• ZxOTP_CRCLOCK • ZxOTP_EXEONLYSECT1
• Z1OTP_JTAGPSWDH • ZxOTP_EXEONLYSECT2
• Z1OTP_CMACKEY • ZxOTP_EXEONLYRAM1
• ZxOTP_CSMPSWD0 • Z1OTP_JTAGPSWDL

Since OTP cannot be erased, the following configurations are placed in zone select blocks of each zone’s OTP
Flash of both the banks:
• ZxOTP_CSMPSWD0 • ZxOTP_GRABRAM1
• ZxOTP_CSMPSWD1 • ZxOTP_GRABRAM2
• ZxOTP_CSMPSWD2 • ZxOTP_GRABRAM3
• ZxOTP_CSMPSWD3 • ZxOTP_EXEONLYSECT1
• ZxOTP_GRABSECT1 • ZxOTP_EXEONLYSECT2
• ZxOTP_GRABSECT2 • ZxOTP_EXEONLYRAM1
• ZxOTP_GRABSECT3 • Z1OTP_JTAGPSWDL

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The location of the valid zone select block in OTP is decided based on the value of three 14-bit link pointers
(Zx-LINKPOINTERx) programmed in the OTP of each zone. All OTP locations except link pointers and
Z1OTP_JLM_ENABLE locations are protected with ECC. Since the link pointer locations are not protected
with ECC, three link pointers are provided that need to be programmed with the same value. The final value of
the link pointer is resolved in hardware, when a dummy read is done to all the link pointers, by comparing all
the three values (bit-wise voting logic). Since in OTP, a ‘1’ can be flipped by the user to ‘0’ but ‘0’ can not be
flipped to ‘1’ (no erase operation for OTP), the most significant bit position in the resolved link pointer which is
‘0’, defines the valid base address for the zone select block. While generating the final link pointer value, if the bit
pattern is not one of those listed in Figure 5-1, the final link pointer value becomes All_1 (0xFFFF_FFFF), which
selects the Zone-Select-Block1 (also known as the default zone select block).

Figure 5-1. Storage of Zone-Select Bits in OTP

Note
Address locations for other security settings that are not part of Zone Select blocks can be
programmed only once; therefore, you should program them towards end of the development cycle.

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Figure 5-2. Location of Zone-Select Block Based on Link-Pointer

CAUTION
USER OTP is ECC protected. You must program the ECC value while programming the security
setting in USER OTP. Failing to program the correct ECC value causes the device to be blocked
permanently and you will have to replace the device.

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5.2.7 C Code Example to Get Zone Select Block Addr for Zone1

unsigned long LinkPointer;

unsigned long *Zone1SelBlockPtr;
int Bitpos = 13;
int ZeroFound = 0;
// Read Z1-Linkpointer register of DCSM module.
LinkPointer = *(unsigned long *)0x5F000;
// Bits 31 to 15 as most-sigificant 0 are reserved LinkPointer options
LinkPointer = LinkPointer << 18;
while ((ZeroFound == 0) && (bitpos > -1))
{
if ((LinkPointer & 0x80000000) == 0)
{
ZeroFound = 1;
Zone1SelBlockPtr = (unsigned long *)(0x78000 + ((bitpos + 2)*32));
}
else
{
bitpos--;
LinkPointer = LinkPointer << 1;
}
}
if (ZeroFound == 0)
{
//Default in case there is no zero found.
Zone1SelBlockPtr = (unsigned long *)0x78020;
}

5.3 Flash and OTP Erase/Program

On this device, OTP as well as normal Flash, are secure resources. Each zone has its own dedicated
OTP, whereas normal Flash sectors can be allocated to any zone based on the value programmed in the
GRABSECTx location in OTP. Each zone has its own 128bit CSM passwords. Read and write accesses are
not allowed to resources assigned to Z1 by code running from memory allocated to Z2 and vice versa. Before
programming any secure Flash sector the user must either unlock the zone to which that particular sector
belongs using PMF or execute the Flash programming code from secure memory which belongs to the same
zone. The same is the case for erasing any secure Flash sector. To program the security settings in OTP Flash,
the user must unlock the CSM of the respective zone. Unless the zone is unlocked, security settings in OTP
Flash can not be updated. The OTP content cannot be erased.
A semaphore mechanism is provided to avoid the program/erase conflict between Z1 and Z2. A zone needs
to grab this semaphore to successfully complete the erase/program operation on the secure Flash sectors
allocated to that zone. A semaphore can be grabbed by a zone by writing the appropriate value in the SEM field
of the FLSEM register. For further details of this field, see the register description.
5.4 Secure Copy Code
In some applications, the user may want to copy the code from secure Flash to secure RAM for better
performance. The user cannot do this for EXEONLY Flash sectors because EXEONLY secure memories cannot
be read from anywhere. TI provides specific “Secure Copy Code” library functions for each zone to enable the
user to copy content from EXEONLY secure Flash sectors to EXEONLY RAM blocks. These functions do the
copy-code operation in a highly secure environment and allow a copy to be performed only when the following
conditions are met:
• The secure RAM block and the secure Flash sector belong to the same zone.
• Both the secure RAM block and the secure Flash sector have EXEONLY protection enabled.
For further usage of these library functions, see the ROM Code and Peripheral Booting chapter.

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5.5 SecureCRC
Since reads from EXEONLY memories are not allowed, the user cannot calculate the CRC on content in
EXEONLY memories using the CRC engine available on this device (for example, VCUCRC, GCRC) or
software. In some safety-critical applications, the user may have to calculate the CRC even on these memories.
To enable this without compromising on security, TI provides specific “SecureCRC” library functions for each
zone. These functions do the CRC calculation in highly secure environment and allow a CRC calculation to be
performed only when the following conditions are met:
• The source address should be modulo the number of words (based on length_id) for which the CRC needs to
be calculated.
• The destination address should belong to the same zone as the source address.
For further usage of these library functions, see the device-specific Boot ROM documentation.

Note
The user must disable all the interrupts before calling the secure functions in ROM. If there is a vector
fetch during secure function execution, the CPU gets reset immediately.

Disclaimer: The Code Security Module (CSM) included on this device was designed to password protect the
data stored in the associated memory and is warranted by Texas Instruments (TI), in accordance with its
standard terms and conditions, to conform to TI's published specifications for the warranty period applicable
for this device. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT
BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES
NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,
INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
PURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE
OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

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5.6 CSM Impact on Other On-Chip Resources

On this device, some of the memories are not secure. To avoid any potential hacking when the device is
in the default state (post reset), accesses (all types) to all memories (secure as well as non-secure, except
BOOT-ROM and OTP ) are disabled until proper security initialization is done. This means that after reset none
of the memory resources except BOOT_ROM and OTP is accessible to the user.
The following steps are required by CPU after reset (any type of reset) to initialize the security on device.
Security Initialization
• Dummy Read to address location of SECDC (0x703F0, TI-reserved register) in TI OTP
• Dummy Read to address location of Z1OTP_LINKPOINTER1 in Z1 OTP
• Dummy Read to address location of Z1OTP_LINKPOINTER2 in Z1 OTP
• Dummy Read to address location of Z1OTP_LINKPOINTER3 in Z1 OTP
• Dummy Read to address location of Z2OTP_LINKPOINTER1 in Z2 OTP
• Dummy Read to address location of Z2OTP_LINKPOINTER2 in Z2 OTP
• Dummy Read to address location of Z2OTP_LINKPOINTER3 in Z2 OTP
• Dummy Read to address location Z1OTP_JLM_ENABLE in Z1 OTP
• Dummy Read to address location of Z1OTP_GPREG1, Z1OTP_GPREG2, Z1OTP_GPREG3,
Z1OTP_GPREG4 in Z1 OTP
• Dummy Read to address location of Z1OTP_PSWDLOCK in Z1 OTP
• Dummy Read to address location of Z1OTP_CRCLOCK in Z1 OTP
• Dummy Read to address location of Z1OTP_JTAGPSWDH0, Z1OTP_JTAGPSWDH1 in Z1 OTP
• Dummy Read to address location of Z2OTP_GPREG1, Z2OTP_GPREG2, Z2OTP_GPREG3,
Z2OTP_GPREG4 in Z2 OTP
• Dummy Read to address location of Z2OTP_PSWDLOCK in Z2 OTP
• Dummy Read to address location of Z2OTP_CRCLOCK in Z2 OTP
• Read to memory map register of Z1_LINKPOINTER in DCSM module to calculate the address of zone select
block for Z1
• Dummy read to address location of Z1OTP_GRABSECT1, Z1OTP_GRABSECT2, Z1OTP_GRABSECT3 in
Z1 OTP
• Dummy read to address location of Z1OTP_GRABRAM1, Z1OTP_GRABRAM2, Z1OTP_GRABRAM3 in Z1
OTP
• Dummy read to address location of Z1OTP_EXEONLYSECT1, Z1OTP_EXEONLYSECT2 in Z1 OTP
• Dummy read to address location of Z1OTP_EXEONLYRAM1 in Z1 OTP
• Dummy Read to address location of Z1OTP_JTAGPSWDL0, Z1OTP_JTAGPSWDL1 in Z1 OTP
• Read to memory map register of Z2_LINKPOINTER in DCSM module to calculate the address of zone select
block for Z2
• Dummy read to address location of Z2OTP_GRABSECT1, Z2OTP_GRABSECT2, Z2OTP_GRABSECT3 in
Z2 OTP
• Dummy read to address location of Z2OTP_GRABRAM1, Z2OTP_GRABRAM2, Z2OTP_GRABRAM3 in Z2
OTP
• Dummy read to address location of Z2OTP_EXEONLYSECT1, Z2OTP_EXEONLYSECT2 in Z2 OTP
• Dummy read to address location of Z2OTP_EXEONLYRAM1 in Z2 OTP

Note
Security Initialization is done by BOOTROM code on all the resets (as part of device initialization) that
assert SYSRSn. This will not be part of user application code.
The order of initialization matters; hence, if a memory watch window with the USER OTP address is
opened in the debugger (CCS), the security initialization could occur in an incorrect order locking the
device down. To avoid this, you should not keep a memory window with USER OTP address opened
in the debugger (CCS) when performing a reset.

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5.7 Incorporating Code Security in User Applications

Code security is typically not required in the development phase of a project. However, security is needed
once a robust code is developed for a zone. Before such a code is programmed in the Flash memory, a CSM
password should be chosen to secure the zone. Once a CSM password is in place for a zone, the zone is
secured (programming a password at the appropriate locations and either performing a device reset or setting
the FORCESEC bit (Zx_CR.31) is the action that secures the device). From that time on, access to debug the
contents of secure memory by any means (via JTAG, code running off external/on-chip memory, and so forth)
requires a valid password. A password is not needed to run the code out of secure memory (such as in a typical
end-user usage); however, access to secure memory contents for debug purposes, requires a password.
5.7.1 Environments That Require Security Unlocking
The following are the typical situations under which unsecuring the zone can be required:
• Code development using debuggers (such as Code Composer Studio™ IDE). This is the most common
environment during the design phase of a product.
• Flash programming using TI's Flash utilities such as Code Composer Studio On-Chip Flash Programmer
plug-in or the Uniflash tool. Flash programming is common during code development and testing. Once
the user supplies the necessary password, the Flash utilities disable the security logic before attempting to
program the Flash. In custom programming solutions that use the Flash API supplied by TI, unlocking the
CSM can be avoided by executing the Flash programming algorithms from secure memory.
• Custom environment defined by the application
In addition to the above, access to secure memory contents can be required in situations such as:
– Using the on-chip bootloader to load code or data into secure SARAM or to erase and program the Flash.
– Executing code from on-chip unsecure memory and requiring access to secure memory for the lookup
table. This is not a suggested operating condition as supplying the password from external code could
compromise code security.
The unsecuring sequence is identical in all the above situations. This sequence is referred to as the password
match flow (PMF) for simplicity. Figure 5-3 explains the sequence of operation that is required every time the
user attempts to unsecure a particular zone. A code example is listed for clarity.
5.7.2 CSM Password Match Flow
Password match flow (PMF) is essentially a sequence of four dummy reads from password locations (PWL)
followed by four writes (32-bit writes) to CSMKEY(0/1/2/3) registers. Figure 5-3 shows how PMF helps to
initialize the security logic registers and disable security logic.

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Figure 5-3. CSM Password Match Flow (PMF)

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5.7.3 C Code Example to Unsecure C28x Zone1

volatile long int *CSM = (volatile long int *)5F090; //CSM register file volatile
long int *CSMPWL = (volatile long int *)0x78020; //CSM Password location (assuming default Zone
select block)
volatile int tmp;
int I;
// Read the 128-bits of the CSM password locations (PWL)
//
for (I=0;I<4; I++) tmp = *CSMPWL++;
// Write the 128-bit password to the CSMKEY registers
// If this password matches that stored in the
// CSLPWL then the CSM will become unsecure. If it does not
// match, then the zone will remain secure.
// An example password of: // 0x11112222333344445555666677778888 is used.
*CSM++ = 0x22221111; // Register Z1_CSMKEY0 at 0x5F090
*CSM++ = 0x44443333; // Register Z1_CSMKEY1 at 0x5F092
*CSM++ = 0x66665555; // Register Z1_CSMKEY2 at 0x5F094
*CSM++ = 0x88887777; // Register Z1_CSMKEY3 at 0x5F096

5.7.4 C Code Example to Resecure C28x Zone1

volatile int *Z1_CR = 0x5F019; //CSMSCR register

//Set FORCESEC bit
*Z1_CR = 0x8000;

5.7.5 Environments That Require ECSL Unlocking

The following are the typical situations under which unsecuring can be required:
• The user develops some main IP, and then outsources peripheral functions to a subcontractor who must be
able to run the user code during debug and may halt while main IP code is running. If ECSL is not unlocked,
then Code Composer Studio connections will get disconnected, which can be inconvenient for the user. Note
that unlocking ECSL does not enable access to secure code but only avoids disconnection of CCS (JTAG).
5.7.6 ECSL Password Match Flow
A password match flow (PMF) is essentially a sequence of eight dummy reads from password locations (PWL)
followed by two writes to KEY registers. Figure 5-4 shows how the PMF helps to initialize the security logic
registers and disable security logic.

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Figure 5-4. ECSL Password Match Flow (PMF)

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5.7.7 ECSL Disable Considerations for any Zone

A zone with ECSL enabled should have a predetermined ECSL password stored in the ECSL password
locations in Flash (same as lower 64 bits of CSM passwords). The following are steps to disable the ECSL
for any particular zone:
• Perform a dummy read of CSM password locations of that Zone.
• Write the password into the CSMKEY0/1 registers, corresponding to that Zone.
• If the password is correct, the ECSL gets disabled; otherwise, it stays enabled.
5.7.7.1 C Code Example to Disable ECSL for C28x Zone1

volatile long int *ECSL = (volatile int *)0x5F090; //ECSL register file
volatile long int *ECSLPWL = (volatile int *)0x78028; //ECSL Password location (assuming default
Zone sel block)
volatile int tmp;
int I;
// Read the 64-bits of the password locations (PWL).
for (I=0;I<2; I++) tmp = *ECSLPWL++;
// Write the 64-bit password to the CSMKEYx registers
// If this password matches that stored in the
// CSMPWL then ECSL will get disable. If it does not
// match, then the zone will remain secure.
// An example password of: // 0x1111222233334444 is used.
*ECSL++ = 0x22221111; // Register Z1_CSMKEY0 at 0x5F090
*ECSL++ = 0x44443333; // Register Z1_CSMKEY1 at 0x5F092

5.7.8 Device Unique ID

TI OTP contains a 256-bit value that is made up of both random and sequential parts. This value can be used as
a seed for code encryption. The starting address of the value is 0x70200. The first 192 bits are random, the next
32 bits are sequential, and the last 32 bits are a checksum value.

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5.8 Software
5.8.1 DCSM Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/dcsm
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
5.8.1.1 Empty DCSM Tool Example
FILE: dcsm_security_tool.c
This example is an empty project setup for DCSM Tool and Driverlib development. For guidance refer to: C2000
DCSM Security Tool
5.9 DCSM Registers
This section describes the various DCSM registers.
5.9.1 DCSM Base Address Table
Table 5-4. DCSM Base Address Table
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 DMA HIC CLA
Instance Structure Protected

DcsmZ1Regs DCSM_Z1_REGS DCSM_Z1_BASE 0x0005_F000 YES - - - YES

DcsmZ2Regs DCSM_Z2_REGS DCSM_Z2_BASE 0x0005_F080 YES - - - YES
DCSM_COMMON DCSMCOMMON_B
DcsmCommonRegs 0x0005_F0C0 YES - - - YES
_REGS ASE
DCSM_Z1OTP_BAS
DcsmZ1OtpRegs DCSM_Z1_OTP 0x0007_8000 YES - - - -
E
DCSM_Z2OTP_BAS
DcsmZ2OtpRegs DCSM_Z2_OTP 0x0007_8200 YES - - - -
E

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5.9.2 DCSM_Z1_REGS Registers

Table 5-5 lists the memory-mapped registers for the DCSM_Z1_REGS registers. All register offset addresses not
listed in Table 5-5 should be considered as reserved locations and the register contents should not be modified.
Table 5-5. DCSM_Z1_REGS Registers
Offset Acronym Register Name Write Protection Section
0h Z1_LINKPOINTER Zone 1 Link Pointer Go
2h Z1_OTPSECLOCK Zone 1 OTP Secure Lock Go
4h Z1_JLM_ENABLE Zone 1 JTAGLOCK Enable Register Go
6h Z1_LINKPOINTERERR Link Pointer Error Go
8h Z1_GPREG1 Zone 1 General Purpose Register-1 Go
Ah Z1_GPREG2 Zone 1 General Purpose Register-2 Go
Ch Z1_GPREG3 Zone 1 General Purpose Register-3 Go
Eh Z1_GPREG4 Zone 1 General Purpose Register-4 Go
10h Z1_CSMKEY0 Zone 1 CSM Key 0 Go
12h Z1_CSMKEY1 Zone 1 CSM Key 1 Go
14h Z1_CSMKEY2 Zone 1 CSM Key 2 Go
16h Z1_CSMKEY3 Zone 1 CSM Key 3 Go
18h Z1_CR Zone 1 CSM Control Register Go
1Ah Z1_GRABSECT1R Zone 1 Grab Flash Status Register 1 Go
1Ch Z1_GRABSECT2R Zone 1 Grab Flash Status Register 2 Go
1Eh Z1_GRABSECT3R Zone 1 Grab Flash Status Register 3 Go
20h Z1_GRABRAM1R Zone 1 Grab RAM Status Register 1 Go
26h Z1_EXEONLYSECT1R Zone 1 Execute Only Flash Status Register 1 Go
28h Z1_EXEONLYSECT2R Zone 1 Execute Only Flash Status Register 2 Go
2Ah Z1_EXEONLYRAM1R Zone 1 Execute Only RAM Status Register 1 Go
2Eh Z1_JTAGKEY0 JTAG Unlock Key Register 0 Go
30h Z1_JTAGKEY1 JTAG Unlock Key Register 1 Go
32h Z1_JTAGKEY2 JTAG Unlock Key Register 2 Go
34h Z1_JTAGKEY3 JTAG Unlock Key Register 3 Go
36h Z1_CMACKEY0 Secure Boot CMAC Key Status Register 0 Go
38h Z1_CMACKEY1 Secure Boot CMAC Key Status Register 1 Go
3Ah Z1_CMACKEY2 Secure Boot CMAC Key Status Register 2 Go
3Ch Z1_CMACKEY3 Secure Boot CMAC Key Status Register 3 Go

Complex bit access types are encoded to fit into small table cells. Table 5-6 shows the codes that are used for
access types in this section.
Table 5-6. DCSM_Z1_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value

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Table 5-6. DCSM_Z1_REGS Access Type Codes

(continued)
Access Type Code Description
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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5.9.2.1 Z1_LINKPOINTER Register (Offset = 0h) [Reset = FFFFC000h]

Z1_LINKPOINTER is shown in Figure 5-5 and described in Table 5-7.
Return to the Summary Table.
Zone 1 Link Pointer
Figure 5-5. Z1_LINKPOINTER Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LINKPOINTER
R-0h R-0h

Table 5-7. Z1_LINKPOINTER Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R 0h Reserved
13-0 LINKPOINTER R 0h This is resolved Link-Pointer value which is generated by looking at
the three physical Link-Pointer values loaded from OTP
Reset type: SYSRSn

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5.9.2.2 Z1_OTPSECLOCK Register (Offset = 2h) [Reset = 1h]

Z1_OTPSECLOCK is shown in Figure 5-6 and described in Table 5-8.
Return to the Summary Table.
Zone 1 OTP Secure Lock
Figure 5-6. Z1_OTPSECLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED CRCLOCK
R-0h R-0h

7 6 5 4 3 2 1 0
PSWDLOCK RESERVED JTAGLOCK
R-0h R-0h R-1h

Table 5-8. Z1_OTPSECLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 RESERVED R 0h Reserved
11-8 CRCLOCK R 0h Value in this field gets loaded from Z1_CRCLOCK[3:0] when a read
is issued to address location of Z1_CRCLOCK in OTP.
1111 : VCU has ability to calculate CRC on secure memories.
Other Value : VCU doesn't have ability to calculate CRC on secure
memories.
Reset type: XRSn
7-4 PSWDLOCK R 0h Value in this field gets loaded from Z1_PSWDLOCK[3:0] when a
read is issued to address location of Z1_PSWDLOCK in OTP.
1111 : CSM password locations in OTP are not protected and can be
read from debugger as well as code running from anywhere.
Other Value : CSM password locations in OTP are protected and
can't be read without unlocking CSM of that zone.
Reset type: XRSn
3-1 RESERVED R 0h Reserved
0 JTAGLOCK R 1h Reflects the state of the JTAGLOCK feature.
0 : JTAG is not locked
1 : JTAG is locked
Reset type: PORESETn

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5.9.2.3 Z1_JLM_ENABLE Register (Offset = 4h) [Reset = Fh]

Z1_JLM_ENABLE is shown in Figure 5-7 and described in Table 5-9.
Return to the Summary Table.
Zone 1 JTAGLOCK Enable Register
Figure 5-7. Z1_JLM_ENABLE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED Z1_JLM_ENABLE
R-0h R-Fh

Table 5-9. Z1_JLM_ENABLE Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R 0h Reserved
3-0 Z1_JLM_ENABLE R Fh Zone1 JLM_ENABLE register. The value in this field gets
loaded from Z1OTP_JLM_ENABLE[3:0] when a read is issued
to address location of Z1OTP_JLM_ENABLE in OTP. If
Z1OTP_JLM_ENABLE[31:0] is equal to all ones during the load,
the JTAGLOCK is not bypassed (is enabled). If the value of
Z1OTP_JLM_ENABLE[31:0] is not all ones during the load, the
JTAGLOCK is governed as follows by the Z1_JLM_ENABLE bits:
1111 : JTAG/Emulation access is allowed (JTAGLOCK is not
enabled)
Other values: JTAGLOCK is governed by the
JTAGKEY==JTAGPSWD match condition
Reset type: PORESETn

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5.9.2.4 Z1_LINKPOINTERERR Register (Offset = 6h) [Reset = 0h]

Z1_LINKPOINTERERR is shown in Figure 5-8 and described in Table 5-10.
Return to the Summary Table.
Link Pointer Error
Figure 5-8. Z1_LINKPOINTERERR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED Z1_LINKPOINTERERR
R-0h R-0h

Table 5-10. Z1_LINKPOINTERERR Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R 0h Reserved
13-0 Z1_LINKPOINTERERR R 0h These bits indicate errors during formation of the resolved Link-
Pointer value after the three physical Link-Pointer values loaded of
OTP in flash.
0 : No Error.
Other : Error on bit positions which is set to 1.
Reset type: SYSRSn

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5.9.2.5 Z1_GPREG1 Register (Offset = 8h) [Reset = 0h]

Z1_GPREG1 is shown in Figure 5-9 and described in Table 5-11.
Return to the Summary Table.
Zone 1 General Purpose Register-1
Figure 5-9. Z1_GPREG1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG1
R-0h

Table 5-11. Z1_GPREG1 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG1 R 0h This field gets loaded with the contents of Z1OTP_GPREG1
locations in Zone-1-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-1
Reset type: SYSRSn

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5.9.2.6 Z1_GPREG2 Register (Offset = Ah) [Reset = 0h]

Z1_GPREG2 is shown in Figure 5-10 and described in Table 5-12.
Return to the Summary Table.
Zone 1 General Purpose Register-2
Figure 5-10. Z1_GPREG2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG2
R-0h

Table 5-12. Z1_GPREG2 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG2 R 0h This field gets loaded with the contents of Z1OTP_GPREG2
locations in Zone-1-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-1
Reset type: SYSRSn

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5.9.2.7 Z1_GPREG3 Register (Offset = Ch) [Reset = 0h]

Z1_GPREG3 is shown in Figure 5-11 and described in Table 5-13.
Return to the Summary Table.
Zone 1 General Purpose Register-3
Figure 5-11. Z1_GPREG3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG3
R-0h

Table 5-13. Z1_GPREG3 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG3 R 0h This field gets loaded with the contents of Z1OTP_GPREG3
locations in Zone-1-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-1
Reset type: SYSRSn

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5.9.2.8 Z1_GPREG4 Register (Offset = Eh) [Reset = 0h]

Z1_GPREG4 is shown in Figure 5-12 and described in Table 5-14.
Return to the Summary Table.
Zone 1 General Purpose Register-4
Figure 5-12. Z1_GPREG4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG4
R-0h

Table 5-14. Z1_GPREG4 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG4 R 0h This field gets loaded with the contents of Z1OTP_GPREG4
locations in Zone-1-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-1
Reset type: SYSRSn

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5.9.2.9 Z1_CSMKEY0 Register (Offset = 10h) [Reset = 0h]

Z1_CSMKEY0 is shown in Figure 5-13 and described in Table 5-15.
Return to the Summary Table.
Zone 1 CSM Key 0
Figure 5-13. Z1_CSMKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY0
R/W-0h

Table 5-15. Z1_CSMKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY0 R/W 0h To unlock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD0, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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5.9.2.10 Z1_CSMKEY1 Register (Offset = 12h) [Reset = 0h]

Z1_CSMKEY1 is shown in Figure 5-14 and described in Table 5-16.
Return to the Summary Table.
Zone 1 CSM Key 1
Figure 5-14. Z1_CSMKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY1
R/W-0h

Table 5-16. Z1_CSMKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY1 R/W 0h To unlock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD1, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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5.9.2.11 Z1_CSMKEY2 Register (Offset = 14h) [Reset = 0h]

Z1_CSMKEY2 is shown in Figure 5-15 and described in Table 5-17.
Return to the Summary Table.
Zone 1 CSM Key 2
Figure 5-15. Z1_CSMKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY2
R/W-0h

Table 5-17. Z1_CSMKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY2 R/W 0h To unlock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD2, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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5.9.2.12 Z1_CSMKEY3 Register (Offset = 16h) [Reset = 0h]

Z1_CSMKEY3 is shown in Figure 5-16 and described in Table 5-18.
Return to the Summary Table.
Zone 1 CSM Key 3
Figure 5-16. Z1_CSMKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY3
R/W-0h

Table 5-18. Z1_CSMKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY3 R/W 0h To unlock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD3, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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5.9.2.13 Z1_CR Register (Offset = 18h) [Reset = 00080000h]

Z1_CR is shown in Figure 5-17 and described in Table 5-19.
Return to the Summary Table.
Zone 1 CSM Control Register
Figure 5-17. Z1_CR Register
31 30 29 28 27 26 25 24
FORCESEC RESERVED
R-0/W-0h R-0h

23 22 21 20 19 18 17 16
RESERVED ARMED UNSECURE ALLONE ALLZERO RESERVED
R-0h R-0h R-0h R-0h R-1h R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R-0h R-0h R-0h R-0h

Table 5-19. Z1_CR Register Field Descriptions

Bit Field Type Reset Description
31 FORCESEC R-0/W 0h A write of '1' to this bit relocks the zone by clearing the zone's
CSMKEYx registers. If the zone's CSMPSWDx OTP locations were
updated prior to using this bit, it is suggested that all of the new
password registers be dummy loaded from OTP immediately to
avoid a mix between old and new password data.
Reset type: SYSRSn
30-24 RESERVED R 0h Reserved
23 RESERVED R 0h Reserved
22 ARMED R 0h 0 : Dummy read to CSM Password locations in OTP hasn't been
performed.
1 : Dummy read to CSM Password locations in OTP has been
performed.
Reset type: SYSRSn
21 UNSECURE R 0h Indiacates the state of Zone.
0 : Zone is in lock(secure) state.
1 : Zone is in unlock(unsecure) state.
Reset type: SYSRSn
20 ALLONE R 0h Indicates the state of CSM passwords.
0 : Zone CSM Passwords are not all ones.
1 : Zone CSM Passwords are all ones.
Reset type: SYSRSn
19 ALLZERO R 1h Indicates the state of CSM passowrds.
0 : CSM Passwords are not all zeros.
1 : CSM Passwords are all zero and device is permanently locked.
Reset type: SYSRSn
18-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 RESERVED R 0h Reserved
1 RESERVED R 0h Reserved

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Table 5-19. Z1_CR Register Field Descriptions (continued)

Bit Field Type Reset Description
0 RESERVED R 0h Reserved

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5.9.2.14 Z1_GRABSECT1R Register (Offset = 1Ah) [Reset = 0h]

Z1_GRABSECT1R is shown in Figure 5-18 and described in Table 5-20.
Return to the Summary Table.
Zone 1 Grab Flash Status Register 1
Figure 5-18. Z1_GRABSECT1R Register
31 30 29 28 27 26 25 24
GRAB_SECT15 GRAB_SECT14 GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 5-20. Z1_GRABSECT1R Register Field Descriptions

Bit Field Type Reset Description
31-30 GRAB_SECT15 R 0h Value in this field gets loaded from Z1_GRABSECT1[31:30] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 15 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 15 to Zone1.
10 : No request for Bank 0 Flash Sector 15
11 : No request for Bank 0 Flash Sector 15 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 15 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
29-28 GRAB_SECT14 R 0h Value in this field gets loaded from Z1_GRABSECT1[29:28] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 14 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 14 to Zone1.
10 : No request for Bank 0 Flash Sector 14
11 : No request for Bank 0 Flash Sector 14 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 14 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z1_GRABSECT1[27:26] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 13 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 13 to Zone1.
10 : No request for Bank 0 Flash Sector 13
11 : No request for Bank 0 Flash Sector 13 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 13 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 5-20. Z1_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z1_GRABSECT1[25:24] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 12 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 12 to Zone1.
10 : No request for Bank 0 Flash Sector 12
11 : No request for Bank 0 Flash Sector 12 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 12 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z1_GRABSECT1[23:22] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 11 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 11 to Zone1.
10 : No request for Bank 0 Flash Sector 11
11 : No request for Bank 0 Flash Sector 11 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 11 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z1_GRABSECT1[21:20] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 10 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 10 to Zone1.
10 : No request for Bank 0 Flash Sector 10
11 : No request for Bank 0 Flash Sector 10 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 10 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z1_GRABSECT1[19:18] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 9 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 9 to Zone1.
10 : No request for Bank 0 Flash Sector 9
11 : No request for Bank 0 Flash Sector 9 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 9 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z1_GRABSECT1[17:16] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 8 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 8 to Zone1.
10 : No request for Bank 0 Flash Sector 8
11 : No request for Bank 0 Flash Sector 8 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 8 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z1_GRABSECT1[15:14] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 7 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 7 to Zone1.
10 : No request for Bank 0 Flash Sector 7
11 : No request for Bank 0 Flash Sector 7 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 7 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z1_GRABSECT1[13:12] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 6 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 6 to Zone1.
10 : No request for Bank 0 Flash Sector 6
11 : No request for Bank 0 Flash Sector 6 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 6 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 5-20. Z1_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z1_GRABSECT1[11:10] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 5 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 5 to Zone1.
10 : No request for Bank 0 Flash Sector 5
11 : No request for Bank 0 Flash Sector 5 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 5 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z1_GRABSECT1[9:8] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 4 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 4 to Zone1.
10 : No request for Bank 0 Flash Sector 4
11 : No request for Bank 0 Flash Sector 4 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 4 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z1_GRABSECT1[7:6] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 3 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 3 to Zone1.
10 : No request for Bank 0 Flash Sector 3
11 : No request for Bank 0 Flash Sector 3 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 3 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z1_GRABSECT1[5:4] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 2 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 2 to Zone1.
10 : No request for Bank 0 Flash Sector 2
11 : No request for Bank 0 Flash Sector 2 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 2 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z1_GRABSECT1[3:2] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 1 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 1 to Zone1.
10 : No request for Bank 0 Flash Sector 1
11 : No request for Bank 0 Flash Sector 1 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 1 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z1_GRABSECT1[1:0] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 0 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 0 to Zone1.
10 : No request for Bank 0 Flash Sector 0
11 : No request for Bank 0 Flash Sector 0 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 0 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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5.9.2.15 Z1_GRABSECT2R Register (Offset = 1Ch) [Reset = 0h]

Z1_GRABSECT2R is shown in Figure 5-19 and described in Table 5-21.
Return to the Summary Table.
Zone 1 Grab Flash Status Register 2
Figure 5-19. Z1_GRABSECT2R Register
31 30 29 28 27 26 25 24
GRAB_SECT15 GRAB_SECT14 GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 5-21. Z1_GRABSECT2R Register Field Descriptions

Bit Field Type Reset Description
31-30 GRAB_SECT15 R 0h Value in this field gets loaded from Z1_GRABSECT2[31:30] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 15 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 15 to Zone1.
10 : No request for Bank 1 Flash Sector 15
11 : No request for Bank 1 Flash Sector 15 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 15 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
29-28 GRAB_SECT14 R 0h Value in this field gets loaded from Z1_GRABSECT2[29:28] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 14 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 14 to Zone1.
10 : No request for Bank 1 Flash Sector 14
11 : No request for Bank 1 Flash Sector 14 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 14 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z1_GRABSECT2[27:26] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 13 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 13 to Zone1.
10 : No request for Bank 1 Flash Sector 13
11 : No request for Bank 1 Flash Sector 13 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 13 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 5-21. Z1_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z1_GRABSECT2[25:24] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 12 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 12 to Zone1.
10 : No request for Bank 1 Flash Sector 12
11 : No request for Bank 1 Flash Sector 12 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 12 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z1_GRABSECT2[23:22] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 11 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 11 to Zone1.
10 : No request for Bank 1 Flash Sector 11
11 : No request for Bank 1 Flash Sector 11 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 11 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z1_GRABSECT2[21:20] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 10 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 10 to Zone1.
10 : No request for Bank 1 Flash Sector 10
11 : No request for Bank 1 Flash Sector 10 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 10 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z1_GRABSECT2[19:18] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 9 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 9 to Zone1.
10 : No request for Bank 1 Flash Sector 9
11 : No request for Bank 1 Flash Sector 9 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 9 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z1_GRABSECT2[17:16] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 8 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 8 to Zone1.
10 : No request for Bank 1 Flash Sector 8
11 : No request for Bank 1 Flash Sector 8 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 8 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z1_GRABSECT2[15:14] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 7 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 7 to Zone1.
10 : No request for Bank 1 Flash Sector 7
11 : No request for Bank 1 Flash Sector 7 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 7 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z1_GRABSECT2[13:12] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 6 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 6 to Zone1.
10 : No request for Bank 1 Flash Sector 6
11 : No request for Bank 1 Flash Sector 6 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 6 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 5-21. Z1_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z1_GRABSECT2[11:10] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 5 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 5 to Zone1.
10 : No request for Bank 1 Flash Sector 5
11 : No request for Bank 1 Flash Sector 5 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 5 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z1_GRABSECT2[9:8] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 4 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 4 to Zone1.
10 : No request for Bank 1 Flash Sector 4
11 : No request for Bank 1 Flash Sector 4 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 4 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z1_GRABSECT2[7:6] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 3 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 3 to Zone1.
10 : No request for Bank 1 Flash Sector 3
11 : No request for Bank 1 Flash Sector 3 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 3 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z1_GRABSECT2[5:4] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 2 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 2 to Zone1.
10 : No request for Bank 1 Flash Sector 2
11 : No request for Bank 1 Flash Sector 2 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 2 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z1_GRABSECT2[3:2] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 1 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 1 to Zone1.
10 : No request for Bank 1 Flash Sector 1
11 : No request for Bank 1 Flash Sector 1 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 1 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z1_GRABSECT2[1:0] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 0 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 0 to Zone1.
10 : No request for Bank 1 Flash Sector 0
11 : No request for Bank 1 Flash Sector 0 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 0 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023 TMS320F28003x Real-Time Microcontrollers 631
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5.9.2.16 Z1_GRABSECT3R Register (Offset = 1Eh) [Reset = 0h]

Z1_GRABSECT3R is shown in Figure 5-20 and described in Table 5-22.
Return to the Summary Table.
Zone 1 Grab Flash Status Register 3
Figure 5-20. Z1_GRABSECT3R Register
31 30 29 28 27 26 25 24
GRAB_SECT15 GRAB_SECT14 GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 5-22. Z1_GRABSECT3R Register Field Descriptions

Bit Field Type Reset Description
31-30 GRAB_SECT15 R 0h Value in this field gets loaded from Z1_GRABSECT3[31:30] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 15 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 15 to Zone1.
10 : No request for Bank 2 Flash Sector 15
11 : No request for Bank 2 Flash Sector 15 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 15 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
29-28 GRAB_SECT14 R 0h Value in this field gets loaded from Z1_GRABSECT3[29:28] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 14 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 14 to Zone1.
10 : No request for Bank 2 Flash Sector 14
11 : No request for Bank 2 Flash Sector 14 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 14 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z1_GRABSECT3[27:26] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 13 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 13 to Zone1.
10 : No request for Bank 2 Flash Sector 13
11 : No request for Bank 2 Flash Sector 13 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 13 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 5-22. Z1_GRABSECT3R Register Field Descriptions (continued)

Bit Field Type Reset Description
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z1_GRABSECT3[25:24] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 12 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 12 to Zone1.
10 : No request for Bank 2 Flash Sector 12
11 : No request for Bank 2 Flash Sector 12 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 12 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z1_GRABSECT3[23:22] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 11 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 11 to Zone1.
10 : No request for Bank 2 Flash Sector 11
11 : No request for Bank 2 Flash Sector 11 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 11 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z1_GRABSECT3[21:20] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 10 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 10 to Zone1.
10 : No request for Bank 2 Flash Sector 10
11 : No request for Bank 2 Flash Sector 10 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 10 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z1_GRABSECT3[19:18] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 9 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 9 to Zone1.
10 : No request for Bank 2 Flash Sector 9
11 : No request for Bank 2 Flash Sector 9 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 9 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z1_GRABSECT3[17:16] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 8 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 8 to Zone1.
10 : No request for Bank 2 Flash Sector 8
11 : No request for Bank 2 Flash Sector 8 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 8 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z1_GRABSECT3[15:14] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 7 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 7 to Zone1.
10 : No request for Bank 2 Flash Sector 7
11 : No request for Bank 2 Flash Sector 7 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 7 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z1_GRABSECT3[13:12] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 6 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 6 to Zone1.
10 : No request for Bank 2 Flash Sector 6
11 : No request for Bank 2 Flash Sector 6 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 6 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 5-22. Z1_GRABSECT3R Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z1_GRABSECT3[11:10] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 5 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 5 to Zone1.
10 : No request for Bank 2 Flash Sector 5
11 : No request for Bank 2 Flash Sector 5 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 5 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z1_GRABSECT3[9:8] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 4 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 4 to Zone1.
10 : No request for Bank 2 Flash Sector 4
11 : No request for Bank 2 Flash Sector 4 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 4 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z1_GRABSECT3[7:6] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 3 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 3 to Zone1.
10 : No request for Bank 2 Flash Sector 3
11 : No request for Bank 2 Flash Sector 3 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 3 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z1_GRABSECT3[5:4] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 2 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 2 to Zone1.
10 : No request for Bank 2 Flash Sector 2
11 : No request for Bank 2 Flash Sector 2 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 2 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z1_GRABSECT3[3:2] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 1 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 1 to Zone1.
10 : No request for Bank 2 Flash Sector 1
11 : No request for Bank 2 Flash Sector 1 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 1 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z1_GRABSECT3[1:0] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 0 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 0 to Zone1.
10 : No request for Bank 2 Flash Sector 0
11 : No request for Bank 2 Flash Sector 0 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 0 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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5.9.2.17 Z1_GRABRAM1R Register (Offset = 20h) [Reset = 0h]

Z1_GRABRAM1R is shown in Figure 5-21 and described in Table 5-23.
Return to the Summary Table.
Zone 1 Grab RAM Status Register 1
Figure 5-21. Z1_GRABRAM1R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_RAM3 GRAB_RAM2 GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h R-0h

Table 5-23. Z1_GRABRAM1R Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z1_GRABRAM1[15:14] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. LS7 RAM is inaccessible.
01 : Request to allocate LS7 RAM to Zone1.
10 : No request for LS7 RAM
11 : No request for LS7 RAM when this zone is UNLOCKED. Else
LS7 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from Z1_GRABRAM1[13:12] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. LS6 RAM is inaccessible.
01 : Request to allocate LS6 RAM to Zone1.
10 : No request for LS6 RAM
11 : No request for LS6 RAM when this zone is UNLOCKED. Else
LS6 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from Z1_GRABRAM1[11:10] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. LS5 RAM is inaccessible.
01 : Request to allocate LS5 RAM to Zone1.
10 : No request for LS5 RAM
11 : No request for LS5 RAM when this zone is UNLOCKED. Else
LS5 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z1_GRABRAM1[9:8] when a read
is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. LS4 RAM is inaccessible.
01 : Request to allocate LS4 RAM to Zone1.
10 : No request for LS4 RAM
11 : No request for LS4 RAM when this zone is UNLOCKED. Else
LS4 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023 TMS320F28003x Real-Time Microcontrollers 635
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Table 5-23. Z1_GRABRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 GRAB_RAM3 R 0h Value in this field gets loaded from Z1_GRABRAM1[7:6] when a read
is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. LS3 RAM is inaccessible.
01 : Request to allocate LS3 RAM to Zone1.
10 : No request for LS3 RAM
11 : No request for LS3 RAM when this zone is UNLOCKED. Else
LS3 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
5-4 GRAB_RAM2 R 0h Value in this field gets loaded from Z1_GRABRAM1[5:4] when a read
is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. LS2 RAM is inaccessible.
01 : Request to allocate LS2 RAM to Zone1.
10 : No request for LS2 RAM
11 : No request for LS2 RAM when this zone is UNLOCKED. Else
LS2 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from Z1_GRABRAM1[3:2] when a read
is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. LS1 RAM is inaccessible.
01 : Request to allocate LS1 RAM to Zone1.
10 : No request for LS1 RAM
11 : No request for LS1 RAM when this zone is UNLOCKED. Else
LS1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from Z1_GRABRAM1[1:0] when a read
is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. LS0 RAM is inaccessible.
01 : Request to allocate LS0 RAM to Zone1.
10 : No request for LS0 RAM
11 : No request for LS0 RAM when this zone is UNLOCKED. Else
LS0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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5.9.2.18 Z1_EXEONLYSECT1R Register (Offset = 26h) [Reset = 0h]

Z1_EXEONLYSECT1R is shown in Figure 5-22 and described in Table 5-24.
Return to the Summary Table.
Zone 1 Execute Only Flash Status Register 1
Figure 5-22. Z1_EXEONLYSECT1R Register
31 30 29 28 27 26 25 24
EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA
NK1_SECT15 NK1_SECT14 NK1_SECT13 NK1_SECT12 NK1_SECT11 NK1_SECT10 NK1_SECT9 NK1_SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA
NK1_SECT7 NK1_SECT6 NK1_SECT5 NK1_SECT4 NK1_SECT3 NK1_SECT2 NK1_SECT1 NK1_SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA
NK0_SECT15 NK0_SECT14 NK0_SECT13 NK0_SECT12 NK0_SECT11 NK0_SECT10 NK0_SECT9 NK0_SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA
NK0_SECT7 NK0_SECT6 NK0_SECT5 NK0_SECT4 NK0_SECT3 NK0_SECT2 NK0_SECT1 NK0_SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 5-24. Z1_EXEONLYSECT1R Register Field Descriptions

Bit Field Type Reset Description
31 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[31] when a
15 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 15
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled forBank 1 Flash Sector 15
(only if it's allocated to Zone1)
Reset type: SYSRSn
30 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[30] when a
14 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 14
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled forBank 1 Flash Sector 14
(only if it's allocated to Zone1)
Reset type: SYSRSn
29 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[29] when a
13 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 13
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled forBank 1 Flash Sector 13
(only if it's allocated to Zone1)
Reset type: SYSRSn
28 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[28] when a
12 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 12
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled forBank 1 Flash Sector 12
(only if it's allocated to Zone1)
Reset type: SYSRSn

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Table 5-24. Z1_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
27 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[27] when a
11 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 11
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled forBank 1 Flash Sector 11
(only if it's allocated to Zone1)
Reset type: SYSRSn
26 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[26] when a
10 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 10
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled forBank 1 Flash Sector 10
(only if it's allocated to Zone1)
Reset type: SYSRSn
25 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[25] when a
9 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 9
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled forBank 1 Flash Sector 9
(only if it's allocated to Zone1)
Reset type: SYSRSn
24 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[24] when a
8 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 8
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled forBank 1 Flash Sector 8
(only if it's allocated to Zone1)
Reset type: SYSRSn
23 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[23] when a
7 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 7
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled forBank 1 Flash Sector 7
(only if it's allocated to Zone1)
Reset type: SYSRSn
22 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[22] when a
6 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 6
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled forBank 1 Flash Sector 6
(only if it's allocated to Zone1)
Reset type: SYSRSn
21 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[21] when a
5 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 5
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled forBank 1 Flash Sector 5
(only if it's allocated to Zone1)
Reset type: SYSRSn
20 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[20] when a
4 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 4
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled forBank 1 Flash Sector 4
(only if it's allocated to Zone1)
Reset type: SYSRSn

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Table 5-24. Z1_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
19 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[19] when a
3 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 3
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled forBank 1 Flash Sector 3
(only if it's allocated to Zone1)
Reset type: SYSRSn
18 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[18] when a
2 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 2
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled forBank 1 Flash Sector 2
(only if it's allocated to Zone1)
Reset type: SYSRSn
17 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[17] when a
1 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 1
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled forBank 1 Flash Sector 1
(only if it's allocated to Zone1)
Reset type: SYSRSn
16 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[16] when a
0 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 0
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled forBank 1 Flash Sector 0
(only if it's allocated to Zone1)
Reset type: SYSRSn
15 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[15] when a
15 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 15
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 15
(only if it's allocated to Zone1)
Reset type: SYSRSn
14 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[14] when a
14 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 14
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 14
(only if it's allocated to Zone1)
Reset type: SYSRSn
13 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[13] when a
13 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 13
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 13
(only if it's allocated to Zone1)
Reset type: SYSRSn
12 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[12] when a
12 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 12
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 12
(only if it's allocated to Zone1)
Reset type: SYSRSn

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Table 5-24. Z1_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
11 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[11] when a
11 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 11
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 11
(only if it's allocated to Zone1)
Reset type: SYSRSn
10 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[10] when a
10 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 10
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 10
(only if it's allocated to Zone1)
Reset type: SYSRSn
9 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[9] when a
9 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 9
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 9
(only if it's allocated to Zone1)
Reset type: SYSRSn
8 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[8] when a
8 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 8
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 8
(only if it's allocated to Zone1)
Reset type: SYSRSn
7 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[7] when a
7 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 7
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 7
(only if it's allocated to Zone1)
Reset type: SYSRSn
6 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[6] when a
6 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 6
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 6
(only if it's allocated to Zone1)
Reset type: SYSRSn
5 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[5] when a
5 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 5
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 5
(only if it's allocated to Zone1)
Reset type: SYSRSn
4 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[4] when a
4 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 4
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 4
(only if it's allocated to Zone1)
Reset type: SYSRSn

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Table 5-24. Z1_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
3 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[3] when a
3 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 3
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 3
(only if it's allocated to Zone1)
Reset type: SYSRSn
2 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[2] when a
2 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 2
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 2
(only if it's allocated to Zone1)
Reset type: SYSRSn
1 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[1] when a
1 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 1
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 1
(only if it's allocated to Zone1)
Reset type: SYSRSn
0 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[0] when a
0 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 0
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 0
(only if it's allocated to Zone1)
Reset type: SYSRSn

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5.9.2.19 Z1_EXEONLYSECT2R Register (Offset = 28h) [Reset = 0h]

Z1_EXEONLYSECT2R is shown in Figure 5-23 and described in Table 5-25.
Return to the Summary Table.
Zone 1 Execute Only Flash Status Register 2
Figure 5-23. Z1_EXEONLYSECT2R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA
NK2_SECT15 NK2_SECT14 NK2_SECT13 NK2_SECT12 NK2_SECT11 NK2_SECT10 NK2_SECT9 NK2_SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA
NK2_SECT7 NK2_SECT6 NK2_SECT5 NK2_SECT4 NK2_SECT3 NK2_SECT2 NK2_SECT1 NK2_SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 5-25. Z1_EXEONLYSECT2R Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[15] when a
15 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for BANK 2 Flash Sector 15
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for BANK 2 Flash Sector 15
(only if it's allocated to Zone1)
Reset type: SYSRSn
14 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[14] when a
14 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for BANK 2 Flash Sector 14
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for BANK 2 Flash Sector 14
(only if it's allocated to Zone1)
Reset type: SYSRSn
13 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[13] when a
13 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for BANK 2 Flash Sector 13
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for BANK 2 Flash Sector 13
(only if it's allocated to Zone1)
Reset type: SYSRSn
12 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[12] when a
12 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for BANK 2 Flash Sector 12
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for BANK 2 Flash Sector 12
(only if it's allocated to Zone1)
Reset type: SYSRSn

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Table 5-25. Z1_EXEONLYSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
11 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[11] when a
11 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for BANK 2 Flash Sector 11
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for BANK 2 Flash Sector 11
(only if it's allocated to Zone1)
Reset type: SYSRSn
10 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[10] when a
10 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for BANK 2 Flash Sector 10
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for BANK 2 Flash Sector 10
(only if it's allocated to Zone1)
Reset type: SYSRSn
9 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[9] when a
9 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for BANK 2 Flash Sector 9
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for BANK 2 Flash Sector 9
(only if it's allocated to Zone1)
Reset type: SYSRSn
8 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[8] when a
8 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for BANK 2 Flash Sector 8
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for BANK 2 Flash Sector 8
(only if it's allocated to Zone1)
Reset type: SYSRSn
7 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[7] when a
7 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for BANK 2 Flash Sector 7
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for BANK 2 Flash Sector 7
(only if it's allocated to Zone1)
Reset type: SYSRSn
6 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[6] when a
6 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for BANK 2 Flash Sector 6
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for BANK 2 Flash Sector 6
(only if it's allocated to Zone1)
Reset type: SYSRSn
5 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[5] when a
5 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for BANK 2 Flash Sector 5
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for BANK 2 Flash Sector 5
(only if it's allocated to Zone1)
Reset type: SYSRSn
4 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[4] when a
4 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for BANK 2 Flash Sector 4
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for BANK 2 Flash Sector 4
(only if it's allocated to Zone1)
Reset type: SYSRSn

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Table 5-25. Z1_EXEONLYSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
3 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[3] when a
3 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for BANK 2 Flash Sector 3
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for BANK 2 Flash Sector 3
(only if it's allocated to Zone1)
Reset type: SYSRSn
2 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[2] when a
2 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for BANK 2 Flash Sector 2
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for BANK 2 Flash Sector 2
(only if it's allocated to Zone1)
Reset type: SYSRSn
1 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[1] when a
1 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for BANK 2 Flash Sector 1
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for BANK 2 Flash Sector 1
(only if it's allocated to Zone1)
Reset type: SYSRSn
0 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[0] when a
0 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for BANK 2 Flash Sector 0
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for BANK 2 Flash Sector 0
(only if it's allocated to Zone1)
Reset type: SYSRSn

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5.9.2.20 Z1_EXEONLYRAM1R Register (Offset = 2Ah) [Reset = 0h]

Z1_EXEONLYRAM1R is shown in Figure 5-24 and described in Table 5-26.
Return to the Summary Table.
Zone 1 Execute Only RAM Status Register 1
Figure 5-24. Z1_EXEONLYRAM1R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA
M7 M6 M5 M4 M3 M2 M1 M0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 5-26. Z1_EXEONLYRAM1R Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R 0h Reserved
7 EXEONLY_RAM7 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[7] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS7 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS7 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
6 EXEONLY_RAM6 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[6] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for LS6 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS6 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
5 EXEONLY_RAM5 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[5] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for LS5 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS5 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
4 EXEONLY_RAM4 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[4] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for LS4 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS4 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn

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Table 5-26. Z1_EXEONLYRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
3 EXEONLY_RAM3 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[3] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for LS3 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS3 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
2 EXEONLY_RAM2 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[2] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for LS2 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS2 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
1 EXEONLY_RAM1 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[1] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for LS1 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS1 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
0 EXEONLY_RAM0 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[0] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for LS0 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for LS0 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn

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5.9.2.21 Z1_JTAGKEY0 Register (Offset = 2Eh) [Reset = 0h]

Z1_JTAGKEY0 is shown in Figure 5-25 and described in Table 5-27.
Return to the Summary Table.
JTAG Unlock Key Register 0
Figure 5-25. Z1_JTAGKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY0
R-0h

Table 5-27. Z1_JTAGKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY0 R 0h Value in this field is scanned in via the JLM scan chain. JTAGKEY is
compared to a hidden register that gets dummy loaded when a read
is issued to the JTAGPSWD locations in OTP.
Reset type: PORESETn

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5.9.2.22 Z1_JTAGKEY1 Register (Offset = 30h) [Reset = 0h]

Z1_JTAGKEY1 is shown in Figure 5-26 and described in Table 5-28.
Return to the Summary Table.
JTAG Unlock Key Register 1
Figure 5-26. Z1_JTAGKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY1
R-0h

Table 5-28. Z1_JTAGKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY1 R 0h Value in this field is scanned in via the JLM scan chain. JTAGKEY is
compared to a hidden register that gets dummy loaded when a read
is issued to the JTAGPSWD locations in OTP.
Reset type: PORESETn

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5.9.2.23 Z1_JTAGKEY2 Register (Offset = 32h) [Reset = 0h]

Z1_JTAGKEY2 is shown in Figure 5-27 and described in Table 5-29.
Return to the Summary Table.
JTAG Unlock Key Register 2
Figure 5-27. Z1_JTAGKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY2
R-0h

Table 5-29. Z1_JTAGKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY2 R 0h Value in this field is scanned in via the JLM scan chain. JTAGKEY is
compared to a hidden register that gets dummy loaded when a read
is issued to the JTAGPSWD locations in OTP.
Reset type: PORESETn

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5.9.2.24 Z1_JTAGKEY3 Register (Offset = 34h) [Reset = 0h]

Z1_JTAGKEY3 is shown in Figure 5-28 and described in Table 5-30.
Return to the Summary Table.
JTAG Unlock Key Register 3
Figure 5-28. Z1_JTAGKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY3
R-0h

Table 5-30. Z1_JTAGKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY3 R 0h Value in this field is scanned in via the JLM scan chain. JTAGKEY is
compared to a hidden register that gets dummy loaded when a read
is issued to the JTAGPSWD locations in OTP.
Reset type: PORESETn

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5.9.2.25 Z1_CMACKEY0 Register (Offset = 36h) [Reset = 0h]

Z1_CMACKEY0 is shown in Figure 5-29 and described in Table 5-31.
Return to the Summary Table.
Secure Boot CMAC Key Status Register 0
Figure 5-29. Z1_CMACKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY0
R-0h

Table 5-31. Z1_CMACKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY0 R 0h Value in this field gets loaded from CMACKEY0 when a read is
issued to its address in OTP.
Reset type: SYSRSn

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5.9.2.26 Z1_CMACKEY1 Register (Offset = 38h) [Reset = 0h]

Z1_CMACKEY1 is shown in Figure 5-30 and described in Table 5-32.
Return to the Summary Table.
Secure Boot CMAC Key Status Register 1
Figure 5-30. Z1_CMACKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY1
R-0h

Table 5-32. Z1_CMACKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY1 R 0h Value in this field gets loaded from CMACKEY1 when a read is
issued to its address in OTP.
Reset type: SYSRSn

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5.9.2.27 Z1_CMACKEY2 Register (Offset = 3Ah) [Reset = 0h]

Z1_CMACKEY2 is shown in Figure 5-31 and described in Table 5-33.
Return to the Summary Table.
Secure Boot CMAC Key Status Register 2
Figure 5-31. Z1_CMACKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY2
R-0h

Table 5-33. Z1_CMACKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY2 R 0h Value in this field gets loaded from CMACKEY2 when a read is
issued to its address in OTP.
Reset type: SYSRSn

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5.9.2.28 Z1_CMACKEY3 Register (Offset = 3Ch) [Reset = 0h]

Z1_CMACKEY3 is shown in Figure 5-32 and described in Table 5-34.
Return to the Summary Table.
Secure Boot CMAC Key Status Register 3
Figure 5-32. Z1_CMACKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY3
R-0h

Table 5-34. Z1_CMACKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY3 R 0h Value in this field gets loaded from CMACKEY3 when a read is
issued to its address in OTP.
Reset type: SYSRSn

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5.9.3 DCSM_Z2_REGS Registers

Table 5-35 lists the memory-mapped registers for the DCSM_Z2_REGS registers. All register offset addresses
not listed in Table 5-35 should be considered as reserved locations and the register contents should not be
modified.
Table 5-35. DCSM_Z2_REGS Registers
Offset Acronym Register Name Write Protection Section
0h Z2_LINKPOINTER Zone 2 Link Pointer Go
2h Z2_OTPSECLOCK Zone 2 OTP Secure Lock Go
6h Z2_LINKPOINTERERR Link Pointer Error Go
8h Z2_GPREG1 Zone 2 General Purpose Register-1 Go
Ah Z2_GPREG2 Zone 2 General Purpose Register-2 Go
Ch Z2_GPREG3 Zone 2 General Purpose Register-3 Go
Eh Z2_GPREG4 Zone 2 General Purpose Register-4 Go
10h Z2_CSMKEY0 Zone 2 CSM Key 0 Go
12h Z2_CSMKEY1 Zone 2 CSM Key 1 Go
14h Z2_CSMKEY2 Zone 2 CSM Key 2 Go
16h Z2_CSMKEY3 Zone 2 CSM Key 3 Go
18h Z2_CR Zone 2 CSM Control Register Go
1Ah Z2_GRABSECT1R Zone 2 Grab Flash Status Register 1 Go
1Ch Z2_GRABSECT2R Zone 2 Grab Flash Status Register 2 Go
1Eh Z2_GRABSECT3R Zone 2 Grab Flash Status Register 3 Go
20h Z2_GRABRAM1R Zone 2 Grab RAM Status Register 1 Go
26h Z2_EXEONLYSECT1R Zone 2 Execute Only Flash Status Register 1 Go
28h Z2_EXEONLYSECT2R Zone 2 Execute Only Flash Status Register 2 Go
2Ah Z2_EXEONLYRAM1R Zone 2 Execute Only RAM Status Register 1 Go

Complex bit access types are encoded to fit into small table cells. Table 5-36 shows the codes that are used for
access types in this section.
Table 5-36. DCSM_Z2_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.

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Table 5-36. DCSM_Z2_REGS Access Type Codes

(continued)
Access Type Code Description
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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5.9.3.1 Z2_LINKPOINTER Register (Offset = 0h) [Reset = FFFFC000h]

Z2_LINKPOINTER is shown in Figure 5-33 and described in Table 5-37.
Return to the Summary Table.
Zone 2 Link Pointer
Figure 5-33. Z2_LINKPOINTER Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LINKPOINTER
R-0h R-0h

Table 5-37. Z2_LINKPOINTER Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R 0h Reserved
13-0 LINKPOINTER R 0h This is resolved Link-Pointer value which is generated by looking at
the three physical Link-Pointer values loaded from OTP
Reset type: SYSRSn

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5.9.3.2 Z2_OTPSECLOCK Register (Offset = 2h) [Reset = 1h]

Z2_OTPSECLOCK is shown in Figure 5-34 and described in Table 5-38.
Return to the Summary Table.
Zone 2 OTP Secure Lock
Figure 5-34. Z2_OTPSECLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED CRCLOCK
R-0h R-0h

7 6 5 4 3 2 1 0
PSWDLOCK RESERVED JTAGLOCK
R-0h R-0h R-1h

Table 5-38. Z2_OTPSECLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 RESERVED R 0h Reserved
11-8 CRCLOCK R 0h Value in this field gets loaded from Z2_CRCLOCK[3:0] when a read
is issued to address location of Z2_CRCLOCK in OTP.
1111 : VCU has ability to calculate CRC on secure memories.
Other Value : VCU doesn't have ability to calculate CRC on secure
memories.
Reset type: XRSn
7-4 PSWDLOCK R 0h Value in this field gets loaded from Z2_PSWDLOCK[3:0] when a
read is issued to address location of Z1_PSWDLOCK in OTP.
1111 : CSM password locations in OTP are not protected and can be
read from debugger as well as code running from anywhere.
Other Value : CSM password locations in OTP are protected and
can't be read without unlocking CSM of that zone.
Reset type: XRSn
3-1 RESERVED R 0h Reserved
0 JTAGLOCK R 1h Reflects the state of the JTAGLOCK feature.
0 : JTAG is not locked
1 : JTAG is locked
This bit is a copy of the Z1_OTPSECLOCK.JTAGLOCK bit.
Reset type: PORESETn

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5.9.3.3 Z2_LINKPOINTERERR Register (Offset = 6h) [Reset = 0h]

Z2_LINKPOINTERERR is shown in Figure 5-35 and described in Table 5-39.
Return to the Summary Table.
Link Pointer Error
Figure 5-35. Z2_LINKPOINTERERR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED Z2_LINKPOINTERERR
R-0h R-0h

Table 5-39. Z2_LINKPOINTERERR Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R 0h Reserved
13-0 Z2_LINKPOINTERERR R 0h These bits indicate errors during formation of the resolved Link-
Pointer value after the three physical Link-Pointer values loaded of
OTP in flash.
0 : No Error.
Other : Error on bit positions which is set to 1.
Reset type: SYSRSn

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5.9.3.4 Z2_GPREG1 Register (Offset = 8h) [Reset = 0h]

Z2_GPREG1 is shown in Figure 5-36 and described in Table 5-40.
Return to the Summary Table.
Zone 2 General Purpose Register-1
Figure 5-36. Z2_GPREG1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG1
R-0h

Table 5-40. Z2_GPREG1 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG1 R 0h This field gets loaded with the contents of Z2OTP_GPREG1
locations in Zone-2-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-2
Reset type: SYSRSn

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5.9.3.5 Z2_GPREG2 Register (Offset = Ah) [Reset = 0h]

Z2_GPREG2 is shown in Figure 5-37 and described in Table 5-41.
Return to the Summary Table.
Zone 2 General Purpose Register-2
Figure 5-37. Z2_GPREG2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG2
R-0h

Table 5-41. Z2_GPREG2 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG2 R 0h This field gets loaded with the contents of Z2OTP_GPREG2
locations in Zone-2-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-2
Reset type: SYSRSn

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5.9.3.6 Z2_GPREG3 Register (Offset = Ch) [Reset = 0h]

Z2_GPREG3 is shown in Figure 5-38 and described in Table 5-42.
Return to the Summary Table.
Zone 2 General Purpose Register-3
Figure 5-38. Z2_GPREG3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG3
R-0h

Table 5-42. Z2_GPREG3 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG3 R 0h This field gets loaded with the contents of Z2OTP_GPREG3
locations in Zone-2-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-2
Reset type: SYSRSn

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5.9.3.7 Z2_GPREG4 Register (Offset = Eh) [Reset = 0h]

Z2_GPREG4 is shown in Figure 5-39 and described in Table 5-43.
Return to the Summary Table.
Zone 2 General Purpose Register-4
Figure 5-39. Z2_GPREG4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG4
R-0h

Table 5-43. Z2_GPREG4 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG4 R 0h This field gets loaded with the contents of Z2OTP_GPREG4
locations in Zone-2-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-2
Reset type: SYSRSn

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5.9.3.8 Z2_CSMKEY0 Register (Offset = 10h) [Reset = 0h]

Z2_CSMKEY0 is shown in Figure 5-40 and described in Table 5-44.
Return to the Summary Table.
Zone 2 CSM Key 0
Figure 5-40. Z2_CSMKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY0
R/W-0h

Table 5-44. Z2_CSMKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY0 R/W 0h To unlock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD0, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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5.9.3.9 Z2_CSMKEY1 Register (Offset = 12h) [Reset = 0h]

Z2_CSMKEY1 is shown in Figure 5-41 and described in Table 5-45.
Return to the Summary Table.
Zone 2 CSM Key 1
Figure 5-41. Z2_CSMKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY1
R/W-0h

Table 5-45. Z2_CSMKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY1 R/W 0h To unlock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD1, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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5.9.3.10 Z2_CSMKEY2 Register (Offset = 14h) [Reset = 0h]

Z2_CSMKEY2 is shown in Figure 5-42 and described in Table 5-46.
Return to the Summary Table.
Zone 2 CSM Key 2
Figure 5-42. Z2_CSMKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY2
R/W-0h

Table 5-46. Z2_CSMKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY2 R/W 0h To unlock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD2, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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5.9.3.11 Z2_CSMKEY3 Register (Offset = 16h) [Reset = 0h]

Z2_CSMKEY3 is shown in Figure 5-43 and described in Table 5-47.
Return to the Summary Table.
Zone 2 CSM Key 3
Figure 5-43. Z2_CSMKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY3
R/W-0h

Table 5-47. Z2_CSMKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY3 R/W 0h To unlock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD3, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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5.9.3.12 Z2_CR Register (Offset = 18h) [Reset = 00080000h]

Z2_CR is shown in Figure 5-44 and described in Table 5-48.
Return to the Summary Table.
Zone 2 CSM Control Register
Figure 5-44. Z2_CR Register
31 30 29 28 27 26 25 24
FORCESEC RESERVED
R-0/W-0h R-0h

23 22 21 20 19 18 17 16
RESERVED ARMED UNSECURE ALLONE ALLZERO RESERVED
R-0h R-0h R-0h R-0h R-1h R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R-0h R-0h R-0h R-0h

Table 5-48. Z2_CR Register Field Descriptions

Bit Field Type Reset Description
31 FORCESEC R-0/W 0h A write of '1' to this bit relocks the zone by clearing the zone's
CSMKEYx registers. If the zone's CSMPSWDx OTP locations were
updated prior to using this bit, it is suggested that all of the new
password registers be dummy loaded from OTP immediately to
avoid a mix between old and new password data.
Reset type: SYSRSn
30-24 RESERVED R 0h Reserved
23 RESERVED R 0h Reserved
22 ARMED R 0h 0 : Dummy read to CSM Password locations in OTP hasn't been
performed.
1 : Dummy read to CSM Password locations in OTP has been
performed.
Reset type: SYSRSn
21 UNSECURE R 0h Indiacates the state of Zone.
0 : Zone is in lock(secure) state.
1 : Zone is in unlock(unsecure) state.
Reset type: SYSRSn
20 ALLONE R 0h Indicates the state of CSM passwords.
0 : Zone CSM Passwords are not all ones.
1 : Zone CSM Passwords are all ones.
Reset type: SYSRSn
19 ALLZERO R 1h Indicates the state of CSM passowrds.
0 : CSM Passwords are not all zeros.
1 : CSM Passwords are all zero and device is permanently locked.
Reset type: SYSRSn
18-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 RESERVED R 0h Reserved
1 RESERVED R 0h Reserved

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Table 5-48. Z2_CR Register Field Descriptions (continued)

Bit Field Type Reset Description
0 RESERVED R 0h Reserved

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5.9.3.13 Z2_GRABSECT1R Register (Offset = 1Ah) [Reset = 0h]

Z2_GRABSECT1R is shown in Figure 5-45 and described in Table 5-49.
Return to the Summary Table.
Zone 2 Grab Flash Status Register 1
Figure 5-45. Z2_GRABSECT1R Register
31 30 29 28 27 26 25 24
GRAB_SECT15 GRAB_SECT14 GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 5-49. Z2_GRABSECT1R Register Field Descriptions

Bit Field Type Reset Description
31-30 GRAB_SECT15 R 0h Value in this field gets loaded from Z2_GRABSECT1[31:30] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 15 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 15 to Zone2.
10 : No request for Bank 0 Flash Sector 15
11 : No request for Bank 0 Flash Sector 15 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 15 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
29-28 GRAB_SECT14 R 0h Value in this field gets loaded from Z2_GRABSECT1[29:28] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 14 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 14 to Zone2.
10 : No request for Bank 0 Flash Sector 14
11 : No request for Bank 0 Flash Sector 14 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 14 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z2_GRABSECT1[27:26] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 13 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 13 to Zone2.
10 : No request for Bank 0 Flash Sector 13
11 : No request for Bank 0 Flash Sector 13 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 13 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 5-49. Z2_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z2_GRABSECT1[25:24] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 12 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 12 to Zone2.
10 : No request for Bank 0 Flash Sector 12
11 : No request for Bank 0 Flash Sector 12 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 12 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z2_GRABSECT1[23:22] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 11 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 11 to Zone2.
10 : No request for Bank 0 Flash Sector 11
11 : No request for Bank 0 Flash Sector 11 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 11 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z2_GRABSECT1[21:20] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 10 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 10 to Zone2.
10 : No request for Bank 0 Flash Sector 10
11 : No request for Bank 0 Flash Sector 10 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 10 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z2_GRABSECT1[19:18] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 9 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 9 to Zone2.
10 : No request for Bank 0 Flash Sector 9
11 : No request for Bank 0 Flash Sector 9 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 9 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z2_GRABSECT1[17:16] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 8 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 8 to Zone2.
10 : No request for Bank 0 Flash Sector 8
11 : No request for Bank 0 Flash Sector 8 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 8 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z2_GRABSECT1[15:14] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 7 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 7 to Zone2.
10 : No request for Bank 0 Flash Sector 7
11 : No request for Bank 0 Flash Sector 7 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 7 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z2_GRABSECT1[13:12] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 6 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 6 to Zone2.
10 : No request for Bank 0 Flash Sector 6
11 : No request for Bank 0 Flash Sector 6 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 6 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 5-49. Z2_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z2_GRABSECT1[11:10] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 5 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 5 to Zone2.
10 : No request for Bank 0 Flash Sector 5
11 : No request for Bank 0 Flash Sector 5 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 5 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z2_GRABSECT1[9:8] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 4 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 4 to Zone2.
10 : No request for Bank 0 Flash Sector 4
11 : No request for Bank 0 Flash Sector 4 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 4 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z2_GRABSECT1[7:6] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 3 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 3 to Zone2.
10 : No request for Bank 0 Flash Sector 3
11 : No request for Bank 0 Flash Sector 3 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 3 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z2_GRABSECT1[5:4] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 2 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 2 to Zone2.
10 : No request for Bank 0 Flash Sector 2
11 : No request for Bank 0 Flash Sector 2 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 2 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z2_GRABSECT1[3:2] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 1 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 1 to Zone2.
10 : No request for Bank 0 Flash Sector 1
11 : No request for Bank 0 Flash Sector 1 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 1 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z2_GRABSECT1[1:0] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. Bank 0 Flash Sector 0 is inaccessible.
01 : Request to allocate Bank 0 Flash Sector 0 to Zone2.
10 : No request for Bank 0 Flash Sector 0
11 : No request for Bank 0 Flash Sector 0 when this zone is
UNLOCKED. Else Bank 0 Flash Sector 0 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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5.9.3.14 Z2_GRABSECT2R Register (Offset = 1Ch) [Reset = 0h]

Z2_GRABSECT2R is shown in Figure 5-46 and described in Table 5-50.
Return to the Summary Table.
Zone 2 Grab Flash Status Register 2
Figure 5-46. Z2_GRABSECT2R Register
31 30 29 28 27 26 25 24
GRAB_SECT15 GRAB_SECT14 GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 5-50. Z2_GRABSECT2R Register Field Descriptions

Bit Field Type Reset Description
31-30 GRAB_SECT15 R 0h Value in this field gets loaded from Z2_GRABSECT2[31:30] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 15 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 15 to Zone2.
10 : No request for Bank 1 Flash Sector 15
11 : No request for Bank 1 Flash Sector 15 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 15 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
29-28 GRAB_SECT14 R 0h Value in this field gets loaded from Z2_GRABSECT2[29:28] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 14 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 14 to Zone2.
10 : No request for Bank 1 Flash Sector 14
11 : No request for Bank 1 Flash Sector 14 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 14 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z2_GRABSECT2[27:26] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 13 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 13 to Zone2.
10 : No request for Bank 1 Flash Sector 13
11 : No request for Bank 1 Flash Sector 13 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 13 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 5-50. Z2_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z2_GRABSECT2[25:24] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 12 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 12 to Zone2.
10 : No request for Bank 1 Flash Sector 12
11 : No request for Bank 1 Flash Sector 12 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 12 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z2_GRABSECT2[23:22] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 11 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 11 to Zone2.
10 : No request for Bank 1 Flash Sector 11
11 : No request for Bank 1 Flash Sector 11 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 11 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z2_GRABSECT2[21:20] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 10 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 10 to Zone2.
10 : No request for Bank 1 Flash Sector 10
11 : No request for Bank 1 Flash Sector 10 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 10 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z2_GRABSECT2[19:18] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 9 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 9 to Zone2.
10 : No request for Bank 1 Flash Sector 9
11 : No request for Bank 1 Flash Sector 9 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 9 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z2_GRABSECT2[17:16] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 8 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 8 to Zone2.
10 : No request for Bank 1 Flash Sector 8
11 : No request for Bank 1 Flash Sector 8 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 8 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z2_GRABSECT2[15:14] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 7 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 7 to Zone2.
10 : No request for Bank 1 Flash Sector 7
11 : No request for Bank 1 Flash Sector 7 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 7 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z2_GRABSECT2[13:12] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 6 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 6 to Zone2.
10 : No request for Bank 1 Flash Sector 6
11 : No request for Bank 1 Flash Sector 6 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 6 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 5-50. Z2_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z2_GRABSECT2[11:10] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 5 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 5 to Zone2.
10 : No request for Bank 1 Flash Sector 5
11 : No request for Bank 1 Flash Sector 5 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 5 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z2_GRABSECT2[9:8] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 4 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 4 to Zone2.
10 : No request for Bank 1 Flash Sector 4
11 : No request for Bank 1 Flash Sector 4 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 4 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z2_GRABSECT2[7:6] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 3 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 3 to Zone2.
10 : No request for Bank 1 Flash Sector 3
11 : No request for Bank 1 Flash Sector 3 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 3 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z2_GRABSECT2[5:4] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 2 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 2 to Zone2.
10 : No request for Bank 1 Flash Sector 2
11 : No request for Bank 1 Flash Sector 2 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 2 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z2_GRABSECT2[3:2] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 1 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 1 to Zone2.
10 : No request for Bank 1 Flash Sector 1
11 : No request for Bank 1 Flash Sector 1 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 1 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z2_GRABSECT2[1:0] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. Bank 1 Flash Sector 0 is inaccessible.
01 : Request to allocate Bank 1 Flash Sector 0 to Zone2.
10 : No request for Bank 1 Flash Sector 0
11 : No request for Bank 1 Flash Sector 0 when this zone is
UNLOCKED. Else Bank 1 Flash Sector 0 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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5.9.3.15 Z2_GRABSECT3R Register (Offset = 1Eh) [Reset = 0h]

Z2_GRABSECT3R is shown in Figure 5-47 and described in Table 5-51.
Return to the Summary Table.
Zone 2 Grab Flash Status Register 3
Figure 5-47. Z2_GRABSECT3R Register
31 30 29 28 27 26 25 24
GRAB_SECT15 GRAB_SECT14 GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 5-51. Z2_GRABSECT3R Register Field Descriptions

Bit Field Type Reset Description
31-30 GRAB_SECT15 R 0h Value in this field gets loaded from Z2_GRABSECT3[31:30] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 15 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 15 to Zone2.
10 : No request for Bank 2 Flash Sector 15
11 : No request for Bank 2 Flash Sector 15 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 15 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
29-28 GRAB_SECT14 R 0h Value in this field gets loaded from Z2_GRABSECT3[29:28] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 14 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 14 to Zone2.
10 : No request for Bank 2 Flash Sector 14
11 : No request for Bank 2 Flash Sector 14 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 14 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z2_GRABSECT3[27:26] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 13 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 13 to Zone2.
10 : No request for Bank 2 Flash Sector 13
11 : No request for Bank 2 Flash Sector 13 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 13 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 5-51. Z2_GRABSECT3R Register Field Descriptions (continued)

Bit Field Type Reset Description
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z2_GRABSECT3[25:24] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 12 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 12 to Zone2.
10 : No request for Bank 2 Flash Sector 12
11 : No request for Bank 2 Flash Sector 12 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 12 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z2_GRABSECT3[23:22] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 11 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 11 to Zone2.
10 : No request for Bank 2 Flash Sector 11
11 : No request for Bank 2 Flash Sector 11 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 11 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z2_GRABSECT3[21:20] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 10 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 10 to Zone2.
10 : No request for Bank 2 Flash Sector 10
11 : No request for Bank 2 Flash Sector 10 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 10 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z2_GRABSECT3[19:18] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 9 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 9 to Zone2.
10 : No request for Bank 2 Flash Sector 9
11 : No request for Bank 2 Flash Sector 9 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 9 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z2_GRABSECT3[17:16] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 8 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 8 to Zone2.
10 : No request for Bank 2 Flash Sector 8
11 : No request for Bank 2 Flash Sector 8 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 8 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z2_GRABSECT3[15:14] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 7 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 7 to Zone2.
10 : No request for Bank 2 Flash Sector 7
11 : No request for Bank 2 Flash Sector 7 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 7 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z2_GRABSECT3[13:12] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 6 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 6 to Zone2.
10 : No request for Bank 2 Flash Sector 6
11 : No request for Bank 2 Flash Sector 6 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 6 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 5-51. Z2_GRABSECT3R Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z2_GRABSECT3[11:10] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 5 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 5 to Zone2.
10 : No request for Bank 2 Flash Sector 5
11 : No request for Bank 2 Flash Sector 5 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 5 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z2_GRABSECT3[9:8] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 4 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 4 to Zone2.
10 : No request for Bank 2 Flash Sector 4
11 : No request for Bank 2 Flash Sector 4 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 4 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z2_GRABSECT3[7:6] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 3 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 3 to Zone2.
10 : No request for Bank 2 Flash Sector 3
11 : No request for Bank 2 Flash Sector 3 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 3 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z2_GRABSECT3[5:4] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 2 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 2 to Zone2.
10 : No request for Bank 2 Flash Sector 2
11 : No request for Bank 2 Flash Sector 2 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 2 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z2_GRABSECT3[3:2] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 1 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 1 to Zone2.
10 : No request for Bank 2 Flash Sector 1
11 : No request for Bank 2 Flash Sector 1 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 1 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z2_GRABSECT3[1:0] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. Bank 2 Flash Sector 0 is inaccessible.
01 : Request to allocate Bank 2 Flash Sector 0 to Zone2.
10 : No request for Bank 2 Flash Sector 0
11 : No request for Bank 2 Flash Sector 0 when this zone is
UNLOCKED. Else Bank 2 Flash Sector 0 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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5.9.3.16 Z2_GRABRAM1R Register (Offset = 20h) [Reset = 0h]

Z2_GRABRAM1R is shown in Figure 5-48 and described in Table 5-52.
Return to the Summary Table.
Zone 2 Grab RAM Status Register 1
Figure 5-48. Z2_GRABRAM1R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_RAM3 GRAB_RAM2 GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h R-0h

Table 5-52. Z2_GRABRAM1R Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z2_GRABRAM1[15:14] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. LS7 RAM is inaccessible.
01 : Request to allocate LS7 RAM to Zone2.
10 : No request for LS7 RAM
11 : No request for LS7 RAM when this zone is UNLOCKED. Else
LS7 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from Z2_GRABRAM1[13:12] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. LS6 RAM is inaccessible.
01 : Request to allocate LS6 RAM to Zone2.
10 : No request for LS6 RAM
11 : No request for LS6 RAM when this zone is UNLOCKED. Else
LS6 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from Z2_GRABRAM1[11:10] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. LS5 RAM is inaccessible.
01 : Request to allocate LS5 RAM to Zone2.
10 : No request for LS5 RAM
11 : No request for LS5 RAM when this zone is UNLOCKED. Else
LS5 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z2_GRABRAM1[9:8] when a read
is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. LS4 RAM is inaccessible.
01 : Request to allocate LS4 RAM to Zone2.
10 : No request for LS4 RAM
11 : No request for LS4 RAM when this zone is UNLOCKED. Else
LS4 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 5-52. Z2_GRABRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 GRAB_RAM3 R 0h Value in this field gets loaded from Z2_GRABRAM1[7:6] when a read
is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. LS3 RAM is inaccessible.
01 : Request to allocate LS3 RAM to Zone2.
10 : No request for LS3 RAM
11 : No request for LS3 RAM when this zone is UNLOCKED. Else
LS3 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
5-4 GRAB_RAM2 R 0h Value in this field gets loaded from Z2_GRABRAM1[5:4] when a read
is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. LS2 RAM is inaccessible.
01 : Request to allocate LS2 RAM to Zone2.
10 : No request for LS2 RAM
11 : No request for LS2 RAM when this zone is UNLOCKED. Else
LS2 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from Z2_GRABRAM1[3:2] when a read
is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. LS1 RAM is inaccessible.
01 : Request to allocate LS1 RAM to Zone2.
10 : No request for LS1 RAM
11 : No request for LS1 RAM when this zone is UNLOCKED. Else
LS1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from Z2_GRABRAM1[1:0] when a read
is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. LS0 RAM is inaccessible.
01 : Request to allocate LS0 RAM to Zone2.
10 : No request for LS0 RAM
11 : No request for LS0 RAM when this zone is UNLOCKED. Else
LS0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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5.9.3.17 Z2_EXEONLYSECT1R Register (Offset = 26h) [Reset = 0h]

Z2_EXEONLYSECT1R is shown in Figure 5-49 and described in Table 5-53.
Return to the Summary Table.
Zone 2 Execute Only Flash Status Register 1
Figure 5-49. Z2_EXEONLYSECT1R Register
31 30 29 28 27 26 25 24
EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA
NK1_SECT15 NK1_SECT14 NK1_SECT13 NK1_SECT12 NK1_SECT11 NK1_SECT10 NK1_SECT9 NK1_SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA
NK1_SECT7 NK1_SECT6 NK1_SECT5 NK1_SECT4 NK1_SECT3 NK1_SECT2 NK1_SECT1 NK1_SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA
NK0_SECT15 NK0_SECT14 NK0_SECT13 NK0_SECT12 NK0_SECT11 NK0_SECT10 NK0_SECT9 NK0_SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA
NK0_SECT7 NK0_SECT6 NK0_SECT5 NK0_SECT4 NK0_SECT3 NK0_SECT2 NK0_SECT1 NK0_SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 5-53. Z2_EXEONLYSECT1R Register Field Descriptions

Bit Field Type Reset Description
31 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[31] when a
15 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 15
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 1 Flash Sector 15
(only if it's allocated to Zone2)
Reset type: SYSRSn
30 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[30] when a
14 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 14
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 1 Flash Sector 14
(only if it's allocated to Zone2)
Reset type: SYSRSn
29 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[29] when a
13 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 13
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 1 Flash Sector 13
(only if it's allocated to Zone2)
Reset type: SYSRSn
28 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[28] when a
12 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 12
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 1 Flash Sector 12
(only if it's allocated to Zone2)
Reset type: SYSRSn

SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023 TMS320F28003x Real-Time Microcontrollers 681
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Table 5-53. Z2_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
27 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[27] when a
11 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 11
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 1 Flash Sector 11
(only if it's allocated to Zone2)
Reset type: SYSRSn
26 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[26] when a
10 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 10
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 1 Flash Sector 10
(only if it's allocated to Zone2)
Reset type: SYSRSn
25 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[25] when a
9 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 9
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 1 Flash Sector 9
(only if it's allocated to Zone2)
Reset type: SYSRSn
24 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[24] when a
8 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 8
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 1 Flash Sector 8
(only if it's allocated to Zone2)
Reset type: SYSRSn
23 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[23] when a
7 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 7
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 1 Flash Sector 7
(only if it's allocated to Zone2)
Reset type: SYSRSn
22 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[22] when a
6 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 6
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 1 Flash Sector 6
(only if it's allocated to Zone2)
Reset type: SYSRSn
21 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[21] when a
5 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 5
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 1 Flash Sector 5
(only if it's allocated to Zone2)
Reset type: SYSRSn
20 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[20] when a
4 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 4
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 1 Flash Sector 4
(only if it's allocated to Zone2)
Reset type: SYSRSn

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Table 5-53. Z2_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
19 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[19] when a
3 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 3
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 1 Flash Sector 3
(only if it's allocated to Zone2)
Reset type: SYSRSn
18 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[18] when a
2 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 2
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 1 Flash Sector 2
(only if it's allocated to Zone2)
Reset type: SYSRSn
17 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[17] when a
1 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 1
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 1 Flash Sector 1
(only if it's allocated to Zone2)
Reset type: SYSRSn
16 EXEONLY_BANK1_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[16] when a
0 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 1 Flash Sector 0
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 1 Flash Sector 0
(only if it's allocated to Zone2)
Reset type: SYSRSn
15 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[15] when a
15 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 15
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 15
(only if it's allocated to Zone2)
Reset type: SYSRSn
14 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[14] when a
14 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 14
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 14
(only if it's allocated to Zone2)
Reset type: SYSRSn
13 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[13] when a
13 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 13
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 13
(only if it's allocated to Zone2)
Reset type: SYSRSn
12 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[12] when a
12 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 12
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 12
(only if it's allocated to Zone2)
Reset type: SYSRSn

SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023 TMS320F28003x Real-Time Microcontrollers 683
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Table 5-53. Z2_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
11 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[11] when a
11 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 11
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 11
(only if it's allocated to Zone2)
Reset type: SYSRSn
10 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[10] when a
10 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 10
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 10
(only if it's allocated to Zone2)
Reset type: SYSRSn
9 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[9] when a
9 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 9
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 9
(only if it's allocated to Zone2)
Reset type: SYSRSn
8 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[8] when a
8 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 8
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 8
(only if it's allocated to Zone2)
Reset type: SYSRSn
7 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[7] when a
7 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 7
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 7
(only if it's allocated to Zone2)
Reset type: SYSRSn
6 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[6] when a
6 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 6
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 6
(only if it's allocated to Zone2)
Reset type: SYSRSn
5 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[5] when a
5 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 5
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 5
(only if it's allocated to Zone2)
Reset type: SYSRSn
4 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[4] when a
4 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 4
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 4
(only if it's allocated to Zone2)
Reset type: SYSRSn

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Table 5-53. Z2_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
3 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[3] when a
3 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 3
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 3
(only if it's allocated to Zone2)
Reset type: SYSRSn
2 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[2] when a
2 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 2
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 2
(only if it's allocated to Zone2)
Reset type: SYSRSn
1 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[1] when a
1 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 1
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 1
(only if it's allocated to Zone2)
Reset type: SYSRSn
0 EXEONLY_BANK0_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[0] when a
0 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for Bank 0 Flash Sector 0
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 0 Flash Sector 0
(only if it's allocated to Zone2)
Reset type: SYSRSn

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5.9.3.18 Z2_EXEONLYSECT2R Register (Offset = 28h) [Reset = 0h]

Z2_EXEONLYSECT2R is shown in Figure 5-50 and described in Table 5-54.
Return to the Summary Table.
Zone 2 Execute Only Flash Status Register 2
Figure 5-50. Z2_EXEONLYSECT2R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA
NK2_SECT15 NK2_SECT14 NK2_SECT13 NK2_SECT12 NK2_SECT11 NK2_SECT10 NK2_SECT9 NK2_SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA EXEONLY_BA
NK2_SECT7 NK2_SECT6 NK2_SECT5 NK2_SECT4 NK2_SECT3 NK2_SECT2 NK2_SECT1 NK2_SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 5-54. Z2_EXEONLYSECT2R Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[15] when a
15 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for Bank 2 Flash Sector 15
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 2 Flash Sector 15
(only if it's allocated to Zone2)
Reset type: SYSRSn
14 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[14] when a
14 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for Bank 2 Flash Sector 14
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 2 Flash Sector 14
(only if it's allocated to Zone2)
Reset type: SYSRSn
13 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[13] when a
13 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for Bank 2 Flash Sector 13
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 2 Flash Sector 13
(only if it's allocated to Zone2)
Reset type: SYSRSn
12 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[12] when a
12 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for Bank 2 Flash Sector 12
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 2 Flash Sector 12
(only if it's allocated to Zone2)
Reset type: SYSRSn

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Table 5-54. Z2_EXEONLYSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
11 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[11] when a
11 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for Bank 2 Flash Sector 11
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 2 Flash Sector 11
(only if it's allocated to Zone2)
Reset type: SYSRSn
10 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[10] when a
10 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for Bank 2 Flash Sector 10
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 2 Flash Sector 10
(only if it's allocated to Zone2)
Reset type: SYSRSn
9 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[9] when a
9 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for Bank 2 Flash Sector 9
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 2 Flash Sector 9
(only if it's allocated to Zone2)
Reset type: SYSRSn
8 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[8] when a
8 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for Bank 2 Flash Sector 8
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 2 Flash Sector 8
(only if it's allocated to Zone2)
Reset type: SYSRSn
7 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[7] when a
7 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for Bank 2 Flash Sector 7
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 2 Flash Sector 7
(only if it's allocated to Zone2)
Reset type: SYSRSn
6 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[6] when a
6 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for Bank 2 Flash Sector 6
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 2 Flash Sector 6
(only if it's allocated to Zone2)
Reset type: SYSRSn
5 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[5] when a
5 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for Bank 2 Flash Sector 5
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 2 Flash Sector 5
(only if it's allocated to Zone2)
Reset type: SYSRSn
4 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[4] when a
4 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for Bank 2 Flash Sector 4
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 2 Flash Sector 4
(only if it's allocated to Zone2)
Reset type: SYSRSn

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Table 5-54. Z2_EXEONLYSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
3 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[3] when a
3 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for Bank 2 Flash Sector 3
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 2 Flash Sector 3
(only if it's allocated to Zone2)
Reset type: SYSRSn
2 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[2] when a
2 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for Bank 2 Flash Sector 2
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 2 Flash Sector 2
(only if it's allocated to Zone2)
Reset type: SYSRSn
1 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[1] when a
1 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for Bank 2 Flash Sector 1
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 2 Flash Sector 1
(only if it's allocated to Zone2)
Reset type: SYSRSn
0 EXEONLY_BANK2_SECT R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[0] when a
0 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for Bank 2 Flash Sector 0
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for Bank 2 Flash Sector 0
(only if it's allocated to Zone2)
Reset type: SYSRSn

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5.9.3.19 Z2_EXEONLYRAM1R Register (Offset = 2Ah) [Reset = 0h]

Z2_EXEONLYRAM1R is shown in Figure 5-51 and described in Table 5-55.
Return to the Summary Table.
Zone 2 Execute Only RAM Status Register 1
Figure 5-51. Z2_EXEONLYRAM1R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA
M7 M6 M5 M4 M3 M2 M1 M0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 5-55. Z2_EXEONLYRAM1R Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R 0h Reserved
7 EXEONLY_RAM7 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[7] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for LS7 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS7 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
6 EXEONLY_RAM6 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[6] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for LS6 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS6 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
5 EXEONLY_RAM5 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[5] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for LS5 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS5 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
4 EXEONLY_RAM4 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[4] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for LS4 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS4 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn

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Table 5-55. Z2_EXEONLYRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
3 EXEONLY_RAM3 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[3] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for LS3 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS3 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
2 EXEONLY_RAM2 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[2] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for LS2 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS2 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
1 EXEONLY_RAM1 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[1] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for LS1 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS1 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
0 EXEONLY_RAM0 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[0] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for LS0 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for LS0 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn

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5.9.4 DCSM_COMMON_REGS Registers

Table 5-56 lists the memory-mapped registers for the DCSM_COMMON_REGS registers. All register offset
addresses not listed in Table 5-56 should be considered as reserved locations and the register contents should
not be modified.
Table 5-56. DCSM_COMMON_REGS Registers
Offset Acronym Register Name Write Protection Section
0h FLSEM Flash Wrapper Semaphore Register EALLOW Go
8h SECTSTAT1 Flash Sectors Status Register 1 Go
Ah SECTSTAT2 Flash Sectors Status Register 2 Go
Ch SECTSTAT3 Flash Sectors Status Register 3 Go
10h RAMSTAT1 RAM Status Register 1 Go
18h SECERRSTAT Security Error Status Register Go
1Ah SECERRCLR Security Error Clear Register Go
1Ch SECERRFRC Security Error Force Register Go

Complex bit access types are encoded to fit into small table cells. Table 5-57 shows the codes that are used for
access types in this section.
Table 5-57. DCSM_COMMON_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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5.9.4.1 FLSEM Register (Offset = 0h) [Reset = 0h]

FLSEM is shown in Figure 5-52 and described in Table 5-58.
Return to the Summary Table.
Flash Wrapper Semaphore Register
Figure 5-52. FLSEM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY RESERVED SEM
R-0/W-0h R-0h R/W-0h

Table 5-58. FLSEM Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 KEY R-0/W 0h Writing a value 0xA5 into this field will allow the writing of the SEM
bits, else writes are ignored. Reads will return 0.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved
1-0 SEM R/W 0h 00 : Flash Wrapper registers can be written by code running from
anywhere without any restriction.
01 : Flash Wrapper registers can be written by code running from
Zone1 security zone.
10 : Flash Wrapper registers can be written by code running from
Zone2 security zone
11 : Flash Wrapper registers can be written by code running from
anywhere without any restriction
Allowed State Transitions in this field.
00 TO 11 : Not allowed.
11 TO 00 : Not allowed.
00/11 TO 01 : Code running from Zone1 only can perform this
transition.
01 TO 00/11 : Code running from Zone1 only can perform this
transition.
00/11 TO 10 : Code running from Zone2 only can perform this
transition.
10 TO 00/11 : Code running from Zone2 can perform this transition
10 TO 01 : Not allowed.
01 TO 10 : Not allowed.
Reset type: SYSRSn

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5.9.4.2 SECTSTAT1 Register (Offset = 8h) [Reset = 0h]

SECTSTAT1 is shown in Figure 5-53 and described in Table 5-59.
Return to the Summary Table.
Flash Sectors Status Register 1
Figure 5-53. SECTSTAT1 Register
31 30 29 28 27 26 25 24
STATUS_SECT15 STATUS_SECT14 STATUS_SECT13 STATUS_SECT12
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
STATUS_SECT11 STATUS_SECT10 STATUS_SECT9 STATUS_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
STATUS_SECT7 STATUS_SECT6 STATUS_SECT5 STATUS_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
STATUS_SECT3 STATUS_SECT2 STATUS_SECT1 STATUS_SECT0
R-0h R-0h R-0h R-0h

Table 5-59. SECTSTAT1 Register Field Descriptions

Bit Field Type Reset Description
31-30 STATUS_SECT15 R 0h Reflects the status of flash Bank 0 Sector 15.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
29-28 STATUS_SECT14 R 0h Reflects the status of flash Bank 0 Sector 14.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
27-26 STATUS_SECT13 R 0h Reflects the status of flash Bank 0 Sector 13.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
25-24 STATUS_SECT12 R 0h Reflects the status of flash Bank 0 Sector 12.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
23-22 STATUS_SECT11 R 0h Reflects the status of flash Bank 0 Sector 11.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 5-59. SECTSTAT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
21-20 STATUS_SECT10 R 0h Reflects the status of flash Bank 0 Sector 10.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
19-18 STATUS_SECT9 R 0h Reflects the status of flash Bank 0 Sector 9.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
17-16 STATUS_SECT8 R 0h Reflects the status of flash Bank 0 sector 8.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_SECT7 R 0h Reflects the status of flash Bank 0 Sector 7.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_SECT6 R 0h Reflects the status of flash Bank 0 Sector 6.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_SECT5 R 0h Reflects the status of flash Bank 0 Sector 5.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_SECT4 R 0h Reflects the status of flash Bank 0 Sector 4.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_SECT3 R 0h Reflects the status of flash Bank 0 Sector 3.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 5-59. SECTSTAT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
5-4 STATUS_SECT2 R 0h Reflects the status of flash Bank 0 Sector 2.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
3-2 STATUS_SECT1 R 0h Reflects the status of flash Bank 0 sector 1.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_SECT0 R 0h Reflects the status of flash Bank 0 Sector 0.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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5.9.4.3 SECTSTAT2 Register (Offset = Ah) [Reset = 0h]

SECTSTAT2 is shown in Figure 5-54 and described in Table 5-60.
Return to the Summary Table.
Flash Sectors Status Register 2
Figure 5-54. SECTSTAT2 Register
31 30 29 28 27 26 25 24
STATUS_SECT15 STATUS_SECT14 STATUS_SECT13 STATUS_SECT12
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
STATUS_SECT11 STATUS_SECT10 STATUS_SECT9 STATUS_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
STATUS_SECT7 STATUS_SECT6 STATUS_SECT5 STATUS_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
STATUS_SECT3 STATUS_SECT2 STATUS_SECT1 STATUS_SECT0
R-0h R-0h R-0h R-0h

Table 5-60. SECTSTAT2 Register Field Descriptions

Bit Field Type Reset Description
31-30 STATUS_SECT15 R 0h Reflects the status of flash Bank 1 Sector 15.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
29-28 STATUS_SECT14 R 0h Reflects the status of flash Bank 1 Sector 14.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
27-26 STATUS_SECT13 R 0h Reflects the status of flash Bank 1 Sector 13.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
25-24 STATUS_SECT12 R 0h Reflects the status of flash Bank 1 Sector 12.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
23-22 STATUS_SECT11 R 0h Reflects the status of flash Bank 1 Sector 11.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 5-60. SECTSTAT2 Register Field Descriptions (continued)

Bit Field Type Reset Description
21-20 STATUS_SECT10 R 0h Reflects the status of flash Bank 1 Sector 10.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
19-18 STATUS_SECT9 R 0h Reflects the status of flash Bank 1 Sector 9.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
17-16 STATUS_SECT8 R 0h Reflects the status of flash Bank 1 sector 8.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_SECT7 R 0h Reflects the status of flash Bank 1 Sector 7.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_SECT6 R 0h Reflects the status of flash Bank 1 Sector 6.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_SECT5 R 0h Reflects the status of flash Bank 1 Sector 5.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_SECT4 R 0h Reflects the status of flash Bank 1 Sector 4.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_SECT3 R 0h Reflects the status of flash Bank 1 Sector 3.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 5-60. SECTSTAT2 Register Field Descriptions (continued)

Bit Field Type Reset Description
5-4 STATUS_SECT2 R 0h Reflects the status of flash Bank 1 Sector 2.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
3-2 STATUS_SECT1 R 0h Reflects the status of flash Bank 1 sector 1.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_SECT0 R 0h Reflects the status of flash Bank 1 Sector 0.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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5.9.4.4 SECTSTAT3 Register (Offset = Ch) [Reset = 0h]

SECTSTAT3 is shown in Figure 5-55 and described in Table 5-61.
Return to the Summary Table.
Flash Sectors Status Register 3
Figure 5-55. SECTSTAT3 Register
31 30 29 28 27 26 25 24
STATUS_SECT15 STATUS_SECT14 STATUS_SECT13 STATUS_SECT12
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
STATUS_SECT11 STATUS_SECT10 STATUS_SECT9 STATUS_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
STATUS_SECT7 STATUS_SECT6 STATUS_SECT5 STATUS_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
STATUS_SECT3 STATUS_SECT2 STATUS_SECT1 STATUS_SECT0
R-0h R-0h R-0h R-0h

Table 5-61. SECTSTAT3 Register Field Descriptions

Bit Field Type Reset Description
31-30 STATUS_SECT15 R 0h Reflects the status of flash Bank 2 Sector 15.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
29-28 STATUS_SECT14 R 0h Reflects the status of flash Bank 2 Sector 14.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
27-26 STATUS_SECT13 R 0h Reflects the status of flash Bank 2 Sector 13.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
25-24 STATUS_SECT12 R 0h Reflects the status of flash Bank 2 Sector 12.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
23-22 STATUS_SECT11 R 0h Reflects the status of flash Bank 2 Sector 11.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 5-61. SECTSTAT3 Register Field Descriptions (continued)

Bit Field Type Reset Description
21-20 STATUS_SECT10 R 0h Reflects the status of flash Bank 2 Sector 10.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
19-18 STATUS_SECT9 R 0h Reflects the status of flash Bank 2 Sector 9.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
17-16 STATUS_SECT8 R 0h Reflects the status of flash Bank 2 sector 8.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_SECT7 R 0h Reflects the status of flash Bank 2 Sector 7.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_SECT6 R 0h Reflects the status of flash Bank 2 Sector 6.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_SECT5 R 0h Reflects the status of flash Bank 2 Sector 5.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_SECT4 R 0h Reflects the status of flash Bank 2 Sector 4.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_SECT3 R 0h Reflects the status of flash Bank 2 Sector 3.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 5-61. SECTSTAT3 Register Field Descriptions (continued)

Bit Field Type Reset Description
5-4 STATUS_SECT2 R 0h Reflects the status of flash Bank 2 Sector 2.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
3-2 STATUS_SECT1 R 0h Reflects the status of flash Bank 2 sector 1.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_SECT0 R 0h Reflects the status of flash Bank 2 Sector 0.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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5.9.4.5 RAMSTAT1 Register (Offset = 10h) [Reset = 0h]

RAMSTAT1 is shown in Figure 5-56 and described in Table 5-62.
Return to the Summary Table.
RAM Status Register 1
Figure 5-56. RAMSTAT1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
STATUS_RAM7 STATUS_RAM6 STATUS_RAM5 STATUS_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
STATUS_RAM3 STATUS_RAM2 STATUS_RAM1 STATUS_RAM0
R-0h R-0h R-0h R-0h

Table 5-62. RAMSTAT1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-14 STATUS_RAM7 R 0h Reflects the status of LS7 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_RAM6 R 0h Reflects the status of LS6 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_RAM5 R 0h Reflects the status of LS5 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_RAM4 R 0h Reflects the status of LS4 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 5-62. RAMSTAT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 STATUS_RAM3 R 0h Reflects the status of LS3 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_RAM2 R 0h Reflects the status of LS2 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
3-2 STATUS_RAM1 R 0h Reflects the status of LS1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_RAM0 R 0h Reflects the status of LS0 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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5.9.4.6 SECERRSTAT Register (Offset = 18h) [Reset = 0h]

SECERRSTAT is shown in Figure 5-57 and described in Table 5-63.
Return to the Summary Table.
Security Error Status Register
Figure 5-57. SECERRSTAT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR
R-0h R-0h

Table 5-63. SECERRSTAT Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 ERR R 0h This bit indicates if any error has occurred in the load of any security
configuration from USER-OTP.
0: No error has occurred in the load of security information from
USER-OTP
1: Error has occurred in the load of security information from USER-
OTP
Reset type: PORESETn

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5.9.4.7 SECERRCLR Register (Offset = 1Ah) [Reset = 0h]

SECERRCLR is shown in Figure 5-58 and described in Table 5-64.
Return to the Summary Table.
Security Error Clear Register
Figure 5-58. SECERRCLR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR
R-0h R-0/
W1S-0
h

Table 5-64. SECERRCLR Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 ERR R-0/W1S 0h A write of '1' clears the SECERRSTST.ERR bit. Write of '0' is
ignored. This bit always reads back '0'.
Reset type: N/A

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5.9.4.8 SECERRFRC Register (Offset = 1Ch) [Reset = 0h]

SECERRFRC is shown in Figure 5-59 and described in Table 5-65.
Return to the Summary Table.
Security Error Force Register
Figure 5-59. SECERRFRC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR
R-0h R-0/
W1S-0
h

Table 5-65. SECERRFRC Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h In order to write to the ERR bits, 0x5a5a must be written to these
key bits at the same time. Otherwise, writes are ignored. The key
is cleared immediately after writing, so it must be written again for
every write to ERR. Reads will return 0.
Reset type: N/A
15-1 RESERVED R 0h Reserved
0 ERR R-0/W1S 0h A write of '1', along with the proper KEY, sets the
SECERRSTST.ERR bit. Write of '0' is ignored. This bit always reads
back '0'.
Reset type: N/A

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5.9.5 DCSM_Z1_OTP Registers

Table 5-66 lists the memory-mapped registers for the DCSM_Z1_OTP registers. All register offset addresses not
listed in Table 5-66 should be considered as reserved locations and the register contents should not be modified.
Table 5-66. DCSM_Z1_OTP Registers
Offset Acronym Register Name Write Protection Section
0h Z1OTP_LINKPOINTER1 Zone 1 Link Pointer1 Go
2h Z1OTP_LINKPOINTER2 Zone 1 Link Pointer2 Go
4h Z1OTP_LINKPOINTER3 Zone 1 Link Pointer3 Go
6h Z1OTP_JLM_ENABLE Zone 1 JTAGLOCK Enable Register Go
8h Z1OTP_GPREG1 Zone 1 General Purpose Register 1 Go
Ah Z1OTP_GPREG2 Zone 1 General Purpose Register 2 Go
Ch Z1OTP_GPREG3 Zone 1 General Purpose Register 3 Go
Eh Z1OTP_GPREG4 Zone 1 General Purpose Register 4 Go
10h Z1OTP_PSWDLOCK Secure Password Lock Go
12h Z1OTP_CRCLOCK Secure CRC Lock Go
14h Z1OTP_JTAGPSWDH0 JTAG Lock Permanent Password 0 Go
16h Z1OTP_JTAGPSWDH1 JTAG Lock Permanent Password 1 Go
18h Z1OTP_CMACKEY0 Secure Boot CMAC Key 0 Go
1Ah Z1OTP_CMACKEY1 Secure Boot CMAC Key 1 Go
1Ch Z1OTP_CMACKEY2 Secure Boot CMAC Key 2 Go
1Eh Z1OTP_CMACKEY3 Secure Boot CMAC Key 3 Go

Complex bit access types are encoded to fit into small table cells. Table 5-67 shows the codes that are used for
access types in this section.
Table 5-67. DCSM_Z1_OTP Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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5.9.5.1 Z1OTP_LINKPOINTER1 Register (Offset = 0h) [Reset = FFFFFFFFh]

Z1OTP_LINKPOINTER1 is shown in Figure 5-60 and described in Table 5-68.
Return to the Summary Table.
Zone 1 Link Pointer1
Figure 5-60. Z1OTP_LINKPOINTER1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER1
R-FFFFFFFFh

Table 5-68. Z1OTP_LINKPOINTER1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_LINKPOINTER1 R FFFFFFFFh Zone1 Link Pointer 1 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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5.9.5.2 Z1OTP_LINKPOINTER2 Register (Offset = 2h) [Reset = FFFFFFFFh]

Z1OTP_LINKPOINTER2 is shown in Figure 5-61 and described in Table 5-69.
Return to the Summary Table.
Zone 1 Link Pointer2
Figure 5-61. Z1OTP_LINKPOINTER2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER2
R-FFFFFFFFh

Table 5-69. Z1OTP_LINKPOINTER2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_LINKPOINTER2 R FFFFFFFFh Zone1 Link Pointer 2 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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5.9.5.3 Z1OTP_LINKPOINTER3 Register (Offset = 4h) [Reset = FFFFFFFFh]

Z1OTP_LINKPOINTER3 is shown in Figure 5-62 and described in Table 5-70.
Return to the Summary Table.
Zone 1 Link Pointer3
Figure 5-62. Z1OTP_LINKPOINTER3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER3
R-FFFFFFFFh

Table 5-70. Z1OTP_LINKPOINTER3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_LINKPOINTER3 R FFFFFFFFh Zone1 Link Pointer 3 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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5.9.5.4 Z1OTP_JLM_ENABLE Register (Offset = 6h) [Reset = FFFFFFFFh]

Z1OTP_JLM_ENABLE is shown in Figure 5-63 and described in Table 5-71.
Return to the Summary Table.
Zone 1 JTAGLOCK Enable Register
Figure 5-63. Z1OTP_JLM_ENABLE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_JLM_ENABLE
R-FFFFFFFFh

Table 5-71. Z1OTP_JLM_ENABLE Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_JLM_ENABLE R FFFFFFFFh Zone1 JLM_ENABLE register location in USER OTP.
Note: When this value is loaded into Z1_JLM_ENABLE, if the value
is 32-bit all-1s, the JTAGLOCK will be enabled. Before shipping parts
to customers, TI will program the default value to 0xFFFF_000F,
which will disable the JTAGLOCK feature. Users should program
0xFFFF_0000 to enable the JTAGLOCK feature.
Reset type: N/A

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5.9.5.5 Z1OTP_GPREG1 Register (Offset = 8h) [Reset = FFFFFFFFh]

Z1OTP_GPREG1 is shown in Figure 5-64 and described in Table 5-72.
Return to the Summary Table.
Zone 1 General Purpose Register 1
Figure 5-64. Z1OTP_GPREG1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_GPREG1
R-FFFFFFFFh

Table 5-72. Z1OTP_GPREG1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_GPREG1 R FFFFFFFFh Zone1 General Purpose register location in USER OTP.
Reset type: N/A

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5.9.5.6 Z1OTP_GPREG2 Register (Offset = Ah) [Reset = FFFFFFFFh]

Z1OTP_GPREG2 is shown in Figure 5-65 and described in Table 5-73.
Return to the Summary Table.
Zone 1 General Purpose Register 2
Figure 5-65. Z1OTP_GPREG2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_GPREG2
R-FFFFFFFFh

Table 5-73. Z1OTP_GPREG2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_GPREG2 R FFFFFFFFh Zone1 General Purpose register location in USER OTP.
Reset type: N/A

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5.9.5.7 Z1OTP_GPREG3 Register (Offset = Ch) [Reset = FFFFFFFFh]

Z1OTP_GPREG3 is shown in Figure 5-66 and described in Table 5-74.
Return to the Summary Table.
Zone 1 General Purpose Register 3
Figure 5-66. Z1OTP_GPREG3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_GPREG3
R-FFFFFFFFh

Table 5-74. Z1OTP_GPREG3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_GPREG3 R FFFFFFFFh Zone1 General Purpose register location in USER OTP.
Reset type: N/A

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5.9.5.8 Z1OTP_GPREG4 Register (Offset = Eh) [Reset = FFFFFFFFh]

Z1OTP_GPREG4 is shown in Figure 5-67 and described in Table 5-75.
Return to the Summary Table.
Zone 1 General Purpose Register 4
Figure 5-67. Z1OTP_GPREG4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_GPREG4
R-FFFFFFFFh

Table 5-75. Z1OTP_GPREG4 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_GPREG4 R FFFFFFFFh Zone1 General Purpose register location in USER OTP.
Reset type: N/A

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5.9.5.9 Z1OTP_PSWDLOCK Register (Offset = 10h) [Reset = FFFFFFFFh]

Z1OTP_PSWDLOCK is shown in Figure 5-68 and described in Table 5-76.
Return to the Summary Table.
Secure Password Lock
Figure 5-68. Z1OTP_PSWDLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_PSWDLOCK
R-FFFFFFFFh

Table 5-76. Z1OTP_PSWDLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_PSWDLOCK R FFFFFFFFh Zone1 password lock location in USER OTP.
Note: When this value is loaded into DCSM, if the value is 32-
bit all-1s, CSMPSWD will remain locked. Before shipping parts to
customers, TI would change the value of this location in such a way
that the ECC field remains all-1s and also LSB 4-bits remain 4'b1111.
Reset type: N/A

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5.9.5.10 Z1OTP_CRCLOCK Register (Offset = 12h) [Reset = FFFFFFFFh]

Z1OTP_CRCLOCK is shown in Figure 5-69 and described in Table 5-77.
Return to the Summary Table.
Secure CRC Lock
Figure 5-69. Z1OTP_CRCLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_CRCLOCK
R-FFFFFFFFh

Table 5-77. Z1OTP_CRCLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_CRCLOCK R FFFFFFFFh Zone1 CRC lock location in USER OTP.
Note: When this value is loaded into DCSM, if the value is 32-bit
all-1s, VCU will not have ability to calculate CRC on secured memory
content.. Before shipping parts to customers, TI would change the
value of this location in such a way that the ECC field remains all-1s
and also LSB 4-bits remain 4'b1111.
Reset type: N/A

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5.9.5.11 Z1OTP_JTAGPSWDH0 Register (Offset = 14h) [Reset = FFFFFFFFh]

Z1OTP_JTAGPSWDH0 is shown in Figure 5-70 and described in Table 5-78.
Return to the Summary Table.
JTAG Lock Permanent Password 0
Figure 5-70. Z1OTP_JTAGPSWDH0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JTAGPSWDH0
R-FFFFFFFFh

Table 5-78. Z1OTP_JTAGPSWDH0 Register Field Descriptions

Bit Field Type Reset Description
31-0 JTAGPSWDH0 R FFFFFFFFh JTAG Lock Password High 0 (bits 95:64) location in USER Z1 OTP.
This value is dummy loaded into the non-memory-mapped
JTAGPSWD register, bits 95:64.
TI must program a default value into this location, leaving the ECC
bits all 1's.
Reset type: N/A

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5.9.5.12 Z1OTP_JTAGPSWDH1 Register (Offset = 16h) [Reset = FFFFFFFFh]

Z1OTP_JTAGPSWDH1 is shown in Figure 5-71 and described in Table 5-79.
Return to the Summary Table.
JTAG Lock Permanent Password 1
Figure 5-71. Z1OTP_JTAGPSWDH1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JTAGPSWDH1
R-FFFFFFFFh

Table 5-79. Z1OTP_JTAGPSWDH1 Register Field Descriptions

Bit Field Type Reset Description
31-0 JTAGPSWDH1 R FFFFFFFFh JTAG Lock Password High 1 (bits 127:96) location in USER Z1 OTP.
This value is dummy loaded into the non-memory-mapped
JTAGPSWD register, bits 127:96.
Reset type: N/A

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5.9.5.13 Z1OTP_CMACKEY0 Register (Offset = 18h) [Reset = FFFFFFFFh]

Z1OTP_CMACKEY0 is shown in Figure 5-72 and described in Table 5-80.
Return to the Summary Table.
Secure Boot CMAC Key 0
Figure 5-72. Z1OTP_CMACKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMACKEY0
R-FFFFFFFFh

Table 5-80. Z1OTP_CMACKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 CMACKEY0 R FFFFFFFFh Secure Boot CMAC Key 0 (bits 31:0) location in User Z1 OTP.
This value is dummy loaded into the CMACKEY0 register.
Reset type: N/A

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5.9.5.14 Z1OTP_CMACKEY1 Register (Offset = 1Ah) [Reset = FFFFFFFFh]

Z1OTP_CMACKEY1 is shown in Figure 5-73 and described in Table 5-81.
Return to the Summary Table.
Secure Boot CMAC Key 1
Figure 5-73. Z1OTP_CMACKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMACKEY1
R-FFFFFFFFh

Table 5-81. Z1OTP_CMACKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 CMACKEY1 R FFFFFFFFh Secure Boot CMAC Key 1 (bits 63:32) location in User Z1 OTP.
This value is dummy loaded into the CMACKEY1 register.
Reset type: N/A

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5.9.5.15 Z1OTP_CMACKEY2 Register (Offset = 1Ch) [Reset = FFFFFFFFh]

Z1OTP_CMACKEY2 is shown in Figure 5-74 and described in Table 5-82.
Return to the Summary Table.
Secure Boot CMAC Key 2
Figure 5-74. Z1OTP_CMACKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMACKEY2
R-FFFFFFFFh

Table 5-82. Z1OTP_CMACKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 CMACKEY2 R FFFFFFFFh Secure Boot CMAC Key 2 (bits 95:64) location in User Z1 OTP.
This value is dummy loaded into the CMACKEY2 register.
Reset type: N/A

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5.9.5.16 Z1OTP_CMACKEY3 Register (Offset = 1Eh) [Reset = FFFFFFFFh]

Z1OTP_CMACKEY3 is shown in Figure 5-75 and described in Table 5-83.
Return to the Summary Table.
Secure Boot CMAC Key 3
Figure 5-75. Z1OTP_CMACKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMACKEY3
R-FFFFFFFFh

Table 5-83. Z1OTP_CMACKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 CMACKEY3 R FFFFFFFFh Secure Boot CMAC Key 3 (bits 127:96) location in User Z1 OTP.
This value is dummy loaded into the CMACKEY3 register.
Reset type: N/A

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5.9.6 DCSM_Z2_OTP Registers

Table 5-84 lists the memory-mapped registers for the DCSM_Z2_OTP registers. All register offset addresses not
listed in Table 5-84 should be considered as reserved locations and the register contents should not be modified.
Table 5-84. DCSM_Z2_OTP Registers
Offset Acronym Register Name Write Protection Section
0h Z2OTP_LINKPOINTER1 Zone 2 Link Pointer1 Go
2h Z2OTP_LINKPOINTER2 Zone 2 Link Pointer2 Go
4h Z2OTP_LINKPOINTER3 Zone 2 Link Pointer3 Go
8h Z2OTP_GPREG1 Zone 2 General Purpose Register 1 Go
Ah Z2OTP_GPREG2 Zone 2 General Purpose Register 2 Go
Ch Z2OTP_GPREG3 Zone 2 General Purpose Register 3 Go
Eh Z2OTP_GPREG4 Zone 2 General Purpose Register 4 Go
10h Z2OTP_PSWDLOCK Secure Password Lock Go
12h Z2OTP_CRCLOCK Secure CRC Lock Go

Complex bit access types are encoded to fit into small table cells. Table 5-85 shows the codes that are used for
access types in this section.
Table 5-85. DCSM_Z2_OTP Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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5.9.6.1 Z2OTP_LINKPOINTER1 Register (Offset = 0h) [Reset = FFFFFFFFh]

Z2OTP_LINKPOINTER1 is shown in Figure 5-76 and described in Table 5-86.
Return to the Summary Table.
Zone 2 Link Pointer1
Figure 5-76. Z2OTP_LINKPOINTER1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER1
R-FFFFFFFFh

Table 5-86. Z2OTP_LINKPOINTER1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_LINKPOINTER1 R FFFFFFFFh Zone2 Link Pointer 1 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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5.9.6.2 Z2OTP_LINKPOINTER2 Register (Offset = 2h) [Reset = FFFFFFFFh]

Z2OTP_LINKPOINTER2 is shown in Figure 5-77 and described in Table 5-87.
Return to the Summary Table.
Zone 2 Link Pointer2
Figure 5-77. Z2OTP_LINKPOINTER2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER2
R-FFFFFFFFh

Table 5-87. Z2OTP_LINKPOINTER2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_LINKPOINTER2 R FFFFFFFFh Zone2 Link Pointer 2 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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5.9.6.3 Z2OTP_LINKPOINTER3 Register (Offset = 4h) [Reset = FFFFFFFFh]

Z2OTP_LINKPOINTER3 is shown in Figure 5-78 and described in Table 5-88.
Return to the Summary Table.
Zone 2 Link Pointer3
Figure 5-78. Z2OTP_LINKPOINTER3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER3
R-FFFFFFFFh

Table 5-88. Z2OTP_LINKPOINTER3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_LINKPOINTER3 R FFFFFFFFh Zone2 Link Pointer 3 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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5.9.6.4 Z2OTP_GPREG1 Register (Offset = 8h) [Reset = FFFFFFFFh]

Z2OTP_GPREG1 is shown in Figure 5-79 and described in Table 5-89.
Return to the Summary Table.
Zone 2 General Purpose Register 1
Figure 5-79. Z2OTP_GPREG1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_GPREG1
R-FFFFFFFFh

Table 5-89. Z2OTP_GPREG1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_GPREG1 R FFFFFFFFh Zone2 General Purpose register location in USER OTP.
Reset type: N/A

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5.9.6.5 Z2OTP_GPREG2 Register (Offset = Ah) [Reset = FFFFFFFFh]

Z2OTP_GPREG2 is shown in Figure 5-80 and described in Table 5-90.
Return to the Summary Table.
Zone 2 General Purpose Register 2
Figure 5-80. Z2OTP_GPREG2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_GPREG2
R-FFFFFFFFh

Table 5-90. Z2OTP_GPREG2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_GPREG2 R FFFFFFFFh Zone2 General Purpose register location in USER OTP.
Reset type: N/A

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5.9.6.6 Z2OTP_GPREG3 Register (Offset = Ch) [Reset = FFFFFFFFh]

Z2OTP_GPREG3 is shown in Figure 5-81 and described in Table 5-91.
Return to the Summary Table.
Zone 2 General Purpose Register 3
Figure 5-81. Z2OTP_GPREG3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_GPREG3
R-FFFFFFFFh

Table 5-91. Z2OTP_GPREG3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_GPREG3 R FFFFFFFFh Zone2 General Purpose register location in USER OTP.
Reset type: N/A

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5.9.6.7 Z2OTP_GPREG4 Register (Offset = Eh) [Reset = FFFFFFFFh]

Z2OTP_GPREG4 is shown in Figure 5-82 and described in Table 5-92.
Return to the Summary Table.
Zone 2 General Purpose Register 4
Figure 5-82. Z2OTP_GPREG4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_GPREG4
R-FFFFFFFFh

Table 5-92. Z2OTP_GPREG4 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_GPREG4 R FFFFFFFFh Zone2 General Purpose register location in USER OTP.
Reset type: N/A

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5.9.6.8 Z2OTP_PSWDLOCK Register (Offset = 10h) [Reset = FFFFFFFFh]

Z2OTP_PSWDLOCK is shown in Figure 5-83 and described in Table 5-93.
Return to the Summary Table.
Secure Password Lock
Figure 5-83. Z2OTP_PSWDLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_PSWDLOCK
R-FFFFFFFFh

Table 5-93. Z2OTP_PSWDLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_PSWDLOCK R FFFFFFFFh Zone2 password lock location in USER OTP.
Note: When this value is loaded into DCSM, if the value is 32-
bit all-1s, CSMPSWD will remain locked. Before shipping parts to
customers, TI would change the value of this location in such a way
that the ECC field remains all-1s and also LSB 4-bits remain 4'b1111.
Reset type: N/A

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5.9.6.9 Z2OTP_CRCLOCK Register (Offset = 12h) [Reset = FFFFFFFFh]

Z2OTP_CRCLOCK is shown in Figure 5-84 and described in Table 5-94.
Return to the Summary Table.
Secure CRC Lock
Figure 5-84. Z2OTP_CRCLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_CRCLOCK
R-FFFFFFFFh

Table 5-94. Z2OTP_CRCLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_CRCLOCK R FFFFFFFFh Zone2 CRC lock location in USER OTP.
Note: When this value is loaded into DCSM, if the value is 32-bit
all-1s, VCU will not have ability to calculate CRC on secured memory
content.. Before shipping parts to customers, TI would change the
value of this location in such a way that the ECC field remains all-1s
and also LSB 4-bits remain 4'b1111.
Reset type: N/A

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Chapter 6
Flash Module

This chapter describes the Flash module.

6.1 Introduction to Flash and OTP Memory................................................................................................................. 736

6.2 Flash Bank, OTP, and Pump.................................................................................................................................... 737
6.3 Flash Module Controller (FMC)............................................................................................................................... 738
6.4 Flash and OTP Power-Down Modes and Wakeup................................................................................................. 738
6.5 Active Grace Period................................................................................................................................................. 740
6.6 Flash and OTP Performance................................................................................................................................... 740
6.7 Flash Read Interface................................................................................................................................................ 741
6.8 Flash Erase and Program........................................................................................................................................ 743
6.9 Error Correction Code (ECC) Protection................................................................................................................744
6.10 Reserved Locations Within Flash and OTP......................................................................................................... 748
6.11 Migrating an Application from RAM to Flash.......................................................................................................748
6.12 Procedure to Change the Flash Control Registers............................................................................................. 749
6.13 Software.................................................................................................................................................................. 750
6.14 Flash Registers.......................................................................................................................................................752

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6.1 Introduction to Flash and OTP Memory

Flash is an electrically erasable/programmable nonvolatile memory that can be programmed and erased many
times to ease code development. Flash memory can be used primarily as a program memory for the core, and
secondarily as static data memory.
This section describes the proper sequence to configure the wait states and operating mode of Flash. It also
includes information on Flash and OTP power modes, how to improve Flash performance by enabling the Flash
prefetch/cache mode, and the SECDED safety feature.
6.1.1 FLASH Related Collateral

Foundational Materials
• C2000 Academy - FLASH
• Embedded Flash Memory (Video)

Getting Started Materials

• [FAQ] FAQ for Flash ECC usage in C2000 devices - Includes ECC test mode, Linker ECC options:
• [FAQ] FAQ on Flash API usage for C2000 devices
• [FAQ] Flash - How to modify an application from RAM configuration to Flash configuration?
• [FAQ] How can we improve the Flash tool performance?
• [FAQ] TI C2000 Device Programming Tools and Services
6.1.2 Features
Features of Flash memory include:
• Three Flash banks (Bank0, 1, 2) (refer to the device data sheet for the size of the Flash bank)
• 128 bits (bank width) can be programmed at a time along with ECC
• Multiple sectors providing the option of leaving some sectors programmed and only erasing specific sectors
• User-programmable OTP locations (in user-configurable DCSM OTP, also called USER OTP) for configuring
security, OTP boot-mode and boot-mode select pins (if the user is unable to use the factory-default boot-
mode select pins)
• Flash pump shared by the two banks
• Enhanced performance using the code prefetch mechanism and data cache in FMC
• Configurable wait states to give the best performance for a given execution speed
• Safety Features:
– SECDED - single-error correction and double-error detection is supported in the FMC
– Address bits are included in ECC
– Test mode to check the health of ECC logic
• Supports low-power modes for Flash bank and pump for power savings
• Built-in power mode control logic
• Integrated Flash program/erase state machine (FSM) in the FMC
– Simple Flash API algorithms
– Fast erase and program times (refer to the device data sheet for details)
• Dual Code Security Module (DCSM) to prevents access to the Flash by unauthorized persons (refer to the
Dual Code Security Module (DCSM) chapter for details)

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6.1.3 Flash Tools

Texas Instruments provides the following tools for Flash:
• Code Composer Studio™ (CCS) IDE - the development environment with integrated Flash plugin. TI
recommends performing a debug reset and restart after programming the code into Flash using CCS.
• Flash API Library - a set of software peripheral functions to erase/program Flash
• UniFlash - standalone tool to erase/program/verify the Flash content through JTAG. No CCS is required.
• Users must check and install available updates for CCS On-Chip Flash Plugin and UniFlash tools.

6.1.4 Default Flash Configuration

The following are Flash module configuration settings at power-up:
• Dedicated Flash banks are in sleep mode (BNKPWR bit field in the FBFALLBAC register)
• Shared pump is in sleep mode (PMPPWR bit field in the FPAC1 register)
• ECC is enabled
• Wait-states are set to the maximum (0xF)
• Code-prefetch mechanism and data cache are disabled in all three FMCs
• Bank and pump active grace periods are set to 0x0 (refer to the BAGP field in the FBAC register and PAGP
bit field in the FPAC2 register)
Note that boot ROM changes the BNKPWR and PMPPWR bit fields to active mode.
User application software must initialize wait-states using the FRDCNTL register, and configure cache/prefetch
features using the FRD_INTF_CTRL register, to achieve optimum system performance. Software that configures
Flash settings like wait-states, cache/prefetch features, and so on, must be executed only from RAM memory,
not from Flash memory.

Note
Before initializing wait-states, turn off the prefetch and data caching in the FRD_INTF_CTRL register.

6.2 Flash Bank, OTP, and Pump

There is a dedicated Flash bank for CPU subsystem. Also, there is a one-time programmable (OTP) memory
called USER OTP, which the user can program only once and cannot erase. Flash and OTP are uniformly
mapped in both program and data memory space.
The CPU subsystem has a TI-OTP that contains manufacturing information like settings used by the Flash
state machine for erase and program operations, and so on. Users can read TI-OTP but TI-OTP cannot be
programmed or erased. For memory maps and size information for the Flash Banks, TI-OTP, USER OTP, and
corresponding ECC locations, refer to the device data sheet.
Figure 5-2 shows the user-programmable OTP locations in USER-OTP. For more information on the functionality
of these fields, refer to the Dual Code Security Module (DCSM) and the ROM Code and Peripheral Booting
chapters.

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6.3 Flash Module Controller (FMC)

The CPU interfaces with the FMC, which in turn interfaces with the Flash bank and the pump, to perform erase
or program operations, to read data, and execute code from the Flash bank.

Bank0

CPU System Clock

CPU FMC PUMP

Bank1 Bank2

Figure 6-1. FMC Interface with Core, Bank, and Pump

6.4 Flash and OTP Power-Down Modes and Wakeup

The Flash bank and pump consume a significant amount of power when active. The Flash module provides a
mechanism to power-down Flash banks and pump. Special timers automatically sequence the power-up of the
CPU Flash bank. The charge pump module includes an independent power-up timer as well.
The Flash bank and OTP operate in three power modes: Sleep (lowest power), Standby, and Active (highest
power)
• Sleep State
This is the state after a device reset. In this state, a CPU data read or opcode fetch automatically initiates
a change in power mode to the standby state and then to the active state. During this transition time to the
active state, the CPU execution is automatically stalled.
• Standby State
This state uses more power than the sleep state, but takes a shorter time to transition to the active or read
state. In this state, a CPU data read or opcode fetch automatically initiates a change in power mode to the
active state. During this transition time to the active state, the CPU execution is automatically stalled. Once
the Flash/OTP has reached the active state, the CPU access completes as normal.
• Active or Read State
In this state, the bank and pump are in active power mode state (highest power)
The charge pump operates in two power modes:
• Sleep (lowest power)
• Active (highest power)
Any access to any Flash bank/OTP causes the charge pump to go into active mode, if in sleep mode. An
erase or program command causes the charge pump and bank to become active. If any bank is in active or in
standby mode, the charge pump is in active mode, independent of the pump power mode control configuration
(PMPPWR bit field in the FPAC1 register). While the pump is in sleep state, a charge pump sleep down counter
holds a user-configurable value (PSLEEP bit field in the FPAC1 register) and when the charge pump exits sleep

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power mode, the down counter delays from 0 to PSLEEP prescaled SYSCLK clock cycles (prescaled clock is
SYSCLK/2) before putting the charge pump into active power mode.
Following are the numbers of cycles for the bank and pump to wake up from low-power modes.
1. Pump sleep to active = PSLEEP * (SYSCLK/2) cycles
2. Bank sleep to standby = 254 Flash clock cycles
3. Bank standby to active = 55 Flash clock cycles
Where: Flash clock = SYSCLK/(RWAIT+1)

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6.5 Active Grace Period

The active grace period (AGP) can be used to optimize the Flash module power consumption versus access
time. Faster access times are associated with higher-power modes of operation. At one extreme, the power
control logic can attempt to reduce power consumption by putting the bank and charge pump into a low-power
mode immediately at the end of every Flash access. However, if accesses are only a few cycles apart, this can
actually increase power consumption versus leaving the Flash powered, because the bank and charge pump
consume more power during Flash startup and access.
The active grace periods allows the bank and charge pump to be maintained in active mode for a specified
period following an access. This is done in anticipation of another read within the AGP time, to allow the
subsequent read to have a faster access and spend less time dissipating power, than if the bank went into one of
the low-power modes immediately. If the next access does not occur within the AGP time, the power control logic
can automatically put the bank and charge pump into a low-power mode to reduce power consumption during
long periods of inactivity.
The AGP value is programmed by a set of programmable counters (FBAC and FPAC2) that keep the Flash
bank or charge pump in active mode until the counter expires, at which time the bank or charge pump reverts
to the fallback power mode as defined in the FBFALLBACK and FPAC1 (refer to PMPPWR bit-field) registers.
The application software can configure the fallback power mode to reduce power consumption, or configure the
power mode to be active mode to keep the bank active regardless of counter settings (default is SLEEP). The
charge pump AGP counter remains in the initialized state when the bank is active, including the AGP counter of
the bank. The charge pump AGP counter begins counting when the bank has become inactive.
The application software can check the current power mode of Flash bank and charge pump by reading the
FBPRDY register.
6.6 Flash and OTP Performance
Flash read or instruction fetch accesses can be classified either as a Flash access (access to an address
location in Flash), or an OTP access (access to an address location in OTP).
When the CPU performs an access to a Flash memory address, data is returned after (RWAIT+1) SYSCLK
cycles.
For a USER-OTP access, data is returned after 11 SYSCLK cycles.
RWAIT defines the number of random access wait states, and is configured using the RWAIT field in the
FRDCNTL register. At reset, RWAIT defaults to a worst-case wait state count (15), and therefore must be
initialized to the appropriate number of wait states to improve performance, based on the CPU clock frequency
and the access time of the Flash. The Flash supports zero-wait accesses when RWAIT is set to zero, when the
CPU clock frequency is low enough to accommodate the Flash access time.
For a given system clock frequency, configure RWAIT using the following formula:

For C28x Flash Bank: RWAIT = ceiling[(SYSCLK/FCLK)-1]

where SYSCLK is the system operating frequency for CPU1, and where FCLK is the clock frequency for Flash.
FCLK must be ≤ FCLKmax, the allowed maximum Flash clock frequency at RWAIT=0.
If RWAIT results in a fractional value when calculated using the above formula, round up RWAIT to the nearest
integer.

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6.7 Flash Read Interface

This section provides details about the data read modes to access Flash bank/OTP and the configuration
registers that control the read interface. In addition to a standard read mode, the FMC has a built-in prefetch and
cache mechanism to allow increased clock speeds and CPU throughput wherever applicable.
6.7.1 C28x-FMC Flash Read Interface
6.7.1.1 Standard Read Mode
Standard read mode is the default Flash read mode after reset. In this mode, the code prefetch mechanism and
data cache are disabled. When standard read mode is active, every read access to Flash is decoded by the
Flash wrapper to fetch the data from the addressed location, and the data is returned after RWAIT+1 cycles
(except User OTP).
Flash data buffers associated with the prefetch mechanism and data cache are bypassed in standard read
mode; therefore, every access to the Flash/OTP is used by the CPU immediately, and every access creates a
unique Flash bank access.
Standard read mode is the recommended mode for lower system frequency operation, where RWAIT can be
set to zero to provide single-cycle access operation. The FMC can operate at higher frequencies using standard
read mode, at the expense of adding wait states. At higher system frequencies, it is recommended to enable
the data cache and prefetch mechanisms to improve performance. Refer to the device data sheet to determine
the maximum Flash frequency allowed in standard read mode (that is, maximum Flash clock frequency with
RWAIT=0, FCLKMAX).
6.7.1.2 Prefetch Mode
Flash memory is typically used to store application code. During code execution, instructions are fetched from
contiguous memory addresses, except when a discontinuity occurs. Usually, the portion of the code that resides
in contiguous address locations makes up the majority of the application code, and is referred to as linear code.
To improve the performance of linear code execution, a Flash prefetch mechanism has been implemented.
Figure 6-2 illustrates how this mode functions.
The prefetch mechanism does a look-ahead prefetch on linear address increments, starting from the address of
the last instruction fetch. The Flash prefetch mechanism is disabled by default. To enable prefetch mode, set the
PREFETCH_EN bit in the FRD_INTF_CTRL register, or call the Flash_enablePrefetch() driverlib function.
Each instruction fetch from the Flash or OTP reads out 128 bits. The starting address of the access from Flash is
automatically aligned to a 128-bit boundary, such that the instruction location is within the 128 bits to be fetched.
When Flash prefetch mode is enabled, the 128 bits read from the instruction fetch are stored in a 128-bit wide
by 2-level deep instruction prefetch buffer. The contents of this prefetch buffer are then sent to the CPU for
processing as required.
Up to four 32-bit or eight 16-bit instructions can reside within a single 128-bit access. The majority of C28x
instructions are 16 bits, so for every 128-bit instruction fetch from the Flash bank, it is likely that there are up to
eight instructions in the prefetch buffer ready to process through the CPU. During the time it takes to process
these instructions, the Flash prefetch mechanism automatically initiates another access to the Flash bank to
prefetch the next 128 bits. In this manner, the Flash prefetch mechanism works in the background to keep the
instruction prefetch buffers as full as possible. Using this technique, the overall efficiency of sequential code
execution from Flash or OTP is improved significantly.

Note
If the prefetch mechanism is enabled, then the last two rows (16 16-bit words, 256 bits) of a Flash
bank can not be used if there are no valid Flash memory addresses beyond the bank boundary. This
is necessary to prevent the Flash prefetch mechanism from attempting to pre-load the instruction
buffer with data from invalid address locations, causing an ECC error.

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Flash and OTP

16-bit

Flash prefetch
Instruction buffer

Flash or OTP Read (128-bit)

128-bit 128-bit
buffer buffer

Instruction fetch

128-bit
M Data cache
CPU 32-bit U
X

Data read from data memory

Figure 6-2. Flash Prefetch Mode

The Flash prefetch is aborted only when there is a code discontinuity caused by executing an instruction such
as a branch, function call, or loop. When this occurs, the prefetch mechanism is aborted, and the contents of the
prefetch buffer are flushed. There are two possible scenarios when this occurs:
1. If the destination address is within the Flash or OTP, the prefetch aborts and then resumes at the destination
address.
2. If the destination address is outside of the Flash and OTP, the prefetch is aborted, and begins again
only when the code branches back into the Flash or OTP. The Flash prefetch mechanism only applies to
instruction fetches from program space. Data reads from data memory and from program memory do not
utilize the prefetch mechanism and thus bypass the prefetch buffer. For example, instructions such as MAC,
DMAC, and PREAD read a data value from program memory. When such a read happens, the prefetch
buffer is bypassed, but the buffer is not flushed. If an instruction prefetch is already in progress when a data
read operation is initiated, then the data read is stalled until the prefetch completes.
Note that the prefetch mechanism gets bypassed when RWAIT is configured as zero.
6.7.1.2.1 Data Cache
In addition to the prefetch mechanism, a data cache of 128-bits wide has been implemented to improve data
space read performance. This data cache is separate from the instruction prefetch buffer, and is used for data
reads only. Whenever a data read access is performed by the CPU to a Flash bank address, if the data located
at that address is not presently loaded into the data cache, then the Flash wrapper reads 128 bits of data from
the Flash bank and stores it in the data cache. This data is eventually sent to the CPU for processing. The
starting address of the Flash bank access is automatically aligned to a 128-bit boundary, such that the requested
address location is within the 128 bits to be read from the bank.
The data cache is disabled by default at reset. To enable the data cache, set the DATA_CACHE_EN bit in the
FRD_INTF_CTRL register, or call the Flash_enableCache() driverlib function. Note that the data cache gets
bypassed when RWAIT is set to zero.

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6.8 Flash Erase and Program

Flash memory can be programmed either by using the CCS Flash plug-in or by using the UniFlash application.
If these methods are not feasible in an application, the Flash API can be used. The Flash memory can be
programmed, erased, and verified only by using the Flash API library. These functions are written, compiled and
validated by Texas Instruments. The Flash module contains a Flash state machine (FSM) to perform program
and erase operations.
The recommended flow for programming Flash is:
Erase → Program → Verify

6.8.1 Erase
When the target Flash is erased, the Flash reads as all 1's. This state is called 'blank.' The erase function must
be executed before programming. The user can not skip erase on sectors that read as 'blank' because these
sectors can require additional erasing due to marginally erased bits columns. The FSM provides an Erase Sector
command to erase the target sector. The erase function erases the data and the ECC together. Bank erase is
also supported in this device.

Note
It is important to provide the correct sector mask for the bank erase command. If the mask is
mistakenly chosen to erase an inaccessible sector (belongs to another security zone), the bank erase
command will continue attempting to erase the sector endlessly and the FSM will never exit (since
erase will not succeed). To avoid such a situation, user must take care to provide the correct mask.
However, given that there is a chance of choosing an incorrect mask, TI suggests to initialize the max
allowed erase pulses to zero after the max number of pulses are issued by the FSM for the bank
erase operation. This will ensure that the FSM will end the bank erase command after trying to erase
the inaccessible sector up to the max allowed erase pulses.
The Example_EraseBanks() function in the C2000Ware’s Flash API usage example depicts the
implementation of this sequence (content of the while loop waiting for the FSM to complete the
bank erase command). Users must use this code as-is irrespective of whether or not security is used
by the application to also make sure that the FSM exits from bank erase operations in case of an
erase-failure.

6.8.2 Program
The FSM provides a command to program the USER OTP and Flash. This command is also used to program
ECC check bits.

Note
The main array Flash programming must be aligned to 64-bit address boundaries and each 64-bit
word can only be programmed once per write/erase cycle.
The DCSM OTP programming must be aligned to 128-bit address boundaries and each 128-bit word
can only be programmed once. The exceptions are:
• The DCSM Zx-LINKPOINTER1 and Zx-LINKPOINTER2 values in the DCSM OTP can be
programmed together and can be programmed one bit at a time as required by the DCSM
operation.
• The DCSM Zx-LINKPOINTER3 values in the DCSM OTP can be programmed one bit at a time as
required by the DCSM operation.

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6.8.3 Verify
After programming, the user must perform verify using API function Fapi_doVerify(). This function verifies the
Flash contents against supplied data.
Application software typically perform a CRC check of the Flash memory contents during power-up and at
regular intervals during runtime (as needed). Apart from this, ECC logic, when enabled (enabled by default),
catches single-bit errors, double-bit errors, and address errors whenever the CPU reads/fetches from a Flash
address.
6.9 Error Correction Code (ECC) Protection
CPU1-FMC and CPU2-FMC contain an embedded single error correction and double error detection (SECDED)
module. SECDED, when enabled, provides the capability to screen out memory faults. SECDED can detect and
correct single-bit data errors and detect address errors/double-bit data errors. For every 64 bits of Flash/OTP
data (aligned on a 64-bit memory boundary) that is programmed, eight ECC check bits have to be calculated
and programmed in ECC memory space. Refer to the device data sheet for the Flash/OTP ECC memory-map.
SECDED works with a total of eight user-calculated error correction code (ECC) check bits associated with each
64-bit wide data word and the corresponding 128-bit memory-aligned address. Users must program ECC check
bits along with Flash data. TI recommends using the AutoEccGeneration option available in the Plugin/API to
program ECC. Users can use the Flash API to calculate and program ECC data along with Flash data. Flash API
uses hardware ECC logic in the device to generate the ECC data for the given Flash data. The Flash Plugin, the
Flash programming tool integrated with the Code Composer Studio™ IDE, uses the Flash API to generate and
program ECC data.
Figure 6-3 illustrates the ECC logic inputs and outputs.
During an instruction fetch or a data read operation, the 19 most significant address bits (three least significant
bits of address are not considered), together with the 64-bit data/8-bit ECC read-out of Flash banks/ECC
memory map area, pass through the SECDED logic and the eight checkbits are produced in FMC. These eight
calculated ECC check bits are then XORed with the stored check bits (user programmed check bits) associated
with the address and the read data. The 8-bit output is decoded inside the SECDED module to determine one of
three conditions:
• No error occurred
• A correctable error (single bit data error) occurred
• A non-correctable error (double bit data error or address error) occurred

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Single-bit data error

Address/Double-bit data error
Single-bit Error position
Corrected data out
SECDED ECC[15:8]

Data[127:64]

128-bit aligned 19-bit CPU address

Flash
and
OTP

Single-bit data error

Address/Double-bit data error
Single-bit Error position
Corrected data out
SECDED Data[63:0]

ECC[7:0]

Figure 6-3. ECC Logic Inputs and Outputs

If the SECDED logic finds a single-bit error in the address field, then the error is considered to be a non-
correctable error.

Note
Since ECC is calculated for an entire 64-bit data, a non 64-bit read such as a byte read or a half-word
read still forces the entire 64-bit data to be read and calculated, but only the byte or half-word are
actually used by the CPU.

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This ECC (SECDED) feature is enabled at reset. The ECC_ENABLE register can be used to configure (enable/
disable) the ECC feature. The ECC for the application code must be programmed. There are two SECDED
modules in each FMC. Out of the 128-bit data (aligned on a 128-bit memory boundary) read from the bank/OTP
address, the lower 64 bits of data and corresponding 8 ECC bits (read from user programmable ECC memory
area) are fed as inputs to one SECDED module along with 128-bit aligned 19-bit address from where data has
been read. The upper 64 bits of data and corresponding 8 ECC bits are fed as inputs to another SECDED
module in parallel, along with 128-bit aligned 19-bit address. Each of the SECDED modules evaluate their inputs
and determine if there is any single-bit data error or double-bit data error/address error.
ECC logic is bypassed when the 64 data bits and the associated ECC bits fetched from the bank are either all
ones or zeros.
6.9.1 Single-Bit Data Error
This section provides information for both single-bit data errors and single-bit ECC check bit errors. If there is a
single bit flip (0 to 1 or 1 to 0) in Flash data or in ECC data, then the error is considered as a single-bit data error.
The SECDED module detects and corrects single-bit errors, if any, in the 64-bit Flash data or eight ECC check
bits read from the Flash/ECC memory map before the read data is provided to the CPU.
When SECDED finds and corrects single bit data errors, the following information is logged in the ECC registers
if the ECC feature is enabled:
• Address where the error occurred: if the single-bit error occurs in the lower 64 bits of a 128-bit memory-
aligned Flash data word, the address of the lower 64-bit word is captured in the SINGLE_ERR_ADDR_LOW
register. If the single-bit error occurs in the upper 64 bits of the 128-bit data word, then the address of the
upper 64-bit word is captured in the SINGLE_ERR_ADDR_HIGH register.
• Whether the error occurred in data bits or ECC bits: the ERR_TYPE_L and ERR_TYPE_H bit fields in the
ERR_POS register indicate whether the error occurred in data bits or ECC bits of the lower 64 bits, or the
upper 64 bits respectively, of a 128-bit memory-aligned Flash data word.
• Bit position at which the error occurred: the ERR_POS_L and ERR_POS_H bit fields in the ERR_POS
register indicate the bit position of the error in the lower 64 bits/lower 8-bit ECC, or the upper 64 bits/upper
8-bit ECC respectively, of a 128-bit memory-aligned Flash data word.
• Whether the corrected value is 0 (FAIL_0_L, FAIL_0_H flags in ERR_STATUS register).
• Whether the corrected value is 1 (FAIL_1_L, FAIL_1_H flags in ERR_STATUS register).
• A single bit error counter that increments on every single bit error occurrence (ERR_CNT register) until a
user-configurable threshold (see ERR_THRESHOLD) is met.
• A flag that gets set when one or more single-bit errors occurs after ERR_CNT equals ERR_THRESHOLD
(SINGLE_ERR_INT_FLG flag in the ERR_INTFLG register).
When the ERR_CNT value equals ERR_THRESHOLD+1, and a single bit error occurs, the Flash module sets
the SINGLE_ERR_INT flag and generates an interrupt signal. To enable propagation of the generated interrupt
pulse to the CPU, the user application must enable the FLASH_CORRECTABLE_ERROR channel in the C28
Peripheral Interrupt Expansion module (PIE). The interrupt signal remains high until the application clears the
SINGLE_ERR_INTFLG flag by writing to the SINGLE_ERR_INTCLR bit in the ERR_INTCLR register. The Flash
module cannot generate any further FLASH_CORRECTABLE_ERROR interrupt signals to the PIE/CPU until
SINGLE_ERR_INTFLG is cleared, as this is an edge-based interrupt.
When multiple single-bit errors have been detected by ECC logic, the contents of the Flash ECC registers reflect
the most recent ECC error. When multiple single-bit errors have been detected, both FAIL_0_L and FAIL_1_L
(or FAIL_0_H and FAIL_1_H) can be set, indicating that single-bit fail0/fail1 occurred in different 64-bit aligned
addresses.
Although ECC is calculated on 64-bit basis, a read of any address location within a 128-bit aligned Flash data
word causes the single-bit error flag to get set, if there is a single-bit error in both or in either the lower 64 or
upper 64 bits (or corresponding ECC check bits) of that 128-bit data word.

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6.9.2 Uncorrectable Error

Uncorrectable errors include address errors and double-bit errors in data or ECC. When the ECC logic finds
uncorrectable errors, the following information is logged in ECC registers if the ECC feature is enabled:
• Address where the error occurred: if the uncorrectable error occurs in the lower 64 bits of a 128-
bit memory-aligned Flash data word, the lower 64-bit memory-aligned address is captured in the
UNC_ERR_ADDR_LOW register. If the uncorrectable error occurs in the upper 64 bits of a 128-
bit memory-aligned Flash data word, the upper 64-bit memory-aligned address is captured in the
UNC_ERR_ADDR_HIGH register.
• A flag is set indicating that an uncorrectable error occurred – the UNC_ERR_L and UNC_ERR_H flags in the
ERR_STATUS register indicate the uncorrectable error occurrence in the lower 64 bits/lower 8-bit ECC, or the
upper 64 bits/upper 8-bit ECC, respectively, of a 128-bit memory-aligned Flash data word.
• A flag is set indicating that an uncorrectable error interrupt is generated (UNC_ERR_INTFLG in
ERR_INTFLG register).
When an uncorrectable error occurs, the Flash module sets the UNC_ERR_INTFLG bit and generates an
uncorrectable error interrupt. This uncorrectable error interrupt generates a non-maskable interrupt (NMI), if
enabled, in the CPU. If an uncorrectable error interrupt flag is not cleared by writing to the UNC_ERR_INTCLR
bit in the ERR_INTCLR register, the Flash module cannot generate new uncorrectable interrupt signals, as this is
an edge-based interrupt.
Although ECC is calculated on 64-bit basis, a read of any address location within a 128-bit aligned Flash word
causes the uncorrectable error flag to get set, and an uncorrectable error interrupt/NMI to occur, when there is
a uncorrectable error in both or in either the lower 64 bits or upper 64 bits (or corresponding ECC check bits) of
that 128-bit data word.
6.9.3 SECDED Logic Correctness Check
Since error detection and correction logic are part of safety-critical logic, safety applications often need to make
sure that the SECDED logic is always working properly. For these safety concerns, to confirm the correctness
of the SECDED logic, an ECC test mode is provided to test the correctness of ECC logic periodically. In this
ECC test mode, data/ECC and address inputs to the ECC logic are controlled by the ECC test mode registers
FDATAH_TEST, FDATAL_TEST, FECC_TEST, and FADDR_TEST, respectively. Using this test mode, users
can introduce single-bit errors, double-bit errors, or address errors and check whether or not SECDED logic is
catching those errors. Users can also check if SECDED logic is reporting any false errors when no errors are
introduced.
This ECC test mode can be enabled by setting the ECC_TEST_EN bit in the FECC_CTRL register. When ECC
test mode is enabled, the CPU cannot read the data from Flash. Instead, the CPU gets data from the ECC test
mode registers (FDATAH_TEST/FDATAL_TEST). This is because the ECC test mode registers (FDATAH_TEST,
FDATAL_TEST, FECC_TEST) are multiplexed with data from the Flash. For this reason, ECC test mode code
must be executed from RAM and not from Flash.
Only one of the SECDED modules (out of the two SECDED modules that work on lower 64 bits and upper 64
bits of a read 128-bit data) at a time can be tested. The ECC_SELECT bit in the FECC_CTRL register can be
configured by users to select one of the SECDED modules for test.
To test the ECC logic using ECC test mode, follow these steps:
1. Obtain the ECC for a given Flash address (128-bit aligned) and 64-bit data by using the Auto ECC
generation option provided in Flash API.
2. Develop an application to test ECC logic using the above data. In this application:
• Write the 128-bit aligned 19-bit Flash address in FADDR_TEST.
• Write 64-bit data in FDATAx_TEST (FDATAL_TEST and FDATAH_TEST) registers.
• Write the corresponding 8-bit ECC in the FECC_TEST register.
• In any of the above three steps, the application can insert errors (single-bit data error or double-bit data
error or address error or single-bit ECC error or double-bit ECC error) to check whether or not ECC logic
is able to detect the errors.

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• Select the ECC logic block (lower 64-bits or upper 64-bits) which needs to be tested using the
ECC_SELECT bit in the FECC_CTRL register.
• Enable ECC test mode using the ECC_TEST_EN bit in FECC_CTRL register.
• Write a value of 1 in the DO_ECC_CALC bit in FECC_CTRL register to enable ECC test logic for a single
cycle to evaluate the address, data, ECC in FADDR_TEST, FDATAx_TEST and FECC_TEST registers
for ECC errors.

Once the above ECC test mode registers are written by the user:
• The FECC_OUTH register holds the data output bits 63:32 from the SECDED block under test.
• The FECC_OUTL register holds the data output bits 31:0 from the SECDED block under test.
• The FECC_STATUS register holds the status of single-bit error occurrence, uncorrectable error occurrence,
and error position of single- bit error in data/check bits.

6.10 Reserved Locations Within Flash and OTP

When allocating code and data to Flash and OTP memory, keep the following reserved locations in mind:
• The entire OTP has reserved user-configurable locations for security and boot process. For more details on
the functionality of these fields, refer to the Dual Code Security Module (DCSM) and the ROM Code and
Peripheral Booting chapters.
• Refer to the ROM Code and Peripheral Booting chapter for reserved locations in Flash for real-time operating
system usage and a boot-to-Flash entry point. A boot-to-Flash entry point is reserved for an entry-into-Flash
branch instruction. When the boot-to-Flash boot option is used, the boot ROM jumps to this address in Flash.
If the user programs a branch instruction here, that then redirects code execution to the entry point of the
application.

6.11 Migrating an Application from RAM to Flash

To migrate an existing application that is configured to run from RAM to a Flash-based linker configuration, follow
the steps:
1. Replace the RAM linker command file with a Flash linker command file. For example Flash-based linker
command files, see the device_support\<device>\common\cmd directory.
2. When modifying the Flash-based linker command file, be sure to map any initialized sections to Flash
memory regions.
3. Make sure the boot mode pins are configured for Flash boot. This tells the boot ROM to redirect execution to
the application programmed into Flash memory after boot code execution is complete. For more information
on boot mode configuration, see "Detailed Description⏵Device Boot Modes" in the device data sheet.
4. When the device is configured for Flash boot, the boot ROM redirects execution to the Flash entry
point location (defined as BEGIN in TI-provided Flash linker command files) at the end of boot code
execution. Make sure there is a branch instruction at the Flash entry point to your code initialization
(for example, _c_int00) function. In the C2000Ware examples, the entry point code is specified in the
CodeStartBranch.asm file.
5. To achieve best performance for Flash execution, configure the Flash wait states as per the device operating
clock frequency, as specified in the device data manual. In addition, enable prefetch mode and data
cache mode. Calling the Flash_initModule() driverlib function achieves these steps. Note that code that
initializes the Flash module must execute from a RAM location. This is accomplished by assigning the Flash
initialization function to the .TI.ramfunc section, and then copying the function to RAM at runtime using
memcpy() before executing the function. In the linker command file, map this section to Flash for load, and
RAM for execution.
6. For any functions that require 0- or 1-wait state performance, be sure to map to RAM for execution in the
linker command file, similar to the Flash initialization function. The .TI.ramfunc section in the TI-provided
Flash linker command files accomplishes this purpose.

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7. Align all code and data sections to 128-bit address boundaries when mapping to Flash memory, using the
ALIGN directive in the linker command file.
8. For EABI executable formats, all uninitialized sections mapped to RAM are defined as NOINIT sections
(using the directive "type=NOINIT") in the linker command file.
9. Be sure to program ECC bits correctly for the Flash application image. Keep the AutoEccGeneration option
enabled in the Code Composer Studio Flash Plugin or UniFlash GUI.

6.12 Procedure to Change the Flash Control Registers

During Flash configuration, no accesses to the Flash or OTP can be in progress. This includes instructions still in
the CPU pipeline, data reads, and instruction prefetch operations. To be sure that no access takes place during
the configuration change, you should follow the procedure shown below for any code that modifies the Flash
control registers.
1. Start executing application code from RAM/Flash/OTP.
2. Branch to or call the Flash configuration code (that writes to Flash control registers) in RAM. This is required
to properly flush the CPU pipeline before the configuration change. The function that changes the Flash
configuration cannot execute from the Flash or OTP. It must reside in RAM.
3. Execute the Flash configuration code (should be located in RAM) that writes to Flash control registers like
FRDCNTL, FRD_INTF_CTRL, and so on.
4. At the end of the Flash configuration code execution, wait eight cycles to let the write instructions propagate
through the CPU pipeline. This must be done before the return-from-function call is made.
5. Return to the calling function that might reside in RAM or Flash/OTP and continue execution.

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6.13 Software
6.13.1 FLASH Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/flash
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
6.13.1.1 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
FILE: flashapi_ex1_programming.c
This example demonstrates how to program Flash using API's following options
1. AutoEcc generation
2. DataOnly and EccOnly
3. DataAndECC
External Connections
• None.
Watch Variables
• None.
6.13.1.2 Flash ECC Test Mode
FILE: flash_ex2_ecc_test_mode.c
This example demonstrates ECC Test mode.
6.13.1.3 Boot Source Code
FILE: flash_kernel_ex3_boot.c
Functions: void copyData(void) uint32_t getLongData(void) void readReservedFn(void)
6.13.1.4 Erase Source Code
FILE: flash_kernel_ex3_erase.c Functions:
6.13.1.5 Live DFU Command Functionality
FILE: flash_kernel_ex3_ldfu.c This file contains the functionality of the Live Device Firmware Update (Live DFU
or LDFU) Command and bank selection logic. The command functionality has 1 build configuration for each
bank: BANK0_LDFU, BANK1_LDFU, and BANK2_LDFU
For the BANK0 build configurations, the following steps are taken when the kernel receives the Live DFU
command:
1. Read an SCI Boot hex formatted file until information related to each block of data remains
2. Read and store the revision values of banks 2, 1 and 0 from flash (B1_REV_ADD: 0x92006, B2_REV_ADD:
0xA2006)
1. Erase sectors 2-15 of bank 1 or 2 depending on the revision number
2. Write 64 bits of 'START' value to B1_START_ADD/B2_START_ADD to indicate that erasing is done and
programming/verifying is about to start
3. Program and verify bank 1/2 by receiving the SCI boot hex formatted file one block of data at a time, writing
each byte to flash, and verifying each byte (the data should not be linked to an address that is less than
0x92008/0xA2008 (B1_RESERVED/B2_RESERVED))
4. Decrement the revision value of bank 1 or 2
5. Write the 'KEY' value to 0x92004/0xA2004 (B1_KEY_ADD/B2_KEY_ADD) and the revision value of bank 1
to 0x92006 (B1_REV_ADD) or of bank 2 to 0xA2006 (B2_REV_ADD)
6. Configure the watchdog for a reset and enable the watchdog in order for a reset to occur

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For the BANK1 build configurations, the following steps are taken when the kernel receives the Live DFU
command:
1. Read an SCI Boot hex formatted file until information related to each block of data remains
2. Read and store the revision value of bank 0, 1 and 2 from flash (B0_REV_ADD: 0x82006, B2_REV_ADD:
0xA2006)
1. Erase sectors 2-15 of bank 0 or 2 depending on the revision number
2. Write 64 bits of 'START' value to B0_START_ADD/B2_START_ADD to indicate that erasing is done and
programming/verifying is about to start
3. Program and verify bank 0/2 by receiving the SCI boot hex formatted file one block of data at a time, writing
each byte to flash, and verifying each byte (the data should not be linked to an address that is less than
0x82008/0xA2008 (B0_RESERVED/B2_RESERVED))
4. Decrement the revision value of bank 0 or 2
5. Write the 'KEY' value to 0x82004/0xA2004 (B0_KEY_ADD/B2_KEY_ADD) and the revision value of bank 0
to 0x82006 (B0_REV_ADD)or of bank 2 to 0xA2006 (B2_REV_ADD)
6. Configure the watchdog for a reset and enable the watchdog in order for a reset to occur
For the BANK2 build configurations, the following steps are taken when the kernel receives the Live DFU
command:
1. Read an SCI Boot hex formatted file until information related to each block of data remains
2. Read and store the revision value of bank 0, 1 and 2 from flash (B1_REV_ADD: 0x92006)
1. Erase sectors 2-15 of bank 0 or 1 depending on the revision number
2. Write 64 bits of 'START' value to B0_START_ADD/B1_START_ADD to indicate that erasing is done and
programming/verifying is about to start
3. Program and verify bank 0/1 by receiving the SCI boot hex formatted file one block of data at a time, writing
each byte to flash, and verifying each byte (the data should not be linked to an address that is less than
0x92008/0xA2008 (B1_RESERVED/B2_RESERVED))
4. Decrement the revision value of bank 1 or 2
5. Write the 'KEY' value to 0x82004/0xA2004 (B0_KEY_ADD/B2_KEY_ADD) and the revision value of bank 0
to 0x82006 (B0_REV_ADD)or of bank 2 to 0xA2006 (B2_REV_ADD)
6. Configure the watchdog for a reset and enable the watchdog in order for a reset to occur
Bank selection logic (bankSelect) is the entry point for the BANK0 build configurations; it is also the first thing
to run after a reset occurs. Bank selection logic branches to the most recently programmed bank or to the
kernel setup when no banks have been programmed using the Live DFU command. When no banks have
been programmed using the Live DFU command, a program must be loaded to bank 1 by using the Live DFU
command.
Bank selection logic is located at 0x80000; therefore the device must be configured to boot to flash at 0x80000
for correct functionality.
When running BANK0 configurations, a breakpoint may need to be placed at the beginning of bankSelect if CCS
debug tools are needed. The breakpoint may be removed afterwards to prevent the program from stopping after
each update.
6.13.1.6 Verify Source Code
FILE: flash_kernel_ex3_verify.c
6.13.1.7 SCI Boot Mode Routines
FILE: flash_kernel_ex3_sci_boot.c Functions: uint32_t sciBoot(void) void sciaInit(void) uint32_t
sciaGetWordData(void)
6.13.1.8 Flash Programming Solution using SCI
FILE: flash_kernel_ex3_sci_flash_kernel.c
In this example, we set up a UART connection with a host using SCI, receive commands for CPU1 to perform
which then sends ACK, NAK, and status packets back to the host after receiving and completing the tasks. This

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kernel has the ability to program, verify, unlock, reset, and run an application. Each command either expects no
data from the command packet or specific data relative to the command.
In this example, we set up a UART connection with a host using SCI, receive an application for CPU01 in -sci8
ascii format to run on the device and program it into Flash.
6.14 Flash Registers
This section describes the Flash Module Registers.
6.14.1 FLASH Base Address Table
Table 6-1. FLASH Base Address Table
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 DMA HIC CLA
Instance Structure Protected

FLASH_CTRL_RE FLASH0CTRL_BAS
Flash0CtrlRegs 0x0005_F800 YES - - - YES
GS E
FLASH_ECC_RE
Flash0EccRegs FLASH0ECC_BASE 0x0005_FB00 YES - - - YES
GS

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6.14.2 FLASH_CTRL_REGS Registers

Table 6-2 lists the memory-mapped registers for the FLASH_CTRL_REGS registers. All register offset
addresses not listed in Table 6-2 should be considered as reserved locations and the register contents should
not be modified.
Table 6-2. FLASH_CTRL_REGS Registers
Offset Acronym Register Name Write Protection Section
0h FRDCNTL Flash Read Control Register EALLOW Go
1Eh FBAC Flash Bank Access Control Register EALLOW Go
20h FBFALLBACK Flash Bank Fallback Power Register EALLOW Go
22h FBPRDY Flash Bank Pump Ready Register EALLOW Go
24h FPAC1 Flash Pump Access Control Register 1 EALLOW Go
26h FPAC2 Flash Pump Access Control Register 2 EALLOW Go
2Ah FMSTAT Flash Module Status Register EALLOW Go
180h FRD_INTF_CTRL Flash Read Interface Control Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 6-3 shows the codes that are used for
access types in this section.
Table 6-3. FLASH_CTRL_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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6.14.2.1 FRDCNTL Register (Offset = 0h) [Reset = F00h]

FRDCNTL is shown in Figure 6-4 and described in Table 6-4.
Return to the Summary Table.
Flash Read Control Register
Figure 6-4. FRDCNTL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RWAIT RESERVED
R-0h R/W-Fh R-0h

Table 6-4. FRDCNTL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 RESERVED R 0h Reserved
11-8 RWAIT R/W Fh Random read waitstate
These bits indicate how many waitstates are added to a flash read/
fetch access. The RWAIT value can be set anywhere from 0 to 0xF.
For a flash access, data is returned in RWAIT+1 SYSCLK cycles.
Note: The required wait states for each SYSCLK frequency can be
found in the device data manual.
Reset type: SYSRSn
7-0 RESERVED R 0h Reserved

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6.14.2.2 FBAC Register (Offset = 1Eh) [Reset = Fh]

FBAC is shown in Figure 6-5 and described in Table 6-5.
Return to the Summary Table.
Flash Bank Access Control Register
Figure 6-5. FBAC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED BAGP RESERVED
R-0h R/W-0h R/W-Fh

Table 6-5. FBAC Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 BAGP R/W 0h Bank Active Grace Period. These bits contain the starting count
value for the BAGP down counter. Any access to a given bank
causes its BAGP counter to reload the BAGP value for that bank.
After the last access to this flash bank, the down counter delays
from 0 to 255 prescaled SYSCLK clock cycles before putting the
bank into one of the fallback power modes as determined by the
FBFALLBACK register. This value must be greater than 1 when the
fallback mode is not ACTIVE.
Note: The prescaled clock used for the BAGP down counter is a
clock divided by 16 from input SYSCLK.
Reset type: SYSRSn
7-0 RESERVED R/W Fh Reserved

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6.14.2.3 FBFALLBACK Register (Offset = 20h) [Reset = 0h]

FBFALLBACK is shown in Figure 6-6 and described in Table 6-6.
Return to the Summary Table.
Flash Bank Fallback Power Register
Figure 6-6. FBFALLBACK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED BNKPWR2 BNKPWR1 BNKPWR0
R-0h R/W-0h R/W-0h R/W-0h

Table 6-6. FBFALLBACK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-6 RESERVED R 0h Reserved
5-4 BNKPWR2 R/W 0h Fall Back power mode
00 Sleep (Sense amplifiers and sense reference disabled)
01 Standby (Sense amplifiers disabled, but sense reference
enabled)
10 Reserved
11 Active (Both sense amplifiers and sense reference enabled)
Reset type: SYSRSn
3-2 BNKPWR1 R/W 0h Fall Back power mode
00 Sleep (Sense amplifiers and sense reference disabled)
01 Standby (Sense amplifiers disabled, but sense reference
enabled)
10 Reserved
11 Active (Both sense amplifiers and sense reference enabled)
Reset type: SYSRSn
1-0 BNKPWR0 R/W 0h Fall Back power mode
00 Sleep (Sense amplifiers and sense reference disabled)
01 Standby (Sense amplifiers disabled, but sense reference
enabled)
10 Reserved
11 Active (Both sense amplifiers and sense reference enabled)
Reset type: SYSRSn

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6.14.2.4 FBPRDY Register (Offset = 22h) [Reset = 0h]

FBPRDY is shown in Figure 6-7 and described in Table 6-7.
Return to the Summary Table.
Flash Bank Pump Ready Register
Figure 6-7. FBPRDY Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
PUMPRDY RESERVED
R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED BANK2RDY BANK1RDY BANK0RDY
R-0h R-0h R-0h R-0h

Table 6-7. FBPRDY Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 PUMPRDY R 0h Pump Ready. This is a read-only bit which allows software to
determine if the pump is ready for flash access before attempting
the actual access. If an access is made to a bank when the pump is
not ready, wait states are asserted until it becomes ready.
0 Pump is not ready.
1 Pump is ready, in active power state.
Reset type: SYSRSn
14-3 RESERVED R 0h Reserved
2 BANK2RDY R 0h Bank 2 Ready. This is a read-only register which allows software to
determine if the Bank 2 is ready for Flash access before the access
is attempted.
Note: The user should wait for both the pump and the bank to be
ready before attempting an access.
0 Bank 2 is not ready.
1 Bank 2 is in active power mode and is ready for access.
Reset type: SYSRSn
1 BANK1RDY R 0h Bank 1 Ready. This is a read-only register which allows software to
determine if the Bank 1 is ready for Flash access before the access
is attempted.
Note: The user should wait for both the pump and the bank to be
ready before attempting an access.
0 Bank 1 is not ready.
1 Bank 1 is in active power mode and is ready for access.
Reset type: SYSRSn
0 BANK0RDY R 0h Bank 0 Ready. This is a read-only register which allows software to
determine if the Bank 0 is ready for Flash access before the access
is attempted.
Note: The user should wait for both the pump and the bank to be
ready before attempting an access.
0 Bank 0 is not ready.
1 Bank 0 is in active power mode and is ready for access.
Reset type: SYSRSn

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6.14.2.5 FPAC1 Register (Offset = 24h) [Reset = 00A00000h]

FPAC1 is shown in Figure 6-8 and described in Table 6-8.
Return to the Summary Table.
Flash Pump Access Control Register 1
Figure 6-8. FPAC1 Register
31 30 29 28 27 26 25 24
RESERVED PSLEEP
R-0h R/W-A0h

23 22 21 20 19 18 17 16
PSLEEP
R/W-A0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED PMPPWR
R-0h R/W-0h

Table 6-8. FPAC1 Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-16 PSLEEP R/W A0h Pump sleep. These bits contain the starting count value for the
charge pump sleep down counter. While the charge pump is in
sleep mode, the power mode management logic holds the charge
pump sleep counter at this value. When the charge pump exits sleep
power mode, the down counter delays from 0 to PSLEEP prescaled
SYSCLK clock cycles before putting the charge pump into active
power mode.
Note: The pump sleep down counter uses the same prescaled clock
as Bank sleep down counter which is divided by 2 of input SYSCLK.
Note: BootROM configures the PSLEEP value as 0x4D4 for 120
MHz operation. Users can modify the PSLEEP value based on their
application requirements if needed.
Reset type: SYSRSn
15-1 RESERVED R 0h Reserved
0 PMPPWR R/W 0h Flash Charge Pump Fallback Power Mode. This bit selects what
power mode the charge pump enters after the pump active grace
period (PAGP) counter has timed out.
0 Sleep (all pump circuits disabled)
1 Active (all pump circuits active)
Note for devices with multiple flash banks: As the pump is shared
between flash banks, if an access is made either bank, the value of
this bit changes to 1 (active).
Reset type: SYSRSn

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6.14.2.6 FPAC2 Register (Offset = 26h) [Reset = 0h]

FPAC2 is shown in Figure 6-9 and described in Table 6-9.
Return to the Summary Table.
Flash Pump Access Control Register 2
Figure 6-9. FPAC2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PAGP
R-0h R/W-0h

Table 6-9. FPAC2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 PAGP R/W 0h Pump Active Grace Period. This register contains the starting count
value for the PAGP mode down counter. Any access to flash memory
causes the counter to reload with the PAGP value. After the last
access to flash memory, the down counter delays from 0 to 65535
prescaled SYSCLK clock cycles before entering one of the charge
pump fallback power modes as determined by PUMPPWR in the
FPAC1 register.
Note: The PAGP down counter is clocked by the same prescaled
clock as the BAGP down counter which is divided by 16 of input
SYSCLK.
Reset type: SYSRSn

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6.14.2.7 FMSTAT Register (Offset = 2Ah) [Reset = 0h]

FMSTAT is shown in Figure 6-10 and described in Table 6-10.
Return to the Summary Table.
Flash Module Status Register
Figure 6-10. FMSTAT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0h R-0h R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED PGV RESERVED EV RESERVED BUSY
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
ERS PGM INVDAT CSTAT VOLTSTAT ESUSP PSUSP RESERVED
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-10. FMSTAT Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R 0h Reserved
17 RESERVED R 0h Reserved
16 RESERVED R 0h Reserved
15 RESERVED R 0h Reserved
14 RESERVED R 0h Reserved
13 RESERVED R 0h Reserved
12 PGV R 0h Program verify When set, indicates that a word is not successfully
programmed after the maximum allowed number of program pulses
are given for program operation.
Reset type: SYSRSn
11 RESERVED R 0h Reserved
10 EV R 0h Erase verify When set, indicates that a sector is not successfully
erased after the maximum allowed number of erase pulses are given
for erase operation.
Reset type: SYSRSn
9 RESERVED R 0h Reserved
8 BUSY R 0h When set, this bit indicates that a program, erase, or suspend
operation is being processed.
Reset type: SYSRSn
7 ERS R 0h Erase Active. When set, this bit indicates that the flash module is
actively performing an erase operation. This bit is set when erasing
starts and is cleared when erasing is complete. It is also cleared
when the erase is suspended and set when the erase resumes.
Reset type: SYSRSn
6 PGM R 0h Program Active. When set, this bit indicates that the flash module
is currently performing a program operation. This bit is set when
programming starts and is cleared when programming is complete.
It is also cleared when programming is suspended and set when
programming is resumed.
Reset type: SYSRSn

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Table 6-10. FMSTAT Register Field Descriptions (continued)

Bit Field Type Reset Description
5 INVDAT R 0h Invalid Data. When set, this bit indicates that the user attempted to
program a "1" where a "0" was already present.
Reset type: SYSRSn
4 CSTAT R 0h Command Status. Once the FSM starts any failure will set this bit.
When set, this bit informs the host that the program, erase, or
validate sector command failed and the command was stopped. This
bit is cleared by the Clear Status command. For some errors, this will
be the only indication of an FSM error because the cause does not
fall within the other error bit types.
Reset type: SYSRSn
3 VOLTSTAT R 0h Core Voltage Status. When set, this bit indicates that the core
voltage generator of the pump power upply dipped below the lower
limit allowable during a program or erase operation.
Reset type: SYSRSn
2 ESUSP R 0h When set, this bit indicates that the flash module has received and
processed an erase suspend operation. This bit remains set until the
erase resume command has been issued or until the Clear_More
command is run.
Reset type: SYSRSn
1 PSUSP R 0h When set, this bit indicates that the flash module has received
and processed a program suspend operation. This bit remains set
until the program resume command has been issued or until the
Clear_More command is run.
Reset type: SYSRSn
0 RESERVED R 0h Reserved

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6.14.2.8 FRD_INTF_CTRL Register (Offset = 180h) [Reset = 0h]

FRD_INTF_CTRL is shown in Figure 6-11 and described in Table 6-11.
Return to the Summary Table.
Flash Read Interface Control Register
Figure 6-11. FRD_INTF_CTRL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED DATA_CACHE_ PREFETCH_E
EN N
R-0h R/W-0h R/W-0h

Table 6-11. FRD_INTF_CTRL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-2 RESERVED R 0h Reserved
1 DATA_CACHE_EN R/W 0h Data cache enable.
0 A value of 0 disables the data cache.
1 A value of 1 enables the data cache.
Reset type: SYSRSn
0 PREFETCH_EN R/W 0h Prefetch enable.
0 A value of 0 disables prefetch mechanism.
1 A value of 1 enables pre-fetch mechanism.
Reset type: SYSRSn

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6.14.3 FLASH_ECC_REGS Registers

Table 6-12 lists the memory-mapped registers for the FLASH_ECC_REGS registers. All register offset
addresses not listed in Table 6-12 should be considered as reserved locations and the register contents should
not be modified.
Table 6-12. FLASH_ECC_REGS Registers
Offset Acronym Register Name Write Protection Section
0h ECC_ENABLE ECC Enable EALLOW Go
2h SINGLE_ERR_ADDR_LOW Single Error Address Low EALLOW Go
4h SINGLE_ERR_ADDR_HIGH Single Error Address High EALLOW Go
6h UNC_ERR_ADDR_LOW Uncorrectable Error Address Low EALLOW Go
8h UNC_ERR_ADDR_HIGH Uncorrectable Error Address High EALLOW Go
Ah ERR_STATUS Error Status EALLOW Go
Ch ERR_POS Error Position EALLOW Go
Eh ERR_STATUS_CLR Error Status Clear EALLOW Go
10h ERR_CNT Error Control EALLOW Go
12h ERR_THRESHOLD Error Threshold EALLOW Go
14h ERR_INTFLG Error Interrupt Flag EALLOW Go
16h ERR_INTCLR Error Interrupt Flag Clear EALLOW Go
18h FDATAH_TEST Data High Test EALLOW Go
1Ah FDATAL_TEST Data Low Test EALLOW Go
1Ch FADDR_TEST ECC Test Address EALLOW Go
1Eh FECC_TEST ECC Test Address EALLOW Go
20h FECC_CTRL ECC Control EALLOW Go
22h FOUTH_TEST Test Data Out High EALLOW Go
24h FOUTL_TEST Test Data Out Low EALLOW Go
26h FECC_STATUS ECC Status EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 6-13 shows the codes that are used for
access types in this section.
Table 6-13. FLASH_ECC_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables

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Table 6-13. FLASH_ECC_REGS Access Type Codes

(continued)
Access Type Code Description
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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6.14.3.1 ECC_ENABLE Register (Offset = 0h) [Reset = Ah]

ECC_ENABLE is shown in Figure 6-12 and described in Table 6-14.
Return to the Summary Table.
ECC Enable
Figure 6-12. ECC_ENABLE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ENABLE
R-0h R/W-Ah

Table 6-14. ECC_ENABLE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3-0 ENABLE R/W Ah ECC enable. A value of 0xA would enable ECC. Any other value
would disable ECC.
Reset type: SYSRSn

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6.14.3.2 SINGLE_ERR_ADDR_LOW Register (Offset = 2h) [Reset = 0h]

SINGLE_ERR_ADDR_LOW is shown in Figure 6-13 and described in Table 6-15.
Return to the Summary Table.
Single Error Address Low
Figure 6-13. SINGLE_ERR_ADDR_LOW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERR_ADDR_L
R/W-0h

Table 6-15. SINGLE_ERR_ADDR_LOW Register Field Descriptions

Bit Field Type Reset Description
31-0 ERR_ADDR_L R/W 0h 64-bit aligned address at which a single bit error occurred in the
lower 64-bits of a 128-bit aligned memory.
Reset type: SYSRSn

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6.14.3.3 SINGLE_ERR_ADDR_HIGH Register (Offset = 4h) [Reset = 0h]

SINGLE_ERR_ADDR_HIGH is shown in Figure 6-14 and described in Table 6-16.
Return to the Summary Table.
Single Error Address High
Figure 6-14. SINGLE_ERR_ADDR_HIGH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERR_ADDR_H
R/W-0h

Table 6-16. SINGLE_ERR_ADDR_HIGH Register Field Descriptions

Bit Field Type Reset Description
31-0 ERR_ADDR_H R/W 0h 64-bit aligned address at which a single bit error occurred in the
upper 64-bits of a 128-bit aligned memory.
Reset type: SYSRSn

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6.14.3.4 UNC_ERR_ADDR_LOW Register (Offset = 6h) [Reset = 0h]

UNC_ERR_ADDR_LOW is shown in Figure 6-15 and described in Table 6-17.
Return to the Summary Table.
Uncorrectable Error Address Low
Figure 6-15. UNC_ERR_ADDR_LOW Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNC_ERR_ADDR_L
R/W-0h

Table 6-17. UNC_ERR_ADDR_LOW Register Field Descriptions

Bit Field Type Reset Description
31-0 UNC_ERR_ADDR_L R/W 0h 64-bit aligned address at which an uncorrectable error occurred in
the lower 64-bits of a 128-bit aligned memory.
Reset type: SYSRSn

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6.14.3.5 UNC_ERR_ADDR_HIGH Register (Offset = 8h) [Reset = 0h]

UNC_ERR_ADDR_HIGH is shown in Figure 6-16 and described in Table 6-18.
Return to the Summary Table.
Uncorrectable Error Address High
Figure 6-16. UNC_ERR_ADDR_HIGH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNC_ERR_ADDR_H
R/W-0h

Table 6-18. UNC_ERR_ADDR_HIGH Register Field Descriptions

Bit Field Type Reset Description
31-0 UNC_ERR_ADDR_H R/W 0h 64-bit aligned address at which an uncorrectable error occurred in
the upper 64-bits of a 128-bit aligned memory.
Reset type: SYSRSn

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6.14.3.6 ERR_STATUS Register (Offset = Ah) [Reset = 0h]

ERR_STATUS is shown in Figure 6-17 and described in Table 6-19.
Return to the Summary Table.
Error Status
Figure 6-17. ERR_STATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED UNC_ERR_H FAIL_1_H FAIL_0_H
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED UNC_ERR_L FAIL_1_L FAIL_0_L
R-0h R-0h R-0h R-0h

Table 6-19. ERR_STATUS Register Field Descriptions

Bit Field Type Reset Description
31-19 RESERVED R 0h Reserved
18 UNC_ERR_H R 0h Uncorrectable error. A value of 1 indicates that an un-correctable
error occurred in upper 64bits of a 128-bit aligned address. Cleared
by writing a 1 to UNC_ERR_H_CLR bit of ERR_STATUS_CLR
register.
Reset type: SYSRSn
17 FAIL_1_H R 0h Fail on 1.
0 Fail on 1 single bit error did not occur in upper 64bits of a 128-bit
aligned address.
1 A value of 1 would indicate that a single bit error occurred in upper
64bits of a 128-bit aligned address and the corrected value was 1.
Cleared by writing a 1 to FAIL_1_H_CLR bit of ERR_STATUS_CLR
register.
Note: This bit is updated on every flash access which results in a
single bit error, So, in case of multiple single bit error, the status
would correspond to the last error which occured.
Reset type: SYSRSn
16 FAIL_0_H R 0h Fail on 0.
0 Fail on 0 single bit error did not occur in upper 64bits of a 128-bit
aligned address.
1 A value of 1 would indicate that a single bit error occurred in upper
64bits of a 128-bit aligned address and the corrected value was 0.
Cleared by writing a 1 to FAIL_0_H_CLR bit of ERR_STATUS_CLR
register.
Note: This bit is updated on every flash access which results in a
single bit error, So, in case of multiple single bit error, the status
would correspond to the last error which occurred.
Reset type: SYSRSn
15-3 RESERVED R 0h Reserved
2 UNC_ERR_L R 0h Uncorrectable error. A value of 1 indicates that an un-correctable
error occurred in lower 64bits of a 128-bit aligned address. Cleared
by writing a 1 to UNC_ERR_L_CLR bit of ERR_STATUS_CLR
register.
Reset type: SYSRSn

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Table 6-19. ERR_STATUS Register Field Descriptions (continued)

Bit Field Type Reset Description
1 FAIL_1_L R 0h Fail on 1.
0 Fail on 1 single bit error did not occur in lower 64bits of a 128-bit
aligned address.
1 A value of 1 would indicate that a single bit error occurred in lower
64bits of a 128-bit aligned address and the corrected value was 1.
Cleared by writing a 1 to FAIL_1_L_CLR bit of ERR_STATUS_CLR
register.
Note: This bit is updated on every flash access which results in a
single bit error, So, in case of multiple single bit error, the status
would correspond to the last error which occured.
Reset type: SYSRSn
0 FAIL_0_L R 0h Fail on 0.
0 Fail on 0 single bit error did not occur in lower 64bits of a 128-bit
aligned address.
1 Would indicate that a single bit error occurred in lower 64bits of a
128-bit aligned address and the corrected value was 0. Cleared by
writing a 1 to FAIL_0_L_CLR bit of ERR_STATUS_CLR register.
Note: This bit is updated on every flash access which results in a
single bit error, So, in case of multiple single bit error, the status
would correspond to the last error which occured.
Reset type: SYSRSn

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6.14.3.7 ERR_POS Register (Offset = Ch) [Reset = 0h]

ERR_POS is shown in Figure 6-18 and described in Table 6-20.
Return to the Summary Table.
Error Position
Figure 6-18. ERR_POS Register
31 30 29 28 27 26 25 24
RESERVED ERR_TYPE_H
R-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED ERR_POS_H
R-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED ERR_TYPE_L
R-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED ERR_POS_L
R-0h R/W-0h

Table 6-20. ERR_POS Register Field Descriptions

Bit Field Type Reset Description
31-25 RESERVED R 0h Reserved
24 ERR_TYPE_H R/W 0h Error type
0 Indicates that a single bit error occured in upper 64 data bits of a
128-bit aligned address.
1 Indicates that a single bit error occured in ECC check bits of upper
64bits of a 128-bit aligned address.
Reset type: SYSRSn
23-22 RESERVED R 0h Reserved
21-16 ERR_POS_H R/W 0h Error position. Bit position of the single bit error in upper 64bits of
a 128-bit aligned address. The position is interpreted depending on
whether the ERR_TYPE bit indicates a check bit or a data bit. If
ERR_TYPE indicates a check bit error, the error position could range
from 0 to 7, else it could range from 0 to 63.
Reset type: SYSRSn
15-9 RESERVED R 0h Reserved
8 ERR_TYPE_L R/W 0h Error type
0 Indicates that a single bit error occured in lower 64 data bits of a
128-bit aligned address.
1 Indicates that a single bit error occured in ECC check bits of lower
64bits of a 128-bit aligned address.
Reset type: SYSRSn
7-6 RESERVED R 0h Reserved
5-0 ERR_POS_L R/W 0h Error position. Bit position of the single bit error in lower 64bits of
a 128-bit aligned address. The position is interpreted depending on
whether the ERR_TYPE bit indicates a check bit or a data bit. If
ERR_TYPE indicates a check bit error, the error position could range
from 0 to 7, else it could range from 0 to 63.
Reset type: SYSRSn

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6.14.3.8 ERR_STATUS_CLR Register (Offset = Eh) [Reset = 0h]

ERR_STATUS_CLR is shown in Figure 6-19 and described in Table 6-21.
Return to the Summary Table.
Error Status Clear
Figure 6-19. ERR_STATUS_CLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED UNC_ERR_H_ FAIL_1_H_CLR FAIL_0_H_CLR
CLR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED UNC_ERR_L_C FAIL_1_L_CLR FAIL_0_L_CLR
LR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 6-21. ERR_STATUS_CLR Register Field Descriptions

Bit Field Type Reset Description
31-19 RESERVED R 0h Reserved
18 UNC_ERR_H_CLR R-0/W1S 0h Uncorrectable error clear. Writing a 1 to this bit will clear the
UNC_ERR_H bit of ERR_STATUS
register. Writes of 0 have no effect. Read returns 0.
Reset type: SYSRSn
17 FAIL_1_H_CLR R-0/W1S 0h Fail on 1 clear. Writing a 1 to this bit will clear the FAIL_1_H bit of
ERR_STATUS register. Writes of 0
have no effect. Read returns 0.
Reset type: SYSRSn
16 FAIL_0_H_CLR R-0/W1S 0h Fail on 0 clear. Writing a 1 to this bit will clear the FAIL_0_H bit of
ERR_STATUS register. Writes of 0
have no effect. Read returns 0.
Reset type: SYSRSn
15-3 RESERVED R 0h Reserved
2 UNC_ERR_L_CLR R-0/W1S 0h Uncorrectable error clear. Writing a 1 to this bit will clear the
UNC_ERR_L bit of ERR_STATUS
register. Writes of 0 have no effect. Read returns 0.
Reset type: SYSRSn
1 FAIL_1_L_CLR R-0/W1S 0h Fail on 1 clear. Writing a 1 to this bit will clear the FAIL_1_L bit of
ERR_STATUS register. Writes of 0
have no effect. Read returns 0.
Reset type: SYSRSn
0 FAIL_0_L_CLR R-0/W1S 0h Fail on 0 clear. Writing a 1 to this bit will clear the FAIL_0_L bit of
ERR_STATUS register. Writes of 0
have no effect. Read returns 0.
Reset type: SYSRSn

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6.14.3.9 ERR_CNT Register (Offset = 10h) [Reset = 0h]

ERR_CNT is shown in Figure 6-20 and described in Table 6-22.
Return to the Summary Table.
Error Control
Figure 6-20. ERR_CNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR_CNT
R-0h R/W-0h

Table 6-22. ERR_CNT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 ERR_CNT R/W 0h Single bit error count. This counter increments with every single bit
ECC error occurrence. Upon reaching the threshold value counter
stops counting on single bit errors. ERR_CNT can be cleared
(irrespective of whether threshold is met or not) using "Single Err
Int Clear" bit. This is applicable for ECC logic test mode and normal
operational mode.
Reset type: SYSRSn

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6.14.3.10 ERR_THRESHOLD Register (Offset = 12h) [Reset = 0h]

ERR_THRESHOLD is shown in Figure 6-21 and described in Table 6-23.
Return to the Summary Table.
Error Threshold
Figure 6-21. ERR_THRESHOLD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR_THRESHOLD
R-0h R/W-0h

Table 6-23. ERR_THRESHOLD Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 ERR_THRESHOLD R/W 0h Single bit error threshold. Sets the threshold for single bit errors.
When the ERR_CNT value equals the THRESHOLD value and
a single bit error occurs, SINGLE_ERR_INT flag is set, and an
interrupt is fired.
Reset type: SYSRSn

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6.14.3.11 ERR_INTFLG Register (Offset = 14h) [Reset = 0h]

ERR_INTFLG is shown in Figure 6-22 and described in Table 6-24.
Return to the Summary Table.
Error Interrupt Flag
Figure 6-22. ERR_INTFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED UNC_ERR_INT SINGLE_ERR_I
FLG NTFLG
R-0h R-0h R-0h

Table 6-24. ERR_INTFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-2 RESERVED R 0h Reserved
1 UNC_ERR_INTFLG R 0h Uncorrectable bit error interrupt flag. When a Un-correctable error
occurs, this bit is set and the UNC_ERR_INT interrupt is fired. When
UNC_ERR_INTCLR bit of ERR_INTCLR register is written a value of
1 this bit is cleared.
Reset type: SYSRSn
0 SINGLE_ERR_INTFLG R 0h Single bit error interrupt flag. When the ERR_CNT value equals
the ERR_THRESHOLD value and a single bit error occurs then
SINGLE_ERR_INT flag is set and SINGLE_ERR_INT interrupt is
fired. When SINGLE_ERR_INTCLR bit of ERR_INTCLR register is
written a value of 1 this bit is cleared.
Reset type: SYSRSn

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6.14.3.12 ERR_INTCLR Register (Offset = 16h) [Reset = 0h]

ERR_INTCLR is shown in Figure 6-23 and described in Table 6-25.
Return to the Summary Table.
Error Interrupt Flag Clear
Figure 6-23. ERR_INTCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED UNC_ERR_INT SINGLE_ERR_I
CLR NTCLR
R-0h R-0/W1S-0h R-0/W1S-0h

Table 6-25. ERR_INTCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-2 RESERVED R 0h Reserved
1 UNC_ERR_INTCLR R-0/W1S 0h Uncorrectable bit error interrupt flag clear. Writing a 1 to this bit will
clear UNC_ERR_INT_FLG. Writes of 0 have no effect.
Reset type: SYSRSn
0 SINGLE_ERR_INTCLR R-0/W1S 0h Single bit error interrupt flag clear. Writing a 1 to this bit will clear
SINGLE_ERR_INT_FLG. Writes of 0 have no effect.
Reset type: SYSRSn

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6.14.3.13 FDATAH_TEST Register (Offset = 18h) [Reset = 0h]

FDATAH_TEST is shown in Figure 6-24 and described in Table 6-26.
Return to the Summary Table.
Data High Test
Figure 6-24. FDATAH_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATAH
R/W-0h

Table 6-26. FDATAH_TEST Register Field Descriptions

Bit Field Type Reset Description
31-0 FDATAH R/W 0h High double word of selected 64-bit data. User-configurable bits
63:32 of the selected data block in ECC test mode.
Reset type: SYSRSn

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6.14.3.14 FDATAL_TEST Register (Offset = 1Ah) [Reset = 0h]

FDATAL_TEST is shown in Figure 6-25 and described in Table 6-27.
Return to the Summary Table.
Data Low Test
Figure 6-25. FDATAL_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATAL
R/W-0h

Table 6-27. FDATAL_TEST Register Field Descriptions

Bit Field Type Reset Description
31-0 FDATAL R/W 0h Low double word of selected 64-bit data. User-configurable bits 31:0
of the selected data block in ECC test mode.
Reset type: SYSRSn

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6.14.3.15 FADDR_TEST Register (Offset = 1Ch) [Reset = 0h]

FADDR_TEST is shown in Figure 6-26 and described in Table 6-28.
Return to the Summary Table.
ECC Test Address
Figure 6-26. FADDR_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED ADDRH
R-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRL RESERVED
R/W-0h R-0h

Table 6-28. FADDR_TEST Register Field Descriptions

Bit Field Type Reset Description
31-22 RESERVED R 0h Reserved
21-16 ADDRH R/W 0h Address for selected 64-bit data. User-configurable address bits of
the selected data in ECC test mode. Left-shift the address by one bit
(to provide byte address) and ignore the three least significant bits of
the address and write the bits 21:16 in remaining address bits in this
field.
Reset type: SYSRSn
15-3 ADDRL R/W 0h Address for selected 64-bit data. User-configurable address bits of
the selected data in ECC test mode. Left-shift the address by one bit
(to provide byte address) and ignore the three least significant bits of
the address and write the bits 15:3 in remaining address bits in this
field.
Reset type: SYSRSn
2-0 RESERVED R 0h Reserved

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6.14.3.16 FECC_TEST Register (Offset = 1Eh) [Reset = 0h]

FECC_TEST is shown in Figure 6-27 and described in Table 6-29.
Return to the Summary Table.
ECC Test Address
Figure 6-27. FECC_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED ECC
R-0h R-0h R/W-0h

Table 6-29. FECC_TEST Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7-0 ECC R/W 0h 8-bit ECC for selected 64-bit data. User-configurable ECC bits of the
selected 64-bit data block in ECC test mode.
Reset type: SYSRSn

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6.14.3.17 FECC_CTRL Register (Offset = 20h) [Reset = 0h]

FECC_CTRL is shown in Figure 6-28 and described in Table 6-30.
Return to the Summary Table.
ECC Control
Figure 6-28. FECC_CTRL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED DO_ECC_CAL ECC_SELECT ECC_TEST_EN
C
R-0h R-0/W1S-0h R/W-0h R/W-0h

Table 6-30. FECC_CTRL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-3 RESERVED R 0h Reserved
2 DO_ECC_CALC R-0/W1S 0h Enable ECC calculation. ECC logic will calculate ECC in one cycle
for the data and address written in ECC test registers when ECC test
logic is enabled by setting ECC_TEST_EN.
Reset type: SYSRSn
1 ECC_SELECT R/W 0h ECC block select.
0 Selects the ECC block on bits [63:0] of bank data.
1 Selects the ECC block on bits [127:64] of bank data.
Reset type: SYSRSn
0 ECC_TEST_EN R/W 0h ECC test mode enable.
0 ECC test mode disabled
1 ECC test mode enabled
Reset type: SYSRSn

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6.14.3.18 FOUTH_TEST Register (Offset = 22h) [Reset = 0h]

FOUTH_TEST is shown in Figure 6-29 and described in Table 6-31.
Return to the Summary Table.
Test Data Out High
Figure 6-29. FOUTH_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAOUTH
R-0h

Table 6-31. FOUTH_TEST Register Field Descriptions

Bit Field Type Reset Description
31-0 DATAOUTH R 0h High double word test data out. Holds bits 63:32 of the data out of
the selected ECC block.
Reset type: SYSRSn

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6.14.3.19 FOUTL_TEST Register (Offset = 24h) [Reset = 0h]

FOUTL_TEST is shown in Figure 6-30 and described in Table 6-32.
Return to the Summary Table.
Test Data Out Low
Figure 6-30. FOUTL_TEST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAOUTL
R-0h

Table 6-32. FOUTL_TEST Register Field Descriptions

Bit Field Type Reset Description
31-0 DATAOUTL R 0h Low double word test data out. Holds bits 31:0 of the data out of the
selected ECC block.
Reset type: SYSRSn

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6.14.3.20 FECC_STATUS Register (Offset = 26h) [Reset = 0h]

FECC_STATUS is shown in Figure 6-31 and described in Table 6-33.
Return to the Summary Table.
ECC Status
Figure 6-31. FECC_STATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED ERR_TYPE
R-0h R-0h

7 6 5 4 3 2 1 0
DATA_ERR_POS UNC_ERR SINGLE_ERR
R-0h R-0h R-0h

Table 6-33. FECC_STATUS Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-9 RESERVED R 0h Reserved
8 ERR_TYPE R 0h Test mode ECC single bit error indicator. When 1, indicates that the
single bit error is in check bits. When 0, indicates that the single bit
error is in data bits (If SINGLE_ERR field is also set).
Reset type: SYSRSn
7-2 DATA_ERR_POS R 0h Test mode single bit error position. Holds the bit position where the
single bit error occurred.
The position is interpreted depending on whether the CHK_ERR bit
indicates a check bit or a data bit. If CHK_ERR indicates a check
bit error, the error position could range from 0 to 7, or it could range
from 0 to 63.
Reset type: SYSRSn
1 UNC_ERR R 0h Test mode ECC double bit error. When 1 indicates that the ECC test
resulted in an uncorrectable bit error.
Reset type: SYSRSn
0 SINGLE_ERR R 0h Test mode ECC single bit error. When 1 indicates that the ECC test
resulted in a single bit error.
Reset type: SYSRSn

6.14.4 FLASH Registers to Driverlib Functions

Table 6-34. FLASH Registers to Driverlib Functions
File Driverlib Function
FRDCNTL
flash.h Flash_setWaitstates
FBAC
flash.h Flash_setBankActiveGracePeriod
FBFALLBACK
flash.h Flash_setBankPowerMode

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Table 6-34. FLASH Registers to Driverlib Functions (continued)

File Driverlib Function
FBPRDY
flash.h Flash_isBankReady
flash.h Flash_isPumpReady
FPAC1
flash.h Flash_setPumpPowerMode
flash.h Flash_setPumpWakeupTime
FPAC2
flash.h Flash_setPumpActiveGracePeriod
FMSTAT
-
FRD_INTF_CTRL
flash.h Flash_enablePrefetch
flash.h Flash_disablePrefetch
flash.h Flash_enableCache
flash.h Flash_disableCache
ECC_ENABLE
flash.h Flash_enableECC
flash.h Flash_disableECC
SINGLE_ERR_ADDR_LOW
flash.h Flash_getSingleBitErrorAddressLow
SINGLE_ERR_ADDR_HIGH
flash.h Flash_getSingleBitErrorAddressHigh
UNC_ERR_ADDR_LOW
flash.h Flash_getUncorrectableErrorAddressLow
UNC_ERR_ADDR_HIGH
flash.h Flash_getUncorrectableErrorAddressHigh
ERR_STATUS
flash.h Flash_getLowErrorStatus
flash.h Flash_getHighErrorStatus
flash.h Flash_clearLowErrorStatus
flash.h Flash_clearHighErrorStatus
ERR_POS
flash.h Flash_getLowErrorPosition
flash.h Flash_getHighErrorPosition
flash.h Flash_clearLowErrorPosition
flash.h Flash_clearHighErrorPosition
flash.h Flash_getLowErrorType
flash.h Flash_getHighErrorType
flash.h Flash_clearLowErrorType
flash.h Flash_clearHighErrorType
ERR_STATUS_CLR
flash.h Flash_clearLowErrorStatus
flash.h Flash_clearHighErrorStatus
ERR_CNT
flash.h Flash_getErrorCount

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Table 6-34. FLASH Registers to Driverlib Functions (continued)

File Driverlib Function
ERR_THRESHOLD
flash.h Flash_setErrorThreshold
ERR_INTFLG
flash.h Flash_getInterruptFlag
ERR_INTCLR
flash.h Flash_clearSingleErrorInterruptFlag
flash.h Flash_clearUncorrectableInterruptFlag
FDATAH_TEST
flash.h Flash_setDataHighECCTest
FDATAL_TEST
flash.h Flash_setDataLowECCTest
FADDR_TEST
flash.h Flash_setECCTestAddress
FECC_TEST
flash.h Flash_setECCTestECCBits
FECC_CTRL
flash.h Flash_enableECCTestMode
flash.h Flash_disableECCTestMode
flash.h Flash_selectLowECCBlock
flash.h Flash_selectHighECCBlock
flash.h Flash_performECCCalculation
FOUTH_TEST
flash.h Flash_getTestDataOutHigh
FOUTL_TEST
flash.h Flash_getTestDataOutLow
FECC_STATUS
flash.h Flash_getECCTestStatus
flash.h Flash_getECCTestErrorPosition
flash.h Flash_getECCTestSingleBitErrorType

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www.ti.com Control Law Accelerator (CLA)

Chapter 7
Control Law Accelerator (CLA)

The Control Law Accelerator (CLA) Type-2 is an independent, fully-programmable, 32-bit floating-point math
processor that brings concurrent control-loop execution to the C28x family. The low interrupt latency of the
CLA allows the CLA to read ADC samples "just-in-time." This significantly reduces the ADC sample to output
delay to enable faster system response and higher MHz control loops. By using the CLA to service time-critical
control loops, the main CPU is free to perform other system tasks such as communications and diagnostics. This
chapter provides an overview of the architectural structure and components of the control law accelerator.

7.1 Introduction...............................................................................................................................................................790
7.2 CLA Interface............................................................................................................................................................ 792
7.3 CLA and CPU Arbitration.........................................................................................................................................798
7.4 CLA Configuration and Debug................................................................................................................................ 799
7.5 Pipeline......................................................................................................................................................................803
7.6 Software.................................................................................................................................................................... 809
7.7 Instruction Set...........................................................................................................................................................813
7.8 CLA Registers...........................................................................................................................................................932

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7.1 Introduction
The Control Law Accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-
critical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables
faster system response and higher frequency control loops. Utilizing the CLA for time-critical tasks frees up the
main CPU to perform other system and communication functions concurrently.
7.1.1 Features
The following is a list of major features of the CLA:
• C compilers are available for CLA software development.
• Clocked at the same rate as the main CPU (SYSCLKOUT).
• An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
• Program Address Bus (PAB) and Program Data Bus (PDB)
• Data Read Address Bus (DRAB), Data Read Data Bus (DRDB), Data Write Address Bus (DWAB), and
Data Write Data Bus (DWDB)
– Independent eight stage pipeline.
– 16-bit program counter (MPC)
– Four 32-bit result registers (MR0-MR3)
– Two 16-bit auxiliary registers (MAR0, MAR1)
– Status register (MSTF)
• Instruction set includes:
– IEEE single-precision (32-bit) floating-point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions.
– Conditional branch and call
– Data load/store operations
• The CLA program code can consist of up to eight tasks or interrupt service routines
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the configurable CLA program memory space.
– One task is serviced at a time until completion. There is no nesting of tasks.
– Upon task completion a task-specific interrupt is flagged within the PIE.
– When a task finishes the next highest-priority pending task is automatically started.
• Task trigger mechanisms:
– C28x CPU using the IACK instruction
– Task1 to Task8: trigger sources from peripherals connected to the shared bus on which the CLA assumes
secondary ownership.
• Memory and Shared Peripherals:
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.

7.1.2 CLA Related Collateral

Foundational Materials
• C2000 Academy - CLA
• C2000 CLA C Compiler Series (Video)
• CLA Hands On Workshop (Video)
• CLA usage in Valley Switching Boost Power Factor Correction (PFC) Reference Design (Video)
• Enhancing the Computational Performance of the C2000™ Microcontroller Family Application Report

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Getting Started Materials

• CLA Software Development Guide
• Software Examples to Showcase Unique Capabilities of TI's C2000™ CLA Application Report

Expert Materials
• Digital Control of Two Phase Interleaved PFC and Motor Drive Using MCU With CLA Application Report
• Sensorless Field Oriented Control:3-Phase Perm.Magnet Synch. Motors With CLA Application Report
7.1.3 Block Diagram
Figure 7-1 is a block diagram of the CLA.

CLA Control
Register Set

MIFR(16)
MPERINT1 MIOVF(16) CLA_INT1
From Shared to to
Peripherals MPERINT8 MICLR(16) CLA_INT8
MICLROVF(16) C28x
PIE INT11
MIFRC(16) CPU
MIER(16) INT12
MIRUN(16)
LVF
MCTLBGRND(16)
LUF
MSTSBGRND(16)
CLA1SOFTINTEN(16)
CLA1INTFRC(16)
SYSCLK
CLA Clock Enable MVECT1(16)
CPU Read/Write Data Bus
SYSRS MVECT2(16)
MVECT3(16)
MVECT4(16) CLA Program
MVECT5(16) CLA Program Bus Memory (LSx)
MVECT6(16)
MVECT7(16)
MVECT8(16) LSxMSEL[MSEL_LSx]
MVECTBGRND(16) LSxCLAPGM[CLAPGM_LSx]
MVECTBGRNDACTIVE(16)
MPSACTL(16)

CPU Data Bus

MPSA1(32) CLA Data
MPSA2(32) Memory (LSx)

MCTL(16)
CLA Data Bus

CLA Message
CLA Execution
RAMs
Register Set

MPC(16)
MSTF(32)
MR0(32)
MR1(32) Shared
MR2(32) MEALLOW Peripherals
MR3(32)
MAR0(16)
MAR1(16)
CPU Read Data Bus

Figure 7-1. CLA (Type 2) Block Diagram

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7.2 CLA Interface

This section describes how the C28x main CPU can interface to the CLA and conversely.
7.2.1 CLA Memory
The CLA can access three types of memory: program, data and message RAMs. The behavior and arbitration
for each type of memory is described in this chapter. The CLA RAMs are protected by the DCSM module. Refer
to the Dual Code Security Module (DCSM) chapter for more details on the security scheme.
• CLA Program Memory
The CLA program can be loaded with any of the local shared memories (LSxRAM). At reset, all memory
blocks are mapped to the CPU. While mapped to the CPU space, the CPU can copy the CLA program code
into the memory. During debug, the memory can also be loaded directly by the Code Composer Studio™
IDE.
Once the memory is initialized with CLA code, the CPU maps the memory to the CLA program space by:
1. Assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s
MemCfgRegs.LSxMSEL[MSEL_LSx] bit.
2. Specifying the memory block as a code block for the CLA by writing a 1 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit.
When a memory block is configured as CLA program memory, debug accesses are allowed only on cycles
where the CLA is not fetching a new instruction. A detailed explanation of the memory configurations and
access arbitration (CPU, CLA, and DEBUG) process can be found in the Memory Controller Module section
of the System Control and Interrupts chapter.
All CLA program fetches are performed as 32-bit read operations and all opcodes must be aligned to an even
address. Since all CLA opcodes are 32-bits, this alignment occurs naturally.

• CLA Data Memory

Any of the device’s LSxRAMs can serve as data memory blocks to the CLA. At reset, all blocks are mapped
to the CPU memory space, whereby the CPU can initialize the memory with data tables, coefficients, and so
on, for the CLA to use.
Once the memory is initialized with CLA data, the CPU maps the memory to the CLA data space by:
1. Assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s
MemCfgRegs.LSxMSEL[MSEL_LSx] bit.
2. Specifying the memory block as a data block for the CLA by writing a 0 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit. The value of this bit at reset is 0.
When a memory block is configured as CLA data memory, CLA read and write accesses are arbitrated along
with CPU accesses. The user has the option of turning on CPU fetch or write protection to the memory by
writing to the appropriate bits of the MemCfgRegs.LSxACCPROTx registers. A detailed explanation of the
memory configurations and access arbitration (CPU, CLA, and DEBUG) process can be found in the Memory
Controller Module section of the System Control and Interrupts chapter.
• CLA Shared Message RAMs
There are two memory blocks for data sharing and communication between the CLA and the CPU . The
message RAMs are always mapped to both CPU and CLA memory spaces, and only data access is allowed;
no program fetches can be performed.
– CLA to CPU Message RAM: The CLA can use this block to pass data to the CPU. This block is both
readable and writable by the CLA. This block is also readable by the CPU but writes by the CPU are
ignored.
– CPU to CLA Message RAM: The CPU can use this block to pass data and messages to the CLA. This
message RAM is both readable and writable by the CPU. The CLA can perform reads but writes by the
CLA are ignored.

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7.2.2 CLA Memory Bus

The CLA has dedicated bus architecture similar to that of the C28x CPU where there are separate program read,
data read, and data write buses. Thus, there can be simultaneous instruction fetch, data read, and data write in
a single cycle. Like the C28x CPU, the CLA expects memory logic to align any 32-bit read or write to an even
address. If the address-generation logic generates an odd address, the CLA can begin reading or writing at the
previous even address. This alignment does not affect the address values generated by the address-generation
logic.
• CLA Program Bus
The CLA program bus has an access range of 32-bit instructions. Since all CLA instructions are 32 bits, this
bus always fetches 32 bits at a time and the opcodes must be even-word aligned. The amount of program
space available for the CLA is limited to the number of blocks. This number is device-dependent and can be
described in the device-specific data manual.

• CLA Data Read Bus

The CLA data read bus has a 64K x 16 address range. The bus can perform 16 or 32-bit reads and can
automatically stall if there are memory access conflicts. The data read bus has access to both the message
RAMs, CLA data memory, and the shared peripherals.

• CLA Data Write Bus

The CLA data write bus has a 64K x 16 address range. This bus can perform 16 or 32-bit writes. The bus can
automatically stall if there are memory access conflicts. The data write bus has access to the CLA to CPU
message RAM, CLA data memory, and the shared peripherals.

7.2.3 Shared Peripherals and EALLOW Protection

Refer to the device data sheet for the list of peripherals connected to the bus.
Several peripheral control registers are protected from spurious 28x CPU writes by the EALLOW protection
mechanism. These same registers are also protected from spurious CLA writes. The EALLOW bit in the CPU
status register 1 (ST1) indicates the state of protection for the CPU. Likewise, the MEALLOW bit in the CLA
status register (MSTF) indicates the state of write protection for the CLA. The MEALLOW CLA instruction
enables write access by the CLA to EALLOW protected registers. Likewise, the MEDIS CLA instruction disables
write access. This way the CLA can enable and disable write access independent of the CPU.
The ADC offers the option to generate an early interrupt pulse at the start of a sample conversion. If this option
is used to start an ADC-triggered CLA task, use the intervening cycles until the completion of the conversion
to perform preliminary calculations or loads and stores before finally reading the ADC value. The CLA pipeline
activity for this scenario is shown in Section 7.5.

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7.2.4 CLA Tasks and Interrupt Vectors

The CLA program code is divided up into tasks or interrupt service routines. Tasks do not have a fixed starting
location or length. The CLA program memory can be divided up as desired. The CLA uses the contents of the
interrupt vectors (MVECT1 to MVECT8) to determine where a task begins; tasks are terminated by the MSTOP
instruction.
The CLA supports eight tasks. Task 1 has the highest priority and task 8 has the lowest priority. The Type-2
CLA offers the option of setting the lowest priority task, for example, task 8, as a background task that, once
triggered, runs continuously until the user either terminates the task or resets the CLA or the device. The
remaining tasks, 1 through 7, maintain their priority levels and interrupt the background task when triggered.
The background task is enabled by setting the BGEN bit in the MCTLBGRND register; this causes the hardware
to disable task 8 in the MIER register. The background task derives the interrupt vector from the MVECTBGRND
register instead of MVECT8.
A task can be requested by a peripheral interrupt or by software:
• Peripheral interrupt trigger
Each task can be triggered by software-selectable interrupt sources. The trigger for each task is defined by
writing an appropriate value to the DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx] bit field. Each option
specifies an interrupt source from a specific peripheral on the shared bus. The peripheral interrupt triggers
are listed in Table 7-1.
For example, task 1 (MVECT1) can be set to trigger on EPWMINT1 by writing 36 to
DmaClaSrcSelRegs.CLA1TASKSRCSEL1.TASK1. To disable the triggering of a task by a peripheral, set
the DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx] bit field to 0. Note that a CLA task only triggers on a
level transition (an edge) of the configured interrupt source.
Table 7-1. Configuration Options
Select Value CLA Trigger Source
0 CLA_SOFTWARE_TRIGGER
1 ADCAINT1
2 ADCAINT2
3 ADCAINT3
4 ADCAINT4
5 ADCA_EVT_INT
6 ADCBINT1
7 ADCBINT2
8 ADCBINT3
9 ADCBINT4
10 ADCB_EVT_INT
11 ADCCINT1
12 ADCCINT2
13 ADCCINT3
14 ADCCINT4
15 ADCC_EVT_INT
16-28 Reserved
29 XINT1
30 XINT2
31 XINT3
32 XINT4
33 XINT5
34-35 Reserved

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Table 7-1. Configuration Options (continued)

Select Value CLA Trigger Source
36 EPWM1_INT
37 EPWM2_INT
38 EPWM3_INT
39 EPWM4_INT
40 EPWM5_INT
41 EPWM6_INT
42 EPWM7_INT
43 EPWM8_INT
44-51 Reserved
52 MCANA_FEVT0
53 MCANA_FEVT1
54 MCANA_FEVT2
55-67 Reserved
68 CPU_TINT0
69 CPU_TINT1
70 CPU_TINT2
71-74 Reserved
75 ECAP1_INT
76 ECAP2_INT
77 ECAP3_INT
78-82 Reserved
83 EQEP1_INT
84 EQEP2_INT
85-88 Reserved
89 ECAP3_INT2
90-94 Reserved
95 SD1_ERRINT
96 SD1FLT1_DRINT
97 SD1FLT2_DRINT
98 SD1FLT3_DRINT
99 SD1FLT4_DRINT
100 SD2_ERRINT
101 SD2FLT1_DRINT
102 SD2FLT2_DRINT
103 SD2FLT3_DRINT
104 SD2FLT4_DRINT
105 PMBUSA_INT
106-108 Reserved
109 SPIA_TXINT
110 SPIA_RXINT
111 SPIB_TXINT
112 SPIB_RXINT
113-116 Reserved
117 LINA_INT1
118 LINA_INT0

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Table 7-1. Configuration Options (continued)

Select Value CLA Trigger Source
119 LINB_INT1
120 LINB_INT0
121 BGCRC_INT
122 Reserved
123 FSITXA_INT1
124 FSITXA_INT2
125 FSIRXA_INT1
126 FSIRXA_INT2
127 CLB1_INT
128 CLB2_INT
129 CLB3_INT
130 CLB4_INT
131-178 Reserved
179 HICA_INT
180-183 Reserved
184 DMA_CH1INT
185 DMA_CH2INT
186 DMA_CH3INT
187 DMA_CH4INT
188 DMA_CH5INT
189 DMA_CH6INT
190-255 Reserved

• Software Trigger
CPU software can trigger tasks by writing to the MIFRC register or by the IACK instruction. Using the
IACK instruction is more efficient because the instruction does not require the need to issue an EALLOW
to set MIFR bits. Set the MCTL[IACKE] bit to enable the IACK feature. Each bit in the operand of the IACK
instruction corresponds to a task. For example, IACK #0x0001 sets bit 0 in the MIFR register to start task 1.
Likewise, IACK #0x0003 set bits 0 and 1 in the MIFR register to start task 1 and task 2.
• Background Task
The Type-2 CLA allows the use of Task 8 as a background task that runs continuously until Task 8 disables
the task or resets the device (or the CLA using a soft reset). The background task vector is given by the
MVECTBGRND register and the operation is controlled by the MCTLBGRND register; the task is enabled
by setting the BGEN bit to 1. Then start the task through software by writing a 1 to the BGSTART bit
(TRIGEN must be 0), or through a peripheral by setting the TRIGEN bit to 1 and then setting the trigger
source in the bit-field, DmaClaSrcSelRegs.CLA1TASKSRCSEL2.bit.TASK8. By default, the background task
is interruptible; the highest priority pending task is executed first. When a task completes and there are not
any pending tasks, the execution returns to the background task. The CLA keeps track of the branching point
by saving the return address to the MVECTBGRNDACTIVE register, and then popping this address to the
MPC when execution returns. Choose to make sections of the background task uninterruptible by possibly
doing this with the MSETC BGINTM assembly instruction.
Subsequently, enabling interrupts with the MCLRC BGINTM instruction.
The background interrupt mask bit, BGINTM, can be queried in the MSTSBGRND register. This register also
provides the current status of the background task. If the task is currently executing, the RUN bit is set to 1, if
another trigger for the background task is received while the task has already started, the overflow (BGOVF)
bit is set.

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The CLA has their own fetch mechanism and can run and execute a task independently of the CPU. Only one
task is serviced at a time; there is no nesting of tasks unless the background task in enabled, then one level
of nesting is possible. The task currently running is indicated in the MIRUN register; if the background task is
enabled and running, the task is reflected in the MSTSBGRND register (the RUN bit).
Interrupts that have been received but not yet serviced are indicated in the flag register (MIFR). If an interrupt
request from a peripheral is received and that same task is already flagged, then the overflow flag bit is set.
Overflow flags remain set until the flags are cleared by the CPU. If the CLA is idle (no task is currently running)
or is executing the background task, then the highest priority interrupt request that is both flagged (MIFR) and
enabled (MIER) starts.
The flow is as follows:
1. The associated RUN register bit is set (MIRUN) and the flag bit (MIFR) is cleared.
2. The CLA begins execution at the location indicated by the associated interrupt vector (MVECTx). MVECT
contains the absolute 16-bit address of the task in the lower 64K memory space. If a task is interrupting
the background task then the current program address is stored in the MVECTBGRNDACTIVE register
before execution jumps to the task; this saved address is restored to the MPC when the task completes and
execution returns to the background task.
3. The CLA executes instructions until the MSTOP instruction is found. This indicates the end of the task.
4. The MIRUN bit is cleared.
5. The task-specific interrupt to the PIE is issued. This informs the main CPU that the task has completed.
6. The CLA returns to idle (or to the background task, if enabled). Once a task completes the next highest-
priority pending task is automatically serviced and this sequence repeats.

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7.3 CLA and CPU Arbitration

Typically, CLA activity is independent of the CPU activity. Under the circumstance where the CLA or CPU
attempt to concurrently access memory or a peripheral register within the same interface, an arbitration
procedure can occur. This section describes this arbitration.
The arbitration follows a fixed arbitration scheme with highest priority first:
Refer to the Memory Controller Module section of the System Control and Interrupts chapter.
7.3.1 CLA Message RAM
Message RAMs consist of blocks:
• CLA to CPU Message RAM
• CPU to CLA Message RAM
These blocks are useful for passing data between the CLA and CPU. No opcode fetches, from either the CLA
or CPU, are allowed from the message RAMs. A write protection violation is not generated if the CLA attempts
to write to the CPU to CLA message RAM, but the write is ignored. The arbitration scheme for the message
RAMs are the same as those for the shared memories, described in the Memory Controller Module section of
the System Control and Interrupts chapter.
The message RAMs have the following characteristics:
• CLA to CPU Message RAM:
The following accesses are allowed:
– CPU reads
– CLA data reads and writes
– CPU debug reads and writes
The following accesses are ignored:
– CPU writes
• CPU to CLA Message RAM:
The following accesses are allowed:
– CPU reads and writes
– CLA reads
– CPU debug reads and writes
The following accesses are ignored:
– CLA writes
7.3.2 Peripheral Registers (ePWM, HRPWM, Comparator)
Accesses to the registers follow these rules:
• If both the CPU and CLA request access at the same time, then the CLA has priority and the main CPU is
stalled.
• If a CPU access is in-progress and another CPU access is pending, then the CLA has priority over the
pending CPU access. In this case, the CLA access begins when the current CPU access completes.
• While a CPU access is in-progress, any incoming CLA access is stalled.
• While a CLA access is in-progress, any incoming CPU access is stalled.
• A CPU write operation has priority over a CPU read operation.
• A CLA write operation has priority over a CLA read operation.
• If the CPU is performing a read-modify-write operation and the CLA performs a write to the same location, the
CLA write can be lost if the operation occurs in-between the CPU read and write. For this reason, do not mix
CPU and CLA accesses to same location.

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7.4 CLA Configuration and Debug

This section discusses the steps necessary to configure and debug the CLA.
7.4.1 Building a CLA Application
The control law accelerator can be programmed in either CLA assembly code, using the instructions described
in Section 7.7, or a reduced subset of the C language. CLA assembly code resides in the same project with
C28x code. The only restriction is the CLA code must be in the assembly section. This can be easily done
using the .sect assembly directive. This does not prevent CLA and C28x code from being linked into the same
memory region in the linker command file.
System and CLA initialization are performed by the main CPU. This can typically be done in C or C++ but can
also include C28x assembly code. The main CPU also copies the CLA code to the program memory and, if
needed, initialize the CLA data RAMs. Once system initialization is complete and the application begins, the
CLA services the interrupts using the CLA assembly code (or tasks). The main CPU can perform other tasks
concurrently with CLA program execution.
7.4.2 Typical CLA Initialization Sequence
A typical CLA initialization sequence is performed by the main CPU as described in this section.
1. Copy CLA code into the CLA program RAM
The source for the CLA code can initially reside in the Flash or a data stream from a communications
peripheral or anywhere the main CPU can access. The debugger can also be used to load code directly to
the CLA program RAM during development.
2. Initialize CLA data RAM, if necessary
Populate the CLA data RAM with any required data coefficients or constants.
3. Configure the CLA registers
Configure the CLA registers, but keep interrupts disabled until later (leave MIER = 0):
• Enable the CLA peripheral clock using the assigned PCLKCRn register
The peripheral clock control (PCLKCRn) registers are defined in the System Control and Interrupts
chapter.
• Populate the CLA task interrupt vectors
– MVECT1 to MVECT8
• Select the task interrupt sources
For each task select the interrupt source in the CLA1TASKSRCSELx register. If a task is software
triggered, select no interrupt.
• Enable IACK to start a task from software, if desired
To enable the IACK instruction to start a task set the MCTL[IACKE] bit. Using the IACK instruction avoids
having to set and clear the EALLOW bit.
• Map CLA data RAM to CLA space, if necessary
• Map CLA program RAM to CLA space
4. Initialize the PIE vector table and registers
When a CLA task completes, the associated interrupt in the PIE is flagged. The CLA overflow and underflow
flags also have associated interrupts within the PIE.
5. Enable CLA tasks/interrupts
Set appropriate bits in the interrupt enable register (MIER) to allow the CLA to service interrupts. Note that a
CLA task only triggers on a level transition (a falling edge) of the configured interrupt source. If a peripheral
is enabled and an interrupt fires before the CLA is configured, then the CLA does not recognize the interrupt
edge and does not respond. To avoid this, configure the CLA before the peripherals or clear any pending
peripheral interrupts before setting bits in the MIER register.

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6. Initialize other peripherals

Initialize any peripherals (such as ePWM, ADC, and others) that generate interrupt triggers for enabled CLA
tasks.
The CLA is now ready to service interrupts and the message RAMs can be used to pass data between the
CPU and the CLA. Mapping of the CLA program and data RAMs typically occurs only during the initialization
process. If the RAM mapping needs to be changed after initialization, the CLA interrupts must be disabled
and all tasks must be completed (by checking the MIRUN register) prior to modifying the RAM ownership.

7.4.3 Debugging CLA Code

Debugging the CLA code is a simple process that occurs independently of the main CPU.
7.4.3.1 Software Breakpoint Support (MDEBUGSTOP1)
The MDEBUGSTOP1 instruction is meant to be used as a software breakpoint; the instruction on which the
execution must halt is replaced with this instruction.
The MDEBUGSTOP1 and MDEBUGSTOP instructions differ in how the CLA pipeline is treated. When halted,
the MDEBUGSTOP1 instruction flushes all the instructions that have already been fetched; on a single-step or
run-free command, the CLA refetches the same instruction that it replaced. Table 7-2 illustrates the pipeline
behavior.
Table 7-2. Pipeline Behavior of the MDEBUGSTOP1 Instruction
Cycles F1 F2 D1 D2 R1 R2 E W Comments
1 i1
2 i2 i1
3 i3 i2 i1
4 i4 i3 i2 i1
5 MDEBUG i4 i3 i2 i1
STOP1
6 i6 MDEBUG i4 i3 i2 i1
STOP1
7 i7 i6 MDEBUG i4 i3 i2 i1
STOP1
9 i8 Flushed Flushed Flushed i4 i3 i2 i1 CLA
(MNOP) (MNOP) (MNOP) halted
10 i5(MDEBUGS Flushed Flushed Flushed Flushed i4 i3 i2 CLA step/run
TOP1) (MNOP) (MNOP) (MNOP) (MNOP)
11 i6 i5(MDEBUGS Flushed Flushed Flushed Flushed i4 i3 CLA step/run
TOP1) (MNOP) (MNOP) (MNOP) (MNOP)
12 i7 i6 i5(MDEBUGS Flushed Flushed Flushed Flushed i4 CLA step/run
TOP1) (MNOP) (MNOP) (MNOP) (MNOP)
13 i8 i7 i6 i5(MDEBUGS Flushed Flushed Flushed Flushed CLA step/run
TOP1) (MNOP) (MNOP) (MNOP) (MNOP)

A software breakpoint is placed at instruction i5. The instruction, i5, is then replaced with MDEBUGSTOP1. It
takes 3 cycles for the MDEBUGSTOP1 to reach the D2 phase at which point the instructions i6, i7, and i8 that
were previously fetched are now flushed from the pipeline. The instruction, i5, is then re-fetched and execution
continues as before.

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7.4.3.2 Breakpoint Support (MDEBUGSTOP)

1. Insert a breakpoint in CLA code
Insert a CLA breakpoint (MDEBUGSTOP instruction) into the code where the CLA is to halt, then rebuild
and reload the code. Because the CLA does not flush the pipeline when in single-step, the MDEBUGSTOP
instruction must be inserted as part of the code. The debugger cannot insert the MDEBUGSTOP instruction
as needed.
If CLA breakpoints are not enabled, then the MDEBUGSTOP instruction is ignored and is treated
as a MNOP. The MDEBUGSTOP instruction can be placed anywhere in the CLA code as long as
the MDEBUGSTOP instruction is not within three instructions of a MBCNDD, MCCNDD, or MRCNDD
instruction. When programming in C, the user can use the __mdebugstop() intrinsic instead; the compiler
makes sure that the placement of the MDEBUSTOP instruction in the generated assembly does not violate
any of the pipeline restrictions.
2. Enable CLA breakpoints
Enable the CLA breakpoints in the debugger. In the Code Composer Studio™ IDE, this is done by
connecting to the CLA core (or tap) from the debug perspective. Breakpoints are disabled when the core is
disconnected.
3. Start the task
There are three ways to start the task:
a. The peripheral can assert an interrupt,
b. The main CPU can execute an IACK instruction, or
c. The user can manually write to the MIFRC register in the debugger window
When the task starts, the CLA executes instructions until the MDEBUGSTOP is in the D2 phase of the
pipeline. At this point, the CLA halts and the pipeline is frozen. The MPC register reflects the address of the
MDEBUGSTOP instruction.

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4. Single-step the CLA code

Once halted, the user can single-step the CLA code. The behavior of a CLA single-step is different than the
main C28x. When issuing a CLA single-step, the pipeline is clocked only one cycle and then again frozen.
On the C28x CPU, the pipeline is flushed for each single-step.
Run to the next MDEBUGSTOP or to the end of the task. If another task is pending, the task automatically
starts when run to the end of the task.

Note
A CLA fetch has higher priority than CPU debug reads. For this reason, it is possible for the
CLA to permanently block CPU debug accesses if the CLA is executing in a loop. This can occur
when initially developing CLA code due to a bug that causes an infinite loop. To avoid locking up
the main CPU, the program memory returns all 0x0000 for CPU debug reads when the CLA is
running. When the CLA is halted or idle, then normal CPU debug read and write access to CLA
program memory can be performed.
If the CLA gets caught in an infinite loop, use a soft or hard reset to exit the condition. A debugger
reset also exits the condition.

There are special cases that can occur when single-stepping a task such that the program counter, MPC,
reaches the MSTOP instruction at the end of the task.
• MPC halts at or after the MSTOP with a task already pending
If single-stepping or halted in "task A" and "task B" comes in before the MPC reaches the MSTOP, then
"task B" starts if continuing to step through the MSTOP instruction. Basically, if "task B" is pending before
the MPC reaches MSTOP in "task A" then there is no issue in "task B" starting and no special action is
required.
• MPC halts at or after the MSTOP with no task pending
In this case, if single-stepped or halted in "task A" and the MPC has reached the MSTOP with no tasks
pending. If "task B" comes in at this point, "task B" is flagged in the MIFR register but "task B" can or can
not start if continuing to single-step through the MSTOP instruction of "task A."
Depending on exactly when the new task comes in, to reliably start "task B", perform a soft reset and
reconfigure the MIER bits. Once this is done, start single-stepping "task B."
This case can be handled slightly differently if there is control over when "task B" comes in (for example,
using the IACK instruction to start the task). In this case, the task is single-stepped or halted in "task A"
and the MPC has reached the MSTOP with no tasks pending. Before forcing "task B," run free to force
the CLA out of the debug state. Once this is done, force "task B" and continue debugging.
5. Disable CLA breakpoints, if desired
In the Code Composer Studio™ IDE, disable the CLA breakpoints by disconnecting the CLA core in the
debug perspective. Make sure to first issue a run or reset; otherwise, the CLA is halted and no other tasks
start.

7.4.4 CLA Illegal Opcode Behavior

If the CLA fetches an opcode that does not correspond to a legal instruction, it will behave as follows:
• The CLA will halt with the illegal opcode in the D2 phase of the pipeline as if it were a breakpoint. This will
occur whether CLA breakpoints are enabled or not.
• The CLA will issue the task-specific interrupt to the PIE.
• The MIRUN bit for the task will remain set.
Further single-stepping is ignored once execution halts due to an illegal op-code. To exit this situation, issue
either a soft or hard reset of the CLA as described in Section 7.4.5.

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7.4.5 Resetting the CLA

There are times when resetting the CLA is needed. For example, during code debug the CLA can enter an
infinite loop due to a code bug. The CLA has two types of resets: hard and soft. Both of these resets can be
performed by the debugger or by the main CPU.
• Hard Reset Writing a 1 to the MCTL[HARDRESET] bit performs a hard reset of the CLA. The behavior of a
hard reset is the same as a system reset (using XRS or the debugger). In this case, all CLA configuration and
execution registers can be set to their default state and CLA execution halts.
• Soft Reset Writing a 1 to the MCTL[SOFTRESET] bit performs a soft reset of the CLA. If a task is executing,
the task halts and the associated MIRUN bit is cleared. All bits within the interrupt enable (MIER) register are
also cleared, so that no new tasks start.
7.5 Pipeline
This section describes the CLA pipeline stages and presents cases where pipeline alignment must be
considered.
7.5.1 Pipeline Overview
The CLA pipeline is very similar to the C28x pipeline with eight stages:
1. Fetch 1 (F1): During the F1 stage the program read address is placed on the CLA program address bus.
2. Fetch 2 (F2): During the F2 stage the instruction is read using the CLA program data bus.
3. Decode 1 (D1): During D1 the instruction is decoded.
4. Decode 2 (D2): Generate the data read address. Changes to MAR0 and MAR1 due to post-increment using
indirect addressing takes place in the D2 phase. Conditional branch decisions are also made at this stage
based on the MSTF register flags.
5. Read 1 (R1): Place the data read address on the CLA data-read address bus. If a memory conflict exists,
the R1 stage will be stalled.
6. Read 2 (R2): Read the data value using the CLA data read data bus.
7. Execute (EXE): Execute the operation. Changes to MAR0 and MAR1 due to loading an immediate value or
value from memory take place in this stage.
8. Write (W): Place the write address and write data on the CLA write data bus. If a memory conflict exists, the
W stage will be stalled.

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7.5.2 CLA Pipeline Alignment

The majority of the CLA instructions do not require any special pipeline considerations. This section lists the few
operations that do require special consideration.
• Write Followed by Read
In both the C28x pipeline and the CLA pipeline, the read operation occurs before the write. This means that
if a read operation immediately follows a write, then the read completes first as shown in Table 7-3. In most
cases this does not cause a problem since the contents of one memory location does not depend on the
state of another. For accesses to peripherals where a write to one location can affect the value in another
location, the code must wait for the write to complete before issuing the read as shown in Table 7-4.
This behavior is different for the C28x CPU. For the C28x CPU, any write followed by read to the same
location is protected by what is called write-followed-by-read protection. This protection automatically stalls
the pipeline so that the write completes before the read. In addition, some peripheral frames are protected
such that a C28x CPU write to one location within the frame always completes before a read to the frame.
The CLA does not have this protection mechanism. Instead, the code must wait to perform the read.
Table 7-3. Write Followed by Read - Read Occurs First
Instruction F1 F2 D1 D2 R1 R2 E W
I1 MMOV16 @Reg1, MR3 I1
I2 MMOV16 MR2, @Reg2 I2 I1
I2 I1
I2 I1
I2 I1
I2 I1
I2 I1
I2 I1

Table 7-4. Write Followed by Read - Write Occurs First

Instruction F1 F2 D1 D2 R1 R2 E W
I1 MMOV16 @Reg1, MR3 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
I5 MMOV16 MR2, @Reg2 I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3
I5 I4
I5

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• Delayed Conditional instructions: MBCNDD, MCCNDD, and MRCNDD

Referring to Example 7-1, the following applies to delayed conditional instructions:
– I1: I1 is the last instruction that can effect the CNDF flags for the branch, call, or return instruction. The
CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is made whether to branch or
not when MBCNDD, MCCNDD, or MRCNDD is in the D2 phase.
– I2, I3, and I4: The three instructions preceding MBCNDD can change the MSTF flags but have no effect
on whether the MBCNDD instruction branches or not. This is because the flag modification occurs after
the D2 phase of the branch, call, or return instruction. These three instructions must not be a MSTOP,
MDEBUGSTOP, MBCNDD, MCCNDD, or MRCNDD.
– I5, I6, and I7: The three instructions following a branch, call, or return are always executed irrespective of
whether the condition is true or not. These instructions must not be MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.
For a more detailed description, refer to the description for MBCNDD, MCCNDD, and MRCNDD.

Example 7-1. Code Fragment For MBCNDD, MCCNDD, or MRCNDD

<Instruction 1> ; I1 Last instruction that can affect flags for

; the branch, call or return operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
<branch/call/ret> ; MBCNDD, MCCNDD or MRCNDD
; I5-I7: Three instructions after are always
; executed whether the branch/call or return is
; taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8
<Instruction 9> ; I9
....

• Stop or Halting a Task: MSTOP and MDEBUGSTOP

The MSTOP and MDEBUGSTOP instructions cannot be placed three instructions before or after a conditional
branch, call or return instruction (MBCNDD, MCCNDD, or MRCNDD). Refer to Example 7-1. To single-step
through a branch/call or return, insert the MDEBUGSTOP at least four instructions back and step from there.

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• Loading MAR0 or MAR1

A load of auxiliary register MAR0 or MAR1 occurs in the EXE phase of the pipeline. Any post increment of
MAR0 or MAR1 using indirect addressing occurs in the D2 phase of the pipeline. Referring to Example 7-2,
the following applies when loading the auxiliary registers:
– I1 and I2
The two instructions following the load instruction use the value in MAR0 or MAR1 before the update
occurs.
– I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-increment addressing
occur in the D2 phase. Thus I3 cannot use the auxiliary register or there is a conflict. In the case of a
conflict, the update due to address-mode post increment wins and the auxiliary register is not updated with
#_X.
– I4
Starting with the 4th instruction MAR0 or MAR1 has the new value.

Example 7-2. Code Fragment for Loading MAR0 or MAR1

; Assume MAR0 is 50 and #_X is 20

MMOVI16 MAR0, #_X ; Load MAR0 with address of X (20)

<Instruction 1> ; I1 Will use the old value of MAR0 (50)
<Instruction 2> ; I2 Will use the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Will use the new value of MAR0 (20)
<Instruction 5> ; I5 Will use the new value of MAR0 (20
....

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7.5.2.1 ADC Early Interrupt to CLA Response

The ADC can be configured to generate an early interrupt pulse before the ADC conversion completes. If this
option is used to start a CLA task, the CLA is able to read the result as soon as the conversion result is available
in the ADC result register. This combination of just-in-time sampling along with the low interrupt response of the
CLA enable faster system response and higher frequency control loops. The CLA task trigger to first instruction
fetch interrupt latency is 4 cycles.
Timings for ADC conversions are shown in the timing diagrams of the ADC chapter. If the ADCCLK is a divided
down version of the SYSCLK, the user has to account for the conversion time in SYSCLK cycles.
From a CLA perspective, the pipeline activity is shown in Table 7-5 for an N-cycle (SYSCLK) ADC conversion.
The N-2 instruction arrives in the R2 phase just in time to read the result register. While the prior instructions
enter the R2 phase of the pipeline too soon to read the conversion, the instructions can be efficiently used for
pre-processing calculations needed by the task.
Table 7-5. ADC to CLA Early Interrupt Response
ADC Activity CLA Activity F1 F2 D1 D2 R1 R2 E W
Sample
Sample
...
Sample
Conversion(Cycle 1) Interrupt Received
Conversion(Cycle 2) Task Startup
Conversion(Cycle 3) Task Startup
Conversion(Cycle 4) I(Cycle 4) I(Cycle 4)
Conversion(Cycle 5) I(Cycle 5) I(Cycle 5) I(Cycle 4)
Conversion(...) ... ... ... ... ... ... ...
Conversion(Cycle N-6) I(Cycle N-6) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8) I(Cycle N-9) I(Cycle N-10) I(Cycle N-11)
Conversion(Cycle N-5) I(Cycle N-5) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8) I(Cycle N-9) I(Cycle N-10)
Conversion(Cycle N-4) I(Cycle N-4) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8) I(Cycle N-9)
Conversion(Cycle N-3) I(Cycle N-3) I(Cycle N-3) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8)
Read
Conversion(Cycle N-2) Read RESULT I(Cycle N-3) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7)
RESULT
Read
Conversion(Cycle N-1) I(Cycle N-3) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6)
RESULT
Read
Conversion(Cycle N-0) I(Cycle N-3) I(Cycle N-4) I(Cycle N-5)
RESULT
Read
Conversion Complete I(Cycle N-3) I(Cycle N-4)
RESULT
Read
RESULT Latched I(Cycle N-3)
RESULT
Read
RESULT Available
RESULT

The ADCINTCYCLE register of the ADC can be programmed by the application to adjust the generation of the
interrupt pulse to align with the ADC read operation. For example, if the first instruction in the task reads the
ADC and the conversion time is N SYSCLK cycles, then the delay programmed is (N-2) - 4 = N-6.

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7.5.3 Parallel Instructions

Parallel instructions are single opcodes that perform two operations in parallel. The following types of parallel
instructions are available: math operation in parallel with a move operation, or two math operations in parallel.
Both operations complete in a single cycle and there are no special pipeline alignment requirements.
Example 7-3. Math Operation with Parallel Load

; MADDF32 || MMOV32 instruction: 32-bit floating-point add with parallel move

; MADDF32 is a 1 cycle operation
; MMOV32 is a 1 cycle operation
MADDF32 MR0, MR1, #2 ; MR0 = MR1 + 2,
|| MMOV32 MR1, @Val ; MR1 gets the contents of Val
; <-- MMOV32 completes here (MR1 is valid)
; <-- DDF32 completes here (MR0 is valid)
MMPYF32 MR0, MR0, MR1 ; Any instruction, can use MR1 and/or MR0

Example 7-4. Multiply with Parallel Add

; MMPYF32 || MADDF32 instruction: 32-bit floating-point multiply with parallel add

; MMPYF32 is a 1 cycle operation
; MADDF32 is a 1 cycle operation
MMPYF32 MR0, MR1, MR3 ; MR0 = MR1 * MR3
|| MADDF32 MR1, MR2, MR0 ; MR1 = MR2 + MR0 (Uses value of MR0 before MMPYF32)
; <-- MMPYF32 and MADDF32 complete here (MR0 and MR1 are valid)
MMPYF32 MR1, MR1, MR0 ; Any instruction, can use MR1 and/or MR0

7.5.4 CLA Task Execution Latency

The CLA task execution latency depends on the state of the system:
• CLA task trigger of new task (normal or background) without background task active:
Task takes 8 cycles from CLA task trigger to first instruction of task to reach the D2 phase of pipeline.

Note
If background task has been configured in the system, then the compiler during code compilation
adds context save instructions at the start of each regular task and restore instructions at end
of each task so that register content can be saved and restored in case a background task
is executing while the regular task is triggered. When a regular task is entered, this compiler-
generated context save instruction is the first instruction of the task.
• CLA task trigger of normal task when background task is active:
Task takes 9 cycles from CLA task trigger to first instruction of normal task to reach the D2 phase of pipeline.
There is a difference of one clock cycle to force the MSTOP in the D2 phase of the background task before
the task exits as compared to a new task trigger without the background task active.

Note
If the MBCNDD/MCCNDD/MRCNDD instructions in the background task are in the D2 phase of the
pipeline when a new task gets triggered, the task takes a minimum of 3 more cycles to complete
these uninterruptible instructions adding to the delay.
• Returning to background task from normal task:
The task takes 5 cycles to return from a normal task to resume the background task instruction at the D2
phase of the pipeline.

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7.6 Software
7.6.1 CLA Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/cla
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
7.6.1.1 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
FILE: cla_ex1_asin.c
In this example, Task 1 of the CLA will calculate the arcsine of an input argument in the range (-1.0 to 1.0) using
a lookup table.
Note that since this example does not use background CLA task, the compile flag cla_background_task is
turned off for this project. Set this flag as on to enable background CLA task. The option is available in Project
Properties -> C2000 Build -> C2000 Compiler -> Advanced Options -> Runtime Model Options.
Memory Allocation
• CLA1 Math Tables (RAMLS1)
– CLAasinTable - Lookup table
• CLA1 to CPU Message RAM
– fResult - Result of the lookup algorithm
• CPU to CLA1 Message RAM
– fVal - Sample input to the lookup algorithm
Watch Variables
• fVal - Argument to task 1
• fResult - Result of arcsin(fVal)
7.6.1.2 CLA arctangent(x) using a lookup table (cla_atan_cpu01)
FILE: cla_ex2_atan.c
In this example, Task 1 of the CLA will calculate the arctangent of an input argument using a lookup table.
Note that since this example does not use background CLA task, the compile flag cla_background_task is
turned off for this project. Set this flag as on to enable background CLA task. The option is available in Project
Properties -> C2000 Build -> C2000 Compiler -> Advanced Options -> Runtime Model Options.
Memory Allocation
• CLA1 Math Tables (RAMLS1)
– CLAatan2Table - Lookup table
• CLA1 to CPU Message RAM
– fResult - Result of the lookup algorithm
• CPU to CLA1 Message RAM
– fNum - Numerator of sample input
– fDen - Denominator of sample input
Watch Variables
• fVal - Argument to task 1
• fResult - Result of arctan(fVal)
7.6.1.3 CLA background nesting task
FILE: cla_ex3_background_nesting_task.c
This example configures CLA task 1 to be triggered by EPWM1 running at 2 Hz (period = 0.5s). A background
task is configured to be triggered by CPU timer running at .5 Hz (period = 2s). CLA task 1 toggles LED1 at the

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start and end of the task and the background task toggles LED2 at the start and end of the task. Background
task will be preempted by Task1 and hence LED1 will be toggling even while LED2 is ON.
Note that the compile flag cla_background_task is turned on in this project. Enabling background task adds
additional context save/restore cycles during task switching thus increasing the overall trigger-to-task latency.
If the application does not use the background CLA task, it is recommended to turn this flag off for better
performance. The option is available in Project Properties -> C2000 Build -> C2000 Compiler -> Advanced
Options -> Runtime Model Options.
External Connections
• None
Watch Variables
• None
7.6.1.4 Controlling PWM output using CLA
FILE: cla_ex4_pwm_control.c
This example showcases how to update PWM signal output using CLA. EPWM1 is configured to generate
complementary signals on both of its channels of fixed frequency 100 KHz. EPWM4 is configured to trigger a
periodic CLA control task of frequency 10 KHz. The CLA task implements a very simple logic to vary the duty of
the EPWM1 outputs by increasing it by 0.1 in every iteration and maintaining it in the range of 0.1-0.9. For actual
use-cases, the control logic could be modified to much more complex depending upon the application. The other
CLA task (CLA task 8) is triggered by software at beginning to initialize the CLA global variables
External Connections
• Observe GPIO0 (EPWM1A) on oscilloscope
• Observe GPIO1 (EPWM1B) on oscilloscope
Watch Variables
• duty
7.6.1.5 Just-in-time ADC sampling with CLA
FILE: cla_ex5_adc_just_in_time.c
This example showcases how to utilize early-interrupt feature of ADC in combination with the low interrupt
response of CLA to enable faster system response and achieve high frequency control loops. EPWM1 is
configured to generate a PWM output signal of frequency 1 MHz and this is also used to trigger the ADC
sampling at each cycle. ADCA is configured to sample the input on Channel 0 and to generate the early interrupt
at the end of S/H + offset cycles. This interrupt is used to trigger the CLA control task. The CLA task implements
the control logic to update the duty of the PWM output based on reading the ADC sample data just-in-time i.e.
as soon as the ADC results gets latched.The early interrupt feature and low interrupt latency of CLA allows
to do some pre-processing as well before reading the ADC data and still completes updating the PWM output
before the next interrupts comes in i.e. data read and PWM update is done within a 1 MHz cycle. For illustration
purposes, 3-point moving average filter is used to simulate some processing and few steps of the filtering code
are done before reading the ADC result which we consider as pre-processing code. The ADC interrupt offset is
programmed based on the cycles consumed by the pre-processing code.
The calculation for interrupt offset value is as follows :- -ADC acquisition cycles programmed = 10 SYSCLKS
-Conversion time for 12-bit data = 10.5 ADCCLKS = N = 42 SYSCLKS -CLA task trigger to first instruction in
Fetch delay = 4 -Let the interrupt offset value be 'x' -The code inside CLA control task before ADC read takes
below cycles : Setting up profiling gpio : 3 cycles Pre-processing : 13 cycles Total = 3 + 13 = 16 cycles
As described in device TRM, in order to read just-in-time the total delay before reading ADC should be (N-2)
cycles = 40 i.e. : x + 4 + 16 = 40 : x = 20
NOTE :- The optimization is off for this project and the cycles quoted above corresponds to that case.
GPIO2 is used for profiling purposes. GPIO2 is set at the beginning of CLA task 1 and is reset at the end of the
task. Thus ON time of GPIO2 indicates the CLA activity. In order to validate the example functionality , observe

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the GPIO0 (PWM output) and GPIO2 (profiling GPIO) on CRO. The cycles difference between the rising edge of
the GPIO0 and GPIO2 indicate the total delay from the time of ADC trigger to setting up of profiling GPIO inside
CLA task which should be around 44 cycles (367 ns) based on the above calculation.
External Connections
• Provide constant DC input on ADCA0 for quick validation. GND -> Should observe PWM output duty = 0.1
3.3V -> Should observe PWM output duty = 0.9 Can also provide analog input in range 0 - 3.3V upto fs / 10 =
100 KHz for observing continuous duty variations
• Observe GPIO0 on oscilloscope
• Observe GPIO2 on oscilloscope
Watch Variables
• None
7.6.1.6 Optimal offloading of control algorithms to CLA
FILE: cla_ex6_cpu_offloading.c
This example showcases how to optimally offload the control algorithms from CPU to CLA in order to meet the
system requirements. In this example, two control loops are simulated, the faster one (loop1) running at 200 KHz
and the slower one (loop2) running at 20 KHz. Loop1 senses the first parameter at ADCA Channel 0, runs the
PI controller to achieve the target and contributes to the duty of EPWM1A output with 80% weightage. Loop2
senses the second parameter at ADCB Channel 2, runs the PI controller and contributes to the duty of EPWM1A
output with 20% weightage. It is important to note that since these are just software simulated control loops but
there is no actual physical process involved and hence updating the duty is not going to have any affect on
sampled inputs. ADCA is configured to oversample the first parameter using SOCs 0-3 to suppress the noise
and similarly ADCB is used to oversample the second parameter. EPWM4 and EPWM5 are configured to trigger
the ADCA and ADCB sampling at loop1 and loop2 frequencies respectively. Once the conversion of all 4 SOCs
complete, a CPU ISR or a CLA task is triggered based on the user-configuration. There is also a background
task running in the main loop which disables the entire system including PWM output and the control loops
when "system_OFF" is set to 1. The system gets enabled again once "system_OFF" is restored back to 0. By
default system_OFF is set to 0 but it's value can be updated dynamically by adding it to expression window and
writing to it. DCL library is included in the project to make use of optimal PI controllers used in both the loops.
User-configurable pre-defined symbol "run_loop1_cla" has been added to the project options in order to specify
whether to run the loop1 on C28x or CLA. GPIO2 and GPIO3 are used to profile the execution of loop1 and
loop2.
For run_loop1_cla == 0 i.e. both loops running on CPU -> Loop1 Utilization = ~77.5% (measured using profiling
GPIO2) -> Loop2 Utilization = ~6% (measured using profiling GPIO3) -> Background task in a while loop ->
Total CPU utilization is greater than Utilization bound (UB) Hence the system is non-schedulable, lower priority
task (Loop2) execution never completes (no toggling observed on GPIO3) and also background task never gets
chance to execute
For run_loop1_cla == 1 i.e. high frequency control loop (loop1) is offloaded to CLA while loop2 runs on CPU ->
Loop1 Utilization (CLA) = ~73% -> Loop2 Utilization (CPU)= ~6% -> Total CPU utilization has come down to just
~6% Hence the system is perfectly schedulable, no miss happens for any of the loops and offloading of loop1 to
CLA saves CPU bandwidth to execute background tasks as well
For quick inspection of the example functionality, constant DC HIGH/LOW inputs can be provided to the analog
channels instead of varying analog voltages. The target value for both the loops are set as some intermediate
value i.e. 3500 corresponds to ~2.8V. Now since the sensed inputs are constant and not same as target so the
controller outputs will get saturated soon to either 1 or 0. Thus the "duty" variable can take only fixed values
based on the equations used in the loops. Infact the duty output would be very intutive, for instance if both inputs
are LOW(GND), the controller will try to produce the maximum duty as the target is higher than sensed value
hence the duty should be 1.0(0.2 + 0.8) but will get saturated to 0.9(the maximum value defined). Similarly if
both inputs are made HIGH, the duty will be 0.1 (the minimum saturation value defined). The final duty table is
shown below :
External Connections

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• Observe GPIO2 (Loop1 Profiling) on oscilloscope

• Observe GPIO3 (Loop2 Profiling) on oscilloscope
• Observe GPIO0 (EPWM1A Output) on oscilloscope
• Provide constant HIGH(3.3V)/LOW(0V) on both ADCA Ch0 and ADCB Ch2 for quick validation, the following
duty value should be observable at EPWM1A for various combinations if the system is perfectly schedulable
i.e. both loops gets chance to execute properly :- A0 B2 duty GND GND 0.9 3.3V GND 0.2 GND 3.3V 0.8
3.3V 3.3V 0.1
Note :- The optimization is OFF for this project and all the profiling data quoted above corresponds to this case.
7.6.1.7 Handling shared resources across C28x and CLA
FILE: cla_ex7_shared_resource_handling.c
This example showcases how to handle shared resource challenges across C28x and CLA. As the peripherals
are shared between CLA and the CPU, overlapping read-modify-write to the registers by them can lead to data
race conditions ultimately leading to data violation or incorrect functionality. In this example, CPU ISR and CLA
tasks runs independently. CPU ISR gets triggered by EPWM4 @10KHz and toggles the EPWM1B output via
software by controlling CSFB bits of AQCSFRC. CLA task gets triggered by EPWM5 @100Khz and toggles the
EPWM1A output via software by controlling CSFA bits of AQCSFRC. Thus in this process both CPU and CLA
do read-modify -write to AQCSFRC register independently at different frequencies so there is chance of race
condition and updates due to one of them can get lost/. overwritten. This can be clearly observed by updating
"phase_shift_ON" to 0U and probing the EPWM1A and 1B outputs on a scope.
This is a standard critical section problem and can be handled by software handshaking mechanism like
mutex etc. But most of the real-time control applications are time-sensitive and cannot afford addition software
overhead hence this example suggests an alternative hardware based technique to avoid shared resource
conflicts between CPU and CLA. The phase shifting mechanism of the EPWM modules is utilized to schedule
the CLA task and CPU ISR as desired. EPWM4 generates a synchronous pulse every ZERO event and provides
a phase shift of 20 cycles to EPWM5. This way both CLA task and C28x ISR runs at original frequencies
i.e. 100KHz and 10KHz but CLA task leads with a phase offset of 20 cycles wrt CPU ISR. Hence concurrent
read-modify-writes to AQCSFRC never happens and the EPWM1A and EPWM1B outputs behave as desired
i.e. consistent 50 KHz PWM output on EPWM1A and 5 KHz PWM output on EPWM1B with a duty ~50% on
both should be generated. In order to utilize this phase shifting mechanism in this example, please make sure
"phase_shift_ON" is set to 1.
External Connections
• Observe GPIO0 (EPWM1A Output) on oscilloscope
• Observe GPIO1 (EPWM1B Output) on oscilloscope
• Observe GPIO2 (CLA Task Profiling) on oscilloscope
• Observe GPIO3 (CPU ISR Profiling) on oscilloscope
Note :- The phase offset value can easily be configured by updating TBPHS register to schedule the CLA task
and C28x ISR as desired depending upon the application need so as to avoid overlapping register writes by
CPU and CLA
Note :- The optimization is on and set to O2 for the project and all the results quoted correspond to this case.

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7.7 Instruction Set

This section describes the assembly language instructions of the control law accelerator. Also described are
parallel operations, conditional operations, resource constraints, and addressing modes. The instructions listed
here are independent from C28x and C28x+FPU instruction sets.
7.7.1 Instruction Descriptions
This section gives detailed information on the instruction set. Each instruction may present the following
information:
• Operands
• Opcode
• Description
• Exceptions
• Pipeline
• Examples
• See also
The example INSTRUCTION is shown to familiarize you with the way each instruction is described. The example
describes the kind of information you will find in each part of the individual instruction description and where to
obtain more information. CLA instructions follow the same format as the C28x; the source operand(s) are always
on the right and the destination operand(s) are on the left.
The explanations for the syntax of the operands used in the instruction descriptions for the C28x CLA are given
in Table 7-6.
Table 7-6. Operand Nomenclature
Symbol Description
#16FHi 16-bit immediate (hex or float) value that represents the upper 16-bits of an IEEE 32-bit floating-point value.
Lower 16-bits of the mantissa are assumed to be zero.
#16FHiHex 16-bit immediate hex value that represents the upper 16-bits of an IEEE 32-bit floating-point value.
Lower 16-bits of the mantissa are assumed to be zero.
#16FLoHex A 16-bit immediate hex value that represents the lower 16-bits of an IEEE 32-bit floating-point value
#32Fhex 32-bit immediate value that represents an IEEE 32-bit floating-point value
#32F Immediate float value represented in floating-point representation
#0.0 Immediate zero
#SHIFT Immediate value of 1 to 32 used for arithmetic and logical shifts.
addr Opcode field indicating the addressing mode
CNDF Condition to test the flags in the MSTF register
FLAG Selected flags from MSTF register (OR) 8 bit mask indicating which floating-point status flags to change
MAR0 auxiliary register 0
MAR1 auxiliary register 1
MARx Either MAR0 or MAR1
mem16 16-bit memory location accessed using direct, indirect, or offset addressing modes
mem32 32-bit memory location accessed using direct, indirect, or offset addressing modes
MRa MR0 to MR3 registers
MRb MR0 to MR3 registers
MRc MR0 to MR3 registers
MRd MR0 to MR3 registers
MRe MR0 to MR3 registers
MRf MR0 to MR3 registers
MSTF CLA Floating-point Status Register
shift Opcode field indicating the number of bits to shift.

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Table 7-6. Operand Nomenclature (continued)

Symbol Description
VALUE Flag value of 0 or 1 for selected flag (OR) 8 bit mask indicating the flag value; 0 or 1

Each instruction has a table that gives a list of the operands and a short description. Instructions always have
their destination operand(s) first followed by the source operand(s).
Table 7-7. INSTRUCTION dest, source1, source2 Short Description
Description
dest1 Description for the 1st operand for the instruction
source1 Description for the 2nd operand for the instruction
source2 Description for the 3rd operand for the instruction
Opcode This section shows the opcode for the instruction
Description Detailed description of the instruction execution is described. Any constraints on the operands imposed by the
processor or the assembler are discussed.
Restrictions Any constraints on the operands or use of the instruction imposed by the processor are discussed.
Pipeline This section describes the instruction in terms of pipeline cycles as described in Section 7.5
Example Examples of instruction execution. If applicable, register and memory values are given before and after instruction
execution. Some examples are code fragments while other examples are full tasks that assume the CLA is correctly
configured and the main CPU has passed it data.
Operands Each instruction has a table that gives a list of the operands and a short description. Instructions always have their
destination operand(s) first followed by the source operand(s).

7.7.2 Addressing Modes and Encoding

The CLA uses the same address to access data and registers as the main CPU. For example, if the main CPU
accesses an ePWM register at address 0x00 6800, then the CLA accesses the register using address 0x6800.
Since all CLA accessible memory and registers are within the low 64k x 16 of memory, only the low 16-bits of the
address are used by the CLA.
To address the CLA data memory, message RAMs and shared peripherals, the CLA supports two addressing
modes:
• Direct addressing mode: Uses the address of the variable or register directly.
• Indirect addressing with 16-bit post increment. This mode uses either XAR0 or XAR1.
The CLA does not use a data page pointer or a stack pointer. The two addressing modes are encoded as shown
Table 7-8.

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Table 7-8. Addressing Modes

Addressing Mode 'addr' Opcode Description
Field
Encode(1)
@dir 0000 Direct Addressing Mode
Example 1: MMOV32 MR1, @_VarA
Example 2: MMOV32 MR1, @_EPwm1Regs.CMPA.all
In this case, the 'mmmm mmmm mmmm mmmm' opcode field is populated with the 16-bit
address of the variable. This is the low 16-bits of the address to access the variable using the
main CPU.
For example, @_VarA populates the address of the variable VarA. and
@_EPwm1Regs.CMPA.all populates the address of the CMPA register.
*MAR0[#imm16]++ 0001 MAR0 Indirect Addressing with 16-bit Immediate Post Increment
*MAR1[#imm16]++ 0010 MAR1 Indirect Addressing with 16-bit Immediate Post Increment
addr = MAR0 (or MAR1) Access memory using the address stored in MAR0 (or MAR1).
MAR0 (or MAR1) += Then post increment MAR0 (or MAR1) by #imm16.
#imm16
Example 1: MMOV32 MR0, *MAR0[2]++
Example 2: MMOV32 MR1, *MAR1[-2]++
For a post increment of 0, the assembler accepts both *MAR0 and *MAR0[0]++.
The 'mmmm mmmm mmmm mmmm' opcode field is populated with the signed 16-bit pointer
offset. For example, if #imm16 is 2, then the opcode field is 0x0002. Likewise, if #imm16 is -2,
then the opcode field is 0xFFFE.
If addition of the 16-bit immediate causes overflow, then the value wraps around on a 16-bit
boundary.

(1) Values not shown are reserved.

Encoding for the shift fields in the MASR32, MLSR32 and MLSL32 instructions is shown in Table 7-9.
Table 7-9. Shift Field Encoding
Shift Value 'shift' Opcode
Field Encode
1 0000
2 0001
3 0010
.... ....
32 1111

For instructions that use MRx (where x can be 'a' through 'f') as operands, the trailing alphabet appears in the
opcode as a two-bit field. For example:

MMPYF32 MRa, MRb, MRc ||

MADDF32 MRd, MRe, MRf

whose opcode is,

LSW: 0000 ffee ddcc bbaa

MSW: 0111 1010 0000 0000

The two-bit field specifies one of four working registers according to Table 7-10.

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Table 7-10. Operand Encoding

Two-Bit Field Working Register
00 MR0
01 MR1
10 MR2
11 MR3

Table 7-11 shows the condition field encoding for conditional instructions such as MNEGF, MSWAPF, MBCNDD,
MCCNDD, and MRCNDD.
Table 7-11. Condition Field Encoding
Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal to zero NF == 0
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to zero ZF == 1 OR NF == 1
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag modification None

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition allows the ZF and NF flags to be modified when a conditional
operation is executed. All other conditions do not modify these flags.

7.7.3 Instructions
The instructions are listed alphabetically.

Instruction Set Summary

MABSF32 MRa, MRb — 32-Bit Floating-Point Absolute Value...........................................................................819
MADD32 MRa, MRb, MRc — 32-Bit Integer Add................................................................................................820
MADDF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Addition........................................................................821
MADDF32 MRa, MRb, #16FHi — 32-Bit Floating-Point Addition........................................................................822
MADDF32 MRa, MRb, MRc — 32-Bit Floating-Point Addition............................................................................824
MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa — 32-Bit Floating-Point Addition with Parallel Move...... 825
MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Addition with Parallel Move..... 826
MAND32 MRa, MRb, MRc — Bitwise AND.........................................................................................................828
MASR32 MRa, #SHIFT — Arithmetic Shift Right................................................................................................ 829
MBCNDD 16BitDest {, CNDF} — Branch Conditional Delayed......................................................................... 830
MCCNDD 16BitDest {, CNDF} — Call Conditional Delayed...............................................................................835
MCMP32 MRa, MRb — 32-Bit Integer Compare for Equal, Less Than or Greater Than....................................839
MCMPF32 MRa, MRb — 32-Bit Floating-Point Compare for Equal, Less Than or Greater Than.......................840
MCMPF32 MRa, #16FHi — 32-Bit Floating-Point Compare for Equal, Less Than or Greater Than...................841
MDEBUGSTOP — Debug Stop Task.................................................................................................................. 843
MEALLOW — Enable CLA Write Access to EALLOW Protected Registers....................................................... 844
MEDIS — Disable CLA Write Access to EALLOW Protected Registers............................................................. 845

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MEINVF32 MRa, MRb — 32-Bit Floating-Point Reciprocal Approximation.........................................................846

MEISQRTF32 MRa, MRb — 32-Bit Floating-Point Square-Root Reciprocal Approximation.............................. 847
MF32TOI16 MRa, MRb — Convert 32-Bit Floating-Point Value to 16-Bit Integer............................................... 849
MF32TOI16R MRa, MRb — Convert 32-Bit Floating-Point Value to 16-Bit Integer and Round..........................850
MF32TOI32 MRa, MRb — Convert 32-Bit Floating-Point Value to 32-Bit Integer............................................... 851
MF32TOUI16 MRa, MRb — Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer ............................852
MF32TOUI16R MRa, MRb — Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer and Round....... 853
MF32TOUI32 MRa, MRb — Convert 32-Bit Floating-Point Value to 32-Bit Unsigned Integer ........................... 854
MFRACF32 MRa, MRb — Fractional Portion of a 32-Bit Floating-Point Value................................................... 855
MI16TOF32 MRa, MRb — Convert 16-Bit Integer to 32-Bit Floating-Point Value .............................................. 856
MI16TOF32 MRa, mem16 — Convert 16-Bit Integer to 32-Bit Floating-Point Value ......................................... 857
MI32TOF32 MRa, mem32 — Convert 32-Bit Integer to 32-Bit Floating-Point Value ......................................... 858
MI32TOF32 MRa, MRb — Convert 32-Bit Integer to 32-Bit Floating-Point Value .............................................. 859
MLSL32 MRa, #SHIFT — Logical Shift Left........................................................................................................ 860
MLSR32 MRa, #SHIFT — Logical Shift Right..................................................................................................... 861
MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Multiply and
Accumulate with Parallel Move............................................................................................................................ 862
MMAXF32 MRa, MRb — 32-Bit Floating-Point Maximum...................................................................................865
MMAXF32 MRa, #16FHi — 32-Bit Floating-Point Maximum...............................................................................867
MMINF32 MRa, MRb — 32-Bit Floating-Point Minimum..................................................................................... 868
MMINF32 MRa, #16FHi — 32-Bit Floating-Point Minimum................................................................................. 870
MMOV16 MARx, MRa, #16I — Load the Auxiliary Register with MRa + 16-bit Immediate Value...................... 871
MMOV16 MARx, mem16 — Load MAR1 with 16-bit Value................................................................................ 874
MMOV16 mem16, MARx — Move 16-Bit Auxiliary Register Contents to Memory............................................. 877
MMOV16 mem16, MRa — Move 16-Bit Floating-Point Register Contents to Memory....................................... 878
MMOV32 mem32, MRa — Move 32-Bit Floating-Point Register Contents to Memory ...................................... 880
MMOV32 mem32, MSTF — Move 32-Bit MSTF Register to Memory.................................................................881
MMOV32 MRa, mem32 {, CNDF} — Conditional 32-Bit Move........................................................................... 882
MMOV32 MRa, MRb {, CNDF} — Conditional 32-Bit Move................................................................................884
MMOV32 MSTF, mem32 — Move 32-Bit Value from Memory to the MSTF Register.........................................886
MMOVD32 MRa, mem32 — Move 32-Bit Value from Memory with Data Copy..................................................887
MMOVF32 MRa, #32F — Load the 32-Bits of a 32-Bit Floating-Point Register.................................................. 889
MMOVI16 MARx, #16I — Load the Auxiliary Register with the 16-Bit Immediate Value.................................... 890
MMOVI32 MRa, #32FHex — Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate............. 892
MMOVIZ MRa, #16FHi — Load the Upper 16-Bits of a 32-Bit Floating-Point Register ......................................894
MMOVZ16 MRa, mem16 — Load MRx with 16-Bit Value...................................................................................895
MMOVXI MRa, #16FLoHex — Move Immediate Value to the Lower 16-Bits of a Floating-Point Register.........896
MMPYF32 MRa, MRb, MRc — 32-Bit Floating-Point Multiply.............................................................................897
MMPYF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Multiply ....................................................................... 898
MMPYF32 MRa, MRb, #16FHi — 32-Bit Floating-Point Multiply ....................................................................... 900
MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf — 32-Bit Floating-Point Multiply with Parallel Add...902
MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Multiply with Parallel Move...... 904
MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa — 32-Bit Floating-Point Multiply with Parallel Move...... 906
MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf — 32-Bit Floating-Point Multiply with Parallel Subtract
.............................................................................................................................................................................907
MNEGF32 MRa, MRb{, CNDF} — Conditional Negation....................................................................................908
MNOP — No Operation....................................................................................................................................... 910
MOR32 MRa, MRb, MRc — Bitwise OR............................................................................................................. 911
MRCNDD {CNDF} — Return Conditional Delayed..............................................................................................912
MSETFLG FLAG, VALUE — Set or Clear Selected Floating-Point Status Flags............................................... 915
MSTOP — Stop Task...........................................................................................................................................916
MSUB32 MRa, MRb, MRc — 32-Bit Integer Subtraction.................................................................................... 918
MSUBF32 MRa, MRb, MRc — 32-Bit Floating-Point Subtraction.......................................................................919
MSUBF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Subtraction...................................................................920

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MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Subtraction with Parallel Move....
922
MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa — 32-Bit Floating-Point Subtraction with Parallel Move....
923
MSWAPF MRa, MRb {, CNDF} — Conditional Swap......................................................................................... 924
MTESTTF CNDF — Test MSTF Register Flag Condition....................................................................................926
MUI16TOF32 MRa, mem16 — Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value........................928
MUI16TOF32 MRa, MRb — Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value............................ 929
MUI32TOF32 MRa, mem32 — Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value........................930
MUI32TOF32 MRa, MRb — Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value............................ 931
MXOR32 MRa, MRb, MRc — Bitwise Exclusive Or............................................................................................ 932

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MABSF32 MRa, MRb

32-Bit Floating-Point Absolute Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0010 0000

Description The absolute value of MRb is loaded into MRa. Only the sign bit of the operand is
modified by the MABSF32 instruction.

if (MRb < 0) {MRa = -MRb};

else {MRa = MRb};

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

NF = 0;
ZF = 0;
if ( MRa(30:23) == 0) ZF = 1;

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #-2.0 ; MR0 = -2.0 (0xC0000000)
MABSF32 MR0, MR0 ; MR0 = 2.0 (0x40000000), ZF = NF = 0
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MABSF32 MR0, MR0 ; MR0 = 5.0 (0x40A00000), ZF = NF = 0
MMOVIZ MR0, #0.0 ; MR0 = 0.0
MABSF32 MR0, MR0 ; MR0 = 0.0 ZF = 1, NF = 0

See also MNEGF32 MRa, MRb {, CNDF}

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MADD32 MRa, MRb, MRc

32-Bit Integer Add

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point destination register (MR0 to MR3)
MRc CLA floating-point destination register (MR0 to MR3)

Opcode
LSW: 0000 0000 000cc bbaa
MSW: 0111 1110 1100 0000

Description 32-bit integer addition of MRb and MRc.

MRa(31:0) = MRb(31:0) + MRc(31:0);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; };

Pipeline This is a single-cycle instruction.

Example
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
; Calculate Y2 = A + B + C
;
_Cla1Task1:
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MADD32 MR3, MR0, MR1 ; A + B
MADD32 MR3, MR2, MR3 ; A + B + C = -4 (0xFFFFFFFC)
MMOV32 @_y2, MR3 ; Store y2
MSTOP ; end of task

See also MAND32 MRa, MRb, MRc

MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MADDF32 MRa, #16FHi, MRb

32-Bit Floating-Point Addition

Operands MRa CLA floating-point destination register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.
MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 0111 1100 bbaa

Description Add MRb to the floating-point value represented by the immediate operand. Store the
result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = MRb + #16FHi:0;

This instruction can also be written as MADDF32 MRa, MRb, #16FHi.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.
Pipeline This is a single-cycle instruction.

Example
; Add to MR1 the value 2.0 in 32-bit floating-point format
; Store the result in MR0
MADDF32 MR0, #2.0, MR1 ; MR0 = 2.0 + MR1
; Add to MR3 the value -2.5 in 32-bit floating-point format
; Store the result in MR2
MADDF32 MR2, #-2.5, MR3 ; MR2 = -2.5 + MR3
; Add to MR3 the value 0x3FC00000 (1.5)
; Store the result in MR3
MADDF32 MR3, #0x3FC0, MR3 ; MR3 = 1.5 + MR3

See also MADDF32 MRa, MRb, #16FHi

MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MADDF32 MRa, MRb, #16FHi

32-Bit Floating-Point Addition

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 0111 1100 bbaa

Description Add MRb to the floating-point value represented by the immediate operand. Store the
result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = MRb + #16FHi:0;

This instruction can also be written as MADDF32 MRa, #16FHi, MRb.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.

Pipeline This is a single-cycle instruction.

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MADDF32 MRa, MRb, #16FHi (continued)

32-Bit Floating-Point Addition

Example 1
; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store the value in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrement the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

Example 2
; Show the basic operation of MADDF32
;
; Add to MR1 the value 2.0 in 32-bit floating-point format
; Store the result in MR0
MADDF32 MR0, MR1, #2.0 ; MR0 = MR1 + 2.0
; Add to MR3 the value -2.5 in 32-bit floating-point format
; Store the result in MR2
MADDF32 MR2, MR3, #-2.5 ; MR2 = MR3 + (-2.5)
; Add to MR0 the value 0x3FC00000 (1.5)
; Store the result in MR0
MADDF32 MR0, MR0, #0x3FC0 ; MR0 = MR0 + 1.5

See also MADDF32 MRa, #16FHi, MRb

MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MADDF32 MRa, MRb, MRc

32-Bit Floating-Point Addition

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 000 0000 00cc bbaa
MSW: 0111 1100 0010 0000

Description Add the contents of MRc to the contents of MRb and load the result into MRa.

MRa = MRb + MRc;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.
Pipeline This is a single-cycle instruction.

Example
; Given M1, X1, and B1 are 32-bit floating-point numbers
; Calculate Y1 = M1*X1+B1
;
_Cla1Task1:
MMOV32 MR0,@M1 ; Load MR0 with M1
MMOV32 MR1,@X1 ; Load MR1 with X1
MMPYF32 MR1,MR1,MR0 ; Multiply M1*X1
|| MMOV32 MR0,@B1 ; and in parallel load MR0 with B1
MADDF32 MR1,MR1,MR0 ; Add M*X1 to B1 and store in MR1
MMOV32 @Y1,MR1 ; Store the result
MSTOP ; end of task

See also MADDF32 MRa, #16FHi, MRb

MADDF32 MRa, MRb, #16FHi
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa

32-Bit Floating-Point Addition with Parallel Move

Operands MRd CLA floating-point destination register for the MADDF32 (MR0 to
MR3)
MRe CLA floating-point source register for the MADDF32 (MR0 to MR3)
MRf CLA floating-point source register for the MADDF32 (MR0 to MR3)
mem32 32-bit memory location accessed using one of the available
addressing modes. This is the destination of the MMOV32.
MRa CLA floating-point source register for the MMOV32 (MR0 to MR3)

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0101 ffee ddaa addr

Description Perform an MADDF32 and a MMOV32 in parallel. Add MRf to the contents of MRe
and store the result in MRd. In parallel move the contents of MRa to the 32-bit location
mem32.

MRd = MRe + MRf;

[mem32] = MRa;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.
Pipeline Both MADDF32 and MMOV32 complete in a single cycle.

Example
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A * B) + C
;
_Cla1Task2:
MMOV32 MR0, @_A ; Load MR0 with A
MMOV32 MR1, @_B ; Load MR1 with B
MMPYF32 MR1, MR1, MR0 ; Multiply A*B
|| MMOV32 MR0, @_C ; and in parallel load MR0 with C
MADDF32 MR1, MR1, MR0 ; Add (A*B) to C
|| MMOV32 @_Y2, MR1 ; and in parallel store A*B
MMOV32 @_Y3, MR1 ; Store the A*B + C
MSTOP ; end of task

See also MADDF32 MRa, #16FHi, MRb

MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32

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MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32

32-Bit Floating-Point Addition with Parallel Move

Operands MRd CLA floating-point destination register for the MADDF32 (MR0 to
MR3).
MRd cannot be the same register as MRa.
MRe CLA floating-point source register for the MADDF32 (MR0 to MR3)
MRf CLA floating-point source register for the MADDF32 (MR0 to MR3)
MRa CLA floating-point destination register for the MMOV32 (MR0 to
MR3).
MRa cannot be the same register as MRd.
mem32 32-bit memory location accessed using one of the available
addressing modes. This is the source for the MMOV32.

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0001 ffee ddaa addr

Description Perform an MADDF32 and a MMOV32 operation in parallel. Add MRf to the contents
of MRe and store the result in MRd. In parallel move the contents of the 32-bit location
mem32 to MRa.

MRd = MRe + MRf;

MRa = [mem32];

Restrictions The destination register for the MADDF32 and the MMOV32 must be unique. That is,
MRa and MRd cannot be the same register.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.
The MMOV32 Instruction sets the NF and ZF flags as follows:

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; };

Pipeline The MADDF32 and the MMOV32 both complete in a single cycle.

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MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 (continued)

32-Bit Floating-Point Addition with Parallel Move

Example 1
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y1 = A + 4B
; Y2 = A + C
;
_Cla1Task1:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR1, MR1, #4.0 ; Multiply 4 * B
|| MMOV32 MR2, @C and in parallel load C
MADDF32 MR3, MR0, MR1 ; Add A + 4B
MADDF32 MR3, MR0, MR2 ; Add A + C
|| MMOV32 @Y1, MR3 ; and in parallel store A+4B
MMOV32 @Y2, MR3 ; store A + C MSTOP
; end of task

Example 2
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y3 = (A + B)
; Y4 = (A + B) * C
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MADDF32 MR1, MR1, MR0 ; Add A+B
|| MMOV32 MR0, @C ; and in parallel load MR0 with C
MMPYF32 MR1, MR1, MR0 ; Multiply (A+B) by C
|| MMOV32 @Y3, MR1 ; and in parallel store A+B
MMOV32 @Y4, MR1 ; Store the (A+B) * C
MSTOP ; end of task

See also MADDF32 MRa, #16FHi, MRb

MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MAND32 MRa, MRb, MRc

Bitwise AND

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 0110 0000

Description Bitwise AND of MRb with MRc.

MRa(31:0) = MRb(31:0) AND MRc(31:0);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x5555 ; MR0 = 0x5555AAAA
MMOVXI MR0, #0xAAAA
MMOVIZ MR1, #0x5432 ; MR1 = 0x5432FEDC
MMOVXI MR1, #0xFEDC
; 0101 AND 0101 = 0101 (5)
; 0101 AND 0100 = 0100 (4)
; 0101 AND 0011 = 0001 (1)
; 0101 AND 0010 = 0000 (0)
; 1010 AND 1111 = 1010 (A)
; 1010 AND 1110 = 1010 (A)
; 1010 AND 1101 = 1000 (8)
; 1010 AND 1100 = 1000 (8)
MAND32 MR2, MR1, MR0 ; MR3 = 0x5410AA88

See also MADD32 MRa, MRb, MRc

MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MASR32 MRa, #SHIFT

Arithmetic Shift Right

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

#SHIFT Number of bits to shift (1 to 32)

Opcode
LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 0100 0000

Description Arithmetic shift right of MRa by the number of bits indicated. The number of bits can be 1
to 32.

MARa(31:0) = Arithmetic Shift(MARa(31:0) by #SHIFT bits);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example
; Given m2 = (int32)32
; x2 = (int32)64
; b2 = (int32)-128
;
; Calculate
; m2 = m2/2
; x2 = x2/4
; b2 = b2/8
;
_Cla1Task2:
MMOV32 MR0, @_m2 ; MR0 = 32 (0x00000020)
MMOV32 MR1, @_x2 ; MR1 = 64 (0x00000040)
MMOV32 MR2, @_b2 ; MR2 = -128 (0xFFFFFF80)
MASR32 MR0, #1 ; MR0 = 16 (0x00000010)
MASR32 MR1, #2 ; MR1 = 16 (0x00000010)
MASR32 MR2, #3 ; MR2 = -16 (0xFFFFFFF0)
MMOV32 @_m2, MR0 ; store results
MMOV32 @_x2, MR1
MMOV32 @_b2, MR2
MSTOP ; end of task

See also MADD32 MRa, MRb, MRc

MAND32 MRa, MRb, MRc
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MBCNDD 16BitDest {, CNDF}

Branch Conditional Delayed

Operands 16BitDest 16-bit destination if condition is true

CNDF Optional condition tested

Opcode
LSW: dest dest dest dest
MSW: 0111 1001 1000 cndf

Description If the specified condition is true, then branch by adding the signed 16BitDest value to the
MPC value. Otherwise, continue without branching. If the address overflows, the address
wraps around. Therefore, a value of "0xFFFE" puts the MPC back to the MBCNDD
instruction.
Refer to the Pipeline section for important information regarding this instruction.

if (CNDF == TRUE) MPC += 16BitDest;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Restrictions The MBCNDD instruction is not allowed three instructions before or after a MBCNDD,
MCCNDD, or MRCNDD instruction. Refer to the Pipeline section for more information.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

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MBCNDD 16BitDest {, CNDF} (continued)

Branch Conditional Delayed

Pipeline The MBCNDD instruction alone is a single-cycle instruction. As shown in Table 7-12, 6
instruction slots are executed for each branch; 3 slots before the branch instruction (I2-I4)
and 3 slots after the branch instruction (I5-I7). The total number of cycles for a branch
taken or not taken depends on the usage of these slots. That is, the number of cycles
depends on how many slots are filled with a MNOP as well as which slots are filled. The
effective number of cycles for a branch can, therefore, range from 1 to 7 cycles. The
number of cycles for a branch taken can not be the same as for a branch not taken.
Referring to Table 7-12 and Table 7-13, the instructions before and after MBCNDD have
the following properties:
• I1
– I1 is the last instruction that can effect the CNDF flags for the MBCNDD instruction.
The CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is
made whether to branch or not when MBCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for I1.
• I2, I3, and I4
– The three instructions proceeding MBCNDD can change MSTF flags but have no
effect on whether the MBCNDD instruction branches or not. This is because the
flag modification occurs after the D2 phase of the MBCNDD instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.
• I5, I6, and I7
– The three instructions following MBCNDD are always executed irrespective of
whether the branch is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.

<Instruction 1> ; I1 Last instruction that can affect flags for

; the MBCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
MBCNDD _Skip, NEQ ; Branch to Skip if not eqal to zero
; Three instructions after MBCNDD are always
; executed whether the branch is taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8
<Instruction 9> ; I9
....
_Skip:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
....
....
MSTOP
....

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MBCNDD 16BitDest {, CNDF} (continued)

Branch Conditional Delayed

Table 7-12. Pipeline Activity for MBCNDD, Branch Not Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MBCNDD MBCNDD I4 I3 I2 I1
I5 I5 MBCNDD I4 I3 I2 I1
I6 I6 I5 MBCNDD I4 I3 I2 I1
I7 I7 I6 I5 MBCNDD I4 I3 I2
I8 I8 I7 I6 I5 - I4 I3
I9 I9 I8 I7 I6 I5 - I4
I10 I10 I9 I8 I7 I6 I5 -
I10 I9 I8 I7 I6 I5
I10 I9 I8 I7 I6
I10 I9 I8 I7
I10 I9 I8
I10 I9
I10

Table 7-13. Pipeline Activity for MBCNDD, Branch Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MBCNDD MBCNDD I4 I3 I2 I1
I5 I5 MBCNDD I4 I3 I2 I1
I6 I6 I5 MBCNDD I4 I3 I2 I1
I7 I7 I6 I5 MBCNDD I4 I3 I2
d1 d1 I7 I6 I5 - I4 I3
d2 d2 d1 I7 I6 I5 - I4
d3 d3 d2 d1 I7 I6 I5 -
d3 d2 d1 I7 I6 I5
d3 d2 d1 I7 I6
d3 d2 d1 I7
d3 d2 d1
d3 d2
d3

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MBCNDD 16BitDest {, CNDF} (continued)

Branch Conditional Delayed

Example 1
; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task1:
MMOV32 MR0, @State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MNOP
MNOP
MNOP
MBCNDD Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MNOP ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MMOV32 MR1, @RampState ; Execute if (A) branch not taken
MMOVXI MR2, #RAMPMASK ; Execute if (A) branch not taken
MOR32 MR1, MR2 ; Execute if (A) branch not taken
MMOV32 @RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken
Skip1:
MCMPF32 MR0,#0.01 ; Affects flags for 2nd MBCNDD (B)
MNOP
MNOP
MNOP
MBCNDD Skip2,NEQ ; (B) If State != 0.01, go to Skip2
MNOP ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MMOV32 MR1, @CoastState ; Execute if (B) branch not taken
MMOVXI MR2, #COASTMASK ; Execute if (B) branch not taken
MOR32 MR1, MR2 ; Execute if (B) branch not taken
MMOV32 @CoastState, MR1 ; Execute if (B) branch not taken
MSTOP
Skip2:
MMOV32 MR3, @SteadyState ; Executed if (B) branch taken
MMOVXI MR2, #STEADYMASK ; Executed if (B) branch taken
MOR32 MR3, MR2 ; Executed if (B) branch taken
MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken
MSTOP

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MBCNDD 16BitDest {, CNDF} (continued)

Branch Conditional Delayed

Example 2
; This example is the same as Example 1, except
; the code is optimized to take advantage of delay slots
;
; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task2:
MMOV32 MR0, @State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MCMPF32 MR0, #0.01 ; Check used by 2nd MBCNDD (B)
MTESTTF EQ ; Store EQ flag in TF for 2nd MBCNDD (B)
MNOP
MBCNDD Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MMOV32 MR1, @RampState ; Always executed
MMOVXI MR2, #RAMPMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken
Skip1:
MMOV32 MR3, @SteadyState
MMOVXI MR2, #STEADYMASK
MOR32 MR3, MR2
MBCNDD Skip2, NTF ; (B) if State != .01, go to Skip2
MMOV32 MR1, @CoastState ; Always executed
MMOVXI MR2, #COASTMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @CoastState, MR1 ; Execute if (B) branch not taken
MSTOP ; end of task if (B) branch not taken
Skip2:
MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken
MSTOP

See also MCCNDD 16BitDest, CNDF

MRCNDD CNDF

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MCCNDD 16BitDest {, CNDF}

Call Conditional Delayed

Operands 16BitDest 16-bit destination if condition is true

CNDF Optional condition to be tested

Opcode
LSW: dest dest dest dest
MSW: 0111 1001 1001 cndf

Description If the specified condition is true, then store the return address in the RPC field of MSTF
and make the call by adding the signed 16BitDest value to the MPC value. Otherwise,
continue code execution without making the call. If the address overflows, the address
wraps around. Therefore a value of "0xFFFE" puts the MPC back to the MCCNDD
instruction.
Refer to the Pipeline section for important information regarding this instruction.

if (CNDF == TRUE)
{
RPC = return address;
MPC += 16BitDest;
};

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation if no CNDF field is specified. This condition allows
the ZF and NF flags to be modified when a conditional operation is executed.
All other conditions do not modify these flags.

Restrictions The MCCNDD instruction is not allowed three instructions before or after a MBCNDD,
MCCNDD, or MRCNDD instruction. Refer to the Pipeline section for more details.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

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MCCNDD 16BitDest {, CNDF} (continued)

Call Conditional Delayed

Pipeline The MCCNDD instruction alone is a single-cycle instruction. As shown in Table 7-14, 6
instruction slots are executed for each call; 3 before the call instruction (I2-I4) and 3 after
the call instruction (I5-I7). The total number of cycles for a call taken or not taken depends
on the usage of these slots. That is, the number of cycles depends on how many slots are
filled with a MNOP as well as which slots are filled. The effective number of cycles for a
call can, therefore, range from 1 to 7 cycles. The number of cycles for a call taken can not
be the same as for a call not taken.
Referring to the following code fragment and the pipeline diagrams in Table 7-14 and
Table 7-15, the instructions before and after MCCNDD have the following properties:
• I1
– I1 is the last instruction that can effect the CNDF flags for the MCCNDD instruction.
The CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is
made whether to branch or not when MCCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for I1.
• I2, I3, and I4
– The three instructions proceeding MCCNDD can change MSTF flags but have no
effect on whether the MCCNDD instruction makes the call or not. This is because
the flag modification occurs after the D2 phase of the MCCNDD instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.
• I5, I6, and I7
– The three instructions following MBCNDD are always executed irrespective of
whether the branch is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.

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MCCNDD 16BitDest {, CNDF} (continued)

Call Conditional Delayed

<Instruction 1> ; I1 Last instruction that can affect flags for

; the MCCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
MCCNDD _func, NEQ ; Call to func if not eqal to zero
; Three instructions after MCCNDD are always
; executed whether the call is taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8 The address of this instruction is saved
; in the RPC field of the MSTF register.
; Upon return this value is loaded into MPC
; and fetching continues from this point.
<Instruction 9> ; I9
....
_func:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
<Destination 4> ; d4 Last instruction that can affect flags for
; the MRCNDD operation
<Destination 5> ; d5 Cannot be stop, branch, call or return
<Destination 6> ; d6 Cannot be stop, branch, call or return
<Destination 7> ; d7 Cannot be stop, branch, call or return
MRCNDD UNC ; Return to <Instruction 8>, unconditional
; Three instructions after MRCNDD are always
; executed whether the return is taken or not
<Destination 8> ; d8 Cannot be stop, branch, call or return
<Destination 9> ; d9 Cannot be stop, branch, call or return
<Destination 10> ; d10 Cannot be stop, branch, call or return
<Destination 11> ; d11
....
MSTOP

Table 7-14. Pipeline Activity for MCCNDD, Call Not Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MCCNDD MCCNDD I4 I3 I2 I1
I5 I5 MCCNDD I4 I3 I2 I1
I6 I6 I5 MCCNDD I4 I3 I2 I1
I7 I7 I6 I5 MCCNDD I4 I3 I2
I8 I8 I7 I6 I5 - I4 I3
I9 I9 I8 I7 I6 I5 - I4
I10 I10 I9 I8 I7 I6 I5 -
etc .... I10 I9 I8 I7 I6 I5
.... I10 I9 I8 I7 I6
.... I10 I9 I8 I7
.... I10 I9 I8
I10 I9
I10

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MCCNDD 16BitDest {, CNDF} (continued)

Call Conditional Delayed

Table 7-15. Pipeline Activity for MCCNDD, Call Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MCCNDD MCCNDD I4 I3 I2 I1
I5 I5 MCCNDD I4 I3 I2 I1
I6 I6 I5 MCCNDD I4 I3 I2 I1
I7 (1) I7 I6 I5 MCCNDD I4 I3 I2
d1 d1 I7 I6 I5 - I4 I3
d2 d2 d1 I7 I6 I5 - I4
d3 d3 d2 d1 I7 I6 I5 -
etc .... d3 d2 d1 I7 I6 I5
.... d3 d2 d1 I7 I6
.... d3 d2 d1 I7
.... d3 d2 d1
d3 d2
d3

(1) The RPC value in the MSTF register points to the instruction following I7 (instruction I8).

See also MBCNDD #16BitDest, CNDF

MMOV32 mem32, MSTF
MMOV32 MSTF, mem32
MRCNDD CNDF

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MCMP32 MRa, MRb

32-Bit Integer Compare for Equal, Less Than or Greater Than

Operands MRa CLA floating-point source register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1111 0010 0000

Description Set ZF and NF flags on the result of MRa - MRb where MRa and MRb are 32-bit integers.
For a floating-point compare, refer to MCMPF32.

Note
A known hardware issue exists in the MCMP32 instruction. Signed-integer
comparisons using MCMP32 alone set the status bits in a way that is not useful
for comparison when the difference between the two operands is too large,
such as when the inputs have opposite sign and are near the extreme 32-bit
signed values. This affects both signed and unsigned integer comparisons.
The compiler (version 18.1.5.LTS or higher) has implemented a workaround for
this issue. The compiler checks the upper bits of the operands by performing
a floating point comparison before proceeding to do the integer comparison or
subtraction.
The compiler flag --cla_signed_compare_workaround enables this workaround.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

If(MRa == MRb) {ZF=1; NF=0;}

If(MRa > MRb) {ZF=0; NF=0;}
If(MRa < MRb) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example
; Behavior of ZF and NF flags for different comparisons
;
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MCMP32 MR2, MR2 ; NF = 0, ZF = 1
MCMP32 MR0, MR1 ; NF = 1, ZF = 0
MCMP32 MR1, MR0 ; NF = 0, ZF = 0

See also MADD32 MRa, MRb, MRc

MSUB32 MRa, MRb, MRc

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MCMPF32 MRa, MRb

32-Bit Floating-Point Compare for Equal, Less Than or Greater Than

Operands MRa CLA floating-point source register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0000 0000

Description Set ZF and NF flags on the result of MRa - MRb. The MCMPF32 instruction is performed
as a logical compare operation. This is possible because of the IEEE format offsetting the
exponent. Basically the bigger the binary number, the bigger the floating-point value.
Special cases for inputs:
• Negative zero is treated as positive zero.
• A denormalized value is treated as positive zero.
• Not-a-Number (NaN) is treated as infinity.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

If(MRa == MRb) {ZF=1; NF=0;}

If(MRa > MRb) {ZF=0; NF=0;}
If(MRa < MRb) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example
; Behavior of ZF and NF flags for different comparisons
MMOVIZ MR1, #-2.0 ; MR1 = -2.0 (0xC0000000)
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MCMPF32 MR1, MR0 ; ZF = 0, NF = 1
MCMPF32 MR0, MR1 ; ZF = 0, NF = 0
MCMPF32 MR0, MR0 ; ZF = 1, NF = 0

See also MCMPF32 MRa, #16FHi

MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, #16FHi
MMINF32 MRa, MRb

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MCMPF32 MRa, #16FHi

32-Bit Floating-Point Compare for Equal, Less Than or Greater Than

Operands MRa CLA floating-point source register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1000 1100 00aa

Description Compare the value in MRa with the floating-point value represented by the immediate
operand. Set the ZF and NF flags on (MRa - #16FHi:0).
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler accepts either a hex or float as the immediate value.
That is, -1.5 can be represented as #-1.5 or #0xBFC0.
The MCMPF32 instruction is performed as a logical compare operation. This is possible
because of the IEEE floating-point format offsets the exponent. Basically the bigger the
binary number, the bigger the floating-point value.
Special cases for inputs:
• Negative zero is treated as positive zero.
• Denormalized value is treated as positive zero.
• Not-a-Number (NaN) is treated as infinity.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

If(MRa == #16FHi:0) {ZF=1, NF=0;}

If(MRa > #16FHi:0) {ZF=0, NF=0;}
If(MRa < #16FHi:0) {ZF=0, NF=1;}

Pipeline This is a single-cycle instruction

Example 1
; Behavior of ZF and NF flags for different comparisons
MMOVIZ MR1, #-2.0 ; MR1 = -2.0 (0xC0000000)
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MCMPF32 MR1, #-2.2 ; ZF = 0, NF = 0
MCMPF32 MR0, #6.5 ; ZF = 0, NF = 1
MCMPF32 MR0, #5.0 ; ZF = 1, NF = 0

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MCMPF32 MRa, #16FHi (continued)

32-Bit Floating-Point Compare for Equal, Less Than or Greater Than

Example 2
; X is an array of 32-bit floating-point values
; and has length elements. Find the maximum value in
; the array and store the value in Result
;
; Note: MCMPF32 and MSWAPF can be replaced with MMAXF32
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MCMPF32 MR2, MR1 ; Compare MR2 with MR1
MSWAPF MR1, MR2, GT ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

See also MCMPF32 MRa, MRb

MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, #16FHi
MMINF32 MRa, MRb

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MDEBUGSTOP

Debug Stop Task

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 0110 0000

Description When CLA breakpoints are enabled, the MDEBUGSTOP instruction is used to halt a task
so that the task can be debugged. That is, MDEBUGSTOP is the CLA breakpoint. If CLA
breakpoints are not enabled, the MDEBUGSTOP instruction behaves like a MNOP. Unlike
the MSTOP, the MIRUN flag is not cleared and an interrupt is not issued. A single-step or
run operation continues execution of the task.

Restrictions The MDEBUGSTOP instruction cannot be placed 3 instructions before or after a

MBCNDD, MCCNDD, or MRCNDD instruction.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

See also MSTOP

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MEALLOW

Enable CLA Write Access to EALLOW Protected Registers

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1001 0000

Description This instruction sets the MEALLOW bit in the CLA status register MSTF. When this bit
is set, the CLA is allowed write access to EALLOW protected registers. To again protect
against CLA writes to protected registers, use the MEDIS instruction.
MEALLOW and MEDIS only control CLA write access; reads are allowed even if
MEALLOW has not been executed. MEALLOW and MEDIS are also independent from
the main CPU's EALLOW/EDIS. This instruction does not modify the EALLOW bit in the
main CPU's status register. The MEALLOW bit in MSTF only controls access for the CLA
while the EALLOW bit in the ST1 register only controls access for the main CPU.
As with EALLOW, the MEALLOW bit is overridden using the JTAG port, allowing full
control of register accesses during debug from Code Composer Studio.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
; C header file including definition of
; the EPwm1Regs structure
;
; The ePWM TZSEL register is EALLOW protected
;
.cdecls C,LIST,"CLAShared.h"
...
_Cla1Task1:
...
MEALLOW ; Allow CLA write access
MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL
MEDIS ; Disallow CLA write access
...
...
MSTOP

See also MEDIS

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MEDIS

Disable CLA Write Access to EALLOW Protected Registers

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1011 0000

Description This instruction clears the MEALLOW bit in the CLA status register MSTF. When this bit is
clear, the CLA is not allowed write access to EALLOW-protected registers. To enable CLA
writes to protected registers, use the MEALLOW instruction.
MEALLOW and MEDIS only control CLA write access; reads are allowed even if
MEALLOW has not been executed. MEALLOW and MEDIS are also independent from
the main CPU's EALLOW/EDIS. This instruction does not modify the EALLOW bit in the
main CPU's status register. The MEALLOW bit in MSTF only controls access for the CLA
while the EALLOW bit in the ST1 register only controls access for the main CPU.
As with EALLOW, the MEALLOW bit is overridden using the JTAG port, allowing full
control of register accesses during debug from the Code Composer Studio™ IDE.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
; C header file including definition of
; the EPwm1Regs structure
;
; The ePWM TZSEL register is EALLOW protected
;
.cdecls C,LIST,"CLAShared.h"
...
_Cla1Task1:
...
MEALLOW ; Allow CLA write access
MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL
MEDIS ; Disallow CLA write access
...
...
MSTOP

See also MEALLOW

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MEINVF32 MRa, MRb

32-Bit Floating-Point Reciprocal Approximation

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1111 0000 0000

Description This operation generates an estimate of 1/X in 32-bit floating-point format accurate to
approximately 8 bits. This value can be used in a Newton-Raphson algorithm to get a
more accurate answer. That is:

Ye = Estimate(1/X);
Ye = Ye*(2.0 - Ye*X);
Ye = Ye*(2.0 - Ye*X);

After two iterations of the Newton-Raphson algorithm, you get an exact answer
accurate to the 32-bit floating-point format. On each iteration, the mantissa bit accuracy
approximately doubles. The MEINVF32 operation does not generate a negative zero,
DeNorm, or NaN value.

MRa = Estimate of 1/MRb;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MEINVF32 generates an underflow condition.
• LVF = 1 if MEINVF32 generates an overflow condition.
Pipeline This is a single-cycle instruction.

Example
; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den ; MR1 = Den
MEINVF32 MR2, MR1 ; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num ; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den ; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ ; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0 ; Store result
MSTOP ; end of task

See also MEISQRTF32 MRa, MRb

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MEISQRTF32 MRa, MRb

32-Bit Floating-Point Square-Root Reciprocal Approximation

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0100 0000

Description This operation generates an estimate of 1/sqrt(X) in 32-bit floating-point format accurate
to approximately 8 bits. This value can be used in a Newton-Raphson algorithm to get a
more accurate answer. That is:

Ye = Estimate(1/sqrt(X));
Ye = Ye*(1.5 - Ye*Ye*X/2.0);
Ye = Ye*(1.5 - Ye*Ye*X/2.0);

After 2 iterations of the Newton-Raphson algorithm, you get an exact answer accurate to
the 32-bit floating-point format. On each iteration, the mantissa bit accuracy approximately
doubles. The MEISQRTF32 operation does not generate a negative zero, DeNorm, or
NaN value.

MRa = Estimate of 1/sqrt (MRb);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MEISQRTF32 generates an underflow condition.
• LVF = 1 if MEISQRTF32 generates an overflow condition.
Pipeline This is a single-cycle instruction.

Example
; Y = sqrt(X)
; Ye = Estimate(1/sqrt(X));
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Y = X*Ye
;
_Cla1Task3:
MMOV32 MR0, @_x ; MR0 = X
MEISQRTF32 MR1, MR0 ; MR1 = Ye = Estimate(1/sqrt(X))
MMOV32 MR1, @_x, EQ ; if(X == 0.0) Ye = 0.0
MMPYF32 MR3, MR0, #0.5 ; MR3 = X*0.5
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR0, MR1, MR0 ; MR0 = Y = Ye*X
MMOV32 @_y, MR0 ; Store Y = sqrt(X)
MSTOP ; end of task

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MEISQRTF32 MRa, MRb (continued)

32-Bit Floating-Point Square-Root Reciprocal Approximation

See also MEINVF32 MRa, MRb

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MF32TOI16 MRa, MRb

Convert 32-Bit Floating-Point Value to 16-Bit Integer

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1110 0000

Description Convert a 32-bit floating point value in MRb to a 16-bit integer and truncate. The result is
stored in MRa.

MRa(15:0) = F32TOI16(MRb);
MRa(31:16) = sign extension of MRa(15);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MF32TOI16 MR1, MR0 ; MR1(15:0) = MF32TOI16(MR0) = 0x0005
; MR1(31:16) = Sign extension of MR1(15) = 0x0000
MMOVIZ MR2, #-5.0 ; MR2 = -5.0 (0xC0A00000)
MF32TOI16 MR3, MR2 ; MR3(15:0) = MF32TOI16(MR2) = -5 (0xFFFB)
; MR3(31:16) = Sign extension of MR3(15) = 0xFFFF

See also MF32TOI16R MRa, MRb

MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023 TMS320F28003x Real-Time Microcontrollers 849
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MF32TOI16R MRa, MRb

Convert 32-Bit Floating-Point Value to 16-Bit Integer and Round

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0110 0000

Description Convert the 32-bit floating point value in MRb to a 16-bit integer and round to the nearest
even value. The result is stored in MRa.

MRa(15:0) = F32TOI16round(MRb);
MRa(31:16) = sign extension of MRa(15);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x3FD9 ; MR0(31:16) = 0x3FD9
MMOVXI MR0, #0x999A ; MR0(15:0) = 0x999A
; MR0 = 1.7 (0x3FD9999A)
MF32TOI16R MR1, MR0 ; MR1(15:0) = MF32TOI16round (MR0) = 2 (0x0002)
; MR1(31:16) = Sign extension of MR1(15) = 0x0000
MMOVF32 MR2, #-1.7 ; MR2 = -1.7 (0xBFD9999A)
MF32TOI16R MR3, MR2 ; MR3(15:0) = MF32TOI16round (MR2) = -2 (0xFFFE)
; MR3(31:16) = Sign extension of MR2(15) = 0xFFFF

See also MF32TOI16 MRa, MRb

MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOI32 MRa, MRb

Convert 32-Bit Floating-Point Value to 32-Bit Integer

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0110 0000

Description Convert the 32-bit floating-point value in MRb to a 32-bit integer value and truncate. Store
the result in MRa.

MRa = F32TOI32(MRb);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example 1
MMOVF32 MR2, #11204005.0 ; MR2 = 11204005.0 (0x4B2AF5A5)
MF32TOI32 MR3, MR2 ; MR3 = MF32TOI32(MR2) = 11204005 (0x00AAF5A5)
MMOVF32 MR0, #-11204005.0 ; MR0 = -11204005.0 (0xCB2AF5A5)
MF32TOI32 MR1, MR0 ; MR1 = MF32TOI32(MR0) = -11204005 (0xFF550A5B)

Example 2
; Given X, M and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
; Convert M, X, and B from IQ24 to float
;
_Cla1Task2:
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also MF32TOUI32 MRa, MRb

MI32TOF32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MF32TOUI16 MRa, MRb

Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1010 0000

Description Convert the 32-bit floating point value in MRb to an unsigned 16-bit integer value and
truncate to zero. The result is stored in MRa. To instead round the integer to the nearest
even value, use the MF32TOUI16R instruction.

MRa(15:0) = F32TOUI16(MRb);
MRa(31:16) = 0x0000;

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #9.0 ; MR0 = 9.0 (0x41100000)
MF32TOUI16 MR1, MR0 ; MR1(15:0) = MF32TOUI16(MR0) = 9 (0x0009)
; MR1(31:16) = 0x0000
MMOVIZ MR2, #-9.0 ; MR2 = -9.0 (0xC1100000)
MF32TOUI16 MR3, MR2 ; MR3(15:0) = MF32TOUI16(MR2) = 0 (0x0000)
; MR3(31:16) = 0x0000

See also MF32TOI16 MRa, MRb

MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOUI16R MRa, MRb

Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer and Round

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1100 0000

Description Convert the 32-bit floating-point value in MRb to an unsigned 16-bit integer and round to
the closest even value. The result is stored in MRa. To instead truncate the converted
value, use the MF32TOUI16 instruction.

MRa(15:0) = MF32TOUI16round(MRb);
MRa(31:16) = 0x0000;

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x412C ; MR0 = 0x412C
MMOVXI MR0, #0xCCCD ; MR0 = 0xCCCD ; MR0 = 10.8 (0x412CCCCD)
MF32TOUI16R MR1, MR0 ; MR1(15:0) = MF32TOUI16round(MR0) = 11 (0x000B)
; MR1(31:16) = 0x0000
MMOVF32 MR2, #-10.8 ; MR2 = -10.8 (0x0xC12CCCCD)
MF32TOUI16R MR3, MR2 ; MR3(15:0) = MF32TOUI16round(MR2) = 0 (0x0000)
; MR3(31:16) = 0x0000

See also MF32TOI16 MRa, MRb

MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOUI32 MRa, MRb

Convert 32-Bit Floating-Point Value to 32-Bit Unsigned Integer

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1010 0000

Description Convert the 32-bit floating-point value in MRb to an unsigned 32-bit integer and store the
result in MRa.

MRa = F32TOUI32(MRb);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #12.5 ; MR0 = 12.5 (0x41480000)
MF32TOUI32 MR0, MR0 ; MR0 = MF32TOUI32 (MR0) = 12 (0x0000000C)
MMOVIZ MR1, #-6.5 ; MR1 = -6.5 (0xC0D00000)
MF32TOUI32 MR2, MR1 ; MR2 = MF32TOUI32 (MR1) = 0.0 (0x00000000)

See also MF32TOI32 MRa, MRb

MI32TOF32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MFRACF32 MRa, MRb

Fractional Portion of a 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0000 0000

Description Returns in MRa the fractional portion of the 32-bit floating-point value in MRb

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR2, #19.625 ; MR2 = 19.625 (0x419D0000)
MFRACF32 MR3, MR2 ; MR3 = MFRACF32(MR2) = 0.625 (0x3F200000)0)

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MI16TOF32 MRa, MRb

Convert 16-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1000 0000

Description Convert the 16-bit signed integer in MRb to a 32-bit floating-point value and store the
result in MRa.

MRa = MI16TOF32(MRb);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x0000 ; MR0(31:16) = 0.0 (0x0000)
MMOVXI MR0, #0x0004 ; MR0(15:0) = 4.0 (0x0004)
MI16TOF32 MR1, MR0 ; MR1 = MI16TOF32 (MR0) = 4.0 (0x40800000)
MMOVIZ MR2, #0x0000 ; MR2(31:16) = 0.0 (0x0000)
MMOVXI MR2, #0xFFFC ; MR2(15:0) = -4.0 (0xFFFC)
MI16TOF32 MR3, MR2 ; MR3 = MI16TOF32 (MR2) = -4.0 (0xC0800000)
MSTOP

See also MF32TOI16 MRa, MRb

MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MI16TOF32 MRa, mem16

Convert 16-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem16 16-bit source memory location to be converted

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 00aa addr

Description Convert the 16-bit signed integer indicated by the mem16 pointer to a 32-bit floating-point
value and store the result in MRa.

MRa = MI16TOF32[mem16];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction:

Example
; Assume A = 4 (0x0004)
; B = -4 (0xFFFC)
MI16TOF32 MR0, @_A ; MR0 = MI16TOF32(A) = 4.0 (0x40800000)
MI16TOF32 MR1, @_B ; MR1 = MI16TOF32(B) = -4.0 (0xC0800000

See also MF32TOI16 MRa, MRb

MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MI32TOF32 MRa, mem32

Convert 32-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem32 32-bit memory source for the MMOV32 operation.

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 01aa addr

Description Convert the 32-bit signed integer indicated by mem32 to a 32-bit floating-point value and
store the result in MRa.

MRa = MI32TOF32[mem32];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
; Given X, M and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
; Convert M, X, and B from IQ24 to float
;
_Cla1Task3:
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also MF32TOI32 MRa, MRb

MF32TOUI32 MRa, MRb
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MI32TOF32 MRa, MRb

Convert 32-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1000 0000

Description Convert the signed 32-bit integer in MRb to a 32-bit floating-point value and store the
result in MRa.

MRa = MI32TOF32(MRb);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR2, #0x1111 ; MR2(31:16) = 4369 (0x1111)
MMOVXI MR2, #0x1111 ; MR2(15:0) = 4369 (0x1111)
; MR2 = +286331153 (0x11111111)
MI32TOF32 MR3, MR2 ; MR3 = MI32TOF32 (MR2) = 286331153.0 (0x4D888888)

See also MF32TOI32 MRa, MRb

MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MLSL32 MRa, #SHIFT

Logical Shift Left

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

#SHIFT Number of bits to shift (1 to 32)

Opcode
LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 1100 0000

Description Logical shift-left of MRa by the number of bits indicated. The number of bits can be 1 to
32.

MARa(31:0) = Logical Shift Left(MARa(31:0) by #SHIFT bits);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example
; Given m2 = (int32)32
; x2 = (int32)64
; b2 = (int32)-128
;
; Calculate:
; m2 = m2*2
; x2 = x2*4
; b2 = b2*8
;
_Cla1Task3:
MMOV32 MR0, @_m2 ; MR0 = 32 (0x00000020)
MMOV32 MR1, @_x2 ; MR1 = 64 (0x00000040)
MMOV32 MR2, @_b2 ; MR2 = -128 (0xFFFFFF80)
MLSL32 MR0, #1 ; MR0 = 64 (0x00000040)
MLSL32 MR1, #2 ; MR1 = 256 (0x00000100)
MLSL32 MR2, #3 ; MR2 = -1024 (0xFFFFFC00)
MMOV32 @_m2, MR0 ; Store results
MMOV32 @_x2, MR1
MMOV32 @_b2, MR2
MSTOP ; end of task

See also MADD32 MRa, MRb, MRc

MASR32 MRa, #SHIFT
MAND32 MRa, MRb, MRc
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MLSR32 MRa, #SHIFT

Logical Shift Right

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

#SHIFT Number of bits to shift (1 to 32)

Opcode
LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 1000 0000

Description Logical shift-right of MRa by the number of bits indicated. The number of bits can be 1 to
32. Unlike the arithmetic shift (MASR32), the logical shift does not preserve the number's
sign bit. Every bit in the operand is moved the specified number of bit positions, and the
vacant bit positions are filled in with zeros.

MARa(31:0) = Logical Shift Right(MARa(31:0) by #SHIFT bits);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1;}

Pipeline This is a single-cycle instruction.

Example
; Illustrate the difference between MASR32 and MLSR32
MMOVIZ MR0, #0xAAAA ; MR0 = 0xAAAA5555
MMOVXI MR0, #0x5555
MMOV32 MR1, MR0 ; MR1 = 0xAAAA5555
MMOV32 MR2, MR0 ; MR2 = 0xAAAA5555
MASR32 MR1, #1 ; MR1 = 0xD5552AAA
MLSR32 MR2, #1 ; MR2 = 0x55552AAA
MASR32 MR1, #1 ; MR1 = 0xEAAA9555
MLSR32 MR2, #1 ; MR2 = 0x2AAA9555
MASR32 MR1, #6 ; MR1 = 0xFFAAAA55
MLSR32 MR2, #6 ; MR2 = 0x00AAAA55

See also MADD32 MRa, MRb, MRc

MASR32 MRa, #SHIFT
MAND32 MRa, MRb, MRc
MLSL32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32

32-Bit Floating-Point Multiply and Accumulate with Parallel Move

Operands MR3 floating-point destination/source register MR3 for the add

operation
MR2 CLA floating-point source register MR2 for the add operation
MRd CLA floating-point destination register (MR0 to MR3) for the
multiply operation
MRd cannot be the same register as MRa
MRe CLA floating-point source register (MR0 to MR3) for the multiply
operation
MRf CLA floating-point source register (MR0 to MR3) for the multiply
operation
MRa CLA floating-point destination register for the MMOV32 operation
(MR0 to MR3).
MRa cannot be MR3 or the same register as MRd.
mem32 32-bit source for the MMOV32 operation

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0011 ffee ddaa addr

Description Multiply and accumulate the contents of floating-point registers and move from register to
memory. The destination register for the MMOV32 cannot be the same as the destination
registers for the MMACF32.

MR3 = MR3 + MR2;

MRd = MRe * MRf;
MRa = [mem32];

Restrictions The destination registers for the MMACF32 and the MMOV32 must be unique. That is,
MRa cannot be MR3 and MRa cannot be the same register as MRd.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMACF32 (add or multiply) generates an underflow condition.
• LVF = 1 if MMACF32 (add or multiply) generates an overflow condition.
MMOV32 sets the NF and ZF flags as follows:

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

Pipeline MMACF32 and MMOV32 complete in a single cycle.

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MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 (continued)

32-Bit Floating-Point Multiply and Accumulate with Parallel Move

Example 1
; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating-point arrays
;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3
;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X ; MAR0 points to X array
MMOVI16 MAR1, #_Y ; MAR1 points to Y array
MNOP ; Delay for MAR0, MAR1 load
MNOP ; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32 MR0, *MAR0[2]++ ; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y0, MAR1 += 2
MMPYF32 MR2, MR0, MR1 ; MR2 = A = X0 * Y0
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X1, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y1, MAR1 += 2
MMPYF32 MR3, MR0, MR1 ; MR3 = B = X1 * Y1
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X2, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y2, MAR2 += 2
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X3
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y3 M
MACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 * Y3
|| MMOV32 MR0, *MAR0 ; In parallel MR0 = X4
MMOV32 MR1, *MAR1 ; MR1 = Y4
MMPYF32 MR2, MR0, MR1 ; MR2 = E = X4 * Y4
|| MADDF32 MR3, MR3, MR2 ; in parallel MR3 = (A + B + C) + D
MADDF32 MR3, MR3, MR2 ; MR3 = (A + B + C + D) + E
MMOV32 @_Result, MR3 ; Store the result
MSTOP ; end of task

Example 2
; sum = X0*B0 + X1*B1 + X2*B2 + Y1*A1 + Y2*B2
;
; X2 = X1
; X1 = X0
; Y2 = Y1 ; Y1 = sum
;
_ClaTask2:
MMOV32 MR0, @_B2 ; MR0 = B2
MMOV32 MR1, @_X2 ; MR1 = X2
MMPYF32 MR2, MR1, MR0 ; MR2 = X2*B2
|| MMOV32 MR0, @_B1 ; MR0 = B1
MMOVD32 MR1, @_X1 ; MR1 = X1, X2 = X1
MMPYF32 MR3, MR1, MR0 ; MR3 = X1*B1
|| MMOV32 MR0, @_B0 ; MR0 = B0
MMOVD32 MR1, @_X0 ; MR1 = X0, X1 = X0
; MR3 = X1*B1 + X2*B2, MR2 = X0*B0
; MR0 = A2
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A2 M

MOV32 MR1, @_Y2 ; MR1 = Y2

; MR3 = X0*B0 + X1*B1 + X2*B2, MR2 = Y2*A2
; MR0 = A1
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A1
MMOVD32 MR1,@_Y1 ; MR1 = Y1, Y2 = Y1
MADDF32 MR3, MR3, MR2 ; MR3 = Y2*A2 + X0*B0 + X1*B1 + X2*B2
|| MMPYF32 MR2, MR1, MR0 ; MR2 = Y1*A1
MADDF32 MR3, MR3, MR2 ; MR3 = Y1*A1 + Y2*A2 + X0*B0 + X1*B1 + X2*B2

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MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 (continued)

32-Bit Floating-Point Multiply and Accumulate with Parallel Move

MMOV32 @_Y1, MR3 ; Y1 = MR3

MSTOP ; end of task

See also MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MMAXF32 MRa, MRb

32-Bit Floating-Point Maximum

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0010 0000

Description
if(MRa < MRb) MRa = MRb;

Special cases for the output from the MMAXF32 operation:

• NaN output is converted to infinity
• A denormalized output is converted to positive zero.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored in
the destination register.

if(MRa == MRb) {ZF=1; NF=0;}

if(MRa > MRb) {ZF=0; NF=0;}
if(MRa < MRb) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example 1
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #-2.0 ; MR1 = -2.0 (0xC0000000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMAXF32 MR2, MR1 ; MR2 = -1.5, ZF = NF = 0
MMAXF32 MR1, MR2 ; MR1 = -1.5, ZF = 0, NF = 1
MMAXF32 MR2, MR0 ; MR2 = 5.0, ZF = 0, NF = 1
MAXF32 MR0, MR2 ; MR2 = 5.0, ZF = 1, NF = 0

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MMAXF32 MRa, MRb (continued)

32-Bit Floating-Point Maximum

Example 2
; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store the value in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

See also MCMPF32 MRa, MRb

MCMPF32 MRa, #16FHi
MMAXF32 MRa, #16FHi
MMINF32 MRa, MRb
MMINF32 MRa, #16FHi

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MMAXF32 MRa, #16FHi

32-Bit Floating-Point Maximum

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1001 0000 00aa

Description Compare MRa with the floating-point value represented by the immediate operand. If the
immediate value is larger, then load the value into MRa.

if(MRa < #16FHi:0) MRa = #16FHi:0;

#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler accepts either a hex or float as the immediate value.
That is, -1.5 can be represented as #-1.5 or #0xBFC0.
Special cases for the output from the MMAXF32 operation:
• NaN output is converted to infinity
• A denormalized output is converted to positive zero.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored in
the destination register.

if(MRa == #16FHi:0) {ZF=1; NF=0;}

if(MRa > #16FHi:0) {ZF=0; NF=0;}
if(MRa < #16FHi:0) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMAXF32 MR0, #5.5 ; MR0 = 5.5, ZF = 0, NF = 1
MMAXF32 MR1, #2.5 ; MR1 = 4.0, ZF = 0, NF = 0
MMAXF32 MR2, #-1.0 ; MR2 = -1.0, ZF = 0, NF = 1
MMAXF32 MR2, #-1.0 ; MR2 = -1.5, ZF = 1, NF = 0

See also MMAXF32 MRa, MRb

MMINF32 MRa, MRb
MMINF32 MRa, #16FHi

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MMINF32 MRa, MRb

32-Bit Floating-Point Minimum

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0100 0000

Description
if(MRa > MRb) MRa = MRb;

Special cases for the output from the MMINF32 operation:

• NaN output is converted to infinity
• A denormalized output is converted to positive zero.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored in
the destination register.

if(MRa == MRb) {ZF=1; NF=0;}

if(MRa > MRb) {ZF=0; NF=0;}
if(MRa < MRb) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example 1
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMINF32 MR0, MR1 ; MR0 = 4.0, ZF = 0, NF = 0
MMINF32 MR1, MR2 ; MR1 = -1.5, ZF = 0, NF = 0
MMINF32 MR2, MR1 ; MR2 = -1.5, ZF = 1, NF = 0
MMINF32 MR1, MR0 ; MR2 = -1.5, ZF = 0, NF = 1

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MMINF32 MRa, MRb (continued)

32-Bit Floating-Point Minimum

Example 2
;
; X is an array of 32-bit floating-point values
; Find the minimum value in an array X
; and store the value in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMINF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

See also MMAXF32 MRa, MRb

MMAXF32 MRa, #16FHi
MMINF32 MRa, #16FHi

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MMINF32 MRa, #16FHi

32-Bit Floating-Point Minimum

Operands MRa floating-point source/destination register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1001 0100 00aa

Description Compare MRa with the floating-point value represented by the immediate operand. If the
immediate value is smaller, then load the value into MRa.

if(MRa > #16FHi:0) MRa = #16FHi:0;

#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler accepts either a hex or float as the immediate value.
That is, -1.5 can be represented as #-1.5 or #0xBFC0.
Special cases for the output from the MMINF32 operation:
• NaN output is converted to infinity
• A denormalized output is converted to positive zero.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored in
the destination register.

if(MRa == #16FHi:0) {ZF=1; NF=0;}

if(MRa > #16FHi:0) {ZF=0; NF=0;}
if(MRa < #16FHi:0) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMINF32 MR0, #5.5 ; MR0 = 5.0, ZF = 0, NF = 1
MMINF32 MR1, #2.5 ; MR1 = 2.5, ZF = 0, NF = 0
MMINF32 MR2, #-1.0 ; MR2 = -1.5, ZF = 0, NF = 1
MMINF32 MR2, #-1.5 ; MR2 = -1.5, ZF = 1, NF = 0

See also MMAXF32 MRa, #16FHi

MMAXF32 MRa, MRb
MMINF32 MRa, MRb

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MMOV16 MARx, MRa, #16I

Load the Auxiliary Register with MRa + 16-bit Immediate Value

Operands MARx Auxiliary register MAR0 or MAR1

MRa CLA Floating-point register (MR0 to MR3)
#16I 16-bit immediate value

Opcode
LSW: IIII IIII IIII IIII (opcode of MMOV16 MAR0, MRa, #16I)
MSW: 0111 1111 1101 00AA
LSW: IIII IIII IIII IIII (opcode of MMOV16 MAR1, MRa, #16I)
MSW: 0111 1111 1111 00AA

Description Load the auxiliary register, MAR0 or MAR1, with MRa(15:0) + 16-bit immediate value.
Refer to the Pipeline section for important information regarding this instruction.

MARx = MRa(15:0) + #16I;

Flags This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction. The load of MAR0 or MAR1 occurs in the EXE phase
of the pipeline. Any post increment of MAR0 or MAR1 using indirect addressing occurs in
the D2 phase of the pipeline. Therefore, the following applies when loading the auxiliary
registers:
• I1 and I2
The two instructions following MMOV16 use MAR0 or MAR1 before the update occurs.
Thus, these two instructions use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-
increment addressing occur in the D2 phase. Thus, I3 cannot use the auxiliary register
or there is a conflict. In the case of a conflict, the update due to address-mode post
increment wins and the auxiliary register is not updated with #_X.
• I4
Starting with the 4th instruction, MAR0 or MAR1 is the new value loaded with
MMOVI16.

; Assume MAR0 is 50, MR0 is 10, and #_X is 20

MMOV16 MAR0, MR0, #_X ; Load MAR0 with address of X (20) + MR0 (10)
<Instruction 1> ; I1 Uses the old value of MAR0 (50)
<Instruction 2> ; I2 Uses the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Uses the new value of MAR0 (30)
<Instruction 5> ; I5

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MMOV16 MARx, MRa, #16I (continued)

Load the Auxiliary Register with MRa + 16-bit Immediate Value

Table 7-16. Pipeline Activity for MMOV16 MARx, MRa , #16I

Instruction F1 F2 D1 D2 R1 R2 E W
MMOV16 MAR0, MR0,
MMOV16
#_X
I1 I1 MMOV16
I2 I2 I1 MMOV16
I3 I3 I2 I1 MMOV16
I4 I4 I3 I2 I1 MMOV16
I5 I5 I4 I3 I2 I1 MMOV16
I6 I6 I5 I4 I3 I2 I1 MMOV16

Example 1
; Calculate an offset into a sin/cos table
;
_Cla1Task1:
MMOV32 MR0,@_rad ; MR0 = rad
MMOV32 MR1,@_TABLE_SIZEDivTwoPi ; MR1 = TABLE_SIZE/(2*Pi)
MMPYF32 MR1,MR0,MR1 ; MR1 = rad* TABLE_SIZE/(2*Pi)
|| MMOV32 MR2,@_TABLE_MASK ; MR2 = TABLE_MASK
MF32TOI32 MR3,MR1 ; MR3 = K=int(rad*TABLE_SIZE/(2*Pi))
MAND32 MR3,MR3,MR2 ; MR3 = K & TABLE_MASK
MLSL32 MR3,#1 ; MR3 = K * 2
MMOV16 MAR0,MR3,#_Cos0 ; MAR0 K*2+addr of table.Cos0
MFRACF32 MR1,MR1 ; I1
MMOV32 MR0,@_TwoPiDivTABLE_SIZE ; I2
MMPYF32 MR1,MR1,MR0 ; I3
|| MMOV32 MR0,@_Coef3
MMOV32 MR2,*MAR0[#-64]++ ; MR2 = *MAR0, MAR0 += (-64)
...
...
MSTOP ; end of task

Example 2
; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task goes back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC triggers this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
; T_sys = 1/200MHz = 5ns
; T_adc = 4*T_sys = 20ns
; The ADC takes 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register can be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg 0, N
.loop
MNOP ;I1 - I28 Wait till I36 to read
result
.eval N + 1, N
.break N = 28
.endloop

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MMOV16 MARx, MRa, #16I (continued)

Load the Auxiliary Register with MRa + 16-bit Immediate Value

MMOVZ16 MR0, @_ConversionCount ;I29 Current Conversion

MMOV16 MAR1, MR0, #_VoltageCLA ;I30 Next array location
MUI16TOF32 MR0, MR0 ;I31 Convert count to float32
MADDF32 MR0, MR0, #1.0 ;I32 Add 1 to conversion count
MCMPF32 MR0, #NUM_DATA_POINTS.0 ;I33 Compare count to max
MF32TOUI16 MR0, MR0 ;I34 Convert count to Uint16
MNOP ;I35 Wait till I36 to read
result
MMOVZ16 MR2, @_AdcaResultRegs.ADCRESULT1 ;I36 Read ADCRESULT1
MMOV16 *MAR1, MR2 ; Store ADCRESULT1
MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS
MMOVIZ MR1, #0.0 ; Always executed: MR1=0
MNOP
MNOP
MMOV16 @_ConversionCount, MR0 ; If branch not taken
MSTOP ; store current count
_RestartCount
MMOV16 @_ConversionCount, MR1 ; If branch taken, restart
count
MSTOP ; end of task
; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ MR0, #0.0
MMOV16 @_ConversionCount, MR0
MSTOP
_ClaT8End:

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MMOV16 MARx, mem16

Load MAR1 with 16-bit Value

Operands MARx CLA auxiliary register MAR0 or MAR1

mem16 16-bit destination memory accessed using one of the available
addressing modes

Opcode
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 MAR0, mem16)
MSW: 0111 0110 0000 addr
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 MAR1, mem16)
MSW: 0111 0110 0100 addr

Description Load MAR0 or MAR1 with the 16-bit value pointed to by mem16. Refer to the Pipeline
section for important information regarding this instruction.

MAR1 = [mem16];

Flags No flags MSTF flags are affected.

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction. The load of MAR0 or MAR1 occurs in the EXE phase
of the pipeline. Any post increment of MAR0 or MAR1 using indirect addressing occurs in
the D2 phase of the pipeline. Therefore, the following applies when loading the auxiliary
registers:
• I1 and I2
The two instructions following MMOV16 use MAR0 or MAR1 before the update occurs.
Thus, these two instructions use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-
increment addressing occur in the D2 phase. Thus, I3 cannot use the auxiliary register
or there is a conflict. In the case of a conflict, the update due to address-mode post
increment, the auxiliary register is not updated with #_X.
• I4
Starting with the 4th instruction, MAR0 or MAR1 is the new value loaded with
MMOV16.

; Assume MAR0 is 50 and @_X is 20

MMOV16 MAR0, @_X ; Load MAR0 with the contents of X (20)
<Instruction 1> ; I1 Uses the old value of MAR0 (50)
<Instruction 2> ; I2 Uses the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Uses the new value of MAR0 (20)
<Instruction 5> ; I5
....

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MMOV16 MARx, mem16 (continued)

Load MAR1 with 16-bit Value

Table 7-17. Pipeline Activity for MMOV16 MAR0/MAR1, mem16

Instruction F1 F2 D1 D2 R1 R2 E W
MMOV16 MAR0, @_X MMOV16
I1 I1 MMOV16
I2 I2 I1 MMOV16
I3 I3 I2 I1 MMOV16
I4 I4 I3 I2 I1 MMOV16
I5 I5 I4 I3 I2 I1 MMOV16
I6 I6 I5 I4 I3 I2 I1 MMOV16

Example
; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task goes back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC triggers this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
; T_sys = 1/200MHz = 5ns
; T_adc = 4*T_sys = 20ns
; The ADC takes 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register can be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg 0, N
.loop
MNOP
;I1 - I28 Wait till I36 to read result
.eval N + 1, N
.break N = 28
.endloop
MMOVZ16 MR0, @_ConversionCount ;I29 Current Conversion
MMOV16 MAR1, MR0, #_VoltageCLA ;I30 Next array location
MUI16TOF32 MR0, MR0 ;I31 Convert count to float32
MADDF32 MR0, MR0, #1.0 ;I32 Add 1 to conversion count
MCMPF32 MR0, #NUM_DATA_POINTS.0 ;I33 Compare count to max
MF32TOUI16 MR0, MR0 ;I34 Convert count to Uint16
MNOP ;I35 Wait until I36 to read
result
MMOVZ16 MR2, @_AdcaResultRegs.ADCRESULT1 ;I36 Read ADCRESULT1
MMOV16 *MAR1, MR2 ; Store ADCRESULT1
MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS
MMOVIZ MR1, #0.0 ; Always executed: MR1=0
MNOP
MNOP
MMOV16 @_ConversionCount, MR0 ; If branch not taken
MSTOP ; store current count
_RestartCount
MMOV16 @_ConversionCount, MR1 ; If branch taken, restart
count
MSTOP ; end of task
; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:

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MMOV16 MARx, mem16 (continued)

Load MAR1 with 16-bit Value

MMOVIZ MR0, #0.0

MMOV16 @_ConversionCount, MR0
MSTOP
_ClaT8End:

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MMOV16 mem16, MARx

Move 16-Bit Auxiliary Register Contents to Memory

Operands mem16 16-bit destination memory accessed using one of the available
addressing modes
MARx CLA auxiliary register MAR0 or MAR1

Opcode
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 mem16, MAR0)
MSW: 0111 0110 1000 addr
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 mem16, MAR1)
MSW: 0111 0110 1100 addr

Description Store the contents of MAR0 or MAR1 in the 16-bit memory location pointed to by mem16.

[mem16] = MAR0;

Flags No flags MSTF flags are affected.

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

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MMOV16 mem16, MRa

Move 16-Bit Floating-Point Register Contents to Memory

Operands mem16 16-bit destination memory accessed using one of the available
addressing modes
MRa CLA floating-point source register (MR0 to MR3)

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 11aa addr

Description Move 16-bit value from the lower 16-bits of the floating-point register (MRa(15:0)) to the
location pointed to by mem16.

[mem16] = MRa(15:0);

Flags No flags MSTF flags are affected.

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task goes back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC triggers this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
; T_sys = 1/200MHz = 5ns
; T_adc = 4*T_sys = 20ns
; The ADC takes 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register can be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg 0, N
.loop
MNOP
;I1 - I28 Wait till I36 to read result
.eval N + 1, N
.break N = 28
.endloop
MMOVZ16 MR0, @_ConversionCount ;I29 Current Conversion
MMOV16 MAR1, MR0, #_VoltageCLA ;I30 Next array location
MUI16TOF32 MR0, MR0 ;I31 Convert count to float32
MADDF32 MR0, MR0, #1.0 ;I32 Add 1 to conversion count
MCMPF32 MR0, #NUM_DATA_POINTS.0 ;I33 Compare count to max
MF32TOUI16 MR0, MR0 ;I34 Convert count to Uint16
MNOP ;I35 Wait till I36 to read
result
MMOVZ16 MR2, @_AdcaResultRegs.ADCRESULT1 ;I36 Read ADCRESULT1
MMOV16 *MAR1, MR2 ; Store ADCRESULT1
MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS
MMOVIZ MR1, #0.0 ; Always executed: MR1=0

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MMOV16 mem16, MRa (continued)

Move 16-Bit Floating-Point Register Contents to Memory

MNOP
MNOP
MMOV16 @_ConversionCount, MR0 ; If branch not taken
MSTOP ; store current count
_RestartCount
MMOV16 @_ConversionCount, MR1 ; If branch taken, restart
count
MSTOP ; end of task
; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ MR0, #0.0
MMOV16 @_ConversionCount, MR0
MSTOP
_ClaT8End:

See also MMOVIZ MRa, #16FHi

MMOVXI MRa, #16FLoHex

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MMOV32 mem32, MRa

Move 32-Bit Floating-Point Register Contents to Memory

Operands MRa floating-point register (MR0 to MR3)

mem32 32-bit destination memory accessed using one of the available
addressing modes

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 11aa addr

Description Move from MRa to 32-bit memory location indicated by mem32.

[mem32] = MRa;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

No flags affected.
Pipeline This is a single-cycle instruction.

Example
; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating-point arrays;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X ; MAR0 points to X array
MMOVI16 MAR1, #_Y ; MAR1 points to Y array
MNOP ; Delay for MAR0, MAR1 load
MNOP ; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32 MR0, *MAR0[2]++ ; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y0, MAR1 += 2
MMPYF32 MR2, MR0, MR1 ; MR2 = A = X0 * Y0
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X1, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y1, MAR1 += 2
MMPYF32 MR3, MR0, MR1 ; MR3 = B = X1 * Y1
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X2, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y2, MAR2 += 2
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X3
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y3
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 *
Y3
|| MMOV32 MR0, *MAR0 ; In parallel MR0 = X4
MMOV32 MR1, *MAR1 ; MR1 = Y4
MMPYF32 MR2, MR0, MR1 ; MR2 = E = X4 * Y4
|| MADDF32 MR3, MR3, MR2 ; in parallel MR3 = (A + B + C) + D
MADDF32 MR3, MR3, MR2 ; MR3 = (A + B + C + D) + E
MMOV32 @_Result, MR3 ; Store the result MSTOP ; end of task

See also MMOV32 mem32, MSTF

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MMOV32 mem32, MSTF

Move 32-Bit MSTF Register to Memory

Operands MSTF Floating-point status register

mem32 32-bit destination memory

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0111 0100 addr

Description Copy the CLA floating-point status register, MSTF, to memory.

[mem32] = MSTF;

Flags This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

One of the uses of this instruction is to save off the return PC (RPC) prior to calling a
function. The decision to jump to a function is made when the MCCNDD is in the decode2
(D2) phase of the pipeline; the RPC is also updated in this phase. The actual jump occurs
3 cycles later when MCCNDD enters the execution (E) phase. You must save the old RPC
before MCCNDD updates in the D2 phase; that is, save MSTF 3 instructions prior to the
function call.

Example The following example illustrates the pipeline flow for the context save (of the flags and
RPC) prior to a function call. The first column in the comments shows the pipeline stages
for the MMOV32 instruction while the second column pertains to the MCCNDD instruction.

MMOV32 @_temp, MSTF ; D2| |

MNOP ; R1|F1| MCCNDD is fetched
MNOP ; R2|F2|
MNOP ; E |D1|
MCCNDD _bar, UNC ; W |D2| old RPC written to memory,
; | | RPC updated with MPC+1
MNOP ; |R1|
MNOP ; |R2|
MNOP ; |E | execution branches to _bar

See also MMOV32 mem32, MRa

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MMOV32 MRa, mem32 {, CNDF}

Conditional 32-Bit Move

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem32 32-bit memory location accessed using one of the available
addressing modes
CNDF Optional condition

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 00cn dfaa addr

Description If the condition is true, then move the 32-bit value referenced by mem32 to the floating-
point register indicated by MRa.

if (CNDF == TRUE) MRa = [mem32];

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

if(CNDF == UNCF)
{
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }
}
else No flags modified;

Pipeline This is a single-cycle instruction.

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MMOV32 MRa, mem32 {, CNDF} (continued)

Conditional 32-Bit Move

Example
; Given A, B, X, M1 and M2 are 32-bit floating-point numbers
;
; if(A == B) calculate Y = X*M1
; if(A! = B) calculate Y = X*M2
;
_Cla1Task5:
MMOV32 MR0, @_A
MMOV32 MR1, @_B
MCMPF32 MR0, MR1
MMOV32 MR2, @_M1, EQ ; if A == B, MR2 = M1
; Y = M1*X
MMOV32 MR2, @_M2, NEQ ; if A! = B, MR2 = M2
; Y = M2*X
MMOV32 MR3, @_X
MMPYF32 MR3, MR2, MR3 ; Calculate Y
MMOV32 @_Y, MR3 ; Store Y
MSTOP ; end of task

See also MMOV32 MRa, MRb {, CNDF}

MMOVD32 MRa, mem32

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MMOV32 MRa, MRb {, CNDF}

Conditional 32-Bit Move

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
CNDF Optional condition

Opcode
LSW: 0000 0000 cndf bbaa
MSW: 0111 1010 1100 0000

Description If the condition is true, then move the 32-bit value in MRb to the floating-point register
indicated by MRa.

if (CNDF == TRUE) MRa = MRb;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF, and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

if(CNDF == UNCF)
{
NF = MRa(31); ZF = 0;
if(MRa(30:23) == 0) {ZF = 1; NF = 0;}
}
else No flags modified;

Pipeline This is a single-cycle instruction.

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MMOV32 MRa, MRb {, CNDF} (continued)

Conditional 32-Bit Move

Example
; Given: X = 8.0
; Y = 7.0
; A = 2.0
; B = 5.0
; _ClaTask1
MMOV32 MR3, @_X ; MR3 = X = 8.0
MMOV32 MR0, @_Y ; MR0 = Y = 7.0
MMAXF32 MR3, MR0 ; ZF = 0, NF = 0, MR3 = 8.0
MMOV32 MR1, @_A, GT ; true, MR1 = A = 2.0
MMOV32 MR1, @_B, LT ; false, does not load MR1
MMOV32 MR2, MR1, GT ; true, MR2 = MR1 = 2.0
MMOV32 MR2, MR0, LT ; false, does not load MR2
MSTOP

See also MMOV32 MRa, mem32 {,CNDF}

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MMOV32 MSTF, mem32

Move 32-Bit Value from Memory to the MSTF Register

Operands MSTF CLA status register

mem32 32-bit source memory location

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0111 0000 addr

Description Move from memory to the CLA's status register MSTF. This instruction is most useful
when nesting function calls (using MCCNDD).

MSTF = [mem32];

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified Yes Yes Yes Yes Yes

Loading the status register can overwrite all flags and the RPC field. The MEALLOW field
is not affected.
Pipeline This is a single-cycle instruction.

See also MMOV32 mem32, MSTF

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MMOVD32 MRa, mem32

Move 32-Bit Value from Memory with Data Copy

Operands MRa CLA floating-point register (MR0 to MR3)

mem32 32-bit memory location accessed using one of the available
addressing modes

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 00aa addr

Description Move the 32-bit value referenced by mem32 to the floating-point register indicated by
MRa.

MRa = [mem32];
[mem32+2] = [mem32];

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0){ ZF = 1; NF = 0; }

Pipeline This is a single-cycle instruction.

Example
; sum = X0*B0 + X1*B1 + X2*B2 + Y1*A1 + Y2*B2
;
; X2 = X1
; X1 = X0
; Y2 = Y1
; Y1 = sum
;
_Cla1Task2:
MMOV32 MR0, @_B2 ; MR0 = B2
MMOV32 MR1, @_X2 ; MR1 = X2
MMPYF32 MR2, MR1, MR0 ; MR2 = X2*B2
|| MMOV32 MR0, @_B1 ; MR0 = B1
MMOVD32 MR1, @_X1 ; MR1 = X1, X2 = X1
MMPYF32 MR3, MR1, MR0 ; MR3 = X1*B1
|| MMOV32 MR0, @_B0 ; MR0 = B0
MMOVD32 MR1, @_X0 ; MR1 = X0, X1 = X0
; MR3 = X1*B1 + X2*B2, MR2 = X0*B0
; MR0 = A2
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A2

MMOV32 MR1, @_Y2 ; MR1 = Y2

; MR3 = X0*B0 + X1*B1 + X2*B2, MR2 = Y2*A2
; MR0 = A1
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A1
MMOVD32 MR1,@_Y1 ; MR1 = Y1, Y2 = Y1
MADDF32 MR3, MR3, MR2 ; MR3 = Y2*A2 + X0*B0 + X1*B1 + X2*B2
|| MMPYF32 MR2, MR1, MR0 ; MR2 = Y1*A1
MADDF32 MR3, MR3, MR2 ; MR3 = Y1*A1 + Y2*A2 + X0*B0 + X1*B1 + X2*B2
MMOV32 @_Y1, MR3 ; Y1 = MR3
MSTOP ; end of task

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MMOVD32 MRa, mem32 (continued)

Move 32-Bit Value from Memory with Data Copy

See also MMOV32 MRa, mem32 {,CNDF}

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MMOVF32 MRa, #32F

Load the 32-Bits of a 32-Bit Floating-Point Register

Operands This instruction is an alias for the MMOVIZ and MMOVXI instructions. The second
operand is translated by the assembler such that the instruction becomes:

MMOVIZ MRa, #16FHiHex MMOVXI MRa, #16FLoHex

MRa CLA floating-point destination register (MR0 to MR3)

#32F Immediate float value represented in floating-point representation

Opcode
LSW: IIII IIII IIII IIII (opcode of MMOVIZ MRa, #16FHiHex)
MSW: 0111 1000 0100 00aa
LSW: IIII IIII IIII IIII (opcode of MMOVXI MRa, #16FLoHex)
MSW: 0111 1000 1000 00aa

Description This instruction accepts the immediate operand only in floating-point representation. To
specify the immediate value as a hex value (IEEE 32-bit floating- point format), use the
MOVI32 MRa, #32FHex instruction.
Load the 32-bits of MRa with the immediate float value represented by #32F.
#32F is a float value represented in floating-point representation. The assembler only
accepts a float value represented in floating-point representation. That is, 3.0 can only be
represented as #3.0 (#0x40400000 results in an error).

MRa = #32F;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline Depending on #32F, this instruction takes one or two cycles. If all of the lower 16-bits
of the IEEE 32-bit floating-point format of #32F are zeros, then the assembler converts
MMOVF32 into only an MMOVIZ instruction. If the lower 16-bits of the IEEE 32-bit
floating-point format of #32F are not zeros, then the assembler converts MMOVF32 into
MMOVIZ and MMOVXI instructions.

Example
MMOVF32 MR1, #3.0 ; MR1 = 3.0 (0x40400000)
; Assembler converts this instruction as
; MMOVIZ MR1, #0x4040
MMOVF32 MR2, #0.0 ; MR2 = 0.0 (0x00000000)
; Assembler converts this instruction as
; MMOVIZ MR2, #0x0
MMOVF32 MR3, #12.265 ; MR3 = 12.625 (0x41443D71)
; Assembler converts this instruction as
; MMOVIZ MR3, #0x4144
; MMOVXI MR3, #0x3D71

See also MMOVIZ MRa, #16FHi

MMOVXI MRa, #16FLoHex
MMOVI32 MRa, #32FHex

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MMOVI16 MARx, #16I

Load the Auxiliary Register with the 16-Bit Immediate Value

Operands MARx Auxiliary register MAR0 or MAR1

#16I 16-bit immediate value

Opcode
LSW: IIII IIII IIII IIII (opcode of MMOVI16 MAR0, #16I)
MSW: 0111 1111 1100 0000
LSW: IIII IIII IIII IIII (opcode of MMOVI16 MAR1, #16I)
MSW: 0111 1111 1110 0000

Description Load the auxiliary register, MAR0 or MAR1, with a 16-bit immediate value. Refer to the
Pipeline section for important information regarding this instruction.

MARx = #16I;

Flags This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction. The immediate load of MAR0 or MAR1 occurs in
the EXE phase of the pipeline. Any post increment of MAR0 or MAR1 using indirect
addressing occurs in the D2 phase of the pipeline. Therefore, the following applies when
loading the auxiliary registers:
• I1 and I2
The two instructions following MMOVI16 use MAR0 or MAR1 before the update
occurs. Thus, these two instructions use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-
increment addressing occur in the D2 phase. Thus, I3 cannot use the auxiliary register
or there is a conflict. In the case of a conflict, the update due to address-mode post
increment, the auxiliary register is not updated with #_X.
• I4
Starting with the 4th instruction, MAR0 or MAR1 is the new value loaded with
MMOVI16.

; Assume MAR0 is 50 and #_X is 20

MMOVI16 MAR0, #_X ; Load MAR0 with address of X (20)
<Instruction 1> ; I1 Uses the old value of MAR0 (50)
<Instruction 2> ; I2 Uses the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Uses the new value of MAR0 (20)
<Instruction 5> ; I5
....

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MMOVI16 MARx, #16I (continued)

Load the Auxiliary Register with the 16-Bit Immediate Value

Table 7-18. Pipeline Activity for MMOVI16 MAR0/MAR1, #16I

Instruction F1 F2 D1 D2 R1 R2 E W
MMOVI16 MAR0, #_X MMOVI16
I1 I1 MMOVI16
I2 I2 I1 MMOVI16
I3 I3 I2 I1 MMOVI16
I4 I4 I3 I2 I1 MMOVI16
I5 I5 I4 I3 I2 I1 MMOVI16
I6 I6 I5 I4 I3 I2 I1 MMOVI16

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MMOVI32 MRa, #32FHex

Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate

Operands MRa Floating-point register (MR0 to MR3)

#32FHex A 32-bit immediate value that represents an IEEE 32-bit floating-
point value.

This instruction is an alias for the MMOVIZ and MMOVXI instructions. The second
operand is translated by the assembler such that the instruction becomes:

MMOVIZ MRa, #16FHiHex

MMOVXI MRa, #16FLoHex

Opcode
LSW: IIII IIII IIII IIII (opcode of MMOVIZ MRa, #16FHiHex)
MSW: 0111 1000 0100 00aa
LSW: IIII IIII IIII IIII (opcode of MMOVXI MRa, #16FLoHex)
MSW: 0111 1000 1000 00aa

Description This instruction only accepts a hex value as the immediate operand. To specify the
immediate value with a floating-point representation, use the MMOVF32 MRa, #32F
instruction.
Load the 32-bits of MRa with the immediate 32-bit hex value represented by #32FHex.
#32FHex is a 32-bit immediate hex value that represents the IEEE 32-bit floating-point
value of a floating-point number. The assembler only accepts a hex immediate value. That
is, 3.0 can only be represented as #0x40400000 (#3.0 results in an error).

MRa = #32FHex;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline Depending on #32FHex, this instruction takes one or two cycles. If all of the lower 16-bits
of #32FHex are zeros, then the assembler converts MOVI32 to an MMOVIZ instruction.
If the lower 16-bits of #32FHex are not zeros, then the assembler converts MOVI32 to
MMOVIZ and MMOVXI instructions.

Example
MOVI32 MR1, #0x40400000 ; MR1 = 0x40400000
; Assembler converts this instruction as
; MMOVIZ MR1, #0x4040
MOVI32 MR2, #0x00000000 ; MR2 = 0x00000000
; Assembler converts this instruction as
; MMOVIZ MR2, #0x0
MOVI32 MR3, #0x40004001 ; MR3 = 0x40004001
; Assembler converts this instruction as
; MMOVIZ MR3, #0x4000
; MMOVXI MR3, #0x4001
MOVI32 MR0, #0x00004040 ; MR0 = 0x00004040
; Assembler converts this instruction as
; MMOVIZ MR0, #0x0000
; MMOVXI MR0, #0x4040

See also MMOVIZ MRa, #16FHi

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MMOVI32 MRa, #32FHex (continued)

Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate

MMOVXI MRa, #16FLoHex

MMOVF32 MRa, #32F

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MMOVIZ MRa, #16FHi

Load the Upper 16-Bits of a 32-Bit Floating-Point Register

Operands MRa Floating-point register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1000 0100 00aa

Description Load the upper 16-bits of MRa with the immediate value #16FHi and clear the low 16-bits
of MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE
32-bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0.
The assembler only accepts a decimal or hex immediate value. That is, -1.5 can be
represented as #-1.5 or #0xBFC0.
By itself, MMOVIZ is useful for loading a floating-point register with a constant in which
the lowest 16-bits of the mantissa are 0. Some examples are 2.0 (0x40000000), 4.0
(0x40800000), 0.5 (0x3F000000), and -1.5 (0xBFC00000). If a constant requires all 32-
bits of a floating-point register to be initialized, then use MMOVIZ along with the MMOVXI
instruction.

MRa(31:16) = #16FHi;
MRa(15:0) = 0;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
; Load MR0 and MR1 with -1.5 (0xBFC00000)
MMOVIZ MR0, #0xBFC0 ; MR0 = 0xBFC00000 (1.5)
MMOVIZ MR1, #-1.5 ; MR1 = -1.5 (0xBFC00000)
; Load MR2 with pi = 3.141593 (0x40490FDB)
MMOVIZ MR2, #0x4049 ; MR2 = 0x40490000
MMOVXI MR2, #0x0FDB ; MR2 = 0x40490FDB

See also MMOVF32 MRa, #32F

MMOVI32 MRa, #32FHex
MMOVXI MRa, #16FLoHex

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MMOVZ16 MRa, mem16

Load MRx with 16-Bit Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem16 16-bit source memory location

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 10aa addr

Description Move the 16-bit value referenced by mem16 to the floating-point register indicated by
MRa.

MRa(31:16) = 0;
MRa(15:0) = [mem16];

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = 0;
if (MRa(31:0)== 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

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MMOVXI MRa, #16FLoHex

Move Immediate Value to the Lower 16-Bits of a Floating-Point Register

Operands MRa CLA floating-point register (MR0 to MR3)

#16FLoHex A 16-bit immediate hex value that represents the lower 16-bits
of an IEEE 32-bit floating-point value. The upper 16-bits are not
modified.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1000 1000 00aa

Description Load the lower 16-bits of MRa with the immediate value #16FLoHex. #16FLoHex
represents the lower 16-bits of an IEEE 32-bit floating-point value. The upper 16-bits of
MRa are not modified. MMOVXI can be combined with the MMOVIZ instruction to initialize
all 32-bits of a MRa register.

MRa(15:0) = #16FLoHex;
MRa(31:16) = Unchanged;

Flags Flag TF ZF NF LUF LVF

Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
; Load MR0 with pi = 3.141593 (0x40490FDB)
MMOVIZ MR0,#0x4049 ; MR0 = 0x40490000
MMOVXI MR0,#0x0FDB ; MR0 = 0x40490FDB

See also MMOVIZ MRa, #16FHi

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MMPYF32 MRa, MRb, MRc

32-Bit Floating-Point Multiply

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 0000 0000

Description Multiply the contents of two floating-point registers.

MRa = MRb * MRc;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.
Pipeline This is a single-cycle instruction.

Example
; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den ; MR1 = Den
MEINVF32 MR2, MR1 ; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num ; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den ; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ ; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0 ; Store result
MSTOP ; end of task

See also MMPYF32 MRa, #16FHi, MRb

MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf
MMPYF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MMPYF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf
MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRa, #16FHi, MRb

32-Bit Floating-Point Multiply

Operands MRa CLA floating-point destination register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The lower 16-bits of the mantissa
are assumed to be all 0.
MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 0111 1000 bbaa

Description Multiply MRb with the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The lower 16-bits of the mantissa are assumed to be all 0. #16FHi
is most useful for representing constants where the lowest 16-bits of the mantissa are
0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = MRb * #16FHi:0;

This instruction can also be written as MMPYF32 MRa, MRb, #16FHi.

Flags This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.
Pipeline This is a single-cycle instruction.

Example 1
; Same as example 2 but #16FHi is represented in float
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, #3.0, MR3 ; MR0 = 3.0 * MR3 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

Example 2
; Same as example 1 but #16FHi is represented in Hex
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, #0x4040, MR3 ; MR0 = 0x4040 * MR3 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

Example 3
; Given X, M, and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;

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MMPYF32 MRa, #16FHi, MRb (continued)

32-Bit Floating-Point Multiply

;
_Cla1Task2:
;
; Convert M, X, and B from IQ24 to float
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also MMPYF32 MRa, MRb, #16FHi

MMPYF32 MRa, MRb, MRc
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MMPYF32 MRa, MRb, #16FHi

32-Bit Floating-Point Multiply

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The lower 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 0111 1000 bbaa

Description Multiply MRb with the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = MRb * #16FHi:0;

This instruction can also be written as MMPYF32 MRa, #16FHi, MRb.

Flags This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.

Pipeline This is a single-cycle instruction.

Example 1
;Same as example 2 but #16FHi is represented in float
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, MR3, #3.0 ; MR0 = MR3 * 3.0 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

Example 2
;Same as example 1 but #16FHi is represented in Hex
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, MR3, #0x4040 ; MR0 = MR3 * 0x4040 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

Example 3
; Given X, M, and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;

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MMPYF32 MRa, MRb, #16FHi (continued)

32-Bit Floating-Point Multiply

_Cla1Task2:
;
; Convert M, X, and B from IQ24 to float
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, #0x3380, MR0 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, #0x3380, MR1 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, #0x3380, MR2 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, #0x4B80, MR2 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also MMPYF32 MRa, #16FHi, MRb

MMPYF32 MRa, MRb, MRc

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MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf

32-Bit Floating-Point Multiply with Parallel Add

Operands MRa CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRa cannot be the same register as MRd
MRb CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRc CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRd CLA floating-point destination register for MADDF32 (MR0 to MR3)
MRd cannot be the same register as MRa
MRe CLA floating-point source register for MADDF32 (MR0 to MR3)
MRf CLA floating-point source register for MADDF32 (MR0 to MR3)

Opcode
LSW: 0000 ffee ddcc bbaa
MSW: 0111 1010 0000 0000

Description Multiply the contents of two floating-point registers with parallel addition of two registers.

MRa = MRb * MRc;

MRd = MRe + MRf;

Restrictions The destination register for the MMPYF32 and the MADDF32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 or MADDF32 generates an underflow condition.
• LVF = 1 if MMPYF32 or MADDF32 generates an overflow condition.

Pipeline Both MMPYF32 and MADDF32 complete in a single cycle.

Example
; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating-point arrays
;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3
;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X ; MAR0 points to X array
MMOVI16 MAR1, #_Y ; MAR1 points to Y array
MNOP ; Delay for MAR0, MAR1 load
MNOP ; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32 MR0, *MAR0[2]++ ; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y0, MAR1 += 2
MMPYF32 MR2, MR0, MR1 ; MR2 = A = X0 * Y0
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X1, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y1, MAR1 += 2
MMPYF32 MR3, MR0, MR1 ; MR3 = B = X1 * Y1

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MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf (continued)

32-Bit Floating-Point Multiply with Parallel Add

|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X2, MAR0 += 2

MMOV32 MR1, *MAR1[2]++ ; MR1 = Y2, MAR2 += 2
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X3
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y3
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 * Y3
|| MMOV32 MR0, *MAR0 ; In parallel MR0 = X4
MMOV32 MR1, *MAR1 ; MR1 = Y4
MMPYF32 MR2, MR0, MR1 ; MR2 = E = X4 * Y4
|| MADDF32 MR3, MR3, MR2 ; in parallel MR3 = (A + B + C) + D

MADDF32 MR3, MR3, MR2 ; MR3 = (A + B + C + D) + E

MMOV32 @_Result, MR3 ; Store the result
MSTOP ; end of task

See also MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32

32-Bit Floating-Point Multiply with Parallel Move

Operands MRd CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRd cannot be the same register as MRa
MRe CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRf CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRa CLA floating-point destination register for MMOV32 (MR0 to MR3)
MRa cannot be the same register as MRd
mem32 32-bit memory location accessed using one of the available
addressing modes. This is the source of MMOV32.

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0000 ffee ddaa addr

Description Multiply the contents of two floating-point registers and load another.

MRd = MRe * MRf;

MRa = [mem32];

Restrictions The destination register for the MMPYF32 and the MMOV32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.
The MMOV32 instruction sets the NF and ZF flags as follows:

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

Pipeline Both MMPYF32 and MMOV32 complete in a single cycle.

Example 1
; Given M1, X1, and B1 are 32-bit floating point
; Calculate Y1 = M1*X1+B1
;
_Cla1Task1:
MMOV32 MR0, @M1 ; Load MR0 with M1
MMOV32 MR1, @X1 ; Load MR1 with X1
MMPYF32 MR1, MR1, MR0 ; Multiply M1*X1
|| MMOV32 MR0, @B1 ; and in parallel load MR0 with B1
MADDF32 MR1, MR1, MR0 ; Add M*X1 to B1 and store in MR1
MMOV32 @Y1, MR1 ; Store the result
MSTOP ; end of task

Example 2
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A * B) * C

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MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 (continued)

32-Bit Floating-Point Multiply with Parallel Move

;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR1, MR1, MR0 ; Multiply A*B
|| MMOV32 MR0, @C ; and in parallel load MR0 with C
MMPYF32 MR1, MR1, MR0 ; Multiply (A*B) by C
|| MMOV32 @Y2, MR1 ; and in parallel store A*B
MMOV32 @Y3, MR1 ; Store the result
MSTOP ; end of task

See also MMPYF32 MRd, MRe, MRf || MMOV32 mem32, MRa

MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa

32-Bit Floating-Point Multiply with Parallel Move

Operands MRd CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRe CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRf CLA floating-point source register for MMPYF32 (MR0 to MR3)
mem32 32-bit memory location accessed using one of the available
addressing modes. This is the destination of MMOV32.
MRa CLA floating-point source register for MMOV32 (MR0 to MR3)

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0100 ffee ddaa addr

Description Multiply the contents of two floating-point registers and move from memory to register.

MRd = MRe * MRf;

[mem32] = MRa;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.

Pipeline MMPYF32 and MMOV32 both complete in a single cycle.

Example
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A * B) * C
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR1, MR1, MR0 ; Multiply A*B
|| MMOV32 MR0, @C ; and in parallel load MR0 with C
MMPYF32 MR1, MR1, MR0 ; Multiply (A*B) by C
|| MMOV32 @Y2, MR1 ; and in parallel store A*B
MMOV32 @Y3, MR1 ; Store the result
MSTOP ; end of task

See also MMPYF32 MRd, MRe, MRf || MMOV32 MRa, mem32

MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf

32-Bit Floating-Point Multiply with Parallel Subtract

Operands MRa CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRa cannot be the same register as MRd
MRb CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRc CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRd CLA floating-point destination register for MSUBF32 (MR0 to MR3)
MRd cannot be the same register as MRa
MRe CLA floating-point source register for MSUBF32 (MR0 to MR3)
MRf CLA floating-point source register for MSUBF32 (MR0 to MR3)

Opcode
LSW: 0000 ffee ddcc bbaa
MSW: 0111 1010 0100 0000

Description Multiply the contents of two floating-point registers with parallel subtraction of two
registers.

MRa = MRb * MRc;

MRd = MRe - MRf;

Restrictions The destination register for the MMPYF32 and the MSUBF32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 or MSUBF32 generates an underflow condition.
• LVF = 1 if MMPYF32 or MSUBF32 generates an overflow condition.

Pipeline MMPYF32 and MSUBF32 both complete in a single cycle.

Example
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A - B)
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR2, MR0, MR1 ; Multiply (A*B)
|| MSUBF32 MR3, MR0, MR1 ; and in parallel Sub (A-B)
MMOV32 @Y2, MR2 ; Store A*B
MMOV32 @Y3, MR3 ; Store A-B
MSTOP ; end of task

See also MSUBF32 MRa, MRb, MRc

MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa

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MNEGF32 MRa, MRb{, CNDF}

Conditional Negation

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
CNDF Condition tested

Opcode
LSW: 0000 0000 cndf bbaa
MSW: 0111 1010 1000 0000

Description
if (CNDF == true) {MRa = - MRb; }
else {MRa = MRb; }

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF, and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

Pipeline This is a single-cycle instruction.

Example 1
; Show the basic operation of MNEGF32
;
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMPYF32 MR3, MR1, MR2 ; MR3 = -6.0
MMPYF32 MR0, MR0, MR1 ; MR0 = 20.0
MMOVIZ MR1, #0.0
MCMPF32 MR3, MR1 ; NF = 1
MNEGF32 MR3, MR3, LT ; if NF = 1, MR3 = 6.0

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MNEGF32 MRa, MRb{, CNDF} (continued)

Conditional Negation

MCMPF32 MR0, MR1 ; NF = 0

MNEGF32 MR0, MR0, GEQ ; if NF = 0, MR0 = -20.0

Example 2
; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den ; MR1 = Den
MEINVF32 MR2, MR1 ; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num ; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den ; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ ; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0 ; Store result
MSTOP ; end of task

See also MABSF32 MRa, MRb

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MNOP

No Operation

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1010 0000

Description Do nothing. This instruction is used to fill required pipeline delay slots when other
instructions are not available to fill the slots.
Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store the value in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP ; Too late to affect MBCNDD
MNOP ; Too late to affect MBCNDD
MNOP ; Too late to affect MBCNDD
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Pad to seperate MBCNDD and MSTOP
MNOP ; Pad to seperate MBCNDD and MSTOP
MSTOP ; End of task

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MOR32 MRa, MRb, MRc

Bitwise OR

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 1000 0000

Description Bitwise OR of MRb with MRc.

MARa(31:0) = MARb(31:0) OR MRc(31:0);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0,
#0x5555 ; MR0 = 0x5555AAAA
MMOVXI MR0,
#0xAAAA
MMOVIZ MR1,
#0x5432 ; MR1 = 0x5432FEDC
MMOVXI MR1,
#0xFEDC
; 0101 OR 0101 = 0101 (5)
; 0101 OR 0100 = 0101 (5)
; 0101 OR 0011 = 0111 (7)
; 0101 OR 0010 = 0111 (7)
; 1010 OR 1111 = 1111 (F)
; 1010 OR 1110 = 1110 (E)
; 1010 OR 1101 = 1111 (F)
; 1010 OR 1100 = 1110 (E)
MOR32 MR2, MR1, MR0 ; MR3 = 0x5555FEFE

See also MAND32 MRa, MRb, MRc

MXOR32 MRa, MRb, MRc

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MRCNDD {CNDF}

Return Conditional Delayed

Operands CNDF Optional condition

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1001 1010 cndf

Description If the specified condition is true, then the RPC field of MSTF is loaded into MPC and
fetching continues from that location. Otherwise, program fetches continue without the
return.
Refer to the Pipeline section for important information regarding this instruction.

if (CNDF == TRUE) MPC = RPC;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline The MRCNDD instruction by itself is a single-cycle instruction. As shown in Table 7-19, 6
instruction slots are executed for each return; 3 slots before the return instruction (d5-d7)
and 3 slots after the return instruction (d8-d10). The total number of cycles for a return
taken or not taken depends on the usage of these slots. That is, the number of cycles
depends on how many slots are filled with a MNOP as well as which slots are filled.
The effective number of cycles for a return can, therefore, range from 1 to 7 cycles. The
number of cycles for a return taken can not be the same as for a return not taken.

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MRCNDD {CNDF} (continued)

Return Conditional Delayed

Referring to the following code fragment and the pipeline diagrams in Table 7-19 and
Table 7-20, the instructions before and after MRCNDD have the following properties:

;
;
<Instruction 1> ; I1 Last instruction that can affect flags for
; the MCCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
MCCNDD _func, NEQ ; Call to func if not eqal to zero
; Three instructions after MCCNDD are always
; executed whether the call is taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8 The address of this instruction is saved
; in the RPC field of the MSTF register.
; Upon return this value is loaded into MPC
; and fetching continues from this point.
<Instruction 9> ; I9
<Instruction 10> ; I10
....
....
_func:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
<Destination 4> ; d4 Last instruction that can affect flags for
; the MRCNDD operation
<Destination 5> ; d5 Cannot be stop, branch, call or return
<Destination 6> ; d6 Cannot be stop, branch, call or return
<Destination 7> ; d7 Cannot be stop, branch, call or return
MRCNDD NEQ ; Return to <Instruction 8> if not equal to zero
; Three instructions after MRCNDD are always
; executed whether the return is taken or not
<Destination 8> ; d8 Cannot be stop, branch, call or return
<Destination 9> ; d9 Cannot be stop, branch, call or return
<Destination 10> ; d10 Cannot be stop, branch, call or return
<Destination 11> ; d11
<Destination 12> ; d12
....
....
MSTOP
....

• d4
– d4 is the last instruction that can effect the CNDF flags for the MRCNDD instruction.
The CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is
made whether to return or not when MRCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for d4.
• d5, d6, and d7
– The three instructions proceeding MRCNDD can change MSTF flags but have no
effect on whether the MRCNDD instruction makes the return or not. This is because
the flag modification occurs after the D2 phase of the MRCNDD instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.
• d8, d9, and d10
– The three instructions following MRCNDD are always executed irrespective of
whether the return is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.

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MRCNDD {CNDF} (continued)

Return Conditional Delayed

Table 7-19. Pipeline Activity for MRCNDD, Return Not Taken

Instruction F1 F2 D1 D2 R1 R2 E W
d4 d4 d3 d2 d1 I7 I6 I5
d5 d5 d4 d3 d2 d1 I7 I6
d6 d6 d5 d4 d3 d2 d1 i7
d7 d7 d6 d5 d4 d3 d2 d1
MRCNDD MRCNDD d7 d6 d5 d4 d3 d2
d8 d8 MRCNDD d7 d6 d5 d4 d3
d9 d9 d8 MRCNDD d7 d6 d5 d4
d10 d10 d9 d8 MRCNDD d7 d6 d5
d11 d11 d10 d9 d8 - d7 d6
d12 d12 d11 d10 d9 d8 - d7
etc.... .... d12 d11 d10 d9 d8 -
.... .... .... d12 d11 d10 d9 d8
.... .... .... .... d12 d11 d10 d9
d12 d11 d10
d12 d11
d12

Table 7-20. Pipeline Activity for MRCNDD, Return Taken

Instruction F1 F2 D1 D2 R1 R2 E W
d4 d4 d3 d2 d1 I7 I6 I5
d5 d5 d4 d3 d2 d1 I7 I6
d6 d6 d5 d4 d3 d2 d1 i7
d7 d7 d6 d5 d4 d3 d2 d1
MRCNDD MRCNDD d7 d6 d5 d4 d3 d2
d8 d8 MRCNDD d7 d6 d5 d4 d3
d9 d9 d8 MRCNDD d7 d6 d5 d4
d10 d10 d9 d8 MRCNDD d7 d6 d5
I8 I8 d10 d9 d8 - d7 d6
I9 I9 I8 d10 d9 d8 - d7
I10 I10 I9 I8 d10 d9 d8 -
etc.... .... I10 I9 I8 d10 d9 d8
.... .... I10 I9 I8 d10 d9
.... .... I10 I9 I8 d10
I10 I9 I8
I10 I9
I10

See also MBCNDD #16BitDest, CNDF

MCCNDD 16BitDest, CNDF
MMOV32 mem32, MSTF
MMOV32 MSTF, mem32

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MSETFLG FLAG, VALUE

Set or Clear Selected Floating-Point Status Flags

Operands FLAG 8-bit mask indicating which floating-point status flags to change.
VALUE 8-bit mask indicating the flag value: 0 or 1.

Opcode
LSW: FFFF FFFF VVVV VVVV
MSW: 0111 1001 1100 0000

Description The MSETFLG instruction is used to set or clear selected floating-point status flags in the
MSTF register. The FLAG field is an 11-bit value that indicates which flags are changed.
That is, if a FLAG bit is set to 1, that flag is changed; all other flags are not modified. The
bit mapping of the FLAG field is:
9 8 7 6 5 4 3 2 1 0
RNDF Reserved TF Reserved ZF NF LUF LVF
32

The VALUE field indicates the value the flag can be set to: 0 or 1.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified Yes Yes Yes Yes Yes

Any flag can be modified by this instruction. The MEALLOW and RPC fields cannot be
modified with this instruction.

Pipeline This is a single-cycle instruction.

Example To make it easier and legible, the assembler accepts a FLAG=VALUE syntax for the
MSTFLG operation as:

MSETFLG RNDF32=0, TF=0, NF=1; FLAG = 11000100; VALUE = 00XXX1XX;

See also MMOV32 mem32, MSTF

MMOV32 MSTF, mem32

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MSTOP

Stop Task

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1000 0000

Description The MSTOP instruction must be placed to indicate the end of each task. In addition,
placing MSTOP in unused memory locations within the CLA program RAM can be useful
for debugging and preventing run away CLA code. When MSTOP enters the D2 phase of
the pipeline, the MIRUN flag for the task is cleared and the associated interrupt is flagged
in the PIE vector table.
There are three special cases that can occur when single-stepping a task such that the
MPC reaches the MSTOP instruction.
1. If you are single-stepping or halted in "task A" and "task B" comes in before the MPC
reaches the MSTOP, then "task B" starts if you continue to step through the MSTOP
instruction. Basically, if "task B" is pending before the MPC reaches MSTOP in "task
A" then there is no issue in "task B" starting and no special action is required.
2. In this case, you have single-stepped or halted in "task A" and the MPC has reached
the MSTOP with no tasks pending. If "task B" comes in at this point, "task B" is
flagged in the MIFR register but "task B" can or can not start if you continue to
single-step through the MSTOP instruction of "task A". It depends on exactly when the
new task comes in. To reliably start "task B", perform a soft reset and reconfigure the
MIER bits. Once this is done, you can start single-stepping "task B".
3. Case 2 can be handled slightly differently if there is control over when "task B" comes
in (for example using the IACK instruction to start the task). In this case you have
single-stepped or halted in "task A" and the MPC has reached the MSTOP with no
tasks pending. Before forcing "task B", run free to force the CLA out of the debug
state. Once this is done you can force "task B" and continue debugging.

Restrictions The MSTOP instruction cannot be placed 3 instructions before or after a MBCNDD,
MCCNDD, or MRCNDD instruction.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction. Table 7-21 shows the pipeline behavior of the MSTOP
instruction. The MSTOP instruction cannot be placed with 3 instructions of a MBCNDD,
MCCNDD, or MRCNDD instruction.
Table 7-21. Pipeline Activity for MSTOP
Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
MSTOP MSTOP I3 I2 I1
I4 I4 MSTOP I3 I2 I1
I5 I5 I4 MSTOP I3 I2 I1
I6 I6 I5 I4 MSTOP I3 I2 I1

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MSTOP (continued)

Stop Task

Table 7-21. Pipeline Activity for MSTOP (continued)

Instruction F1 F2 D1 D2 R1 R2 E W
New Task Arbitrated and
- - - - - I3 I2
Prioritized
New Task Arbitrated and
- - - - - - I3
Prioritized
I1 I1 - - - - - -
I2 I2 I1 - - - - -
I3 I3 I2 I1 - - - -
I4 I4 I3 I2 I1 - - -
I5 I5 I4 I3 I2 I1 - -
I6 I6 I5 I4 I3 I2 I1 -
I7 I7 I6 I5 I4 I3 I2 I1
....

Example
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
; Calculate Y2 = A - B - C
_Cla1Task3:
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MSUB32 MR3, MR0, MR1 ; A + B
MSUB32 MR3, MR3, MR2 ; A + B + C = 6 (0x0000006)
MMOV32 @_y2, MR3 ; Store y2
MSTOP ; End of task

See also MDEBUGSTOP

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MSUB32 MRa, MRb, MRc

32-Bit Integer Subtraction

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point destination register (MR0 to MR3)
MRc CLA floating-point destination register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 1110 0000

Description 32-bit integer addition of MRb and MRc.

MARa(31:0) = MARb(31:0) - MRc(31:0);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
;
Calculate Y2 = A - B - C
;
_Cla1Task3:
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MSUB32 MR3, MR0, MR1 ; A + B
MSUB32 MR3, MR3, MR2 ; A + B + C = 6 (0x0000006)
MMOV32 @_y2, MR3 ; Store y2
MSTOP ; End of task

See also MADD32 MRa, MRb, MRc

MAND32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc

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MSUBF32 MRa, MRb, MRc

32-Bit Floating-Point Subtraction

Operands MRa CLA floating-point destination register (MR0 to R1)

MRb CLA floating-point source register (MR0 to R1)
MRc CLA floating-point source register (MR0 to R1)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 0100 0000

Description Subtract the contents of two floating-point registers

MRa = MRb - MRc;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.
Pipeline This is a single-cycle instruction.

Example
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = A + B - C
;
_Cla1Task5:
MMOV32 MR0, @_A ; Load MR0 with A
MMOV32 MR1, @_B ; Load MR1 with B
MADDF32 MR0, MR1, MR0 ; Add A + B
|| MMOV32 MR1, @_C ; and in parallel load C
MSUBF32 MR0, MR0, MR1 ; Subtract C from (A + B)
MMOV32 @Y, MR0 ; (A+B) - C
MSTOP ; end of task

See also MSUBF32 MRa, #16FHi, MRb

MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSUBF32 MRa, #16FHi, MRb

32-Bit Floating-Point Subtraction

Operands MRa CLA floating-point destination register (MR0 to R1)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The lower 16-bits of the mantissa
are assumed to be all 0.
MRb CLA floating-point source register (MR0 to R1)

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1000 0000 baaa

Description Subtract MRb from the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The lower 16-bits of the mantissa are assumed to be all 0. #16FHi
is most useful for representing constants where the lowest 16-bits of the mantissa are
0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = #16FHi:0 - MRb;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.
Pipeline This is a single-cycle instruction.

Example
; Y = sqrt(X)
; Ye = Estimate(1/sqrt(X));
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Y = X*Ye
;
_Cla1Task3:
MMOV32 MR0, @_x ; MR0 = X
MEISQRTF32 MR1, MR0 ; MR1 = Ye = Estimate(1/sqrt(X))
MMOV32 MR1, @_x, EQ ; if(X == 0.0) Ye = 0.0
MMPYF32 MR3, MR0, #0.5 ; MR3 = X*0.5
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR0, MR1, MR0 ; MR0 = Y = Ye*X
MMOV32 @_y, MR0 ; Store Y = sqrt(X)
MSTOP ; end of task

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MSUBF32 MRa, #16FHi, MRb (continued)

32-Bit Floating-Point Subtraction

See also MSUBF32 MRa, MRb, MRc

MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32

32-Bit Floating-Point Subtraction with Parallel Move

Operands MRd CLA floating-point destination register (MR0 to MR3) for the
MSUBF32 operation
MRd cannot be the same register as MRa
MRe CLA floating-point source register (MR0 to MR3) for the MSUBF32
operation
MRf CLA floating-point source register (MR0 to MR3) for the MSUBF32
operation
MRa CLA floating-point destination register (MR0 to MR3) for the
MMOV32 operation
MRa cannot be the same register as MRd
mem32 32-bit memory location accessed using one of the available
addressing modes. Source for the MMOV32 operation.

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0010 ffee ddaa addr

Description Subtract the contents of two floating-point registers and move from memory to a floating-
point register.

MRd = MRe - MRf;

MRa = [mem32];

Restrictions The destination register for the MSUBF32 and the MMOV32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.
The MMOV32 instruction sets the NF and ZF flags.
Pipeline Both MSUBF32 and MMOV32 complete in a single cycle.

Example
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

See also MSUBF32 MRa, MRb, MRc

MSUBF32 MRa, #16FHi, MRb
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa

32-Bit Floating-Point Subtraction with Parallel Move

Operands MRd CLA floating-point destination register (MR0 to MR3) for the
MSUBF32 operation
MRe CLA floating-point source register (MR0 to MR3) for the MSUBF32
operation
MRf CLA floating-point source register (MR0 to MR3) for the MSUBF32
operation
mem32 32-bit destination memory location for the MMOV32 operation
MRa CLA floating-point source register (MR0 to MR3) for the MMOV32
operation

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0110 ffee ddaa addr

Description Subtract the contents of two floating-point registers and move from a floating-point
register to memory.

MRd = MRe - MRf;

[mem32] = MRa;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.
Pipeline Both MSUBF32 and MMOV32 complete in a single cycle.

See also MSUBF32 MRa, MRb, MRc

MSUBF32 MRa, #16FHi, MRb
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSWAPF MRa, MRb {, CNDF}

Conditional Swap

Operands MRa CLA floating-point register (MR0 to MR3)

MRb CLA floating-point register (MR0 to MR3)
CNDF Optional condition tested based on the MSTF flags

Opcode
LSW: 0000 0000 CNDF bbaa
MSW: 0111 1011 0000 0000

Description Conditional swap of MRa and MRb.

if (CNDF == true) swap MRa and MRb;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

No flags affected

Pipeline This is a single-cycle instruction.

Example
; X is an array of 32-bit floating-point values
; and has length elements. Find the maximum value in
; the array and store the value in Result
;
; Note: MCMPF32 and MSWAPF can be replaced by MMAXF32
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address

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MSWAPF MRa, MRb {, CNDF} (continued)

Conditional Swap

MUI16TOF32 MR0, @_len ; Length of the array

MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MCMPF32 MR2, MR1 ; Compare MR2 with MR1
MSWAPF MR1, MR2, GT ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

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MTESTTF CNDF

Test MSTF Register Flag Condition

Operands CNDF Condition to test based on MSTF flags

Opcode
LSW: 0000 0000 0000 cndf
MSW: 0111 1111 0100 0000

Description Test the CLA floating-point condition and if true, set the MSTF[TF] flag. If the condition is
false, clear the MSTF[TF] flag. This is useful for temporarily storing a condition for later
use.

if (CNDF == true) TF = 1;
else TF = 0;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified Yes No No No No

TF = 0;
if (CNDF == true) TF = 1;

Note: If (CNDF == UNC or UNCF), the TF flag is set to 1.

Pipeline This is a single-cycle instruction.

Example
; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)

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MTESTTF CNDF (continued)

Test MSTF Register Flag Condition

; CoastState = CoastState || COASTMASK

; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task2:
MMOV32 MR0, @_State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MCMPF32 MR0, #0.01 ; Check used by 2nd MBCNDD (B)
MTESTTF EQ ; Store EQ flag in TF for 2nd MBCNDD (B)
MNOP
MBCNDD _Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MMOV32 MR1, @_RampState ; Always executed
MMOVXI MR2, #RAMPMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @_RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken
_Skip1:
MMOV32 MR3, @_SteadyState
MMOVXI MR2, #STEADYMASK
MOR32 MR3, MR2
MBCNDD _Skip2, NTF ; (B) if State != .01, go to Skip2
MMOV32 MR1, @_CoastState ; Always executed
MMOVXI MR2, #COASTMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @_CoastState, MR1 ; Execute if (B) branch not taken
MSTOP ; end of task if (B) branch not taken
_Skip2:
MMOV32 @_SteadyState, MR3 ; Executed if (B) branch taken
MSTOP

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MUI16TOF32 MRa, mem16

Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem16 16-bit source memory location

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 01aa addr

Description When converting F32 to I16/UI16 data format, the MF32TOI16/UI16 operation truncates to
zero while the MF32TOI16R/UI16R operation rounds to the nearest (even) value.

MRa = UI16TOF32[mem16];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

See also MF32TOI16 MRa, MRb

MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MUI16TOF32 MRa, MRb

Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1110 0000

Description Convert an unsigned 16-bit integer to a 32-bit floating-point value. When converting
float32 to I16/UI16 data format, the MF32TOI16/UI16 operation truncates to zero while
the MF32TOI16R/UI16R operation rounds to the nearest (even) value.

MRa = UI16TOF32[MRb];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVXI MR1, #0x800F ; MR1(15:0) = 32783 (0x800F)
MUI16TOF32 MR0, MR1 ; MR0 = UI16TOF32 (MR1(15:0))
; = 32783.0 (0x47000F00)

See also MF32TOI16 MRa, MRb

MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16

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MUI32TOF32 MRa, mem32

Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem32 32-bit memory location accessed using one of the available
addressing modes

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 10aa addr

Description
MRa = UI32TOF32[mem32];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
; Given x2, m2, and b2 are Uint32 numbers:
;
; x2 = Uint32(2) = 0x00000002
; m2 = Uint32(1) = 0x00000001
; b2 = Uint32(3) = 0x00000003
;
; Calculate y2 = x2 * m2 + b2
;
_Cla1Task1:
MUI32TOF32 MR0, @_m2 ; MR0 = 1.0 (0x3F800000)
MUI32TOF32 MR1, @_x2 ; MR1 = 2.0 (0x40000000)
MUI32TOF32 MR2, @_b2 ; MR2 = 3.0 (0x40400000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR3, MR2, MR3 ; Y=MX+B = 5.0 (0x40A00000)
MF32TOUI32 MR3, MR3 ; Y = Uint32(5.0) = 0x00000005
MMOV32 @_y2, MR3 ; store result
MSTOP ; end of task

See also MF32TOI32 MRa, MRb

MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, MRb

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MUI32TOF32 MRa, MRb

Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1100 0000

Description
MRa = UI32TOF32 [MRb];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR3, #0x8000 ; MR3(31:16) = 0x8000
MMOVXI MR3, #0x1111 ; MR3(15:0) = 0x1111
; MR3 = 2147488017
MUI32TOF32 MR3, MR3 ; MR3 = MUI32TOF32 (MR3) = 2147488017.0 (0x4F000011)

See also MF32TOI32 MRa, MRb

MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MXOR32 MRa, MRb, MRc

Bitwise Exclusive Or

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 1010 0000

Description Bitwise XOR of MRb with MRc.

MARa(31:0) = MARb(31:0) XOR MRc(31:0);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x5555 ; MR0 = 0x5555AAAA
MMOVXI MR0, #0xAAAA
MMOVIZ MR1, #0x5432 ; MR1 = 0x5432FEDC
MMOVXI MR1, #0xFEDC
; 0101 XOR 0101 = 0000 (0)
; 0101 XOR 0100 = 0001 (1)
; 0101 XOR 0011 = 0110 (6)
; 0101 XOR 0010 = 0111 (7)
; 1010 XOR 1111 = 0101 (5)
; 1010 XOR 1110 = 0100 (4)
; 1010 XOR 1101 = 0111 (7)
; 1010 XOR 1100 = 0110 (6)
MXOR32 MR2, MR1, MR0 ; MR3 = 0x01675476

See also MAND32 MRa, MRb, MRc

MOR32 MRa, MRb, MRc

7.8 CLA Registers

This section describes the Control Law Accelerator registers.
7.8.1 CLA Base Address Table
Table 7-22. CLA Base Address Table
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 DMA HIC CLA
Instance Structure Protected

CLA1_ONLY_BAS
Cla1OnlyRegs CLA_ONLY_REGS 0x0000_0C00 - - - YES -
E

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Table 7-22. CLA Base Address Table (continued)

Bit Field Name Pipeline
DriverLib Name Base Address CPU1 DMA HIC CLA
Instance Structure Protected

CLA_SOFTINT_R CLA1_SOFTINT_B
Cla1SoftIntRegs 0x0000_0CE0 - - - YES -
EGS ASE
Cla1Regs CLA_REGS CLA1_BASE 0x0000_1400 YES - - - -

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7.8.2 CLA_ONLY_REGS Registers

Table 7-23 lists the memory-mapped registers for the CLA_ONLY_REGS registers. All register offset addresses
not listed in Table 7-23 should be considered as reserved locations and the register contents should not be
modified.
Table 7-23. CLA_ONLY_REGS Registers
Offset Acronym Register Name Write Protection Section
80h _MVECTBGRNDACTIVE Active register for MVECTBGRND. EALLOW Go
C0h _MPSACTL CLA PSA Control Register EALLOW Go
C2h _MPSA1 CLA PSA1 Register EALLOW Go
C4h _MPSA2 CLA PSA2 Register EALLOW Go
E0h SOFTINTEN CLA Software Interrupt Enable Register Go
E2h SOFTINTFRC CLA Software Interrupt Force Register Go

Complex bit access types are encoded to fit into small table cells. Table 7-24 shows the codes that are used for
access types in this section.
Table 7-24. CLA_ONLY_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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7.8.2.1 _MVECTBGRNDACTIVE Register (Offset = 80h) [Reset = 0h]

_MVECTBGRNDACTIVE is shown in Figure 7-2 and described in Table 7-25.
Return to the Summary Table.
Gives the current interrupted MPC value of the background task, if the background task was running and
interrupted, or reflects the MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.
Figure 7-2. _MVECTBGRNDACTIVE Register
15 14 13 12 11 10 9 8
i16
R-0h

7 6 5 4 3 2 1 0
i16
R-0h

Table 7-25. _MVECTBGRNDACTIVE Register Field Descriptions

Bit Field Type Reset Description
15-0 i16 R 0h Gives the current interrupted MPC value of the background task,
if the background task was running and interrupted, or reflects the
MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.
Reset type: SYSRSn

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7.8.2.2 _MPSACTL Register (Offset = C0h) [Reset = 0h]

_MPSACTL is shown in Figure 7-3 and described in Table 7-26.
Return to the Summary Table.
PSA Control Register
Figure 7-3. _MPSACTL Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
MPSA2CFG MPSA2CLEAR MPSA1CLEAR MDWDBCYC MDWDBSTART MPABCYC MPABSTART
R/W-0h R-0/W1S-0h R-0/W1S-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-26. _MPSACTL Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7-6 MPSA2CFG R/W 0h CLA PSA2 Polynomial Configuration Bits: These bits configure the
type of polynomial used for PSA2. The polynomials chosen are
commonly used in the industry:
Mode Polynomial Type
0,0 PSA
0,1 CRC32
1,0 CRC16
1,1 CRC16-CCITT
Note: [1] Polynomial configuration should be performed when PSA2
is stopped.
Reset type: SYSRSn
5 MPSA2CLEAR R-0/W1S 0h CLA PSA2 Clear Bit:
Writing of "1" will clear contents of PSA2 register.
Writes of "0" are ignored.
Always reads back a "0"
Note: Clearing operation should be performed when PSA2 is
stopped.
Reset type: SYSRSn
4 MPSA1CLEAR R-0/W1S 0h CLA PSA1 Clear Bit:
Writing of "1" will clear contents of PSA1 register.
Writes of "0" are ignored.
Always reads back a "0"
Note: Clearing operation should be performed when PSA1 is
stopped.
Reset type: SYSRSn
3 MDWDBCYC R/W 0h CLA Data Write Data Bus PSA2 Cycle or Event Based Bit:
0 PSA2 calculated on every cycle
1 PSA2 calculated on every bus event
Reset type: SYSRSn
2 MDWDBSTART R/W 0h CLA Data Write Data Bus PSA2 Start/Stop Bit:
0 PSA2 stopped
1 PSA2 start
Reset type: SYSRSn
1 MPABCYC R/W 0h CLA Program Address Bus PSA1 Cycle/Event Based Bit:
0 PSA1 calculated on every cycle
1 PSA1 calculated on every bus event
Reset type: SYSRSn
0 MPABSTART R/W 0h CLA Program Address Bus PSA1 Start/Stop Bit:
0 PSA1 stopped
1 PSA1 start
Reset type: SYSRSn

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7.8.2.3 _MPSA1 Register (Offset = C2h) [Reset = 0h]

_MPSA1 is shown in Figure 7-4 and described in Table 7-27.
Return to the Summary Table.
PSA1 Register
Figure 7-4. _MPSA1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R/W-0h

Table 7-27. _MPSA1 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R/W 0h PSA1 Value: Reading this register gives the current PSA1 value. The
value can be read at any time.
Writes to this register are allowed to initialize the PSA1 to a known
value. Writes to this register should only be made when PSA1 is
stopped.
Register value is cleared to zero by reset or by writing to the
MPSA1CLEAR bit in the MPSACTL register.
Reset type: SYSRSn

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7.8.2.4 _MPSA2 Register (Offset = C4h) [Reset = 0h]

_MPSA2 is shown in Figure 7-5 and described in Table 7-28.
Return to the Summary Table.
PSA2 Register
Figure 7-5. _MPSA2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R/W-0h

Table 7-28. _MPSA2 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R/W 0h PSA2 Value: Reading this register gives the current PSA2 value. The
value can be read at any time.
Writes to this register are allowed to initialize the PSA2 to a known
value. Writes to this register should only be made when PSA2 is
stopped.
Register value is cleared to zero by reset or by writing to the
MPSA2CLEAR bit in the MPSACTL register.
Reset type: SYSRSn

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7.8.2.5 SOFTINTEN Register (Offset = E0h) [Reset = 0h]

SOFTINTEN is shown in Figure 7-6 and described in Table 7-29.
Return to the Summary Table.
Enables the ability to generate CLA task interrupt from within the task, by writing to SOFTINTFRC register.
SOFTINTFRC register can only be written from CLA.
Figure 7-6. SOFTINTEN Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-29. SOFTINTEN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
6 TASK7 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
5 TASK6 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
4 TASK5 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
3 TASK4 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
2 TASK3 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
1 TASK2 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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Table 7-29. SOFTINTEN Register Field Descriptions (continued)

Bit Field Type Reset Description
0 TASK1 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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7.8.2.6 SOFTINTFRC Register (Offset = E2h) [Reset = 0h]

SOFTINTFRC is shown in Figure 7-7 and described in Table 7-30.
Return to the Summary Table.
Writing a value of 1 in a bit will generate the corresponding task interrupt.
Figure 7-7. SOFTINTFRC Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-30. SOFTINTFRC Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
6 TASK7 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
5 TASK6 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
4 TASK5 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
3 TASK4 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
2 TASK3 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
1 TASK2 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
0 TASK1 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn

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7.8.3 CLA_SOFTINT_REGS Registers

Table 7-31 lists the memory-mapped registers for the CLA_SOFTINT_REGS registers. All register offset
addresses not listed in Table 7-31 should be considered as reserved locations and the register contents should
not be modified.
Table 7-31. CLA_SOFTINT_REGS Registers
Offset Acronym Register Name Write Protection Section
0h SOFTINTEN CLA Software Interrupt Enable Register Go
2h SOFTINTFRC CLA Software Interrupt Force Register Go

Complex bit access types are encoded to fit into small table cells. Table 7-32 shows the codes that are used for
access types in this section.
Table 7-32. CLA_SOFTINT_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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7.8.3.1 SOFTINTEN Register (Offset = 0h) [Reset = 0h]

SOFTINTEN is shown in Figure 7-8 and described in Table 7-33.
Return to the Summary Table.
Enables the ability to generate CLA task interrupt from within the task, by writing to SOFTINTFRC register.
SOFTINTFRC register can only be written from CLA.
Figure 7-8. SOFTINTEN Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-33. SOFTINTEN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
6 TASK7 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
5 TASK6 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
4 TASK5 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
3 TASK4 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
2 TASK3 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
1 TASK2 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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Table 7-33. SOFTINTEN Register Field Descriptions (continued)

Bit Field Type Reset Description
0 TASK1 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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7.8.3.2 SOFTINTFRC Register (Offset = 2h) [Reset = 0h]

SOFTINTFRC is shown in Figure 7-9 and described in Table 7-34.
Return to the Summary Table.
Writing a value of 1 in a bit will generate the corresponding task interrupt.This register is only accessible by the
CLA (not the CPU).
Figure 7-9. SOFTINTFRC Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-34. SOFTINTFRC Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
6 TASK7 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
5 TASK6 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
4 TASK5 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
3 TASK4 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
2 TASK3 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
1 TASK2 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
0 TASK1 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn

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7.8.4 CLA_REGS Registers

Table 7-35 lists the memory-mapped registers for the CLA_REGS registers. All register offset addresses not
listed in Table 7-35 should be considered as reserved locations and the register contents should not be modified.
Table 7-35. CLA_REGS Registers
Offset Acronym Register Name Write Protection Section
0h MVECT1 Task Interrupt Vector EALLOW Go
1h MVECT2 Task Interrupt Vector EALLOW Go
2h MVECT3 Task Interrupt Vector EALLOW Go
3h MVECT4 Task Interrupt Vector EALLOW Go
4h MVECT5 Task Interrupt Vector EALLOW Go
5h MVECT6 Task Interrupt Vector EALLOW Go
6h MVECT7 Task Interrupt Vector EALLOW Go
7h MVECT8 Task Interrupt Vector EALLOW Go
10h MCTL Control Register EALLOW Go
1Bh _MVECTBGRNDACTIVE Active register for MVECTBGRND. EALLOW Go
1Ch SOFTINTEN CLA Software Interrupt Enable Register Go
1Dh _MSTSBGRND Status register for the back ground task. EALLOW Go
1Eh _MCTLBGRND Control register for the back ground task. EALLOW Go
1Fh _MVECTBGRND Vector for the back ground task. EALLOW Go
20h MIFR Interrupt Flag Register EALLOW Go
21h MIOVF Interrupt Overflow Flag Register EALLOW Go
22h MIFRC Interrupt Force Register EALLOW Go
23h MICLR Interrupt Flag Clear Register EALLOW Go
24h MICLROVF Interrupt Overflow Flag Clear Register EALLOW Go
25h MIER Interrupt Enable Register EALLOW Go
26h MIRUN Interrupt Run Status Register EALLOW Go
28h _MPC CLA Program Counter Go
2Ah _MAR0 CLA Auxiliary Register 0 Go
2Bh _MAR1 CLA Auxiliary Register 1 Go
2Eh _MSTF CLA Floating-Point Status Register Go
30h _MR0 CLA Floating-Point Result Register 0 Go
34h _MR1 CLA Floating-Point Result Register 1 Go
38h _MR2 CLA Floating-Point Result Register 2 Go
3Ch _MR3 CLA Floating-Point Result Register 3 Go
42h _MPSACTL CLA PSA Control Register EALLOW Go
44h _MPSA1 CLA PSA1 Register EALLOW Go
46h _MPSA2 CLA PSA2 Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 7-36 shows the codes that are used for
access types in this section.
Table 7-36. CLA_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type

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Table 7-36. CLA_REGS Access Type Codes

(continued)
Access Type Code Description
W W Write
W1C W Write
1C 1 to clear
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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7.8.4.1 MVECT1 Register (Offset = 0h) [Reset = 0h]

MVECT1 is shown in Figure 7-10 and described in Table 7-37.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 7-10. MVECT1 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 7-37. MVECT1 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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7.8.4.2 MVECT2 Register (Offset = 1h) [Reset = 0h]

MVECT2 is shown in Figure 7-11 and described in Table 7-38.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 7-11. MVECT2 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 7-38. MVECT2 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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7.8.4.3 MVECT3 Register (Offset = 2h) [Reset = 0h]

MVECT3 is shown in Figure 7-12 and described in Table 7-39.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 7-12. MVECT3 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 7-39. MVECT3 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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7.8.4.4 MVECT4 Register (Offset = 3h) [Reset = 0h]

MVECT4 is shown in Figure 7-13 and described in Table 7-40.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 7-13. MVECT4 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 7-40. MVECT4 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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7.8.4.5 MVECT5 Register (Offset = 4h) [Reset = 0h]

MVECT5 is shown in Figure 7-14 and described in Table 7-41.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 7-14. MVECT5 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 7-41. MVECT5 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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7.8.4.6 MVECT6 Register (Offset = 5h) [Reset = 0h]

MVECT6 is shown in Figure 7-15 and described in Table 7-42.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 7-15. MVECT6 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 7-42. MVECT6 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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7.8.4.7 MVECT7 Register (Offset = 6h) [Reset = 0h]

MVECT7 is shown in Figure 7-16 and described in Table 7-43.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 7-16. MVECT7 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 7-43. MVECT7 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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7.8.4.8 MVECT8 Register (Offset = 7h) [Reset = 0h]

MVECT8 is shown in Figure 7-17 and described in Table 7-44.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 7-17. MVECT8 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 7-44. MVECT8 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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7.8.4.9 MCTL Register (Offset = 10h) [Reset = 0h]

MCTL is shown in Figure 7-18 and described in Table 7-45.
Return to the Summary Table.
Control Register
Figure 7-18. MCTL Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED IACKE SOFTRESET HARDRESET
R-0h R/W-0h R-0/W1S-0h R-0/W1S-0h

Table 7-45. MCTL Register Field Descriptions

Bit Field Type Reset Description
15-3 RESERVED R 0h Reserved
2 IACKE R/W 0h IACK Operation Enable Bit: Writing a "1" to this bit will enable the
IACK operation for setting the MIFR bits in the same manner as the
MIFRC register (write of "1" will set respective MIFR bit). At reset,
this feature is disabled.
This feature enables the C28 CPU to efficiently trigger a task.
Note: IACK operation should ignore EALLOW status of C28 core
when accessing the MIFRC register.
Reset type: SYSRSn
0h (R/W) = The CLA ignores the IACK instruction. (default)
1h (R/W) = Enable the main CPU to use the IACK #16bit instruction
to set MIFR bits in the same manner as writing to the MIFRC
register. Each bit in the operand, #16bit, corresponds to a bit in the
MIFRC register. Using IACK has the advantage of not having to first
set the EALLOW bit. This allows the main CPU to efficiently trigger a
CLA task through software.
Examples IACK #0x0001 Write a 1 to MIFRC bit 0 to force task 1
IACK #0x0003 Write a 1 to MIFRC bit 0 and 1 to force task 1 and
task 2
1 SOFTRESET R-0/W1S 0h Soft Reset Bit: Writing a "1" to this bit will stop a current task, clear
the RUN flag and also clear all bits in the MIER register. Writes of "0"
are ignored and reads always return a "0".
Note: After issuing SOFTRESET command, user should wait at least
1 clock cycle before attempting to write to MIER register.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 are ignored.
1h (R/W) = Writing a 1 will cause a soft reset of the CLA. This
will stop the current task, clear the MIRUN flag and clear all bits
in the MIER register. After a soft reset you must wait at least 1
SYSCLKOUT cycle before reconfiguring the MIER bits. If these two
operations are done back-to-back then the MIER bits will not get set.
0 HARDRESET R-0/W1S 0h Hard Reset Bit: Writing a "1" to this bit will cause a HARD reset on
the CLA. The behavior of a HARD reset is the same as a system
reset SYSRSn on the CLA. Writes of "0" are ignored and reads
always return a "0".
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 are ignored.
1h (R/W) = Writing a 1 will cause a hard reset of the CLA. This will
set all CLA registers to their default state.

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7.8.4.10 _MVECTBGRNDACTIVE Register (Offset = 1Bh) [Reset = 0h]

_MVECTBGRNDACTIVE is shown in Figure 7-19 and described in Table 7-46.
Return to the Summary Table.
Gives the current interrupted MPC value of the background task, if the background task was running and
interrupted, or reflects the MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.
Figure 7-19. _MVECTBGRNDACTIVE Register
15 14 13 12 11 10 9 8
i16
R-0h

7 6 5 4 3 2 1 0
i16
R-0h

Table 7-46. _MVECTBGRNDACTIVE Register Field Descriptions

Bit Field Type Reset Description
15-0 i16 R 0h Gives the current interrupted MPC value of the background task,
if the background task was running and interrupted, or reflects the
MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.
Reset type: SYSRSn

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7.8.4.11 SOFTINTEN Register (Offset = 1Ch) [Reset = 0h]

SOFTINTEN is shown in Figure 7-20 and described in Table 7-47.
Return to the Summary Table.
Enables the ability to generate CLA task interrupt from within the task, by writing to SOFTINTFRC register.
SOFTINTFRC register can only be written from CLA. Only reads are allowed from CPU. Writes are not allowed
from CPU.
Figure 7-20. SOFTINTEN Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-47. SOFTINTEN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
6 TASK7 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
5 TASK6 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
4 TASK5 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
3 TASK4 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
2 TASK3 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
1 TASK2 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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Table 7-47. SOFTINTEN Register Field Descriptions (continued)

Bit Field Type Reset Description
0 TASK1 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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7.8.4.12 _MSTSBGRND Register (Offset = 1Dh) [Reset = 0h]

_MSTSBGRND is shown in Figure 7-21 and described in Table 7-48.
Return to the Summary Table.
Status bits for the backgrondtask.
Figure 7-21. _MSTSBGRND Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
RESERVED BGOVF _BGINTM RUN
R/W-0h R/W1C-0h R-0h R-0h

Table 7-48. _MSTSBGRND Register Field Descriptions

Bit Field Type Reset Description
15-3 RESERVED R/W 0h Reserved
2 BGOVF R/W1C 0h Value of 1 indicates a hardware trigger (which is enabled) occurred
while the MCTLBGRND.BGSTART bit is set.
Writing a value of 1 to this bit clears the BGOVF bit.
Write of 0 has no effect,
Value of 0 indicates the background task trigger did not result in a
overflow.
Reset type: SYSRSn
1 _BGINTM R 0h Value of 1 indicates that backgroiund task will not be interrupted.
This bit is set when MSETC _BGINTM bit is executed.
Value of 0 indicates that background task can be interrupted.
Reset type: SYSRSn
0 RUN R 0h Value of 1 indicates that background task is running.
Value of 0 indicates that background task is not running.
Reset type: SYSRSn

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7.8.4.13 _MCTLBGRND Register (Offset = 1Eh) [Reset = 0h]

_MCTLBGRND is shown in Figure 7-22 and described in Table 7-49.
Return to the Summary Table.
Holds the configuration bits to start the background task, enable hardware trigger.
Figure 7-22. _MCTLBGRND Register
15 14 13 12 11 10 9 8
BGEN RESERVED
R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED TRIGEN BGSTART
R/W-0h R/W-0h R/W1S-0h

Table 7-49. _MCTLBGRND Register Field Descriptions

Bit Field Type Reset Description
15 BGEN R/W 0h 0 Background task is disabled, BGSTART will not be set either in a
hardware trigger or by writing 1 to BGSTART bit.
1 Background task is enabled and MIER[INT8] will be cleared,
preventing task 8 from triggering.
Reset type: SYSRSn
14-2 RESERVED R/W 0h Reserved
1 TRIGEN R/W 0h Hardware trigger enable for the background task.
1 Hardware trigger is enabled.
0 Hardware trigger is disabled.
Note: Trigger source for the background task will be the same as that
for task 8
Reset type: SYSRSn
0 BGSTART R/W1S 0h Value of 1 will start the background task, provided there are no other
pending tasks.
- Value of 0 has no effect if the background task has not started.
- This bit is also set by hardware, if MCTLBGRND.TRIGEN = 1 and a
hardware trigger occurs.
- This bit is cleared by hardware when a MSTOP instruction occurs in
the background task
- If the background task is running and this bit is cleared, it will not
have any effect on the task execution.
Reset type: SYSRSn

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7.8.4.14 _MVECTBGRND Register (Offset = 1Fh) [Reset = 0h]

_MVECTBGRND is shown in Figure 7-23 and described in Table 7-50.
Return to the Summary Table.
These bits specify the start address for the background task . The value in this register is forced into the MPC
register when the background task starts.
Figure 7-23. _MVECTBGRND Register
15 14 13 12 11 10 9 8
i16
R/W-0h

7 6 5 4 3 2 1 0
i16
R/W-0h

Table 7-50. _MVECTBGRND Register Field Descriptions

Bit Field Type Reset Description
15-0 i16 R/W 0h MPC Start Address: These bits specify the start address for the
background task . The value in this register is forced into the MPC
register, when the background task starts.
Reset type: SYSRSn

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7.8.4.15 MIFR Register (Offset = 20h) [Reset = 0h]

MIFR is shown in Figure 7-24 and described in Table 7-51.
Return to the Summary Table.
Each bit in the interrupt flag register corresponds to a CLA task. The corresponding bit is automatically set
when the task request is received from the peripheral interrupt. The bit can also be set by the main CPU
writing to the MIFRC register or using the IACK instruction to start the task. To use the IACK instruction to
begin a task first enable this feature in the MCTL register. If the bit is already set when a new peripheral
interrupt is received, then the corresponding overflow bit will be set in the MIOVF register.
The corresponding MIFR bit is automatically cleared when the task begins execution. This will occur if the
interrupt is enabled in the MIER register and no other higher priority task is pending. The bits can also be
cleared manually by writing to the MICLR register. Writes to the MIFR register are ignored.
Figure 7-24. MIFR Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-51. MIFR Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 8 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 8 interrupt has been received and is pending execution

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Table 7-51. MIFR Register Field Descriptions (continued)

Bit Field Type Reset Description
6 INT7 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 7 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 7 interrupt has been received and is pending execution
5 INT6 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 6 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 6 interrupt has been received and is pending execution
4 INT5 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 5 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 5 interrupt has been received and is pending execution

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Table 7-51. MIFR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 4 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 4 interrupt has been received and is pending execution
2 INT3 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 3 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 3 interrupt has been received and is pending execution
1 INT2 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 2 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 2 interrupt has been received and is pending execution

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Table 7-51. MIFR Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INT1 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 1 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 1 interrupt has been received and is pending execution

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7.8.4.16 MIOVF Register (Offset = 21h) [Reset = 0h]

MIOVF is shown in Figure 7-25 and described in Table 7-52.
Return to the Summary Table.
Each bit in the overflow flag register corresponds to a CLA task. The bit is set when an interrupt overflow
event has occurred for the specific task. An overflow event occurs when the MIFR register bit is already
set when a new interrupt is received from a peripheral source. The MIOVF bits are only affected by
peripheral interrupt events. They do not respond to a task request by the main CPU IACK instruction or by
directly setting MIFR bits. The overflow flag will remain latched and can only be cleared by writing to the
overflow flag clear (MICLROVF) register. Writes to the MIOVF register are ignored.
Figure 7-25. MIOVF Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-52. MIOVF Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 8 interrupt overflow has not occurred (default)
1h (R/W) = A task 8 interrupt overflow has occurred
6 INT7 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 7 interrupt overflow has not occurred (default)
1h (R/W) = A task 7 interrupt overflow has occurred

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Table 7-52. MIOVF Register Field Descriptions (continued)

Bit Field Type Reset Description
5 INT6 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 6 interrupt overflow has not occurred (default)
1h (R/W) = A task 6 interrupt overflow has occurred
4 INT5 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 5 interrupt overflow has not occurred (default)
1h (R/W) = A task 5 interrupt overflow has occurred
3 INT4 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 4 interrupt overflow has not occurred (default)
1h (R/W) = A task 4 interrupt overflow has occurred
2 INT3 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 3 interrupt overflow has not occurred (default)
1h (R/W) = A task 3 interrupt overflow has occurred

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Table 7-52. MIOVF Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INT2 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 2 interrupt overflow has not occurred (default)
1h (R/W) = A task 2 interrupt overflow has occurred
0 INT1 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 1 interrupt overflow has not occurred (default)
1h (R/W) = A task 1 interrupt overflow has occurred

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7.8.4.17 MIFRC Register (Offset = 22h) [Reset = 0h]

MIFRC is shown in Figure 7-26 and described in Table 7-53.
Return to the Summary Table.
The interrupt force register can be used by the main CPU to start tasks through software. Writing a 1 to a
MIFRC bit will set the corresponding bit in the MIFR register. Writes of 0 are ignored and reads always
return 0. The IACK #16bit operation can also be used to start tasks and has the same effect as the
MIFRC register. To enable IACK to set MIFR bits you must first set the MCTL[IACKE] bit. Using IACK has
the advantage of not having to first set the EALLOW bit. This allows the main CPU to efficiently trigger
CLA tasks through software.
Figure 7-26. MIFRC Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-53. MIFRC Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 8 interrupt
6 INT7 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 7 interrupt
5 INT6 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 6 interrupt
4 INT5 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 5 interrupt

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Table 7-53. MIFRC Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 4 interrupt
2 INT3 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 3 interrupt
1 INT2 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 2 interrupt
0 INT1 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 1 interrupt

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7.8.4.18 MICLR Register (Offset = 23h) [Reset = 0h]

MICLR is shown in Figure 7-27 and described in Table 7-54.
Return to the Summary Table.
Normally bits in the MIFR register are automatically cleared when a task begins. The interrupt flag clear
register can be used to instead manually clear bits in the interrupt flag (MIFR) register. Writing a 1 to a
MICLR bit will clear the corresponding bit in the MIFR register. Writes of 0 are ignored and reads always
return 0.
Figure 7-27. MICLR Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-54. MICLR Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 8 interrupt flag
6 INT7 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 7 interrupt flag
5 INT6 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 6 interrupt flag
4 INT5 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 5 interrupt flag

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Table 7-54. MICLR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 4 interrupt flag
2 INT3 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 3 interrupt flag
1 INT2 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 2 interrupt flag
0 INT1 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 1 interrupt flag

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7.8.4.19 MICLROVF Register (Offset = 24h) [Reset = 0h]

MICLROVF is shown in Figure 7-28 and described in Table 7-55.
Return to the Summary Table.
Overflow flag bits in the MIOVF register are latched until manually cleared using the MICLROVF register.
Writing a 1 to a MICLROVF bit will clear the corresponding bit in the MIOVF register. Writes of 0 are
ignored and reads always return 0.
Figure 7-28. MICLROVF Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-55. MICLROVF Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 8 interrupt overflow flag
6 INT7 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 7 interrupt overflow flag
5 INT6 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 6 interrupt overflow flag
4 INT5 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 5 interrupt overflow flag
3 INT4 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 4 interrupt overflow flag

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Table 7-55. MICLROVF Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INT3 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 3 interrupt overflow flag
1 INT2 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 2 interrupt overflow flag
0 INT1 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 1 interrupt overflow flag

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7.8.4.20 MIER Register (Offset = 25h) [Reset = 0h]

MIER is shown in Figure 7-29 and described in Table 7-56.
Return to the Summary Table.
Setting the bits in the interrupt enable register (MIER) allow an incoming interrupt or main CPU software to
start the corresponding CLA task. Writing a 0 will block the task, but the interrupt request will still be
latched in the flag register (MIFLG). Setting the MIER register bit to 0 while the corresponding task is
executing will have no effect on the task. The task will continue to run until it hits the MSTOP instruction.
When a soft reset is issued, the MIER bits are cleared. There should always be at least a 1 SYSCLKOUT
delay between issuing the soft reset and reconfiguring the MIER bits.
Figure 7-29. MIER Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-56. MIER Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 8 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 8 interrupt is enabled
6 INT7 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 7 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 7 interrupt is enabled

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Table 7-56. MIER Register Field Descriptions (continued)

Bit Field Type Reset Description
5 INT6 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 6 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 6 interrupt is enabled
4 INT5 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 5 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 5 interrupt is enabled
3 INT4 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 4 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 4 interrupt is enabled
2 INT3 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 3 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 3 interrupt is enabled

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Table 7-56. MIER Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INT2 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 2 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 2 interrupt is enabled
0 INT1 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 1 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 1 interrupt is enabled

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7.8.4.21 MIRUN Register (Offset = 26h) [Reset = 0h]

MIRUN is shown in Figure 7-30 and described in Table 7-57.
Return to the Summary Table.
The interrupt run status register (MIRUN) indicates which task is currently executing. Only one MIRUN bit
will ever be set to a 1 at any given time. The bit is automatically cleared when the task competes and the
respective interrupt is fed to the peripheral interrupt expansion (PIE) block of the device. This lets the main
CPU know when a task has completed. The main CPU can stop a currently running task by writing to the
MCTL[SOFTRESET] bit. This will clear the MIRUN flag and stop the task. In this case no interrupt will be
generated to the PIE.
Figure 7-30. MIRUN Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-57. MIRUN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R 0h These bits indicate which task is currently active. Only one bit can
be set to "1" at any one time. The bit is automatically cleared to
"0" when the task completes and the respective CLAINTxn line is
toggled to indicate task completion. The CLAINTxn interrupt line can
be fed to the PIE of the CPU so the CPU knows when a task has
completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 8 is not executing (default)
1h (R/W) = Task 8 is executing
6 INT7 R 0h These bits indicate which task is currently active. Only one bit can
be set to "1" at any one time. The bit is automatically cleared to
"0" when the task completes and the respective CLAINTxn line is
toggled to indicate task completion. The CLAINTxn interrupt line can
be fed to the PIE of the CPU so the CPU knows when a task has
completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 7 is not executing (default)
1h (R/W) = Task 7 is executing
5 INT6 R 0h These bits indicate which task is currently active. Only one bit can
be set to "1" at any one time. The bit is automatically cleared to
"0" when the task completes and the respective CLAINTxn line is
toggled to indicate task completion. The CLAINTxn interrupt line can
be fed to the PIE of the CPU so the CPU knows when a task has
completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 6 is not executing (default)
1h (R/W) = Task 6 is executing

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Table 7-57. MIRUN Register Field Descriptions (continued)

Bit Field Type Reset Description
4 INT5 R 0h These bits indicate which task is currently active. Only one bit can
be set to "1" at any one time. The bit is automatically cleared to
"0" when the task completes and the respective CLAINTxn line is
toggled to indicate task completion. The CLAINTxn interrupt line can
be fed to the PIE of the CPU so the CPU knows when a task has
completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 5 is not executing (default)
1h (R/W) = Task 5 is executing
3 INT4 R 0h These bits indicate which task is currently active. Only one bit can
be set to "1" at any one time. The bit is automatically cleared to
"0" when the task completes and the respective CLAINTxn line is
toggled to indicate task completion. The CLAINTxn interrupt line can
be fed to the PIE of the CPU so the CPU knows when a task has
completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 4 is not executing (default)
1h (R/W) = Task 4 is executing
2 INT3 R 0h These bits indicate which task is currently active. Only one bit can
be set to "1" at any one time. The bit is automatically cleared to
"0" when the task completes and the respective CLAINTxn line is
toggled to indicate task completion. The CLAINTxn interrupt line can
be fed to the PIE of the CPU so the CPU knows when a task has
completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 3 is not executing (default)
1h (R/W) = Task 3 is executing
1 INT2 R 0h These bits indicate which task is currently active. Only one bit can
be set to "1" at any one time. The bit is automatically cleared to
"0" when the task completes and the respective CLAINTxn line is
toggled to indicate task completion. The CLAINTxn interrupt line can
be fed to the PIE of the CPU so the CPU knows when a task has
completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 2 is not executing (default)
1h (R/W) = Task 2 is executing
0 INT1 R 0h These bits indicate which task is currently active. Only one bit can
be set to "1" at any one time. The bit is automatically cleared to
"0" when the task completes and the respective CLAINTxn line is
toggled to indicate task completion. The CLAINTxn interrupt line can
be fed to the PIE of the CPU so the CPU knows when a task has
completed.
A currently running task can be stopped by a SOFTRESET. The
RUN flag is cleared, the task is stopped, but no CLAINTxn interrupt
is generated.
Reset type: SYSRSn
0h (R/W) = Task 1 is not executing (default)
1h (R/W) = Task 1 is executing

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7.8.4.22 _MPC Register (Offset = 28h) [Reset = 0h]

_MPC is shown in Figure 7-31 and described in Table 7-58.
Return to the Summary Table.
CLA Program Counter
Figure 7-31. _MPC Register
15 14 13 12 11 10 9 8
_MPC
R-0h

7 6 5 4 3 2 1 0
_MPC
R-0h

Table 7-58. _MPC Register Field Descriptions

Bit Field Type Reset Description
15-0 _MPC R 0h Program Counter: The PC value is initialized by the appropriate
MVECTx register when an interrupt (task) is serviced.
The MPC register address 16-bits and not 32-bits. Hence the
address range of the CLA with a 16-bit MPC is 64Kx16 words or
32K CLA instructions.
Notes: [1] To be consistent with C28 core implementation, the PC
value points to the instruction in D2 stage of pipeline.
[2] After a STOP operation, and with no other task pending, the PC
will remain pointing to the STOP operation.
Reset type: SYSRSn

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7.8.4.23 _MAR0 Register (Offset = 2Ah) [Reset = 0h]

_MAR0 is shown in Figure 7-32 and described in Table 7-59.
Return to the Summary Table.
CLA Auxiliary Register 0
Figure 7-32. _MAR0 Register
15 14 13 12 11 10 9 8
_MAR0
R-0h

7 6 5 4 3 2 1 0
_MAR0
R-0h

Table 7-59. _MAR0 Register Field Descriptions

Bit Field Type Reset Description
15-0 _MAR0 R 0h CLA Auxillary Register 0
Reset type: SYSRSn

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7.8.4.24 _MAR1 Register (Offset = 2Bh) [Reset = 0h]

_MAR1 is shown in Figure 7-33 and described in Table 7-60.
Return to the Summary Table.
CLA Auxiliary Register 1
Figure 7-33. _MAR1 Register
15 14 13 12 11 10 9 8
_MAR1
R-0h

7 6 5 4 3 2 1 0
_MAR1
R-0h

Table 7-60. _MAR1 Register Field Descriptions

Bit Field Type Reset Description
15-0 _MAR1 R 0h CLA Auxillary Register 1
Reset type: SYSRSn

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7.8.4.25 _MSTF Register (Offset = 2Eh) [Reset = 0h]

_MSTF is shown in Figure 7-34 and described in Table 7-61.
Return to the Summary Table.
The CLA status register (MSTF) reflects the results of different operations. These are the basic rules for
the flags:
- Zero and negative flags are cleared or set based on:
- floating-point moves to registers
- the result of compare, minimum, maximum, negative and absolute value operations
- the integer result of operations such as MMOV16, MAND32, MOR32, MXOR32, MCMP32,
MASR32, MLSR32
- Overflow and underflow flags are set by floating-point math instructions such as multiply, add, subtract
and 1/x. These flags may also be connected to the peripheral interrupt expansion (PIE) block on your
device. This can be useful for debugging underflow and overflow conditions within an application.
Figure 7-34. _MSTF Register
31 30 29 28 27 26 25 24
RESERVED _RPC
R-0h R-0h

23 22 21 20 19 18 17 16
_RPC
R-0h

15 14 13 12 11 10 9 8
_RPC MEALLOW RESERVED RNDF32 RESERVED
R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED TF RESERVED ZF NF LUF LVF
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-61. _MSTF Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-12 _RPC R 0h Return program counter
The _RPC is used to save and restore the MPC address by the
MCCNDD and MRCNDD operations
Reset type: SYSRSn
11 MEALLOW R 0h MEALLOW Status
This bit enables and disables CLA write access to EALLOW
protected registers This is independent of the state of the EALLOW
bit in the main CPU status register This status bit can be saved and
restored by the MMOV32 STF, mem32 instruction
Reset type: SYSRSn
0h (R/W) = The CLA cannot write to EALLOW protected registers.
This bit is cleared by the CLA instruction, MEDIS.
1h (R/W) = The CLA is allowed to write to EALLOW protected
registers. This bit is set by the CLA instruction, MEALLOW.
10 RESERVED R 0h Reserved
9 RNDF32 R 0h Round 32-bit Floating-Point Mode
Use the MSETFLG and MMOV32 MSTF, mem32 instructions to
change the rounding mode
Reset type: SYSRSn
0h (R/W) = If this bit is zero, the MMPYF32, MADDF32 and
MSUBF32 instructions will round to zero (truncate).
1h (R/W) = If this bit is one, the MMPYF32, MADDF32 and
MSUBF32 instructions will round to the nearest even value.

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Table 7-61. _MSTF Register Field Descriptions (continued)

Bit Field Type Reset Description
8-7 RESERVED R 0h Reserved
6 TF R 0h Test Flag
The MTESTTF instruction can modify this flag based on the
condition tested The MSETFLG and MMOV32 MSTF, mem32
instructions can also be used to modify this flag
Reset type: SYSRSn
0h (R/W) = The condition tested with the MTESTTF instruction is
false.
1h (R/W) = The condition tested with the MTESTTF instruction is
true.
5-4 RESERVED R 0h Reserved
3 ZF R 0h Zero Flag
- Instructions that modify this flag based on the floating-point value
stored in the destination register:
MMOV32, MMOVD32, MABSF32, MNEGF32
- Instructions that modify this flag based on the floating-point result of
the operation:
MCMPF32, MMAXF32, and MMINF32
- Instructions that modify this flag based on the integer result of the
operation:
MMOV16, MAND32, MOR32, MXOR32, MCMP32, MASR32,
MLSR32 and
MLSL32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = The value is not zero
1h (R/W) = The value is zero
2 NF R 0h Negative Flag
- Instructions that modify this flag based on the floating-point value
stored in the destination register:
MMOV32, MMOVD32, MABSF32, MNEGF32
- Instructions that modify this flag based on the floating-point result of
the operation:
MCMPF32, MMAXF32, and MMINF32
- Instructions that modify this flag based on the integer result of the
operation:
MMOV16, MAND32, MOR32, MXOR32, MCMP32, MASR32,
MLSR32 and
MLSL32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = The value is not negative
1h (R/W) = The value is negative
1 LUF R 0h Latched Underflow Flag
The following instructions will set this flag to 1 if an underflow occurs:
MMPYF32, MADDF32,
MSUBF32, MMACF32, MEINVF32, MEISQRTF32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = An underflow condition has not been latched
1h (R/W) = An underflow condition has been latched

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Table 7-61. _MSTF Register Field Descriptions (continued)

Bit Field Type Reset Description
0 LVF R 0h Latched Overflow Flag
The following instructions will set this flag to 1 if an overflow
occurs: MMPYF32, MADDF32, MSUBF32, MMACF32, MEINVF32,
MEISQRTF32
The MSETFLG and MMOV32 MSTF, mem32 instructions can also
be used to modify this flag
Reset type: SYSRSn
0h (R/W) = An overflow condition has not been latched
1h (R/W) = An overflow condition has been latched

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7.8.4.26 _MR0 Register (Offset = 30h) [Reset = 0h]

_MR0 is shown in Figure 7-35 and described in Table 7-62.
Return to the Summary Table.
CLA Floating-Point Result Register 0
Figure 7-35. _MR0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R-0h

Table 7-62. _MR0 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R 0h CLA Result Register 0
Reset type: SYSRSn

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7.8.4.27 _MR1 Register (Offset = 34h) [Reset = 0h]

_MR1 is shown in Figure 7-36 and described in Table 7-63.
Return to the Summary Table.
CLA Floating-Point Result Register 1
Figure 7-36. _MR1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R-0h

Table 7-63. _MR1 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R 0h CLA Result Register 1
Reset type: SYSRSn

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7.8.4.28 _MR2 Register (Offset = 38h) [Reset = 0h]

_MR2 is shown in Figure 7-37 and described in Table 7-64.
Return to the Summary Table.
CLA Floating-Point Result Register 2
Figure 7-37. _MR2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R-0h

Table 7-64. _MR2 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R 0h CLA Result Register 2
Reset type: SYSRSn

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7.8.4.29 _MR3 Register (Offset = 3Ch) [Reset = 0h]

_MR3 is shown in Figure 7-38 and described in Table 7-65.
Return to the Summary Table.
CLA Floating-Point Result Register 3
Figure 7-38. _MR3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R-0h

Table 7-65. _MR3 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R 0h CLA Result Register 3
Reset type: SYSRSn

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7.8.4.30 _MPSACTL Register (Offset = 42h) [Reset = 0h]

_MPSACTL is shown in Figure 7-39 and described in Table 7-66.
Return to the Summary Table.
PSA Control Register
Figure 7-39. _MPSACTL Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
MPSA2CFG MPSA2CLEAR MPSA1CLEAR MDWDBCYC MDWDBSTART MPABCYC MPABSTART
R/W-0h R-0/W1S-0h R-0/W1S-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-66. _MPSACTL Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7-6 MPSA2CFG R/W 0h CLA PSA2 Polynomial Configuration Bits: These bits configure the
type of polynomial used for PSA2. The polynomials chosen are
commonly used in the industry:
Mode Polynomial Type
0,0 PSA
0,1 CRC32
1,0 CRC16
1,1 CRC16-CCITT
Note: [1] Polynomial configuration should be performed when PSA2
is stopped.
Reset type: SYSRSn
5 MPSA2CLEAR R-0/W1S 0h CLA PSA2 Clear Bit:
Writing of "1" will clear contents of PSA2 register.
Writes of "0" are ignored.
Always reads back a "0"
Note: Clearing operation should be performed when PSA2 is
stopped.
Reset type: SYSRSn
4 MPSA1CLEAR R-0/W1S 0h CLA PSA1 Clear Bit:
Writing of "1" will clear contents of PSA1 register.
Writes of "0" are ignored.
Always reads back a "0"
Note: Clearing operation should be performed when PSA1 is
stopped.
Reset type: SYSRSn
3 MDWDBCYC R/W 0h CLA Data Write Data Bus PSA2 Cycle or Event Based Bit:
0 PSA2 calculated on every cycle
1 PSA2 calculated on every bus event
Reset type: SYSRSn
2 MDWDBSTART R/W 0h CLA Data Write Data Bus PSA2 Start/Stop Bit:
0 PSA2 stopped
1 PSA2 start
Reset type: SYSRSn
1 MPABCYC R/W 0h CLA Program Address Bus PSA1 Cycle/Event Based Bit:
0 PSA1 calculated on every cycle
1 PSA1 calculated on every bus event
Reset type: SYSRSn
0 MPABSTART R/W 0h CLA Program Address Bus PSA1 Start/Stop Bit:
0 PSA1 stopped
1 PSA1 start
Reset type: SYSRSn

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7.8.4.31 _MPSA1 Register (Offset = 44h) [Reset = 0h]

_MPSA1 is shown in Figure 7-40 and described in Table 7-67.
Return to the Summary Table.
PSA1 Register
Figure 7-40. _MPSA1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R/W-0h

Table 7-67. _MPSA1 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R/W 0h PSA1 Value: Reading this register gives the current PSA1 value. The
value can be read at any time.
Writes to this register are allowed to initialize the PSA1 to a known
value. Writes to this register should only be made when PSA1 is
stopped.
Register value is cleared to zero by reset or by writing to the
MPSA1CLEAR bit in the MPSACTL register.
Reset type: SYSRSn

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7.8.4.32 _MPSA2 Register (Offset = 46h) [Reset = 0h]

_MPSA2 is shown in Figure 7-41 and described in Table 7-68.
Return to the Summary Table.
PSA2 Register
Figure 7-41. _MPSA2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R/W-0h

Table 7-68. _MPSA2 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R/W 0h PSA2 Value: Reading this register gives the current PSA2 value. The
value can be read at any time.
Writes to this register are allowed to initialize the PSA2 to a known
value. Writes to this register should only be made when PSA2 is
stopped.
Register value is cleared to zero by reset or by writing to the
MPSA2CLEAR bit in the MPSACTL register.
Reset type: SYSRSn

7.8.5 CLA Registers to Driverlib Functions

Table 7-69. CLA Registers to Driverlib Functions
File Driverlib Function
MVECT1
cla.h CLA_mapTaskVector
MVECT2
- See MVECT1
MVECT3
- See MVECT1
MVECT4
- See MVECT1
MVECT5
- See MVECT1
MVECT6
- See MVECT1
MVECT7
- See MVECT1
MVECT8
- See MVECT1
MCTL
cla.h CLA_performHardReset
cla.h CLA_performSoftReset
cla.h CLA_enableIACK
cla.h CLA_disableIACK
cla.h CLA_enableBackgroundTask
cla.h CLA_disableBackgroundTask
cla.h CLA_startBackgroundTask
cla.h CLA_enableHardwareTrigger

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Table 7-69. CLA Registers to Driverlib Functions (continued)

File Driverlib Function
cla.h CLA_disableHardwareTrigger
MVECTBGRNDACTIVE
cla.h CLA_getBackgroundActiveVector
SOFTINTEN
cla.h CLA_enableSoftwareInterrupt
cla.h CLA_disableSoftwareInterrupt
MSTSBGRND
cla.h CLA_getBackgroundTaskStatus
MCTLBGRND
cla.h CLA_enableBackgroundTask
cla.h CLA_disableBackgroundTask
cla.h CLA_startBackgroundTask
cla.h CLA_enableHardwareTrigger
cla.h CLA_disableHardwareTrigger
MVECTBGRND
cla.h CLA_getBackgroundActiveVector
cla.h CLA_mapBackgroundTaskVector
MIFR
cla.h CLA_getPendingTaskFlag
cla.h CLA_getAllPendingTaskFlags
cla.h CLA_forceTasks
MIOVF
cla.h CLA_getTaskOverflowFlag
cla.h CLA_getAllTaskOverflowFlags
MIFRC
cla.h CLA_forceTasks
MICLR
cla.h CLA_clearTaskFlags
MICLROVF
-
MIER
cla.h CLA_enableTasks
cla.h CLA_disableTasks
MIRUN
cla.h CLA_getTaskRunStatus
cla.h CLA_getAllTaskRunStatus
MPC
-
MAR0
-
MAR1
-
MSTF
-
MR0

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Table 7-69. CLA Registers to Driverlib Functions (continued)

File Driverlib Function
-
MR1
-
MR2
-
MR3
-
MPSACTL
-
MPSA1
-
MPSA2
-
MVECTBGRNDACTIVE
cla.h CLA_getBackgroundActiveVector
MPSACTL
-
MPSA1
-
MPSA2
-
SOFTINTEN
cla.h CLA_enableSoftwareInterrupt
cla.h CLA_disableSoftwareInterrupt
SOFTINTFRC
cla.h CLA_forceSoftwareInterrupt

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Chapter 8
Dual-Clock Comparator (DCC)

This chapter describes the Dual-Clock Comparator (DCC) module.

8.1 Introduction...............................................................................................................................................................998
8.2 Module Operation..................................................................................................................................................... 999
8.3 Interrupts.................................................................................................................................................................1005
8.4 Software.................................................................................................................................................................. 1006
8.5 DCC Registers........................................................................................................................................................ 1007

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8.1 Introduction
The dual-clock comparator module is used for evaluating and monitoring the clock input based on a second
clock, which can be a more accurate and reliable version. This instrumentation is used to detect faults in clock
source or clock structures, thereby enhancing the system's safety metrics.
8.1.1 Features
The main features of each of the DCC modules are:
• Allows the application to ensure that a fixed ratio is maintained between frequencies of two clock signals.
• Supports the definition of a programmable tolerance window in terms of the number of reference clock cycles.
• Supports continuous monitoring without requiring application intervention.
• Supports a single-sequence mode for spot measurements.
• Allows the selection of a clock source for each of the counters, resulting in several specific use cases.
8.1.2 Block Diagram
Figure 8-1 shows how the DCC connects to the rest of the system. Figure 8-2 shows the main concept of the
DCC module.

VBUSP Bus Interface

Clock Sources

Input XBAR

APLL

Error
XOSC

Interrupt
INTOSC1,2 DCC

AUXCLK

System Control
Clock
Gates, Dividers Peripheral
Clocks

Figure 8-1. DCC Module Overview

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DCC
20 Module
DCCxCLKSRC0 Counter0

DCCxCLKSRC0
20 DCC DONE
Valid0
Compare Logic ERROR

20
DCCxCLKSRC1 Counter1

Figure 8-2. DCC Operation

8.2 Module Operation

As shown in Figure 8-2, DCC contains three counters – Counter0, Valid0 and Counter1. Initially, all counters
are loaded with their user-defined, pre-load value. Counter0 and Counter1 start decrementing once the DCC is
enabled at rates determined by the frequencies of Clock0 and Clock1, respectively. When Counter0 equals 0
(expires), the Valid0 counter decrements at a rate determined by Clock0. If Counter1 decrements to 0 in the valid
window, then no error is generated and Clock1 is considered to be good within allowable tolerance as configured
by the user.

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8.2.1 Configuring DCC Counters

Counter0 and Counter1 are configured based on the ratio between the frequencies of Clock0 and Clock1
(Fclk1×Counter0 = Fclk0×Counter1). The Valid0 counter provides tolerance and is configured based on the
error in DCC. Since Clock0 and Clock1 are asynchronous, the start and stop of the counters do not occur
synchronously. Hence, while configuring the counters, two different sources of errors must be accounted for:
• DCC Errors due to the asynchronous timing of Clock0 and Clock1: this depends on the frequency of Clock0
and Clock1:
– If Fclk1 > Fclk0, then Async. Error (in Clock0 cycles) = 2 + 2×(max(Fsysclk/Fclk0))
– If Fclk1 < Fclk0, then Async. Error (in Clock0 cycles) = 2×(Fclk0/Fclk1) + 2×(max(Fsysclk/Fclk0))
– If Fclk1 is unknown, then Async. Error (in Clock0 cycles) = 2 + 2×(Fsysclk/Fclk0)
• Digitization Error = 8 Clock0 cycles
DCC Error (in Clock0 Cycles) = Async. Error + Digitization Error
DCC error shows up as a frequency error for clock under measurement. This error is DCC induced and does not
represent error in frequency of clock under measurement. The application needs to take this into consideration
while configuring the counters, and determine a desirable tolerance for DCC error that defines the window of
measurement. To illustrate:
Window (in Clock0 Cycles) = (DCC Error) / (0.01×Tolerance)
For example, if DCC Error is 10 and the tolerance desired is +/-0.1%, then:
Window (in Clock0 Cycles) = 10/(0.01×0.1) = 10000

Based on above formula for Window, if the desired tolerance is low, then the counter values are large and
increase the window of measurement. This means that counter values for a tolerance of 0.1% are larger than
that of 0.2%. So, based on the application defined tolerance, define the window of measurement in terms of
Clock0 cycles.
The clock under measurement can have an allowed frequency error. If this error is expected, then the error
can also be accounted while configuring counters. For example, if measuring INTOSC1/2 frequency using
an external crystal as a reference clock, the allowable tolerance of INTOSC1/2 (for example, +/-1%) can be
accounted for and factored into the counter configuration. The formula is:
Frequency Error Allowed (in Clock0 Cycles) = Window × (Allowable Frequency Tolerance (in %) / 100)
Total Error (in Clock0 Cycles) = DCC Error + Frequency Error Allowed

The following equations are used to configure counter values:

Counter0 (DCCCNTSEED0) = Window - Total Error
Valid0 (DCCVALIDSEED0) = 2 × Total Error
Counter1 (DCCCNTSEED1) = Window × (Fclk1/Fclk0)

Note
Counter1 is a 20-bit counter, so the maximum possible value cannot exceed 1048575. If the value
does exceed, then increase the desired Tolerance for DCC error, so that Window of measurement is
lowered. The following formula can be used to compute minimum tolerance possible:
Tolerance (%) = (100 × DCC Error × (Fclk1/Fclk0)) / 1048575

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8.2.2 Single-Shot Measurement Mode

The DCC module can be programmed to count down one time by enabling the single-shot mode. In this mode,
the DCC stops operating when the down counter0 and the valid counter0 reach 0.
At the end of one sequence of counting down in this single-shot mode, the DCC gets disabled automatically,
which prevents further counting. This mode is typically used for spot-checking the frequency of a signal.
Example-1: Validating PLLRAWCLK frequency
A practical example of the usage is to validate the PLL output clock frequency using the XTAL as the reference
clock. Assume XTAL is 10 MHz, PLL output frequency is 100 MHz, SYSCLK is 100 MHz, allowable Frequency
Tolerance is 0.1%, and DCC Tolerance required is 0.1%. The measurement sequence proceeds as follows:
• Set Clock0 source for Counter0 and Valid0 as XTAL, and Clock1 source for Counter1 as PLL output clock.
• Based on the equations defined in Section 8.2.1, calculated seed values for Counters can be Counter0 =
29940; Valid0 = 120; Counter1 = 300000
• Once the DCC is enabled, the counters Counter0 and Counter1 both start counting down from their seed
values.
• When Counter0 reaches zero, Counter0 automatically triggers the Valid0 counter.
• When Valid0 reaches zero and Counter1 is not zero, an ERROR status flag is set and a "DCC error" is
sent to the PIE. Counter1 is frozen so that the counter stops counting down any further. The application can
enable an interrupt to be generated from the PIE whenever this DCC error is indicated. Refer to Section 3.5.5
to know the channel mapping of DCC Interrupt.
• The application then needs to clear the ERROR status flag and restart the DCC module so that the module is
ready for the next spot measurement.
If there is no error generated at the end of the sequence, then the DONE status flag is set and a DONE interrupt
is generated. The application must clear the DONE flag before restarting the DCC.
Error Conditions:
An error condition is generated by any one of the following:
1. Counter1 counts down to 0 before Counter0 reaches 0. This means that Clock1 is faster than expected, or
Clock0 is slower than expected. This error includes the case when Clock0 is stuck at 1 or 0.
2. Counter1 does not reach 0 even when Counter0 and Valid0 have both reached 0. This means that Clock1 is
slower than expected. This error includes the case when Clock1 is stuck at 1 or 0.
Any error freezes the counters from counting. An application can then read out the counter values to help
determine what caused the error.

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Example-2: Measuring AUXCLKIN frequency

Another example of single-shot mode is to measure the frequency of AUXCLKIN (unknown frequency) using
INTOSC1 (10 MHz) as the reference clock and SYSCLK is 10 MHz. The measurement sequence proceeds as
follows:
• Set Clock0 source for Counter0 and Valid0 as INTOSC1 (10 MHz), and Clock1 source for Counter1 as
AUXCLKIN.
• Now configure counter values using equations in Section 8.2.1. For tolerance = ±0.1%, Total
Error = 10 clock0 cycles; Window = 10000 clock0 cycles; Counter0 = 9990; Valid0 = 20. Since Clock1
frequency (Fclk1) is unknown, the Counter1 value can be set to the maximum value, 1048575 (0xFFFFF).
• Once the DCC is enabled, the counters Counter0 and Counter1 both start counting down from their seed
values.
• Since Counter1 is set to the maximum value, 1048575, the counter does not expire when Counter0 and
Valid0 have expired. This generates an error that is expected and the application ignores this error and uses
Counter1 values to compute the frequency of Clock1 (Fclk1).
• Knowing the frequency of Clock0 (INTOSC1), Fclk0 = 10 MHz, and using Equation 1, the frequency of
AUXCLKIN, Fclk1, can be measured:

(?HG0 × :1048575 F /A=O. %KQJPAN1; 10 × (1048575 F /A=O. %KQJPAN1)

(?HG1 = =
:%KQJPAN0 + 8=HE@0; (9990 + 20)
(1)

8.2.3 Continuous Monitoring Mode

In this mode, the DCC is used by the application to make sure that two clock signals maintain the correct
frequency ratio. Suppose the application wants to make sure that the PLL output signal always maintains a fixed
frequency relationship with the XTAL:
• In this case, the application can use the XTAL as the Clock0 signal (for Counter0 and Valid0) and the PLL
output as the Clock1 (for Counter1).
• The seed values of Counter0, Valid0 and Counter1 are selected based on the equations defined in Section
8.2.1 such that if the actual frequencies of Clock0 and Clock1 are equal to their expected frequencies, then
the Counter1 reaches zero during the count down of the Valid0 counter.
• If the Counter1 reaches zero during the count down of the Valid0 counter, then all the counters (Counter0,
Valid0, Counter1) are reloaded with their initial seed values.
• This sequence of counting down and checking then continues as long as there is no error, or until the DCC
module is disabled.
• The counters must get reloaded if the application resets and restarts the DCC module.
Error Conditions:
An error condition is generated by one of the following:
1. Counter1 counts down to 0 before Counter0 reaches 0. This means that Clock1 is faster than expected or
Clock0 is slower than expected. This condition includes the case when Clock0 is stuck at 1 or 0.
2. Counter1 does not reach 0 even when Counter0 and Valid0 have both reached 0. This means that Clock1 is
slower than expected. This condition includes the case when Clock1 is stuck at 1 or 0.
Any error freezes the counters from counting. An application can then read out the counter values to help
determine what caused the error.

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8.2.4 Error Conditions

While operating in continuous mode, the counters get reloaded with the seed values and continue counting down
under the following conditions:
• The module is reset or restarted by the application, OR
• Counter0, Valid 0, and Counter1 all reach 0 without any error.

(no error)
Error

Count0 Count0
Clock0

Valid0 Valid0
0

Count1 Count1
Clock1

0
time
reload reload
Clock1 must expire
in this window, otherwise
signal an error

Figure 8-3. Counter Relationship

Error

Count0
Clock0

Valid0
0

Count1
Clock1

0
time
reload
Counter1 does not reach 0
before VALID0 reaches 0
Figure 8-4. Clock1 Slower Than Clock0 - Results in an Error and Stops Counting

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Error

Count0
Clock0

Valid0
0

Count1
Clock1

0
time
reload
Counter1 reaches 0 before
Counter0 reaches 0
Figure 8-5. Clock1 Faster Than Clock0 - Results in an Error and Stops Counting

Error

Count0
Clock0

Valid0
0

Count1
Count1 does not count down
Clock1 due to an inactive clock 1

0
time
reload
An error signal is generated since Count1
does not reach 0 in the Valid0 window.
Figure 8-6. Clock1 Not Present - Results in an Error and Stops Counting

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Error
Count0
Count0 and Valid 0 do not
Clock0 count down due to an
inactive clock 0
Valid0

Count1
Clock1

time
reload
Counter1 reaches 0 at the
right time, but since Clock0 is not running,
Valid0 hasn’t started, thus an error is generated.

Figure 8-7. Clock0 Not Present - Results in an Error and Stops Counting

8.3 Interrupts
DCC generates an interrupt on either of two events:
• DCC finishes counting and all the counters expire within a defined window indicating DONE operation,
provided DCCGCTRL.DONENA=1.
• DCC finishes counting with error where counters do not expire in a defined window. This indicates an
ERROR event, and sets an interrupt provided DCCGCTRL.ERRENA=1.
Interrupts generated by DONE or ERROR events are ORed and flagged as DCCx interrupts. Refer to Section
3.5.5 to determine the interrupt channel mapping. The application interrupt service routine needs to check the
status flag inside the DCCSTATUS register to determine whether the interrupt is due to ERROR or DONE.
DCC Error interrupts can also be configured as a Non-Maskable Interrupt (NMI) by enabling the
CLKFAILCFG.DCCx_ERROR_EN flag.

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8.4 Software
8.4.1 DCC Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/dcc
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
8.4.1.1 DCC Single shot Clock verification
FILE: dcc_ex1_single_shot_verification.c
This program uses the XTAL clock as a reference clock to verify the frequency of the PLLRAW clock.
The Dual-Clock Comparator Module 0 is used for the clock verification. The clocksource0 is the reference clock
(Fclk0 = 20Mhz) and the clocksource1 is the clock that needs to be verified (Fclk1 = 120Mhz). Seed is the value
that gets loaded into the Counter.
Please refer to the TRM for details on counter seed values to be set.

External Connections
• None
Watch Variables
• status/result - Status of the PLLRAW clock verification
8.4.1.2 DCC Single shot Clock measurement
FILE: dcc_ex2_single_shot_measurement.c
This program demonstrates Single Shot measurement of the INTOSC2 clock post trim using XTAL as the
reference clock.
The Dual-Clock Comparator Module 0 is used for the clock measurement. The clocksource0 is the reference
clock (Fclk0 = 20Mhz) and the clocksource1 is the clock that needs to be measured (Fclk1 = 10Mhz). Since the
frequency of the clock1 needs to be measured an initial seed is set to the max value of the counter.
Please refer to the TRM for details on counter seed values to be set.

External Connections
• None
Watch Variables
• result - Status if the INTOSC2 clock measurement completed successfully.
• meas_freq1 - measured clock frequency, in this case for INTOSC2.
8.4.1.3 DCC Continuous clock monitoring
FILE: dcc_ex3_continuous_monitoring_of_clock.c
This program demonstrates continuous monitoring of PLL Clock in the system using INTOSC2 as the reference
clock. This would trigger an interrupt on any error, causing the decrement/ reload of counters to stop.
The Dual-Clock Comparator Module 0 is used for the clock monitoring. The clocksource0 is the reference clock
(Fclk0 = 10Mhz) and the clocksource1 is the clock that needs to be monitored (Fclk1 = 120Mhz). The clock0 and
clock1 seed are set to achieve a window of 340us. Seed is the value that gets loaded into the Counter. For the
sake of demo a slight variance is given to clock1 seed value to generate an error on continuous monitoring.
Please refer to the TRM for details on counter seed values to be set. Note : When running in flash configuration
it is good to do a reset & restart after loading the example to remove any stale flags/states.
External Connections

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• None
Watch Variables
• status/result - Status of the PLLRAW clock monitoring
• cnt0 - Counter0 Value measure when error is generated
• cnt1 - Counter1 Value measure when error is generated
• valid - Valid0 Value measure when error is generated
8.4.1.4 DCC Continuous clock monitoring
FILE: dcc_ex3_continuous_monitoring_of_clock_syscfg.c
This program demonstrates continuous monitoring of PLL Clock in the system using INTOSC2 as the reference
clock. This would trigger an interrupt on any error, causing the decrement/ reload of counters to stop. The
Dual-Clock Comparator Module 0 is used for the clock monitoring. The clocksource0 is the reference clock
(Fclk0 = 10Mhz) and the clocksource1 is the clock that needs to be monitored (Fclk1 = 120Mhz). The clock0 and
clock1 seed are set automatically by the error tolerances defined in the sysconfig file included this project. For
the sake of demo an un-realistic tolerance is assumed to generate an error on continuous monitoring.
Please refer to the TRM for details on counter seed values to be set. Note : When running in flash configuration
it is good to do a reset & restart after loading the example to remove any stale flags/states.
External Connections
• None
Watch Variables
• status/result - Status of the PLLRAW clock monitoring
• cnt0 - Counter0 Value measure when error is generated
• cnt1 - Counter1 Value measure when error is generated
• valid - Valid0 Value measure when error is generated
8.4.1.5 DCC Detection of clock failure
FILE: dcc_ex4_clock_fail_detect.c
This program demonstrates clock failure detection on continuous monitoring of the PLL Clock in the system
using XTAL as the osc clock source. Once the oscillator clock fails, it would trigger a DCC error interrupt,
causing the decrement/ reload of counters to stop. In this examples, the clock failure is simulated by turning off
the XTAL oscillator. Once the ISR is serviced, the osc source is changed to INTOSC1 and the PLL is turned off.
The Dual-Clock Comparator Module 0 is used for the clock monitoring. The clocksource0 is the reference clock
(Fclk0 = 20Mhz) and the clocksource1 is the clock that needs to be monitored (Fclk1 = 120Mhz). Seed is the
value that gets loaded into the Counter.
In the current example, the XTAL is expected to be a Resonator running in Crystal mode which is later switched
off to simulate the clock failure. If an SE Crystal is used, you will need to physically disconnect the clock on
the board. Please refer to the TRM for details on counter seed values to be set. Note : When running in flash
configuration it is good to do a reset & restart after loading the example to remove any stale flags/states.

External Connections
• None
Watch Variables
• status/result - Status of the clock failure detection
8.5 DCC Registers
This section describes the Dual Clock Comparator Registers.

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Note
DCC is used by Boot ROM, hence the register values can be different than the hardware reset value.
The user needs to make sure to configure the values of these registers to the desired value before
enabling DCC.

8.5.1 DCC Base Address Table

Table 8-1. DCC Base Address Table
Bit Field Name
DriverLib Name Base Address CPU1 DMA HIC CLA Pipeline Protected
Instance Structure
Dcc0Regs DCC_REGS DCC0_BASE 0x0005_E700 YES - - - YES
Dcc1Regs DCC_REGS DCC1_BASE 0x0005_E740 YES - - - YES

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8.5.2 DCC_REGS Registers

Table 8-2 lists the memory-mapped registers for the DCC_REGS registers. All register offset addresses not
listed in Table 8-2 should be considered as reserved locations and the register contents should not be modified.
Table 8-2. DCC_REGS Registers
Offset Acronym Register Name Write Protection Section
0h DCCGCTRL Starts / stops the counters. Clears the error Go
signal.
8h DCCCNTSEED0 Seed value for the counter attached to Clock Go
Source 0.
Ch DCCVALIDSEED0 Seed value for the timeout counter attached to Go
Clock Source 0.
10h DCCCNTSEED1 Seed value for the counter attached to Clock Go
Source 1.
14h DCCSTATUS Specifies the status of the DCC Module. Go
18h DCCCNT0 Value of the counter attached to Clock Source 0. Go
1Ch DCCVALID0 Value of the valid counter attached to Clock Go
Source 0.
20h DCCCNT1 Value of the counter attached to Clock Source 1. Go
24h DCCCLKSRC1 Selects the clock source for Counter 1. Go
28h DCCCLKSRC0 Selects the clock source for Counter 0. Go

Complex bit access types are encoded to fit into small table cells. Table 8-3 shows the codes that are used for
access types in this section.
Table 8-3. DCC_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
R-1 R Read
-1 Returns 1s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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8.5.2.1 DCCGCTRL Register (Offset = 0h) [Reset = 5555h]

DCCGCTRL is shown in Figure 8-8 and described in Table 8-4.
Return to the Summary Table.
Starts / stops the counters. Clears the error signal.
Figure 8-8. DCCGCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DONEENA SINGLESHOT ERRENA DCCENA
R/W-5h R/W-5h R/W-5h R/W-5h

Table 8-4. DCCGCTRL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 DONEENA R/W 5h DONE Enable
Enables/disables the done interrupt signal, but has no effect on the
done status flag in DCCSTAT register.
0101 The done signal is disabled
Others The done signal is enabled
Reset type: SYSRSn
11-8 SINGLESHOT R/W 5h Single-Shot Enable
Enables/disables repetitive operation of the DCC.
1010: Stop counting when COUNTER0 and VALID0 both reach zero
1011: Reserved
Others: Continuously repeat (until error)
Reset type: SYSRSn
7-4 ERRENA R/W 5h Error Enable
Enables/disables the error signal.
0101 The error signal is disabled
Others The error signal is enabled
Reset type: SYSRSn
3-0 DCCENA R/W 5h DCC Enable
Starts and stops the operation of the DCC.
0101 Counters are stopped
Others Counters are running
Reset type: SYSRSn

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8.5.2.2 DCCCNTSEED0 Register (Offset = 8h) [Reset = 0h]

DCCCNTSEED0 is shown in Figure 8-9 and described in Table 8-5.
Return to the Summary Table.
Seed value for the counter attached to Clock Source 0.
Figure 8-9. DCCCNTSEED0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED COUNTSEED0
R-0h R/W-0h

Table 8-5. DCCCNTSEED0 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-0 COUNTSEED0 R/W 0h Seed Value for Counter 0
Contains the seed value that gets loaded into Counter 0 (Clock
Source 0).
NOTE: Operating the DCC with '0' in the COUNTSEED0 register will
result in undefined operation.
Reset type: SYSRSn

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8.5.2.3 DCCVALIDSEED0 Register (Offset = Ch) [Reset = 0h]

DCCVALIDSEED0 is shown in Figure 8-10 and described in Table 8-6.
Return to the Summary Table.
Seed value for the timeout counter attached to Clock Source 0.
Figure 8-10. DCCVALIDSEED0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VALIDSEED
R-0h R/W-0h

Table 8-6. DCCVALIDSEED0 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 VALIDSEED R/W 0h Seed Value for Valid Duration Counter 0
Contains the seed value that gets loaded into the valid duration
counter for Clock Source 0.
NOTE: Operating the DCC with '0' in the VALIDSEED0 register will
result in undefined operation. VALID0 defines a window in which
COUNT1 expires. This window is meant to be at least four cycles
wide. Do not program a value less than '4' into the VALID0 register.
Reset type: SYSRSn

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8.5.2.4 DCCCNTSEED1 Register (Offset = 10h) [Reset = 0h]

DCCCNTSEED1 is shown in Figure 8-11 and described in Table 8-7.
Return to the Summary Table.
Seed value for the counter attached to Clock Source 1.
Figure 8-11. DCCCNTSEED1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED COUNTSEED1
R-0h R/W-0h

Table 8-7. DCCCNTSEED1 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-0 COUNTSEED1 R/W 0h Seed Value for Counter 1
Contains the seed value that gets loaded into Counter 1 (Clock
Source 1).
NOTE: Operating the DCC with '0' in the COUNTSEED1 register will
result in undefined operation.
Reset type: SYSRSn

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8.5.2.5 DCCSTATUS Register (Offset = 14h) [Reset = 0h]

DCCSTATUS is shown in Figure 8-12 and described in Table 8-8.
Return to the Summary Table.
Specifies the status of the DCC Module.
Figure 8-12. DCCSTATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED DONE ERR
R-0h R/W-0h R/W-0h

Table 8-8. DCCSTATUS Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 DONE R/W 0h Single-Shot Done Flag
Indicates when single-shot mode is complete without error. Writing a
'1' to this bit clears the flag.
0 Single-shot mode has not completed.
1 Single-shot mode has completed.
Reset type: SYSRSn
0 ERR R/W 0h Error Flag
Indicates whether or not an error has occurred. Writing a '1' to this bit
clears the flag.
0 No errors have occurred.
1 An error has occurred.
Reset type: SYSRSn

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8.5.2.6 DCCCNT0 Register (Offset = 18h) [Reset = 0h]

DCCCNT0 is shown in Figure 8-13 and described in Table 8-9.
Return to the Summary Table.
Value of the counter attached to Clock Source 0.
Figure 8-13. DCCCNT0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED COUNT0
R-0h R-0h

Table 8-9. DCCCNT0 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-0 COUNT0 R 0h Current Value of Counter 0
Reset type: SYSRSn

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8.5.2.7 DCCVALID0 Register (Offset = 1Ch) [Reset = 0h]

DCCVALID0 is shown in Figure 8-14 and described in Table 8-10.
Return to the Summary Table.
Value of the valid counter attached to Clock Source 0.
Figure 8-14. DCCVALID0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VALID0
R-0h R-0h

Table 8-10. DCCVALID0 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 VALID0 R 0h Current Value of Valid 0
Reset type: SYSRSn

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8.5.2.8 DCCCNT1 Register (Offset = 20h) [Reset = 0h]

DCCCNT1 is shown in Figure 8-15 and described in Table 8-11.
Return to the Summary Table.
Value of the counter attached to Clock Source 1.
Figure 8-15. DCCCNT1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED COUNT1
R-0h R-0h

Table 8-11. DCCCNT1 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-0 COUNT1 R 0h Current Value of Counter 1
Reset type: SYSRSn

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8.5.2.9 DCCCLKSRC1 Register (Offset = 24h) [Reset = 0h]

DCCCLKSRC1 is shown in Figure 8-16 and described in Table 8-12.
Return to the Summary Table.
Selects the clock source for Counter 1.
Figure 8-16. DCCCLKSRC1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY RESERVED CLKSRC1
R-0/W-0h R-0h R/W-0h

Table 8-12. DCCCLKSRC1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 KEY R-0/W 0h Enables or Disables Clock Source Write for COUNT1
1010 The CLKSRC field selects the clock source for COUNT1.
Others: Previous values retained new writes on register fields has no
impact.
Reset type: SYSRSn
11-5 RESERVED R 0h Reserved
4-0 CLKSRC1 R/W 0h Clock Source Select for Counter 1
Specifies the clock source for COUNT1, when the KEY field enables
this feature.
00000: PLLRAWCLK
00010: INTOSC1
00011: INTOSC2
00110: CPU1SYSCLK
01001: INPUTXBAR (Output15 of the input-xbar)
01010: AUXCLKIN
01011: EPWMCLK
01100: LSPCLK
01101: ADCCLK
01110: WDCLK
01111: CAN0BITCLK
Note: All other values are "RSVD"
Reset type: SYSRSn

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8.5.2.10 DCCCLKSRC0 Register (Offset = 28h) [Reset = 0h]

DCCCLKSRC0 is shown in Figure 8-17 and described in Table 8-13.
Return to the Summary Table.
Selects the clock source for Counter 0.
Figure 8-17. DCCCLKSRC0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY RESERVED CLKSRC0
R-0/W-0h R-0h R/W-0h

Table 8-13. DCCCLKSRC0 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 KEY R-0/W 0h Enables or Disables Clock Source Write for COUNT0
1010: The CLKSRC0 field written with key gets updated to with new
selection to clock COUNT0.
Others: Previous values retained new writes on register fields has no
impact.
Reset type: SYSRSn
11-4 RESERVED R 0h Reserved
3-0 CLKSRC0 R/W 0h Clock Source Select for Counter 0
Specifies the clock source for COUNT0, when the KEY field enables
this feature.
0000: XTAL/X1
0001: INTOSC1
0010: INTOSC2
0101: CPU1SYSCLK
1100: INPUTXBAR (Output16 of the input-xbar)
Note: All other values are Reserved
Reset type: SYSRSn

8.5.3 DCC Registers to Driverlib Functions

Table 8-14. DCC Registers to Driverlib Functions
File Driverlib Function
DCCGCTRL
dcc.h DCC_enableModule
dcc.h DCC_disableModule
dcc.h DCC_enableErrorSignal
dcc.h DCC_enableDoneSignal
dcc.h DCC_disableErrorSignal
dcc.h DCC_disableDoneSignal
dcc.h DCC_enableSingleShotMode
dcc.h DCC_disableSingleShotMode
DCCCNTSEED0
dcc.h DCC_setCounterSeeds
DCCVALIDSEED0
dcc.h DCC_setCounterSeeds
DCCCNTSEED1

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Table 8-14. DCC Registers to Driverlib Functions (continued)

File Driverlib Function
dcc.h DCC_setCounterSeeds
DCCSTATUS
dcc.h DCC_getErrorStatus
dcc.h DCC_getSingleShotStatus
dcc.h DCC_clearErrorFlag
dcc.h DCC_clearDoneFlag
sysctl.c SysCtl_isPLLValid
DCCCNT0
dcc.h DCC_getCounter0Value
DCCVALID0
dcc.h DCC_getValidCounter0Value
DCCCNT1
dcc.h DCC_getCounter1Value
DCCCLKSRC1
dcc.h DCC_setCounter1ClkSource
dcc.h DCC_getCounter1ClkSource
DCCCLKSRC0
dcc.h DCC_setCounter0ClkSource
dcc.h DCC_getCounter0ClkSource

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Chapter 9
Background CRC-32 (BGCRC)

The Background CRC (BGCRC) module that helps to identify memory faults and corruption, is discussed in this
chapter.

9.1 Introduction.............................................................................................................................................................1022
9.2 Functional Description...........................................................................................................................................1024
9.3 Application of the BGCRC..................................................................................................................................... 1026
9.4 Software.................................................................................................................................................................. 1032
9.5 BGCRC Registers................................................................................................................................................... 1033

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9.1 Introduction
The Background CRC (BGCRC) module computes a CRC-32 on a configurable block of memory. It
accomplishes this by fetching the specified block of memory during idle cycles (when the CPU, CLA, or DMA
is not accessing the memory block). The calculated CRC-32 value is compared against a golden CRC-32 value
to indicate a pass or fail. In essence, the BGCRC helps identify memory faults and corruption. There are two
BGCRC modules, CPU_CRC and CLA_CRC. The two BGCRC modules differ only in the memories they test.
9.1.1 BGCRC Related Collateral

Getting Started Materials

• CRC Engines in C2000 Devices Application Report
9.1.2 Features
The BGCRC module has the following features:
• One cycle CRC-32 computation on 32 bits of data
• No CPU bandwidth impact for zero wait state memory
• Minimal CPU bandwidth impact for non-zero wait state memory
• Dual operation modes (CRC-32 mode and scrub mode)
• Watchdog timer to time CRC-32 completion
• Ability to pause and resume CRC-32 computation

9.1.3 Block Diagram

Figure 9-1 shows the BGCRC block diagram.

Figure 9-1. BGCRC Block Diagram

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9.1.4 Memory Wait States and Memory Map

Figure 9-2 shows the memory map of the BGCRC module. M0, M1, MSGRAM, LS[x]RAM, and GS[x]RAM
are all zero wait-state memories. BGCRC accesses these memories with minimal impact on normal program
operation. For instance, if a BGCRC access is being made to a zero wait-state memory in the current cycle,
the earliest the operating program can make access to the same memory location is in the next cycle. Similarly
for the non-zero wait state memories SECROM, DATAROM and BOOTROM, the worst case delay for functional
access after a BGCRC access is the wait-state amount.

CPU.LS[x]RAM CPU2CLA.MSGRAM
Memories tested
by CPU CRC

CPU.M0/M1 CLA2CPU.MSGRAM
Memories tested
by CLA CRC

CPU.SECROM CPU_CRC CLA2DMA.MSGRAM

CPU.BOOTROM DMA2CLA.MSGRAM

CPU.GS[x]RAM

CLA.DATAROM

CLA_CRC

CLA.PROGROM

Figure 9-2. BGCRC Memory Map

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9.2 Functional Description

The CRC-32 calculation of the BGCRC module can be kicked off by configuring the register BGCRC_EN.START
to 1010. Once started, the module performs the background memory checks without CPU or CLA intervention.
However, on completion of the CRC-32 calculation or in the event of a failure, the CPU or CLA is notified through
an interrupt and task, respectively.
As highlighted in the overview, there are two BGCRC modules. CPU_CRC that is configurable by the CPU can
only generate an interrupt. CLA_CRC however, can be configured by both the CPU and CLA and can generate
an interrupt to the CPU or task for the CLA.
9.2.1 Data Read Unit
Once the CRC-32 calculation is started, the BGCRC module continuously reads data from memory as
a background process. These reads happen during the idle times (when the CPU, CLA or DMA is not
accessing the memory block) and so does not impact functional access. The data read unit only reads data
if there is no pending functional access. The data read unit begins operation by reading a block of data
BGCRC_CTRL2.BLOCK_SIZE from address BGCRC_START_ADDR. Note that BGCRC_START_ADDR must
be 0x80 word aligned. For a non-0x80 word aligned BGCRC_START_ADDR, the LSB bits are zeroed out to
get a 0x80 word aligned BGCRC_START_ADDR. For instance, if the programmed BGCRC_START_ADDR =
0x1AF3, the internal 0x80 word aligned start address is 0x1A80.
When the data read unit reads a block of data, ECC and parity are checked. Any ECC or parity errors that
occur during the read is indicated by setting the respective NMI and generating an interrupt if configured as
so. The BGCRC module, however, does not write back the corrected memory contents on the occurrence of a
correctable ECC error. Writing back the corrected values can be handled by software.
9.2.2 CRC-32 Compute Unit
After the data read unit reads a block of data, the data read unit feeds this data to the CRC-32 compute unit.
This unit computes the CRC-32 using the standard polynomial 0x04C11DB7 (x32 + x26 + x23 + x22 + x16 +
x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1). The CRC-32 unit retrieves 32-bit of data at a time from the
block of data to compute the polynomial. This computation takes 1 cycle. For instance, the CRC-32 calculation
for 1KB block of data is 256 cycles, 1 cycle for each of the 256 32-bit chunks. The initial value for the CRC-32
computation can be configured using BGCRC_SEED.
After the CRC-32 calculation is complete for a data block, the final result is loaded into BGCRC_RESULT.
Note that BGCRC_RESULT only contains the final calculation for the whole data block; intermediate 32-bit
calculations do not update BGCRC_RESULT. The value in BGCRC_RESULT is compared against the value in
BGCRC_GOLDEN by hardware and the NMI/Interrupt flags are set accordingly by the CRC notification unit.
Once CRC-32 calculation is commenced, the calculation can be halted by setting BGCRC_CTRL2.TEST_HALT
to 1010. Clearing this bit resumes CRC-32 calculation from the halt point.

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9.2.3 CRC Notification Unit

After the CRC-32 compute unit completes the CRC-32 calculation for a block of data or fails to complete the
calculation within BGCRC_WD_MIN and BGCRC_WD_MAX, if configured, the CRC-32 compute unit sends out
a NMI/Interrupt on the occurrence of a pass or fail. In addition, during a data read by the data read unit, if an
ECC or parity error occurs, the CRC notification unit can send out a NMI/Interrupt. In the case of an ECC or
parity error, the BGCRC stops operation and BGCRC_CURR_ADDR contains the memory address that caused
the ECC or parity error. The contents of BGCRC_CURR_ADDR in addition to the NMI/Interrupt flags can be
used to debug a BGCRC failure.
9.2.3.1 CPU Interrupt, CLA Task and NMI
The BGCRC module has configurable interrupt and NMI lines. NMIs are enabled by default but can be disabled
by writing 0xA to BGCRC_CTRL1.NMIDIS register. Conversely, all interrupts are disabled by default but can be
enabled by writing 0x7E to BGCRC_INTEN register. When an error occurs in the BGCRC, the BGCRC can be
configured to generate an NMI or interrupt. Since NMIs are enabled by default, all BGCRC errors cause an NMI.
Figure 9-3 and Figure 9-4 show the NMI and Interrupt lines, respectively.

Figure 9-3. BGCRC NMI

Figure 9-4. BGCRC Interrupt

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9.2.4 Operating Modes

BGCRC module supports two modes of operation: CRC mode and scrub mode. The mode of operation can be
configured by clearing or setting the register BGCRC_CTRL2.SCRUB_MODE.
9.2.4.1 CRC Mode
In CRC mode, the BGCRC module operates as explained in Section 9.2.2. CRC-32 calculation is performed on
a block of data and the result compared against a golden value. ECC and parity errors are checked in this mode.
Result mismatch, ECC or parity error can trigger an NMI/Interrupt.
9.2.4.2 Scrub Mode
In scrub mode, the CRC-32 result is not compared against the golden value and BGCRC_RESULT register is
not updated. ECC and parity errors are also checked in this mode. However unlike CRC mode, NMI/Interrupt are
only from ECC or parity error. In scrub mode, Parity and ECC bits of the memory block need to be initialized by
the CPU and/or CLA.
9.2.5 BGCRC Watchdog
The BGCRC module has an embedded windowed watchdog that is used as a diagnostic to check memory
test completion within the expected time window. This can protect against hardware defects that can cause the
memory check not to complete in the allotted time, which can not be caught by the system watchdog as the error
can be due to the CLA or DMA having continuous access. Windowing also helps detect additional failure modes
in the watchdog operation, for example, stuck watchdog.
The BGCRC watchdog is enabled by default and starts when the BGCRC module begins reading from memory.
The watchdog can be disabled using the register BGCRC_WD_CFG.WDDIS. The BGCRC watchdog counter
is a 32-bit counter with the value reflected in BGCRC_WD_CNT register. The lower and upper window
settings are configured using BGCRC_WD_MIN and BGCRC_WD_MAX, respectively. BGCRC_WD_MIN and
BGCRC_WD_MAX need to be configured before the test is started and can not be changed while the BGCRC is
operating. If configured, an NMI or interrupt is triggered if the memory test fails to complete within the configured
time window. The counter stops on completion of the CRC-32 check done, CRC-32 check failure and ECC/Parity
errors. The counter is reset when the next memory check begins.
The BGCRC watchdog can be halted by configuring the BGCRC_WD_CFG.WDDIS register. After the watchdog
resumes from being halted, the counter starts counting from the previous count unless a new memory check
operation is initiated. The counter is not halted when CRC-32 computation halts but by default halts during
a debug halt. The behavior of the watchdog during emulation can be changed by configuring the appropriate
BGCRC registers. In addition, due to the changing nature of memory contents during emulation, it is not
recommended to run BGCRC during emulation. CRC-32 computation continues during a watchdog failure and
software needs to address this condition.
9.2.6 Hardware and Software Faults Protection
The configuration registers are protected using a lock and commit configuration. Each of the configuration
registers can be individually locked and committed. The register once locked, can no longer be updated until the
lock is removed. However if the register lock is committed, no further writes is permitted until the device is reset.
It is recommended to lock the registers after configuration to protect against corruption due to software faults. In
addition, registers critical to the module functionality and fault detection are implemented using multi-bit fields to
protect against hardware faults.
9.3 Application of the BGCRC
This section contains use case scenarios of how the BGCRC module can be configured to test a block of
memory. However, the use case scenarios presented are for reference only and do not cover all the possible
application scenarios. These use case scenarios could be used as a starting point to configure the BGCRC
module for specific applications.

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9.3.1 Software Configuration

The configuration registers for the BGCRC can be split into three groups (see Table 9-1):
• CFG1: Registers that determine the operating mode and configured at the beginning.
• CFG2: Registers that need to be updated during kickoff of a new test.
• CFG3: Registers used for test and error management.

CFG1 registers are expected to be locked and committed after initial configuration. It is recommended to lock the
CFG2 and CFG3 registers after configuration. Figure 9-5 shows the BGCRC execution sequence.
Table 9-1. BGCRC Register Groups
CFG1 - One Time CFG2 - Periodic CFG3 - Registers Used for Test and Error
Configuration Registers Configuration Registers Management
BGCRC_CTRL1 BGCRC_EN BGCRC_NMICLR
BGCRC_WD_CFG BGCRC_CTRL2 BGCRC_INTCLR
BGCRC_INTEN BGCRC_START_ADDR BGCRC_NMIFRC
BGCRC_SEED BGCRC_GOLDEN BGCRC_INTFRC
BGCRC_WD_MIN
BGCRC_WD_MAX

Figure 9-5. BGCRC Execution Sequence Flow

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9.3.2 Decision on Error Response Severity

The error sources for BGCRC are:
• Test completion before BGCRC_WD_MIN.
• Test completed after BGCRC_WD_MAX.
• Mismatch between the calculated CRC and golden CRC.
• Uncorrectable error during data read (single bit error for parity memory or double bit error for ECC memory).
• Correctable error during memory read (single bit error for ECC memory).
Error severity can be chosen as either NMI or interrupt. By default, error severity is set to NMI. It is not possible
to configure error response for each individual error source. The response can be chosen as either interrupt or
NMI for all error sources. When error severity is chosen as NMI, ERROR_STS pin is asserted during an error.
CPU and CLA can be assigned the same error severity.
9.3.3 Decision of Controller for CLA_CRC
CPU_CRC can only be kicked off by the CPU. However, CLA_CRC can be kicked off by the CPU or CLA. If
BGCRC error severity is chosen as NMI, it is possible to handle the background test using the CLA and error
response with the CPU. Once the controller for BGCRC is chosen, it is possible to prevent accesses from other
controllers by using the system level access protection configuration.
9.3.4 Execution of Time Critical Code from Wait-Stated Memories
BGCRC access to functionally wait-stated memories is also wait-stated by the same number. Since it is
impossible to predict the next functional access, any ongoing BGCRC access has to complete before functional
access is granted. To mitigate delay in functional access, the BGCRC can be halted when time-critical code that
accesses the wait-stated memories is in progress. When BGCRC execution is halted, the BGCRC watchdog
is not halted. This is consistent with the safety requirement to complete the background test in a predictable
window irrespective of the user code. In such scenarios, it is recommended to adjust the upper BGCRC
watchdog window limit to account for the halt duration during functional access. However, if required, the
BGCRC watchdog can be disabled.
9.3.5 BGCRC Execution
Two notes about BGCRC execution are:
• BGCRC task can run as a background task once kicked off.
• BGCRC task does not impact functional execution for zero-wait stated memories. For memories with higher
wait-states, the BGCRC engine can be halted to make functional execution predictable.
Figure 9-6 shows a few examples of BGCRC execution sequences.

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Figure 9-6. BGCRC Execution Sequence Example

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9.3.6 Debug/Error Response for BGCRC Errors

The BGCRC error severity can be decoded by reading the BGCRC_INTFLG or BGCRC_NMIFLG. The errors
can be:
• WD_OVERFLOW/WD_UNDERFLOW: The test did not complete in the programmed window. System timing
needs to be checked to understand reason for non-completion of the test. BGCRC_CURR_ADDR and
BGCRC_WD_CNT indicate how far the test progressed.
• UNCORRECTABLE_ERR: BGCRC_CURR_ADDR contains the address of the memory location causing the
error. This error is due to single bit failure for Parity SRAM or double bit failure for ECC SRAM. The memory
location can be reloaded (if possible, for cases where code is copied from Flash) to see if the problem
resolves. If the problem persists, the problem can be a permanent defect.
• CORRECTABLE_ERR: This error is due to single bit failure for ECC SRAM. If the problem location is
accessed again (execution from the location for execute only memory or reading the location in other cases),
the expectation is that the single bit error is corrected. If the single bit error is not corrected, this can be an
indication of a permanent defect.
• CRC_FAIL: This indicates a failure in the computation of the CRC-32 value. This error does not occur in
scrub mode. For SRAMs with protection, in the absence of code bugs, this error is less likely since the
error is most often manifest as a correctable/uncorrectable error. Code bugs can cause failure if the code
inadvertently writes to a wrong address thus causing a CRC-32 error.

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9.3.7 BGCRC Golden CRC-32 Value Computation

The C28x is a little-endian, 16-bit word addressable CPU. Therefore, the 32-bit value of 0x12345678 stored at
address 0x100 is stored in the C28x memory as shown in Table 9-2.
Table 9-2. Data Address Location Example 1
Address 0x100 0x101
Data 0x5678 0x1234

The BGCRC order of byte calculations of the above example is 0x78, 0x56, 0x34, 0x12 and yields 0x6A330D2D.
The 32-bit polynomial 0x04C11DB7 is used with an initialization vector of 0x00000000. The following code
snippet shows the effective bit processing. Processing for all 32-bits within a word occurs in a single cycle within
the BGCRC hardware.

seed = 0x0UL; //Initialize With Seed

poly = 0x04C11DB7UL: //32-Bit Polynomial
crc32 = seed;

for(i=0; i<dataSize; i++)

{
byteSwappedData = ((data[i] & 0x000000FF) << 24)|
= ((data[i] & 0x0000FF00) << 8) |
= ((data[i] & 0x00FF0000) >> 8) |
= ((data[i] & 0xFF000000) >> 24);

crc32 = byteSwappedData^crc32;
for(j=0; j<32; j++)
{
if(crc32 & 0x80000000) crc32 = (crc32 << 1)^poly;
else crc32 = crc32 << 1;

crc32 = crc32 & 0xFFFFFFFF;

}
}

A second example (Table 9-3) with two 32-bit words, 0x12345678 and 0x9ABCDEF0 at address 0x100 and
0x102 successively, can calculate the bytes in the order 0x78, 0x56, 0x34, 0x12, 0xDE, 0xBC, and 0x9A and
yield 0x7E0B4164.
Table 9-3. Data Address Location Example 2
Address 0x100 0x101 0x102 0x103
Data 0x5678 0x1234 0xDEF0 0x9ABC

All data input to the BGCRC must align to a 32-bit boundary, both in the starting address and the size. It is
possible to include 16-bit data within the span of data; however, when the data is read by the BGCRC, it always
assume 32-bits and conform to the above calculation order. For example, if two 16-bit words (0xA0B1 and
0xC2D3) were placed in between the previous two 32-bit words (Table 9-4), the calculations can be performed
in byte order 0x78, 0x56, 0x34, 0x12, 0xB1, 0xA0, 0xD3, 0xC2, 0xF0, 0xDE, 0xBC, and 0x9A and yield
0x2AEFD987.
Table 9-4. Data Address Location Example 3
Address 0x100 0x101 0x102 0x103 0x104 0x105
Data 0x5678 0x1234 0xA0B1 0xC2D3 0xDEF0 0x9ABC

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9.4 Software
9.4.1 BGCRC Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/bgcrc
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
9.4.1.1 BGCRC CPU Interrupt Example
FILE: bgcrc_ex1_cpuinterrupt.c
This example demonstrates how to configure and trigger BGCRC from the CPU. BGCRC module is configured
for 1 KB of GS0 RAM which is programmed with a known data. The pre-computed CRC value is used as the
golden CRC value. Interrupt is generated once the computation is done and checks if no error flags are raised
Calculation uses the 32-bit polynomial 0x04C11DB7 and seed value 0x00000000.
External Connections
• None.
Watch Variables
• pass - This can be 1.
• runStatus - BGCRC running status. This is BGCRC_ACTIVE if the module is running, BGCRC_IDLE if the
module is idle.
9.4.1.2 BGCRC Example with Watchdog and Lock
FILE: bgcrc_ex2_cpubgcrc_basic.c
This example demonstrates how to configure and trigger BGCRC from the CPU. It also showcases how to
configure the CRC watchdog and lock the registers after configuring the module. The watchdog is used as a
diagnostic to check memory test completion within the expected time window. An error signal is generated if the
test does not complete in the specified time window.
The module is configured for 1kB of GS0 RAM which is programmed with random data. The golden CRC value
for comparison is computed using software method. Interrupt is generated once the computation is done and
checks if no error flags are raised. The NMI is enabled and is triggered if an error is detected.
External Connections
• None.
Watch Variables
• pass
• bgcrcDone
9.4.1.3 CLA-BGCRC Example in CRC mode
FILE: bgcrc_ex3_clabgcrc_crcmode.c
This example demonstrates how to configure and trigger CLABGCRC from the CPU. It also showcases how to
configure the CRC watchdog and lock the registers after configuring the module. The watchdog is used as a
diagnostic to check memory test completion within the expected time window. An error signal is generated if the
test does not complete in the specified time window.
The module is configured for 1kB of CLA ROM memory. The golden CRC value for comparison is computed
using software method. Interrupt is generated once the computation is done and checks if no error flags are
raised. The NMI is enabled and is triggered if an error is detected.
External Connections
• None.
Watch Variables

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• pass
• bgcrcDone
9.4.1.4 CLA-BGCRC Example in Scrub mode mode
FILE: bgcrc_ex4_clabgcrc_scrubmode.c
This example demonstrates how to configure and trigger CLA-BGCRC in Scrub mode. In Scrub mode, CRC of
data is not compared with the golden CRC. Error check is done using the ECC/Parity logic. It also showcases
how to configure the CRC watchdog and lock the registers after configuring the module. The watchdog is used
as a diagnostic to check memory test completion within the expected time window. An error signal is generated if
the test does not complete in the specified time window.
The module is configured for 256 bytes of CLA ROM memory. Interrupt is generated once the computation is
done and checks if no error flags are raised. The NMI is enabled and is triggered if an error is detected.
External Connections
• None.
Watch Variables
• pass
• bgcrcDone
9.5 BGCRC Registers
This section describes the Background CRC registers.
9.5.1 BGCRC Base Address Table
Table 9-5. BGCRC Base Address Table
Bit Field Name
DriverLib Name Base Address CPU1 DMA HIC CLA Pipeline Protected
Instance Structure
BGCRC_CPU_BAS
BgcrcCpuRegs BGCRC_REGS 0x0000_6340 YES - - - YES
E
BGCRC_CLA1_BA
BgcrcCla1Regs BGCRC_REGS 0x0000_6380 YES - - YES YES
SE

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9.5.2 BGCRC_REGS Registers

Table 9-6 lists the memory-mapped registers for the BGCRC_REGS registers. All register offset addresses not
listed in Table 9-6 should be considered as reserved locations and the register contents should not be modified.
Table 9-6. BGCRC_REGS Registers
Offset Acronym Register Name Write Protection Section
0h BGCRC_EN BGCRC Enable EALLOW Go
2h BGCRC_CTRL1 BGCRC Control register 1 EALLOW Go
4h BGCRC_CTRL2 BGCRC Control register 2 EALLOW Go
6h BGCRC_START_ADDR Start address for the BGCRC check EALLOW Go
8h BGCRC_SEED Seed for CRC calculation EALLOW Go
Eh BGCRC_GOLDEN Golden CRC to be compared against EALLOW Go
10h BGCRC_RESULT CRC calculated Go
12h BGCRC_CURR_ADDR Current address regsiter Go
1Ch BGCRC_WD_CFG BGCRC windowed watchdog configuration EALLOW Go
1Eh BGCRC_WD_MIN BGCRC windowed watchdog min value EALLOW Go
20h BGCRC_WD_MAX BGCRC windowed watchdog max value EALLOW Go
22h BGCRC_WD_CNT BGCRC windowed watchdog count Go
2Ah BGCRC_NMIFLG BGCRC NMI flag register Go
2Ch BGCRC_NMICLR BGCRC NMI flag clear register EALLOW Go
2Eh BGCRC_NMIFRC BGCRC NMI flag force register EALLOW Go
34h BGCRC_INTEN Interrupt enable EALLOW Go
36h BGCRC_INTFLG Interrupt flag Go
38h BGCRC_INTCLR Interrupt flag clear EALLOW Go
3Ah BGCRC_INTFRC Interrupt flag force EALLOW Go
3Ch BGCRC_LOCK BGCRC register map lockconfiguration EALLOW Go
3Eh BGCRC_COMMIT BGCRC register map commit configuration EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 9-7 shows the codes that are used for
access types in this section.
Table 9-7. BGCRC_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables

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Table 9-7. BGCRC_REGS Access Type Codes

(continued)
Access Type Code Description
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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9.5.2.1 BGCRC_EN Register (Offset = 0h) [Reset = 0h]

BGCRC_EN is shown in Figure 9-7 and described in Table 9-8.
Return to the Summary Table.
BGCRC Enable
Figure 9-7. BGCRC_EN Register
31 30 29 28 27 26 25 24
RUN_STS RESERVED
R-0h R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED START
R-0-0h R-0/W-0h

Table 9-8. BGCRC_EN Register Field Descriptions

Bit Field Type Reset Description
31 RUN_STS R 0h Status bit:
0 : CRC module is IDLE
1 : CRC module is Active
This bit will remain set during BGCRC_CTRL2.TEST_HALT = 1
Reset type: CPUx.SYSRSn
30-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3-0 START R-0/W 0h Start Bit:
"1010": Kick-off CRC calculations
"any other value": ignored
Notes:
BGCRC_WD_CNT regsters will be reset CRCEN.START = "1010".
BGCRC_INTFLG, BGCRC_NMIFLG will not be impacted by this
configuration.
This bit should not be set before the previous CRC computation
completes.
Reset type: CPUx.SYSRSn

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9.5.2.2 BGCRC_CTRL1 Register (Offset = 2h) [Reset = 0h]

BGCRC_CTRL1 is shown in Figure 9-8 and described in Table 9-9.
Return to the Summary Table.
BGCRC Control register 1
Figure 9-8. BGCRC_CTRL1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED NMIDIS
R-0-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED FREE_SOFT RESERVED
R-0-0h R/W-0h R-0-0h

Table 9-9. BGCRC_CTRL1 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19-16 NMIDIS R/W 0h 1010 : NMI is disabled
Any other value : NMI is enabled.
Reset type: CPUx.SYSRSn
15-5 RESERVED R-0 0h Reserved
4 FREE_SOFT R/W 0h Emulation control bit : This bit controls behaviour of CRC calculation
during emulation
0 : Soft, CRC module and CRC Watchdog stops immediately on
DEBUG SUSPEND (of CRC-controller ).
1 : Free, CRC calcuation and CRC watchdog is not affected by
DEBUG HALT (of CRC-controller )
Reset type: CPUx.SYSRSn
3-0 RESERVED R-0 0h Reserved

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9.5.2.3 BGCRC_CTRL2 Register (Offset = 4h) [Reset = 0h]

BGCRC_CTRL2 is shown in Figure 9-9 and described in Table 9-10.
Return to the Summary Table.
BGCRC Control register 2
Figure 9-9. BGCRC_CTRL2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED SCRUB_MODE
R-0-0h R/W-0h

15 14 13 12 11 10 9 8
TEST_HALT RESERVED BLOCK_SIZE
R/W-0h R-0-0h R/W-0h

7 6 5 4 3 2 1 0
BLOCK_SIZE
R/W-0h

Table 9-10. BGCRC_CTRL2 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19-16 SCRUB_MODE R/W 0h Scrub mode configuration
1010 : Scrub mode, CRC of data is not compared with the golden
CRC. Error check is done using the ECC/Parity logic.
Any other value: CRC value is compared with golden CRC at the end
in addition to the data correctness check by ECC/Parity logic.
Notes:
1010 configuration is used for scrub mode (for data memories)
where the memory value is read and ECC/Parity logic is used for
the error detection. BGCRC_RESULT.CRC_VALUE is not updated in
this configuration.
Reset type: CPUx.SYSRSn
15-12 TEST_HALT R/W 0h Halt Bit :
1010 : Module operation is stopped
Any other value : CRC calaculation will continue/resume from where
it was halted
Notes:
BGCRC_EN.START = 1010 configuration with TEST_HALT = 1010
will halt the CRC calculation. The new check will resume when
TEST_HALT is configured to a value other than 1010
Reset type: CPUx.SYSRSn
11-10 RESERVED R-0 0h Reserved
9-0 BLOCK_SIZE R/W 0h Configures the block size for the check
0x0 : 256 Byte (default)
0x1 : 512 Byte
0x2 : 768 Byte
0x3 : 1KB
...
0x3FF : 256KB
(0xn : (n+1)*256Byte)
Reset type: CPUx.SYSRSn

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9.5.2.4 BGCRC_START_ADDR Register (Offset = 6h) [Reset = 0h]

BGCRC_START_ADDR is shown in Figure 9-10 and described in Table 9-11.
Return to the Summary Table.
Start address for the BGCRC check
Figure 9-10. BGCRC_START_ADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
START_ADDRESS
R/W-0h

Table 9-11. BGCRC_START_ADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 START_ADDRESS R/W 0h START_ADDRESS indicates the start point of the test.
(For CPU_CRC, this will be the CPU address. For CLA_CRC, this
will be the CLA address where the memory is mapped)
Reset type: CPUx.SYSRSn

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9.5.2.5 BGCRC_SEED Register (Offset = 8h) [Reset = 0h]

BGCRC_SEED is shown in Figure 9-11 and described in Table 9-12.
Return to the Summary Table.
Seed for CRC calculation
Figure 9-11. BGCRC_SEED Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEED
R/W-0h

Table 9-12. BGCRC_SEED Register Field Descriptions

Bit Field Type Reset Description
31-0 SEED R/W 0h Initial value of CRC, this value is coiped to the CRC register on
triggering CRC calculation by writing to START bit.
Reset type: CPUx.SYSRSn

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9.5.2.6 BGCRC_GOLDEN Register (Offset = Eh) [Reset = 0h]

BGCRC_GOLDEN is shown in Figure 9-12 and described in Table 9-13.
Return to the Summary Table.
Golden CRC to be compared against
Figure 9-12. BGCRC_GOLDEN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_VALUE
R/W-0h

Table 9-13. BGCRC_GOLDEN Register Field Descriptions

Bit Field Type Reset Description
31-0 CRC_VALUE R/W 0h Golden CRC register:
If CRC check is enabled, the calcuated CRC value is compared with
golden CRC and status is updated.
Reset type: CPUx.SYSRSn

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9.5.2.7 BGCRC_RESULT Register (Offset = 10h) [Reset = 0h]

BGCRC_RESULT is shown in Figure 9-13 and described in Table 9-14.
Return to the Summary Table.
CRC calculated
Figure 9-13. BGCRC_RESULT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_VALUE
R-0h

Table 9-14. BGCRC_RESULT Register Field Descriptions

Bit Field Type Reset Description
31-0 CRC_VALUE R 0h CRC result register
This reister value will be updated only on the completion
of CRC check on a block of data as programmed by
BGCRC_CTRL2.BLOCK_SIZE.
Reset type: CPUx.SYSRSn

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9.5.2.8 BGCRC_CURR_ADDR Register (Offset = 12h) [Reset = 0h]

BGCRC_CURR_ADDR is shown in Figure 9-14 and described in Table 9-15.
Return to the Summary Table.
Current address regsiter
Figure 9-14. BGCRC_CURR_ADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRENT_ADDR
R-0h

Table 9-15. BGCRC_CURR_ADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 CURRENT_ADDR R 0h Current address from where the data is fetched.
During a failure, the CURRENT_ADDR field indicates the value from
where the last fetch happened.
Reset type: CPUx.SYSRSn

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9.5.2.9 BGCRC_WD_CFG Register (Offset = 1Ch) [Reset = 0h]

BGCRC_WD_CFG is shown in Figure 9-15 and described in Table 9-16.
Return to the Summary Table.
BGCRC windowed watchdog configuration
Figure 9-15. BGCRC_WD_CFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED WDDIS
R-0-0h R/W-0h

Table 9-16. BGCRC_WD_CFG Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3-0 WDDIS R/W 0h 1010: CRC Watchdog counter is disabled.
Any other value: CRC watchdog is enabled
Watchdog is an upcounter and starts counting when
BGCRC_EN.START is asserted. Watchdog continues to count during
TEST_HALT state also(BGCRC_CTRL2.TEST_HALT = "1010").
CRC watchdog can be disabled during TEST_HALT by explicit
configuration. (BGCRC_WD_CFG.WDDIS = 1010). Once the
watchdog is disabled and re-enabled, watchdog count resumes from
the previous disabled point.
Reset type: CPUx.SYSRSn

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9.5.2.10 BGCRC_WD_MIN Register (Offset = 1Eh) [Reset = 0h]

BGCRC_WD_MIN is shown in Figure 9-16 and described in Table 9-17.
Return to the Summary Table.
BGCRC windowed watchdog min value
Figure 9-16. BGCRC_WD_MIN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MINVAL
R/W-0h

Table 9-17. BGCRC_WD_MIN Register Field Descriptions

Bit Field Type Reset Description
31-0 MINVAL R/W 0h If the CRC computation completes before
BGCRC_WD_MIN.MINVAL FAIL_STATUS.WD_UNDERFLOW flag
gets set.
Reset type: CPUx.SYSRSn

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9.5.2.11 BGCRC_WD_MAX Register (Offset = 20h) [Reset = FFFFFFFFh]

BGCRC_WD_MAX is shown in Figure 9-17 and described in Table 9-18.
Return to the Summary Table.
BGCRC windowed watchdog max value
Figure 9-17. BGCRC_WD_MAX Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAXVAL
R/W-FFFFFFFFh

Table 9-18. BGCRC_WD_MAX Register Field Descriptions

Bit Field Type Reset Description
31-0 MAXVAL R/W FFFFFFFFh If the CRC computation doesn't complete before
BGCRC_WD_MIN.MAXVAL FAIL_STATUS.WD_OVERFLOW flag
gets set.
Reset type: CPUx.SYSRSn

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9.5.2.12 BGCRC_WD_CNT Register (Offset = 22h) [Reset = 0h]

BGCRC_WD_CNT is shown in Figure 9-18 and described in Table 9-19.
Return to the Summary Table.
BGCRC windowed watchdog count
Figure 9-18. BGCRC_WD_CNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WD_CNT
R-0h

Table 9-19. BGCRC_WD_CNT Register Field Descriptions

Bit Field Type Reset Description
31-0 WD_CNT R 0h CRC windowed watchdog counter value
Counter value freezes at the end of CRC computation and will
be reloaded only by BGCRC_EN.START = "1010" configuration.
BGCRC_WD_CNT register freezes when a failure occurs.
Reset type: CPUx.SYSRSn

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9.5.2.13 BGCRC_NMIFLG Register (Offset = 2Ah) [Reset = 0h]

BGCRC_NMIFLG is shown in Figure 9-19 and described in Table 9-20.
Return to the Summary Table.
BGCRC NMI flag register
Figure 9-19. BGCRC_NMIFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL RESERVED RESERVED
W OW E_ERR BLE_ERR
R-0-0h R-0h R-0h R-0h R-0h R-0h R-0-0h R-0-0h

Table 9-20. BGCRC_NMIFLG Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R 0h Windowed watchdog Overflow.
1 : Test did not complete before BGCRC_WD_MAX.MAXVAL
0 : No such errors
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R 0h Windowed watchdog underflow.
1 : Test completed before BGCRC_WD_MIN.MINVAL
0 : No such errors
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R 0h Correctable error indication:
0 : No ECC correctable error during memory read
1 : Correctable ECC error during memory read
Note: ECC computation is done during every memory read.
(Correctable errors are not ignored since the module doesn't write-
back corrected value. The error remains in the memory and required
corrective action need to be taken by CPU/CLA as part of ISR)
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R 0h Uncorrectable error indication:
0 : No ECC-uncorrectable/Parity error during memory read
1 : ECC-uncorrectable/Parity error during memory read
Note: ECC/Parity check is done during every memory read.
Reset type: CPUx.SYSRSn
2 CRC_FAIL R 0h CRC FAIL interrupt
0 : No failure in CRC check.
1 : CRC check failure
Note: Comparion is enabled only after CRC calc is completed
Reset type: CPUx.SYSRSn
1 RESERVED R-0 0h Reserved
0 RESERVED R-0 0h Reserved

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9.5.2.14 BGCRC_NMICLR Register (Offset = 2Ch) [Reset = 0h]

BGCRC_NMICLR is shown in Figure 9-20 and described in Table 9-21.
Return to the Summary Table.
BGCRC NMI flag clear register
Figure 9-20. BGCRC_NMICLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL RESERVED RESERVED
W OW E_ERR BLE_ERR
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0-0h R-0-0h

Table 9-21. BGCRC_NMICLR Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R-0/W1S 0h Clear WD_OVERFLOW NMI flag
0 No effect
1 Clears NMI flag
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R-0/W1S 0h Clear WD_UNDERFLOW NMI flag
0 No effect
1 Clears NMI flag
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R-0/W1S 0h Clear CORRECTABLE_ERR NMI flag
0 No effect
1 Clears NMI flag
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R-0/W1S 0h Clear UNCORRECTABLE_ERROR NMI flag
0 No effect
1 Clears NMI flag
Reset type: CPUx.SYSRSn
2 CRC_FAIL R-0/W1S 0h Clear CRC_FAIL NMI flag
0 No effect
1 Clears NMI flag
Reset type: CPUx.SYSRSn
1 RESERVED R-0 0h Reserved
0 RESERVED R-0 0h Reserved

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9.5.2.15 BGCRC_NMIFRC Register (Offset = 2Eh) [Reset = 0h]

BGCRC_NMIFRC is shown in Figure 9-21 and described in Table 9-22.
Return to the Summary Table.
BGCRC NMI flag force register
Figure 9-21. BGCRC_NMIFRC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL RESERVED RESERVED
W OW E_ERR BLE_ERR
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0-0h R-0-0h

Table 9-22. BGCRC_NMIFRC Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R-0/W1S 0h Force WD_OVERFLOW NMI flag
0 No effect
1 force NMI flag
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R-0/W1S 0h Force WD_UNDERFLOW NMI flag
0 No effect
1 force NMI flag
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R-0/W1S 0h Force CORRECTABLE_ERR NMI flag
0 No effect
1 force NMI flag
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R-0/W1S 0h Force UNCORRECTABLE_ERR NMI flag
0 No effect
1 force NMI flag
Reset type: CPUx.SYSRSn
2 CRC_FAIL R-0/W1S 0h Force CRC_FAIL NMI flag
0 No effect
1 force NMI flag
Reset type: CPUx.SYSRSn
1 RESERVED R-0 0h Reserved
0 RESERVED R-0 0h Reserved

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9.5.2.16 BGCRC_INTEN Register (Offset = 34h) [Reset = 0h]

BGCRC_INTEN is shown in Figure 9-22 and described in Table 9-23.
Return to the Summary Table.
Interrupt enable
Figure 9-22. BGCRC_INTEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL TEST_DONE RESERVED
W OW E_ERR BLE_ERR
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0-0h

Table 9-23. BGCRC_INTEN Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R 0h Reserved
6 WD_OVERFLOW R/W 0h 0 WD_OVERFLOW Interrupt disabled
1 WD_OVERFLOW Interrupt enabled
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R/W 0h 0 WD_UNDERFLOW Interrupt disabled
1 WD_UNDERFLOW Interrupt enabled
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R/W 0h 0 CORRECTABLE_ERR Interrupt disabled
1 CORRECTABLE_ERR Interrupt enabled
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R/W 0h 0 UNCORRECTABLE_ERR Interrupt disabled
1 UNCORRECTABLE_ERR Interrupt enabled
Reset type: CPUx.SYSRSn
2 CRC_FAIL R/W 0h 0 CRC_FAIL Interrupt disabled
1 CRC_FAIL Interrupt enabled
Reset type: CPUx.SYSRSn
1 TEST_DONE R/W 0h 0 TEST_DONE Interrupt disabled
1 TEST_DONE Interrupt enabled
Reset type: CPUx.SYSRSn
0 RESERVED R-0 0h Reserved

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9.5.2.17 BGCRC_INTFLG Register (Offset = 36h) [Reset = 0h]

BGCRC_INTFLG is shown in Figure 9-23 and described in Table 9-24.
Return to the Summary Table.
Interrupt flag
Figure 9-23. BGCRC_INTFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL TEST_DONE INT
W OW E_ERR BLE_ERR
R-0-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 9-24. BGCRC_INTFLG Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R 0h Windowed watchdog Overflow.
1 : Test did not completed before BGCRC_WD_MAX.MAXVAL
0 : No such errors
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R 0h Windowed watchdog underflow.
1 : Test completed before BGCRC_WD_MIN.MINVAL
0 : No such errors
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R 0h Correctable error indication:
0 : No ECC correctable error during memory read
1 : Correctable ECC error during memory read
Note: ECC computation is done during every memory read.
(Correctable errors are not ignored since the module doesn't write-
back corrected value. The error remains in the memory and required
corrective action need to be taken by CPU/CLA as part of ISR)
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R 0h uncorrectable error indication:
0 : No ECC-uncorrectable/Parity error during memory read
1 : ECC-uncorrectable/Parity error during memory read
Note: ECC/Parity check is done during every memory read.
Reset type: CPUx.SYSRSn
2 CRC_FAIL R 0h CRC fail interrupt
0 : No failure of CRC check
1 : CRC check failure
Note: Comparion is enabled only after CRC calc is completed
Reset type: CPUx.SYSRSn
1 TEST_DONE R 0h Done Interrupt Status flag
0 CRC calculation is in progress or CRC module is idle.
1 CRC calculation is done.
Note: TEST_DONE flag will get set on CRC calculation completion
even in case of CRC mismatch
Reset type: CPUx.SYSRSn

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Table 9-24. BGCRC_INTFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INT R 0h Global Interrupt Status flag
0 No interrupt generated
1 Interrupt was generated
Reset type: CPUx.SYSRSn

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9.5.2.18 BGCRC_INTCLR Register (Offset = 38h) [Reset = 0h]

BGCRC_INTCLR is shown in Figure 9-24 and described in Table 9-25.
Return to the Summary Table.
Interrupt flag clear
Figure 9-24. BGCRC_INTCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL TEST_DONE INT
W OW E_ERR BLE_ERR
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 9-25. BGCRC_INTCLR Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
2 CRC_FAIL R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
1 TEST_DONE R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
0 INT R-0/W1S 0h Global Interrupt Clear
0 No effect
1 Clears the interrupt flag and enables further interrupts to be
generated if an event flags is set to 1.
Reset type: CPUx.SYSRSn

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9.5.2.19 BGCRC_INTFRC Register (Offset = 3Ah) [Reset = 0h]

BGCRC_INTFRC is shown in Figure 9-25 and described in Table 9-26.
Return to the Summary Table.
Interrupt flag force
Figure 9-25. BGCRC_INTFRC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL TEST_DONE RESERVED
W OW E_ERR BLE_ERR
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0-0h

Table 9-26. BGCRC_INTFRC Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
2 CRC_FAIL R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
1 TEST_DONE R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
0 RESERVED R-0 0h Reserved

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9.5.2.20 BGCRC_LOCK Register (Offset = 3Ch) [Reset = 0h]

BGCRC_LOCK is shown in Figure 9-26 and described in Table 9-27.
Return to the Summary Table.
BGCRC register map lockconfiguration
Figure 9-26. BGCRC_LOCK Register
31 30 29 28 27 26 25 24
RESERVED RESERVED BGCRC_INTFR RESERVED RESERVED BGCRC_INTEN RESERVED RESERVED
C
R-0-0h R-0-0h R/W-0h R-0-0h R-0-0h R/W-0h R-0-0h R-0-0h

23 22 21 20 19 18 17 16
BGCRC_NMIF RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BGCRC_WD_M
RC AX
R/W-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R/W-0h

15 14 13 12 11 10 9 8
BGCRC_WD_M BGCRC_WD_C RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
IN FG
R/W-0h R/W-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h

7 6 5 4 3 2 1 0
BGCRC_GOLD RESERVED RESERVED BGCRC_SEED BGCRC_STAR BGCRC_CTRL BGCRC_CTRL BGCRC_EN
EN T_ADDR 2 1
R/W-0h R-0-0h R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 9-27. BGCRC_LOCK Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0 0h Reserved
30 RESERVED R-0 0h Reserved
29 BGCRC_INTFRC R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
28 RESERVED R-0 0h Reserved
27 RESERVED R-0 0h Reserved
26 BGCRC_INTEN R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
25 RESERVED R-0 0h Reserved
24 RESERVED R-0 0h Reserved
23 BGCRC_NMIFRC R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
22 RESERVED R-0 0h Reserved
21 RESERVED R-0 0h Reserved
20 RESERVED R-0 0h Reserved
19 RESERVED R-0 0h Reserved
18 RESERVED R-0 0h Reserved
17 RESERVED R-0 0h Reserved
16 BGCRC_WD_MAX R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn

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Table 9-27. BGCRC_LOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
15 BGCRC_WD_MIN R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
14 BGCRC_WD_CFG R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
13 RESERVED R-0 0h Reserved
12 RESERVED R-0 0h Reserved
11 RESERVED R-0 0h Reserved
10 RESERVED R-0 0h Reserved
9 RESERVED R-0 0h Reserved
8 RESERVED R-0 0h Reserved
7 BGCRC_GOLDEN R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
6 RESERVED R-0 0h Reserved
5 RESERVED R-0 0h Reserved
4 BGCRC_SEED R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
3 BGCRC_START_ADDR R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
2 BGCRC_CTRL2 R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
1 BGCRC_CTRL1 R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
0 BGCRC_EN R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn

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9.5.2.21 BGCRC_COMMIT Register (Offset = 3Eh) [Reset = 0h]

BGCRC_COMMIT is shown in Figure 9-27 and described in Table 9-28.
Return to the Summary Table.
BGCRC register map commit configuration
Figure 9-27. BGCRC_COMMIT Register
31 30 29 28 27 26 25 24
RESERVED RESERVED BGCRC_INTFR RESERVED RESERVED BGCRC_INTEN RESERVED RESERVED
C
R-0-0h R-0-0h R/WSonce-0h R-0-0h R-0-0h R/WSonce-0h R-0-0h R-0-0h

23 22 21 20 19 18 17 16
BGCRC_NMIF RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BGCRC_WD_M
RC AX
R/WSonce-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R/WSonce-0h

15 14 13 12 11 10 9 8
BGCRC_WD_M BGCRC_WD_C RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
IN FG
R/WSonce-0h R/WSonce-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h

7 6 5 4 3 2 1 0
BGCRC_GOLD RESERVED RESERVED BGCRC_SEED BGCRC_STAR BGCRC_CTRL BGCRC_CTRL BGCRC_EN
EN T_ADDR 2 1
R/WSonce-0h R-0-0h R-0-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 9-28. BGCRC_COMMIT Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0 0h Reserved
30 RESERVED R-0 0h Reserved
29 BGCRC_INTFRC R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
28 RESERVED R-0 0h Reserved
27 RESERVED R-0 0h Reserved
26 BGCRC_INTEN R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
25 RESERVED R-0 0h Reserved
24 RESERVED R-0 0h Reserved
23 BGCRC_NMIFRC R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
22 RESERVED R-0 0h Reserved
21 RESERVED R-0 0h Reserved
20 RESERVED R-0 0h Reserved
19 RESERVED R-0 0h Reserved
18 RESERVED R-0 0h Reserved

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Table 9-28. BGCRC_COMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
17 RESERVED R-0 0h Reserved
16 BGCRC_WD_MAX R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
15 BGCRC_WD_MIN R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
14 BGCRC_WD_CFG R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
13 RESERVED R-0 0h Reserved
12 RESERVED R-0 0h Reserved
11 RESERVED R-0 0h Reserved
10 RESERVED R-0 0h Reserved
9 RESERVED R-0 0h Reserved
8 RESERVED R-0 0h Reserved
7 BGCRC_GOLDEN R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
6 RESERVED R-0 0h Reserved
5 RESERVED R-0 0h Reserved
4 BGCRC_SEED R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
3 BGCRC_START_ADDR R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
2 BGCRC_CTRL2 R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
1 BGCRC_CTRL1 R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
0 BGCRC_EN R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn

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9.5.3 BGCRC Registers to Driverlib Functions

Table 9-29. BGCRC Registers to Driverlib Functions
File Driverlib Function
EN
bgcrc.h BGCRC_start
bgcrc.h BGCRC_getRunStatus
CTRL1
bgcrc.h BGCRC_setConfig
CTRL2
bgcrc.h BGCRC_setRegion
bgcrc.h BGCRC_halt
bgcrc.h BGCRC_resume
START_ADDR
bgcrc.h BGCRC_setRegion
SEED
bgcrc.h BGCRC_setSeedValue
GOLDEN
bgcrc.h BGCRC_setGoldenCRCValue
RESULT
bgcrc.h BGCRC_getResult
CURR_ADDR
bgcrc.h BGCRC_getCurrentAddress
WD_CFG
bgcrc.h BGCRC_enableWatchdog
bgcrc.h BGCRC_disableWatchdog
WD_MIN
bgcrc.h BGCRC_setWatchdogWindow
WD_MAX
bgcrc.h BGCRC_setWatchdogWindow
WD_CNT
bgcrc.h BGCRC_getWatchdogCounterValue
NMIFLG
bgcrc.h BGCRC_getNMIStatus
NMICLR
bgcrc.h BGCRC_clearNMIStatus
NMIFRC
bgcrc.h BGCRC_forceNMI
INTEN
bgcrc.h BGCRC_enableInterrupt
bgcrc.h BGCRC_disableInterrupt
INTFLG
bgcrc.h BGCRC_getInterruptStatus
INTCLR
bgcrc.h BGCRC_clearInterruptStatus
INTFRC
bgcrc.h BGCRC_forceInterrupt
LOCK

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Table 9-29. BGCRC Registers to Driverlib Functions (continued)

File Driverlib Function
bgcrc.h BGCRC_lockRegister
bgcrc.h BGCRC_unlockRegister
COMMIT
bgcrc.h BGCRC_commitRegisterLock

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Chapter 10
General-Purpose Input/Output (GPIO)

The GPIO module controls the device's digital and analog I/O multiplexing, which uses shared pins to maximize
application flexibility. The pins are named by their general-purpose I/O name (for example, GPIO0, GPIO25,
GPIO58). These pins can be individually selected to operate as digital I/O (also called GPIO mode), or
connected to one of several peripheral I/O signals. The input signals can be qualified to remove unwanted
noise.

10.1 Introduction...........................................................................................................................................................1064
10.2 Configuration Overview....................................................................................................................................... 1067
10.3 Digital Inputs on ADC Pins (AIOs)...................................................................................................................... 1067
10.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)...........................................................................................1068
10.5 Digital General-Purpose I/O Control................................................................................................................... 1068
10.6 Input Qualification................................................................................................................................................ 1071
10.7 GPIO and Peripheral Muxing............................................................................................................................... 1074
10.8 Internal Pullup Configuration Requirements..................................................................................................... 1079
10.9 Software................................................................................................................................................................ 1080
10.10 GPIO Registers................................................................................................................................................... 1081

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10.1 Introduction
Up to twelve independent peripheral signals are multiplexed on a single GPIO-enabled pin in addition to the
CPU-controlled I/O capability. Each pin output can be controlled by either a peripheral or one of the two CPU
masters.
• CPU1
• CPU1.CLA
There are up to 8 possible I/O ports:
• Port A consists of GPIO0-GPIO31
• Port B consists of GPIO32-GPIO63
• Port C consists of GPIO64-GPIO95
• Port D consists of GPIO96-GPIO127
• Port E consists of GPIO128-GPIO159
• Port F consists of GPIO160-GPIO191
• Port G consists of GPIO192-GPIO223
• Port H consists of GPIO224-GPIO255

Note
Some GPIO and I/O ports can be unavailable on particular devices. See the GPIO Registers section
for available GPIO and I/O ports.

The analog signals on this device are multiplexed with digital inputs and outputs. Some of these analog IO (AIO)
pins do not have digital output capability. Others of these pins are analog pins capable of full digital input and
output capability (AGPIO). Analog pins with AIO (digital input only) capability contain "AIO" signals in the Pin
Attributes table of the device data sheet. Analog pins with full input and output capability (AGPIO pins) contain
"GPIO" signals in the Pin Attributes table of the device data sheet. AGPIO pins also have pin names with both
analog signals and GPIO in the name.

Note
By default, all analog pins with digital input support shall come up in analog mode. To turn ON the
digital input functionality, GPHAMSEL register needs to be configured.

Figure 10-1 shows the GPIO logic for a single pin.

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00:00 Unused
00:01 Peripheral A
00:10 Peripheral B
CPU1 / CLA Input 00:11 Peripheral C
GPyDAT_R (R) GPyDAT (R) XBAR 01:00 Unused
01:01 Peripheral D
01:10 Peripheral E
Low Power CPU1 01:11 Peripheral F
CPU1 Mode Control
GPyCTRL GPyQSEL1-2 10:00 Unused
GPyPUD Pull-Up CPU1 10:01 Peripheral G
GPyINV 10:10 Peripheral H
SYSCLK 10:11 Peripheral I
Sync 00
3-sample 01 11:00 Unused
11:01 Peripheral J
0 6-sample 10
11:10 Peripheral K
Async 11 11:11 Peripheral L
GPIOx 1

CPU1 CLA
GPySET.1 GPySET.2
GPyCLEAR.1 GPyCLEAR.2
GPyTOGGLE.1 GPyTOGGLE.2
GPyDAT (W).1 GPyDAT (W).2

GPyGMUX1-2 : GPyMUX1-2 0 1 GPyCSEL

Direction GPyDIR
00:00 Data
00:01 Peripheral A
00:10 Peripheral B
Data 00:11 Peripheral C

01:00 GPIO (same as 00:00)

01:01 Peripheral D
CPU1 Enable and 01:10 Peripheral E
GPyODR Open Drain Direction 01:11 Peripheral F
Logic 10:00 GPIO (same as 00:00)
10:01 Peripheral G
10:10 Peripheral H
10:11 Peripheral I
11:00 GPIO (same as 00:00)
11:01 Peripheral J
11:10 Peripheral K
11:11 Peripheral L

Figure 10-1. GPIO Logic for a Single Pin

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There are two key features to note in Figure 10-1. The first is that the input and output paths are entirely
separate, connecting only at the pin. The second is that peripheral muxing takes place far from the pin. As a
result, it is always possible for both CPUs and CLAs to read the physical state of the pin independent of CPU
mastering and peripheral muxing. Likewise, external interrupts can be generated from peripheral activity. All pin
options such as input qualification and open-drain output are valid for all masters and peripherals. However, the
peripheral muxing, CPU muxing, and pin options can only be configured by CPU1. Table 10-1 provides details of
GPIO registers accessible by different masters.
Table 10-1. GPIO access by different controllers
Register Type Function CPU CLA DMA HIC Comments
GPIO_CTRL Peripheral muxing, Pull Control ,etc. Yes No No No -
Based on
GPIO_DATA GPIODAT, SET, CLEAR, TOGGLE, and pin status, etc. Yes Yes No No GPxCSEL
configuration.
GPIO_DATA_REA
Read back of GPIODAT register Yes Yes No Yes -
D

Note
JTAG uses a different signal path that does not support inversion or qualification.
GPIO18/X2 and GPIO19/X1 have different timings due to the load placed on them by the oscillator
circuit. For information on using GPIO18/X2 and GPIO19/X1 as GPIOs, see the device data sheet and
the Clocking section of this document.
If digital signals with sharp edges (high dv/dt) are connected to the AIOs or AGPIOs, cross-talk can
occur with adjacent analog signals. Therefore, limit the edge rate of signals connected to AIOs or
AGPIOs if adjacent channels are being used for analog functions.

10.1.1 GPIO Related Collateral

Foundational Materials
• C2000 Academy - GPIO

Getting Started Materials

• How to Maximize GPIO Usage in C2000 Devices Application Report
• [FAQ] C2000 GPIO FAQ

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10.2 Configuration Overview

I/O pin configuration consists of several steps:
1. Plan the device pin-out
Make a list of all required peripherals for the application. Using the peripheral mux information in the device
data manual, choose which GPIOs to use for the peripheral signals. Decide which of the remaining GPIOs to
use as inputs and outputs for each CPU and CLA.
Once the peripheral muxing has been chosen, muxing can be implemented by writing the appropriate values
to the GPyMUX1/2 and GPyGMUX1/2 registers. When changing the GPyGMUX value for a pin, always
set the corresponding GPyMUX bits to zero first to avoid glitching in the muxes. By default, all pins are
general-purpose I/Os, not peripheral signals, with the exception of GPIO35 and GPIO37.
2. (Optional) Enable internal pullup resistors
To enable or disable the pullup resistors, write to the appropriate bits in the GPIO pullup disable registers
(GPyPUD). All pullups are disabled by default. Pullups can be used to keep input pins in a known state when
there is no external signal driving them.
3. Select input qualification
If the pin is used as an input, specify the required input qualification, if any. The input qualification sampling
period is selected in the GPyCTRL registers, while the type of qualification is selected in the GPyQSEL1
and GPyQSEL2 registers. By default, all qualification is synchronous with a sampling period equal to
PLLSYSCLK, with the exception of GPIO35 and GPIO37. For an explanation of input qualification, see
Section 10.6.
4. Select the direction of any general-purpose I/O pins
For each pin configured as a GPIO, specify the direction of the pin as either input or output using the
GPyDIR registers. By default, all GPIO pins are inputs. Before changing a pin to an output, load the output
latch with the value to be driven by writing that value to the GPySET, GPyCLEAR, or GPyDAT registers.
Once the latch is loaded, write to GPyDIR to change the pin direction. By default, all output latches are zero.
The GPyDAT_R register can be used to read what value was written to the GPyDAT register.
5. Select low-power mode wake-up sources
GPIOs 0-63 can be used to wake the system up from low power modes. To select one or more GPIOs for
wake-up, write to the appropriate bits in the GPIOLPMSEL0 and GPIOLPMSEL1 registers. These registers
are part of the CPU system register space. For more information on low-power modes and GPIO wake-up,
see the Low-Power Modes section in the System Control and Interrupts chapter.
6. Select external interrupt sources
Configuring external interrupts is a two-step process. First, the interrupts themselves must be enabled and
their polarity must be configured using the XINTnCR registers. Second, the XINT1-5 GPIO pins must be set
by selecting the sources for Input X-BAR signals 4, 5, 6, 13, and 14, respectively. For more information on
the Input X-BAR architecture, see the Crossbar (X-BAR) chapter.

10.3 Digital Inputs on ADC Pins (AIOs)

Some GPIOs are multiplexed with analog pins and only have digital input functionality. These are also referred to
as AIOs. Pins with only an AIO option on this port can only function in input mode. See the device data sheet for
list of AIO signals. By default, these pins function as analog pins and the GPIOs are in a high-impedance state.
The GPyAMSEL register is used to configure these pins for digital or analog operation.

Note
If digital signals with sharp edges (high dv/dt) are connected to the AIOs, cross-talk can occur with
adjacent analog signals. Therefore, limit the edge rate of signals connected to AIOs if adjacent
channels are being used for analog functions.

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10.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)

Some GPIOs on this device are multiplexed with analog pins. These are also referred to as AGPIOs. Unlike
AIOs, AGPIOs have full input and output capability. This device has two GPIOs (GPIO20 and GPIO21) that offer
this feature on the 100-pin PZ and 80-pin PN packages.
100-Pin PZ: On this package, there are dedicated pins for B5 (pin 32) and B11 (pin 30) that also have AIO252
and AIO251 functionality, respectively. In addition, GPIO20 (pin 48) and GPIO21 (pin 49) are also available as
B5 and B11, respectively. Since B5 and B11 are dedicated pins on this package, it is recommended to use them
instead of the pins on GPIO20/21.
80-Pin PN: On this package, GPIO20 (pin 33) and GPIO21 (pin 34) are also available as B5 and B11,
respectively. There are no dedicated pin for B5 and B11.
By default, the AGPIOs are not connected and have to be configured. Table 10-2 shows how to configure the
AGPIOs using B5 (pin 32) and GPIO20 (pin 48) on the 100-pin PZ as an example.
Table 10-2. AGPIO Configuration
AGPIOCTRLA.bit. GPAAMSEL.bit. GPHAMSEL.bit. B5 Connected To GPIO20 Connected To
GPIO20 GPIO20 GPIO252 ADC GPIO20 AIO252 ADC GPIO20 AIO252
0 0 1 Yes - - - Yes -
0 1 1 Yes - - - - -
1 0 1 Yes - - - Yes -
1 1 1 - - - Yes - -
0 0 0 Yes - Yes - Yes -
0 1 0 Yes - Yes - - -
1 0 0 Yes - Yes - Yes -
1 1 0 - - Yes Yes - -

Note
If digital signals with sharp edges (high dv/dt) are connected to the AGPIOs, cross-talk can occur with
adjacent analog signals. The user can therefore limit the edge rate of signals connected to AGPIOs, if
adjacent channels are being used for analog functions.

10.5 Digital General-Purpose I/O Control

The values on the pins that are configured as GPIO can be changed by using the following registers.
• GPyDAT Registers
Each I/O port has one data register. Each bit in the data register corresponds to one GPIO pin. No matter
how the pin is configured (GPIO or peripheral function), the corresponding bit in the data register reflects the
current state of the pin after qualification. Writing to the GPyDAT register clears or sets the corresponding
output latch and if the pin is enabled as a general-purpose output (GPIO output), the pin is also driven either
low or high. If the pin is not configured as a GPIO output, then the value is latched but the pin is not driven.
Only if the pin is later configured as a GPIO output is the latched value driven onto the pin.
When using the GPyDAT register to change the level of an output pin, be cautious to not accidentally change
the level of another pin. For example, to change the output latch level of GPIOA1 by writing to the GPADAT
register bit 0 using a read-modify-write instruction, a problem can occur if another I/O port A signal changes
level between the read and the write stage of the instruction. Following is an analysis of why this happens:
The GPyDAT registers reflect the state of the pin, not the latch. This means the register reflects the actual
pin value. However, there is a lag between when the register is written to when the new pin value is reflected
back in the register. This can pose a problem when this register is used in subsequent program statements to
alter the state of GPIO pins. An example is shown below where two program statements attempt to drive two
different GPIO pins that are currently low to a high state.

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If Read-Modify-Write operations are used on the GPyDAT registers, because of the delay between the output
and the input of the first instruction (I1), the second instruction (I2) reads the old value and writes the value
back.

GpioDataRegs.GPADAT.bit.GPIO1 = 1; //I1 performs read-modify-write of GPADAT

GpioDataRegs.GPADAT.bit.GPIO2 = 1; //I2 also a read-modify-write of GPADAT
//GPADAT gets the old value of GPIO1 due to the delay

The second instruction waits for the first to finish the write due to the write-followed-by-read protection on this
peripheral frame. There is some lag, however, between the write of (I1) and the GPyDAT bit reflecting the
new value (1) on the pin. During this lag, the second instruction reads the old value of GPIO1 (0) and writes
the value back along with the new value of GPIO2 (1). Therefore, GPIO1 pin stays low.
One answer is to put some NOPs between instructions. A better answer is to use the GPySET/GPyCLEAR/
GPyTOGGLE registers instead of the GPyDAT registers. These registers always read back a 0 and writes of
0 have no effect. Only bits that need to be changed can be specified without disturbing any other bits that are
currently in the process of changing.
• GPyDAT_R Registers
The GPyDAT_R registers are read only registers which return the value written to the GPyDAT registers
instead of pin status. Writes to these registers have no effect.

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• GPySET Registers
The set registers are used to drive specified GPIO pins high without disturbing other pins. Each I/O port has
one set register and each bit corresponds to one GPIO pin. The set registers always read back 0. If the
corresponding pin is configured as an output, then writing a 1 to that bit in the set register sets the output
latch high and the corresponding pin is driven high. If the pin is not configured as a GPIO output, then the
value is latched but the pin is not driven. Only if the pin is later configured as a GPIO output is the latched
value driven onto the pin. Writing a 0 to any bit in the set registers has no effect.
• GPyCLEAR Registers
The clear registers are used to drive specified GPIO pins low without disturbing other pins. Each I/O port
has one clear register. The clear registers always read back 0. If the corresponding pin is configured as a
general-purpose output, then writing a 1 to the corresponding bit in the clear register clears the output latch
and the pin is driven low. If the pin is not configured as a GPIO output, then the value is latched but the pin is
not driven. Only if the pin is later configured as a GPIO output is the latched value driven onto the pin. Writing
a 0 to any bit in the clear registers has no effect.
• GPyTOGGLE Registers
The toggle registers are used to drive specified GPIO pins to the opposite level without disturbing other pins.
Each I/O port has one toggle register. The toggle registers always read back 0. If the corresponding pin is
configured as an output, then writing a 1 to that bit in the toggle register flips the output latch and pulls the
corresponding pin in the opposite direction. That is, if the output pin is driven low, then writing a 1 to the
corresponding bit in the toggle register pulls the pin high. Likewise, if the output pin is high, then writing a 1
to the corresponding bit in the toggle register pulls the pin low. If the pin is not configured as a GPIO output,
then the value is latched but the pin is not driven. Only if the pin is later configured as a GPIO output is the
latched value driven onto the pin. Writing a 0 to any bit in the toggle registers has no effect.

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10.6 Input Qualification

The input qualification scheme has been designed to be very flexible. Select the type of input qualification for
each GPIO pin by configuring the GPyQSEL1 and GPyQSEL2 registers. In the case of a GPIO input pin, the
qualification can be specified as only synchronized to SYSCLKOUT or qualification by a sampling window. For
pins that are configured as peripheral inputs, the input can also be asynchronous in addition to synchronized to
SYSCLKOUT or qualified by a sampling window. The remainder of this section describes the options available.
10.6.1 No Synchronization (Asynchronous Input)
This mode is used for peripherals where input synchronization is not required or the peripheral itself performs the
synchronization. Examples include communication ports McBSP, SCI, SPI, and I2C. In addition, the ePWM trip
zone (TZn) signals can function independent of the presence of SYSCLKOUT.

Note
Using input synchronization when the peripheral itself performs the synchronization can cause
unexpected results. The user must make sure that the GPIO pin is configured for asynchronous in
this case.

10.6.2 Synchronization to SYSCLKOUT Only

This is the default qualification mode of all the pins at reset. In this mode, the input signal is only synchronized to
the system clock (SYSCLKOUT). Because the incoming signal is asynchronous, a SYSCLKOUT period of delay
is needed for the input to the device to be changed. No further qualification is performed on the signal.
10.6.3 Qualification Using a Sampling Window
In this mode, the signal is first synchronized to the system clock (SYSCLKOUT) and then qualified by a specified
number of cycles before the input is allowed to change. Figure 10-2 and Figure 10-3 show how the input
qualification is performed to eliminate unwanted noise. Two parameters are specified by the user for this type
of qualification: 1) the sampling period, or how often the signal is sampled, and 2) the number of samples to be
taken.
Time between samples

GPxCTRL Reg

GPIOx SYNC Qualification Input Signal

Qualified By 3
or 6 Samples

GPxQSEL1/2
SYSCLKOUT
Number of Samples

Figure 10-2. Input Qualification Using a Sampling Window

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Time between samples (sampling period):

To qualify the signal, the input signal is sampled at a regular period. The sampling period is specified by the user
and determines the time duration between samples, or how often the signal is sampled, relative to the CPU clock
(SYSCLKOUT).
The sampling period is specified by the qualification period (QUALPRDn) bits in the GPxCTRL register.
The sampling period is configurable in groups of 8 input signals. For example, GPIO0 to GPIO7 use
GPACTRL[QUALPRD0] setting and GPIO8 to GPIO15 use GPACTRL[QUALPRD1]. Table 10-3 and Table 10-4
show the relationship between the sampling period or sampling frequency and the GPxCTRL[QUALPRDn]
setting.
Table 10-3. Sampling Period
Sampling Period
If GPxCTRL[QUALPRDn] = 0 1 × TSYSCLKOUT
If GPxCTRL[QUALPRDn] ≠ 0 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT
Where TSYSCLKOUT is the period in time of SYSCLKOUT

Table 10-4. Sampling Frequency

Sampling Frequency
If GPxCTRL[QUALPRDn] = 0 fSYSCLKOUT
If GPxCTRL[QUALPRDn] ≠ 0 fSYSCLKOUT × 1 ÷ (2 × GPxCTRL[QUALPRDn])
Where fSYSCLKOUT is the frequency of SYSCLKOUT

From these equations, the minimum and maximum time between samples can be calculated for a given
SYSCLKOUT frequency:

Example: Maximum Sampling Frequency:

If GPxCTRL[QUALPRDn] = 0
then the sampling frequency is fSYSCLKOUT
If, for example, fSYSCLKOUT = 60 MHz
then the signal is sampled at 60 MHz or one sample every 16.67 ns.

Example: Minimum Sampling Frequency:

If GPxCTRL[QUALPRDn] = 0xFF (255)
then the sampling frequency is fSYSCLKOUT × 1 ÷ (2 × GPxCTRL[QUALPRDn])
If, for example, fSYSCLKOUT = 60 MHz
then the signal is sampled at 60 MHz × 1 ÷ (2 × 255) (117.647 kHz) or one sample every 8.5 μs.

Number of samples:
The number of times the signal is sampled is either three samples or six samples as specified in the qualification
selection (GPAQSEL1, GPAQSEL2, GPBQSEL1, and GPBQSEL2) registers. When three or six consecutive
cycles are the same, then the input change is passed through to the device.
Total Sampling Window Width:
The sampling window is the time during which the input signal is sampled as shown in Figure 10-3. By using the
equation for the sampling period, along with the number of samples to be taken, the total width of the window
can be determined.
For the input qualifier to detect a change in the input, the level of the signal must be stable for the duration of the
sampling window width or longer.

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The number of sampling periods within the window is always one less than the number of samples taken. For
a three-sample window, the sampling window width is two sampling periods wide where the sampling period is
defined in Table 10-3. Likewise, for a six-sample window, the sampling window width is five sampling periods
wide. Table 10-5 and Table 10-6 show the calculations used to determine the total sampling window width based
on GPxCTRL[QUALPRDn] and the number of samples taken.
Table 10-5. Case 1: Three-Sample Sampling Window Width
Total Sampling Window Width
If GPxCTRL[QUALPRDn] = 0 2 × TSYSCLKOUT
If GPxCTRL[QUALPRDn] ≠ 0 2 × 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT
Where TSYSCLKOUT is the period in time of SYSCLKOUT

Table 10-6. Case 2: Six-Sample Sampling Window Width

Total Sampling Window Width
If GPxCTRL[QUALPRDn] = 0 5 × TSYSCLKOUT
If GPxCTRL[QUALPRDn] ≠ 0 5 × 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT
Where TSYSCLKOUT is the period in time of SYSCLKOUT

Note
The external signal change is asynchronous with respect to both the sampling period and
SYSCLKOUT. Due to the asynchronous nature of the external signal, the input must be held stable for
a time greater than the sampling window width to make sure the logic detects a change in the signal.
The extra time required can be up to an additional sampling period + TSYSCLKOUT.
The required duration for an input signal to be stable for the qualification logic to detect a change is
described in the data manual.

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Example Qualification Window:

For the example shown in Figure 10-3, the input qualification has been configured as follows:
• GPxQSEL1/2 = 1,0. This indicates a six-sample qualification.
• GPxCTRL[QUALPRDn] = 1. The sampling period is tw(SP) = 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT = 2 x
TSYSCLKOUT.
This configuration results in the following:
• The width of the sampling window is:
tw(IQSW) = 5 × tw(SP) = 5 × 2 × GPxCTRL[QUALPRDn] × TSYSCLKOUT = 5 × 2 × TSYSCLKOUT
• If, for example, TSYSCLKOUT = 16.67 ns, then the duration of the sampling window is:
Sampling period, tw(SP) = 2 x TSYSCLKOUT = 2 x 16.67 ns = 33.3 ns
Sampling window, tw(IQSW) = 5 × tw(SP) = 5 × 33.3 ns = 166.7 ns
• To account for the asynchronous nature of the input relative to the sampling period and SYSCLKOUT, up to
a single additional sampling period and SYSCLK period is required to detect a change in the input signal. For
this example:
tw(IQSW) + tw(SP) + TSYSCLKOUT = 166.7 ns + 33.3 ns + 16.67 ns = 216.7 ns
• In Figure 10-3, the glitch (A) is shorter then the qualification window and is ignored by the input qualifier.

Figure 10-3. Input Qualifier Clock Cycles

10.7 GPIO and Peripheral Muxing

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10.7.1 GPIO Muxing

Up to twelve different peripheral functions are multiplexed to each pin along with a general-purpose input/output (GPIO) function. This allows you to
choose the peripheral mix and pinout that works best for your particular application. Refer to Table 10-7 for muxing combinations and definitions.
Table 10-7. GPIO Muxed Pins
0, 4, 8, 12 1 2 3 5 6 7 9 10 11 13 14 15 ALT
CLB_OUTPUTX
GPIO0 EPWM1_A I2CA_SDA SPIA_STE FSIRXA_CLK MCAN_RX EQEP1_INDEX HIC_D7 HIC_BASESEL1
BAR8
CLB_OUTPUTX FSITXA_TDM_
GPIO1 EPWM1_B I2CA_SCL SPIA_SOMI MCAN_TX HIC_A2 HIC_D10
BAR7 D1
GPIO2 EPWM2_A OUTPUTXBAR1 PMBUSA_SDA SPIA_SIMO SCIA_TX FSIRXA_D1 I2CB_SDA HIC_A1 CANA_TX HIC_D9
GPIO3 EPWM2_B OUTPUTXBAR2 OUTPUTXBAR2 PMBUSA_SCL SPIA_CLK SCIA_RX FSIRXA_D0 I2CB_SCL HIC_NOE CANA_RX HIC_D4
EQEP2_ CLB_OUTPUTX
GPIO4 EPWM3_A MCAN_TX OUTPUTXBAR3 CANA_TX SPIB_CLK FSIRXA_CLK HIC_BASESEL2 HIC_NWE
STROBE BAR6
CLB_OUTPUTX
GPIO5 EPWM3_B OUTPUTXBAR3 MCAN_RX CANA_RX SPIA_STE FSITXA_D1 HIC_A7 HIC_D4 HIC_D15
BAR5
CLB_OUTPUTX
GPIO6 EPWM4_A OUTPUTXBAR4 SYNCOUT EQEP1_A SPIB_SOMI FSITXA_D0 FSITXA_D1 HIC_NBE1 HIC_D14
BAR8
CLB_OUTPUTX
GPIO7 EPWM4_B OUTPUTXBAR5 EQEP1_B SPIB_SIMO FSITXA_CLK HIC_A6 HIC_D14
BAR2
EQEP1_ CLB_OUTPUTX FSITXA_TDM_
GPIO8 EPWM5_A ADCSOCAO SCIA_TX SPIA_SIMO I2CA_SCL FSITXA_D1 HIC_A0 HIC_D8
STROBE BAR5 CLK
GPIO9 EPWM5_B SCIB_TX OUTPUTXBAR6 EQEP1_INDEX SCIA_RX SPIA_CLK FSITXA_D0 LINB_RX HIC_BASESEL0 I2CB_SCL HIC_NRDY
FSITXA_TDM_ CLB_OUTPUTX
GPIO10 EPWM6_A ADCSOCBO EQEP1_A SCIB_TX SPIA_SOMI I2CA_SDA FSITXA_CLK LINB_TX HIC_NWE
D0 BAR4
GPIO11 EPWM6_B OUTPUTXBAR7 EQEP1_B SCIB_RX SPIA_STE FSIRXA_D1 LINB_RX EQEP2_A SPIA_SIMO HIC_D6 HIC_NBE0
EQEP1_
GPIO12 EPWM7_A MCAN_RX SCIB_TX PMBUSA_CTL FSIRXA_D0 LINB_TX SPIA_CLK CANA_RX HIC_D13 HIC_INT
STROBE
PMBUSA_
GPIO13 EPWM7_B MCAN_TX EQEP1_INDEX SCIB_RX FSIRXA_CLK LINB_RX SPIA_SOMI CANA_TX HIC_D11 HIC_D5
ALERT
CLB_OUTPUTX
GPIO14 EPWM8_A SCIB_TX I2CB_SDA OUTPUTXBAR3 PMBUSA_SDA SPIB_CLK EQEP2_A LINB_TX EPWM3_A HIC_D15
BAR7
CLB_OUTPUTX
GPIO15 EPWM8_B SCIB_RX I2CB_SCL OUTPUTXBAR4 PMBUSA_SCL SPIB_STE EQEP2_B LINB_RX EPWM3_B HIC_D12
BAR6
EQEP1_
GPIO16 SPIA_SIMO OUTPUTXBAR7 EPWM5_A SCIA_TX SD1_D1 PMBUSA_SCL XCLKOUT EQEP2_B SPIB_SOMI HIC_D1
STROBE
GPIO17 SPIA_SOMI OUTPUTXBAR8 EPWM5_B SCIA_RX SD1_C1 EQEP1_INDEX PMBUSA_SDA CANA_TX HIC_D2
FSITXA_TDM_
GPIO18 SPIA_CLK SCIB_TX CANA_RX EPWM6_A I2CA_SCL SD1_D2 EQEP2_A PMBUSA_CTL XCLKOUT LINB_TX HIC_INT X2
CLK
PMBUSA_ CLB_OUTPUTX FSITXA_TDM_
GPIO19 SPIA_STE SCIB_RX CANA_TX EPWM6_B I2CA_SDA SD1_C2 EQEP2_B LINB_RX HIC_NBE0 X1
ALERT BAR1 D0
GPIO20 EQEP1_A SPIB_SIMO SD1_D3 MCAN_TX
GPIO21 EQEP1_B SPIB_SOMI SD1_C3 MCAN_RX
EQEP1_ CLB_OUTPUTX
GPIO22 SCIB_TX SPIB_CLK SD1_D4 LINA_TX LINB_TX HIC_A5 EPWM4_A HIC_D13
STROBE BAR1
CLB_OUTPUTX
GPIO23 EQEP1_INDEX SCIB_RX SPIB_STE SD1_C4 LINA_RX LINB_RX HIC_A3 EPWM4_B HIC_D11
BAR3

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Table 10-7. GPIO Muxed Pins (continued)

0, 4, 8, 12 1 2 3 5 6 7 9 10 11 13 14 15 ALT
GPIO24 OUTPUTXBAR1 EQEP2_A EPWM8_A SPIB_SIMO SD2_D1 LINB_TX PMBUSA_SCL SCIA_TX ERRORSTS HIC_D3
GPIO25 OUTPUTXBAR2 EQEP2_B EQEP1_A SPIB_SOMI SD2_C1 FSITXA_D1 PMBUSA_SDA SCIA_RX HIC_BASESEL0
GPIO26 OUTPUTXBAR3 EQEP2_INDEX OUTPUTXBAR3 SPIB_CLK SD2_D2 FSITXA_D0 PMBUSA_CTL I2CA_SDA HIC_D0 HIC_A1
EQEP2_ PMBUSA_
GPIO27 OUTPUTXBAR4 OUTPUTXBAR4 SPIB_STE SD2_C2 FSITXA_CLK I2CA_SCL HIC_D1 HIC_A4
STROBE ALERT
EQEP2_
GPIO28 SCIA_RX EPWM7_A OUTPUTXBAR5 EQEP1_A SD2_D3 LINA_TX SPIB_CLK ERRORSTS I2CB_SDA HIC_NOE
STROBE
AUX
GPIO29 SCIA_TX EPWM7_B OUTPUTXBAR6 EQEP1_B SD2_C3 EQEP2_INDEX LINA_RX SPIB_STE ERRORSTS I2CB_SCL HIC_NCS
CLKIN
EQEP1_
GPIO30 CANA_RX SPIB_SIMO OUTPUTXBAR7 SD2_D4 FSIRXA_CLK MCAN_RX EPWM1_A HIC_D8
STROBE
GPIO31 CANA_TX SPIB_SOMI OUTPUTXBAR8 EQEP1_INDEX SD2_C4 FSIRXA_D1 MCAN_TX EPWM1_B HIC_D10
GPIO32 I2CA_SDA SPIB_CLK EPWM8_B LINA_TX SD1_D2 FSIRXA_D0 CANA_TX PMBUSA_SDA ADCSOCBO HIC_INT
GPIO33 I2CA_SCL SPIB_STE OUTPUTXBAR4 LINA_RX SD1_C2 FSIRXA_CLK CANA_RX EQEP2_B ADCSOCAO SD1_C1 HIC_D0
GPIO34 OUTPUTXBAR1 PMBUSA_SDA HIC_NBE1 I2CB_SDA HIC_D9
GPIO35 SCIA_RX I2CA_SDA CANA_RX PMBUSA_SCL LINA_RX EQEP1_A PMBUSA_CTL EPWM5_B SD2_C1 HIC_NWE TDI
PMBUSA_
GPIO37 OUTPUTXBAR2 I2CA_SCL SCIA_TX CANA_TX LINA_TX EQEP1_B HIC_NRDY TDO
ALERT
CLB_OUTPUTX
GPIO39 MCAN_RX FSIRXA_CLK EQEP2_INDEX SYNCOUT EQEP1_INDEX HIC_D7
BAR2
GPIO40 SPIB_SIMO EPWM2_B PMBUSA_SDA FSIRXA_D0 SCIB_TX EQEP1_A LINB_TX HIC_NBE1 HIC_D5
GPIO41 EPWM2_A PMBUSA_SCL FSIRXA_D1 SCIB_RX EQEP1_B LINB_RX HIC_A4 SPIB_SOMI HIC_D12
EQEP1_ CLB_OUTPUTX
GPIO42 LINA_RX OUTPUTXBAR5 PMBUSA_CTL I2CA_SDA HIC_D2 HIC_A6
STROBE BAR3
PMBUSA_ PMBUSA_ CLB_OUTPUTX
GPIO43 OUTPUTXBAR6 I2CA_SCL EQEP1_INDEX SD2_D3 HIC_D3 HIC_A7
ALERT ALERT BAR4
CLB_OUTPUTX
GPIO44 OUTPUTXBAR7 EQEP1_A PMBUSA_SDA FSITXA_CLK PMBUSA_CTL FSIRXA_D0 HIC_D7 LINB_TX HIC_D5
BAR3
PMBUSA_ CLB_OUTPUTX
GPIO45 OUTPUTXBAR8 FSITXA_D0 SD2_C3 HIC_D6
ALERT BAR4
GPIO46 LINA_TX MCAN_TX FSITXA_D1 PMBUSA_SDA SD2_C4 HIC_NWE
CLB_OUTPUTX FSITXA_TDM_
GPIO47 LINA_RX MCAN_RX PMBUSA_SCL SD2_D4 HIC_A6
BAR2 CLK
GPIO48 OUTPUTXBAR3 CANA_TX SCIA_TX SD1_D1 PMBUSA_SDA HIC_A7
GPIO49 OUTPUTXBAR4 CANA_RX SCIA_RX SD1_C1 LINA_RX SD2_D1 FSITXA_D0 HIC_D2
GPIO50 EQEP1_A MCAN_TX SPIB_SIMO SD1_D2 I2CB_SDA SD2_D2 FSITXA_D1 HIC_D3
GPIO51 EQEP1_B MCAN_RX SPIB_SOMI SD1_C2 I2CB_SCL SD2_D3 FSITXA_CLK HIC_D6
EQEP1_ CLB_OUTPUTX
GPIO52 SPIB_CLK SD1_D3 SYNCOUT SD2_D4 FSIRXA_D0 HIC_NWE
STROBE BAR5
CLB_OUTPUTX
GPIO53 EQEP1_INDEX SPIB_STE SD1_C3 ADCSOCAO CANA_RX SD1_C1 FSIRXA_D1
BAR6
FSITXA_TDM_
GPIO54 SPIA_SIMO EQEP2_A OUTPUTXBAR2 SD1_D4 ADCSOCBO LINB_TX SD1_C2 FSIRXA_CLK
D1
GPIO55 SPIA_SOMI EQEP2_B OUTPUTXBAR3 SD1_C4 ERRORSTS LINB_RX SD1_C3 HIC_A0

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Table 10-7. GPIO Muxed Pins (continued)

0, 4, 8, 12 1 2 3 5 6 7 9 10 11 13 14 15 ALT
CLB_OUTPUTX EQEP2_
GPIO56 SPIA_CLK MCAN_TX SCIB_TX SD2_D1 SPIB_SIMO I2CA_SDA EQEP1_A SD1_C4 FSIRXA_D1 HIC_D6
BAR7 STROBE
CLB_OUTPUTX
GPIO57 SPIA_STE MCAN_RX EQEP2_INDEX SCIB_RX SD2_C1 SPIB_SOMI I2CA_SCL EQEP1_B FSIRXA_CLK HIC_D4
BAR8
EQEP1_
GPIO58 OUTPUTXBAR1 SPIB_CLK SD2_D2 LINA_TX CANA_TX SD2_C2 FSIRXA_D0 HIC_NRDY
STROBE
FSITXA_TDM_
GPIO59 OUTPUTXBAR2 SPIB_STE SD2_C2 LINA_RX CANA_RX EQEP1_INDEX SD2_C3
D1
GPIO60 MCAN_TX OUTPUTXBAR3 SPIB_SIMO SD2_D3 SD2_C4 HIC_A0
GPIO61 MCAN_RX OUTPUTXBAR4 SPIB_SOMI SD2_C3 CANA_RX
AIO228 SD2_C1 HIC_A0
AIO226 SD2_D4 HIC_A1
AIO242 SD2_D2 HIC_A2
AIO224 SD2_D3 HIC_A3
AIO233 SD2_D1 HIC_A4
AIO229
AIO239 SD1_D1 HIC_A5
AIO237 SD1_D2 HIC_A6
AIO244 SD1_D3 HIC_A7
AIO232 SD1_D4 HIC_BASESEL0
AIO231 SD1_C1 HIC_BASESEL1
AIO238 SD2_C3 HIC_NCS
AIO248
AIO251
AIO245 SD1_C2 HIC_NOE
AIO252 SD2_C4
AIO241 SD2_C1 HIC_NBE1
AIO249
AIO225 SD2_C2 HIC_NWE
AIO240 SD2_C1 HIC_NBE1
AIO227 SD1_C3 HIC_NBE0
AIO236
AIO230 SD1_C4 HIC_BASESEL2
AIO253
AIO247

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10.7.2 Peripheral Muxing

For example, multiplexing for the GPIO6 pin is controlled by writing to GPAGMUX[13:12] and GPAMUX[13:12].
By writing to these bits, GPIO6 is configured as either a general-purpose digital I/O or one of several different
peripheral functions. An example of GPyGMUX and GPyMUX selection and options for a single GPIO are shown
in Table 10-8.

Note
The table below is for example only. GPIO6 may not be available on this device. If GPIO6 is available,
the functions mentioned in the table below may not match the actual functions available. Please see
the GPIO Muxing section of this document for correct list of GPIOs and corresponding mux options for
this device.

Table 10-8. GPIO and Peripheral Muxing

GPAGMUX1[13:12] GPAMUX1[13:12] Pin Functionality
00 00 GPIO6
00 01 Peripheral 1
00 10 Peripheral 2
00 11 Peripheral 3
01 00 GPIO6
01 01 Peripheral 4
01 10 Peripheral 5
01 11
10 00 GPIO6
10 01
10 10 Peripheral 6
10 11 Peripheral 7
11 00 GPIO6
11 01 Peripheral 8
11 10 Peripheral 9
11 11 Peripheral 10

The devices have different multiplexing schemes. If a peripheral is not available on a particular device, that mux
selection is reserved on that device and can not be used.

CAUTION
If a reserved GPIO mux configuration that is not mapped to either a peripheral or GPIO mode is
selected, the state of the pin is undefined and the pin is driven. Unimplemented configurations are
for future expansion and must not be selected. In the device mux table (see the data manual), these
options are indicated as Reserved or left blank.

Some peripherals can be assigned to more than one pin by way of the mux registers. For example,
OUTPUTXBAR1 can be assigned to GPIOs p, q, or r (where p, q, and r are example GPIO numbers), depending
on individual system requirements. An example of this is shown in Table 10-9.

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Note
The table below is for example only. Bit ranges may not correspond to OUTPUTXBAR1 on this device.
Please see the GPIO Muxing section of this document for correct list of GPIOs and corresponding
mux options for this device.

If none or more then one of the GPIO pins is configured as peripheral input pins, then that GPIO is set to a
hard-wired default value.
Table 10-9. Peripheral Muxing (Multiple Pins Assigned)
GMUX Configuration MUX Configuration
Choice 1: GPIOp GPyGMUX1[5:4]=01 GPyMUX1[5:4]=01
or Choice 2: GPIOq GPyGMUX2[17:16]=00 GPyMUX2[17:16]=01
or Choice 3: GPIOr GPyGMUX1[7:6]=01 GPyMUX1[7:6]=01

10.8 Internal Pullup Configuration Requirements

On reset, GPIOs are in input mode and have the internal pullups disabled. An un-driven input can float to a
mid-rail voltage and cause wasted shoot-through current on the input buffer. The user should always put each
GPIO in one of these configurations:
• Input mode and driven on the board by another component to a level above Vih or below Vil
• Input mode with GPIO internal pullup enabled
• Output mode
On devices with lesser pin count packages, pull-ups on unbonded GPIOs are by default enabled to prevent
floating inputs. The user should take care to avoid disabling these pullups in their application code.
On devices with larger pin count packages, the pullups for any internally unbonded GPIO must be
enabled to prevent floating inputs. TI has provided functions in controlSUITE/C2000Ware which users
can call to enable the pullup on any unbonded GPIO for the package they are using. This function,
GPIO_EnabledUnbondedIOPullups(), resides in the (Device)_Sysctrl.c file and is called by default from
InitSysCtrl(). The user should take care to avoid disabling these pullups in their application code.

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10.9 Software
10.9.1 GPIO Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/gpio
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
10.9.1.1 Device GPIO Setup
FILE: gpio_ex1_setup.c
Configures the device GPIO into two different configurations This code is verbose to illustrate how the GPIO
could be setup. In a real application, lines of code can be combined for improved code size and efficiency.
This example only sets-up the GPIO. Nothing is actually done with the pins after setup.
In general:
• All pullup resistors are enabled. For ePWMs this may not be desired.
• Input qual for communication ports (CAN, SPI, SCI, I2C) is asynchronous
• Input qual for Trip pins (TZ) is asynchronous
• Input qual for eCAP and eQEP signals is synch to SYSCLKOUT
• Input qual for some I/O's and __interrupts may have a sampling window
10.9.1.2 Device GPIO Toggle
FILE: gpio_ex2_toggle.c
Configures the device GPIO through the sysconfig file. The GPIO pin is toggled in the infinit loop.
10.9.1.3 Device GPIO Interrupt
FILE: gpio_ex3_interrupt.c
Configures the device GPIOs through the sysconfig file. One GPIO output pin, and one GPIO input pin is
configured. The example then configures the GPIO input pin to be the source of an external interrupt which
toggles the GPIO output pin.
10.9.1.4 External Interrupt (XINT)
FILE: gpio_ex4_aio_external_interrupt.c
In this example AIO pins are configured as digital inputs. Two other GPIO signals (connected externally to AIO
pins) are toggled in software to trigger external interrupt through AIO224 and AIO225 (AIO224 assigned to
XINT1 and AIO225 assigned to XINT2). The user is required to externally connect these signals for the program
to work properly. Each interrupt is fired in sequence: XINT1 first and then XINT2.
GPIO34 will go high outside of the interrupts and low within the interrupts. This signal can be monitored on a
scope.
ExternalConnections
• Connect GPIO30 to AIO224. AIO224 will be assigned to XINT1
• Connect GPIO31 to AIO225. AIO225 will be assigned to XINT2
• GPIO34 can be monitored on an oscilloscope
Watch Variables
• xint1Count for the number of times through XINT1 interrupt
• xint2Count for the number of times through XINT2 interrupt
• loopCount for the number of times through the idle loop
10.9.2 LED Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/led

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Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
10.9.2.1 LED Blinky Example
FILE: led_ex1_blinky.c
This example demonstrates how to blink a LED.
External Connections
• None.
Watch Variables
• None.
10.10 GPIO Registers
This section describes the General-Purpose Input/Output Registers.
10.10.1 GPIO Base Address Table
Table 10-10. GPIO Base Address Table
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 DMA HIC CLA
Instance Structure Protected

GPIO_CTRL_RE
GpioCtrlRegs GPIOCTRL_BASE 0x0000_7C00 YES - - - YES
GS
GPIO_DATA_RE
GpioDataRegs GPIODATA_BASE 0x0000_7F00 YES - - YES YES
GS
GPIO_DATA_REA GPIODATAREAD_BAS
GpioDataReadRegs 0x0000_7F80 YES - YES YES YES
D_REGS E

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10.10.2 GPIO_CTRL_REGS Registers

Table 10-11 lists the memory-mapped registers for the GPIO_CTRL_REGS registers. All register offset
addresses not listed in Table 10-11 should be considered as reserved locations and the register contents should
not be modified.
Table 10-11. GPIO_CTRL_REGS Registers
Offset Acronym Register Name Write Protection Section
0h GPACTRL GPIO A Qualification Sampling Period Control EALLOW Go
(GPIO0 to 31)
2h GPAQSEL1 GPIO A Qualifier Select 1 Register (GPIO0 to 15) EALLOW Go
4h GPAQSEL2 GPIO A Qualifier Select 2 Register (GPIO16 to EALLOW Go
31)
6h GPAMUX1 GPIO A Mux 1 Register (GPIO0 to 15) EALLOW Go
8h GPAMUX2 GPIO A Mux 2 Register (GPIO16 to 31) EALLOW Go
Ah GPADIR GPIO A Direction Register (GPIO0 to 31) EALLOW Go
Ch GPAPUD GPIO A Pull Up Disable Register (GPIO0 to 31) EALLOW Go
10h GPAINV GPIO A Input Polarity Invert Registers (GPIO0 to EALLOW Go
31)
12h GPAODR GPIO A Open Drain Output Register (GPIO0 to EALLOW Go
GPIO31)
14h GPAAMSEL GPIO A Analog Mode Select register (GPIO0 to EALLOW Go
GPIO31)
20h GPAGMUX1 GPIO A Peripheral Group Mux (GPIO0 to 15) EALLOW Go
22h GPAGMUX2 GPIO A Peripheral Group Mux (GPIO16 to 31) EALLOW Go
28h GPACSEL1 GPIO A Core Select Register (GPIO0 to 7) EALLOW Go
2Ah GPACSEL2 GPIO A Core Select Register (GPIO8 to 15) EALLOW Go
2Ch GPACSEL3 GPIO A Core Select Register (GPIO16 to 23) EALLOW Go
2Eh GPACSEL4 GPIO A Core Select Register (GPIO24 to 31) EALLOW Go
3Ch GPALOCK GPIO A Lock Configuration Register (GPIO0 to EALLOW Go
31)
3Eh GPACR GPIO A Lock Commit Register (GPIO0 to 31) EALLOW Go
40h GPBCTRL GPIO B Qualification Sampling Period Control EALLOW Go
(GPIO32 to 63)
42h GPBQSEL1 GPIO B Qualifier Select 1 Register (GPIO32 to EALLOW Go
47)
44h GPBQSEL2 GPIO B Qualifier Select 2 Register (GPIO48 to EALLOW Go
63)
46h GPBMUX1 GPIO B Mux 1 Register (GPIO32 to 47) EALLOW Go
48h GPBMUX2 GPIO B Mux 2 Register (GPIO48 to 63) EALLOW Go
4Ah GPBDIR GPIO B Direction Register (GPIO32 to 63) EALLOW Go
4Ch GPBPUD GPIO B Pull Up Disable Register (GPIO32 to 63) EALLOW Go
50h GPBINV GPIO B Input Polarity Invert Registers (GPIO32 EALLOW Go
to 63)
52h GPBODR GPIO B Open Drain Output Register (GPIO32 to EALLOW Go
GPIO63)
60h GPBGMUX1 GPIO B Peripheral Group Mux (GPIO32 to 47) EALLOW Go
62h GPBGMUX2 GPIO B Peripheral Group Mux (GPIO48 to 63) EALLOW Go
68h GPBCSEL1 GPIO B Core Select Register (GPIO32 to 39) EALLOW Go
6Ah GPBCSEL2 GPIO B Core Select Register (GPIO40 to 47) EALLOW Go
6Ch GPBCSEL3 GPIO B Core Select Register (GPIO48 to 55) EALLOW Go
6Eh GPBCSEL4 GPIO B Core Select Register (GPIO56 to 63) EALLOW Go

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Table 10-11. GPIO_CTRL_REGS Registers (continued)

Offset Acronym Register Name Write Protection Section
7Ch GPBLOCK GPIO B Lock Configuration Register (GPIO32 to EALLOW Go
63)
7Eh GPBCR GPIO B Lock Commit Register (GPIO32 to 63) EALLOW Go
1C0h GPHCTRL GPIO H Qualification Sampling Period Control EALLOW Go
(GPIO224 to 255)
1C2h GPHQSEL1 GPIO H Qualifier Select 1 Register (GPIO224 to EALLOW Go
239)
1C4h GPHQSEL2 GPIO H Qualifier Select 2 Register (GPIO240 to EALLOW Go
255)
1C6h GPHMUX1 GPIO H Mux 1 Register (GPIO224 to 239) EALLOW Go
1C8h GPHMUX2 GPIO H Mux 2 Register (GPIO240 to 255) EALLOW Go
1CCh GPHPUD GPIO H Pull Up Disable Register (GPIO224 to EALLOW Go
255)
1D0h GPHINV GPIO H Input Polarity Invert Registers (GPIO224 EALLOW Go
to 255)
1D4h GPHAMSEL GPIO H Analog Mode Select register (GPIO224 EALLOW Go
to GPIO255)
1E0h GPHGMUX1 GPIO H Peripheral Group Mux (GPIO224 to 239) EALLOW Go
1E2h GPHGMUX2 GPIO H Peripheral Group Mux (GPIO240 to 255) EALLOW Go
1E8h GPHCSEL1 GPIO H Core Select Register (GPIO224 to 231) EALLOW Go
1EAh GPHCSEL2 GPIO H Core Select Register (GPIO232 to 239) EALLOW Go
1ECh GPHCSEL3 GPIO H Core Select Register (GPIO240 to 247) EALLOW Go
1EEh GPHCSEL4 GPIO H Core Select Register (GPIO248 to 255) EALLOW Go
1FCh GPHLOCK GPIO H Lock Configuration Register (GPIO224 to EALLOW Go
255)
1FEh GPHCR GPIO H Lock Commit Register (GPIO224 to 255) EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 10-12 shows the codes that are used for
access types in this section.
Table 10-12. GPIO_CTRL_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.

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Table 10-12. GPIO_CTRL_REGS Access Type Codes

(continued)
Access Type Code Description
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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10.10.2.1 GPACTRL Register (Offset = 0h) [Reset = 0h]

GPACTRL is shown in Figure 10-4 and described in Table 10-13.
Return to the Summary Table.
GPIO A Qualification Sampling Period Control (GPIO0 to 31)
Figure 10-4. GPACTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QUALPRD3 QUALPRD2 QUALPRD1 QUALPRD0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-13. GPACTRL Register Field Descriptions

Bit Field Type Reset Description
31-24 QUALPRD3 R/W 0h Qualification sampling period for GPIO24 to GPIO31:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
23-16 QUALPRD2 R/W 0h Qualification sampling period for GPIO16 to GPIO23:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
15-8 QUALPRD1 R/W 0h Qualification sampling period for GPIO8 to GPIO15:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
7-0 QUALPRD0 R/W 0h Qualification sampling period for GPIO0 to GPIO7:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

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10.10.2.2 GPAQSEL1 Register (Offset = 2h) [Reset = 0h]

GPAQSEL1 is shown in Figure 10-5 and described in Table 10-14.
Return to the Summary Table.
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 10-5. GPAQSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-14. GPAQSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO15 R/W 0h Select input qualification type for GPIO15:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
29-28 GPIO14 R/W 0h Select input qualification type for GPIO14:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
27-26 GPIO13 R/W 0h Select input qualification type for GPIO13:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
25-24 GPIO12 R/W 0h Select input qualification type for GPIO12:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
23-22 GPIO11 R/W 0h Select input qualification type for GPIO11:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
21-20 GPIO10 R/W 0h Select input qualification type for GPIO10:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-14. GPAQSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 GPIO9 R/W 0h Select input qualification type for GPIO9:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
17-16 GPIO8 R/W 0h Select input qualification type for GPIO8:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
15-14 GPIO7 R/W 0h Select input qualification type for GPIO7:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
13-12 GPIO6 R/W 0h Select input qualification type for GPIO6:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
11-10 GPIO5 R/W 0h Select input qualification type for GPIO5:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
9-8 GPIO4 R/W 0h Select input qualification type for GPIO4:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
7-6 GPIO3 R/W 0h Select input qualification type for GPIO3:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
5-4 GPIO2 R/W 0h Select input qualification type for GPIO2:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
3-2 GPIO1 R/W 0h Select input qualification type for GPIO1:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
1-0 GPIO0 R/W 0h Select input qualification type for GPIO0:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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10.10.2.3 GPAQSEL2 Register (Offset = 4h) [Reset = 0h]

GPAQSEL2 is shown in Figure 10-6 and described in Table 10-15.
Return to the Summary Table.
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 10-6. GPAQSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-15. GPAQSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO31 R/W 0h Select input qualification type for GPIO31:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
29-28 GPIO30 R/W 0h Select input qualification type for GPIO30:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
27-26 GPIO29 R/W 0h Select input qualification type for GPIO29:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
25-24 GPIO28 R/W 0h Select input qualification type for GPIO28:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
23-22 GPIO27 R/W 0h Select input qualification type for GPIO27:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
21-20 GPIO26 R/W 0h Select input qualification type for GPIO26:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-15. GPAQSEL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 GPIO25 R/W 0h Select input qualification type for GPIO25:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
17-16 GPIO24 R/W 0h Select input qualification type for GPIO24:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
15-14 GPIO23 R/W 0h Select input qualification type for GPIO23:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
13-12 GPIO22 R/W 0h Select input qualification type for GPIO22:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
11-10 GPIO21 R/W 0h Select input qualification type for GPIO21:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
9-8 GPIO20 R/W 0h Select input qualification type for GPIO20:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
7-6 GPIO19 R/W 0h Select input qualification type for GPIO19:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
5-4 GPIO18 R/W 0h Select input qualification type for GPIO18:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
3-2 GPIO17 R/W 0h Select input qualification type for GPIO17:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
1-0 GPIO16 R/W 0h Select input qualification type for GPIO16:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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10.10.2.4 GPAMUX1 Register (Offset = 6h) [Reset = 0h]

GPAMUX1 is shown in Figure 10-7 and described in Table 10-16.
Return to the Summary Table.
GPIO A Mux 1 Register (GPIO0 to 15)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO. Refer to GPIO chapter for more details.
Figure 10-7. GPAMUX1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-16. GPAMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO15 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO14 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO13 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO12 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO11 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO10 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO9 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO8 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO7 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO6 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO5 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO4 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO3 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO2 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO1 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO0 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.10.2.5 GPAMUX2 Register (Offset = 8h) [Reset = 0h]

GPAMUX2 is shown in Figure 10-8 and described in Table 10-17.
Return to the Summary Table.
GPIO A Mux 2 Register (GPIO16 to 31)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO. Refer to GPIO chapter for more details.
Figure 10-8. GPAMUX2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-17. GPAMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO31 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO30 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO29 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO28 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO27 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO26 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO25 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO24 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO23 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO22 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO21 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO20 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO19 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO18 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO17 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO16 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.10.2.6 GPADIR Register (Offset = Ah) [Reset = 0h]

GPADIR is shown in Figure 10-9 and described in Table 10-18.
Return to the Summary Table.
GPIO A Direction Register (GPIO0 to 31)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 10-9. GPADIR Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-18. GPADIR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
30 GPIO30 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
29 GPIO29 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
28 GPIO28 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
27 GPIO27 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
26 GPIO26 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
25 GPIO25 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
24 GPIO24 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
23 GPIO23 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
22 GPIO22 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
21 GPIO21 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
20 GPIO20 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
19 GPIO19 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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Table 10-18. GPADIR Register Field Descriptions (continued)

Bit Field Type Reset Description
18 GPIO18 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
17 GPIO17 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
16 GPIO16 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
15 GPIO15 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
14 GPIO14 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
13 GPIO13 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
12 GPIO12 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
11 GPIO11 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
10 GPIO10 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
9 GPIO9 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
8 GPIO8 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
7 GPIO7 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
6 GPIO6 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
5 GPIO5 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
4 GPIO4 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
3 GPIO3 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
2 GPIO2 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
1 GPIO1 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
0 GPIO0 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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10.10.2.7 GPAPUD Register (Offset = Ch) [Reset = FFFFFFFFh]

GPAPUD is shown in Figure 10-10 and described in Table 10-19.
Return to the Summary Table.
GPIO A Pull Up Disable Register (GPIO0 to 31)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.
Figure 10-10. GPAPUD Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 10-19. GPAPUD Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
30 GPIO30 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
29 GPIO29 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
28 GPIO28 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
27 GPIO27 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
26 GPIO26 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
25 GPIO25 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
24 GPIO24 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
23 GPIO23 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
22 GPIO22 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
21 GPIO21 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
20 GPIO20 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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Table 10-19. GPAPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO19 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
18 GPIO18 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
17 GPIO17 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
16 GPIO16 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
15 GPIO15 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
14 GPIO14 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
13 GPIO13 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
12 GPIO12 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
11 GPIO11 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
10 GPIO10 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
9 GPIO9 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
8 GPIO8 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
7 GPIO7 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
6 GPIO6 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
5 GPIO5 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
4 GPIO4 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
3 GPIO3 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
2 GPIO2 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
1 GPIO1 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
0 GPIO0 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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10.10.2.8 GPAINV Register (Offset = 10h) [Reset = 0h]

GPAINV is shown in Figure 10-11 and described in Table 10-20.
Return to the Summary Table.
GPIO A Input Polarity Invert Registers (GPIO0 to 31)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 10-11. GPAINV Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-20. GPAINV Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
30 GPIO30 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
29 GPIO29 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
28 GPIO28 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
27 GPIO27 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
26 GPIO26 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
25 GPIO25 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
24 GPIO24 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
23 GPIO23 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
22 GPIO22 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
21 GPIO21 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
20 GPIO20 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
19 GPIO19 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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Table 10-20. GPAINV Register Field Descriptions (continued)

Bit Field Type Reset Description
18 GPIO18 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
17 GPIO17 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
16 GPIO16 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
15 GPIO15 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
14 GPIO14 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
13 GPIO13 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
12 GPIO12 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
11 GPIO11 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
10 GPIO10 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
9 GPIO9 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
8 GPIO8 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
7 GPIO7 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
6 GPIO6 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
5 GPIO5 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
4 GPIO4 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
3 GPIO3 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
2 GPIO2 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
1 GPIO1 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
0 GPIO0 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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10.10.2.9 GPAODR Register (Offset = 12h) [Reset = 0h]

GPAODR is shown in Figure 10-12 and described in Table 10-21.
Return to the Summary Table.
GPIO A Open Drain Output Register (GPIO0 to GPIO31)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes
out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 10-12. GPAODR Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-21. GPAODR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
30 GPIO30 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
29 GPIO29 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
28 GPIO28 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
27 GPIO27 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
26 GPIO26 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
25 GPIO25 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
24 GPIO24 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
23 GPIO23 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
22 GPIO22 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
21 GPIO21 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn

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Table 10-21. GPAODR Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO20 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
19 GPIO19 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
18 GPIO18 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
17 GPIO17 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
16 GPIO16 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
15 GPIO15 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
14 GPIO14 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
13 GPIO13 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
12 GPIO12 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
11 GPIO11 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
10 GPIO10 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
9 GPIO9 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
8 GPIO8 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
7 GPIO7 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
6 GPIO6 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
5 GPIO5 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
4 GPIO4 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
3 GPIO3 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
2 GPIO2 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
1 GPIO1 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
0 GPIO0 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn

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10.10.2.10 GPAAMSEL Register (Offset = 14h) [Reset = 00300000h]

GPAAMSEL is shown in Figure 10-13 and described in Table 10-22.
Return to the Summary Table.
GPIO A Analog Mode Select register (GPIO0 to GPIO31)
Selects between digital and analog functionality for GPIO pins.
0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other
GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For
all the IOs, the corresponding bits in these registers dont have any affect.
Figure 10-13. GPAAMSEL Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED GPIO21 GPIO20 RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-22. GPAAMSEL Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 RESERVED R/W 0h Reserved
28 RESERVED R/W 0h Reserved
27 RESERVED R/W 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23 RESERVED R/W 0h Reserved
22 RESERVED R/W 0h Reserved
21 GPIO21 R/W 1h Analog Mode select for this pin
Reset type: SYSRSn
20 GPIO20 R/W 1h Analog Mode select for this pin
Reset type: SYSRSn
19 RESERVED R/W 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15 RESERVED R/W 0h Reserved

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Table 10-22. GPAAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
14 RESERVED R/W 0h Reserved
13 RESERVED R/W 0h Reserved
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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10.10.2.11 GPAGMUX1 Register (Offset = 20h) [Reset = 0h]

GPAGMUX1 is shown in Figure 10-14 and described in Table 10-23.
Return to the Summary Table.
GPIO A Peripheral Group Mux (GPIO0 to 15)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 10-14. GPAGMUX1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-23. GPAGMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO15 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO14 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO13 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO12 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO11 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO10 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO9 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO8 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO7 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO6 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO5 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO4 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO3 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO2 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO1 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO0 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.10.2.12 GPAGMUX2 Register (Offset = 22h) [Reset = 0h]

GPAGMUX2 is shown in Figure 10-15 and described in Table 10-24.
Return to the Summary Table.
GPIO A Peripheral Group Mux (GPIO16 to 31)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 10-15. GPAGMUX2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-24. GPAGMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO31 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO30 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO29 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO28 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO27 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO26 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO25 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO24 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO23 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO22 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO21 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO20 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO19 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO18 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO17 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO16 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.10.2.13 GPACSEL1 Register (Offset = 28h) [Reset = 0h]

GPACSEL1 is shown in Figure 10-16 and described in Table 10-25.
Return to the Summary Table.
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-16. GPACSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO7 GPIO6 GPIO5 GPIO4
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-25. GPACSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO7 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO6 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO5 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO4 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO3 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO2 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO1 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO0 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.10.2.14 GPACSEL2 Register (Offset = 2Ah) [Reset = 0h]

GPACSEL2 is shown in Figure 10-17 and described in Table 10-26.
Return to the Summary Table.
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-17. GPACSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO15 GPIO14 GPIO13 GPIO12
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-26. GPACSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO15 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO14 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO13 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO12 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO11 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO10 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO9 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO8 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.10.2.15 GPACSEL3 Register (Offset = 2Ch) [Reset = 0h]

GPACSEL3 is shown in Figure 10-18 and described in Table 10-27.
Return to the Summary Table.
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-18. GPACSEL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-27. GPACSEL3 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO23 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO22 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO21 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO20 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO19 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO18 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO17 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO16 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.10.2.16 GPACSEL4 Register (Offset = 2Eh) [Reset = 0h]

GPACSEL4 is shown in Figure 10-19 and described in Table 10-28.
Return to the Summary Table.
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-19. GPACSEL4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO31 GPIO30 GPIO29 GPIO28
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-28. GPACSEL4 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO31 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO30 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO29 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO28 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO27 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO26 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO25 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO24 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.10.2.17 GPALOCK Register (Offset = 3Ch) [Reset = 0h]

GPALOCK is shown in Figure 10-20 and described in Table 10-29.
Return to the Summary Table.
GPIO A Lock Configuration Register (GPIO0 to 31)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1,
GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 10-20. GPALOCK Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-29. GPALOCK Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
30 GPIO30 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
29 GPIO29 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
28 GPIO28 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
27 GPIO27 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
26 GPIO26 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
25 GPIO25 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
24 GPIO24 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
23 GPIO23 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
22 GPIO22 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
21 GPIO21 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
20 GPIO20 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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Table 10-29. GPALOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO19 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
18 GPIO18 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
17 GPIO17 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
16 GPIO16 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
15 GPIO15 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
14 GPIO14 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
13 GPIO13 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
12 GPIO12 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
11 GPIO11 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
10 GPIO10 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
9 GPIO9 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
8 GPIO8 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
7 GPIO7 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
6 GPIO6 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
5 GPIO5 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
4 GPIO4 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
3 GPIO3 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
2 GPIO2 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
1 GPIO1 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
0 GPIO0 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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10.10.2.18 GPACR Register (Offset = 3Eh) [Reset = 0h]

GPACR is shown in Figure 10-21 and described in Table 10-30.
Return to the Summary Table.
GPIO A Lock Commit Register (GPIO0 to 31)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 10-21. GPACR Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 10-30. GPACR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
30 GPIO30 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
29 GPIO29 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
28 GPIO28 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
27 GPIO27 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
26 GPIO26 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
25 GPIO25 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
24 GPIO24 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
23 GPIO23 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
22 GPIO22 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
21 GPIO21 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
20 GPIO20 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
19 GPIO19 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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Table 10-30. GPACR Register Field Descriptions (continued)

Bit Field Type Reset Description
18 GPIO18 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
17 GPIO17 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
16 GPIO16 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
15 GPIO15 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
14 GPIO14 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
13 GPIO13 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
12 GPIO12 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
11 GPIO11 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
10 GPIO10 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
9 GPIO9 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
8 GPIO8 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
7 GPIO7 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
6 GPIO6 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
5 GPIO5 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
4 GPIO4 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
3 GPIO3 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
2 GPIO2 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
1 GPIO1 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
0 GPIO0 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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10.10.2.19 GPBCTRL Register (Offset = 40h) [Reset = 0h]

GPBCTRL is shown in Figure 10-22 and described in Table 10-31.
Return to the Summary Table.
GPIO B Qualification Sampling Period Control (GPIO32 to 63)
Figure 10-22. GPBCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QUALPRD3 QUALPRD2 QUALPRD1 QUALPRD0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-31. GPBCTRL Register Field Descriptions

Bit Field Type Reset Description
31-24 QUALPRD3 R/W 0h Qualification sampling period for GPIO56 to GPIO63:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
23-16 QUALPRD2 R/W 0h Qualification sampling period for GPIO48 to GPIO55:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
15-8 QUALPRD1 R/W 0h Qualification sampling period for GPIO40 to GPIO47:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn
7-0 QUALPRD0 R/W 0h Qualification sampling period for GPIO32 to GPIO39:
0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

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10.10.2.20 GPBQSEL1 Register (Offset = 42h) [Reset = CC0h]

GPBQSEL1 is shown in Figure 10-23 and described in Table 10-32.
Return to the Summary Table.
GPIO B Qualifier Select 1 Register (GPIO32 to 47)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 10-23. GPBQSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO39 RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-3h R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h

Table 10-32. GPBQSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO47 R/W 0h Select input qualification type for GPIO47:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
29-28 GPIO46 R/W 0h Select input qualification type for GPIO46:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
27-26 GPIO45 R/W 0h Select input qualification type for GPIO45:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
25-24 GPIO44 R/W 0h Select input qualification type for GPIO44:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
23-22 GPIO43 R/W 0h Select input qualification type for GPIO43:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
21-20 GPIO42 R/W 0h Select input qualification type for GPIO42:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-32. GPBQSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 GPIO41 R/W 0h Select input qualification type for GPIO41:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
17-16 GPIO40 R/W 0h Select input qualification type for GPIO40:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
15-14 GPIO39 R/W 0h Select input qualification type for GPIO39:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
13-12 RESERVED R/W 0h Reserved
11-10 GPIO37 R/W 3h Select input qualification type for GPIO37:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
9-8 RESERVED R/W 0h Reserved
7-6 GPIO35 R/W 3h Select input qualification type for GPIO35:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
5-4 GPIO34 R/W 0h Select input qualification type for GPIO34:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
3-2 GPIO33 R/W 0h Select input qualification type for GPIO33:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
1-0 GPIO32 R/W 0h Select input qualification type for GPIO32:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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10.10.2.21 GPBQSEL2 Register (Offset = 44h) [Reset = 0h]

GPBQSEL2 is shown in Figure 10-24 and described in Table 10-33.
Return to the Summary Table.
GPIO B Qualifier Select 2 Register (GPIO48 to 63)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 10-24. GPBQSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED RESERVED GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-33. GPBQSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 GPIO61 R/W 0h Select input qualification type for GPIO61:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
25-24 GPIO60 R/W 0h Select input qualification type for GPIO60:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
23-22 GPIO59 R/W 0h Select input qualification type for GPIO59:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
21-20 GPIO58 R/W 0h Select input qualification type for GPIO58:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
19-18 GPIO57 R/W 0h Select input qualification type for GPIO57:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-33. GPBQSEL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
17-16 GPIO56 R/W 0h Select input qualification type for GPIO56:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
15-14 GPIO55 R/W 0h Select input qualification type for GPIO55:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
13-12 GPIO54 R/W 0h Select input qualification type for GPIO54:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
11-10 GPIO53 R/W 0h Select input qualification type for GPIO53:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
9-8 GPIO52 R/W 0h Select input qualification type for GPIO52:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
7-6 GPIO51 R/W 0h Select input qualification type for GPIO51:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
5-4 GPIO50 R/W 0h Select input qualification type for GPIO50:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
3-2 GPIO49 R/W 0h Select input qualification type for GPIO49:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
1-0 GPIO48 R/W 0h Select input qualification type for GPIO48:
0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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10.10.2.22 GPBMUX1 Register (Offset = 46h) [Reset = CC0h]

GPBMUX1 is shown in Figure 10-25 and described in Table 10-34.
Return to the Summary Table.
GPIO B Mux 1 Register (GPIO32 to 47)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO. Refer to GPIO chapter for more details.
Figure 10-25. GPBMUX1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO39 RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-3h R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h

Table 10-34. GPBMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO47 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO46 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO45 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO44 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO43 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO42 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO41 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO40 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO39 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 RESERVED R/W 0h Reserved
11-10 GPIO37 R/W 3h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 RESERVED R/W 0h Reserved
7-6 GPIO35 R/W 3h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO34 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO33 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO32 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.10.2.23 GPBMUX2 Register (Offset = 48h) [Reset = 0h]

GPBMUX2 is shown in Figure 10-26 and described in Table 10-35.
Return to the Summary Table.
GPIO B Mux 2 Register (GPIO48 to 63)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO. Refer to GPIO chapter for more details.
Figure 10-26. GPBMUX2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED RESERVED GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-35. GPBMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 GPIO61 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO60 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO59 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO58 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO57 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO56 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO55 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO54 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO53 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO52 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO51 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO50 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO49 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO48 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.10.2.24 GPBDIR Register (Offset = 4Ah) [Reset = 0h]

GPBDIR is shown in Figure 10-27 and described in Table 10-36.
Return to the Summary Table.
GPIO B Direction Register (GPIO32 to 63)
Controls direction of GPIO pins when the specified pin is configured in GPIO mode.
0: Configures pin as input.
1: Configures pin as output.
Reading the register returns the current value of the register setting.
Figure 10-27. GPBDIR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-36. GPBDIR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 GPIO61 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
28 GPIO60 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
27 GPIO59 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
26 GPIO58 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
25 GPIO57 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
24 GPIO56 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
23 GPIO55 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
22 GPIO54 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
21 GPIO53 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
20 GPIO52 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
19 GPIO51 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
18 GPIO50 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

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Table 10-36. GPBDIR Register Field Descriptions (continued)

Bit Field Type Reset Description
17 GPIO49 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
16 GPIO48 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
15 GPIO47 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
14 GPIO46 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
13 GPIO45 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
12 GPIO44 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
11 GPIO43 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
10 GPIO42 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
9 GPIO41 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
8 GPIO40 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
7 GPIO39 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
6 RESERVED R/W 0h Reserved
5 GPIO37 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
4 RESERVED R/W 0h Reserved
3 GPIO35 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
2 GPIO34 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
1 GPIO33 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn
0 GPIO32 R/W 0h Defines direction for this pin in GPIO mode
Reset type: SYSRSn

1120 TMS320F28003x Real-Time Microcontrollers SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023
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10.10.2.25 GPBPUD Register (Offset = 4Ch) [Reset = FFFFFFFFh]

GPBPUD is shown in Figure 10-28 and described in Table 10-37.
Return to the Summary Table.
GPIO B Pull Up Disable Register (GPIO32 to 63)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.
Figure 10-28. GPBPUD Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
GPIO39 RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 10-37. GPBPUD Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 1h Reserved
30 RESERVED R/W 1h Reserved
29 GPIO61 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
28 GPIO60 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
27 GPIO59 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
26 GPIO58 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
25 GPIO57 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
24 GPIO56 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
23 GPIO55 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
22 GPIO54 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
21 GPIO53 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
20 GPIO52 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
19 GPIO51 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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Table 10-37. GPBPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
18 GPIO50 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
17 GPIO49 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
16 GPIO48 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
15 GPIO47 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
14 GPIO46 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
13 GPIO45 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
12 GPIO44 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
11 GPIO43 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
10 GPIO42 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
9 GPIO41 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
8 GPIO40 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
7 GPIO39 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
6 RESERVED R/W 1h Reserved
5 GPIO37 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
4 RESERVED R/W 1h Reserved
3 GPIO35 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
2 GPIO34 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
1 GPIO33 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn
0 GPIO32 R/W 1h Pull-Up Disable control for this pin
Reset type: SYSRSn

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10.10.2.26 GPBINV Register (Offset = 50h) [Reset = 0h]

GPBINV is shown in Figure 10-29 and described in Table 10-38.
Return to the Summary Table.
GPIO B Input Polarity Invert Registers (GPIO32 to 63)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 10-29. GPBINV Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-38. GPBINV Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 GPIO61 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
28 GPIO60 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
27 GPIO59 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
26 GPIO58 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
25 GPIO57 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
24 GPIO56 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
23 GPIO55 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
22 GPIO54 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
21 GPIO53 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
20 GPIO52 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
19 GPIO51 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
18 GPIO50 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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Table 10-38. GPBINV Register Field Descriptions (continued)

Bit Field Type Reset Description
17 GPIO49 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
16 GPIO48 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
15 GPIO47 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
14 GPIO46 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
13 GPIO45 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
12 GPIO44 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
11 GPIO43 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
10 GPIO42 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
9 GPIO41 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
8 GPIO40 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
7 GPIO39 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
6 RESERVED R/W 0h Reserved
5 GPIO37 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
4 RESERVED R/W 0h Reserved
3 GPIO35 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
2 GPIO34 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
1 GPIO33 R/W 0h Input inversion control for this pin
Reset type: SYSRSn
0 GPIO32 R/W 0h Input inversion control for this pin
Reset type: SYSRSn

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10.10.2.27 GPBODR Register (Offset = 52h) [Reset = 0h]

GPBODR is shown in Figure 10-30 and described in Table 10-39.
Return to the Summary Table.
GPIO B Open Drain Output Register (GPIO32 to GPIO63)
Selects between normal and open-drain output for the GPIO pin.
0: Normal Output
1: Open Drain Output
Reading the register returns the current value of the register setting.
Note:
[1] In the Open Drain output mode, if the buffer is configured for output mode, a 0 value to be driven out comes
out on the on the PAD while a 1 value to be driven out tri-states the buffer.
Figure 10-30. GPBODR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-39. GPBODR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 GPIO61 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
28 GPIO60 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
27 GPIO59 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
26 GPIO58 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
25 GPIO57 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
24 GPIO56 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
23 GPIO55 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
22 GPIO54 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
21 GPIO53 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
20 GPIO52 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn

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Table 10-39. GPBODR Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO51 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
18 GPIO50 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
17 GPIO49 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
16 GPIO48 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
15 GPIO47 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
14 GPIO46 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
13 GPIO45 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
12 GPIO44 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
11 GPIO43 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
10 GPIO42 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
9 GPIO41 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
8 GPIO40 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
7 GPIO39 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
6 RESERVED R/W 0h Reserved
5 GPIO37 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
4 RESERVED R/W 0h Reserved
3 GPIO35 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
2 GPIO34 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
1 GPIO33 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn
0 GPIO32 R/W 0h Outpout Open-Drain control for this pin
Reset type: SYSRSn

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10.10.2.28 GPBGMUX1 Register (Offset = 60h) [Reset = CC0h]

GPBGMUX1 is shown in Figure 10-31 and described in Table 10-40.
Return to the Summary Table.
GPIO B Peripheral Group Mux (GPIO32 to 47)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 10-31. GPBGMUX1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO39 RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-3h R/W-0h R/W-3h R/W-0h R/W-0h R/W-0h

Table 10-40. GPBGMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO47 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO46 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO45 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO44 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO43 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO42 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO41 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO40 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO39 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 RESERVED R/W 0h Reserved
11-10 GPIO37 R/W 3h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 RESERVED R/W 0h Reserved
7-6 GPIO35 R/W 3h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO34 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO33 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO32 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.10.2.29 GPBGMUX2 Register (Offset = 62h) [Reset = 0h]

GPBGMUX2 is shown in Figure 10-32 and described in Table 10-41.
Return to the Summary Table.
GPIO B Peripheral Group Mux (GPIO48 to 63)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 10-32. GPBGMUX2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED RESERVED GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-41. GPBGMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 GPIO61 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 GPIO60 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 GPIO59 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
21-20 GPIO58 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
19-18 GPIO57 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO56 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO55 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO54 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 GPIO53 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO52 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO51 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO50 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO49 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO48 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.10.2.30 GPBCSEL1 Register (Offset = 68h) [Reset = 0h]

GPBCSEL1 is shown in Figure 10-33 and described in Table 10-42.
Return to the Summary Table.
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-33. GPBCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO39 RESERVED GPIO37 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-42. GPBCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO39 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 RESERVED R/W 0h Reserved
23-20 GPIO37 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 RESERVED R/W 0h Reserved
15-12 GPIO35 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO34 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO33 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO32 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.10.2.31 GPBCSEL2 Register (Offset = 6Ah) [Reset = 0h]

GPBCSEL2 is shown in Figure 10-34 and described in Table 10-43.
Return to the Summary Table.
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-34. GPBCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO47 GPIO46 GPIO45 GPIO44
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-43. GPBCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO47 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO46 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO45 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO44 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO43 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO42 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO41 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO40 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.10.2.32 GPBCSEL3 Register (Offset = 6Ch) [Reset = 0h]

GPBCSEL3 is shown in Figure 10-35 and described in Table 10-44.
Return to the Summary Table.
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-35. GPBCSEL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-44. GPBCSEL3 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO55 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO54 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO53 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO52 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO51 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO50 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO49 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO48 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.10.2.33 GPBCSEL4 Register (Offset = 6Eh) [Reset = 0h]

GPBCSEL4 is shown in Figure 10-36 and described in Table 10-45.
Return to the Summary Table.
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-36. GPBCSEL4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED RESERVED GPIO61 GPIO60
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-45. GPBCSEL4 Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R/W 0h Reserved
27-24 RESERVED R/W 0h Reserved
23-20 GPIO61 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO60 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO59 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO58 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO57 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO56 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.10.2.34 GPBLOCK Register (Offset = 7Ch) [Reset = 0h]

GPBLOCK is shown in Figure 10-37 and described in Table 10-46.
Return to the Summary Table.
GPIO B Lock Configuration Register (GPIO32 to 63)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1,
GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 10-37. GPBLOCK Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-46. GPBLOCK Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 GPIO61 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
28 GPIO60 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
27 GPIO59 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
26 GPIO58 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
25 GPIO57 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
24 GPIO56 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
23 GPIO55 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
22 GPIO54 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
21 GPIO53 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
20 GPIO52 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
19 GPIO51 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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Table 10-46. GPBLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
18 GPIO50 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
17 GPIO49 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
16 GPIO48 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
15 GPIO47 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
14 GPIO46 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
13 GPIO45 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
12 GPIO44 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
11 GPIO43 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
10 GPIO42 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
9 GPIO41 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
8 GPIO40 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
7 GPIO39 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
6 RESERVED R/W 0h Reserved
5 GPIO37 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
4 RESERVED R/W 0h Reserved
3 GPIO35 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
2 GPIO34 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
1 GPIO33 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn
0 GPIO32 R/W 0h Configuration Lock bit for this pin
Reset type: SYSRSn

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10.10.2.35 GPBCR Register (Offset = 7Eh) [Reset = 0h]

GPBCR is shown in Figure 10-38 and described in Table 10-47.
Return to the Summary Table.
GPIO B Lock Commit Register (GPIO32 to 63)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 10-38. GPBCR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
GPIO39 RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 10-47. GPBCR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/WSonce 0h Reserved
30 RESERVED R/WSonce 0h Reserved
29 GPIO61 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
28 GPIO60 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
27 GPIO59 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
26 GPIO58 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
25 GPIO57 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
24 GPIO56 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
23 GPIO55 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
22 GPIO54 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
21 GPIO53 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
20 GPIO52 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
19 GPIO51 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
18 GPIO50 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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Table 10-47. GPBCR Register Field Descriptions (continued)

Bit Field Type Reset Description
17 GPIO49 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
16 GPIO48 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
15 GPIO47 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
14 GPIO46 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
13 GPIO45 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
12 GPIO44 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
11 GPIO43 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
10 GPIO42 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
9 GPIO41 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
8 GPIO40 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
7 GPIO39 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
6 RESERVED R/WSonce 0h Reserved
5 GPIO37 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
4 RESERVED R/WSonce 0h Reserved
3 GPIO35 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
2 GPIO34 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
1 GPIO33 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn
0 GPIO32 R/WSonce 0h Configuration lock commit bit for this pin
Reset type: SYSRSn

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10.10.2.36 GPHCTRL Register (Offset = 1C0h) [Reset = 0h]

GPHCTRL is shown in Figure 10-39 and described in Table 10-48.
Return to the Summary Table.
GPIO H Qualification Sampling Period Control (GPIO224 to 255)
Figure 10-39. GPHCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QUALPRD3 QUALPRD2 QUALPRD1 QUALPRD0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-48. GPHCTRL Register Field Descriptions

Bit Field Type Reset Description
31-24 QUALPRD3 R/W 0h 0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/513
Reset type: SYSRSn
23-16 QUALPRD2 R/W 0h 0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/512
Reset type: SYSRSn
15-8 QUALPRD1 R/W 0h 0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/511
Reset type: SYSRSn
7-0 QUALPRD0 R/W 0h 0x00,QUALPRDx = PLLSYSCLK
0x01,QUALPRDx = PLLSYSCLK/2
0x02,QUALPRDx = PLLSYSCLK/4
....
0xFF,QUALPRDx = PLLSYSCLK/510
Reset type: SYSRSn

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10.10.2.37 GPHQSEL1 Register (Offset = 1C2h) [Reset = 0h]

GPHQSEL1 is shown in Figure 10-40 and described in Table 10-49.
Return to the Summary Table.
GPIO H Qualifier Select 1 Register (GPIO224 to 239)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 10-40. GPHQSEL1 Register
31 30 29 28 27 26 25 24
GPIO239 GPIO238 GPIO237 GPIO236
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO231 GPIO230 GPIO229 GPIO228
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-49. GPHQSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO239 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
29-28 GPIO238 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
27-26 GPIO237 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
25-24 GPIO236 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 GPIO233 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-49. GPHQSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
17-16 GPIO232 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
15-14 GPIO231 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
13-12 GPIO230 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
11-10 GPIO229 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
9-8 GPIO228 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
7-6 GPIO227 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
5-4 GPIO226 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
3-2 GPIO225 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
1-0 GPIO224 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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10.10.2.38 GPHQSEL2 Register (Offset = 1C4h) [Reset = 0h]

GPHQSEL2 is shown in Figure 10-41 and described in Table 10-50.
Return to the Summary Table.
GPIO H Qualifier Select 2 Register (GPIO240 to 255)
Input qualification type:
0,0 Sync
0,1 Qualification (3 samples)
1,0 Qualification (6 samples)
1,1 Async (no Sync or Qualification)
Figure 10-41. GPHQSEL2 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO251 RESERVED GPIO249 GPIO248
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO247 RESERVED GPIO245 GPIO244
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED GPIO242 GPIO241 GPIO240
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-50. GPHQSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 GPIO253 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
25-24 GPIO252 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
23-22 GPIO251 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
21-20 RESERVED R/W 0h Reserved
19-18 GPIO249 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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Table 10-50. GPHQSEL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
17-16 GPIO248 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
15-14 GPIO247 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
13-12 RESERVED R/W 0h Reserved
11-10 GPIO245 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
9-8 GPIO244 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
7-6 RESERVED R/W 0h Reserved
5-4 GPIO242 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
3-2 GPIO241 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn
1-0 GPIO240 R/W 0h 0,0,Sync
0,1,Qualification (3 samples)
1,0,Qualification (6 samples)
1,1,Async (no Sync or Qualification)
Reset type: SYSRSn

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10.10.2.39 GPHMUX1 Register (Offset = 1C6h) [Reset = 0h]

GPHMUX1 is shown in Figure 10-42 and described in Table 10-51.
Return to the Summary Table.
GPIO H Mux 1 Register (GPIO224 to 239)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO. Refer to GPIO chapter for more details.
Figure 10-42. GPHMUX1 Register
31 30 29 28 27 26 25 24
GPIO239 GPIO238 GPIO237 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO231 GPIO230 RESERVED GPIO228
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-51. GPHMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO239 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO238 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO237 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 RESERVED R/W 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 GPIO233 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO232 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO231 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO230 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 RESERVED R/W 0h Reserved
9-8 GPIO228 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO227 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO226 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 10-51. GPHMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 GPIO225 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO224 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.10.2.40 GPHMUX2 Register (Offset = 1C8h) [Reset = 0h]

GPHMUX2 is shown in Figure 10-43 and described in Table 10-52.
Return to the Summary Table.
GPIO H Mux 2 Register (GPIO240 to 255)
Defines pin-muxing selection for GPIO.
Notes:
The respective GPyGMUXn.GPIOz must be configured prior to this register to avoid intermediate peripheral
selects being mapped to the GPIO. Refer to GPIO chapter for more details.
Figure 10-43. GPHMUX2 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED GPIO252
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED GPIO245 GPIO244
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED GPIO242 GPIO241 GPIO240
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-52. GPHMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 RESERVED R/W 0h Reserved
25-24 GPIO252 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 RESERVED R/W 0h Reserved
17-16 RESERVED R/W 0h Reserved
15-14 RESERVED R/W 0h Reserved
13-12 RESERVED R/W 0h Reserved
11-10 GPIO245 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO244 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 RESERVED R/W 0h Reserved
5-4 GPIO242 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO241 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO240 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.10.2.41 GPHPUD Register (Offset = 1CCh) [Reset = FFFFFFFFh]

GPHPUD is shown in Figure 10-44 and described in Table 10-53.
Return to the Summary Table.
GPIO H Pull Up Disable Register (GPIO224 to 255)
Disables the Pull-Up on GPIO.
0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously when IORSn signal is low.
Figure 10-44. GPHPUD Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252 GPIO251 RESERVED GPIO249 GPIO248
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
GPIO247 RESERVED GPIO245 GPIO244 RESERVED GPIO242 GPIO241 GPIO240
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
GPIO239 GPIO238 GPIO237 GPIO236 RESERVED RESERVED GPIO233 GPIO232
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
GPIO231 GPIO230 GPIO229 GPIO228 GPIO227 GPIO226 GPIO225 GPIO224
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 10-53. GPHPUD Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 1h Reserved
30 RESERVED R/W 1h Reserved
29 GPIO253 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
28 GPIO252 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn

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Table 10-53. GPHPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
27 GPIO251 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
26 RESERVED R/W 1h Reserved
25 GPIO249 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
24 GPIO248 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
23 GPIO247 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
22 RESERVED R/W 1h Reserved
21 GPIO245 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
20 GPIO244 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
19 RESERVED R/W 1h Reserved

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Table 10-53. GPHPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
18 GPIO242 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
17 GPIO241 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
16 GPIO240 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
15 GPIO239 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
14 GPIO238 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
13 GPIO237 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
12 GPIO236 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn

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Table 10-53. GPHPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
11 RESERVED R/W 1h Reserved
10 RESERVED R/W 1h Reserved
9 GPIO233 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
8 GPIO232 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
7 GPIO231 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
6 GPIO230 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
5 GPIO229 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
4 GPIO228 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn

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Table 10-53. GPHPUD Register Field Descriptions (continued)

Bit Field Type Reset Description
3 GPIO227 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
2 GPIO226 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
1 GPIO225 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn
0 GPIO224 R/W 1h 0: Enables the Pull-Up.
1: Disables the Pull-Up.
Reading the register returns the current value of the register setting.
Note:
[1] The Pull-Ups on the GPIO pins are disabled asynchronously
when IORSn signal is low. When coming out of reset, the pull-
ups will remain disabled until the user enables them selectively in
software by writing to this register.
Reset type: SYSRSn

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10.10.2.42 GPHINV Register (Offset = 1D0h) [Reset = 0h]

GPHINV is shown in Figure 10-45 and described in Table 10-54.
Return to the Summary Table.
GPIO H Input Polarity Invert Registers (GPIO224 to 255)
Selects between non-inverted and inverted GPIO input to the device.
0: selects non-inverted GPIO input
1: selects inverted GPIO input
Reading the register returns the current value of the register setting.
Figure 10-45. GPHINV Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252 GPIO251 RESERVED GPIO249 GPIO248
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO247 RESERVED GPIO245 GPIO244 RESERVED GPIO242 GPIO241 GPIO240
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO239 GPIO238 GPIO237 GPIO236 RESERVED RESERVED GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO231 GPIO230 GPIO229 GPIO228 GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-54. GPHINV Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 GPIO253 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
28 GPIO252 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
27 GPIO251 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
26 RESERVED R/W 0h Reserved
25 GPIO249 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn

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Table 10-54. GPHINV Register Field Descriptions (continued)

Bit Field Type Reset Description
24 GPIO248 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
23 GPIO247 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
22 RESERVED R/W 0h Reserved
21 GPIO245 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
20 GPIO244 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
19 RESERVED R/W 0h Reserved
18 GPIO242 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
17 GPIO241 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
16 GPIO240 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
15 GPIO239 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
14 GPIO238 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn

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Table 10-54. GPHINV Register Field Descriptions (continued)

Bit Field Type Reset Description
13 GPIO237 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
12 GPIO236 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 GPIO233 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
8 GPIO232 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
7 GPIO231 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
6 GPIO230 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
5 GPIO229 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
4 GPIO228 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
3 GPIO227 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn

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Table 10-54. GPHINV Register Field Descriptions (continued)

Bit Field Type Reset Description
2 GPIO226 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
1 GPIO225 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn
0 GPIO224 R/W 0h 0: selects non-inverted GPIO input
1: selects inverted GPIO input
Notes:
[1] Reading the register returns the current value of the register
setting.
Reset type: SYSRSn

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10.10.2.43 GPHAMSEL Register (Offset = 1D4h) [Reset = FFFFFFFFh]

GPHAMSEL is shown in Figure 10-46 and described in Table 10-55.
Return to the Summary Table.
GPIO H Analog Mode Select register (GPIO224 to GPIO255)
Selects between digital and analog functionality for GPIO pins.
0: The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other
GPIO configuration registers
1: The analog function of the pin is enabled and the pin is capable of analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share analog function through a unified I/O pad. For
all the IOs, t
Figure 10-46. GPHAMSEL Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252 GPIO251 RESERVED GPIO249 GPIO248
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

23 22 21 20 19 18 17 16
GPIO247 RESERVED GPIO245 GPIO244 RESERVED GPIO242 GPIO241 GPIO240
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

15 14 13 12 11 10 9 8
GPIO239 GPIO238 GPIO237 GPIO236 RESERVED RESERVED GPIO233 GPIO232
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

7 6 5 4 3 2 1 0
GPIO231 GPIO230 GPIO229 GPIO228 GPIO227 GPIO226 GPIO225 GPIO224
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 10-55. GPHAMSEL Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 1h Reserved
30 RESERVED R/W 1h Reserved
29 GPIO253 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
28 GPIO252 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn

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Table 10-55. GPHAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
27 GPIO251 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
26 RESERVED R/W 1h Reserved
25 GPIO249 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
24 GPIO248 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
23 GPIO247 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
22 RESERVED R/W 1h Reserved
21 GPIO245 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn

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Table 10-55. GPHAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO244 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
19 RESERVED R/W 1h Reserved
18 GPIO242 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
17 GPIO241 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
16 GPIO240 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
15 GPIO239 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn

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Table 10-55. GPHAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
14 GPIO238 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
13 GPIO237 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
12 GPIO236 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
11 RESERVED R/W 1h Reserved
10 RESERVED R/W 1h Reserved
9 GPIO233 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
8 GPIO232 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn

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Table 10-55. GPHAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
7 GPIO231 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
6 GPIO230 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
5 GPIO229 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
4 GPIO228 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
3 GPIO227 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn

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Table 10-55. GPHAMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
2 GPIO226 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
1 GPIO225 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn
0 GPIO224 R/W 1h 0: The analog function of the pin is disabled and the pin is capable
of digital functions as specified by the other GPIO configuration
registers
1: The analog function of the pin is enabled and the pin is capable of
analog functions
Reading the register returns the current value of the register setting.
Note:
[1] This register and bits are only valid for GPIO signals that share
analog function through a unified I/O pad. For all the IOs, the
corresponding bits in these registers dont have any affect.
Reset type: SYSRSn

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10.10.2.44 GPHGMUX1 Register (Offset = 1E0h) [Reset = 0h]

GPHGMUX1 is shown in Figure 10-47 and described in Table 10-56.
Return to the Summary Table.
GPIO H Peripheral Group Mux (GPIO224 to 239)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 10-47. GPHGMUX1 Register
31 30 29 28 27 26 25 24
GPIO239 GPIO238 GPIO237 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO231 GPIO230 RESERVED GPIO228
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-56. GPHGMUX1 Register Field Descriptions

Bit Field Type Reset Description
31-30 GPIO239 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
29-28 GPIO238 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
27-26 GPIO237 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
25-24 RESERVED R/W 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 GPIO233 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
17-16 GPIO232 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
15-14 GPIO231 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
13-12 GPIO230 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
11-10 RESERVED R/W 0h Reserved
9-8 GPIO228 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 GPIO227 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
5-4 GPIO226 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO225 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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Table 10-56. GPHGMUX1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 GPIO224 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.10.2.45 GPHGMUX2 Register (Offset = 1E2h) [Reset = 0h]

GPHGMUX2 is shown in Figure 10-48 and described in Table 10-57.
Return to the Summary Table.
GPIO H Peripheral Group Mux (GPIO240 to 255)
Defines pin-muxing selection for GPIO.
Notes:
[1]For complete pin-mux selection on GPIOx, GPAMUXy.GPIOx configuration is also required.
Figure 10-48. GPHGMUX2 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED GPIO252
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED GPIO245 GPIO244
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED GPIO242 GPIO241 GPIO240
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-57. GPHGMUX2 Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R/W 0h Reserved
29-28 RESERVED R/W 0h Reserved
27-26 RESERVED R/W 0h Reserved
25-24 GPIO252 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 RESERVED R/W 0h Reserved
17-16 RESERVED R/W 0h Reserved
15-14 RESERVED R/W 0h Reserved
13-12 RESERVED R/W 0h Reserved
11-10 GPIO245 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
9-8 GPIO244 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
7-6 RESERVED R/W 0h Reserved
5-4 GPIO242 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
3-2 GPIO241 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn
1-0 GPIO240 R/W 0h Defines pin-muxing selection for GPIO
Reset type: SYSRSn

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10.10.2.46 GPHCSEL1 Register (Offset = 1E8h) [Reset = 0h]

GPHCSEL1 is shown in Figure 10-49 and described in Table 10-58.
Return to the Summary Table.
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-49. GPHCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO231 GPIO230 GPIO229 GPIO228
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-58. GPHCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO231 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO230 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO229 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO228 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO227 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 GPIO226 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO225 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO224 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.10.2.47 GPHCSEL2 Register (Offset = 1EAh) [Reset = 0h]

GPHCSEL2 is shown in Figure 10-50 and described in Table 10-59.
Return to the Summary Table.
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-50. GPHCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO239 GPIO238 GPIO237 GPIO236
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-59. GPHCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO239 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 GPIO238 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
23-20 GPIO237 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO236 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 RESERVED R/W 0h Reserved
11-8 RESERVED R/W 0h Reserved
7-4 GPIO233 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO232 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.10.2.48 GPHCSEL3 Register (Offset = 1ECh) [Reset = 0h]

GPHCSEL3 is shown in Figure 10-51 and described in Table 10-60.
Return to the Summary Table.
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-51. GPHCSEL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO247 RESERVED GPIO245 GPIO244
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED GPIO242 GPIO241 GPIO240
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-60. GPHCSEL3 Register Field Descriptions

Bit Field Type Reset Description
31-28 GPIO247 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
27-24 RESERVED R/W 0h Reserved
23-20 GPIO245 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO244 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 RESERVED R/W 0h Reserved
11-8 GPIO242 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
7-4 GPIO241 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO240 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.10.2.49 GPHCSEL4 Register (Offset = 1EEh) [Reset = 0h]

GPHCSEL4 is shown in Figure 10-52 and described in Table 10-61.
Return to the Summary Table.
Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers control this GPIO pin
0000: CPU1 selected
0001: CPU1.CLA1 selected
0010: CPU2 selected (Reserved)
0011: CPU2.CLA1 selected (Reserved)
0100: CM selected (Reserved)
0101: HIC selected (Reserved)
Figure 10-52. GPHCSEL4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED RESERVED GPIO253 GPIO252
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO251 RESERVED GPIO249 GPIO248
R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-61. GPHCSEL4 Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R/W 0h Reserved
27-24 RESERVED R/W 0h Reserved
23-20 GPIO253 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
19-16 GPIO252 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
15-12 GPIO251 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
11-8 RESERVED R/W 0h Reserved
7-4 GPIO249 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn
3-0 GPIO248 R/W 0h Selects which master's GPIODAT/SET/CLEAR/TOGGLE registers
control this GPIO pin
Reset type: SYSRSn

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10.10.2.50 GPHLOCK Register (Offset = 1FCh) [Reset = 0h]

GPHLOCK is shown in Figure 10-53 and described in Table 10-62.
Return to the Summary Table.
GPIO H Lock Configuration Register (GPIO224 to 255)
GPIO Configuration Lock for GPIO.
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx register which control the same pin can be changed
1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR, GPyAMSEL, GPyGMUX1,
GPyGMUX2 and GPyCSELx registers which control the same pin
Figure 10-53. GPHLOCK Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252 GPIO251 RESERVED GPIO249 GPIO248
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO247 RESERVED GPIO245 GPIO244 RESERVED GPIO242 GPIO241 GPIO240
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO239 GPIO238 GPIO237 GPIO236 RESERVED RESERVED GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO231 GPIO230 GPIO229 GPIO228 GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-62. GPHLOCK Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 GPIO253 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
28 GPIO252 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
27 GPIO251 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
26 RESERVED R/W 0h Reserved

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Table 10-62. GPHLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
25 GPIO249 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
24 GPIO248 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
23 GPIO247 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
22 RESERVED R/W 0h Reserved
21 GPIO245 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
20 GPIO244 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
19 RESERVED R/W 0h Reserved
18 GPIO242 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
17 GPIO241 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
16 GPIO240 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn

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Table 10-62. GPHLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
15 GPIO239 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
14 GPIO238 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
13 GPIO237 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
12 GPIO236 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 GPIO233 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
8 GPIO232 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
7 GPIO231 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
6 GPIO230 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn

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Table 10-62. GPHLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
5 GPIO229 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
4 GPIO228 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
3 GPIO227 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
2 GPIO226 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
1 GPIO225 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn
0 GPIO224 R/W 0h 1: Locks changes to the bits in GPyMUX1, GPyMUX2, GPyDIR,
GPyINV, GPyODR, GPyAMSEL, GPyGMUX1, GPyGMUX2 and
GPyCSELx registers which control the same pin
0: Bits in GPyMUX1, GPyMUX2, GPyDIR, GPyINV, GPyODR,
GPyAMSEL, GPyGMUX1, GPyGMUX2 and GPyCSELx register
which control the same pin can be changed
Reset type: SYSRSn

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10.10.2.51 GPHCR Register (Offset = 1FEh) [Reset = 0h]

GPHCR is shown in Figure 10-54 and described in Table 10-63.
Return to the Summary Table.
GPIO H Lock Commit Register (GPIO224 to 255)
GPIO Configuration Lock Commit for GPIO:
1: Locks changes to the bit in GPyLOCK register which controls the same pin
0: Bit in the GPyLOCK register which controls the same pin can be changed
Figure 10-54. GPHCR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252 GPIO251 RESERVED GPIO249 GPIO248
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO247 RESERVED GPIO245 GPIO244 RESERVED GPIO242 GPIO241 GPIO240
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO239 GPIO238 GPIO237 GPIO236 RESERVED RESERVED GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO231 GPIO230 GPIO229 GPIO228 GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-63. GPHCR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 GPIO253 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
28 GPIO252 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
27 GPIO251 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
26 RESERVED R/W 0h Reserved
25 GPIO249 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
24 GPIO248 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn

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Table 10-63. GPHCR Register Field Descriptions (continued)

Bit Field Type Reset Description
23 GPIO247 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
22 RESERVED R/W 0h Reserved
21 GPIO245 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
20 GPIO244 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
19 RESERVED R/W 0h Reserved
18 GPIO242 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
17 GPIO241 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
16 GPIO240 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
15 GPIO239 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
14 GPIO238 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
13 GPIO237 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
12 GPIO236 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 GPIO233 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn

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Table 10-63. GPHCR Register Field Descriptions (continued)

Bit Field Type Reset Description
8 GPIO232 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
7 GPIO231 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
6 GPIO230 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
5 GPIO229 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
4 GPIO228 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
3 GPIO227 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
2 GPIO226 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
1 GPIO225 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn
0 GPIO224 R/W 0h 1: Locks changes to the bit in GPyLOCK register which controls the
same pin
0: Bit in the GPyLOCK register which controls the same pin can be
changed
Reset type: SYSRSn

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10.10.3 GPIO_DATA_REGS Registers

Table 10-64 lists the memory-mapped registers for the GPIO_DATA_REGS registers. All register offset
addresses not listed in Table 10-64 should be considered as reserved locations and the register contents should
not be modified.
Table 10-64. GPIO_DATA_REGS Registers
Offset Acronym Register Name Write Protection Section
0h GPADAT GPIO A Data Register (GPIO0 to 31) Go
2h GPASET GPIO A Data Set Register (GPIO0 to 31) Go
4h GPACLEAR GPIO A Data Clear Register (GPIO0 to 31) Go
6h GPATOGGLE GPIO A Data Toggle Register (GPIO0 to 31) Go
8h GPBDAT GPIO B Data Register (GPIO32 to 63) Go
Ah GPBSET GPIO B Data Set Register (GPIO32 to 63) Go
Ch GPBCLEAR GPIO B Data Clear Register (GPIO32 to 63) Go
Eh GPBTOGGLE GPIO B Data Toggle Register (GPIO32 to 63) Go
38h GPHDAT GPIO H Data Register (GPIO224 to 255) Go

Complex bit access types are encoded to fit into small table cells. Table 10-65 shows the codes that are used for
access types in this section.
Table 10-65. GPIO_DATA_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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10.10.3.1 GPADAT Register (Offset = 0h) [Reset = 0h]

GPADAT is shown in Figure 10-55 and described in Table 10-66.
Return to the Summary Table.
GPIO A Data Register (GPIO0 to 31)
Reading this register indicates the current status of the GPIO pin, irrespective of which mode the pin is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode, otherwise the
value written is latched but ignored. The state of the output register latch will remain in its current state until the
next write operation. A system reset will clear all bits and latched values to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN (after qualification), not the state of the
output latch of the GPIODAT register.
Figure 10-55. GPADAT Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-66. GPADAT Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h Data Register for this pin
Reset type: SYSRSn
30 GPIO30 R/W 0h Data Register for this pin
Reset type: SYSRSn
29 GPIO29 R/W 0h Data Register for this pin
Reset type: SYSRSn
28 GPIO28 R/W 0h Data Register for this pin
Reset type: SYSRSn
27 GPIO27 R/W 0h Data Register for this pin
Reset type: SYSRSn
26 GPIO26 R/W 0h Data Register for this pin
Reset type: SYSRSn
25 GPIO25 R/W 0h Data Register for this pin
Reset type: SYSRSn
24 GPIO24 R/W 0h Data Register for this pin
Reset type: SYSRSn
23 GPIO23 R/W 0h Data Register for this pin
Reset type: SYSRSn
22 GPIO22 R/W 0h Data Register for this pin
Reset type: SYSRSn
21 GPIO21 R/W 0h Data Register for this pin
Reset type: SYSRSn

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Table 10-66. GPADAT Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO20 R/W 0h Data Register for this pin
Reset type: SYSRSn
19 GPIO19 R/W 0h Data Register for this pin
Reset type: SYSRSn
18 GPIO18 R/W 0h Data Register for this pin
Reset type: SYSRSn
17 GPIO17 R/W 0h Data Register for this pin
Reset type: SYSRSn
16 GPIO16 R/W 0h Data Register for this pin
Reset type: SYSRSn
15 GPIO15 R/W 0h Data Register for this pin
Reset type: SYSRSn
14 GPIO14 R/W 0h Data Register for this pin
Reset type: SYSRSn
13 GPIO13 R/W 0h Data Register for this pin
Reset type: SYSRSn
12 GPIO12 R/W 0h Data Register for this pin
Reset type: SYSRSn
11 GPIO11 R/W 0h Data Register for this pin
Reset type: SYSRSn
10 GPIO10 R/W 0h Data Register for this pin
Reset type: SYSRSn
9 GPIO9 R/W 0h Data Register for this pin
Reset type: SYSRSn
8 GPIO8 R/W 0h Data Register for this pin
Reset type: SYSRSn
7 GPIO7 R/W 0h Data Register for this pin
Reset type: SYSRSn
6 GPIO6 R/W 0h Data Register for this pin
Reset type: SYSRSn
5 GPIO5 R/W 0h Data Register for this pin
Reset type: SYSRSn
4 GPIO4 R/W 0h Data Register for this pin
Reset type: SYSRSn
3 GPIO3 R/W 0h Data Register for this pin
Reset type: SYSRSn
2 GPIO2 R/W 0h Data Register for this pin
Reset type: SYSRSn
1 GPIO1 R/W 0h Data Register for this pin
Reset type: SYSRSn
0 GPIO0 R/W 0h Data Register for this pin
Reset type: SYSRSn

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10.10.3.2 GPASET Register (Offset = 2h) [Reset = 0h]

GPASET is shown in Figure 10-56 and described in Table 10-67.
Return to the Summary Table.
GPIO A Data Set Register (GPIO0 to 31)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-56. GPASET Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-67. GPASET Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
30 GPIO30 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
29 GPIO29 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
28 GPIO28 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
27 GPIO27 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
26 GPIO26 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
25 GPIO25 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
24 GPIO24 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
23 GPIO23 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
22 GPIO22 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
21 GPIO21 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
20 GPIO20 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
19 GPIO19 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn

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Table 10-67. GPASET Register Field Descriptions (continued)

Bit Field Type Reset Description
18 GPIO18 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
17 GPIO17 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
16 GPIO16 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
15 GPIO15 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
14 GPIO14 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
13 GPIO13 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
12 GPIO12 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
11 GPIO11 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
10 GPIO10 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
9 GPIO9 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
8 GPIO8 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
7 GPIO7 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
6 GPIO6 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
5 GPIO5 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
4 GPIO4 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
3 GPIO3 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
2 GPIO2 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
1 GPIO1 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
0 GPIO0 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn

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10.10.3.3 GPACLEAR Register (Offset = 4h) [Reset = 0h]

GPACLEAR is shown in Figure 10-57 and described in Table 10-68.
Return to the Summary Table.
GPIO A Data Clear Register (GPIO0 to 31)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-57. GPACLEAR Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-68. GPACLEAR Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
30 GPIO30 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
29 GPIO29 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
28 GPIO28 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
27 GPIO27 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
26 GPIO26 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
25 GPIO25 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
24 GPIO24 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
23 GPIO23 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
22 GPIO22 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
21 GPIO21 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
20 GPIO20 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
19 GPIO19 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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Table 10-68. GPACLEAR Register Field Descriptions (continued)

Bit Field Type Reset Description
18 GPIO18 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
17 GPIO17 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
16 GPIO16 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
15 GPIO15 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
14 GPIO14 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
13 GPIO13 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
12 GPIO12 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
11 GPIO11 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
10 GPIO10 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
9 GPIO9 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
8 GPIO8 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
7 GPIO7 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
6 GPIO6 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
5 GPIO5 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
4 GPIO4 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
3 GPIO3 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
2 GPIO2 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
1 GPIO1 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
0 GPIO0 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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10.10.3.4 GPATOGGLE Register (Offset = 6h) [Reset = 0h]

GPATOGGLE is shown in Figure 10-58 and described in Table 10-69.
Return to the Summary Table.
GPIO A Data Toggle Register (GPIO0 to 31)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-58. GPATOGGLE Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-69. GPATOGGLE Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
30 GPIO30 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
29 GPIO29 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
28 GPIO28 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
27 GPIO27 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
26 GPIO26 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
25 GPIO25 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
24 GPIO24 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
23 GPIO23 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
22 GPIO22 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
21 GPIO21 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
20 GPIO20 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
19 GPIO19 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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Table 10-69. GPATOGGLE Register Field Descriptions (continued)

Bit Field Type Reset Description
18 GPIO18 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
17 GPIO17 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
16 GPIO16 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
15 GPIO15 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
14 GPIO14 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
13 GPIO13 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
12 GPIO12 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
11 GPIO11 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
10 GPIO10 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
9 GPIO9 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
8 GPIO8 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
7 GPIO7 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
6 GPIO6 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
5 GPIO5 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
4 GPIO4 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
3 GPIO3 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
2 GPIO2 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
1 GPIO1 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
0 GPIO0 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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10.10.3.5 GPBDAT Register (Offset = 8h) [Reset = 0h]

GPBDAT is shown in Figure 10-59 and described in Table 10-70.
Return to the Summary Table.
GPIO B Data Register (GPIO32 to 63)
Reading this register indicates the current status of the GPIO pin, irrespective of which mode the pin is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode, otherwise the
value written is latched but ignored. The state of the output register latch will remain in its current state until the
next write operation. A system reset will clear all bits and latched values to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN (after qualification), not the state of the
output latch of the GPIODAT register.
Figure 10-59. GPBDAT Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-70. GPBDAT Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 GPIO61 R/W 0h Data Register for this pin
Reset type: SYSRSn
28 GPIO60 R/W 0h Data Register for this pin
Reset type: SYSRSn
27 GPIO59 R/W 0h Data Register for this pin
Reset type: SYSRSn
26 GPIO58 R/W 0h Data Register for this pin
Reset type: SYSRSn
25 GPIO57 R/W 0h Data Register for this pin
Reset type: SYSRSn
24 GPIO56 R/W 0h Data Register for this pin
Reset type: SYSRSn
23 GPIO55 R/W 0h Data Register for this pin
Reset type: SYSRSn
22 GPIO54 R/W 0h Data Register for this pin
Reset type: SYSRSn
21 GPIO53 R/W 0h Data Register for this pin
Reset type: SYSRSn
20 GPIO52 R/W 0h Data Register for this pin
Reset type: SYSRSn

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Table 10-70. GPBDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
19 GPIO51 R/W 0h Data Register for this pin
Reset type: SYSRSn
18 GPIO50 R/W 0h Data Register for this pin
Reset type: SYSRSn
17 GPIO49 R/W 0h Data Register for this pin
Reset type: SYSRSn
16 GPIO48 R/W 0h Data Register for this pin
Reset type: SYSRSn
15 GPIO47 R/W 0h Data Register for this pin
Reset type: SYSRSn
14 GPIO46 R/W 0h Data Register for this pin
Reset type: SYSRSn
13 GPIO45 R/W 0h Data Register for this pin
Reset type: SYSRSn
12 GPIO44 R/W 0h Data Register for this pin
Reset type: SYSRSn
11 GPIO43 R/W 0h Data Register for this pin
Reset type: SYSRSn
10 GPIO42 R/W 0h Data Register for this pin
Reset type: SYSRSn
9 GPIO41 R/W 0h Data Register for this pin
Reset type: SYSRSn
8 GPIO40 R/W 0h Data Register for this pin
Reset type: SYSRSn
7 GPIO39 R/W 0h Data Register for this pin
Reset type: SYSRSn
6 RESERVED R/W 0h Reserved
5 GPIO37 R/W 0h Data Register for this pin
Reset type: SYSRSn
4 RESERVED R/W 0h Reserved
3 GPIO35 R/W 0h Data Register for this pin
Reset type: SYSRSn
2 GPIO34 R/W 0h Data Register for this pin
Reset type: SYSRSn
1 GPIO33 R/W 0h Data Register for this pin
Reset type: SYSRSn
0 GPIO32 R/W 0h Data Register for this pin
Reset type: SYSRSn

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10.10.3.6 GPBSET Register (Offset = Ah) [Reset = 0h]

GPBSET is shown in Figure 10-60 and described in Table 10-71.
Return to the Summary Table.
GPIO B Data Set Register (GPIO32 to 63)
Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-60. GPBSET Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
GPIO39 RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-71. GPBSET Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0/W 0h Reserved
30 RESERVED R-0/W 0h Reserved
29 GPIO61 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
28 GPIO60 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
27 GPIO59 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
26 GPIO58 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
25 GPIO57 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
24 GPIO56 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
23 GPIO55 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
22 GPIO54 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
21 GPIO53 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
20 GPIO52 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
19 GPIO51 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
18 GPIO50 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn

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Table 10-71. GPBSET Register Field Descriptions (continued)

Bit Field Type Reset Description
17 GPIO49 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
16 GPIO48 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
15 GPIO47 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
14 GPIO46 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
13 GPIO45 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
12 GPIO44 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
11 GPIO43 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
10 GPIO42 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
9 GPIO41 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
8 GPIO40 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
7 GPIO39 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
6 RESERVED R-0/W 0h Reserved
5 GPIO37 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
4 RESERVED R-0/W 0h Reserved
3 GPIO35 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
2 GPIO34 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
1 GPIO33 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn
0 GPIO32 R-0/W 0h Output Set bit for this pin
Reset type: SYSRSn

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10.10.3.7 GPBCLEAR Register (Offset = Ch) [Reset = 0h]

GPBCLEAR is shown in Figure 10-61 and described in Table 10-72.
Return to the Summary Table.
GPIO B Data Clear Register (GPIO32 to 63)
Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-61. GPBCLEAR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
GPIO39 RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-72. GPBCLEAR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0/W 0h Reserved
30 RESERVED R-0/W 0h Reserved
29 GPIO61 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
28 GPIO60 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
27 GPIO59 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
26 GPIO58 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
25 GPIO57 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
24 GPIO56 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
23 GPIO55 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
22 GPIO54 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
21 GPIO53 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
20 GPIO52 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
19 GPIO51 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
18 GPIO50 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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Table 10-72. GPBCLEAR Register Field Descriptions (continued)

Bit Field Type Reset Description
17 GPIO49 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
16 GPIO48 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
15 GPIO47 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
14 GPIO46 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
13 GPIO45 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
12 GPIO44 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
11 GPIO43 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
10 GPIO42 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
9 GPIO41 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
8 GPIO40 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
7 GPIO39 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
6 RESERVED R-0/W 0h Reserved
5 GPIO37 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
4 RESERVED R-0/W 0h Reserved
3 GPIO35 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
2 GPIO34 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
1 GPIO33 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn
0 GPIO32 R-0/W 0h Output Clear bit for this pin
Reset type: SYSRSn

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10.10.3.8 GPBTOGGLE Register (Offset = Eh) [Reset = 0h]

GPBTOGGLE is shown in Figure 10-62 and described in Table 10-73.
Return to the Summary Table.
GPIO B Data Toggle Register (GPIO32 to 63)
Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.
Figure 10-62. GPBTOGGLE Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

7 6 5 4 3 2 1 0
GPIO39 RESERVED GPIO37 RESERVED GPIO35 GPIO34 GPIO33 GPIO32
R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h R-0/W-0h

Table 10-73. GPBTOGGLE Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0/W 0h Reserved
30 RESERVED R-0/W 0h Reserved
29 GPIO61 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
28 GPIO60 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
27 GPIO59 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
26 GPIO58 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
25 GPIO57 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
24 GPIO56 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
23 GPIO55 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
22 GPIO54 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
21 GPIO53 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
20 GPIO52 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
19 GPIO51 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
18 GPIO50 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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Table 10-73. GPBTOGGLE Register Field Descriptions (continued)

Bit Field Type Reset Description
17 GPIO49 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
16 GPIO48 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
15 GPIO47 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
14 GPIO46 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
13 GPIO45 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
12 GPIO44 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
11 GPIO43 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
10 GPIO42 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
9 GPIO41 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
8 GPIO40 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
7 GPIO39 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
6 RESERVED R-0/W 0h Reserved
5 GPIO37 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
4 RESERVED R-0/W 0h Reserved
3 GPIO35 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
2 GPIO34 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
1 GPIO33 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn
0 GPIO32 R-0/W 0h Output Toggle Register GPIO pin
Reset type: SYSRSn

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10.10.3.9 GPHDAT Register (Offset = 38h) [Reset = 0h]

GPHDAT is shown in Figure 10-63 and described in Table 10-74.
Return to the Summary Table.
GPIO H Data Register (GPIO224 to 255)
Reading this register indicates the current status of the GPIO pin, irrespective of which mode the pin is in.
Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode, otherwise the
value written is latched but ignored. The state of the output register latch will remain in its current state until the
next write operation. A system reset will clear all bits and latched values to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN (after qualification), not the state of the
output latch of the
Figure 10-63. GPHDAT Register
31 30 29 28 27 26 25 24
RESERVED RESERVED GPIO253 GPIO252 GPIO251 RESERVED GPIO249 GPIO248
R/W-0h R/W-0h R-0h R/W-0h R-0h R/W-0h R-0h R-0h

23 22 21 20 19 18 17 16
GPIO247 RESERVED GPIO245 GPIO244 RESERVED GPIO242 GPIO241 GPIO240
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO239 GPIO238 GPIO237 GPIO236 RESERVED RESERVED GPIO233 GPIO232
R/W-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO231 GPIO230 GPIO229 GPIO228 GPIO227 GPIO226 GPIO225 GPIO224
R/W-0h R/W-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 10-74. GPHDAT Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W 0h Reserved
30 RESERVED R/W 0h Reserved
29 GPIO253 R 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
28 GPIO252 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn

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Table 10-74. GPHDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
27 GPIO251 R 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
26 RESERVED R/W 0h Reserved
25 GPIO249 R 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
24 GPIO248 R 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
23 GPIO247 R 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
22 RESERVED R/W 0h Reserved
21 GPIO245 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn

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Table 10-74. GPHDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
20 GPIO244 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
19 RESERVED R/W 0h Reserved
18 GPIO242 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
17 GPIO241 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
16 GPIO240 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
15 GPIO239 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn

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Table 10-74. GPHDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
14 GPIO238 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
13 GPIO237 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
12 GPIO236 R 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
11 RESERVED R/W 0h Reserved
10 RESERVED R/W 0h Reserved
9 GPIO233 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
8 GPIO232 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn

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Table 10-74. GPHDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
7 GPIO231 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
6 GPIO230 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
5 GPIO229 R 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
4 GPIO228 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
3 GPIO227 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn

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Table 10-74. GPHDAT Register Field Descriptions (continued)

Bit Field Type Reset Description
2 GPIO226 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
1 GPIO225 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn
0 GPIO224 R/W 0h Reading this register indicates the current status of this GPIO pin,
irrespective of which mode the pin is in. Writing to this register will
set this GPIO pin high or low if the pin is enabled for GPIO output
mode, otherwise the value written is latched but ignored. The state of
the output register latch will remain in its current state until the next
write operation. A system reset will clear all bits and latched values
to zero.
DESIGNER NOTE:
[1] Reading the GPIODAT register should reflect the state of the PIN
(after qualification), not the state of the output latch of the GPIODAT
register.
Reset type: SYSRSn

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10.10.4 GPIO_DATA_READ_REGS Registers

Table 10-75 lists the memory-mapped registers for the GPIO_DATA_READ_REGS registers. All register offset
addresses not listed in Table 10-75 should be considered as reserved locations and the register contents should
not be modified.
Table 10-75. GPIO_DATA_READ_REGS Registers
Offset Acronym Register Name Write Protection Section
0h GPADAT_R GPIO A Data Read Register Go
2h GPBDAT_R GPIO B Data Read Register Go
Eh GPHDAT_R GPIO H Data Read Register Go

Complex bit access types are encoded to fit into small table cells. Table 10-76 shows the codes that are used for
access types in this section.
Table 10-76. GPIO_DATA_READ_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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10.10.4.1 GPADAT_R Register (Offset = 0h) [Reset = 0h]

GPADAT_R is shown in Figure 10-64 and described in Table 10-77.
Return to the Summary Table.
GPIO A Data Read Register.
Returns the contents of GPADAT register on a read, write to this register has no effect
Figure 10-64. GPADAT_R Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R-0h

Table 10-77. GPADAT_R Register Field Descriptions

Bit Field Type Reset Description
31-0 DATA R 0h A read from this register returns the contents of GPADAT register,
writes have no impact
Reset type: CPU1.SYSRSn

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10.10.4.2 GPBDAT_R Register (Offset = 2h) [Reset = 0h]

GPBDAT_R is shown in Figure 10-65 and described in Table 10-78.
Return to the Summary Table.
GPIO B Data Read Register.
Returns the contents of GPBDAT register on a read, write to this register has no effect
Figure 10-65. GPBDAT_R Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R-0h

Table 10-78. GPBDAT_R Register Field Descriptions

Bit Field Type Reset Description
31-0 DATA R 0h A read from this register returns the contents of GPBDAT register,
writes have no impact
Reset type: CPU1.SYSRSn

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10.10.4.3 GPHDAT_R Register (Offset = Eh) [Reset = 0h]

GPHDAT_R is shown in Figure 10-66 and described in Table 10-79.
Return to the Summary Table.
GPIO H Data Read Register.
Returns the contents of GPHDAT register on a read, write to this register has no effect
Figure 10-66. GPHDAT_R Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R-0h

Table 10-79. GPHDAT_R Register Field Descriptions

Bit Field Type Reset Description
31-0 DATA R 0h A read from this register returns the contents of GPHDAT register,
writes have no impact
Reset type: CPU1.SYSRSn

10.10.5 GPIO Registers to Driverlib Functions

Table 10-80. GPIO Registers to Driverlib Functions
File Driverlib Function
GPACTRL
gpio.c GPIO_setQualificationPeriod
GPAQSEL1
gpio.c GPIO_setQualificationMode
gpio.c GPIO_getQualificationMode
GPAQSEL2
- See GPAQSEL1
GPAMUX1
gpio.c GPIO_setPinConfig
GPAMUX2
- See GPAMUX1
GPADIR
gpio.c GPIO_setDirectionMode
gpio.c GPIO_getDirectionMode
GPAPUD
gpio.c GPIO_setPadConfig
gpio.c GPIO_getPadConfig
GPAINV
gpio.c GPIO_setPadConfig
gpio.c GPIO_getPadConfig
GPAODR
gpio.c GPIO_setPadConfig
gpio.c GPIO_getPadConfig
GPAAMSEL
-
GPAGMUX1
gpio.c GPIO_setPinConfig
GPAGMUX2

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Table 10-80. GPIO Registers to Driverlib Functions (continued)

File Driverlib Function
- See GPAGMUX1
GPACSEL1
gpio.c GPIO_setControllerCore
GPACSEL2
- See GPACSEL1
GPACSEL3
- See GPACSEL1
GPACSEL4
- See GPACSEL1
GPALOCK
gpio.h GPIO_lockPortConfig
gpio.h GPIO_unlockPortConfig
GPACR
gpio.h GPIO_commitPortConfig
GPBCTRL
- See GPACTRL
GPBQSEL1
- See GPAQSEL1
GPBQSEL2
- See GPAQSEL1
GPBMUX1
- See GPAMUX1
GPBMUX2
- See GPAMUX1
GPBDIR
- See GPADIR
GPBPUD
- See GPAPUD
GPBINV
- See GPAINV
GPBODR
- See GPAODR
GPBGMUX1
- See GPAGMUX1
GPBGMUX2
- See GPAGMUX1
GPBCSEL1
- See GPACSEL1
GPBCSEL2
- See GPACSEL1
GPBCSEL3
- See GPACSEL1
GPBCSEL4
- See GPACSEL1
GPBLOCK

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Table 10-80. GPIO Registers to Driverlib Functions (continued)

File Driverlib Function
- See GPALOCK
GPBCR
- See GPACR
GPHCTRL
- See GPACTRL
GPHQSEL1
- See GPAQSEL1
GPHQSEL2
- See GPAQSEL1
GPHMUX1
- See GPAMUX1
GPHMUX2
- See GPAMUX1
GPHINV
- See GPAINV
GPHAMSEL
-
GPHGMUX1
- See GPAGMUX1
GPHGMUX2
- See GPAGMUX1
GPHCSEL1
- See GPACSEL1
GPHCSEL2
- See GPACSEL1
GPHCSEL3
- See GPACSEL1
GPHCSEL4
- See GPACSEL1
GPHLOCK
- See GPALOCK
GPHCR
- See GPACR
GPADAT
gpio.h GPIO_readPin
gpio.h GPIO_readPortData
gpio.h GPIO_writePortData
GPASET
gpio.h GPIO_writePin
gpio.h GPIO_setPortPins
GPACLEAR
gpio.h GPIO_writePin
gpio.h GPIO_clearPortPins
GPATOGGLE
gpio.h GPIO_togglePin

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Table 10-80. GPIO Registers to Driverlib Functions (continued)

File Driverlib Function
gpio.h GPIO_togglePortPins
GPBDAT
- See GPADAT
GPBSET
- See GPASET
GPBCLEAR
- See GPACLEAR
GPBTOGGLE
- See GPATOGGLE
GPHDAT
- See GPADAT
GPADAT_R
-
GPBDAT_R
-
GPHDAT_R
-

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www.ti.com Crossbar (X-BAR)

Chapter 11
Crossbar (X-BAR)

The crossbars (referred to as X-BAR throughout this chapter) provide flexibility to connect device inputs, outputs,
and internal resources in a variety of configurations.
The device contains a total of six X-BARs:
• Input X-BAR
• CLB Input X-BAR
• Output X-BAR
• CLB Output X-BAR
• CLB X-BAR
• ePWM X-BAR
Each of the X-BARs is named according to where the X-BAR takes signals. For example, the Input X-BAR and
CLB Input X-BAR bring external signals “in” to the device. The Output X-BAR and CLB Output X-BAR take
internal signals “out” of the device to a GPIO. The CLB X-BAR and ePWM X-BAR take signals to the CLB and
ePWM modules, respectively.

11.1 Input X-BAR and CLB Input X-BAR ....................................................................................................................1206

11.2 ePWM, CLB, and GPIO Output X-BAR................................................................................................................ 1209
11.3 XBAR Registers.................................................................................................................................................... 1219

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11.1 Input X-BAR and CLB Input X-BAR

On this device, the Input X-BAR is used to route signals from a GPIO to many different IP blocks such as the
ADC, eCAP, ePWM, and external interrupts. The Input X-BAR has access to every GPIO and can route each
signal to any (or multiple) of the IP blocks previously mentioned. The digital input of AIOs are also available on
the Input X-BAR. This flexibility relieves some of the constraints on peripheral muxing by just requiring any GPIO
pin to be available. Note that the function selected on the GPIO mux does not affect the Input X-BAR. The Input
X-BAR simply connects the signal on the input buffer to the selected destination. Therefore, you can do things
such as route the output of one peripheral to another (that is, measure the output of an ePWM with an eCAP for
a frequency test).
The Input X-BAR is configured by way of the INPUTxSELECT registers. The available IP destinations for
each INPUTx is shown in Figure 11-1 and Table 11-1. For more information on configuration, see the
INPUT_XBAR_REGS register definitions in the XBAR Registers section.

GPIO0 Asynchronous
Synchronous Input X-BAR
Sync. + Qual. Other Sources 127:16
GPIOx
eCAP
Modules
INPUT[16:1] 15:0
INPUT16
INPUT15
INPUT14
INPUT13
INPUT12

INPUT10
INPUT11

INPUT6
INPUT5
INPUT4
INPUT3
INPUT2
INPUT1
INPUT9
INPUT8
INPUT7

DCCx Clock Source-1 TZ1,TRIP1

TZ2,TRIP2
DCCx Clock Source-0 TZ3,TRIP3
TRIP6
EPG1

XINT1 TRIP4
XINT2 TRIP5 ePWM
CPU PIE XINT3 Modules
XINT4 TRIP7
XINT5 TRIP8
ePWM TRIP9
X-BAR
TRIP10
TRIP11
TRIP12

Other
Sources
ADC ADCEXTSOC
EXTSYNCIN1 ePWM and eCAP
EXTSYNCIN2 Sync Scheme
Other Sources

Output X-BAR

Figure 11-1. Input X-BAR

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Table 11-1. Input X-BAR Destinations

ADC
EPWM /
ECAP / EPWM X- CLB X- OUTPUT CPU EPWM START OF
INPUT ECAP DCCx EPG ERAD
HRCAP BAR BAR X-BAR XINT TRIP CONVERS
SYNC
ION
TZ1,TRI
1 Yes Yes Yes Yes - - - - - Yes
P1
TZ2,TRI
2 Yes Yes Yes Yes - - - - - Yes
P2
TZ3,TRI
3 Yes Yes Yes Yes - - - - - Yes
P3
4 Yes Yes Yes Yes XINT1 - - - - - Yes
ADCEXTS EXTSYN
5 Yes Yes Yes Yes XINT2 - - - Yes
OC CIN1
EXTSYN
6 Yes Yes Yes Yes XINT3 TRIP6 - - - Yes
CIN2
7 Yes Yes Yes - - - - - - - Yes
8 Yes Yes Yes - - - - - - - Yes
9 Yes Yes Yes - - - - - - - Yes
10 Yes Yes Yes - - - - - - - Yes
11 Yes Yes Yes - - - - - CLK1 - Yes
12 Yes Yes Yes - - - - - CLK1 - Yes
EPG1I
13 Yes Yes Yes - XINT4 - - - - Yes
N1
EPG1I
14 Yes Yes Yes - XINT5 - - - - Yes
N2
EPG1I
15 Yes - - - - - - - CLK1 Yes
N3
EPG1I
16 Yes - - - - - - - CLK0 Yes
N4

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11.1.1 CLB Input X-BAR

The CLB Input X-BAR is architecturally identical to the Input X-BAR. The only difference is the destination for
each INPUTx. The destination for each INPUTx is only the CLB Tiles as shown in Table 11-2. This allows for
GPIOs to be accessed by the CLB tiles without using the combination of Input X-BAR and CLB X-BAR.

Note
Signals routed into the CLB using the XBAR must be synchronized within the CLB.

Table 11-2. CLB Input X-BAR Destinations

INPUT CLB EPWM XBAR DCCx
1 Yes - -
2 Yes - -
3 Yes - -
4 Yes - -
5 Yes - -
6 Yes - -
7 Yes Yes -
8 Yes Yes -
9 Yes Yes -
10 Yes Yes -
11 Yes Yes CLK1
12 Yes Yes CLK1
13 Yes Yes -
14 Yes Yes -
15 Yes - -
16 Yes - -

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11.2 ePWM, CLB, and GPIO Output X-BAR

This section describes the ePWM, CLB, and GPIO Output X-BAR.
11.2.1 ePWM X-BAR
The ePWM X-BAR brings signals to the ePWM modules. Specifically, the ePWM X-BAR is connected to the
Digital Compare (DC) submodule of each ePWM module for actions such as tripzones and syncing. Refer to the
Enhanced Pulse Width Modulator (ePWM) chapter for more information on additional ways the DC submodule
can be used. Figure 11-2 shows the architecture of the ePWM X-BAR. Note that the architecture of the ePWM
X-BAR is identical to the architecture of the GPIO Output X-BAR (with the exception of the output latch).
11.2.1.1 ePWM X-BAR Architecture
The ePWM X-BAR has eight outputs that are routed to each ePWM module. Figure 11-2 represents the
architecture of a single output, but this output is identical to the architecture of all of the other outputs.
First, determine the signals that can be passed to the ePWM by referencing Table 11-3. Select up to one signal
per mux (32 total muxes) for each TRIPx output. Select the inputs to each mux using the TRIPxMUX0TO15CFG
and TRIPxMUX16TO31CFG registers. To pass any signal through to the ePWM, enable the mux in the
TRIPxMUXENABLE register. All muxes that are enabled are logically ORed before being passed on to the
respective TRIPx signal on the ePWM. To optionally invert the signal, use the TRIPOUTINV register.

0.0
0.1 0
0.2
0.3
TRIPxMUXENABLE
(32 bits)
TRIPxMUX0TO15CFG.MUX0

1.0
1.1 1
1.2
1.3

TRIPxMUX0TO15CFG.MUX1

31.0
31.1 TRIPOUTINV
31 (1 bit)
31.2
31.3

TRIPxMUX16TO31CFG.MUX31

Figure 11-2. ePWM X-BAR Architecture - Single Output

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Note
Do not use "Reserved" signals in your application.

Table 11-3. EPWM X-BAR Mux Configuration Table

Mux 0 1 2 3
G0 CMPSS1_CTRIPH CMPSS1_CTRIPH_OR_CTRIPL ADCAEVT1 ECAP1_OUT
G1 CMPSS1_CTRIPL INPUTXBAR1 CLB1_OUT12 ADCCEVT1
G2 CMPSS2_CTRIPH CMPSS2_CTRIPH_OR_CTRIPL ADCAEVT2 ECAP2_OUT
G3 CMPSS2_CTRIPL INPUTXBAR2 CLB1_OUT13 ADCCEVT2
G4 CMPSS3_CTRIPH CMPSS3_CTRIPH_OR_CTRIPL ADCAEVT3 ECAP3_OUT
G5 CMPSS3_CTRIPL INPUTXBAR3 CLB2_OUT12 ADCCEVT3
G6 CMPSS4_CTRIPH CMPSS4_CTRIPH_OR_CTRIPL ADCAEVT4 Reserved
G7 CMPSS4_CTRIPL INPUTXBAR4 CLB2_OUT13 ADCCEVT4
G8 Reserved Reserved ADCBEVT1 Reserved
G9 Reserved INPUTXBAR5 CLB3_OUT12 Reserved
G10 Reserved Reserved ADCBEVT2 Reserved
G11 Reserved INPUTXBAR6 CLB3_OUT13 Reserved
G12 Reserved Reserved ADCBEVT3 Reserved
G13 Reserved ADCSOCAO CLB4_OUT12 Reserved
G14 Reserved Reserved ADCBEVT4 EXTSYNCOUT
G15 Reserved ADCSOCBO CLB4_OUT13 Reserved
G16 SD1FLT1_CEVT1 SD1FLT1_CEVT1_OR_CEVT2 Reserved Reserved
G17 SD1FLT1_CEVT2 INPUTXBAR7 CLBINPUTXBAR7 CLAHALT
G18 SD1FLT2_CEVT1 SD1FLT2_CEVT1_OR_CEVT2 Reserved Reserved
G19 SD1FLT2_CEVT2 INPUTXBAR8 CLBINPUTXBAR8 ERRORSTS
G20 SD1FLT3_CEVT1 SD1FLT3_CEVT1_OR_CEVT2 Reserved FSIRXA_TRIG1
G21 SD1FLT3_CEVT2 INPUTXBAR9 CLBINPUTXBAR9 Reserved
G22 SD1FLT4_CEVT1 SD1FLT4_CEVT1_OR_CEVT2 Reserved Reserved
G23 SD1FLT4_CEVT2 INPUTXBAR10 CLBINPUTXBAR10 Reserved
G24 SD2FLT1_CEVT1 SD2FLT1_CEVT1_OR_CEVT2 Reserved Reserved
G25 SD2FLT1_CEVT2 INPUTXBAR11 MCANA_FEVT0 CLBINPUTXBAR11
G26 SD2FLT2_CEVT1 SD2FLT2_CEVT1_OR_CEVT2 Reserved Reserved
G27 SD2FLT2_CEVT2 INPUTXBAR12 MCANA_FEVT1 CLBINPUTXBAR12
G28 SD2FLT3_CEVT1 SD2FLT3_CEVT1_OR_CEVT2 Reserved Reserved
G29 SD2FLT3_CEVT2 INPUTXBAR13 MCANA_FEVT2 CLBINPUTXBAR13
G30 SD2FLT4_CEVT1 SD2FLT4_CEVT1_OR_CEVT2 Reserved Reserved
G31 SD2FLT4_CEVT2 INPUTXBAR14 ERRORSTS CLBINPUTXBAR14

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11.2.2 CLB X-BAR

The CLB X-BAR brings signals to the CLB modules. Figure 11-3 shows the architecture of the CLB X-BAR.
Note that the architecture of the CLB X-BAR is identical to the architecture of the GPIO Output X-BAR (with the
exception of the output latch).
11.2.2.1 CLB X-BAR Architecture
The CLB X-BAR has eight outputs that are routed to each CLB module. Figure 11-3 represents the architecture
of a single output, but the output is identical to the architecture of all of the other outputs.
First, determine the signals that can be passed to the CLB by referencing Table 11-4. Select up to one
signal per mux (31 total muxes) for each AUXSIGx output. Select the inputs to each mux using the
AUXSIGxMUX0TO15CFG and AUXSIGxMUX16TO31CFG registers. To pass any signal through to the CLB,
enable the mux in the AUXSIGxMUXENABLE register. All muxes that are enabled are logically ORed before
being passed on to the respective AUXSIGx signal on the CLB. To optionally invert the signal, use the
AUXSIGOUTINV register.

0.0
0.1 0
0.2
0.3 AUXSIGxMUXENABLE
(32 bits)

AUXSIGxMUX0TO15CFG.MUX0

1.0
1.1 1
1.2
1.3

AUXSIGx
AUXSIGxMUX0TO15CFG.MUX1

31.0
31.1 AUXSIGOUTINV
31 (1 bits)
31.2
31.3

AUXSIGxMUX16TO31CFG.MUX31

Figure 11-3. CLB X-BAR Architecture - Single Output

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GPIO0 Asynchronous
To Synchronous Input X-BAR
GPIOx Sync. + Qual

CLB
Other INPUT1 – INPUT14 TILE
Sources OUT 4/5

CLB X-BAR

Other AUXSIG0 – AUXSIG7

Sources
CLB INPUT X-BAR CLB

CLB TILE1

GPREG CELL
CLB Global Signals
IN0-7
Local OUT 0-7
Signals

.
CLB Tile Outputs
.
INPUT1 – INPUT16 . Intersect other
Peripherals
CLB TILEx
OUTPUT X-BAR
GPREG CELL
IN0-7
Local OUT 0-7
Signals

All CLB
Tile
Outputs

CLB OUTPUT X-BAR

GPIO MUX

Figure 11-4. GPIO to CLB Tile Connections

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Table 11-4. CLB X-BAR Mux Configuration Table

Mux 0 1 2 3
G0 CMPSS1_CTRIPH CMPSS1_CTRIPH_OR_CTRIPL ADCAEVT1 ECAP1_OUT
G1 CMPSS1_CTRIPL INPUTXBAR1 CLB1_OUT12 ADCCEVT1
G2 CMPSS2_CTRIPH CMPSS2_CTRIPH_OR_CTRIPL ADCAEVT2 ECAP2_OUT
G3 CMPSS2_CTRIPL INPUTXBAR2 CLB1_OUT13 ADCCEVT2
G4 CMPSS3_CTRIPH CMPSS3_CTRIPH_OR_CTRIPL ADCAEVT3 ECAP3_OUT
G5 CMPSS3_CTRIPL INPUTXBAR3 CLB2_OUT12 ADCCEVT3
G6 CMPSS4_CTRIPH CMPSS4_CTRIPH_OR_CTRIPL ADCAEVT4 Reserved
G7 CMPSS4_CTRIPL INPUTXBAR4 CLB2_OUT13 ADCCEVT4
G8 Reserved Reserved ADCBEVT1 Reserved
G9 Reserved INPUTXBAR5 CLB3_OUT12 Reserved
G10 Reserved Reserved ADCBEVT2 Reserved
G11 Reserved INPUTXBAR6 CLB3_OUT13 Reserved
G12 Reserved Reserved ADCBEVT3 Reserved
G13 Reserved ADCSOCAO CLB4_OUT12 Reserved
G14 Reserved Reserved ADCBEVT4 EXTSYNCOUT
G15 Reserved ADCSOCBO CLB4_OUT13 Reserved
G16 SD1FLT1_CEVT1 SD1FLT1_CEVT1_OR_CEVT2 SD1FLT1_COMPZ SD1FLT1_DRINT
G17 SD1FLT1_CEVT2 INPUTXBAR7 Reserved CLAHALT
G18 SD1FLT2_CEVT1 SD1FLT2_CEVT1_OR_CEVT2 SD1FLT2_COMPZ SD1FLT2_DRINT
G19 SD1FLT2_CEVT2 INPUTXBAR8 Reserved ERRORSTS
G20 SD1FLT3_CEVT1 SD1FLT3_CEVT1_OR_CEVT2 SD1FLT3_COMPZ SD1FLT3_DRINT
G21 SD1FLT3_CEVT2 INPUTXBAR9 Reserved Reserved
G22 SD1FLT4_CEVT1 SD1FLT4_CEVT1_OR_CEVT2 SD1FLT4_COMPZ SD1FLT4_DRINT
G23 SD1FLT4_CEVT2 INPUTXBAR10 Reserved Reserved
G24 SD2FLT1_CEVT1 SD2FLT1_CEVT1_OR_CEVT2 SD2FLT1_COMPZ SD2FLT1_DRINT
G25 SD2FLT1_CEVT2 INPUTXBAR11 MCANA_FEVT0 Reserved
G26 SD2FLT2_CEVT1 SD2FLT2_CEVT1_OR_CEVT2 SD2FLT2_COMPZ SD2FLT2_DRINT
G27 SD2FLT2_CEVT2 INPUTXBAR12 MCANA_FEVT1 Reserved
G28 SD2FLT3_CEVT1 SD2FLT3_CEVT1_OR_CEVT2 SD2FLT3_COMPZ SD2FLT3_DRINT
G29 SD2FLT3_CEVT2 INPUTXBAR13 MCANA_FEVT2 Reserved
G30 SD2FLT4_CEVT1 SD2FLT4_CEVT1_OR_CEVT2 SD2FLT4_COMPZ SD2FLT4_DRINT
G31 SD2FLT4_CEVT2 INPUTXBAR14 ERRORSTS Reserved

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11.2.3 GPIO Output X-BAR

The GPIO Output X-BAR takes signals from inside the device and brings them out to a GPIO. Figure 11-5 shows
the architecture of the GPIO Output X-BAR. The X-BAR contains eight outputs and each contains at least one
position on the GPIO mux, denoted as OUTPUTXBARx. The X-BAR allows the selection of a single signal or a
logical-OR of up to 32 signals.
11.2.3.1 GPIO Output X-BAR Architecture
The GPIO Output X-BAR has eight outputs that are routed to the GPIO module. Figure 11-5 represents the
architecture of a single output, but this output is identical to the architecture of all of the other outputs. Note that
the architecture of the Output X-BAR (with the exception of the output latch) is similar to the architecture of the
ePWM X-BAR.
First, determine the signals that can be passed to the GPIO by referencing Table 11-5. Select up to one
signal per mux (32 total muxes) for each OUTPUTXBARx output. Select the inputs to each mux using the
OUTPUTxMUX0TO15CFG and OUTPUTxMUX16TO31CFG registers.
To pass any signal through to the GPIO, enable the mux in the OUTPUTxMUXENABLE register. All muxes that
are enabled are logically ORed before being passed on to the respective OUTPUTx signal on the GPIO module.
To optionally invert the signal, use the OUTPUTINV register. The signal is only recognized on the GPIO, if the
proper OUTPUTx muxing options are selected using the GpioCtrlRegs.GPxMUX and GpioCtrlRegs.GPxGMUX
registers.

0.0
0.1 0
0.2
0.3
OUTPUTxMUXENABLE
(32 bits)
OUTPUTxMUX0TO15CFG.MUX0

1.0
1.1 1
1.2
1.3

OUTPUTx
OUTPUTxMUX0TO15CFG.MUX1

OUTPUTLATCHENABLE
31.0
D Q
31.1 31
31.2 OLAT OUTPUTINV
31.3
Q

OUTPUTxMUX16TO31CFG.MUX31 OUTPUTLATCHFRC OUTPUTLATCHCLR

Figure 11-5. GPIO Output X-BAR Architecture

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Note
Do not use "Reserved" signals in your application.

Table 11-5. Output X-BAR Mux Configuration Table

Mux 0 1 2 3
CMPSS1_CTRIPOUTH_OR_CTRIPO
G0 CMPSS1_CTRIPOUTH ADCAEVT1 ECAP1_OUT
UTL
G1 CMPSS1_CTRIPOUTL INPUTXBAR1 CLB1_OUT12 ADCCEVT1
CMPSS2_CTRIPOUTH_OR_CTRIPO
G2 CMPSS2_CTRIPOUTH ADCAEVT2 ECAP2_OUT
UTL
G3 CMPSS2_CTRIPOUTL INPUTXBAR2 CLB1_OUT13 ADCCEVT2
CMPSS3_CTRIPOUTH_OR_CTRIPO
G4 CMPSS3_CTRIPOUTH ADCAEVT3 ECAP3_OUT
UTL
G5 CMPSS3_CTRIPOUTL INPUTXBAR3 CLB2_OUT12 ADCCEVT3
CMPSS4_CTRIPOUTH_OR_CTRIPO
G6 CMPSS4_CTRIPOUTH ADCAEVT4 Reserved
UTL
G7 CMPSS4_CTRIPOUTL INPUTXBAR4 CLB2_OUT13 ADCCEVT4
G8 Reserved Reserved ADCBEVT1 Reserved
G9 Reserved INPUTXBAR5 CLB3_OUT12 Reserved
G10 Reserved Reserved ADCBEVT2 Reserved
G11 Reserved INPUTXBAR6 CLB3_OUT13 Reserved
G12 Reserved Reserved ADCBEVT3 Reserved
G13 Reserved ADCSOCAO CLB4_OUT12 Reserved
G14 Reserved Reserved ADCBEVT4 EXTSYNCOUT
G15 Reserved ADCSOCBO CLB4_OUT13 Reserved
G16 SD1FLT1_CEVT1 SD1FLT1_CEVT1_OR_CEVT2 Reserved Reserved
G17 SD1FLT1_CEVT2 Reserved Reserved CLAHALT
G18 SD1FLT2_CEVT1 SD1FLT2_CEVT1_OR_CEVT2 Reserved Reserved
G19 SD1FLT2_CEVT2 Reserved Reserved ERRORSTS
G20 SD1FLT3_CEVT1 SD1FLT3_CEVT1_OR_CEVT2 Reserved Reserved
G21 SD1FLT3_CEVT2 Reserved Reserved FSIRXA_TRIG2
G22 SD1FLT4_CEVT1 SD1FLT4_CEVT1_OR_CEVT2 Reserved Reserved
G23 SD1FLT4_CEVT2 Reserved Reserved Reserved
G24 SD2FLT1_CEVT1 SD2FLT1_CEVT1_OR_CEVT2 Reserved Reserved
G25 SD2FLT1_CEVT2 Reserved Reserved Reserved
G26 SD2FLT2_CEVT1 SD2FLT2_CEVT1_OR_CEVT2 Reserved Reserved
G27 SD2FLT2_CEVT2 Reserved Reserved Reserved
G28 SD2FLT3_CEVT1 SD2FLT3_CEVT1_OR_CEVT2 Reserved Reserved
G29 SD2FLT3_CEVT2 Reserved Reserved Reserved
G30 SD2FLT4_CEVT1 SD2FLT4_CEVT1_OR_CEVT2 Reserved EPG1OUT0
G31 SD2FLT4_CEVT2 Reserved ERRORSTS EPG1OUT1

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11.2.4 CLB Output X-BAR

The CLB Output X-BAR takes signals from inside the CLB Tiles and brings them out to a GPIO.
11.2.4.1 CLB Output X-BAR Architecture
The CLB Output X-BAR has eight outputs that are routed to the GPIO module. CLB Output X-BAR architecture
is identical to the architecture of the GPIO Output X-BAR. First, determine the signals that can be passed to the
GPIO by referencing Table 11-6.

Note
Do not use "Reserved" signals in your application.

Table 11-6. CLB Output X-BAR Mux Configuration Table

Mux 0 0.1 0.2 0.3
G0 CLB1_OUT0 Reserved Reserved OUTPUTXBAR1
G1 CLB1_OUT1 Reserved Reserved OUTPUTXBAR2
G2 CLB1_OUT2 Reserved Reserved Reserved
G3 CLB1_OUT3 Reserved Reserved Reserved
G4 CLB1_OUT4 Reserved Reserved Reserved
G5 CLB1_OUT5 Reserved Reserved Reserved
G6 CLB1_OUT6 Reserved Reserved Reserved
G7 CLB1_OUT7 Reserved Reserved Reserved
G8 CLB2_OUT0 Reserved Reserved OUTPUTXBAR3
G9 CLB2_OUT1 Reserved Reserved OUTPUTXBAR4
G10 CLB2_OUT2 Reserved Reserved Reserved
G11 CLB2_OUT3 Reserved Reserved Reserved
G12 CLB2_OUT4 Reserved Reserved Reserved
G13 CLB2_OUT5 Reserved Reserved Reserved
G14 CLB2_OUT6 Reserved Reserved Reserved
G15 CLB2_OUT7 Reserved Reserved Reserved
G16 CLB3_OUT0 Reserved Reserved OUTPUTXBAR5
G17 CLB3_OUT1 Reserved Reserved OUTPUTXBAR6
G18 CLB3_OUT2 Reserved Reserved Reserved
G19 CLB3_OUT3 Reserved Reserved Reserved
G20 CLB3_OUT4 Reserved Reserved Reserved
G21 CLB3_OUT5 Reserved Reserved Reserved
G22 CLB3_OUT6 Reserved Reserved Reserved
G23 CLB3_OUT7 Reserved Reserved Reserved
G24 CLB4_OUT0 Reserved Reserved OUTPUTXBAR7
G25 CLB4_OUT1 Reserved Reserved OUTPUTXBAR8
G26 CLB4_OUT2 Reserved Reserved Reserved
G27 CLB4_OUT3 Reserved Reserved Reserved
G28 CLB4_OUT4 Reserved Reserved Reserved
G29 CLB4_OUT5 Reserved Reserved Reserved
G30 CLB4_OUT6 Reserved Reserved EPG1OUT2
G31 CLB4_OUT7 Reserved Reserved EPG1OUT3

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11.2.5 X-BAR Flags

With the exception of the CMPSS signals, the ePWM X-BAR and the Output X-BAR have all of the same input
signals. Due to the inputs being similar, the ePWM X-BAR and Output X-BAR leverage a single set of input
flags to indicate which input signals have been triggered. This allows software to check the input flags when an
event occurs. See Figure 11-6 for more information. There is a bit allocated for each input signal in one of the
XBARFLGx registers. The flag remains set until cleared through the appropriate XBARCLRx register.

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CTRIPOUTH
CTRIPOUTL (Output X-BAR only)

CMPSSx
CTRIPH
CTRIPL (ePWM X-BAR only)

ePWM and eCAP

EXTSYNCOUT AUXSIG1
Sync Chain
AUXSIG2
AUXSIG3
ADCSOCA0 CLB AUXSIG4
CLB
ADCSOCA0
Select Circuit X-BAR AUXSIG5 Global
AUXSIG6 Mux
ADCSOCB0 AUXSIG7
ADCSOCB0 AUXSIG8
Select Circuit

eCAPx ECAPxOUT TRIP4

TRIP5
EVT1 TRIP7 All
ADCx EVT2 ePWM
TRIP8
EVT3 EPWM
EVT4 TRIP9 Modules
X-BAR TRIP10
TRIP11
INPUT1-6 TRIP12
Input X-BAR INPUT7-14
(ePWM X-BAR only)
eQEPx

OUTPUTXBAR1
OUTPUTXBAR2
OUTPUTXBAR3
Output OUTPUTXBAR4
X-BAR OUTPUTXBAR5
OUTPUTXBAR6
OUTPUTXBAR7
OUTPUTXBAR8

X-BAR Flags GPIO

(shared) Mux

CLB_OUTPUTXBAR1
CLB_OUTPUTXBAR2
CLB CLB_OUTPUTXBAR3
CLB_OUTPUTXBAR4
CLB Input X-BAR CLB TILEx Output CLB_OUTPUTXBAR5
X-BAR CLB_OUTPUTXBAR6
CLB_OUTPUTXBAR7
CLB_OUTPUTXBAR8

Figure 11-6. ePWM and Output X-BARs Sources

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11.3 XBAR Registers

This section describes the Crossbar registers.
11.3.1 XBAR Base Address Table
Table 11-7. XBAR Base Address Table
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 DMA HIC CLA
Instance Structure Protected

INPUT_XBAR_R
InputXbarRegs INPUTXBAR_BASE 0x0000_7900 YES - - - YES
EGS
XbarRegs XBAR_REGS XBAR_BASE 0x0000_7920 YES - - - YES
INPUT_XBAR_R
ClbInputXbarRegs CLBINPUTXBAR_BASE 0x0000_7960 YES - - - YES
EGS
EPWM_XBAR_R
EPwmXbarRegs EPWMXBAR_BASE 0x0000_7A00 YES - - - YES
EGS
CLB_XBAR_REG
ClbXbarRegs CLBXBAR_BASE 0x0000_7A40 YES - - - YES
S
OUTPUT_XBAR_
OutputXbarRegs OUTPUTXBAR_BASE 0x0000_7A80 YES - - - YES
REGS
OUTPUT_XBAR_ CLBOUTPUTXBAR_BA
ClbOutputXbarRegs 0x0000_7BC0 YES - - - YES
REGS SE

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11.3.2 INPUT_XBAR_REGS Registers

Table 11-8 lists the memory-mapped registers for the INPUT_XBAR_REGS registers. All register offset
addresses not listed in Table 11-8 should be considered as reserved locations and the register contents should
not be modified.
Table 11-8. INPUT_XBAR_REGS Registers
Offset Acronym Register Name Write Protection Section
0h INPUT1SELECT INPUT1 Input Select Register (GPIO0 to x) EALLOW Go
1h INPUT2SELECT INPUT2 Input Select Register (GPIO0 to x) EALLOW Go
2h INPUT3SELECT INPUT3 Input Select Register (GPIO0 to x) EALLOW Go
3h INPUT4SELECT INPUT4 Input Select Register (GPIO0 to x) EALLOW Go
4h INPUT5SELECT INPUT5 Input Select Register (GPIO0 to x) EALLOW Go
5h INPUT6SELECT INPUT6 Input Select Register (GPIO0 to x) EALLOW Go
6h INPUT7SELECT INPUT7 Input Select Register (GPIO0 to x) EALLOW Go
7h INPUT8SELECT INPUT8 Input Select Register (GPIO0 to x) EALLOW Go
8h INPUT9SELECT INPUT9 Input Select Register (GPIO0 to x) EALLOW Go
9h INPUT10SELECT INPUT10 Input Select Register (GPIO0 to x) EALLOW Go
Ah INPUT11SELECT INPUT11 Input Select Register (GPIO0 to x) EALLOW Go
Bh INPUT12SELECT INPUT12 Input Select Register (GPIO0 to x) EALLOW Go
Ch INPUT13SELECT INPUT13 Input Select Register (GPIO0 to x) EALLOW Go
Dh INPUT14SELECT INPUT14 Input Select Register (GPIO0 to x) EALLOW Go
Eh INPUT15SELECT INPUT15 Input Select Register (GPIO0 to x) EALLOW Go
Fh INPUT16SELECT INPUT16 Input Select Register (GPIO0 to x) EALLOW Go
1Eh INPUTSELECTLOCK Input Select Lock Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 11-9 shows the codes that are used for
access types in this section.
Table 11-9. INPUT_XBAR_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.

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Table 11-9. INPUT_XBAR_REGS Access Type Codes

(continued)
Access Type Code Description
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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11.3.2.1 INPUT1SELECT Register (Offset = 0h) [Reset = FFFEh]

INPUT1SELECT is shown in Figure 11-7 and described in Table 11-10.
Return to the Summary Table.
INPUT1 Input Select Register (GPIO0 to x)
Figure 11-7. INPUT1SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-FFFEh

7 6 5 4 3 2 1 0
SELECT
R/W-FFFEh

Table 11-10. INPUT1SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W FFFEh Select GPIO for INPUT1 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xFFFD: '1' will be driven to the destination
0xFFFE: '1' will be driven to the destination
0xFFFF: '0' will be driven to the destination
NOTE: SELECT value greater than the available number of GPIO
pins on a device (except 0xFFFF) will cause the destination to be
driven '1'.
Reset type: CPU1.SYSRSn

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11.3.2.2 INPUT2SELECT Register (Offset = 1h) [Reset = FFFEh]

INPUT2SELECT is shown in Figure 11-8 and described in Table 11-11.
Return to the Summary Table.
INPUT2 Input Select Register (GPIO0 to x)
Figure 11-8. INPUT2SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-FFFEh

7 6 5 4 3 2 1 0
SELECT
R/W-FFFEh

Table 11-11. INPUT2SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W FFFEh Select GPIO for INPUT2 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xFFFD: '1' will be driven to the destination
0xFFFE: '1' will be driven to the destination
0xFFFF: '0' will be driven to the destination
NOTE: SELECT value greater than the available number of GPIO
pins on a device (except 0xFFFF) will cause the destination to be
driven '1'.
Reset type: CPU1.SYSRSn

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11.3.2.3 INPUT3SELECT Register (Offset = 2h) [Reset = FFFEh]

INPUT3SELECT is shown in Figure 11-9 and described in Table 11-12.
Return to the Summary Table.
INPUT3 Input Select Register (GPIO0 to x)
Figure 11-9. INPUT3SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-FFFEh

7 6 5 4 3 2 1 0
SELECT
R/W-FFFEh

Table 11-12. INPUT3SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W FFFEh Select GPIO for INPUT3 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xFFFD: '1' will be driven to the destination
0xFFFE: '1' will be driven to the destination
0xFFFF: '0' will be driven to the destination
NOTE: SELECT value greater than the available number of GPIO
pins on a device (except 0xFFFF) will cause the destination to be
driven '1'.
Reset type: CPU1.SYSRSn

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11.3.2.4 INPUT4SELECT Register (Offset = 3h) [Reset = FFFEh]

INPUT4SELECT is shown in Figure 11-10 and described in Table 11-13.
Return to the Summary Table.
INPUT4 Input Select Register (GPIO0 to x)
Figure 11-10. INPUT4SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-FFFEh

7 6 5 4 3 2 1 0
SELECT
R/W-FFFEh

Table 11-13. INPUT4SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W FFFEh Select GPIO for INPUT4 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xFFFD: '1' will be driven to the destination
0xFFFE: '1' will be driven to the destination
0xFFFF: '0' will be driven to the destination
NOTE: SELECT value greater than the available number of GPIO
pins on a device (except 0xFFFF) will cause the destination to be
driven '1'.
Reset type: CPU1.SYSRSn

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11.3.2.5 INPUT5SELECT Register (Offset = 4h) [Reset = FFFEh]

INPUT5SELECT is shown in Figure 11-11 and described in Table 11-14.
Return to the Summary Table.
INPUT5 Input Select Register (GPIO0 to x)
Figure 11-11. INPUT5SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-FFFEh

7 6 5 4 3 2 1 0
SELECT
R/W-FFFEh

Table 11-14. INPUT5SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W FFFEh Select GPIO for INPUT5 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xFFFD: '1' will be driven to the destination
0xFFFE: '1' will be driven to the destination
0xFFFF: '0' will be driven to the destination
NOTE: SELECT value greater than the available number of GPIO
pins on a device (except 0xFFFF) will cause the destination to be
driven '1'.
Reset type: CPU1.SYSRSn

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11.3.2.6 INPUT6SELECT Register (Offset = 5h) [Reset = FFFEh]

INPUT6SELECT is shown in Figure 11-12 and described in Table 11-15.
Return to the Summary Table.
INPUT6 Input Select Register (GPIO0 to x)
Figure 11-12. INPUT6SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-FFFEh

7 6 5 4 3 2 1 0
SELECT
R/W-FFFEh

Table 11-15. INPUT6SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W FFFEh Select GPIO for INPUT6 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xFFFD: '1' will be driven to the destination
0xFFFE: '1' will be driven to the destination
0xFFFF: '0' will be driven to the destination
NOTE: SELECT value greater than the available number of GPIO
pins on a device (except 0xFFFF) will cause the destination to be
driven '1'.
Reset type: CPU1.SYSRSn

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11.3.2.7 INPUT7SELECT Register (Offset = 6h) [Reset = FFFEh]

INPUT7SELECT is shown in Figure 11-13 and described in Table 11-16.
Return to the Summary Table.
INPUT7 Input Select Register (GPIO0 to x)
Figure 11-13. INPUT7SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-FFFEh

7 6 5 4 3 2 1 0
SELECT
R/W-FFFEh

Table 11-16. INPUT7SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W FFFEh Select GPIO for INPUT7 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xFFFD: '1' will be driven to the destination
0xFFFE: '1' will be driven to the destination
0xFFFF: '0' will be driven to the destination
NOTE: SELECT value greater than the available number of GPIO
pins on a device (except 0xFFFF) will cause the destination to be
driven '1'.
Reset type: CPU1.SYSRSn

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11.3.2.8 INPUT8SELECT Register (Offset = 7h) [Reset = FFFEh]

INPUT8SELECT is shown in Figure 11-14 and described in Table 11-17.
Return to the Summary Table.
INPUT8 Input Select Register (GPIO0 to x)
Figure 11-14. INPUT8SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-FFFEh

7 6 5 4 3 2 1 0
SELECT
R/W-FFFEh

Table 11-17. INPUT8SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W FFFEh Select GPIO for INPUT8 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xFFFD: '1' will be driven to the destination
0xFFFE: '1' will be driven to the destination
0xFFFF: '0' will be driven to the destination
NOTE: SELECT value greater than the available number of GPIO
pins on a device (except 0xFFFF) will cause the destination to be
driven '1'.
Reset type: CPU1.SYSRSn

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11.3.2.9 INPUT9SELECT Register (Offset = 8h) [Reset = FFFEh]

INPUT9SELECT is shown in Figure 11-15 and described in Table 11-18.
Return to the Summary Table.
INPUT9 Input Select Register (GPIO0 to x)
Figure 11-15. INPUT9SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-FFFEh

7 6 5 4 3 2 1 0
SELECT
R/W-FFFEh

Table 11-18. INPUT9SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W FFFEh Select GPIO for INPUT9 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xFFFD: '1' will be driven to the destination
0xFFFE: '1' will be driven to the destination
0xFFFF: '0' will be driven to the destination
NOTE: SELECT value greater than the available number of GPIO
pins on a device (except 0xFFFF) will cause the destination to be
driven '1'.
Reset type: CPU1.SYSRSn

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11.3.2.10 INPUT10SELECT Register (Offset = 9h) [Reset = FFFEh]

INPUT10SELECT is shown in Figure 11-16 and described in Table 11-19.
Return to the Summary Table.
INPUT10 Input Select Register (GPIO0 to x)
Figure 11-16. INPUT10SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-FFFEh

7 6 5 4 3 2 1 0
SELECT
R/W-FFFEh

Table 11-19. INPUT10SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W FFFEh Select GPIO for INPUT10 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xFFFD: '1' will be driven to the destination
0xFFFE: '1' will be driven to the destination
0xFFFF: '0' will be driven to the destination
NOTE: SELECT value greater than the available number of GPIO
pins on a device (except 0xFFFF) will cause the destination to be
driven '1'.
Reset type: CPU1.SYSRSn

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11.3.2.11 INPUT11SELECT Register (Offset = Ah) [Reset = FFFEh]

INPUT11SELECT is shown in Figure 11-17 and described in Table 11-20.
Return to the Summary Table.
INPUT11 Input Select Register (GPIO0 to x)
Figure 11-17. INPUT11SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-FFFEh

7 6 5 4 3 2 1 0
SELECT
R/W-FFFEh

Table 11-20. INPUT11SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W FFFEh Select GPIO for INPUT11 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xFFFD: '1' will be driven to the destination
0xFFFE: '1' will be driven to the destination
0xFFFF: '0' will be driven to the destination
NOTE: SELECT value greater than the available number of GPIO
pins on a device (except 0xFFFF) will cause the destination to be
driven '1'.
Reset type: CPU1.SYSRSn

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11.3.2.12 INPUT12SELECT Register (Offset = Bh) [Reset = FFFEh]

INPUT12SELECT is shown in Figure 11-18 and described in Table 11-21.
Return to the Summary Table.
INPUT12 Input Select Register (GPIO0 to x)
Figure 11-18. INPUT12SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-FFFEh

7 6 5 4 3 2 1 0
SELECT
R/W-FFFEh

Table 11-21. INPUT12SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W FFFEh Select GPIO for INPUT12 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xFFFD: '1' will be driven to the destination
0xFFFE: '1' will be driven to the destination
0xFFFF: '0' will be driven to the destination
NOTE: SELECT value greater than the available number of GPIO
pins on a device (except 0xFFFF) will cause the destination to be
driven '1'.
Reset type: CPU1.SYSRSn

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11.3.2.13 INPUT13SELECT Register (Offset = Ch) [Reset = FFFEh]

INPUT13SELECT is shown in Figure 11-19 and described in Table 11-22.
Return to the Summary Table.
INPUT13 Input Select Register (GPIO0 to x)
Figure 11-19. INPUT13SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-FFFEh

7 6 5 4 3 2 1 0
SELECT
R/W-FFFEh

Table 11-22. INPUT13SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W FFFEh Select GPIO for INPUT13 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xFFFD: '1' will be driven to the destination
0xFFFE: '1' will be driven to the destination
0xFFFF: '0' will be driven to the destination
NOTE: SELECT value greater than the available number of GPIO
pins on a device (except 0xFFFF) will cause the destination to be
driven '1'.
Reset type: CPU1.SYSRSn

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11.3.2.14 INPUT14SELECT Register (Offset = Dh) [Reset = FFFEh]

INPUT14SELECT is shown in Figure 11-20 and described in Table 11-23.
Return to the Summary Table.
INPUT14 Input Select Register (GPIO0 to x)
Figure 11-20. INPUT14SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-FFFEh

7 6 5 4 3 2 1 0
SELECT
R/W-FFFEh

Table 11-23. INPUT14SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W FFFEh Select GPIO for INPUT14 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xFFFD: '1' will be driven to the destination
0xFFFE: '1' will be driven to the destination
0xFFFF: '0' will be driven to the destination
NOTE: SELECT value greater than the available number of GPIO
pins on a device (except 0xFFFF) will cause the destination to be
driven '1'.
Reset type: CPU1.SYSRSn

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11.3.2.15 INPUT15SELECT Register (Offset = Eh) [Reset = FFFEh]

INPUT15SELECT is shown in Figure 11-21 and described in Table 11-24.
Return to the Summary Table.
INPUT15 Input Select Register (GPIO0 to x)
Figure 11-21. INPUT15SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-FFFEh

7 6 5 4 3 2 1 0
SELECT
R/W-FFFEh

Table 11-24. INPUT15SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W FFFEh Select GPIO for INPUT15 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xFFFD: '1' will be driven to the destination
0xFFFE: '1' will be driven to the destination
0xFFFF: '0' will be driven to the destination
NOTE: SELECT value greater than the available number of GPIO
pins on a device (except 0xFFFF) will cause the destination to be
driven '1'.
Reset type: CPU1.SYSRSn

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11.3.2.16 INPUT16SELECT Register (Offset = Fh) [Reset = FFFEh]

INPUT16SELECT is shown in Figure 11-22 and described in Table 11-25.
Return to the Summary Table.
INPUT16 Input Select Register (GPIO0 to x)
Figure 11-22. INPUT16SELECT Register
15 14 13 12 11 10 9 8
SELECT
R/W-FFFEh

7 6 5 4 3 2 1 0
SELECT
R/W-FFFEh

Table 11-25. INPUT16SELECT Register Field Descriptions

Bit Field Type Reset Description
15-0 SELECT R/W FFFEh Select GPIO for INPUT16 signal:
0x0 : Select GPIO0
0x1 : Select GPIO1
0x2 : Select GPIO2
...
0xFFFD: '1' will be driven to the destination
0xFFFE: '1' will be driven to the destination
0xFFFF: '0' will be driven to the destination
NOTE: SELECT value greater than the available number of GPIO
pins on a device (except 0xFFFF) will cause the destination to be
driven '1'.
Reset type: CPU1.SYSRSn

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11.3.2.17 INPUTSELECTLOCK Register (Offset = 1Eh) [Reset = 0h]

INPUTSELECTLOCK is shown in Figure 11-23 and described in Table 11-26.
Return to the Summary Table.
Input Select Lock Register.
Any bit in this register, once set can only be cleared through SYSRSn. Write of 0 to any bit of this register has no
effect. Reads to the registers which have LOCK protection are always allowed.
Figure 11-23. INPUTSELECTLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
INPUT16SELE INPUT15SELE INPUT14SELE INPUT13SELE INPUT12SELE INPUT11SELE INPUT10SELE INPUT9SELEC
CT CT CT CT CT CT CT T
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
INPUT8SELEC INPUT7SELEC INPUT6SELEC INPUT5SELEC INPUT4SELEC INPUT3SELEC INPUT2SELEC INPUT1SELEC
T T T T T T T T
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 11-26. INPUTSELECTLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 INPUT16SELECT R/WSonce 0h Lock bit for INPUT16SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
14 INPUT15SELECT R/WSonce 0h Lock bit for INPUT15SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
13 INPUT14SELECT R/WSonce 0h Lock bit for INPUT14SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
12 INPUT13SELECT R/WSonce 0h Lock bit for INPUT13SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
11 INPUT12SELECT R/WSonce 0h Lock bit for INPUT12SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
10 INPUT11SELECT R/WSonce 0h Lock bit for INPUT11SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
9 INPUT10SELECT R/WSonce 0h Lock bit for INPUT10SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

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Table 11-26. INPUTSELECTLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
8 INPUT9SELECT R/WSonce 0h Lock bit for INPUT9SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
7 INPUT8SELECT R/WSonce 0h Lock bit for INPUT8SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
6 INPUT7SELECT R/WSonce 0h Lock bit for INPUT7SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
5 INPUT6SELECT R/WSonce 0h Lock bit for INPUT6SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
4 INPUT5SELECT R/WSonce 0h Lock bit for INPUT5SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
3 INPUT4SELECT R/WSonce 0h Lock bit for INPUT4SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
2 INPUT3SELECT R/WSonce 0h Lock bit for INPUT3SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
1 INPUT2SELECT R/WSonce 0h Lock bit for INPUT2SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn
0 INPUT1SELECT R/WSonce 0h Lock bit for INPUT1SELECT Register
0: Register is not locked
1: Register is locked
Reset type: CPU1.SYSRSn

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11.3.3 XBAR_REGS Registers

Table 11-27 lists the memory-mapped registers for the XBAR_REGS registers. All register offset addresses
not listed in Table 11-27 should be considered as reserved locations and the register contents should not be
modified.
Table 11-27. XBAR_REGS Registers
Offset Acronym Register Name Write Protection Section
0h XBARFLG1 X-Bar Input Flag Register 1 Go
2h XBARFLG2 X-Bar Input Flag Register 2 Go
4h XBARFLG3 X-Bar Input Flag Register 3 Go
6h XBARFLG4 X-Bar Input Flag Register 4 Go
8h XBARCLR1 X-Bar Input Flag Clear Register 1 Go
Ah XBARCLR2 X-Bar Input Flag Clear Register 2 Go
Ch XBARCLR3 X-Bar Input Flag Clear Register 3 Go
Eh XBARCLR4 X-Bar Input Flag Clear Register 4 Go

Complex bit access types are encoded to fit into small table cells. Table 11-28 shows the codes that are used for
access types in this section.
Table 11-28. XBAR_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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11.3.3.1 XBARFLG1 Register (Offset = 0h) [Reset = 0h]

XBARFLG1 is shown in Figure 11-24 and described in Table 11-29.
Return to the Summary Table.
X-Bar Input Flag Register 1
Figure 11-24. XBARFLG1 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
CMPSS4_CTRI CMPSS4_CTRI CMPSS3_CTRI CMPSS3_CTRI CMPSS2_CTRI CMPSS2_CTRI CMPSS1_CTRI CMPSS1_CTRI
POUTH POUTL POUTH POUTL POUTH POUTL POUTH POUTL
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
CMPSS4_CTRI CMPSS4_CTRI CMPSS3_CTRI CMPSS3_CTRI CMPSS2_CTRI CMPSS2_CTRI CMPSS1_CTRI CMPSS1_CTRI
PH PL PH PL PH PL PH PL
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 11-29. XBARFLG1 Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R 0h Reserved
30 RESERVED R 0h Reserved
29 RESERVED R 0h Reserved
28 RESERVED R 0h Reserved
27 RESERVED R 0h Reserved
26 RESERVED R 0h Reserved
25 RESERVED R 0h Reserved
24 RESERVED R 0h Reserved
23 CMPSS4_CTRIPOUTH R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
22 CMPSS4_CTRIPOUTL R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
21 CMPSS3_CTRIPOUTH R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

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Table 11-29. XBARFLG1 Register Field Descriptions (continued)

Bit Field Type Reset Description
20 CMPSS3_CTRIPOUTL R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
19 CMPSS2_CTRIPOUTH R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
18 CMPSS2_CTRIPOUTL R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
17 CMPSS1_CTRIPOUTH R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
16 CMPSS1_CTRIPOUTL R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
15 RESERVED R 0h Reserved
14 RESERVED R 0h Reserved
13 RESERVED R 0h Reserved
12 RESERVED R 0h Reserved
11 RESERVED R 0h Reserved
10 RESERVED R 0h Reserved
9 RESERVED R 0h Reserved
8 RESERVED R 0h Reserved
7 CMPSS4_CTRIPH R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
6 CMPSS4_CTRIPL R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

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Table 11-29. XBARFLG1 Register Field Descriptions (continued)

Bit Field Type Reset Description
5 CMPSS3_CTRIPH R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
4 CMPSS3_CTRIPL R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
3 CMPSS2_CTRIPH R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
2 CMPSS2_CTRIPL R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
1 CMPSS1_CTRIPH R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
0 CMPSS1_CTRIPL R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

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11.3.3.2 XBARFLG2 Register (Offset = 2h) [Reset = 0h]

XBARFLG2 is shown in Figure 11-25 and described in Table 11-30.
Return to the Summary Table.
X-Bar Input Flag Register 2
Figure 11-25. XBARFLG2 Register
31 30 29 28 27 26 25 24
ADCCEVT1 ADCBEVT4 ADCBEVT3 ADCBEVT2 ADCBEVT1 ADCAEVT4 ADCAEVT3 ADCAEVT2
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
ADCAEVT1 EXTSYNCOUT RESERVED RESERVED RESERVED ECAP3_OUT ECAP2_OUT ECAP1_OUT
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
INPUT14 INPUT13 INPUT12 INPUT11 INPUT10 INPUT9 INPUT8 INPUT7
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
ADCSOCB ADCSOCA INPUT6 INPUT5 INPUT4 INPUT3 INPUT2 INPUT1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 11-30. XBARFLG2 Register Field Descriptions

Bit Field Type Reset Description
31 ADCCEVT1 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
30 ADCBEVT4 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
29 ADCBEVT3 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
28 ADCBEVT2 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
27 ADCBEVT1 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

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Table 11-30. XBARFLG2 Register Field Descriptions (continued)

Bit Field Type Reset Description
26 ADCAEVT4 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
25 ADCAEVT3 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
24 ADCAEVT2 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
23 ADCAEVT1 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
22 EXTSYNCOUT R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
21 RESERVED R 0h Reserved
20 RESERVED R 0h Reserved
19 RESERVED R 0h Reserved
18 ECAP3_OUT R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
17 ECAP2_OUT R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
16 ECAP1_OUT R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

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Table 11-30. XBARFLG2 Register Field Descriptions (continued)

Bit Field Type Reset Description
15 INPUT14 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
14 INPUT13 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
13 INPUT12 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
12 INPUT11 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
11 INPUT10 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
10 INPUT9 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
9 INPUT8 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
8 INPUT7 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

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Table 11-30. XBARFLG2 Register Field Descriptions (continued)

Bit Field Type Reset Description
7 ADCSOCB R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
6 ADCSOCA R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
5 INPUT6 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
4 INPUT5 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
3 INPUT4 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
2 INPUT3 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
1 INPUT2 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
0 INPUT1 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

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11.3.3.3 XBARFLG3 Register (Offset = 4h) [Reset = 0h]

XBARFLG3 is shown in Figure 11-26 and described in Table 11-31.
Return to the Summary Table.
X-Bar Input Flag Register 3
Figure 11-26. XBARFLG3 Register
31 30 29 28 27 26 25 24
SD1FLT4_DRIN SD1FLT4_COM SD1FLT3_DRIN SD1FLT3_COM SD1FLT2_DRIN SD1FLT2_COM SD1FLT1_DRIN SD1FLT1_COM
T PZ T PZ T PZ T PZ
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
RESERVED SD2FLT4_COM SD2FLT4_COM SD2FLT3_COM SD2FLT3_COM SD2FLT2_COM SD2FLT2_COM SD2FLT1_COM
PH PL PH PL PH PL PH
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
SD2FLT1_COM SD1FLT4_COM SD1FLT4_COM SD1FLT3_COM SD1FLT3_COM SD1FLT2_COM SD1FLT2_COM SD1FLT1_COM
PL PH PL PH PL PH PL PH
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
SD1FLT1_COM RESERVED RESERVED RESERVED RESERVED ADCCEVT4 ADCCEVT3 ADCCEVT2
PL
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 11-31. XBARFLG3 Register Field Descriptions

Bit Field Type Reset Description
31 SD1FLT4_DRINT R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
30 SD1FLT4_COMPZ R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
29 SD1FLT3_DRINT R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
28 SD1FLT3_COMPZ R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

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Table 11-31. XBARFLG3 Register Field Descriptions (continued)

Bit Field Type Reset Description
27 SD1FLT2_DRINT R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
26 SD1FLT2_COMPZ R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
25 SD1FLT1_DRINT R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
24 SD1FLT1_COMPZ R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
23 RESERVED R 0h Reserved
22 SD2FLT4_COMPH R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
21 SD2FLT4_COMPL R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
20 SD2FLT3_COMPH R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
19 SD2FLT3_COMPL R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

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Table 11-31. XBARFLG3 Register Field Descriptions (continued)

Bit Field Type Reset Description
18 SD2FLT2_COMPH R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
17 SD2FLT2_COMPL R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
16 SD2FLT1_COMPH R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
15 SD2FLT1_COMPL R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
14 SD1FLT4_COMPH R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
13 SD1FLT4_COMPL R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
12 SD1FLT3_COMPH R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
11 SD1FLT3_COMPL R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

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Table 11-31. XBARFLG3 Register Field Descriptions (continued)

Bit Field Type Reset Description
10 SD1FLT2_COMPH R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
9 SD1FLT2_COMPL R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
8 SD1FLT1_COMPH R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
7 SD1FLT1_COMPL R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
6 RESERVED R 0h Reserved
5 RESERVED R 0h Reserved
4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 ADCCEVT4 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
1 ADCCEVT3 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
0 ADCCEVT2 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

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11.3.3.4 XBARFLG4 Register (Offset = 6h) [Reset = 0h]

XBARFLG4 is shown in Figure 11-27 and described in Table 11-32.
Return to the Summary Table.
X-Bar Input Flag Register 4
Figure 11-27. XBARFLG4 Register
31 30 29 28 27 26 25 24
CLAHALT RESERVED RESERVED ERRORSTS_E RESERVED RESERVED RESERVED RESERVED
RROR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
CLB4_5_1 CLB4_4_1 CLB3_5_1 CLB3_4_1 CLB2_5_1 CLB2_4_1 CLB1_5_1 CLB1_4_1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED MCANA_FEVT MCANA_FEVT MCANA_FEVT RESERVED
2 1 0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
SD2FLT4_DRIN SD2FLT4_COM SD2FLT3_DRIN SD2FLT3_COM SD2FLT2_DRIN SD2FLT2_COM SD2FLT1_DRIN SD2FLT1_COM
T PZ T PZ T PZ T PZ
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 11-32. XBARFLG4 Register Field Descriptions

Bit Field Type Reset Description
31 CLAHALT R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
30 RESERVED R 0h Reserved
29 RESERVED R 0h Reserved
28 ERRORSTS_ERROR R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: ERRORSTS_ERROR input was triggered
0: ERRORSTS_ERROR Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
27 RESERVED R 0h Reserved
26 RESERVED R 0h Reserved
25 RESERVED R 0h Reserved
24 RESERVED R 0h Reserved
23 CLB4_5_1 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

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Table 11-32. XBARFLG4 Register Field Descriptions (continued)

Bit Field Type Reset Description
22 CLB4_4_1 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
21 CLB3_5_1 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
20 CLB3_4_1 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
19 CLB2_5_1 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
18 CLB2_4_1 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
17 CLB1_5_1 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
16 CLB1_4_1 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
15 RESERVED R 0h Reserved
14 RESERVED R 0h Reserved
13 RESERVED R 0h Reserved
12 RESERVED R 0h Reserved
11 MCANA_FEVT2 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: MCANA_FEVT2 input was triggered
0: MCANA_FEVT2 Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023 TMS320F28003x Real-Time Microcontrollers 1253
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Table 11-32. XBARFLG4 Register Field Descriptions (continued)

Bit Field Type Reset Description
10 MCANA_FEVT1 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: MCANA_FEVT1 input was triggered
0: MCANA_FEVT1 Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
9 MCANA_FEVT0 R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: MCANA_FEVT0 input was triggered
0: MCANA_FEVT0 Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
8 RESERVED R 0h Reserved
7 SD2FLT4_DRINT R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
6 SD2FLT4_COMPZ R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
5 SD2FLT3_DRINT R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
4 SD2FLT3_COMPZ R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
3 SD2FLT2_DRINT R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
2 SD2FLT2_COMPZ R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

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Table 11-32. XBARFLG4 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 SD2FLT1_DRINT R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn
0 SD2FLT1_COMPZ R 0h This register is used to Flag the inputs of the X-Bars to provide
software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
Note:
[1] setting of this bit has priority over clear by software
Reset type: CPU1.SYSRSn

SPRUIW9B – OCTOBER 2021 – REVISED JUNE 2023 TMS320F28003x Real-Time Microcontrollers 1255
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11.3.3.5 XBARCLR1 Register (Offset = 8h) [Reset = 0h]

XBARCLR1 is shown in Figure 11-28 and described in Table 11-33.
Return to the Summary Table.
X-Bar Input Flag Clear Register 1
Figure 11-28. XBARCLR1 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

23 22 21 20 19 18 17 16
CMPSS4_CTRI CMPSS4_CTRI CMPSS3_CTRI CMPSS3_CTRI CMPSS2_CTRI CMPSS2_CTRI CMPSS1_CTRI CMPSS1_CTRI
POUTH POUTL POUTH POUTL POUTH POUTL POUTH POUTL
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
CMPSS4_CTRI CMPSS4_CTRI CMPSS3_CTRI CMPSS3_CTRI CMPSS2_CTRI CMPSS2_CTRI CMPSS1_CTRI CMPSS1_CTRI
PH PL PH PL PH PL PH PL
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 11-33. XBARCLR1 Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0/W1S 0h Reserved
30 RESERVED R-0/W1S 0h Reserved
29 RESERVED R-0/W1S 0h Reserved
28 RESERVED R-0/W1S 0h Reserved
27 RESERVED R-0/W1S 0h Reserved
26 RESERVED R-0/W1S 0h Reserved
25 RESERVED R-0/W1S 0h Reserved
24 RESERVED R-0/W1S 0h Reserved
23 CMPSS4_CTRIPOUTH R-0/W1S 0h Writing 1 to a bit in this register clears the corresponding bit in the
XBARFLG1 register.
Writing 0 has no effect
Reset type: CPU1.SYSRSn
22 CMPSS4_CTRIPOUTL R-0/W1S 0h Writing 1 to a bit in this register clears the corresponding bit in the
XBARFLG1 register.
Writing 0 has no effect
Reset type: CPU1.SYSRSn
21 CMPSS3_CTRIPOUTH R-0/W1S 0h Writing 1 to a bit in this register clears the corresponding bit in the
XBARFLG1 register.
Writing 0 has no effect
Reset type: CPU1.SYSRSn
20 CMPSS3_CTRIPOUTL R-0/W1S 0h Writing 1 to a bit in this register clears the corresponding bit in the
XBARFLG1 register.
Writing 0 has no effect
Reset type: CPU1.SYSRSn
19 CMPSS2_CTRIPOUTH R-0/W1S 0h Writing 1 to a bit in this register clears the corresponding bit in the
XBARFLG1 register.
Writing 0 has no effect
Reset type: CPU1.SYSRSn

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Table 11-33. XBARCLR1 Register Field Descriptions (continued)

Bit Field Type Reset Description
18 CMPSS2_CTRIPOUTL R-0/W1S 0h Writing 1 to a bit in this register clears the corresponding bit in the
XBARFLG1 register.
Writing 0 has no effect
Reset type: CPU1.SYSRSn
17 CMPSS1_CTRIPOUTH R-0/W1S 0h Writing 1 to a bit in this register clears the corresponding bit in the
XBARFLG1 register.
Writing 0 has no effect
Reset type: CPU1.SYSRSn
16 CMPSS1_CTRIPOUTL R-0/W1S 0h Writing 1 to a bit in this register clears the corresponding bit in the
XBARFLG1 register.
Writing 0 has no effect
Reset type: CPU1.SYSRSn
15 RESERVED R-0/W1S 0h Reserved
14 RESERVED R-0/W1S 0h Reserved
13 RESERVED R-0/W1S 0h Reserved
12 RESERVED R-0/W1S 0h Reserved
11 RESERVED R-0/W1S 0h Reserved
10 RESERVED R-0/W1S 0h Reserved
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 CMPSS4_CTRIPH R-0/W1S 0h Writing 1 to a bit in this register clears the corresponding bit in the
XBARFLG1 register.
Writing 0 has no effect
Reset type: CPU1.SYSRSn
6 CMPSS4_CTRIPL R-0/W1S 0h Writing 1 to a bit in this register clears the corresponding bit in the
XBARFLG1 register.
Writing 0 has no effect