Voltage Stability Enhancement by Optimal Placement
Voltage Stability Enhancement by Optimal Placement
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K.K. Ray
Indian Institute of Technology Kharagpur
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⎢ G ⎥ = ⎢ GL GG ⎥ ⎢ G ⎥
(1)
* Associate Professor & Senior Professor, School of Electrical Sci-
⎣ I ⎦ ⎣K Y ⎦ ⎣V ⎦
ences, Power Electronics and Drives Division, VIT University, India.
+91 9791114931([email protected], [email protected] )
Where ZLL, FLG, KGL, and YGG are sub-block of matrix
** Under graduate Scholar, School of Electrical Sciences, VIT Univer-
H; VG, IG, VL, IL are voltage and current vector of PV buses
sity, Vellore, India.
and load buses respectively. Voltage stability index Lj for
Received 2 September 2008; Accepted 10 August 2009
any load bus can be defined as given in equation (2)
M.Kowsalya, K.K.Ray, Udai Shipurkar and Saranathan 311
g
Vi
Lj = 1 − ∑F ji
Vj
(2)
i =1
4. Methodology
Fig. 7. L-index vs. load bus for the WSCC 9-bus system
Fig. 5. L-index vs. load bus for each load bus after inclusion of UPFC in the Optimized position
M.Kowsalya, K.K.Ray, Udai Shipurkar and Saranathan 313
7. Conclusions
A pictorial representation is the bar graph of fig 10 M.Kowsalya She received B.E degr
which shows the reduction in the value of ΣL2 depicting an ee in electrical and electronics engi
increase in the overall stability neering and M.E degree in from A
nnamalai University, 1995 and 1997.
Her research interests are power s
Acknowledgements ystem stability, power electronics ap
plications in power systems.
This work was supported by the Vellore Institute of
Technology University, Vellore, Tamilnadu, India, 632014.