EE204

Logic Circuits
Lecture Notes
Part-3 Sequential Circuits

Avni Morgül
ANALYSIS OF
CLOCKED SEQUENTIAL
CIRCUITS
ANALYSIS OF
CLOCKED SEQUENTIAL CIRCUITS
• The behavior of a clocked sequential circuit can be described
algebraically by means of state equations.
• The State is the logic value of the flip-flop output variable(s) at a
given time.
• A state equation specifies the next state as a function of the present
state and inputs. Example:
A(t+1)=A(t) x + B(t) x
Where
A(t+1): Next State;
A(t), B(t): Present States;
x : Input variable
STATE DIAGRAM
• The state diagram is a pictorial guide used to describe the state to state
transitions. It is an equivalent tool of the truth table of combinational circuit.
Combinational Analysis  Truth Table
Sequential Analysis  State Diagram b
Previous state
Output for
state c
Next state c Present state
input code Q 1Q 2
XX/ZZ YY/WW
Next state Next state
d e

State Diagram
STATE DIAGRAM EXAMPLE
• Problem: A sequential circuit which has an input x, two outputs A, B. The
output changes from 00 to 01, 10, 11 if x=1, it holds the present state if x=0
at any time. Draw the state diagram.

State A B
x Seq. A a 0 0
CLK Circuit B b 0 1
c 1 0
d 1 1
STATE DIAGRAM EXAMPLE
• A sequential circuit which has an input x, two outputs A, B. The output
changes from 00 to 01, 10, 11 if x=1, it holds the present state if x=0 at any
time. Draw the state diagram.
0/00
Branch format: x/AB
State A B a
x Seq. A a 0 0 00 1/11
1/00
CLK Circuit B b 0 1 0/01 0/11
c 1 0 b d
d 1 1 01 11
1/01 c The
1/10
10 State
0/10 Diagram
 STATE DIAGRAM EXAMPLE
• A sequential circuit which has an input x, two outputs A, B. The output
changes from 00 to 01, 10, 11 if x=1, it holds the present state if x=0 at any
time. Draw the state diagram.
0/00
Branch format: x/AB
State A B a
x Seq. A a 0 0 00 1/11
1/00
CLK Circuit B b 0 1 0/01 0/11
c 1 0 b d
d 1 1 01 11

Sequences for x=1: 00  01  10  11  00 1/01 c The

1/10
10 State
cloc # 1 2 3 4 0/10 Diagram
time
state 00 01 10 11 00
 ANALYSIS PROCEDURE
Analysis of a sequantial circuit means that
obtaining the state transition diagram of the
circuit of which the circuit diagram is given.
x
A
The procedure: D1 Q
1. Identify the
• INPUT (Next State) DECODER y
Q A
• MEMORY
• OUTPUT DECODER
2. Write the Boolean expression for B Output
each of the outputs of the Next State D2 Q Decoder
decoder, inputs of MEMORY
elements (FFs) Input
Decoder Q B
A(t+1)=D1(t)=Ax+Bx
B(t+1)=D2(t)= Ax clock
Memory
Elements
3. Write the output expression
Example Circuit
y = x (A+B)
ANALYSIS PRECEDURE
4. By using the equations (or using the Karnough maps) perform the
present and next state map.
5. Determine the NEXT STATE by using this maps and the characteristic
tables of FFs
6. Plot the STATE DIAGRAM by using this map.
Present Next State Next
Input Output A(t+1) = D1(t) =Ax+Bx 0/0
State Input Code State
A B x DA DB y A B B(t+1) = D2(t) = Ax Branch format: x/y
y = x (A+B)
0 0 0 0 0 0 0 0 1/0 00
0/1
0 0 1 0 1 0 0 1 0/1
D=1
0 1 0 0 0 1 0 0 01 0/1 10 1/0
D=0 D=1
0 1 1 1 1 0 1 1 0 1
1/0
1 0 0 0 0 1 0 0 11 1/0 State: AB
1 0 1 1 0 0 1 0 D=0
1 1 0 0 0 1 0 0 STATE DIAGRAM
of D flip-flop STATE DIAGRAM of the system
1 1 1 1 0 0 1 0
Present-Next STATE Map
 Analysis Example 2 Present
State
A B
Input Next State Input Code Output
x SA RA SB RB y
Next
State
A B
x
x A 0 0 0 0 0 0 0 0 0 0
S Q 0 0 1 0 1 1 0 0 0 1
B
0 1 0 1 0 0 0 0 1 1
0 1 1 0 0 1 0 0 0 1
x A y y = xAB
R Q 1 0 0 0 0 0 1 0 1 0
B
1 0 1 0 1 0 0 1 0 0
Output
x B Decoder 1 1 0 1 0 0 1 0 1 0
S Q 1 1 1 0 0 0 0 0 1 1
A

STATE DIAGRAM 0/0 Branch format: x/y

x B of the circuit
R Q 1/0 00
A 1/1
SR=10 1/0
SR=0Ø SR=Ø0 01 10 0/0
Input Memory 0 1
clock

Decoder Elements 0/0

11 0/0 State: AB
SR=01
LOGIC DIAGRAM of the circuit STATE DIAGRAM of SR flip-flop 1/0

Result: If x=0 the circuit remains at 00 state. If x is set to 1 once and goes back to 0, it goes to 01 and continuos to states 11,
10 and stops there. Then, if input x=1 again it goes to 00 and generates an outpu 1 during the last transition and stops.
Registers and
Counters
 Registers, Latches
• A register is a group of flip‐flops, each one of which shares a common
clock and is capable of storing one bit of information. Registers use edge
triggered flip-flops. If the flip-flops are sensitive to pulse duration it is
called a latch.
• A register capable of shifting the binary information to its neighboring cell,
in a selected direction, is called a shift register.
A1 A2 An
Data Data
D Q D Q D Q
Q Q Q in out
D D D
Clk
Clk
I1 I2 In
Latch or Register
(It is n-bit memory element. The data is lodaed when Shift register
the clock goes high and stored until the next clock signal) The input data is sifted to the next FF for every clock
 Universal Shift Register
Bidirectional Shift Register
with Parallel Load

s1s0= 01 (Select inp.1) shift‐right

s1s0= 10 (Select inp.2) shift‐left
s1s0= 11 (Select inp.3) latch the input
s1s0= 00 (Select inp.0) no change
 COUNTERS
• A counter is essentially a register that goes through a predetermined sequence
of binary states.
• There is two types of counters:
1. Synchronous Counters: The clock inputs of all FFs are connected to a
common clock signal. So, all FFs change state at the same time.
2. Asynchronous Counters: The clock input of FFs is connected to the
output of the previous FF. So, each FF changes the state in different times.

1. Synchronous Counters
a) Design of synchronous counters is similar to any other sequential circuit
design. The state transition diagrams of binary counter is shown in the
next page
Asynchronous Counters
1. Asynchronous Counters
a. Asynchronous Binary Ripple Counter
A0 A1 An-1
0 1 2 3 4 5 6 7 8
input
1 T Q 1 T Q 1 T Q
A0
A1
Q Q Q A2
Negative Edge
Triggered T- FF Counts up to (2n-1) Input/Output waveforms
Binary Down Counter
• Binary Down Counter: A binary counter with reverse count sequence is called «Down
Counter». It is possible to implement it by using negative or positive edge triggred FFs.
A0 A1 An-1
7 6 5 4 3 2 1 0 7
1 T Q 1 T Q 1 T Q input

input
A0
Q Q Q A1
A2
Negative Edge
Triggered FF Counts fron (2n-1) down to 0 Input/Output waveforms
A0 A1 An-1
7 6 4 5 3 2 1 0
1 T Q 1 T Q 1 T Q input

input
A0
Q Q Q A1
A2
Positive Edge
Triggered FF Counts from (2n-1) down to 0 Input/Output waveforms
 BCD (Binary Coded Decimal) Counter
0 1 2 3 4 5 6 7 8 9 0 • Q1 toggles (J1=K1=1)
input
Q1 • Q2 toggles if Q8=0, cleared if Q8=1 (J2=Q8)
Q2 • Q4 toggles with Q2’s low going edge
Q4
Q8 • Q8 set if Q2 Q4=1 at the low going edge of Q1
J=1 • Q8 reset if Q2 Q4=0 at the low going edge of Q1
J=0 K=0
0 1

K=1
Q1 Q2 Q4 Q8

1 J Q J Q 1 J Q J Q

input
1 K Q 1 K Q 1 K Q 1 K Q
 BCD (Binary Coded Decimal) Counter
0 1 2 3 4 5 6 7 8 9 0 • Q1 toggles (J1=K1=1)
input
Q1 • Q2 toggles if Q8=0, cleared if Q8=1 (J2=Q8)
Q2 • Q4 toggles with Q2’s low going edge
Q4
Q8 • Q8 set if Q2 Q4=1 at the low going edge of Q1
J=1 • Q8 reset if Q2 Q4=0 at the low going edge of Q1
J=0 K=0
0 1

Q1 K=1
Q2 Q4 Q8 BCD Counters can be cascaded
1's 10's
1 J Q J Q 1 J Q J Q Q1 Q 2 Q 4 Q 8 Q1 Q2 Q4 Q8
carry carry
input
1 K Q 1 K Q 1 K Q 1 K Q input
4 Flip-Flops 4 Flip-Flops

Nmax=99
Design of
Sequential Circuits
Design of Sequential Circuits
Design of a sequential circuit means that obtaining the circuit diagram of a logic
system of which the input-output function is given.
Design steps:
1. Receive the design specifications
2. Study the real operational behavior of the system
3. Make a block diagram model. Identify and name all inputs and outputs. Understand
when the outputs are to be generated.
4. Design a primitive state diagram.
5. Design a primitive state table. Check the table for possible redundant states.
6. If possible simplify the state diagram and obtain a simplified state diagram.
7. Make a State Assignment (optional)
8. Develop PRESENT/NEXT STATE Table
9. Develop PRESENT/NEXT STATE maps. Derive PRESENT/NEXT STATE Decoder
Logic for D, T, SR or JK flip-flops.
10. Make a selection for your memory elements (flip-flops).
11. Develop the output decoder circuit.
12. Draw the Schematic Diagram.
Design of Sequential Circuits (cont.)
Design Example: The circuit of which the block diagram is gi ven below will control the
outputs Z, W according to the input X, such that: At the beginning the output is 00 and the
input switch is high (X=1). When the input is pushed down once (X=0), the output is to
sequence with the rising edge of the clock (CLK) pulse, starting from ZW=00 to 01, 11, 10
and then stop and hold until the switch is moved back to logic 1. During the transition the
input does not affect the circuit.
1/00 Branch format:
Step 3 Step 4 X/ZW
a
AB
1 X 0/00 1/10
Z 00
0 LOGIC 0/10
CIRCUIT b d
CLK W 01 10
f/01 c f/11
11
Design of Sequential Circuits (cont.)
Step 8: PRESENT/NEXT STATE Table 1/00 Branch format:
X/ZW
Present Next a
Present Input Next Output AB
State State DA DB TA TB 0/00 00 1/10
State X State Z W
A B A B 0/10
b d
0 b 0 0 0 1 0 1 0 1 01 10
a 0 0
1 a 0 0 0 0 0 0 0 0
f/01 c f/11
0 c 0 1 1 1 1 1 1 0 11
b 0 1
1 c 0 1 1 1 1 1 1 0
0 d 1 1 1 0 1 0 0 1
c 1 1 D=1 T=1
1 d 1 1 1 0 1 0 0 1
D=0 D=1 T=0 T=0
0 d 1 0 1 0 1 0 0 0 0 1 0 1
d 1 0
1 a 1 0 0 0 0 0 1 0 D=0 T=1

AB AB AB AB AB AB
X 00 01 11 10 X 00 01 11 10 X 00 01 11 10 X 00 01 11 10 X 00 01 11 10 X 00 01 11 10
0 0 1 1 1 0 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0
1 0 1 1 0 1 0 1 0 0 1 0 0 1 1 1 0 1 1 0 1 0 1 0 1 1 0 0 1 0
Design of Sequential Circuits (cont.)
Implementation with D Flip-flops Implementation with T Flip-flops

A X A
X D Q Z T Q Z

Q A Q A

T Q B
D Q B

clock
B Q W
clock

Q W
State Reduction
• Definition: Two states p and q are equivalent if when the
machine starts from these states and identical output
sequences are generated from every possible set of input
sequences.
• If two states p and q are equivalent the state q is called
redundant.
• State reduction is possible if there are redundant states and we
only interested in external input-output relationships.
• The state reduction doesn’t mean flip-flop reduction for every
case. Sometimes, it reduces the input/output decoder circuitry
by taking the redundant states as don’t care entries to the
Karnough map.
 State Reduction Example
0/0
Branch format: x/y
Present Input Next Output
a State x State y
0/0 0 a 0
0/0 1/0 a
1 b 0
0/0
b 0/0
c b
0 c 0
1 d 0
1/0 a
1/0 0 0
c d
g d e 1
0 e
0
0
0/0 d
1/1 1/1 1 d f 1
a Equivalent
0 0
e after g=e
0/0 f 1/1 1 d f 1
f=d
Equivalent 0 ge 0
g=e f d f
1/1 1 1 Redundant
0 a 0 States
g f
1 1
state a a b c d e f f g f g a
input x 0 1 0 1 0 1 1 0 1 0 0
output y 0 0 0 0 0 1 1 0 1 0 0
 State Reduction Example Present Input Next Output
State x State y
0 a 0
0/0 a b
Branch format: x/y 1 0
Present Input Next Output 0 c 0
a State x State y
b
1 d 0
0/0 0 a 0
0 a 0 c
0/0 1/0 a 1 d 0
1 b 0
0/0 e
b 0/0
c b
0 c 0 d
0
1 d
0
1
1 d 0
1/0 0 a 0
1/0 0 a 0 e
c 1 d 1
d
g d e 1
0 e
0
0
0/0 d
1/1 1/1 1 d f 1 0/0 Branch format: x/y
a Equivalent
0 0
0/0 f 1/1 e
1 d f 1
after g=e a
Equivalent ge f=d 0/0
0 0
g=e f d f 0/0 1/0
1/1 1 1 Redundant
a
g
0
1 f
0
1
States e b 0/0
c
state a a b c d e f f g f g a 1/1 1/0
input x 0 1 0 1 0 1 1 0 1 0 0 0/0 1/0
output y 0 0 0 0 0 1 1 0 1 0 0
d
1/1
 Realization PRESENT/NEXT STATE Table
Next State
State assignment Present State Input
Input Code
Out Next State
St. A B C x DA DB DC y A B C
0 0 0 0 0 0 0 0 0 0 0
a
0 0 0 1 0 0 1 0 0 0 1
0 0 1 0 0 1 0 0 0 1 0
b
0 0 1 1 0 1 1 0 0 1 1
0 1 0 0 0 0 0 0 0 0 0
c
0 1 0 1 0 1 1 1 0 1 1
0 1 1 0 1 0 0 0 1 0 0
d
0 1 1 1 0 1 1 0 0 1 1
1 0 0 0 0 0 0 0 0 0 0
FF Input functions Output function e
1 0 0 1 0 1 1 1 0 1 1
AB AB AB AB 1 0 1 0 X X X X X X X
Cx 00 01 11 10 Cx 00 01 11 10 Cx 00 01 11 10 Cx 00 01 11 10 1 0 1 1 X X X X X X X
00 0 0 X 0 00 0 0 X 0 00 0 0 X 0 00 0 0 X 0 1 1 0 0 X X X X X X X
01 0 0 X 0 01 0 1 X 1 01 1 1 X 1 01 0 1 X 0 1 1 0 1 X X X X X X X
11 0 0 X X 11 1 0 X X 11 1 1 X X 11 0 1 X X 1 1 1 0 X X X X X X X
10 0 1 X X 10 1 1 X X 10 0 0 X X 10 0 0 X X
1 1 1 1 X X X X X X X
DA=BCx DB=Ax+Cx+ABC+BCx DC =x y=ABx
 Realization (circuit) PRESENT/NEXT STATE Table
Next State
State assignment Present State Input
Input Code
Out Next State
St. A B C x DA DB DC y A B C
0 0 0 0 0 0 0 0 0 0 0
a
0 0 0 1 0 0 1 0 0 0 1
0 0 1 0 0 1 0 0 0 1 0
b
0 0 1 1 0 1 1 0 0 1 1
0 1 0 0 0 0 0 0 0 0 0
c
0 1 0 1 0 1 1 1 0 1 1
0 1 1 0 1 0 0 0 1 0 0
d
0 1 1 1 0 1 1 0 0 1 1
1 0 0 0 0 0 0 0 0 0 0
FF Input functions Output function e
1 0 0 1 0 1 1 1 0 1 1
AB AB AB AB 1 0 1 0 X X X X X X X
Cx 00 01 11 10 Cx 00 01 11 10 Cx 00 01 11 10 Cx 00 01 11 10 1 0 1 1 X X X X X X X
00 0 0 X 0 00 0 0 X 0 00 0 0 X 0 00 0 0 X 0 1 1 0 0 X X X X X X X
01 0 0 X 0 01 0 1 X 1 01 1 1 X 1 01 0 1 X 0 1 1 0 1 X X X X X X X
11 0 0 X X 11 1 0 X X 11 1 1 X X 11 0 1 X X 1 1 1 0 X X X X X X X
10 0 1 X X 10 1 1 X X 10 0 0 X X 10 0 0 X X
1 1 1 1 X X X X X X X
DA=BCx DB=Ax+Cx+ABC+BCx DC =x y=ABx
Synchronous
Counters
 Synchronous Binary Counter
The state transition diagrams, present/next state map and circuit diagram of a 3-bit binary
synchronous counter is shown below.
a A1A0 A1A0
000 A2 00 01 11 10 A2 00 01 11 10
b h 0 0 0 1 0 0 0 1 1 0
001 111 1 0 0 1 0 1 0 1 1 0
TA2=A0A1 TA1=A0
c g A1A0
010 110
A2 00 01 11 10
0 1 1 1 1 TA0=1
d 1 1 1 1 1
f
011 101
e
100

1 2 3 4 5 6 7 8
T=1
Clk
A0 T=0 T=0
0 1
A1
A2 T=1
 Synchronous Binary Counter (Cont.)
The state transition diagrams, present/next state map and circuit diagram of a 3-bit binary
synchronous counter is shown below.
a A1A0 A1A0
000 A2 00 01 11 10 A2 00 01 11 10
b h 0 0 0 1 0 0 0 1 1 0
001 111 1 0 0 1 0 1 0 1 1 0
TA2=A0A1 TA1=A0
c g A1A0
010 110
A2 00 01 11 10
0 1 1 1 1 TA0=1
d 1 1 1 1 1
f
011 101
A0 A1 A2
e
100
1 T Q T Q T Q
1 2 3 4 5 6 7 8
T=1
Clk
T=0 T=0 Q Q Q
A0 0 1
A1 CLK
A2 T=1
UNIVERSAL COUNTERS
• Synchronous UP/DOWN Counter

U/D UP
Q Q Q Q
T T DOWN

CLK
Single input UP/DOWN control
U/D=0 is UP, U/D=1 is DOWN
UP

DOWN
 UNIVERSAL COUNTERS
Q1 Q2 Q 4 Q 8 Q1 Q2 Q4 Q8

UP Clk CPU TCU (Carry)

Clk CO (Carry Out)
TCD (Barrow)
DOWN Clk CPD

MR TC:Terminal Count
UP DOWN MR
(Master (Master Reset)
Reset)
Cascadable UP/DOWN counter with seperate
Selectible UP/DOWN counter UP/DOWN Clk and Carry/Borrow outputs

Q0 Q1 Q 2 Q 3

Clk CO (Carry Out)

Load Clear Universal Counter
with Parallel Load
P0 P1 P2 P3
 Universal Counters Available
• BCD single control input (U’/D) Counter: 74190
• Modulo-16 Binary single control input (U’/D) Counter: 74191
• BCD Seperate control input (CPU/CPD) Counter: 74192 LS192/193

• Binary Seperate control input (CPU/CPD) Counter: 74193

The SN54/74LS190 and SN54/74LS191 are synchronous
UP/DOWN Counters. State changes with the LOW-to-HIGH
transition of the Clock input. The LS192 and LS193 are
An asynchronous Parallel Load (PL) input overrides counting Asynchronously Presettable
LS190/191
and loads the data present on the Pi inputs to use it as Decade and 4-Bit Binary
programmable counters. A Count Enable (CE) input serves Synchronous UP/DOWN
as the carry /borrow input in multi-stage counters. (Reversable) Counters.
An Up/Down Count Control (U/D) input determines whether a Each circuit contains four
circuit counts up or down. A Terminal Count (TC) output and a master/slave flip-flops, with
Ripple Clock (RC) output provide overflow/underflow internal gating and steering
indication and make possible a variety of methods for logic to provide master reset,
generating carry/borrow signals in multistage counter individual preset, count up
applications and count down operations.
 Design with Universal Counters
4-bit Counter 74HC161 Circuit. It is possibble to build any counter that may count up or down from any
number to any other number between 0 to 15.
𝐿𝐷 : Parallel Load (Active Low)
P0…P3 : Parallel inputs
Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
Clk Clk
CP 74HC161 CO Carry 𝑀𝑅 : Master Resel (Active Low)
CP 74HC161 CO Carry
LD MR 1 1 LD MR Q0…Q3 : Parallel Outputs
P0 P1 P2 P3 P0 P1 P2 P3 CO : Carry Output
0 Inputs have no effect
CP : Clock Pulse Input
a) Count Sequence : 0,1,2,3,4,5,0 ... b) Count Sequence : 0,1,2,3,4,5,0 ...

Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
Clk Clk
CP 74HC161 CO Carry CP 74HC161 CO Carry
LD MR 1 LD MR 1
P0 P1 P2 P3 P0 P1 P2 P3

0 1 0 1 1 1 0 0
c) Count Sequence : 10,11,12,13,14,15,10 ... d) Count Sequence : 3,4,5,6,7,8,3 ...