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A Virtual Logic Analyzer Implemented with Arduino

Article · September 2018

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 A Virtual Logic Analyzer Implemented with Arduino

Jianghua Bai1, Jingwei Chen2

1. Department of Physics, Portland State University, USA
2. Software Department, Xiamen Malata Technology Inc.

Abstract: A simple, stable and reliable virtual logic analyzer is presented. The logic analyzer had two
modules. One was the test pattern generation module. The other was the logic monitoring module.
Combining the two modules, one is able to test a digital circuit automatically. The user interface of the
logic analyzer was programmed with LabVIEW. Two Arduino UNO boards were used as the hardware
targets to input and output the logic signals. The maximum pattern update rate was set to be 20 Hz. The
maximum logic sampling rate was set to be 200 Hz. After twelve thousand cycles of exhaustive tests, the
logic analyzer had a 100% accuracy. As a tutorial showing how to build virtual instruments with Arduino,
the software detail is also explained in this article.
Keywords: Automatic Test Equipment (ATE), Automatic Test Pattern Generation (ATGP), Logic
Analyzer, LabVIEW, Arduino, Virtual Instruments

0. INTRODUCTION

High-end electronics hobbyists may deploy some complicated applications either in a microcontroller
platform or other kind of digital circuits. Simple applications are achieved by driving several digital lines
high or low at different time frames. Complex applications may employ many digital lines or 8 bit and 16
bit buses. Waveform graphs are the most intuitive method for developing and testing complex digital
applications. In order to test a digital circuit, one needs to excite the circuit with some digital waveforms,
and at the same time, one needs to monitor the output of the circuit. A logic analyzer is used to generate
the test waveforms and measure the output waveforms of the device under test (DUT). Commercial logic
analyzers are fast and expensive. But amateur electronics and controller designers do not need the fast
speed offered by an expensive commercial logic analyzer. Usually, they just need a tool to test whether
the logic and timing of their circuits are correct. Debugging a circuit, many engineers may drive the
circuit at 1 Hz, then, monitor the responses of the circuit for about 100 cycles. This project is developed
for this kind of applications.
There are some similar designs proposed already. Some of them have difficult programs [1], [2]. Some of
them have bad user interfaces [2]. Some of them are not reliable [2], [3]. All of them can only monitor
the logic outputs of the DUT [1], [2], [3], [4], [5]. This design builds pattern generation and logic
monitoring functions together. One is able to achieve automatic testing of digital circuits with this virtual
logic analyzer.
 1. HARDWARE OF THE LOGIC ANALYZER

Fig. 1 shows the hardware illustration of the virtual logic analyzer. The main controller of the instrument
is running on a computer. Two Arduino UNO boards are connected to the computer with USB. One
Arduino board offers the output port. The other Arduino board offers the input port. Both the input and
output ports have 16 channels. D0 to D15 are mapped to Arduino pins 2 to A3. See Fig. 1. During an
operation, test patterns are generated in the main controller and outputted through Arduino Board1. The
device under test (DUT) is driven by the logic patterns. Its responses are measured by Arduino Board2.
Finally, the test waveforms and the measured waveforms will be displayed on the main controller. Users
can generate any test patterns as they need and verify the measured waveforms to finish their testing. This
virtual logic analyzer can also be configured as an automatic test equipment (ATE). Then a high-level test
program will generate the test waveforms and examine the measured responses.

Fig. 1. A functional illustration of the logic analyzer. ( The DUT is not a part of this logic analyzer.)
 2. THE OPERATION OF THE VIRTUAL LOGIC ANALYZER

The user interface of the logic analyzer has three tabs. By default, the first tab has a 16X32 LED matrix.
See Fig. 2. According to their needs, users can design their test patterns by clicking the LEDs. LED ONs
and OFFs are related to logic highs and lows. After the test patterns are set, users can select the second tab
to verify the logic and send the logic out. See Fig.3.

Fig. 2. The test pattern generation tab.

The second tab of the virtual logic analyzer displays the logic patterns with digital waveforms. Users can
verify the logic and send them out to the port. If users want to modify the waveforms, they can go back to
the first tab and toggle the related LEDs. During operations, users may go back and forth between the first
tab and the second tab several times, till they confirm the waveforms. UpDate(Hz) sets how fast the pulse
trains will be sent to the output port. For manual debugging, this frequency can be set to 0.1- 0.5 Hz.
When the device under test (DUT) is driven by the pulse trains, one could follow the output of the DUT
to verify its functionalities. For automatic tests, the UpDate(Hz) can be set as high as 20 Hz. The reason
will be explained in Section 3B.

After the waveforms are confirmed, users can output the pulse trains by clicking the button
SendPattensOut. This time, T will display the clock cycles, while the LEDs will display the instantaneous
logic levels appearing on each line of the logic output port. See Fig. 3.
Fig. 3. The test pattern output tab.

The third tab is a logic viewer. When the DUT is driven by the test patterns, the DUT’s responses will be
measured by the logic monitoring module and displayed in this tab. Users may switch between the second
tab and the third tab several times to finish a manual test. Only manual operational procedures are
covered here. The whole program can be called as a subroutine for automatic test applications.

Fig.4. The logic viewer tab.

 3. Software of the virtual logic analyzer

A. The software structure.

Fig. 5. A 4-layer abstraction of the software structure. (Layers 1 & 2 are implemented in Arduino. Layers
3 & 4 are implemented by LabVIEW programs in a PC.)

The software of this logic analyzer was organized with a 4-layer virtual instrument software model [6].
The first layer of the software was used to map the hardware ports with logic lines. The second layer of
the software was used to format the data package and communicate between the second layer and the
third layer. The third layer was used to hold the graphic user interface and display the logic waveforms.
The fourth layer was used to employ ATE applications.

B. Software of the pattern generation module.

Fig. 6 shows the LabVIEW program of the test pattern generation module (Layer 3). The user interface of
this program is shown in Fig. 2 and Fig. 3. Test pattern matrix and pattern waveform displaying were
programmed by a while loop [7]. After the users finish the setting of the test patterns and verify the
waveforms, they can click the SendPatternsOut button. The button will stop the while loop and send the
logic pattern array to the subsequent for loop. The for loop will read the patterns cycle by cycle and
transform the logic patterns into strings, which will be sent to the Arduino board1 through USB bus. The
Windows has a 1 ms timmer and the USB to RS232 has some delay, so a minimum 50 ms time cycle was
set in the for loop to maintain a stable data transferring between the PC and the Arduino board. Hence, a
maximum frequency of 20 Hz was set for the pattern generation module.

In order to increase the reliability of the data transmission across the USB bus, a 7 character string
pattern was used to format the data sent from Layer3 to Layer2. The format starts with ‘D’ and ends with
‘T’. Five number characters are sandwiched between them. See. Fig.7. Building the data into a format,
not only enables asynchronous data transmission but offers a way for error checking of the transmission.
[8], [9], [10].

Fig. 6. Test pattern generation (layer 3)

Fig.7. The format of the string sent out by the LabVIEW program.

On the front panel of the virtual logic analyzer, there are 3 tabs. But indeed the codes in tab1 and tab2 are
all programmed as shown in Fig. 6. Tab2 is an empty tab used to display the logic waveforms. See Fig.3
and Fig. 7.

Fig. 8. The tab2 was not programmed. It was used to display the waveforms only.
Fig. 9. Arduino code of the test pattern generation module. (Layers 1 & 2)

Fig. 9 shows the Arduino code of the test pattern generation module (Layer 1 and Layer 2). Layer1 of
the module was implemented by the array pin[16]. Here the logic assignment was corresponding to the
hardware connections shown in Fig.1. If users have a different connection, they need to match the array
elements with the actual hardware port numbers. Layer2 of the module was implemented by the
subroutine readLvNum(). The subroutine has a 15-bit buffer storing the data transmitted from the
LabVIEW program running at Layer3. Suppose the data were buried in the buffer like the one shown in
Fig. 10. The subroutine will check the head character ‘D’ and the tail character ‘T’ of the data format.
After the head and tail characters are verified, the data chunk between them will be converted to logic bits
and sent to the related Arduino hardware ports [8].

Because Layer3 is running on a PC and Layer 2 is running on an Arduino board, usually, they would have
different speeds. The benefit of this programming method is that different layers of the software can run
independently. Data transmitted between layers are stored in buffers. Then inside of each layer, data will
be read out and processed at its own speed. This way asynchronous communications are achieved
between layers running with different speeds [8], [9].

Fig. 10. A supposed string read by the Arduino buffer.

 C. Software of the logic monitoring module.

Fig. 11. Logic measurement and display (layer 3).

Fig. 11 shows the LabVIEW program of the logic monitoring module (Layer 3). At first, a while loop was
used to read the measured logic strings continuously. The format of the string was also verified in the
while loop. When the format was correct, the while loop will send the logic strings to a converter. Finally,
the logic strings will be converted into logic patterns and displayed on a waveform viewer. See Fig.4.

Fig. 12 shows the Arduino codes of the logic monitoring module (Layer 1 and Layer 2). It uses a similar
technique as the Arduino codes of the test pattern generation module. The algorithm of data formatting
can be found in [8].
Fig. 12. Arduino code of the Logic monitoring board. (Layers 1 &2)

4. Test of the logic analyzer.

Fig. 13 shows the preliminary test of the pattern generation module. 16 channels of digital patterns were
generated by the module. A 4 channel Tektronix oscilloscope was used to test the outputs of the Arduino
board1 4 lines after 4 lines. One could see the correctness of the module was verified.

This logic analyzer is a test equipment. Its reliability is important. After the preliminary test, an
exhaustive test was performed as illustrated in Fig. 14. Logic file1 has 12000 cycles of 16 channel
boolean data. The data was clocked out to the pattern generation module and read by the logic monitoring
module, which saves the data into Logic file2. The update rate was set to be 20 Hz. After the data
transferring, file1 and file2 were compared. The result showed this logic analyzer had a 100% accuracy.
Fig. 13, a preliminary test of pattern generation module.

Fig. 14. an illustration of an exhaustive testing applied on the logic analyzer.

 Conclusion.

This logic analyzer is a useful tool for digital circuit debugging and testing. It can also be used as a 20 Hz
ATE. The hardware and software of a virtual logic analyzer are explained in great detail. Readers can
follow the process described in this paper to develop their own virtual instruments with LabVIEW and
Arduino microcontrollers.

References:

[1] ptorelli， Turn Your Arduino Into a Logic Analyzer,

http://www.instructables.com/id/Arduinolyzerjs-Turn-your-Arduino-into-a-Logic-Anal/
[2] James Lewis ， Logic Analyzer Tutorial and Introduction,
https://www.baldengineer.com/logic-analyzer-tutorial-introduction.html
[3] vincenzo-g, DIY Logic Analyzer, https://create.arduino.cc/projecthub/vincenzo-g/diy-logic-
analyzer-f61ee5
[4] MARCO_C， Low Cost DIY Logic Analyzer，
https://arduinoplusplus.wordpress.com/2017/07/08/low-cost-logic-analyzer/
[5] Daniel Hankewycz， Arduino: 3 Powerful, Yet Overlooked Uses,
https://www.mouser.com/blog/arduino-3-powerful-yet-overlooked-uses
[6] Jianghua Bai, Jingwei Chen, John Freeouf, Andres La Rosa. A 4-layer method of developing
integrated sensor systems with LabVIEW, Journal of Measurement Science and
Instrumentation. 2013
[7] National Instruments, Types of Graphs and Charts , http://zone.ni.com/reference/en-
XX/help/371361P-01/lvconcepts/types_of_graphs_and_charts/
[8] Jianghua Bai, Andres La Rosa. Essentials of Building Virtual Instruments with LabVIEW
and Arduino for Lab Automation Applications, International Journal of Science and
Research (IJSR), https://www.ijsr.net/archive/v6i5/v6i5.php, Volume 6 Issue 5, May 2017,
640 – 644
[9] Jianghua Bai, Andres La Rosa. An SPM Stage Driven by 3 Stepper Motors. Journal of
Measurement Science and Instrumentation. 2017
[10] Jianghua Bai, Andres La Rosa， An Automated AFM Designed for Nanoindentation and
Force Measurements, Journal of Measurement Science and Instrumentation. 2017

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