CHAPTER-1

INTRODUCTION

An application-specific integrated circuit (ASIC) is a type of integrated circuit (IC) that is

customized for a specific application, such as a particular device or system. ASICs are designed
to perform a specific set of tasks and are typically much more efficient and faster at performing
those tasks than a general-purpose microprocessor.

Application-Specific Integrated Circuits (ASICs) are custom-designed semiconductor

devices tailored for specific applications. They offer significant performance, power efficiency,
and space advantages over general-purpose integrated circuits.

The development of ASICs began in the late 1970s and early 1980s with the advent of
semiconductor technology. Initially, the cost and complexity of designing ASICs limited their
use to high-volume products. However, advancements in design tools and fabrication processes
have made ASICs more accessible and affordable.

Application Specific Integrated Circuit (ASIC) is a type of integrated circuit (IC)

customized for a particular use, rather than intended for general-purpose use. ASICs are
designed to perform specific tasks in industries such as telecommunications, automotive,
consumer electronics, and more. They are essential for applications requiring high
performance, low power consumption, and efficient use of space.

An application-specific integrated circuit is an integrated circuit (IC) that's custom-

designed for a particular task or application. Unlike FPGA boards that can be programmed to
meet a variety of use case requirements after manufacturing, ASIC designs are tailored early
in the design process to address specific needs.

Compared to a programmable logic device or a standard logic integrated circuit, an ASIC

can improve speed because it is specifically designed to do one thing and it does this one thing
well. It can also be made smaller and use less electricity. The disadvantage of this circuit is that
it can be more expensive to design and manufacture, particularly if only a few units are needed.

ASICs are typically fabricated using metal–oxide–semiconductor (MOS) technology and

can offer high performance and low power consumption compared to circuits using off-the-
shelf components. ASICs are also non-reprogrammable once they are produced.

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CHAPTER-2

TYPES OF APPLICATION SPECIFIC INTEGRATED CIRCUIT

Fig1.Types of ASIC

1.Full Custom:

In this type of design all the logic cells are tailored made for specific application .i.e.
designer has to specially make the logic cells for the circuits. All the mask layers for
interconnection are customized. So programmer can’t change interconnections of the chip and
while programming he has to be aware of the circuit layout.
One of the best examples of Full custom ASIC is a microprocessor. This type of
customization allows designers to built various analog circuits, optimized memory cells, or
mechanical structures on a single IC. This ASIC is costly and very time consuming to
manufacture and design. The time is taken to design these ICs is around eight weeks.
These are usually intended for high-level applications. Maximum performance, minimized
area and highest degree of flexibility are major features of Full custom design. Eventually, the
risk is high in design as the logic cells, resistor etc… circuit elements used are not pretested.

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2.Semi-custome:

To shorten the design time and cut down the cost of full-custom ASICs, numerous other
design approaches have been developed and these are called as Semi-Custom ASIC Designs.
Usually, the lowest level of hierarchy involved in semi-custom design is the logic level or gate
level. This is in contrast to full-custom job, where the design and layout individual transistor
might be involved.

As mentioned earlier, the semi-custom ASIS design can be further divided into Gate
Arrays and Standard Cells. Let us see a little bit about these types.

Gate Array ASIC

In Gate Array based ASICs, p and n types transistors are predefined on a silicon wafer as
arrays. Based on the design from the customer and the interconnections obtained from the
design, the silicon vendor provides these base wafers. Therefore, the base wafer is specific to
the customer as it is designed based on the customer provided connections between the
transistors of the gate array.

The gate arrays are again divided into two types called the Channelled Gate Array and the
Channel-less Gate Array. In channelled gate arrays, the interconnections between the logic
cells are performed within the predefined channels between the rows of the logic cells. In case
of channel-less gate arrays, the connections are made on an upper metal layer on top of the
logic cells.

Fig2.Gate Array Types

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Standard Cell based ASIC

A Standard Cell based ASIC uses predesigned logic cells like Gates, Multiplexers, Flip-
flops, Adders etc. These logic cells are known as Standard Cells that are already designed and
stored in a library. This library is imported into the CAD tool and the design can performed
using the components of the library as inputs.

Typically, Standard Cell based designs are organized as rows of constant height cells on
the chip, just like a row of bricks. When combined with logic-level components, standard cell-
based designs can be used to implement complex functions like Multipliers and Memory
Arrays.

Fig3.Standed Cell Based ASIC

The standard cell design may also contain a larger and more complex predesigned cells like
Microcontrollers or Microprocessors. These larger cells are called as Megacells.

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3.Programable ASICs:
There are two types of programmable ASICs. They are PLD and FPGA
PLDs (Programable Logic Devices)
These are the standard cells readily available. We can program a PLD to customized a part
of the application, so they are considered as ASIC. We can use different methods and software
to program a PLD. These contain a regular matrix of logic cells usually programmable array
logic along with flip-flops or latches. Here interconnects are present as a single large block.
PROM is a common example of this IC. EPROM uses MOS transistors as interconnect so by
applying high voltage we can program it. PLDs have no customized logic cells or interconnect.
These have a fast design turnaround.
FGPAs (Field Programable Programmable Gate Array)
Where PLDs have programmable array logic as logic cells FPGA has gate array-like
arrangement. PLDs are smaller and less complex than FPGAs. Due to its flexibility and
characteristics, FPGA is replacing TTL in microelectronic systems. Design turnaround is only
a few hours.
The core consists of programmable basic logic cells which can perform both combinational
and sequential logic. We can program logic cells and interconnect using some methods. Basic
logic cells are surrounded by the matrix of programmable interconnects and the core is
surrounded by programmable I/O cells.
FPGA usually comprises of configurable logic blocks, configurable I/O blocks,
programmable interconnects, clock circuitry, ALU, memory, decoders.
We have seen the different types of ASIC available. Now let’s understand when all these
customizations and interconnects are done during manufacturing.

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CHAPTER-3
DESIGEN FLOW
In order to fulfill futuristic demands of chip design, changes are required in design tools,
methodologies, and software/hardware capabilities. For those changes, ASIC design flow
adopted by engineers for efficient structured ASIC chip architecture and focus on its design
functionalities
ASIC design flow is a mature and silicon-proven IC design process which includes various
steps like design conceptualization, chip optimization, logical/physical implementation, and
design validation and verification. Let’s have an overview of each of the steps involved in the
process.

Fig a.

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 Fig b.
Fig4.Desigen Flow Of Application Specific Integrated Circuit

Step 1. Chip Specification

This is the stage at which the engineer defines features, microarchitecture, functionalities
(hardware/software interface), specifications (Time, Area, Power, Speed) with design
guidelines of ASIC. Two different teams are involved at this juncture:

 Design team: Generates RTL code.

 Verification team: Generates test bench.
Step 2. Design Entry / Functional Verification
Functional verification confirms the functionality and logical behavior of the circuit by
simulation on a design entry level. This is the stage where the design team and verification
team come into the cycle where they generate RTL code using test-benches. This is known
as behavioral simulation.
In this simulation, once the RTL code (RTL code is a set of code that checks whether the RTL
implementation meets the design verification) is done in HDL, a lot of code coverage metrics

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proposed for HDL. Engineers aim to verify correctness of the code with the help of test
vectors and trying to achieve it by 95% coverage test. This code coverage includes statement
coverage, expression coverage, branch coverage, and toggle coverage.
There are two types of simulation tools:
Functional simulation tools: After the testbench and design code, functional simulation
verifies logical behavior and its implementation based on design entry.
Timing simulation tools: Verifies that circuit design meets the timing requirements and
confirms the design is free of circuit signal delays.
Step 3. RTL block synthesis / RTL Function
Once the RTL code and testbench are generated, the RTL team works on RTL description
they translate the RTL code into a gate-level netlist using a logical synthesis tool that meets
required timing constraints. Thereafter, a synthesized database of the ASIC design is created
in the system. When timing constraints are met with the logic synthesis, the design proceeds to
the design for testability (DFT) techniques.
Step 4. Chip Partitioning
This is the stage wherein the engineer follows the ASIC design layout requirement and
specification to create its structure using EDA tools and proven methodologies. This design
structure is going to be verified with the help of HLL programming languages like C++ or
System C.
After understanding the design specifications, the engineers partition the entire ASIC into
multiple functional blocks (hierarchical modules), while keeping in mind ASIC’s best
performance, technical feasibility, and resource allocation in terms of area, power, cost and
time. Once all the functional blocks are implemented in the architectural document, the
engineers need to brainstorm ASIC design partitioning by reusing IPs from previous projects
and procuring them from other parties.
Step 5. Design for Test (DFT) Insertion
With the ongoing trend of lower technology nodes, there is an increase in system-on-chip
variations like size, threshold voltage and wire resistance. Due to these factors, new models
and techniques are introduced to high-quality testing.
ASIC design is complex enough at different stages of the design cycle. Telling the
customers that the chips have fault when you are already at the production stage is embarrassing
and disruptive. It’s a situation that no engineering team wants to be in. In order to overcome
this situation, design for test is introduced with a list of techniques:
 Scan path insertion: A methodology of linking all registers elements into one long
shift register (scan path). This can help to check small parts of design instead of the
whole design in one go.

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  Memory BIST (built-in Self-Test): In the lower technology node, chip memory
requires lower area and fast access time. MBIST is a device which is used to check
RAMs. It is a comprehensive solution to memory testing errors and self-repair
proficiencies.

 ATPG (automatic test pattern generation): ATPG is a method of creating test

vectors / sequential input patterns to check the design for faults generated within various
elements of a circuit.
Step 6. Floor Planning (blueprint your chip)
After, DFT, the physical implementation process is to be followed. In physical design, the
first step in RTL-to-GDSII design is floorplanning. It is the process of placing blocks in the
chip. It includes: block placement, design portioning, pin placement, and power optimization.
Floorplan determines the size of the chip, places the gates and connects them with wires.
While connecting, engineers take care of wire length, and functionality which will ensure
signals will not interfere with nearby elements. In the end, simulate the final floor plan with
post-layout verification process.
A good floorplanning exercise should come across and take care of the below points;
otherwise, the life of IC and its cost will blow out:
 Minimize the total chip area
 Make routing phase easy (routable)
 Improve signal delays
Step 7. Placement
Placement is the process of placing standard cells in row. A poor placement requires larger
area and also degrades performance. Various factors, like the timing requirement, the net
lengths and hence the connections of cells, power dissipation should be taken care. It removes
timing violation.
Step 8. Clock tree synthesis
Clock tree synthesis is a process of building the clock tree and meeting the defined timing,
area and power requirements. It helps in providing the clock connection to the clock pin of a
sequential element in the required time and area, with low power consumption.
In order to avoid high power consumption, increase in delays and a huge number of
transitions, certain structures can be used for optimizing CTS structure such as Mesh Structure,
H-Tree Structure, X-Tree Structure, Fishbone Structure and Hybrid structure.
With the help of these structures, each flop in the clock tree gets the clock connection.
During the optimization, tools insert the buffer to build the CTS structure. Different clock
structures will build the clock tree with a minimum buffer insertion and lower power
consumption of chips.

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Step 9. Routing

 Global Routing: Calculates estimated values for each net by the delays of fan-out of
wire. Global routing is mainly divided into line routingand maze routing.
 Detailed Routing: In detailed routing, the actual delays of wire is calculated by various
optimization methods like timing optimization, clock tree synthesis, etc.
As we are moving towards a lower technology node, engineers face complex design
challenges with the need for implanting millions of gates in a small area. In order to make this
ASIC design routable, placement density range needs to be followed for better QoR. Placement
density analysis is an important parameter to get better outcomes with less number of iterations.
Step 10. Final Verification (Physical Verification and Timing)
After routing, ASIC design layout undergoes three steps of physical verification, known as
signoff checks. This stage helps to check whether the layout working the way it was designed
to. The following checks are followed to avoid any errors just before the tapeout:
Layout versus schematic(LVS) is a process of checking that the geometry/layout matches
the schematic/netlist.
Design rule checks(DRC) is the process of checking that the geometry in the GDS file
follows the rules given by the foundry.
Logical equivalence checks(LVC) is the process of equivalence check between pre and post
design layout.
Step 11. GDS II – Graphical Data Stream Information Interchange
In the last stage of the tapeout, the engineer performs wafer processing, packaging, testing,
verification and delivery to the physical IC. GDSII is the file produced and used by the
semiconductor foundries to fabricate the silicon and handled to client.

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CHAPTER-4
APPLICATIONS
1. Telecommunications:-
Network Equipment: Routers, switches, and modems use ASICs for data routing, switching,
and signal processing.
Mobile Devices: ASICs in smartphones and tablets manage tasks such as signal processing,
power management, and multimedia processing.
2. Consumer Electronics:-
Audio and Video Devices: ASICs handle tasks like video compression/decompression, audio
processing, and image enhancement in TVs, cameras, and sound systems.
Gaming Consoles: Custom ASICs provide high-performance graphics processing and game
physics handling.
3. Automotive Industry:-
Infotainment Systems: ASICs control multimedia interfaces, navigation, and connectivity
features.
Advanced Driver-Assistance Systems (ADAS): These systems use ASICs for real-time
processing of sensor data (cameras, radars, lidars) to enhance driving safety and automation.
4. Healthcare:-
Medical Imaging Devices: ASICs enable high-speed processing and image enhancement in
devices like MRI, CT scanners, and ultrasound machines.
Wearable Health Monitors: ASICs in wearable devices track and analyze health metrics such
as heart rate, blood pressure, and activity levels.
5. Industrial Automation:-
Robotics: ASICs in industrial robots provide precise control over motion, sensing, and
processing tasks.
Control Systems: ASICs are used in programmable logic controllers (PLCs) and other
automation control systems for efficient operation.
6. Cryptocurrency Mining:-
Bitcoin Mining: Specialized ASICs known as mining rigs are designed for the high-efficiency
processing of cryptocurrency transactions and solving cryptographic puzzles.
7. Networking and Data Centers:-
Servers and Storage: ASICs optimize data processing, encryption, and compression tasks in
servers and storage systems.

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Network Security: Custom ASICs are used in firewalls, intrusion detection systems, and VPNs
to handle encryption and security protocols efficiently.
8. Aerospace and Defense:-
Satellite Communications: ASICs provide reliable and efficient processing for satellite
communication systems.
Military Equipment: Custom ASICs are used in radar, sonar, and other defense systems for
real-time data processing and analysis.
9. Financial Services:-
High-Frequency Trading: ASICs enable low-latency processing and execution of financial
transactions in high-frequency trading systems.
Encryption and Security: Financial institutions use ASICs for secure data encryption and
decryption, ensuring the protection of sensitive information.
10. Artificial Intelligence and Machine Learning:-
Deep Learning Accelerators: ASICs designed for AI and ML applications accelerate the
training and inference processes for neural networks, providing significant performance
improvements over general-purpose processors.

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CHAPTER-5
ADVANTAGES
1. Performance:-
Speed: ASICs are designed for a specific task, which allows them to operate much faster than
general-purpose chips.
Efficiency: They are optimized for a specific function, which often results in lower latency and
higher throughput.
2. Power Consumption:-
Lower Power Usage: ASICs consume less power compared to general-purpose processors
because they eliminate the overhead of unnecessary functions.
Energy Efficiency: This is crucial for battery-operated devices and applications where energy
efficiency is a priority.
3. Size and Space:-
Compact Design: ASICs are typically smaller than their general-purpose counterparts because
they include only the necessary circuitry for a specific task.
Integration: The ability to integrate multiple functions into a single chip reduces the overall
footprint of the hardware.
4. Cost-Effectiveness (at scale):-
Economies of Scale: While the initial cost of designing and manufacturing ASICs is high, the
per-unit cost decreases significantly with large volume production.
Long-term Savings: For products with long life cycles and high production volumes, ASICs
can lead to substantial cost savings.
5. Security:-
Enhanced Security: ASICs can be designed with custom security features, making it harder for
unauthorized parties to tamper with or reverse-engineer the hardware.
Reduced Attack Surface: Since ASICs perform only specific tasks, there are fewer potential
vulnerabilities compared to general-purpose processors.
6. Customization:-
Tailored Solutions: ASICs can be customized to meet the exact requirements of an application,
ensuring optimal performance and functionality.
Special Features: Designers can include special features and optimizations that are not possible
with off-the-shelf components.

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7. Reliability:-

Robust Design: ASICs are designed for specific environments and use cases, which can
enhance their reliability and durability.
Consistency: ASICs provide consistent performance and behavior since they are not influenced
by the variability of general-purpose operations.
8. Intellectual Property (IP) Protection:-
Proprietary Designs: Companies can protect their proprietary algorithms and designs more
effectively by embedding them in an ASIC, reducing the risk of copying and counterfeiting.

ASICs offer significant advantages in performance, power efficiency, size, and cost (at scale),
along with enhanced security, customization, and reliability. These benefits make ASICs ideal
for applications where specific tasks need to be performed with high efficiency and precision.

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 DISADVANTAGES
1. High Development Cost:-
ASICs require a significant initial investment in design and manufacturing. The development
process involves custom chip design, fabrication, and testing, which are all expensive.
2. Long Development Time:-
The design and production cycle of an ASIC can be lengthy, taking months or even years from
initial design to final production. This extended timeline can be a drawback in fast-paced
industries.
3. Lack of Flexibility:-
Once manufactured, ASICs cannot be reprogrammed or modified. This inflexibility means that
any design errors or changes in specifications after production require a new design and
manufacturing cycle, leading to additional costs and delays.
4. Risk of Obsolescence:-
Rapid advancements in technology can make an ASIC design obsolete quickly. If the market
or technology standards shift, the ASIC may not be adaptable to new requirements, leading to
potential losses.
5. Limited Market:-
ASICs are designed for specific applications, limiting their usability to niche markets. This
specialization can restrict the potential customer base and market opportunities.
6. High Volume Requirement:-
To justify the high development and manufacturing costs, ASICs usually require high-volume
production. Low-volume applications might not be cost-effective, making ASICs unsuitable
for smaller markets or custom applications.
7. Manufacturing Challenges:-
Producing ASICs involves complex manufacturing processes, and any issues during
fabrication can result in significant delays and costs. Yield issues, where not all chips meet the
required quality standards, can also impact the overall cost-effectiveness.
8. Technological Barriers:-
Designing ASICs requires specialized knowledge and expertise. Companies without in-house
expertise may need to rely on third-party design firms, which can increase costs and complicate
project management.

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9. Supply Chain Dependency:-

ASIC production often depends on specific foundries or suppliers. Disruptions in the supply
chain, such as shortages of materials or geopolitical issues, can impact production timelines
and costs.
10. Thermal Management:-
High-performance ASICs can generate significant heat, requiring advanced cooling solutions.
Effective thermal management is crucial to maintain performance and reliability but can add
to the design complexity and cost.

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CHAPTER-6
CONCLUSION
In summary, ASICs represent a critical advancement in the field of integrated circuits,
offering unmatched performance and efficiency for specific applications. Their ability to
provide customized solutions makes them indispensable in various high-tech industries, from
telecommunications to healthcare. While challenges remain in the design and production
processes, ongoing technological advancements promise to enhance the viability and
functionality of ASICs. As the demand for specialized, high-performance electronic solutions
continues to grow, ASICs will undoubtedly play a crucial role in shaping the future of
technology.
Application-Specific Integrated Circuits (ASICs) have emerged as a pivotal technology in
the realm of electronics and computing, offering unparalleled performance, efficiency, and
customization. As the demand for high-speed, low-power, and highly specialized electronic
devices continues to surge, ASICs provide a robust solution that caters to these needs with
precision and efficacy.
Despite their numerous advantages, ASICs also present certain challenges. The design
cycle of ASICs is lengthy and complex, requiring significant expertise and investment.
Additionally, the inability to modify ASIC designs post-manufacturing necessitates a
meticulous design process to ensure all specifications are met. However, the continuous
evolution of electronic design automation (EDA) tools and methodologies is mitigating these
challenges, making the design process more streamlined and efficient.
Looking ahead, the future of ASICs appears promising, with ongoing research focused on
enhancing their capabilities and expanding their applications. The integration of AI and
machine learning algorithms into ASIC design is set to revolutionize their performance,
enabling more intelligent and adaptive systems. Furthermore, the rise of the Internet of Things
(IoT) and 5G technologies will drive the demand for more sophisticated and efficient ASICs,
cementing their role as a cornerstone of modern electronics.

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CHAPTER-7
REFERENCES
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November 2019.
3) ^ Kriegbaum, Jeff (13 September 2004). "FPGA's vs. ASIC's". EE Times.
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(2019). Foundations of Embedded Systems. Studies in Systems, Decision and Control.

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