VLSI

Very large scale integration

What is VLSI ?
VLSI Stands for Very large-scale integrated circuits. In VLSI, a
greater number of Transistors are integrated into a single silicon
chip.
Why VLSI
• Reduces the Size of Circuits. Reduces effective cost of the
devices. Requires less power than Discrete components.
Occupies a relatively smaller area.
• VLSI plays a crucial role in communication systems, including
wireless networks, cellular devices, and the Internet of Things
(IoT). VLSI chips enable efficient signal processing, data
transmission, and reception, enabling seamless connectivity
and improved communication capabilities.
VLSI Design flow
Verilog HDL
What is HDL?
HDL Stands for hardware description language. Used to design
electronic devices while C is used to for implementing database.
Verilog HDL
• Verilog HDL is a low-level hardware.
• It consists of concurrency of time.
• Notation of time.
• It is flexible
• It has time delay of circuits
Difference between Verilog HDL and C
Verilog HDL C
1. It is used to design electronic 1. It is used to implement data
circuits base
2. It consists of notation of time 2. It doesn't have notation of
3. It consists of time delay which time
is present in electronic circuits 3. It doesn’t have any time delay
4. It consists of concurrency of 4. It doesn’t have a concurrency
time which means it can do of time.
operations at a time
5. File extension .v 5. File extension .c
What is DUT ?
• DUT Stands for device under Test.
• DUT is used to write a design for hardware.
• DUT is written in Verilog or VHDL.
• It is usually used in pre silicon design.
What is Test Bench ?
• Test bench is the code module that describes the design into
stimulus and checks whether the DUT output matches its
specification or not .

• NOTE: Stimulus means driving the DUT into Test bench.

Structure of DUT and Test bench
Lexical conventions
• Numbers
• Comments
• Identifiers
• Keywords
• Operators
• Strings
• White spaces
1. Numbers:
In numbers, there are two types
Sized and unsized
Sized numbers: <size>'<base format><number>
Ex: 2'b01, 3'o341, 4'b1001

Unsized numbers: '<base format><number>

Ex: 'b00, 'b10111
Base formats:
Binary – b
Octal – o
Decimal – d
Hexadecimal - h
2. Comments:
There are two types of comments
Single line comment
Multi line comment

Single line comment:

//this is a single line comment

Multi line comment:

/*this is a multi- line
Comments */
3. Identifiers:
Identifiers are the names given to object in a code.

• Identifiers can be A to Z , a to z, 0 to 9, underscore(_), dollar sign

($)
• It should not start with numbers, underscore or dollar sign
4. Keywords
• Keywords are special identifiers
• They are reserved to define Verilog language
• Keywords are already present in Verilog library
• Keywords should be always in lower case letters

Ex: and, or, always, module, end, etc.,

5. Operators
There are three types of operators
1. Unary
2. Binary
3. Ternary
Unary operator:
It consists of single operator and single operand
Ex: ~a;

Binary operator:
It consists of single operator and two operands
Ex: a&b;

Ternary operator:
It consists of multiple operators and multiple operands
Ex: a+b+c+d+e;
6. Strings :
It stores the ASCII values inside it. String is represented in between
double quotes ("")
Ex: "a=%b,b=%b,c=%b"

7. white space:
Used to create new line, space etc
Data types in Verilog
Net data types
Variable data types

1. Net data types:

It is just a physical connection between input and output. It does
not store any value
Ex: wire, wand, wor etc.,
2. Variable data type:
It Stores the data
Registers
Scalars
Vectors
String
Constant
Time
Arrays
Are few variable data types.
Register data type:
reg data type is used to store the data.
Ex: reg a,b;
Again in reg data type there are two types scalar data type and vector data
type

Scalar data type:

Scalar data type stores single bit of data
Ex: reg a,b;
Vector data type:
Vector data type stores multiple bit of data
Ex: reg[3:0]a;
reg[4:0]b;
String :
It stores ASCII values inside double quotes ("")
Ex: "a,b,y"

Constant:
It stores the constant values which can never be changed

Integer:
It will store integer values. It is a 32 bit general purpose register. It is
declared by int keyword
Ex: int count;
Time:
It stores the time of the data

Arrays:
Array is a data structure that allows multiple data elements of the same
data type into a single collection.
Compiler directives and system tasks
Compiler directives:
Used to specify certain information and asks compiler to process it.
'define – used to define text macros
'include – used to include all the files into existing Verilog file
'ifdef, 'endif, 'else, 'endif – conditional compiler directives
which behaves as conditions
statements
'timescale – to specify time units
System tasks in Verilog:
The system tasks in Verilog performs the operations like terminating
simulation, displaying messages, generating numbers etc.,
$display:
It is used to display the statement during the simulation.

$monitor:
It is used to monitor the variables and display the statement whenever
the variables changes the values.

$strobe:
$strobe is similar to $monitor but only active for the time duration
specified.
$time:
Returns the current simulation time.

$finish:
Terminates the simulation.

$stop:
Stops the simulation until manually resumed.
Levels of Abstraction
In Verilog, there are 5 levels of abstraction
• Data flow modeling
• Gate level modeling
• Structural modeling
• Behavioral modeling
• Switch level modeling
Data flow modeling
• In data flow modeling, the code will be written by using the output expression of the
circuit.
• "assign" keyword is used in data flow modeling

Syntax: assign y=a&b;

And - &
Or - |
Not - ~
Nand - ~(&)
Nor - ~(|)
Xor- ^
Xnor- ~(^)
Gate level modeling
• This is the lowest level of abstraction. Here, the circuit is
described by logical links and their timing properties.
• The module is implemented in terms of logic gates and
interconnections between these gates.
• It resembles a schematic drawing with components connected
with signals.
Example: Verilog code for 4x1 mux
module mux_dut(s1,s0,i0,i1,i2,i3,y);
input s0,s1;
input i0,i1,i2,i3;
output y;
and(w1,~s1,~s0,i0);
and(w2,~s1,s0,i1);
and(w3,s1,~s0,i2);
and(w4,s1,s0,i3);
or(y,w1,w2,w3,w4);
endmodule
Structural modeling
Structural modeling in Verilog involves describing the
interconnections of components to create a digital circuit. It is akin
to drawing a circuit schematic, where individual components
(gates, flip-flops, multiplexers, etc.) are connected together to form
the desired functionality.
Operators:
Concatenation operator
Replication operator
Arithmetic operator
Relational operator
Equality operator
Negation operator
Unary reduction operator
Shift operator
Bitwise operator
Logical wise operator
Conditional operator
Concatenation operator:
Concatenation operator is used to combine two bits. It is
represented in "{}"

Replication operator:
Replication operator is used to replicate the value n number of
times. It is represented by "{{}}"

Arithmetic operator:
It performs arithmetic operations such as addition, subtraction,
multiplication etc.,
Relational operator:

Symbol Operation

> Greater than

< Less than

>= Greater than equal to

<= Less than equal to

35
Equality operator:

Symbol Operation

= Equal to
!= Not equal to
Negation operator:
In Verilog, the negation operator is represented by the
unary operator !. This operator is used to perform logical
negation on a single bit or a logical expression
Unary reduction operator:

Operator Description
& and

| or
^ xor
~& nand
~| nor
~^ or ^~ xnor
Shift operators:
>> -logical right shift
<< - logical left shift
>>> - arithmetic right shift
>>> - arithmetic left shift
Bitwise operator:

Operator Description
& and

| or
^ xor
~& nand
~| nor
~^ or ^~ xnor
Behavioral modeling

In behavioral modeling, the code will be written by using its

truth table.
Procedural blocks:
procedural statements are used to describe the behavior of a design in
terms of operations that occur over time, rather than specifying the
physical hardware structure. Procedural statements are used within
procedural blocks, primarily within always and initial blocks.
There are two types of procedural blocks

Blocking Assignments (=):

• Blocking assignments are used to assign values to variables or nets
sequentially within a procedural block.
• The statement on the left side of the assignment is executed before the
statement on the right side.
Non-blocking Assignments (<=):
• Non-blocking assignments schedule assignments to occur
simultaneously within the same time step.
• The statement on the right side of the assignment is evaluated
before the statement on the left side, but the actual assignment
doesn't occur until the end of the time step.
• Non-blocking assignments are commonly used for modeling flip-
flops and other sequential logic elements.
Conditional Statements (if, else if, else):
• Conditional statements are used to execute different
code blocks based on certain conditions.
• They are useful for creating conditional logic within
procedural blocks
Case Statements (case, casez, casex):
• Case statements are used to select one or more statements based
on the value of a variable or expression.
• They provide a more concise way to express conditional behavior
than using nested if-else statements.
Always and initial block :
Initial block
There can be multiple initial blocks.
An initial block is started at the beginning of a simulation at time 0
unit. This block will be executed only once during the entire
simulation. Execution of an initial block finishes once all the
statements within the block are executed, as shown in the following
image.
Always block:
In Verilog, the always block is one of the procedural blocks.
Statements inside an always block are executed sequentially.

An always block always executes, unlike initial blocks that execute

only once at the beginning of the simulation. The always block should
have a sensitive list or a delay associated with it

The sensitive list is the one that tells the always block when to execute
the block of code.
Verilog regions:
The Verilog regions are,
• Active region
• Inactive region
• NBA(non-blocking assignments)
• Postponed region
Active region:
The active region is used to hold current events being evaluated and
can be processed in any order.

Inactive region:
The inactive region holds the events to be evaluated after all the
active events are processed. An explicit zero delay (#0) requires that
the process be suspended and an event scheduled into the inactive
region of the current time slot so that the process can be resumed in
the next inactive to active iteration.
NBA:
Non-blocking Assignment Events region (NBA)The principal function
of this region is to execute the updates to the Left-Hand-Side (LHS)
variables that were scheduled in the Active region for all currently
executing nonblocking assignments.

Postponed region:
Also known as monitor region.
Verilog Display Tasks. $monitor prints out variable or expression
values whenever the variable or expression in its argument list
changes. So, at S0 state, nothing changes so you won't get it printed
unless you change code.