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Swami Keshvanand Institute of Technology, Management &Gramothan,

Ramnagaria, Jagatpura, Jaipur-302017, INDIA

Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

Lecture-1

UNIT-I
COURSE OUTCOMES
After completion of this course, students will be able to
1. Understand basic mos technology with high order effects and the scaling effects on mos transistor
circuit model parameters.
2. Compare different MOS inverters based on inverter parameters with speed and power dissipation
analysis.
3. Apply layout design rules to design layouts of CMOS circuits with the clear understanding of
interconnect issues
4. Describe different types of memories anddynamic CMOS VLSI circuits.
5. Use EDA tools for VLSI Circuit design and model a system using VHDL.

COURSE OBJECTIVES
 The course provides for final year undergraduates a solid and fundamental engineering view of
digital system operation and how to design systematically well performing digital VLSI systems
exceeding consistently, customer expectations and competitor fears.
 The aim is to teach the critical methods and circuit structures to identify the key of the circuitry on-
chip which dominates the performance, reliability, manufacturability, and the cost of the VLSI
circuit.
 With the current utilization of the deep submicron CMOS technologies (0.25 micron and below
design rules) the major design pattern is associated with the fact that the interconnections (metal
Al or Cu wires connecting gates) and the chip communication in general is the main design object
instead of active transistors or logic gates.
 The main design issues defining the make-or-break point in each project is associated with power
and signal distribution and bit/symbol communication between functional blocks on-chip and off-
chip.
 The course objective is to provide the student with a solid understanding of the underlying
mechanism and solution techniques, so that the student, when working as industrial designer, is
capable of identifying the key problems and focus his creative attention and 90% of available
resources to right issues for 1% of the circuitry and leave the remaining 99% of circuitry to
computer automated tools.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

WHAT IS VLSI ?
 VLSI refers
• V : Very
• L : Large
• S : Scale
• I : Integrated Circuits
 VLSI is a process of creating an integrated circuit (IC) by combining thousands of transistors into
a single Silicon Chip.

INTEGRATED CIRCUITS ERA

 Transistor was first invented by William. B. Shockley, Walter Brattain and John Bardeen of Bell
laboratories. In 1961, first IC was introduced.
 Levels of Integration:-
 SSI: - (10-100) transistors => Example: Logic gates
 MSI: - (100-1000) => Example: counters
 LSI: - (1000-20000) => Example: 8-bit chip
 VLSI: - (20000-1000000) => Example: 16 &32 bit up
 ULSI: - (1000000-10000000) => Example: Special processors, virtual reality
machines, smart sensors.
Moore’s Law
In1965, Gordon Moore predicted the way the circuit design and fabrication technology would evolve over
the years and introduced a law: The number of transistors embedded on the chip doubles after every 18
months
1,000,000,000

100,000,000
Pentium 4
Pentium III
10,000,000 Pentium II
Pentium Pro
Pentium
Intel486
1,000,000
Intel386
80286
100,000
8086
10,000 8080
8008
4004
1,000

1970 1975 1980 1990 1995 2000

VLSI TECHNOLOGY
 CMOS (Complementary Metal Oxide Semiconductor)
 CMOS technology uses both PMOS and NMOS transistors
 The transistors are arranged in a structure formed by two complementary networks:
Pull-up network and pull-down network
 Pull-up network is complement of pull-down
 BiCMOS technology is also used in places where high driving capability is required but BiCMOS
consumes more power compared to CMOS.

CMOS
 The term CMOS stands for “Complementary Metal Oxide Semiconductor”.
 This technology makes use of both P channel and N channel semiconductor devices.
 most popular technology in the computer chip design industry
 Today’s computer memories, CPUs and cell phones make use of this technology due to several
key advantages.
 The main features of CMOS technology are low static power consumption and high noise
immunity.
 It draws significant power only during switching between ON & OFF states

COMPARISON BETWEEN CMOS AND BIPOLAR TECHNOLOGIES

CMOS BIPOLAR TECHNOLOGIES
Low static power dissipation High power dissipation
• High input impedance • Low input impedance
• High noise margin • Low voltage swing logic
• High packing density • Low packing density
• High delay sensitivity to load • Low delay sensitivity to load
• Low output drive current • High output drive current
• Bidirectional capability • Essentially unidirectional
• A near ideal switching device
• Scalable threshold voltage
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

VLSI DESIGN FLOW

The VLSI design cycle starts with a formal specification of a VLSI chip, follows a series of steps, and
eventually produces a packaged chip. A typical design cycle may be represented by the flow chart
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

VLSI Applications
 VLSI is an implementation technology for electronic circuitry - analogue or digital
 It is concerned with forming a pattern of interconnected switches and gates on the surface of a
crystal of semiconductor
 Microprocessors
 personal computers
 microcontrollers
 Memory - DRAM / SRAM
 Special Purpose Processors - ASICS (CD players, DSP applications)
 Optical Switches
 Mass production of highly sophisticated control systems therefore cheap

Advantages
VLSI has many advantages:
 Reduces the Size of Circuits.
 Reduces the effective cost of the devices.
 Increases the Operating speed of circuits
 Reduces the current consumption
 Requires less power than discrete components.
 Higher Reliability
 Occupies a relatively smaller area.

Future Scope
 Race is going on to make the devices as small as possible with highest possible efficiency and low
power. For this we surely need smallest possible IC with lot many peripherals in it. But at the same
time, power consumption should be low. Take any of the high end microcontroller IC and see what
all peripherals are into it. ADC, DAC, Communication protocols (SPI, I2C, Serial, Ethernet etc),
timers, crystal oscillators, variety of clock systems etc. For designing such ICs, think for yourself
as how much VLSI has gone far to develop these. Vast scope in this field too.
 Today many companies like Texas Instruments, Infineon, Alliance Semiconductors, Cadence,
Synopsys, Celox Networks, Cisco, Micron Tech, National Semiconductors, ST Microelectronics,
Qualcomm, Lucent, Mentor Graphics, Analog Devices, Intel, Philips, Motorola and many other
firms have been established and are dedicated to the various fields in "VLSI" like Programmable
Logic Devices, Hardware Descriptive Languages, Design tools, Embedded Systems etc.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

Lecture-2

UNIT-II
NMOS FABRICATION
NMOS FABRICATION PROCESS
Each processing step requires that certain areas are defined on chip by appropriate masks. Consequently,
the integrated circuit may be viewed as a set of patterned layers of doped silicon, polysilicon, metal, and
insulating silicon dioxide. In general, a layer must be patterned before the next layer of material is applied
on the chip. The process used to transfer a pattern to a layer on the chip is called lithography. Since each
layer has its own distinct patterning requirements, the lithographic sequence must be repeated for every
layer, using a different mask.

Photoresist
o Photoresist is a light-sensitive material.
o The type of photoresist which is initially insoluble and becomes soluble after exposure to UV light is
called positive photoresist. The process sequence shown here uses positive photoresist.
o There is another type of photoresist which is initially soluble and becomes insoluble (hardened) after
exposure to UV light, called negative photoresist.
o If negative photoresist is used in the photolithography process, the areas which are not shielded from
the UV light by the opaque mask features become insoluble, whereas the shielded areas can
subsequently be etched away by a developing solution.
o Negative photoresists are more sensitive to light, but their photolithographic resolution is not as high
as that of the positive photoresists. Therefore, negative photoresists are-used less commonly in the
manufacturing of high-density integrated circuits.

Process Steps Required for Patterning of Silicon dioxide

 The sequence starts with the thermal oxidation of the silicon surface, by which an oxide layer of about
1 um thickness, for example, is created on the substrate
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

 The entire oxide surface is then covered with a layer of photoresist, which is essentially a light-
sensitive, acid-resistant organic polymer, initially insoluble in the developing solution.

 If the photoresist material is exposed to ultraviolet (UV) light, the exposed areas become soluble so
that they are no longer resistant to etching solvents.

 To selectively expose the photoresist, we have to cover some of the areas on the surface with a mask
during exposure. Thus, when the structure with the mask on top is exposed to UV light, areas which
are covered by the opaque features on the mask are shielded. In the areas where the UV light can pass
through, on the other hand, the photoresist is exposed and becomes soluble.

 Following the UV exposure step, the unexposed portions of the photoresist can be removed by a
solvent. Now, the silicon dioxide regions which are not covered by hardened photoresist can be etched
away either by using a chemical solvent (HF acid) or by using a dry etch (plasma etch) process. At the
end of this step, we obtain an oxide window that reaches down to the silicon surface.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

 The remaining photoresist can now be stripped from the silicon dioxide surface by using another
solvent, leaving the patterned silicon dioxide feature on the surface as shown in Fig.

 These sequence of process steps actually accomplishes a single pattern transfer onto the silicon
dioxide surface. The fabrication of semiconductor devices requires several such pattern transfers to be
performed on silicon dioxide, polysilicon, and metal. The basic patterning process used in all
fabrication steps, however, is quite similar to the one shown here.

NMOS TRANSISTOR FABRICATION STEPS

Step 1: Substrate Selection

Processing is carried on single crystal silicon of high purity on which required P impurities are introduced
as crystal is grown. Such wafers are about 75 to 150 mm in diameter and 0.4 mm thick and they are doped
with say boron to impurity concentration of 10 to power 15/cm3 to 10 to the power 16 /cm3.

Step 2: Oxidation
The oxidation process is done by using high-purity oxygen and hydrogen, which are exposed in an
oxidation furnace approximately at 1000 0centigrade. A layer of silicon dioxide (SiO2) typically 1
micrometer thick is grown all over the surface of the wafer to protect the surface, acts as a barrier to
the dopant during processing, and provides a generally insulating substrate on to which other layers may
be deposited and patterned.

Step 3: Photoresist
A light-sensitive polymer that softens whenever exposed to light is called as Photo resist layer. It is
formed. The surface is now covered with the photo resist which is deposited onto the wafer and spun to an
even distribution of the required thickness.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

Step 4: Masking
The photo resist is exposed to UV rays through the N-well mask. The photo resist layer is then exposed to
ultraviolet light through masking which defines those regions into which diffusion is to take place together
with transistor channels. Assume, for example, that those areas exposed to UV radiations are polymerized
(hardened), but that the areas required for diffusion are shielded by the mask and remain unaffected.

Step 5: Photo resist removal

A part of the photo resist layer is removed by treating the wafer with the basic or acidic solution.
These areas are subsequently readily etched away together with the underlying silicon di oxide so that the
wafer surface is exposed in the window defined by the mask.

Step 6: Removal of SiO2 using acid etching

The SiO2 oxidation layer is removed through the open area made by the removal of photoresist using
hydrofluoric acid.

Step 7: Thin layer of gate oxide

Process is used to deposit a very thin layer of gate oxide. The remaining photo resist is removed and a thin
layer of SiO2 (0.1 micro m typical) is grown over the entire chip surface
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

Step 8: Deposition of polysilicon

Poly silicon is deposited on the top of this to form the gate structure. The polysilicon layer consists of
heavily doped polysilicon deposited by chemical vapour deposition (CVD). In the fabrication of fine
pattern devices, precise control of thickness, impurity concentration, and resistivity is necessary Further
photo resist coating and masking allows the poly silicon to be patterned and then the thin oxide is removed
to expose areas into which n-type impurities are to be diffused to form the source and drain. Diffusion is
achieved by heating the wafer to a high temperature and passing a gas containing the desired n-type
impurity. The poly silicon with underlying thin oxide and the thick oxide acts as mask during diffusion the
process is self-aligning.

Step 9: Oxidation process

Thick oxide (SiO2) is grown over all again and is then masked with photo resist and etched to expose
selected areas of the poly silicon gate and the drain and source areas where connections are to be made.

Step 10: Masking and N-diffusion by using the masking process small gaps are made for the purpose of
N-diffusion.

Step 11: Metallization

The whole chip then has metal (aluminum) deposited over its surface to a thickness typically of 1 micro m. This
metal layer is then masked and etched to form the required interconnection pattern.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

Step 12: Patterning

Finally, the metal layer is patterned and etched, completing the interconnection of the MOS transistors on
the surface. Usually, a second layer of metallic interconnect can also be added on top of this structure by
creating another insulating oxide layer, cutting contact, depositing, and patterning the metal.

CMOS: “Complementary Metal Oxide Semiconductor”

 CMOS technology uses both PMOS and NMOS transistors
 The transistors are arranged in a structure formed by two complementary networks:
Pull-up network and pull-down network
 Pull-up network is complementary of pull-down

COMPARISON BETWEEN CMOS AND BIPOLAR TECHNOLOGIES

CMOS
• Low static power dissipation
• High input impedance
• High noise margin
• High packing density
• High delay sensitivity to load
• Low output drive current
• Bidirectional capability
• A near ideal switching device
• Scalable threshold voltage
BIPOLAR TECHNOLOGIES
• High power dissipation
• Low input impedance
• Low voltage swing logic
• Low packing density
• Low delay sensitivity to load
• High output drive current
• Essentially unidirectional
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

Lecture-3
CMOS: “Complementary Metal Oxide Semiconductor”
 CMOS technology uses both PMOS and NMOS transistors
 The transistors are arranged in a structure formed by two complementary networks:
Pull-up network and pull-down network
 Pull-up network is complementary of pull-down

CMOS Fabrication
The CMOS can be fabricated using following processes:
 N-well process
 P-well process
 Twin tub process
 Silicon On Insulator
 For integrating these NMOS and PMOS devices on the same chip, special regions called as “wells”
are required in which semiconductor type and substrate type are opposite to each other.
 A P-well has to be created on a N-substrate or N-well has to be created on a P-substrate.
 The fabrication sequence consists of a series of steps in which layers of the chip are defined through
photolithography process.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

Inverter Mask View

The inverter could be defined by a hypothetical set of six masks:

1. n-well mask

2. Polysilicon pattern

3. n diffusion mask

4. p diffusion mask
5. Contact cut mask

6. Metal layer pattern

Simplified Process Sequence For Fabrication Of CMOS ICs

CMOS FABRICATION: N-well Process

 Step 1: First we choose a substrate as a base for fabrication. For N- well, a P-type silicon substrate is
selected.

 Step 2 – Oxidation: The selective diffusion of n-type impurities is accomplished using SiO2 as a
barrier which protects portions of the wafer against contamination of the substrate. Oxidation process
is carried out by exposing the substrate to high-quality oxygen and hydrogen in an oxidation chamber
at approximately 10000C

 Step 3 –Photoresist deposition: To permit the selective etching, the SiO2 layer is subjected to the
photolithography process. In this step, the wafer is coated with a uniform film of a photosensitive.

Step 4 – Masking: In this step, a desired pattern is made using a mask over the photoresist. The substrate
is exposed to UV light. The photoresist present under the exposed regions of mask gets polymerized.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

 Step 5 – Removal of Unexposed Photoresist: The mask is removed and the unexposed region of
photoresist is etched away by developing wafer in chemical such as Trichloroethylene.

 Step 6 – Etching: The wafer is immersed in an etching solution of hydrofluoric acid, which removes
the oxide from the areas through which dopants are to be diffused.

 Step 7 – Removal of Whole Photoresist Layer: During the etching process, those portions of SiO2
which are protected by the photoresist layer are not affected. The photoresist mask is now stripped off
with a chemical solvent (hot H2SO4).

 Step 8 – Formation of N-well: The n-type impurities are diffused into the p-type substrate through
the exposed region thus forming an N- well.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
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 Step 9 – Removal of SiO2: The layer of SiO2 is now removed by using hydrofluoric acid.

 Step 10 – Deposition of Polysilicon: The misalignment of the gate of a CMOS transistor would lead
to the unwanted capacitance which could harm the circuit. To prevent this “Self-aligned gate process”
is preferred where gate regions are formed before the formation of source and drain using ion
implantation.

 Polysilicon is used for formation of the gate because it can withstand the high temperature when a
wafer is subjected to annealing methods for formation of source and drain. Polysilicon is deposited by
using Chemical Deposition Process over a thin layer of gate oxide. This thin gate oxide under the
Polysilicon layer prevents further doping under the gate region.
 Step 11 – Formation of Gate Region: Except the two regions required for formation of the gate
for NMOS and PMOS transistors the remaining portion of Polysilicon is stripped off.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
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Step 12 – Oxidation Process: An oxide layer is deposited over the wafer which acts as a shield for
further diffusion and metallization processes.

 Step 13 – Masking and Diffusion: For making regions for diffusion of n-type impurities using
masking process small gaps are made.

Using diffusion process three n+ regions are developed for the formation of terminals of NMOS.
 Step 14 – Removal of Oxide: The oxide layer is stripped off.

 Step 15 – P-type Diffusion: Similar to the n-type diffusion for forming the terminals of PMOS p-type
diffusions are carried out.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
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 Step 16 –Thick Field oxide deposition: Before forming the metal terminals a thick field oxide is
deposited to form a protective layer for the regions of the wafer where no terminals are required

 Step 17 – Metallization: This step is used for the formation of metal terminals which can provide
interconnections. Aluminum is preferred.

 Step 18 – Removal of Excess Metal: The excess metal is removed from the wafer.
 Step 19 – Formation of Terminals: In the gaps formed after removal of excess metal terminals are
formed for the interconnections.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
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CMOS FABRICATION: P-well Process

The p-well process is similar to N well process except that here n-type substrate is used and p-type
diffusions are carried out. For simplicity usually, N well process is preferred.

Vin

Vout
VDD VSS

Polysilicon
Oxide
n-diffusion
P-diffusion

Twin-tub structure
( A logical extension of the p-well and n-well)
Vin

Vout
VDD VSS

Epitaxial
n well p well layer

n substrate

Polysilicon
Oxide
n-diffusion
P-diffusion
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
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SILICON ON INSULATOR (SOI)

silicon on insulator (SOI) technology is fabrication of silicon semiconductor devices in a layered silicon–
insulator–silicon substrate, to reduce parasitic capacitance within the device, thereby improving
performance. SOI-based devices differ from conventional silicon-built devices in that the silicon junction
is above an electrical insulator, typically silicon dioxide or sapphire (these types of devices are
called silicon on sapphire, or SOS). The choice of insulator depends largely on intended application, with
sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and
silicon dioxide for diminished short-channel effects in other microelectronics devices. The insulating layer
and topmost silicon layer also vary widely with application.

Advantages and Disadvantages of SOI

 This technology offers advantages in the form of higher integration density (because of the
absence of well regions), complete avoidance of the latch-up problem, and lower parasitic
capacitances compared to the conventional n-well or twin-tub CMOS processes.
 The insulating layer increases device performance by reducing junction capacitance as the junction
is isolated from bulk silicon. The decrease in junction capacitance also reduces overall power
consumption.
 But this technology comes with the disadvantage of higher cost than the standard n-well CMOS
process. Yet the improvements of device performance and the absence of latchup problems can
justify its use, especially in deep submicron devices.
**Latch-Up is a condition where a low impedance path is created between a supply pin and ground. This
condition is caused by a trigger (current injection or overvoltage), but once activated, the low impedance
path remains even after the trigger is no longer present. This low impedance path may cause system upset
or catastrophic damage due to excessive current levels. The Latch-Up condition typically requires a power
cycle to eliminate the low impedance path.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
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Lecture-4
BASIC MOS STRUCTURE
MOS structure contains three layers −
 The Metal Gate Electrode
 The Thin Insulating Oxide Layer(SiO2)
 P-Type Semiconductor (substrate)
MOS structure forms a capacitor, with gate and substrate are as two plates and oxide layer as the dielectric
material.

Mass Action Law

The equilibrium concentrations of mobile carriers in a semiconductor always follow the Mass Action Law
given by
----1

nthe mobile carrier concentrations of electrons

p  the mobile carrier concentrations of holes,
nidenotes the intrinsic carrier concentration of silicon, which is a function of the temperature T.
 Assuming that the substrate is uniformly doped with an acceptor (e.g., Boron) concentration NA, the
equilibrium electron and hole concentrations in the p-type substrate are approximated by

ENERGY BAND DIAGRAM OF MOS STRUCTURE

 The Fermi Potential is a function of temperature and doping, denotes the difference between the
intrinsic Fermi level Ei, and the Fermi level EF
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 For a p-type semiconductor, the Fermi potential can be approximated by

 Similarly, for n-type semiconductor, the Fermi potential can be approximated by

Energy band diagram of combined MOS system

 The electron affinity of silicon, which is the potential difference between the conduction band level
and the vacuum (free-space) level, is denoted by qχ.
 The energy required for an electron to move from the Fermi level into free space is called the work
function and is given by

The bulk Fermi level is not significantly affected by the band bending, whereas the surface Fermi level
moves closer to the intrinsic Fermi (mid-gap) level. The Fermi potential at the surface, also called surface
potential φs, is smaller in magnitude than the bulk Fermi potentialΦF.
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The MOS System under External Bias

o Assume that the substrate voltage is set at VB = 0,
o Depending on polarity and magnitude of input gate voltage, three different operating regions can
be observed for the MOS system: accumulation, depletion, and inversion.
 Accumulation mode: If a negative voltage is applied to the gate electrode.

Fig: The cross-sectional view and the energy band diagram of the MOS structure operating in
accumulation region.

 Depletion mode: If a small positive gate voltage is applied

Fig: The cross-sectional view and the energy band diagram of the MOS structure operating in
depletion region.
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o The thickness xd of this depletion region on the surface can be found as a function of the surface
potential φs.
o Assume that the mobile hole charge in a thin horizontal layer parallel to the surface is

o The change in surface potential required to displace this charge sheet dQby a distance xd away
from the surface can be found by using the Poisson equation.

o Integrating along the vertical dimension (perpendicular to the surface) yields

o Thus, the depth of the depletion region is

o the depletion region charge density, (which consists solely of fixed acceptor ions) is given by the
following expression

 Inversion mode: further increase in the positive gate bias

o the surface is said to be inverted when the density of mobile electrons on the surface becomes
equal to the density of holes in the bulk (p type) substrate.
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Difference Between BJT and MOSFET

 The BJT is a bipolar junction transistor whereas MOSFET is a metal oxide semiconductor field-effect
transistor.
 A BJT has three terminals namely base, emitter, and collector, while a MOSFET has four terminals
namely source, drain, gate and substrate.
 BJT’s are used for low current applications, whereas MOSFET is used for high power applications.
 Nowadays, in analog and digital circuits, MOSFETs are treated to be more commonly used than BJTS.
 The working of BJT depends on the current at the base terminal and the working of the MOSFET
depends on the voltage at the oxide insulated gate terminal.
 The BJT is a current controlled device and MOSFET is a voltage-controlled device.

Advantages of FET over conventional Transistors

 Unipolar device i.e. operation depends on only one type of charge carriers (h or e)
 Voltage controlled Device (gate voltage controls drain current)
 Very high input impedance
 Source and drain are interchangeable in most Low-frequency applications
 Low Voltage Low Current Operation is possible (Low-power consumption)
 Less Noisy as Compared to BJT
 Very small in size, occupies very small space in ICs

MOSFET
MOSFET stands for Metal Oxide Semiconductor Field Effect Transistor. This is also called as IGFET
meaning Insulated Gate Field Effect Transistor. The FET is operated in both depletion and enhancement
modes of operation.

MOSFET (IGFET)

Enhancement Depletion
MOSFET MOSFET

n-Channel p-Channel n-Channel p-Channel

EMOSFET EMOSFET DMOSFET DMOSFET
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MOSFET STRUCTURE
A MOSFET or MOS transistor, is a device where current through a channel between the source and drain
is controlled by the voltage applied to the gate.

Fig. physical structure of an n-channel enhancement-type MOSFET

In PMOS current is carried by holes and in NMOS it‘s by electrons. Since the mobility is of holes less
than that of electrons PMOS is slower.

NMOS Transistors Symbols

The N-channel MOSFETs are simply called as NMOS. The symbols for N-channel MOSFET are as
givenbelow.
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PMOS Transistors Symbols

The P-channel MOSFETs are simply called as PMOS. The symbols for P-channel MOSFET are as given
below.

MOS transistors Simplified Symbols without substrate

D D

G G

S S
NMOS Enhancement NMOS Depletion

D D

G G

S S
PMOS Enhancement PMOS Depletion
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MOSFET
(Metal Oxide Semiconductor Field Effect Transistor)
 The name Metal Oxide Semiconductor transistor, because the structure consists of a layer of Metal
(gate), a layer of oxide(SiO2) and a layer of semiconductor.

 In Enhancement type transistor channel is going to form after giving a proper positive gate voltage.
(Device has +ve threshold). The transistor requires a Gate-Source voltage, (VGS) to switch the device
“ON”. The enhancement mode MOSFET is equivalent to a “Normally Open” switch.

In Depletion type transistor During fabrication, a thin channel is built under the gate. It can be removed
by giving a proper negative gate voltage. (Device has -ve threshold). i.e. The transistor requires the Gate-
Source voltage, ( VGS ) to switch the device “OFF”. The depletion mode MOSFET is equivalent to a
“Normally Closed” switch.

MOS OPERATION
 Mode of operation depends on Vgs, Vds, Vgd
Vgs = Vg – Vs
Vgd = Vg – Vd
Vds = Vd – Vs = Vgs – Vgd

Three Regions:

1. “Cut-off”: Virtually no current flows, except the source-drain leakage current.

2. “Linear”: Weak inversion; Drain current increases linearly with drain-source voltage.

3. “Saturation”: Strong inversion; Drain current independent of drain voltage.

+ +
Vgs Vgd
- -
Vs Vd
-
Vds +
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NMOS: Enhancement Mode

 The Enhancement mode MOSFET is commonly used type of transistor. This type of MOSFET is
equivalent to normally-open switch because it does not conduct when the gate voltage is zero. If the
positive voltage (+VGS) is applied to the N-channel gate terminal, then the channel conducts and the
drain current flows through the channel.
 Operating principle of this device is: control the current conduction between the source and the drain,
using the electric field generated by the gate voltage as a control variable.
 Since the current flow in the channel is also controlled by the drain to-source voltage and by the
substrate voltage, the current can be considered a function of these external terminal voltages.

NMOS with no gate voltage

Metal (or conductor )
VGS = 0
Small depletion Insulator (Sio2)
G
layer S D VDS = 0
n+ n+

Cutoff
If VGS = 0;
Back-to-back diodes are formed. These back-to-back diodes prevent current conduction from drain to
source when a voltage VDS is applied.
No current between the Source &Drain (ID = 0)

NMOS with small positive gate bias:

 For small gate voltage levels, the majority carriers (holes) are repelled back into the substrate, and the
surface of the p-type substrate is depleted.
 Since the surface is devoid of any mobile carriers, current conduction between the source and the drain
is not possible.
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Formation of Inversion Layer (Channel):

NMOS Operation: Linear Region

VDS small + ve

0 < VDS < VGS - VT

ID > 0

IDS = f (VGS , VDS )

• At VDS = 0, thermal equilibrium exists in the inverted channel region, and the drain current IDis equal
to zero.
• If a small drain voltage VDS>0 is applied, a drain current proportional to VDSwill flow from the source
to the drain through the conducting channel.
• This operation mode is called the linear mode, or the linear region.
• As the drain voltage is increased, the inversion layer charge and the channel depth at the drain end
start to decrease.
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NMOS Operation: Saturation (pinch-off)

 For VDS = VDSAT, the inversion charge at the drain is reduced to zero, which is called the pinch-off
point.
 Beyond the pinch-off point, i.e., for VDS>VDSAT, a depleted surface region forms adjacent to the drain,
and this depletion region grows toward the source with increasing drain voltages.
 This operation mode of the MOSFET is called the saturation mode or the saturation region;
 For a MOSFET operating in the saturation region, the effective channel length is reduced as the
inversion layer near the drain vanishes, while the channel-end voltage remains essentially constant and
equal to VDSAT. The pinched-off (depleted) section of the channel absorbs most of the excess voltage
drop (VDS - VDSAT) and a high-field region forms between the channel-end and the drain boundary.
Electrons arriving from the source to the channel-end are injected into the drain-depletion region and
are accelerated toward the drain in this high electric field, usually reaching the drift velocity limit.

NMOS CHARACTERISTICS
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P-Channel MOSFET
The P- Channel MOSFET has a P- Channel region between source and drain. The drain and source are
heavily doped p+ region and the body or substrate is n-type. The flow of current is positively charged
holes. When we apply the negative gate voltage, the electrons present under the oxide layer with are
pushed downward into the substrate with a repulsive force. The depletion region populated by the bound
positive charges which are associated with the donor atoms. The negative gate voltage also attracts holes
from p+ source and drain region into the channel region.

PMOS CHARACTERISTICS
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Depletion Mode MOSFET

 Depletion mode FETs have a channel implanted such that there is conduction
with VGS=0
 The operation is the same as the enhancement mode FET, but the threshold
voltage is shifted
 Threshold voltage (Vt) is negative for depletion type NMOS, and positive for depletion type PMOS.

Important Points:
• In field-effect transistors (FETS), depletion mode and enhancement mode are two major transistor
types, corresponding to whether the transistor is in an ON state or an OFF state at zero gate-source
voltage.
• Enhancement-mode MOSFETS (metal–oxide–semiconductor FETs) are the common switching
elements in most integrated circuits. These devices are off at zero gate–source voltage. NMOS can be
turned on by pulling the gate voltage higher than the source voltage, PMOS can be turned on by
pulling the gate voltage lower than the source voltage.
• In a depletion-mode MOSFET, the device is normally ON at zero gate–source voltage. Such devices
are used as load "resistors" in logic circuits.
• For an N-type MOSFET, enhancement-mode devices have positive thresholds, and depletion-mode
devices have negative thresholds.
• For a P-type MOSFET, enhancement-mode devices have negative thresholds, and depletion-mode
devices have positive thresholds.

NMOS Operating Modes:

• Cut off Region: (i) VGS<VT ; (ii) VGS< VT and VDS = 0;
• Linear Region: VGS ≥ VTandVDS<VGS - VT
• Saturation Region VGS ≥ VT and VDS ≥ VGS - VT

PMOS Operating Modes:

• Cut off Region: (i) VGS>VT ; (ii) VGS> VT and VDS = 0;
• Linear Region: VGS ≤ VTandVDS>VGS - VT
• Saturation Region VGS ≤ VT and VDS ≤ VGS - VT
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Lecture-5
Threshold Voltage
 The value of the gate-to-source voltage VGS needed to cause surface inversion (to create the
conducting channel) is called the threshold voltage VT0.
 For gate-to-source voltages larger than the threshold voltage, a larger number of electrons are attracted
to the surface, which contribute to channel current conduction.
 Further increasing the gate to source voltage beyond the threshold voltage will not affect the surface
potential and the depletion region depth.

Aspects of Threshold Voltage

There are four physical components of the threshold voltage:
(i) the work function difference between the gate and the channel
(ii) the gate voltage component to change the surface potential at inversion
(iii) the gate voltage component to offset the depletion region charge
(iv) the voltage component to offset the fixed charges in the gate oxide and in the silicon-oxide
interface.
 The work function difference FGC between the gate and the channel reflects the built-in potential of
the MOS system, which consists of the p-type substrate, the thin silicon dioxide layer, and the gate
electrode. Depending on the gate material, the work function difference is

ΦGC= ΦF (substrate) - ΦM for metal gate

ΦGC= ΦF (substrate) - ΦF (gate) for polysilicon gate

 This first component of the threshold voltage accounts for part of the voltage drop across the MOS
system that is built-in. V1 = FGC
 Now, the second component of the threshold voltage is the externally applied gate voltage which is
required to achieve surface inversion

V2 = ΦS -ΦF = -2ΦF as ΦS = -ΦF

 Now, the third component of the threshold voltage is the necessary to offset the depletion region
charge. which is due to the fixed acceptor ions located in the depletion region near
the surface.
 We know that depletion region charge density is which solely consist of acceptor ions is given by

Q = -qNAxd= - -

 Now, Depletion region charge density at surface inversion(fS=-fF)

So, = Q = - -qNAxd= - -

 Now if body of the MOSFET is attached with potential other than ground potential then a source to
substrate voltage (VSB) is added to it

= -qNAxd= - -

 The third component that offsets the depletion region charge is

V3 = -QB / Cox
 Where COX is the gate oxide capacitance per unit area.

Cox = εox / tox

 Due to the influence of a non ideal physical phenomenon, there always exists a fixed positive charge
density Qox at the interface between the gate oxide and the silicon substrate, due to impurities and/or
lattice imperfections at the interface.
The (fourth) gate voltage component that is necessary to offset this positive charge at the interface is
V4 = -Qox / Cox
 Combining all of these voltage components
VT = V1 + V2 + V3 + V4
 For zero substrate bias, the threshold voltage VT0 is expressed as follows

 The generalized threshold voltage expression is given as

Substrate Bias Effect:

 The generalized form of the threshold voltage can also be written in terms of VT0

 Thus, the most general expression of the threshold voltage VT can be found as follows:

 Where  substrate bias (or body-effect) coefficient.

 The threshold voltage expression can be used both for n-channel and p-channel MOS transistors.
 But some of the terms and coefficients in this equation have different polarities for the n-channel
(nMOS) and for the p-channel (pMOS).
 The reason for this polarity difference is that the substrate semiconductor is p-type in an n-channel
MOSFET and n-type in a p-channel MOSFET.
o The substrate Fermi potential ΦF is negative in nMOS, positive in pMOS.
o The depletion region charge densities QB0 and QB are negative in nMOS, positive in pMOS.
o The substrate bias coefficient is positive in nMOS, negative in pMOS.
o The substrate bias voltage VSB is positive in nMOS, negative in pMOS.
 Typically, the threshold voltage of an enhancement-type n-channel MOSFET is a positive quantity,
whereas the threshold voltage of a p-channel MOSFET is negative.
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Lecture-6
Vds-Ids Characteristics
• The MOS transistors are voltage controlled device. A voltage on the gate terminal induces a charge in
the channel, that move from source to drain under the influence of electric field generated by voltage
Vds applied between drain and source
• The induced charge is dependent on the gate to source voltage VGS (controlling voltage).
• The current Ids is dependent on both VGS and VDS.

Fig : NMOS Transistor Structure

NMOS with small positive gate bias:

Formation of Inversion Layer (Channel):

 Now the gate-to-source voltage is further increased.
 a conducting n-type layer will form between the source and the drain diffusion regions.
 The value of the gate-to-source voltage VGS needed to cause surface inversion (to create the
conducting channel) is called the threshold voltage VTO.
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NMOS Operation: Linear Region:

 At VDS = 0, thermal equilibrium exists in the inverted channel region, and the drain current ID is
equal to zero.
 If a small drain voltage VDS >0 is applied, a drain current proportional to VDS will flow from the
source to the drain through the conducting channel.
 This operation mode is called the linear mode, or the linear region.
 As the drain voltage is increased, the inversion layer charge and the channel depth at the drain end
start to decrease.

NMOS Operation: Saturation (pinch-off):

 For VDS = VDSAT, the inversion charge at the drain is reduced to zero, which is called the pinch-off
point.
 Beyond the pinch-off point, i.e., for VDS >VDSAT, a depleted surface region forms adjacent to the
drain, and this depletion region grows toward the source with increasing drain voltages.
 This operation mode of the MOSFET is called the saturation mode or the saturation region;
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V-I characteristic equation (Drain Current equation) for linear and saturation modes: we will use
the gradual channel approximation (GCA) is used for establishing the MOSFET current-voltage
relationships, which will effectively reduce the analysis to a one-dimensional current-flow problem.
This will allow us to devise relatively simple current equations that agree well with experimental results.
As in every approximate approach, however, the GCA also has its limitations, especially for small-
geometry MOSFETs.

Gradual Channel Approximation

• To begin with the current-flow analysis, consider the cross-sectional view of the n channel MOSFET
operating in the linear mode, Here, the source and the substrate terminals are connected to ground, i.e.,
Vs = VB = 0.
• The gate-to-source voltage (VGS) and the drain-to-source voltage (VDS) are the external parameters
controlling the drain (channel) current ID. The gate-to-source voltage is set to be larger than the
threshold voltage V, to create a conducting inversion layer between the source and the drain.
• We define the coordinate system for this structure such that the x-direction is perpendicular to the
surface, pointing down into the substrate, and the y-direction is parallel to the surface. The y-
coordinate origin (y = 0) is at the source end of the channel.

Fig: Simplified geometry of the surface inversion layer (channel region)

The thickness of the inversion layer tapers off as movefrom the source to the drain, since the gate-to-
channel voltage causing surface inversion is smaller at the drain end
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The channel voltage with respect to the source will be denoted by Vc (y). Now assume that the threshold
voltage is constant along the entire channel region, between y = 0 and y = L. In reality, the threshold
voltage changes along the channel since the channel voltage is not constant. the channel voltage VC are:
VC(y =0 ) = Vs =0
VC (y=L)=VDS
it is also, assumed that the entire channel region between the source and the drain is inverted, i.e.,
VGS≥VT0
VGD=VGS -VDS≥VT0
Let Q(y) be the total mobile electron charge in the surface inversion layer. This charge can be expressed as
a function of the gate-to-source voltage VGS and of the channel voltage VC(y) as follows:
QI(y)= - Cox.[ VGS- VC(y)-VT0]
Now consider the incremental resistance dR of the differential channel segment Assuming that all mobile
electrons in the inversion layer have a constant surface mobility (µn), the incremental resistance can be
expressed as follows. Note that the minus sign is due to the negative polarity of the inversion layer charge
Q1(y)

Applying Ohm's law for this segment yields the voltage drop along the incremental segment dy, in the y
direction.
.dR= -
dV= ID.dR= - ID
This equation can now be integrated along the channel, i.e., from y = 0 to y = L, using the boundary
conditions
(y).dVc
.L=W.
=

where the parameters k and k' are defined as

and
For saturation region

.
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Lecture-7
CHANNEL LENGTH MODULATION
 Consider the inversion layer charge Q I that represents the total mobile electron charge on the surface,
given by
QI(y)= - Cox .[ VGS- VC(y)-VT0]
 The inversion layer charge at the source end of the channel is
QI(y=0)= - Cox .[ VGS- VT0]
 and the inversion layer charge at the drain end of the channel is
QI(y=L)= - Cox .[ VGS-VT0- VDS]
 at the edge of saturation, i.e., when the drain-to-source voltage reaches VDSAT
VDS= VDSAT = VGS-VT0
 The inversion layer charge at the drain end becomes zero according to equation, but in reality it
becomes very small.
 Thus, we can state that under the given bias condition, the channel is pinched- off at the drain end, i.e.,
at y = L. The onset of the saturation mode operation in the MOSFET is signified by this pinch-off
event. If the drain-to-source voltage VDS is increased even further beyond the saturation edge so that
VDS> VDSAT, an even larger portion of the channel becomes pinched-off.

 Consequently, the effective channel length (the length of the inversion layer where GCA is still valid)
is reduced to
L` = L - ΔL
 where ΔL is the length of the channel segment with QI = 0
 Hence, the pinch- off point moves from the drain end of the channel toward the source with increasing
drain-to-source voltages. The remaining portion of the channel between the pinch-off point and the
drain will be in depletion mode.
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 SinceQ1(y) =0 for L'< y <L, the channel voltage at the pinch-off point remains equal to VDSAT,i.e.,
VC (y=L`) = VDSAT

 we can represent the inverted portion of the surface by a shortened channel, with a channel-end
voltage of VDSAT. The gradual channel approximation is valid in this region; thus, the channel current
can be found using

 This current equation corresponds to a MOSFET with effective channel length L', operating in
saturation.
 Above current equation accounts for the actual shortening of the channel, also called channel length
modulation.
 We do this by incorporating the incremental channel-length reduction into the original expression:

 we can rearrange this as follows:

 The first term of this saturation current expression accounts for the channel modulation effect
 Channel length shortening ΔL is actually proportional to the square root of (VDS - VDSAT).

 To simplify the analysis even further, we will use the following empirical relation between ΔLand the
drain-to-source voltage instead:

 Here, is an empirical model parameter, and is called the channel length modulation coefficient.
Assuming that VDS<<1, the saturation current can be written as:
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 Current-voltage characteristics of an n-channel MOS transistor, including the channel length

modulation effect.

 The resistance of the channel is proportional to its width-to-length ratio;

 Reducing the length leads to decreased resistance and hence higher current flow.
 Thus, channel-length modulation means that the saturation-region drain current will increase slightly
as the drain-to-source voltage increases.
 So we need to modify the saturation-region drain-current expression to account for channel-length
modulation.
 This modified drain-current expression is a first-order approximation that is reasonably accurate for
FETs with channel length greater than, say, 2 µm.
 As the channel length decreases, so-called “short-channel effects” become more influential, and thus
the above expression (which does not account for short-channel effects) becomes less valid.
 Note also that the above expression incorporates the assumption that ΔL is much less than L; this
assumption becomes less justifiable with shorter channel lengths, and indeed, researchers have
developed a more sophisticated channel-length-modulation model for use with simulations involving
modern short-channel devices.

 The original observation that the current is constant in the saturation region is not quite correct. The
end point of the channel actually moves toward the source as VD increases, increasing ID.

Therefore, the current in the saturation region is a weak function of the drain voltage.
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Substrate Bias Effect:

 In many digital circuit applications, the source potential of an nMOS transistor can be larger than the
substrate potential, which results in a positive source-to-substrate voltage VSB>0.
 For VSB ≠ 0, Threshold Voltage is given as

 replacing the threshold voltage terms in linear-mode and saturation-mode current equations, we get

 Current-voltage equations of the n-channel MOSFET:

Current-voltage equations of the p-channel MOSFET:

Lecture-8
High Frequency Small Signal Equivalent Circuit Model
There are intrinsic or parasitic capacitances related to the MOSFET structure,

Fig: Complete MOS small signal model

Key points:
 Small-signal is small ⇒ response of non-linear components becomes linear
 Can separate response of MOSFET to bias and small signal.
 Since response is linear, superposition can be used
⇒ effects of different small signals are independent from each other
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Low Frequency Small Signal Models:

With VSB=0 
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Transconductance can be increased by

 Increase in Cox i.e. increase in gate oxide thickness
 Increasing width of the device
 Decreasing length of the device
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Output Resistance:
 Since the drain current is a function of the gate source voltage, we incorporate a voltage dependent
current source equal to gmVGS.
 Drain current also varies with the drain source voltage. This effect can be modeled by a voltage
dependent current source. But a current source whose value linearly depends on the voltage across it, is
equivalent to a linear resistor given as

Defined as the inverse of the change in drain current dueto a change in the drain-source voltage, with
everything else constant.

With all other terminals at constant voltage, the draincurrent is a function of the bulk voltage. This can be
modeled by a current source connected between Drain and Source (gmbVBS).

Back-Gate Conductance
One more factor is substrate or body bias on which ID depends. This can be modeled by a voltage
dependent current source equal to gmbVBS in paralle to rDS.

Where
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Lecture-9
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Lecture-10
MOSFET Capacitances
 Study of MOSFET Capacitances are required for transient (AC) analysis of MOSFET related digital
circuits
 Switching speed of a MOS circuit (Dynamic response) depends upon, the parasitic capacitances
together with the Transistor & conductor Resistances.
 simple On-chip MOSFET capacitances are discussed here, which can be used for simple hand
calculations.

N-channel MOSFET Transistor

MOS Device Capacitances

Gate (input) Oxide Capacitances:

Total gate capacitance Cg, of a MOS device is, = Channel Capacitance + Overlap Capacitance
Cg(channel)= Cgs + Cgb + Cgd
Cgs (overlap) = Cox. W. Ld= Cgd (overlap)

Where Cox = ox/tox

No, gate overlap, over Drain and Source region

Simple MOS gate capacitor (assuming as parallel plate capacitor) = C ox. W. L

Behavior of Gate Capacitances: In Terms of 3 Regions of operations

The gate-to-channel capacitance is distributed and voltage-dependent. Then, the Cgs is actually the gate-to-
channel capacitance seen between the G & S terminals; the Cgd is actually the gate-to-channel capacitance
seen between the G & D terminals.

Cutoff Region (Vgs<Vt)

 Surface is not inverted, so no Channel. Hence, Cgs = Cgd = 0
 Only Capacitance between Gate and Substrate exist Cgb = Cox. W. L
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In linear-mode operation, the inverted channel extends across the MOSFET, between the source and the
drain.
The distributed gate-to-channel capacitance may be viewed as being shared equally between the source
and the drain.

Linear Region (Vgs>= VtandVds<=Vgs – Vt )

• Channel is formed between S and D, shielding bulk =>Cgb =0
• Capacitances between Gate - Source (Cgs), Gate - Drain (Cgd) is evenly distributed.
• Hence, Cgs = Cgd = ½ Cox. W. L

Saturation Region (Vgs>= VtandVds<=Vgs – Vt )

• The inversion layer does not extend to the drain and Channel is pinched-off => Hence, Cgd ~ 0;
• Since the source is still linkedto the conducting channel, its shielding effect also forces Cgb ~0
• So Capacitances are mainly due to Gate – Source. Hence Cgs can be approximated by
Cgs = 2/3 Cox. W. L

Behavior of Gate Capacitances: Graphical Representation

Junction/Diffusion Capacitances
• Contributed by the p-n-junctions formed by Source/drain with Substrate (body) and Channel-stop
implant
• Both of these p-n junctions are reversed biased under normal operating conditions of MOSFET
• These Capacitances (Csb&Cdb) depend on terminal voltages

Derivation of Junction Capacitance

Where, ND, NA: doping densities of n & p type

 V: reverse biased –Ve voltage
 Xd: depletion region thickness
 p-n junction is F/B for +ve bias voltage and R/B for –ve bias voltage
 A: junction area
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Side wall junction Capacitance

Lecture-11
MOSFET SCALING AND BIASING

MOSFET Scaling:
Design of high-density chips in VLSI (Very Large Scale Integration) technology requires:-
(a) Packing density of MOSFETs used in the circuits must be high.
(b) Sizes of the transistors are as small as possible.
So, The reduction in size i.e. dimension of MOSFET is called scaling.

The effect of scaling must be studied for certain parameters that affect the performance: -
(1) Minimum feature size
(2) Number of gates on the chip
(3) Power dissipation
(4) Maximum operational frequency
(5) Die size
(6) Production cost
• Many of these factors can be improved by scaling.

Why Scaling
Scaling the device and wires , make the chips “better” – functionality, intelligence, memory, faster and
increases yield.

Implications of Scaling
(1) Improved Performance
(2) Improved Cost
(3) Interconnect Woes
(4) Power Woes
(5) Productivity Challenges
(6) Physical Limits
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Types of MOSFET Scaling

1. Constant field scaling or full scaling :

 Magnitude of internal electric fields is kept constant.
 Only lateral dimensions are changed.
 Threshold voltage is also effected.
2. Constant Voltage Scaling :
 More preferred.
 All dimensions are scaled down except power supply and terminal voltages.
 S>1 has been introduced to describe device scaling

Scaling effect on a typical MOSFET

Scaling by S > 1 leads to the reduction of the area occupied by the transistor by a factor of S2
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Constant field scaling or full scaling

• This scaling preserve the magnitude of internal electric fields in the MOSFET, while the dimensions
are scaled down by a factor of S.

Quantity Before Scaling After Scaling

Channel Length L L’ = L/S

Channel Width W W’ = W/S

Gate Oxide
tox t’ox = tox/s
Thickness

Junction Depth Xj X’j =Xj/s

Power supply
VDD V’DD = VDD/s
voltage

Threshold voltage VTO V’TO = VTO/s

N’A = S.NA
Doping Densities NA, ND
N’D = S.ND
• The linear-mode drain current of the scaled MOSFET

• The Saturation-mode drain current of the scaled MOSFET

Quantity Before Scaling After Scaling

Oxide Capacitance Cox C’ox= S. Cox

Drain Current ID I’D = ID/S

Power Dissipation P P’ = P/S2

Power Density P/Area P’/Area’ = P/Area

 Gate oxide capacitance is scaled down as Cg´ = Cg/S. So, charge-up and charge-down times, of the
scaled device will improve accordingly.
 Overall performance of the device will improve as various parasitic capacitances and resistances will
reduce because of the result of scaled dimensions.

Constant Voltage scaling:

• Here, all dimensions of the MOSFET are reduced by a factor of S, as in full scaling.
• The power supply voltage and the terminal voltages, on the other hand, remain unchanged.
Quantity Before Scaling After Scaling

Channel Length L L’ = L/S

Channel Width W W’ = W/S

Gate Oxide Thickness tox t’ox = tox/s

Junction Depth Xj X’j =Xj/s

Power supply voltage VDD V’DD = VDD

Threshold voltage VTO V’TO = VTO

N’A = S2.NA
Doping Densities NA, ND
N’D = S2.ND
• The linear-mode drain current of the scaled MOSFET

• The Saturation-mode drain current of the scaled MOSFET

Quantity Before Scaling After Scaling

Oxide Capacitance Cox C’ox= S. Cox

Drain Current ID I’D = S. ID

Power Dissipation P P’ = S.P

Power Density P/Area P’/Area’ = S3.(P/Area)

 Increase in drain current density and power density by a factor of S³ adversely effecting device
reliability.
 Causes problems like :
• Electro Migration
• Hot Carrier Degradation
• Gate Oxide Breakdown
• Electrical Over-Stress

Limitation of Scaling:
• Substrate Doping
• Depletion width
• Limits of miniaturization
• Limits of inter connect and contact resistance
• Limits due to subthreshold currents
• Limits on logic levels and supply voltage due to noise
• Limits due to current density

Substrate Doping
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Depletion Width

Limit of miniaturization
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Limit of interconnect and contact resistance:

• Short distance inter-connect- conductor length is scaled by 1/α and the resistance is increases by α.
• For constant field scaling, I is scaled by 1/α so that IR drop remains constant as a result of scaling,
- driving capability/ noise margin.

Limit due to subthreshold current

• Major concern in scaling devices.
• Isub is directly proportional to exp(Vgs - Vt) q/ KT
• As voltage will scaled down, ratio of (Vgs - Vt) to KT will reduce – so that threshold current
increases.
• Therefore, scaling Vgs and Vt together with Vdd.
• Maximum electric field across a depletion region is
Emax = 2{Va+Vb}/d

Limit on supply voltage due to noise:

• Decreased inter-feature spacing and greater switching speed – results in noise problem.

Which Type of Scaling Behaves Best?

Constant Voltage Scaling
 Here, the power supply and signal voltage are unchanged
 But, IDS => S IDS& W => W/S and xj =>xj/S for the source and drain (same for metal width and
thickness).
 So JD => S3JD, increasing current density by S3.
 Causes metal migration and self-heating in interconnects.
 Since Vdd =>Vdd and IDS => S IDS, the power P => SP. The area A => A/S2.
 The power density per unit area increases by factor S3.
 Cause localized heating and heat dissipation problems.
 Electric field increases by factor S. Can cause failures such as oxide breakdown, punch-through,
and hot electron charging of the oxide.
 With all of these problems, why not use full scaling reducing voltages as well?
 Done – Over last several years, departure from 5.0 V: 3.3, 2.5, 1.5 V

 Does Scaling Really Work?

 Not totally as dimension become small.
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Comparative MOS Scaling

Quantity Sensitivity Constant Field Constant Voltage

Scaling Parameters
Length L 1/S 1/S
Width W 1/S 1/S
Gate Oxide Thickness tox 1/S 1/S
Supply Voltage Vdd 1/S 1
Threshold Voltage VT0 1/S 1
Doping Density NA, ND S S2
Device Characteristics
Area (A) WL 1/S2 1/S2

 W/Ltox S S
D-S Current (IDS) (Vdd - vT)2 1/S S
Gate Capacitance (Cg) WL/tox 1/S 1/S
Transistor On-Resistance (Rtr) Vdd/IDS 1 1/S
Intrinsic Gate Delay () RtrCg 1/S 1/S2
Clock Frequency f=1/ S S2
Power Dissipation (P) IDSVdd 1/S2 S
Power Dissipation Density (P/A) P/A 1 S3
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Lecture-12

High Order Effects

• Short Channel
• Narrow Channel
• Sub threshold Conduction
• Punch Through
• Hot Electron

SHORT CHANNEL EFFECTS:

 A MOS transistor is called a short-channel device if its channel length is on the same order of
magnitude as the depletion region thicknesses of the source and drain junctions.
 Alternatively a MOSFET can be defined as a short-channel device if the effective channel length Leff
is approximately equal to the source and drain junction depth xj.
 The short-channel effects that arise in this case are attributed to two physical phenomena:
(i) the limitations imposed on electron drift characteristics in the channel,
(ii) the modification of the threshold voltage due to the shortening channel length.
 The lateral electric field EYalong the channel increases, as the effective channel length is decreased.
 While the electron drift velocity Vd in the channel is proportional to the electric field for lower field
values, this drift velocity tends to saturate at high channel electric fields.
 For channel electric fields of E = 10 V/cm and higher, the electron drift velocity in the channel
reaches a saturation value of about vd(sat) = 10^7 cm/s.
 The effective channel length Leffwill be reduced due to channel-length shortening

 Since the channel-end voltage is equal to VDSAT, the saturation current can be found as follows:

The dependence of the surface electron mobility on the vertical electric field can be expressed by the
following empirical formula:
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NARROW-CHANNEL EFFECTS
 MOS transistors having channel widths W on the same order of magnitude as the maximum depletion
region thickness xdm are defined as narrow-channel devices.
 the transistors start behaving differently, which impacts performance, modeling and reliability.
 Narrow-channel MOSFETs exhibit typical characteristics which are not accounted for GCA analysis.
 Due to this effect, actual threshold voltage of such a device is largerthan that predicted by the
conventional threshold voltage formula.
 A typical cross-sectional view of a narrow-channel device is shown here:

 The oxide thickness in the channel region is tox, while the regions around the channel are covered by a
thick field oxide (FOX).
 Gate electrode overlaps with the field oxide.
 A shallow depletion region formed underneath this FOX-overlap area as well.
 Consequently, the gate voltage must also support this additional depletion charge in order to establish
the conducting channel.
 The charge contribution of this fringe depletion region to the overall channel depletion charge is
negligible in wider devices.
 For MOSFETs with small channel widths, however, the actual threshold voltage increases as a result
of this extra depletion charge. V T 0  V T 0   V T 0
 The additional contribution to the threshold voltage due to narrow-channel effects can be modeled as
follows:
1  x dm
 VT 0  . 2 q  Si N A
2 F .
C ox W


 
2

Where  is an empirical parameter depending on the shape of the fringe depletion region.
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 The amount of threshold voltage increase becomes significant only for devices which have a channel
width W on the same order of magnitude as xdm.
 For minimum-geometry MOSFETs which have a small channel length anda small channel width, the
threshold voltage variations due to short- and narrow-channel effects may tend to cancel each other
out.
 The simple one-dimensional gradual channel approximation (GCA) assumes that the electric field
components parallel to the surface and perpendicular to the surface are effectively decoupled and
cannot fully account for some of the observed device characteristics.
 These small-geometry device characteristics may severely restrict the operating conditions of the
transistor and impose limitations upon the practical utility of the device.

SUB-THRESHOLD CONDUCTION:
 Accurate identification and characterization of these small-geometry effects are crucial, especially for
submicron MOSFETs.
 One typical condition, which is due to the two-dimensional nature of channel current flow, is the sub
threshold conduction in small-geometry MOS transistors.
 Current flow in the channel depends on creating and sustaining an inversion layer on the surface.
 If the gate bias voltage is not sufficient to invert the surface, i.e. VGS<V, the carriers (electrons) in the
channel face a potential barrier that blocks the flow.
 Increasing the gate voltage reduces this potential barrier allowing the flow of carriers under the
influence of the channel electric field. This simple picture becomes more complicated in small-
geometry MOSFETs, because the potential barrier is controlled by both the gate-to-source voltage VGS
and the drain-to-source voltage VDS.
 If the drain voltage is increased, the potential barrier in the channel decreases, leading to drain-induced
barrier lowering (DIBL).
 The reduction of the potential barrier eventually allows electron flow between the source and the
drain, even if the gate-to-source voltage is lower than the threshold voltage.
 The channel current that flows under these conditions (VGS< VT0)is called the sub threshold current.
 GCA cannot account for any nonzero drain current ID for VGS< VT0. Two-dimensional analysis of the
small-geometry MOSFET yields the following approximate expression for the sub threshold current.
qT q
qD n Wx c n 0 ( A .V GS  B .V DS )
I D ( subthresho ld )  .e kT
.e kT
Ln

where, xCis the sub threshold channel depth

Dnis the electron diffusion coefficient
LBis the length of the barrier region in the channel
ɸr is a reference potential.
 Note the exponential dependence of the sub threshold current on both gate and the drain voltages.
 Identifying sub threshold conduction is very important for circuit applications where small amounts of
current flow may significantly disturb the circuit operation
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PUNCH THROUGH EFFECT:

 In small-geometry MOSFETs, the channel length is on the same order of magnitude as the source and
drain depletion region thicknesses.
 For large drain-bias voltages, the depletion region surrounding the drain can extend farther toward the
source, and the two depletion regions can eventually merge. This condition is termed punch-through.
 In punch through effect, the gate voltage loses its control upon the drain current, and the current rises
sharply once punch-through occurs.
 Being able to cause permanent damage to the transistor by localized melting of material, punch-
through is obviously an undesirable condition, and should be prevented in normal circuit operation.
 As some device dimensions, such as the channel length, are scaled down with each new generation,
some dimensions cannot be arbitrarily scaled because of physical limitations.
 One such dimension is the gate oxide thickness tox.
 The reduction of toxby a scaling factor of S, i.e., building a MOSFET with tox' = tox / S, is restricted by
processing difficulties involved in growing very thin, uniform silicon- dioxide layers.
 Localized sites(pinholes) of non uniform oxide growth may cause electrical shorts between the gate
electrode and the substrate.
 Another limitation on the scaling of toxis the possibility of oxide breakdown.
 If the oxide electric field perpendicular to the surface is larger than a certain breakdown field, the
silicon-dioxide layer may sustain permanent damage during operation, leading to device failure.

HOT ELECTRON EFFECT

 Advances in VLSI fabrication technologies are
primarily based on the reduction of device dimensions, such as the channel length, the junction depth,
and the gate oxide thickness, without proportional scaling of the power supply voltage (constant-
voltage scaling).
 This decrease in critical device dimensions to submicron ranges, accompanied by increasing substrate
doping densities, results in a significant increase of the horizontal and vertical electric fields in the
channel region.
 Hot electron effect is observed in short channel MOSFET due to presence of high lateral and
transverse electric field.
 High electric fields result in high kinetic energy of electrons and some electrons may get enough
energy to overcome the barrier between the body and the gate.
 This leads to deposition of negative charge on the gate (some electron may trap in oxide) which leads
to an increase in threshold voltage by increasing flat band voltage.
 It may cause permanent changes in the oxide interface charge distribution.
 It results in degradation in the current-voltage characteristics of the MOSFET.
 This effect is more pronounced at large drain-to-source voltages, at which the lateral electric field at
the drain end of the channel accelerates the electrons.
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 Channel hot-electron current and the subsequent damage in the gate oxide are localized near the drain
junction.
 The damage caused by hot-carrier injection affects transistor characteristics by causing a degradation
in trans-conductance, a shift in the threshold voltage, and a general decrease in the drain current
capability.

Figure: Typical drain current vs. drain voltage characteristics of an n-channel MOS transistor
before and after hot-carrier induced oxide damage.

 This performance degradation in the devices leads to the degradation of circuit performance over time.
Hence, new MOSFET technologies based on smaller device dimensions must carefully account for the
hot-carrier effects and also ensure reliable long-term operation of the devices.

 Since the likelihood of hot-carrier induced degradation increases with shrinking device dimensions,
this problem was identified as one of the important factors that may impose strict limitations on
maximum achievable device densities in VLSI circuits.
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Lecture-13

NUMERICAL PROBLEMS:
Example 1: For the n – channel MOS transistor shown in figure, the threshold voltage VTH is 0.8V.
Neglect channel length modulation effects. When the drain voltage VD = 1.6, the drain current ID was
found to be 0.5 mA. If VD is adjusted to be 2V by changing the values of R and VDD, what will be the new
value of ID.

Solution:

Given, = . , = . , = .
For the given figure we notice that Gate is connected to drain
So, = =
In saturation ID is given by
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Example 2:For the MOSFET M1 shown in figure, assume ⁄ = 2, = 2.0 , = 100 ⁄ 2

=
0.5 . For what value of , The transistor M1 switches from saturation region to linear region.

Solution:
For saturation region drain current is given by

From equation (1) and (2) we get

Example 3:Consider the MOS structure that consists of a p-type doped silicon substrate, a SiO2 layer, and
a metal (aluminum) gate. The equilibrium Fermi potential of the doped silicon substrate is given as
qΦFp=0.2 eV. Calculate the built-in potential difference across the MOS system. Assume that the MOS
system contains no other charges in the oxide or on the silicon-oxide interface.
Given:
electron affinity for silicon: 4.15eV
work function for aluminum: 4.1eV

Solution:
First, calculate the work function for the doped silicon, using equation
qΦs=qχ + (EC-EF)
electron affinity for silicon: 4.15eV
and (EC-EF) = Ei+ qΦFP =0.55+0.2 eV =0.75eV
So, qΦs= 4.15eV+0.75eV = 4.95eV
The built-in potential difference across this MOS system is
qΦM – qΦs = 4.1eV – 4.9eV = -0.8eV
If a voltage corresponding to this potential difference is applied externally between the gate and the
substrate, the bending of the energy bands near the surface can be compensated, i.e., the energy bands
become "flat." Thus, the voltage defined by VFB= ΦM – Φs, is called the flat band voltage.

Example 4: A depletion type N – channel MOSFET in biased in its linear region for use as a voltage
controlled resistor . Assume threshold voltage = 0.5 , = 2.0 , = 5 , ⁄ = 100, = 10-
8
/ 2 and = 800 ⁄2 - . Find the value of the resistance of the voltage controlled resistor ( Ω).

Solution:
Given, Depletion type MOSFET (N – Channel) In linear region = . , = . , = ,
/ = , = - ⁄
The value of voltage controlled resistor is given by
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Lecture-14
Example 5: Calculate the threshold voltage VTO at VB= 0, for a polysilicon gate n-channel MOS
transistor, with the following parameters:
substrate doping density NA = 1016 cm-3,
polysilicon gate doping density ND= 2 x 1020 cm-3,
gate oxide thickness tox = 500 Å, and
oxide-interface fixed charge density Nox = 4 x 1010 cm-2.

Solution:
First, calculate the Fermi potentials for the p-type substrate and for the n-type
polysilicon gate:

Since the doping density of the polysilicon gate is very high, we may assume that the Fermi potential of
the polysilicon gate is approximately equal to the conduction band potential, i.e., ΦF (gate) =0.55 V.

Now, calculate the work function difference between the gate and the channel:

ΦGC = ΦF (substrate) - ΦF (gate) = -0.35V – 0.55V =-0.90V

The depletion region charge density at VSB= 0 is found as follows:

The oxide-interface charge is:

The gate oxide capacitance per unit area is calculated using the dielectric constant of silicon dioxide and
the oxide thickness tox.

Now, combining all components of the threshold voltage,

Example 6: For the nMOS transistors, = 100 / 2 and the threshold voltage VT = 1 V. For the
circuit shown in figure, what is the voltage VX at the source of the upper transistor.

Solution:
The two MOSFET are in series so, same current will be flowing.

For MOSFET M1
VG1> T, and VDS1> VGS1 - T  MOSFET M1 is operating in saturation region
Drain current for M1 is

1= 1 ( 1− )

Similarly for MOSFET M2

= D  MOSFET M2 is operating in saturation region
Therefore, Drain current 2 = 2 ( 2 − )

Since 1 = 2

Thus,

1 = - X =5– X and 2 = X
– VX
( – VX
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Example 7: When the gate to source voltage (VGS) of a MOSFET with threshold voltage of 400 mV,
working in saturation is 900 mV, the drain current is observed to be 1 mA. Neglecting the channel length
modulation effect and assuming that the MOSFET is operating in saturation mode, what will be the drain
current for an applied VGS of 1400 mV.

Solution:

Given, = = .
 When applied gate voltage = =0.9 V,

Drain current for =

MOSFET is operating in saturation

= ( − )
−
, × = ( . − . )
−
, = /( . ) = × − /

 For VGS = 1.4 V

−
= ( − ) = × ( . − . )2 = 4mA

Example 8: For Enhancement type N – channel MOSFET following parameters are given:
threshold voltage 0= 1 , K = 110 A/V2, =3.0 , D =5.0 Find the drain current and
transconductance for the device.

Solution:
Since VGS> VT0 and VDS> VGS - VT0

Device is operating in saturation region

= 200 A

= 200 A/V
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Lecture-15

UNIT-V
Electronic Design Automation
 Also referred as electronic computer-aided design (ECAD)
 It is category of Software tools
 Used for designing electronic systems such as integrated circuits and printed circuit boards.
 consists of a design flow to design and analyze the electronic circuit.
 these tools are used for synthesis, implementation and simulation of Electronic circuits on the
software itself.
 ECAD tools are used for generating physical representation of integrated circuit form high level
description.
 It mainly concerned with the design of integrated circuit in terms of behavioral descriptions,
netlists, schematics and layout.
 It can model the integrated circuit as a whole or as a set of functional blocks.

Design Flow
 EDA tools generally follow a flow.
 The design flow can be divided into two designs: Digital Design and Analog Design
 In Digital design: circuit is described using a hardware description language, followed by
simulation of circuit design, synthesis, place & route and post layout simulation.
 In Analog design: circuit is captured, followed by simulation, physical design, layout extraction
and post layout simulation.
The combined layouts of digital and analog designs are used in a manufacturing facility to produce an
electronic chip.

Advantages of EDA Tools

 Minimizing time in designing complex ICs
 Eliminating manufacturing errors
 Reducing manufacturing costs
 Optimizing the IC design
 Simplicity of usage
Disadvantages of EDA Tools
 Expensive
 Many of the tools are not easy to install
 Many of the tools are not user friendly enough to learn
 There are not many experts available to teach the EDA tools.
 System to Silicon Design
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System to Silicon Design

VLSI Design Flow

 Specification: This is the first stage in the design process where we define the important parameters
of the system that has to be designed into a specification.
 High level Design: In this stage, various details of the design architecture are defined. The different
functional blocks and the interface communication protocols between them etc. are also defined.
 Low level Design: This phase is also known as microarchitecture phase. In this phase lower level
design details about each functional block implementation are designed. This can include details like
modules, state machines, counters, MUXes, decoders, internal registers etc.
 RTL coding: In RTL coding phase, the micro design is modelled in a Hardware Description
Language like Verilog/VHDL, using synthesizable constructs of the language. Synthesizable
constructs are used so that the RTL model can be input to a synthesis tool to map the design to actual
gate level implementation later.
 Functional Verification: Functional Verification is the process of verifying the functional
characteristics of the design by generating different input stimulus and checking for correct behavior
of the design implementation.
 Logic Synthesis: Synthesis is the process in which a synthesis tool like design compiler takes in the
RTL, target technology, and constraints as inputs and maps the RTL to target technology primitives.
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 Placement and Routing: Gate-level netlist from the synthesis tool is taken and imported into place
and route tool in the Verilog netlist format. All the gates and flip-flops are placed, Clock tree
synthesis and reset is routed. After this each block is routed, output of the P&R tool is a GDS file,
which is used by a foundry for fabricating the ASIC
 Gate level Simulation: The Placement and Routing tool generates an SDF (Standard Delay File)
that contains timing information of the gates. This is back annotated along with gate level netlist and
some functional patterns are run to verify the design functionality. A static timing analysis tool like
Prime time can also be used for performing static timing analysis checks
 Post silicon Validation: Once the chip is back from fabrication, it needs to be put in a real test
environment and tested before it can be used widely in the market. This phase involves testing in lab
using real hardware boards and software/firmware that programs the chip. Since the speed of
simulation with RTL is very slow compared to testing in lab with real silicon, there is always a
possibility to find a bug in silicon validation and hence this is very important before qualifying the
design for a market.
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Lecture-16

VLSI Design Flow

Classification of VLSI design flow

 The VLSI design flow can be divided into two parts: Frontend design flow and Backend design
flow.

Both together, allow the creation of a functional chip from scratch to production.

Y-Chart for Domains and levels of VLSI Design

• The design representation space consists of domains and levels

• Behavioral domain most abstract
• Structural domain specifies the architecture
• Physical domain include the transistors and layout

VLSI Design Flow: Front end and Back end

VLSI Design Cycle

System Specification:
Specification of the size, speed, power and functionality of the VLSI Design.

Architectural Design:
Decision on the Architecture eg. RISC/CISC, # of ALU’s pipeline structure, cache size, etc. Such decision
can provide an accurate estimation of the system performance, die size, power consumption etc.

Functional Design:
Identity main functional units and their interconnections. No details of implementation.
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Logic Design:
Design the logic e.g. boolean expression, control flow, word width, register allocation etc. The outcome is
called RTL description. RTL is expressed in a HDL e.g. VHDL and Verilog.
X= (AB+CD) (E+F) Y=(A(B+C)+Z+D)

Circuit Design:
Design the circuit including gates, transistors, interconnections etc. The outcome is called a netlist.
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Physical Design:
Convert the netlist into a geometric representation.. The outcome is called a layout.

Fabrication: Process includes lithography, polishing, deposition, diffusion etc. to produce a chip.
Packaging: Put together the chips on a PCB (Printed Circuit Board) or an MCM (Multi-Chip Module)
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Front end Design Flow

 The frontend flow is responsible to determine a solution for a given problem
 opportunity and transform it into a RTL circuit description.
The stages of the frontend flow are identified in figure .

Front End Design

 It starts from system-level description and verification, like extracting the architecture from an IEEE
standard and modeling the system using C/C++/SystemC or Matlab.
 Then the output of the modeling and verification, which is the test vectors, is passed to RTL team to
design the hardware using any common HDL language like VHDL or Verilog. This designed
hardware has be simulated using an HDL simulator like Mentor Graphics' Modelsim (commonly
used) .. or any other RTL simulator/wave viewer from Cadence or Synopsis.
 After the design is verified on the RTL level, it goes for Synthesis and Netlist generation. Most of the
time, people use Design Compiler (by Synopsis) and some others use Leonardo (By Mentor)..
Simply, u get the netlist out of this process (without more details), then pass it to the backend.

Back end Design Flow

 The Backend process is responsible for the physical implementation of a circuit.
 It transforms the RTL circuit description into a physical design, composed by gates and its
interconnections.
 The main phases of the backend process are Synthesis and Place&Route.
 Figure represents the flow of the backend process. Each step is done by running TcL (Tool
Command Language) scripts that execute commands on the corresponding Synopsys tool.
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Back End

 Back end encompasses

 static timing analysis
 Floor-planning,
 clock tree synthesis,
 layout,
 signal integrity issues
 formal verification etc.
Simulators may be used for post layout simulation.
The vendors providing tools are:
 Synopsys
 Cadence
 Tanner
 Mentor Graphics etc.

EDA Tools
Design flow regardless of technology is a fully automated process.Followings are the most common tools
available in the market that are briefly explained here:
1. Design Capture Tools
Design entry tool encapsulates a circuit description. These tools capture a design and prepare it for
simulation. Design requirements dictate type of the design capture tool as well as the options needed.
Some of the options would be:
 Manual netlist entry
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 Schematic capture
 Hardware Description Language (HDL) capture (VHDL, Verilog, ...)
 State diagram entry
2. Simulation and Verification Tools
Functional verification tool confirms that the functionality of a model of a circuit conforms to the intended
or specified behavior, by simulation or by formal verification methods.
 There are two major tool sets for simulation: Functional (Logic) simulation tools and Timing
simulation tools.
 Functional simulators verify the logical behavior of a design based on design entry.
 Timing simulators on the other hand perform timing verifications at multiple stages of the design.
In this simulation the real behavior of the system is verified when encountering the circuit delays
and circuit elements in actual device.
3. Layout Tools
 ASIC designers usually use these tools. Designers transform a logic representation of an ASIC into
a physical representation that allows the ASIC to be manufactured.
 The transistor layout tools take a cell level ASIC representation and for a given technology create
a set of layers representing transistors for each cell.
 Physical design tool works in conjunction with floorplanning tools that show where various cells
should go on the ASIC die.
4. Synthesis and Optimization Tools
 Synthesis tools translate abstract descriptions of functionality such as HDL into optimal physical
realizations, creating netlists that can be passed to a place and route tool.
 Then, the designer maps the gate level description or netlist to the target design library and
optimizes for speed, area or power consumption.

Tools used for FPGA/CPLD

 Xilinx
ISE- Synthesis
ISim simulator- Simulation
 Mentor – Graphics
Leonardo Spectrum- Synthesis
ModelSim- Simulation

Tools used for ASIC

 Cadence
 Synopsys
 Mentor Graphics

Tools used for Analog Design Flow

 Cadence
 Synopsys
Virtuoso
 Mentor Graphics
 Tanner
 HSpice
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Lecture-17

ASIC
ASIC [“a-sick”] is an acronym for Application Specific Integrated Circuit.
 As the name indicates, ASIC is a non-standard integrated circuit that is designed for a specific use or
application.
 Generally an ASIC design will be undertaken for a product that will have a large production run, and
the ASIC may contain a very large part of the electronics needed on a single integrated circuit.
 Examples for ASIC are : a chip for a toy bear that talks; a chip for a satellite; a chip designed to handle
the interface between memory and a microprocessor for a workstation CPU; and a chip containing a
microprocessor as a cell together with other logic.

Two ICs that might or might not be considered as ASICs are, a controller chip for a PC and a chip for a
modem.
Both of these examples are specific to an application (shades of an ASIC) but are sold to many different
system vendors (shades of a standard part).

ASICs such as these are sometimes called application-specific standard products (ASSPs).

Concept Map
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Integrated Circuit
 Wafer :A circular piece of pure silicon
 Wafer Lot:5 ~ 30 wafers, each containing hundreds of chips(dies) depending upon size of the die
 Die: A rectangular piece of silicon that contains one IC design
 Mask Layers: Each IC is manufactured with successive mask layers(10 –15 layers)
 First half-dozen or so layers define transistors
 Other half-dozen define Interconnect

Integrated Circuit (IC) in a package

(a)A pin-grid array (PGA) package.

(b) The silicon die or chip is under the package lid.

Types of ASIC
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Full-Custom ASICs
 All mask layers are customized in a full-custom ASIC
 Generally, the designer lays out all cells by hand
 Some automatic placement and routing may be done
 Critical (timing) paths are usually laid out completely by hand
 Full-custom design offers the highest performance and lowest part cost (smallest die size) for a given
design
 The disadvantages of full-custom design include increased design time, complexity, design expense,
and highest risk
 Microprocessors (strategic silicon) were exclusively full-custom, but designers are increasingly
turning to semicustom ASIC techniques in this area as well
 Other examples of full-custom ICs or ASICs are requirements for high-voltage (automobile),
analog/digital (communications), sensors and actuators, and memory (DRAM).

Semicustom ASICs
 ASICs for which all of the logic cells are predesigned and some (possibly all) of the mask layers are
customized are called semi-custom ASICs.
 Using the predesigned cells from a cell library makes the design, much easier.

There are two types of semicustom ASICs

(i) Standard-cell–based ASICs
(ii) Gate-array–based ASICs

(i) Standard-Cell Based ASICs

 The standard-cell areas (also called flexible blocks) in a CBIC are built of rows of standard cells
like a wall built of bricks.
 The standard-cell areas may be used in combination with microcontrollers or even microprocessors,
known as mega cells.
 Mega cells are also called mega functions, full-custom blocks, system-level macros (SLMs), fixed
blocks, cores, or Functional Standard Blocks (FSBs).
 A cell-based ASIC (CBIC) die with a single standard-cell area (a flexible block) together with four
fixed blocks.
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(ii) Gate-Array Based ASICs

 In a gate-array-based ASIC, the transistors are predefined on the silicon wafer
 The predefined pattern of transistors is called the base array
 The smallest element that is replicated to make the base array is called the base or primitive cell.
 The top level interconnect between the transistors is defined by the designer in custom masks -
Masked Gate Array (MGA)
 Design is performed by connecting predesigned and characterized logic cells from a library
(macros)
 After validation, automatic placement and routing are typically used to convert the macro-based
design into a layout on the ASIC using primitive cells

Types of MGAs:
(i) Channeled Gate Array
(ii) Channelless Gate Array
(iii) Structured Gate Array

 The predefined pattern of transistors on a gate array is the base array, and the smallest element that is
replicated to make the base array is the base cell (sometimes called a primitive cell ).
 Only the top few layers of metal, which define the interconnect between transistors, are defined by the
designer using custom masks. To distinguish this type of gate array from other types of gate array, it is
often called a masked gate array (MGA).
 The designer chooses from a gate-array library of predesigned and pre-characterized logic cells
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Channeled Gate Array

 Only the interconnect is customized

 The interconnect uses predefined spaces between rows of base cells
 Manufacturing lead time is between two days and two weeks

Channel less Gate Array

 Only the interconnect is customized.

 The interconnect uses predefined spaces between rows of base cells.
 Manufacturing lead time is around two days to two weeks.
 When we use an area of transistors for routing in a channel less array, we do not make any contacts
to the devices lying underneath, we simply leave the transistors unused. Achievable logic density
is higher than for channeled gate arrays.
 Manufacturing lead time is between two days and two weeks.
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Structured Gate Array

 A structured or embedded gate-array die showing an embedded block in the upper left corner
 Only the interconnect is customized
 Custom blocks (the same for each design) can be embedded
o These can be complete blocks such as a processor or memory array, or
o An array of different base cells better suited to implementing a specific function
 Manufacturing lead time is between two days and two weeks.

 Custom Blocks (same for each design can be embedded)

 Manufacturing lead time is between two days and two weeks.
 An embedded gate array gives the improved area efficiency and increased performance of a CBIC
but with the lower cost and faster turn around of an MGA.
 The disadvantage of an embedded gate array is that the embedded function is fixed.
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Programmable Logic Devices

 Programmable logic devices (PLDs) are standard ICs that are available in standard configurations.
 However, PLDs may be configured or programmed to create a part customized to a specific
application, and so they also belong to the family of ASICs.
 PLDs use different technologies to allow programming of the device.

Features of PLDs

 No customized mask layers or logic cells

 Fast design turnaround
 A single large block of programmable interconnect
 A matrix of logic macro cells that usually consist of programmable array logic followed by a flip-
flop or latch
 The simplest type of programmable IC is a read-only memory(ROM ). The most common types of
ROM use a metal fuse that can be blown permanently (a programmable ROM or PROM ).
 An electrically programmable ROM , or EPROM , uses programmable MOS transistors whose
characteristics are altered by applying a high voltage.
 One can erase an EPROM either by using another high voltage (an electrically erasable PROM , or
EEPROM ) or by exposing the device to ultraviolet light (UV-erasable PROM,or UVPROM).
 There is another type of ROM that can be placed on any ASIC a mask-programmable ROM
(mask-programmed ROM or masked ROM). A masked ROM is a regular array of transistors
permanently programmed using custom mask patterns.
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COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLDs)

 PLAs and PALs are useful for implementing a wide variety of small digital circuits.
 Each device can be used to implement circuits that do not require more than the number of inputs,
product terms, and outputs that are provided in the particular chip.
 These chips are limited to fairly modest sizes, typically supporting a combined number of inputs
plus outputs of not more than 32.
 For implementation of circuits that require more input sand outputs, either multiple PLAs or PALs
can be employed or else a more sophisticated type of chip, called a complex programmable logic
device (CPLD), can be used.
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Field-Programmable Gate Arrays(FPGAs)

 A field programmable gate array (FPGA) is a semiconductor device that can be configured by the
customer or designer after manufacturing - hence the name “field-programmable”.
 FPGAs are quite different from SPLDs and CPLDs because FPGAs do not contain AND or OR
planes.
 FPGAs provide logic blocks for implementation of the required functions.

Essential characteristics of FPGA

 Core-regular array of Programmable basic logic cells implement combinational or sequential logic
 Matrix of programmable interconnects surround the basic logic cells
 Programmable I/O cells surround the core
 A method of programming the basic logic cells and interconnect
 None of the mask layers are customized
 Design turnaround is few hours.

Comparison
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Major Activities in ASIC Design

ASIC Design Flow

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Lecture-18
Hardware Description Languages
 Due to the exploding complexity of digital electronic circuits since the 1970s (see Moore's law),
circuit designers needed digital logic descriptions to be performed at a high level without being
tied to a specific electronic technology, such as ECL, TTL or CMOS
 HDLs were created to implement register-transfer level abstraction, a model of the data flow
and timing of a circuit
 HDLs are specialized languages used to describe the structure and behavior of electronic circuits,
and most commonly, digital logic circuits.
 HDLs enable a precise, formal description of an electronic circuit that allows for the automated
analysis and simulation of an electronic circuit.
 It also allows for the synthesis of an HDL description into a netlist (a specification of physical
electronic components and how they are connected together), which can then be placed and
routed to produce the set of masks used to create an integrated circuit.
 HDLs form an integral part of electronic design automation (EDA) systems, especially for
complex circuits, such as application specific integrated circuits, microprocessors,
and programmable logic devices.
 One important difference between most programming languages and HDLs is that HDLs explicitly
include the notion of time.
 There are two major hardware description languages: VHDL and Verilog.

Importance of HDL:
 In software language everything is sequential. Sequence of statements is important, since they are
executed in order
 In hardware events are concurrent, so a software language cannot be used for describing and
simulating hardware accurately.

Advantages of using HDL Languages:

 Designs can be described at various levels of abstractions
 Top-Down Approach and hierarchical designs for large projects
 Automatic Conversion of HDL Code to Gate net list
 Early Testing of Various Design Implementations
 Due to fast synthesis, there is a scope for trying different implementations.
 Design Reusability
 Technology independence, standardization, portability, ease of maintenance.
 All this results in low risk, high convergence, fast time to market, more money.
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VHDL
What is VHDL?
V H I S C  Very High Speed Integrated Circuit
Hardware
Description
Language

History of VHDL
 In the mid 1980’s the U.S. Department of Defense and the IEEE sponsored the development of this
HDL with the goal to develop very high speed Integrated Circuits.
 The initial version of VHDL, designed to standard IEEE 1076-1987, included a wide range of data
types, including numerical (integer and real), logical (bit and boolean), character and time,
arrays of bit called bit_vector and arrays of character called string.
 Enhanced version of the language defined in 1993: IEEE 1076-1993
 Additional standardized packages provide definitions of data types and expressions of timing data
o IEEE 1164 (data types)
o IEEE 1076.3 (numeric)
o IEEE 1076.4 (timing)

BASIC FEATURES OF VHDL

 CONCURRENCY.
 SUPPORTS SEQUENTIAL STATEMENTS.
 SUPPORTS FOR TEST & SIMULATION.
 STRONGLY TYPED LANGUAGE.
 SUPPORTS HIERARCHIES.
 SUPPORTS FOR VENDOR DEFINED LIBRARIES.
 SUPPORTS MULTIVALUED LOGIC.

CONCURRENCY
 VHDL is a concurrent language.
 HDL differs with Software languages with respect to Concurrency only.
 VHDL executes statements at the same time in parallel, as in Hardware.

SUPPORTS SEQUENTIAL STATEMENTS

 VHDL supports sequential statements also, it executes one statement at a time in sequence only as
the case with any conventional language.
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 example:
if a=‘1’ then
y<=‘0’;
else
y<=‘1’;
end if ;

SUPPORTS FOR TEST & SIMULATION.

 To ensure that design is correct as per the specifications, the designer has to write another
program known as “TEST BENCH”.
 It generates a set of test vectors and sends them to the design under test(DUT).
 Also gives the responses made by the DUT against a specifications for correct results to ensure
the functionality.

STRONGLY TYPED LANGUAGE

 one has always to declare the type of every object that can have a value, such as signals, constants
and variables.
 VHDL allows LHS & RHS operators of same type.
 example:
A : in std_logic_vector(3 downto 0);
B : out std_logic_vector(3 downto 0);
C : in bit_vector(3 downto 0);

B <= A; --perfect
B <= C; --type mismatch, syntax error

SUPPORTS HIRERCHIES
 Hierarchy can be represented using VHDL.
 Consider example of a Full-adder which is the top-level module, being composed of three lower
level modules i.e. Half-Adder and OR gate.
example :
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Basic Structure of a VHDL File

VHDL is a hardware description language that can be used to model a digital system. A digital system is
usually designed as a hierarchical collection modules. Each module corresponds to a design entity in
VHDL. Each design entity is modeled using an entity declaration and at least one architecture body

An entity declaration describes a component’s external interface (input and output ports etc.), whereas
architecture bodies describe its internal implementations (functionality).

Packages define global information that can be used by several entities.

A configuration binds component instances of a structure design into entity architecture pairs. It allows a
designer to experiment with different variations of a design by selecting different implementations.
A VHDL design consists of several library units, each of which is compiled and saved in a design
library.

Entity Declaration
The entity declaration provides an external view of a component but does not provide information about
how a component is implemented.
The syntax is ;
entity entity_nameis
[generic(generic_declarations);]
[port (port_declarations);]
{entity_declarative_item{constants, types, signals};}
end [entity_name];
**Entity port is a signal with a specified data flow direction which provides an interconnection between
the component and its environment.
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Mode:
It indicate the signal direction
 in – can only be read. It is used for input only (can be only on the right side of the assignment)
 out – can only be assigned a value. It is used for output only (can be only on the left side of the
assignment).
 inout – can be read and assigned a value. It can have more than one driver (can be both on the right
and left side of the assignment)
 buffer – indicates that the signal is an output of the entity whose value can be read inside the
entity’s architecture. It can have only one driver. Its an out port with read capability. It is not a bi-
directional port. (can be both on the right and left side of the assignment ).

Example:
entity xxx is
port (A : in integer ;
B : in integer ;
C : out integer ;
D : inout integer ;
E : buffer integer)
end xxx ;
architecture bhv of xxx is
begin
process(A, B)
Begin
C <= A ; -- valid : A is assigned to C
A <= B ; -- not valid : A is an input port so cannot be assigned a value, A is on the left
side)
E <= D+1; -- valid : D is inout, so it can be both assigned and read
D <= C+1; -- not valid : C is out port, so cannot be read for input, C is on the right side
end process ;
end bhv ;
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Type:
A built-in or user-defined signal type.

Examples of types are bit, bit_vector, Boolean, character, std_logic, and std_ulogic.
 bit – can have the value 0 and 1
 bit_vector – is a vector of bit values (e.g. bit_vector (0 to 7)
 std_logic, std_ulogic, std_logic_vector, std_ulogic_vector: can have 9 values to indicate the value
and strength of a signal. Std_ulogic and std_logicare preferred over the bit or bit_vector types.
 boolean – can have the value TRUE and FALSE
 integer – can have a range of integer values
 real – can have a range of real values
 character – any printing character
 time – to indicate time

GENERICS
 The generic_declarationdeclares constants that can be used to control the structure and timing of
an entity.

 syntax for a generic

generic (
constant_name : type [:=init_value]
{;constant_name : type [:=init_value]}
);

**where constant_namespecifies the name of a generic constant, type specifies the data type of the
constant, and init_valuespecifies an initial value for the constant.

Architecture
 The architecture body specifies how the circuit operates and how it is implemented.
 Syntax
architecturearchitecture_nameof NAME_OF_ENTITY is
--architectureDeclarations
begin
-- Concurrent Statements
endarchitecture_name;
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CONFIGURATION:
 This statement selects one of several architectures for a single entity.
 Components within architectures can also be chosen.
 Unless specified, the compiled architecture is used for last simulation.
 Synthesis tool ignores configurations.
 Configuration saves re-compile time when some components need substitution in a large design.

CONFIGURATION: Syntax
configuration configuration_nameofentity_nameis
for architecture_name
for instance_name:component_name
use entity
library_name.entity_name(architecture_name);
end for;
end for;
end configuration_name;

Example:
entity half_adder is
Port (A,B : in bit;
Sum, carry : out bit); end half_adder;
architecture ha_stru of half_adderis component xor_2
Port (c,d:in bit,
e:out bit);
end component; Component and_2 Port(l,m:in bit,
n:out bit);
end component;
begin
X1: xor_2 port map (A,B,Sum);
A1: and_2 port map(A,B,Carry);
end ha_stru;
Configuration for Half-adder entity:
Library CMOS_LIB, MY_LIB;
configuration HA_BINDING of half_adderisforHA_stru
for X1: xor_2 use entity cmos_lib.xor_gate(dataflow);
end for;
for A1 : and_2 use configuration MY_LIB.and_config;
end for;
end for;
end HA_BINDING;
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Example of XOR gate

EXOR Example with internal signals

library IEEE;
use IEEE.std_logic_1164.all; Internal connections are
entity my_exor is made using signals.
port (ip1 : in std_logic; Signals are defined
ip2 : in std_logic; inside the architecture.
op1 : out std_logic
);
end my_exor;
architecture exor_w_sig of my_exor is
signal temp1, temp2 : std_logic;
begin
temp1 <= ip1 and (not ip2);
temp2 <= ip2 and (not ip1);
op1 <= temp1 or temp2;
end exor_w_sig;
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LIBRARY & PACKAGE:

 A library can be considered as a place where the compiler stores information about a design project.
 Before accessing any unit in a library it needs to be declared .
 Syntax
librarylibrary_name;
 components declared inside a library can be accessed by the ‘USE’ statement
uselibrary_name.package_name.item_name ;
uselibrary_name.item_name ;
 A VHDL package is a file or module that contains declarations of commonly used objects, data type,
component declarations, signal, procedures and functions that can be shared among different VHDL
models.
 std_logic is defined in the package ieee.std_logic_1164 in the ieee library. In order to use the std_logic
one needs to specify the library and package. This is done at the beginning of the VHDL file using
the library and the use keywords as follows:
library ieee;
use ieee.std_logic_1164.all;
 The .all extension indicates to use all of the eee.std_logic_1164 package.
 The Xilinx Foundation Express comes with several packages.

 ieee Library:
 std_logic_1164: package defines the standard datatypes
 std_logic_arith: package provides arithmetic, conversion and comparison functions for the signed,
unsigned, integer, std_ulogic, std_logic and std_logic_vector types
 std_logic_unsigned: defines all of the same arithmatic (+, -, *), comparison (<, <=, >, >=, =, /=)
and shift (shl, shr) operations as the std_logic_arith library, difference is that the extensions will
take std_logic_vector values as arguments and treat them as unsigned integers
 std_logic_misc package: defines supplemental types, subtypes, constants and functions for the
std_logic_1164 package.
 To use any of these packages, one must include the library and use clause:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 In addition, the synopsis library has the attributes package:
library SYNOPSYS;
use SYNOPSYS.attributes.all;
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 A package may consist of two separate design units : a package declaration and a package body.
 A package declaration declares all the names of items that will be seen by the design units that use
the package.
 A package body contains the implementation details of the subprograms declared in the package
declaration. A package body is not required if no subprograms are declared in a package
declaration.
 The separation between package declaration and package body serves the same purpose as the
separation between the entity declaration and architecture body.
 The syntax to declare a package is as follows:

-- Package declaration
package name_of_package is
{package declarations}
end [name_of_package];

-- Package body declarations

package body name_of_package is
{package body declarations}
end [name_of_package];

Test Benches:
 Testing a design by simulation
 Use a test bench model
 an architecture body that includes an instance of the design under test
 applies sequences of test values to inputs
 monitors values on output signals
 either using simulator
 or with a process that verifies correct operation
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Lexical Elements of VHDL:

 Identifiers
 Keywords (Reserved words)
 Numbers
 characters, Strings and Bit Strings

Identifier
 When choosing an identifier one needs to follow these basic rules:
 A basic identifier may contain only capital ‘A’ - ’Z’ , ‘a’ - ’z’, ‘0’ - ’9’, underscore
character ‘_’
 Must start with alphabet.
 May not end with underscore character.
 Must not include two successive underscore characters.
 Reserved words cannot be used as identifiers.
 An identifier is case insensitive
 An identifier can be of any length.

Extended Identifier
 An extended identifier is a sequence of characters written between two backslashes (“\”).
 case sensitive.
 different from reserved words (keywords) or any basic identifier
 any of the allowable characters can be used in any order, including special characters like, !, @, $
 Examples: \TEST\ ; \-25\ ; \2-$\ ; \BUS:\data\ ;
 Extended identifiers are allowed in the VHDL-93 version but not in VHDL-87

Keywords (Reserved Words)

 Certain identifiers are used by the system as keywords for special use such as specific constructs.
 The language defines a set of reserved words that have some specific meaning.
 These keywords cannot be used as identifiers for signals or objects we define.
 Extended identifiers can make use of keywords since these are considered different words

Numbers
 The default number representation is the decimal system.
 VHDL allows integer literals and real literals. Integer literals consist of whole numbers without a
decimal point, while real literals always include a decimal point.
 Exponential notation is allowed using the letter “E” or “e”.
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 For integer literals the exponent must always be positive.

 Examples are:
Integer literals: 12 10 256E3
Real literals: 1.2 256.24 3.14E-2
 The number –12 is a combination of a negation operator and an integer literal.
 To express a number in a base different from the base “10”, the convention used is: base#number#.
 A few examples follow.
Base 2: 2#10010# (representing the decimal number “18”)
Base 16: 16#12#
Base 8: 8#22#
Base 16: 16#1D#
 To make the readability of large numbers easier, one can insert underscores in the numbers as long
as the underscore is not used at the beginning or the end.
2#1001_1101_1100_0010#

Characters, Strings and Bit Strings

 Character literals are enclosed in single quotes
eg : ‘a’ , ‘A’, ‘1’
 a string of characters are placed in double quotation marks
eg “This is a string”
 A bit-string represents a sequence of bit values. In order to indicate that this is a bit string, one
places the ‘B’ in front of the string: B”1001”. One can also use strings in the hexadecimal or octal
base by using the X or O specifiers, respectively. Some examples are:
Binary: B”1100_1001”, b”1001011”
Hexagonal: X”C9”, x” b”
Octal: O”311”, o”113”
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Lecture-19

OBJECT TYPE

A data object holds a value of a specific type There are FOUR object types in VHDL
 Constant: can hold a single value of given type. This value is assigned to the constant before
simulation starts and value can not be changed during the course of simulation.
 Variable: can also hold a single value of given type . However, in this case different values can be
assigned to the variable at different times using a variable assignment statement.
 Signal: holds a list of values, which include the current value of the signal and a set of possible
future values that are to be appear on the signal.
 File: contains a sequence of values. Values can be read or written to the file using read and write
procedures.

 CONSTANTS:
 Syntax :
constant constant_name{, constant_name}: type [:=initial_value];
 the initial value is optional (deferred constants)
 Constants are identifiers with a fixed value.
 A constant can have a single value of a given type and cannot be changed during the simulation.
 improve the clarity and readability of a project.
 give the designer the ability to have a better documented model that is easy to update.
 If a model requires a fixed value in a number of instances, a constant should be used.
 The designer can change the value of a constant and recompile. All the instances of the constant
value are updated to reflect the new value of the constant.

 VARIABLES:
 Syntax :
variable variable_name{,variable_name}: type [:= initial_value];
 Used for local storage in process statements and subprograms.
 Canbe declaredandusedinsideaprocessstatement or in subprograms.
 The variable is updated without any delay as soon as the statement is executed.
 Variable assignment operator : ‘:=‘.
 don’t have delay associated with it.
 Require less memory & results in fast simulation
 Examples:
variable CNTR_BIT: bit :=0;
variable STS_BIT: bit_vector (7 downto 0);
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 SIGNALS:
 Syntax:
signalsignal_name{, signal_name}: type [:= initial_value];
 Connect design entities together and communicate changes in values within a
design.
 Computed value is assigned to signal after a specified delay called as Delta Delay.
 Signals can be declared in an entity declaration sections (it can be seen by all the architectures), in
an architecture declarations (local to the architecture), in a package declarations (globally
available to the user of the package) or as a parameter of a subprogram (function or procedure).
 Signal assignment operator: ‘<=‘.
 Signal assignment can be concurrent or sequential.

 FILES:
 Syntax:
filefile_names: file_type [[open mode] is string-expression];
 The string operation is interpreted by the host environment as the physical name of a file.
 The mode specifies whether the file is to be used as a read-only or write-only, or in the append
mode.
 Example:
--File type declarations
type STD_LOGIC_FILE is file of STD_LOGIC_VECTOR;
type BIT_FILE is file of BIT_VECTOR;
-- File declarations
file STIMULUS: TEXT open READ_MODE is “/usr/home/jb/add.sti”;
file VECTOR: BIT_FILE;

GENERICS vs. CONSTANTS

 Generics
 Are specified in entities.
 Hence, any change in the value of a generic affects all architectures associated with that
entity.
 Constants
 Are specified in architectures.
 Hence, any change in the value of a constant will be localized to the selected architecture
only.
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DATA TYPES
 Each data object has a type associated with it. The type defines the set of values that the object can
have and the set of operations that are allowed on it.
 VHDL is a strongly typed language that requires each object to be of a certain type.
 It is not allowed to assign a value of one type to an object of another data type (e.g. assigning an
integer to a bit type is not allowed).
 A type is a name that has a set of values and a set of operations associated with it.
 For example, INTEGER is a predefined type, with the set of values being integers in a specific range
provided by the VHDL system. The range must be provided is -(231-1) to +(231-1). Some of the
allowable and frequently used predefined operators are +, -, /, *
 BOOLEAN is another predefined data type, that has the values ‘TRUE’ and ‘FALSE’ and some of
its predefined operators are and, or, nand, nor, xor, xnor, and not.
 The declarations for the predefined types of the language are contained in package STANDARD; the
operators for these types are predefined in language.

User-defined Types
 The language also provide the facility to define new types by using type declarations and also to
define a set of operations on these types by writing functions that returns values of this new type.
 One can introduce new types by using the type declaration, which names the type and specifies its
value range.
 Syntax:
type identifier is type_definition;

SUBTYPE
 It is a type with a constraint
 Useful for range checking and for imposing additional constraints on types.
 syntax:
subtype subtype_nameisbase_type range range_constraint;
 example:
subtype DIGITS is integer range 0 to 9;
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Data Types defined in the Standard Package:

 VHDL has several predefined types in the standard package
 To use this package one has to include the following clause:
library std, work;
use std.standard.all;
Types defined in the Package Standard of the std Library
Type Range of values Example
Bit ‘0’, ‘1’ signal A: bit :=1;
bit_vector an array with each element of type bit signal INBUS: bit_vector(7 downto 0);
Boolean FALSE, TRUE variable TEST: Boolean :=FALSE
Character any legal VHDL character (see package variable VAL: character :=’$’;
standard); printable characters must be
placed between single quotes (e.g. ‘#’)

file_open_kind* read_mode, write_mode, append_mode

file_open_status* open_ok, status_error, name_error,
mode_error
Integer range is implementation dependent but constant CONST1: integer
includes at least –(231 – 1) to +(231 – 1) :=129;
Natural integer starting with 0 up to the max variable VAR1: natural :=2;
specified in the implementation
Positive integer starting from 1 up the max variable VAR2: positive :=2;
specified in the implementation

real* floating point number in the range of –1.0 x 1038 to variable VAR3: real
+1.0x 1038 (can be implementation dependent. Not :=+64.2E12;
supported by the Foundation synthesis program.
severity_level note, warning, error, failure
String array of which each element is of the type variable VAR4: string(1 to
character 1 ):= “@$#ABC*()_%Z”;
time* an integer number of which the range is variable DELAY:
implementation defined; units can be expressed in time:=5ns;
sec, ms, us, ns, ps, fs, min and hr. . Not supported
by the Foundation synthesis program
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type

Composite
Scalar type Access type file
type

Integer type Array

Floating
record
point

Enumerated
type

Physical
type

 SCALAR TYPES:

 Integer:
• Defines a type whose set of values fall within a specified integer range.
• Example:
type small_int is range 0 to 1024;
type my_word_length is range 31 downto 0;
subtype data_word is my_word_length range 7 downto 0;

Signal my_int : integer range 0 to 255;

• A subtype is a subset of a previously defined type.

 Floating point:
• has a set of values in a given range of real numbers.
• Example:
type cmos_level is range 0.0 to 3.3;
type pmos_level is range -5.0 to 0.0;

subtype cmos_low_V is cmos_level range 0.0 to +1.8;

 Physical
• Contains values that represent measurement of some physical quantity, like time, length, voltage
etc.
• Values of this type are expressed as integer multiples of a base unit.
• Example:
type CURRENT is range 0 to 1E9
units
nA;
uA = 1000 nA;
mA = 1000 uA;
Amp = 1000 mA;
end units [CURRENT];
 Enumerated
• defines a type that has a set of user-defined values consisting of identifiers and character literals.
• Syntax:
type type_name is (identifier list or character literal);
• Examples:
type MVL is (‘U’, ‘0’, ‘1’, ‘Z’);
type MICRO_OP is (load, store, add, sub, div, mult);
type state_type is (S0, S1, S2, S3);
• If one does not initialize the signal, the default initialization is the leftmost element of the list.
• The order in which values appear in declaration defines their ordering. When using relational
operators, a value is always less than a value that appears to its right in the order.
• Enumerated types have to be defined in the architecture body or inside a package

STD_LOGIC TYPE
 It is a data type defined in the std_logic_1164 package of IEEE library.
 It is an enumerated type and is defined as
type std_logic is (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’,’-’)
‘U’ unspecifie
‘X’ unknown
‘0’ strong zero
‘1’ strong one
‘Z’ high impedance
‘W’ weak unknown
‘L’ weak zero
‘H’ weak one
’-’ don’t care
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 COMPOSITE TYPES:
Composite data objects consist of a collection of related data elements in the form of
an array or record.

 ARRAY :
• Consists of elements of the same type.
• Array can be either one or multidimensional.
• One dimensional array are synthesizable.
• The synthesis of multidimensional array depends upon the synthesizer being used.
• Syntax
type array_name is array (indexing scheme) of element_type;
• Example:
type MY_WORD is array (15 downto 0) of std_logic;
type VAR is array (0 to 7) of integer;
• We can now declare objects of these data types.
signal MEM_ADDR: MY_WORD;
constant SETTING: VAR := (2,4,6,8,10,12,14,16);

 RECORD :
• Contain elements of different types.
• Syntax:
type name is
record
identifier :subtype_indication;
:
end record;
• Example:
type MY_MODULE is
record
RISE_TIME :time;
FALL_TIME : time;
SIZE : integer range 0 to 200;
DATA :bit_vector (15 downto 0);
end record;
signal A, B: MY_MODULE;
To access values or assign values to records, following method can be used:
A.RISE_TIME <= 5ns;
A.SIZE<= 120;
B <= A;
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OPERATORS
 VHDL supports different classes of operators that operate on signals, variables and constants.
 The different classes of operators are summarized below.
Class
1. Logical operators and or nand nor xor xnor
2.Relational operators = /= < <= > >=
3. Shift operators sll srl sla sra rol ror
4.Addition operators + = &
5. Unary operators + -
6. Multiplying op. * / mod rem
7. Miscellaneous op. ** abs not
 The order of precedence is the highest for the operators of class 7, followed by class 6 with the lowest
precedence for class 1.
 Unless parentheses are used, the operators with the highest precedence are applied first.
 Operators of the same class have the same precedence and are applied from left to right in an
expression.

Logic Operators:
 The logic operators (and, or, nand, nor, xor, xnor) are defined for the predefined types BIT and
BOOLEAN types and for one dimensional array of BIT and BOOLEAN.
 They give a result of the same type as the operand (Bit or Boolean).
 During evaluation, bit values ‘0’ and ‘1’ are treated as FALSE and TRUE values of BOOLEAN type
respectively.
 These operators can be applied to signals, variables and constants.
 the nand and nor operators are not associative. One should use parentheses in a sequence of nand or
nor operators to prevent a syntax error.

Relational Operators:
 The relational operators test the relative values of two scalar types and give as result a Boolean output
of “TRUE” or “FALSE”.
Operator Description Operand Types Result Type
= Equality any type Boolean
/= Inequality any type Boolean
< Smaller than scalar or discrete array types Boolean
<= Smaller than or equal scalar or discrete array types Boolean
> Greater than scalar or discrete array types Boolean
>= Greater than or equal scalar or discrete array types Boolean
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Shift Operators
 These operators perform a bit-wise shift or rotate operation on a one-dimensional array of elements of
the type bit (or std_logic) or Boolean.

Operator Description Operand Type Result Type

Sll Shift left logical (fill right Left: Any 1-D array type Same as left type
vacated bits with the 0) with elements of type bit
or Boolean;
Right: integer
Srl Shift right logical (fill left same as above Same as left type
vacated bits with 0)
Sla Shift left arithmetic (fill right same as above Same as left type
vacated bits with rightmost bit)
Sra Shift right arithmetic (fill left same as above Same as left type
vacated bits with leftmost bit)
Rol Rotate left (circular) same as above Same as left type
Ror Rotate right (circular) same as above Same as left type

Addition Operators
 The addition operators are used to perform arithmetic operation (addition and subtraction) on operands
of any numeric type.
 The concatenation (&) operator is used to concatenate two vectors together to make a longer one.
 In order to use these operators one has to specify the ieee.std_logic_unsigned.all or std_logic_arith
package package in addition to the ieee.std_logic_1164 package.

Operator Description Left Operand Type Right Operand Type Result Type
+ Addition Numeric type Same as left operand Same type
- Subtraction Numeric type Same as left operand Same type
& Concatenation Array or element type Same as left operand Same array type

CONCATENATION
 This is the process of combining two signals into a single set which can be individually addressed.
 The concatenation operator is ‘&’.
 A concatenated signal’s value is written in double quotes whereas the value of a single bit signal is
written in single quotes.
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Unary Operators
 The unary operators “ ” and “-“ are used to specify the sign of a numeric type
Operator Description Operand Type Result Type
+ Identity Any numeric type Same type
- Negation Any numeric type Same type

Multiplying Operators
 The multiplying operators are used to perform mathematical functions on numeric types (integer or
floating point).
Operator Description Left Operand Type Right Operand Type Result Type
Any integer or floating point Same type Same type
* Multiplication Any physical type Integer or real type Same as left
Any integer or real type Any physical type Same as right
/ Division Any integer or floating point Any integer or floating Same type
point
Any physical type Any integer or real Same as left
type
Any physical type Same type Integer
Mod Modulus Any integer type Same type
Rem Remainder Any integer type Same type

Miscellaneous Operators
 These are the absolute value and exponentiation operators that can be applied to numeric types. The
logical negation (not) results in the inverse polarity but the same type.
Operator Description Left Operand Type Right Operand Type Result Type
** Exponentiation Integer type Integer type Same as left
Floating point Integer type Same as left
abs Absolute value Any numeric type Same type
not Logical negation Any bit or Boolean type Same type
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Lecture-20
Concurrent and sequential statements
Concurrent VHDL Constructs
 Process statement
 When-Else statement
 With-select statement
 Signal declaration
 Block statement

Sequential VHDL Constructs

 If-else statement
 Case statement
 Loop statement
 Return statement
 Null statement
 Wait statement
 Variable Declaration
 Variable Assignment
Both
 Signal assignment
 Type and constant declaration
 Function and procedure calls
 Assert statement.
 After delay
 Signal attributes.

CONCURRENT CONSTRUCTS
 All concurrent statements in an architecture are executed simultaneously.
 Concurrent statements are used to express parallel activity as is the case with any digital circuit.
 Concurrent statements are executed with no predefined order by the simulator. So the order in which
the code is written doesn’t have any effect on its function.
 They can be used for dataflow, behavioral and structural descriptions.
 Process is the only concurrent statement in which sequential statements are allowed.
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Concurrent Statements
 Signal assignment statements:
 Simple assignment
 Selected Assignment Statement
 Conditional Assignment Statement
 block statement
 generate statement
 Assertion Statement
 Component Instantiation Statement

 Concurrent signal assignments

 The syntax is as follows:
Target_signal<= expression [after time];
 Simple concurrent signal assignment examples:
Sum <= (A xor B) xor Cin;
Z <= (not X) or Y after 2 ns;
 As soon as an event occurs on one of the signals, the expression will be evaluated.
 The type of the target_signal has to be the same as the type of the value of the expression.

 Conditional Signal assignments

 Syntax for the conditional signal assignment :
Target_signal<= expression1 when Boolean_condition else
expression2 when Boolean_condition else
:
expression;
 The target signal will receive the value of the first expression whose Boolean condition is TRUE.
 If no condition is found to be TRUE, the target signal will receive the value of the final expression.
 If more than one condition is true, the value of the first condition that is TRUE will be assigned.
 The conditional signal assignment will be re-evaluated as soon as any of the signals in the
conditions or expression change.

 When Else Statement:

 Conditions may overlap. The expression corresponding to the first "true" condition is assigned.
architecture COND of BRANCH is
begin
Z <= A when X = 5 el se
B when X < 10 else
C;
end COND;
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 Each condition is a boolean expression:

architecture COND of BRANCH is
begin
Z <= A when X > 5 else
B when X < 5 else
C;
end COND;
 There must be a final unconditional else expression:
architecture COND of WRONG is
begin
Z <= A when X > 5; --illegal
end COND;

 Selected Signal assignments

 Syntax
with choice_expression select
target_name <= expression1 when choices,
expression2 when choices;
:
expression when others;
 The target is a signal that will receive the value of an expression whose choice includes the value
of the choice_expression. The expression selected is the first with a matching choice.
 The following rules must be followed for the choices:
 No two choices can overlap
 All possible values of choice_expression must be covered by the set of choices, unless
an others choice is present.
 The choices can express a single value, a range or combined choices as shown below.
target <= value1 when “000”,
value2 when “001” “011” “101”,
value3 when others;

 WHEN-ELSE VS. WITH-SELECT

 In the ‘with’ statement, choice is limited to the choices provided by the with ‘expression’.
 In the ‘when’ statement each choice itself can be a separate expression.
 when statement is prioritized (since each choice can be a different expression, more than one
condition can be true at the same time, thus necessitating a priority based assignment)
 with statement does not have any priority (since choices are mutually exclusive).
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 Generate statement
 describe regular and/or slightly irregular structure by automatically generating component
instantiations instead of manually writing each instantiation.
 There are two variants of the generate statement:

 FOR GENERATE statement

Provides a convenient way of repeating either a logic equation or a component instantiation.
Syntax:
label: for variable in range generate -- label required
begin
concurrent statements
end generate [label] ;
 IF GENERATE statement
label: if condition generate -- label required
begin
concurrent statements
End generate [label];

 Assertion Statement
 ASSERT STATEMENT
Concurrent  used in entity, Architecture
Sequential  used in process, function, procedure.
 A statement that checks that a specified condition is true and reports an error if it is not.
 Simplified Syntax
assert condition
report string
severity severity_level;
 It has three optional fields and usually all three are used.
 The condition specified in an assertion statement must evaluate to a boolean value (true or false).
If it is false, it is said that an assertion violation occurred.
 The expression specified in the report clause must be of predefined type STRING and is a
message to be reported when assertion violation occurred.
 If the severity clause is present, it must specify an expression of predefined type
SEVERITY_LEVEL, which determines the severity level of the assertion violation.
 The SEVERITY_LEVEL type is specified in the STANDARD package and contains following
values: NOTE, WARNING, ERROR, and FAILURE.
 If the severity clause is omitted it is implicitly assumed to be ERROR.
 When an assertion violation occurs, the report is issued and displayed on the screen. The supported
severity level supplies an information to the simulator.
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 The severity level defines the degree to which the violation of the assertion affects operation of the
process:
 NOTE can be used to pass information messages from simulation;
 WARNING can be used in unusual situation in which the simulation can be continued, but the
results may be unpredictable;
 ERROR can be used when assertion violation makes continuation of the simulation not feasible;
 FAILURE can be used when the assertion violation is a fatal error and the simulation must be
stopped at once.
 Assertion statements are not only sequential, but can be used as concurrent statements as well. A
concurrent assertion statement represents a passive process statement containing the specified
assertion statement.

Example 1
assert Status = OPEN_OK
report "The call to FILE_OPEN was not successful"
severity WARNING;
o Having called the procedure FILE_OPEN, if the status is different from OPEN_OK, it is indicated
by the warning message.
Example 2
assert not (S= '1' and R= '1')
report "Both values of signals S and R are equal to '1'"
severity ERROR;
o When the values of the signals S and R are equal to '1', the message is displayed and the simulation
is stopped because the severity is set to ERROR.

Example 3
assert Operation_Code = "0000"
report "Illegal Code of Operation"
severity FAILURE;
o Event like illegal operation code are severe errors and should cause immediate termination of the
simulation, which is forced by the severity level FAILURE.
 The message is displayed when the condition is NOT met, therefore the message should be an
opposite to the condition.
 Concurrent assertion statement is a passive process and as such can be specified in an entity.
 Concurrent assertion statement monitors specified condition continuously.
 Synthesis tools generally ignore assertion statements.
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SEQUENTIAL STATEMENTS
 signal assignments
 variable assignments
 case statement
 exit statement
 if statement
 loop statement
 next statement
 null statement
 procedure call
 wait statement

 If Statements
 The if statement executes a sequence of statements whose sequence depends on one or more
conditions.
 syntax:
if condition then
sequential statements
[elsif condition then
sequential statements ]
[else
sequential statements ]
end if;

 Case Statements
 The case statement executes one of several sequences of statements, based on the value of a single
expression.
 syntax:
case expression is
when choices => sequential statements
when choices => sequential statements
-- branches are allowed
[when others => sequential statements ]
end case;
 The following rules must be adhered to:
o no two choices can overlap
o if the “when others" choice is not present, all possible values of the expression must be
covered by the set of choices.
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 Loop statements
 A loop statement is used to repeatedly execute a sequence of sequential statements
 syntax:
[ loop_label :]iteration_scheme loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop [loop_label];
 Labels are optional but are useful when writing nested loops. The next and exit statement are
sequential statements that can only be used inside a loop.
 The next statement terminates the rest of the current loop iteration and execution will proceed to
the next loop iteration.
 The exit statement skips the rest of the statements, terminating the loop entirely, and continues
with the next statement after the exited loop.
 There are three types of iteration schemes:
 basic loop
 while … loop
 for … loop
 Basic loop has no iteration scheme. It will be executed continuously until it encounters an exit or
next statement.
 The basic loop (as well as the while-loop) must have at least one wait statement.
 The while loop evaluates a Boolean iteration condition. When the condition is TRUE, the loop
repeats, otherwise the loop is skipped and the execution will halt.
 The condition of the loop is tested before each iteration, including the first iteration. If it is false,
the loop is terminated.
 Syntax:
[loop_label :] while condition loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop[ loop_label ];
 The for-loop uses an integer iteration scheme that determines the number of iterations.
 Syntax:
[ loop_label :] for identifier in range loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop[ loop_label ];
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 The identifier (index) is automatically declared by the loop itself, so one does not need to declare it
separately. The value of the identifier can only be read inside the loop and is not available outside
its loop. One cannot assign or change the value of the index. This is in contrast to the while-loop
whose condition can involve variables that are modified inside the loop.
 The range must be a computable integer range in one of the following forms, in which
integer_expression must evaluate to an integer:
 integer_expression to integer_expression
 integer_expression downto integer_expression

 Next and Exit Statement

 The next statement skips execution to the next iteration of a loop statement and proceeds with the
next iteration.
 Syntax:
next [label] [when condition];
 The exit statement skips the rest of the statements, terminating the loop entirely, and continues
with the next statement after the exited loop.
 Syntax:
exit [label] [when condition];
 The when keyword is optional in both the statements and will execute the next statement when its
condition evaluates to the Boolean value TRUE.

 Wait Statement
 The wait statement will halt a process until an event occurs.
 There are several forms of the wait statement:
wait until condition;
wait for time expression;
wait on signal;
wait;
WAIT ON signal:
 Specifies a list of one or more signals that the WAIT statement will wait for events upon.
 if any signal list has an event occur on it, execution continues with the statement following the
wait statement.
 example: WAIT ON a, b;
WAIT UNTIL expression
 Suspends execution of the process until the expression returns a value of true.
 example: WAIT UNTIL (( x * 10) < 100);
WAIT FOR time_expression
 Suspends execution of the process for the time specified by the time expression.
 example: WAIT FOR 10 ns;
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Lecture-21
Architecture Modeling Styles in VHDL

 Architecture describes the functionality of the design.

 Architecture can be described in one of the following coding styles:
 Dataflow modeling: a set of concurrent assignment statements (to represent dataflow)
 Behavioral modeling: a set of sequential assignment statements
 Structural modeling: a set of interconnected components (to represent structure),
 mixed modeling: Any combination of the above three.

 Dataflow Modeling
 The dataflow modeling describes a circuit in terms of its function and the flow of data through the
circuit.
 It shows that how the data / signal flows from input to output through the registers / Components.
 A dataflow description directly implies a corresponding gate level implementations
 Dataflow modeling Style works on Concurrent Execution.
 Concurrent signal assignments are event triggered and executed as soon as an event on one of the
signals occurs.
 Behavioural Modeling
 The behavioral style of modeling specifies the behavior of an entity as a set of statements that are
executed sequentially in the specified order.
 It is very similar in syntax and semantics to that of a high level programming languages such as C
or Pascal.
 It consists of one or more process statements.
 A process statement is a concurrent statement that can appear within architecture. It contains one
or more sequential statements.
 Structural Modeling:
 In Structural Modeling Style, entity is described as a set of interconnected components.
 Top level design module describes the interconnections of lower level design entities.
 Each lower level design entities can be described as an interconnection of design entities at the
next lower level and so on.
 Structural Modeling is most useful and efficient when a complex system is described as an
interconnections of moderately complex design entities
 Mixed Style of Modeling:
 It is possible to mix the three modeling styles in a single architecture body.
 That is, within an architecture body, we could use component instantiation statements (that
represent structure), concurrent signal assignment statements (that represent dataflow), and process
statements (that represent behavior).
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STRUCTURAL MODELING

 A structural way of modeling describes a circuit in terms of components and its interconnection.
 At the lowest hierarchy, each component is described as a behavioral model, using the basic logic
operators defined in VHDL.
 structural modeling is very good to describe complex digital systems, though a set of components
in a hierarchical fashion.
 VHDL provides a formal way by
o Declare a list of components being used
o Declare signals which define the nets that interconnect components
o Label multiple instances of the same component so that each instance is uniquely defined.

Component declaration
 Before components can be instantiated they need to be declared in the architecture declaration
section or in the package declaration.
 The component declaration consists of the component name and the interface (ports).
 The syntax is as follows:
component component_name [is]
[port (port_signal_names: mode type;
port_signal_names: mode type;
:
port_signal_names: mode type);]
end component [component_name];
 The component name refers to either the name of an entity defined in a library or an entity
explicitly defined in the VHDL file.
 The list of interface ports gives the name, mode and type of each port, similarly as is done in
the entity declaration.
 The component declaration has to be done either in the architecture body or in the package
declaration.
 If the component is declared in a package, one does not have to declare it again in the architecture
body as long as one uses the library and use clause.

Component Instantiation
 The component instantiation statement references a component that can be
o Previously defined at the current level of the hierarchy or
o Defined in a technology library (vendor’s library).
 The syntax for the components instantiation is as follows,
instance_name : component name
port map (port1=>signal1, port2=> signal2,…port3=>signaln);
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 The instance name or label can be any legal identifier and is the name of this particular instance.
 The component name is the name of the component declared earlier using the component
declaration statement.
 alternative method is the positional association,
port map (signal1, signal2,…signaln);

Generics in Component Instantiation

Syntax:
 component declaration
component component_name is generic (list-of-generics);
port (list-of-interface-ports);
end component ;
 component instantiation statement
component-label: component-name generic map (generic-association-list) port map (port
association-list);

BEHAVIORAL MODELING (SEQUENTIAL MODELIONG)

 The behavior of the entity is expressed using sequentially executed, procedural code, which is very
similar in syntax and semantics to that of a high level programming languages such as C or Pascal.
 Process statement is the primary mechanism used to model the behavior of an entity.
 Process statement has a declarative part (before the keyword begin) and a statement part (between
the keywords begin and end process).
 The statements appearing within the statement part are sequential statements and are executed
sequentially.
 Process Statement
 A process statement is the main construct in behavioralmodeling that allows you to use
sequential statements to describe the behavior of a system over time.
 syntax for a process statement is
[process_label:] process [ (sensitivity_list) ] [is]
[ process_declarations]
begin
list of sequential statements
end process [process_label];
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VHDL code for all logic gates using dataflow modeling style:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ALLGATES is
Port ( A,B : in STD_LOGIC;
AND1,OR1,NOT1,NAND1,NOR1,XOR1,XNOR1: out STD_LOGIC);
end ALLGATES_SOURCE;

architecture df of ALLGATES is
begin
AND1<=A AND B;
OR1<= A OR B;
NOT1 <= NOT A;
NAND1<= A NAND B;
NOR1<= A NOR B;
XOR1<= A XOR B;
XNOR1<= A XNOR B;
end df;

Test bench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity gates_tb is
end entity;

architecture tb of gates_tb is
component ALLGATES is
Port ( A,B : in STD_LOGIC;
AND1,OR1,NOT1,NAND1,NOR1,XOR1,XNOR1: out STD_LOGIC);
end component;
signal A, B, P, Q, R, S, T, U, V : STD_LOGIC;
begin
uut: ALLGATES port map( A,B,P, Q, R, S, T, U, V);
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st: process
begin
A <= '0'; B <= '0';
wait for 20 ns;
A <= '0'; B <= '1';
wait for 20 ns;
A <= '1'; B <= '0';
wait for 20 ns;
A <= '1'; B <= '1';
wait for 20 ns;
wait;
end process;
end tb;
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HALF ADDER
Truth Table

VHDL PROGRAM FOR HALF ADDER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

Entity half_adder is
Port ( A,B : in STD_LOGIC;
sum, carry : out STD_LOGIC);
end half_adder;
--BEHAVIOURAL MODELING
architecture Behavioral of half_adder is
begin
PROCESS(A,B)
BEGIN
--logic for sum
If (a=b) then
sum<= ‘0’;
else
sum<= ‘1’;
end if;
--logic for carry
If (a=’1’ and b = ‘1’) then
carry <= ‘1’;
else
carry <= ‘0’;
end if;
END PROCESS;
end Behavioral;
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--DATAFLOW MODELING

architecture data_flow of half_adder is

begin
sum<= A XOR B;
carry<= A AND B;
end data_flow;

Test bench for Half Adder

library IEEE;
use IEEE.std_logic_1164.all;

entity half_adder_tb is
end entity;

architecture tb of half_adder_tb is
component half_adder is
port( a,b : IN std_logic;
sum,carry : OUT std_logic);
end component;
signal a,b,sum,carry: std_logic;
Begin
uut: half_adder port map( a => a, b => b, sum => sum, carry => carry);
stim: process
begin
a <= '0'; b <= '0';
wait for 20 ns;
a <= '0'; b <= '1';
wait for 20 ns;
a <= '1'; b <= '0';
wait for 20 ns;
a <= '1'; b <= '1';
wait for 20 ns;
wait;
end process;
end tb;
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Lecture-22

VHDL PROGRAMS FOR COMBINATIONAL CIRCUITS

HALF SUBTRACTOR

VHDL Code (Behavioural Modeling)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

Entity HS is
Port ( a,b : in bit;
diff, bor : out bit);
end HS;

architecture HS_beh of HS is
begin
Process (a,b)
Begin
--logic for difference
If (a=b) then
diff<= ‘0’;
else
diff<= ‘1’;
end if;

--logic for borrow

If (a=’0’ and b = ‘1’) then
bor<= ‘1’;
else
bor<= ‘0’;
end if;
end process;
end HS_beh;
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FULL SUBTRACTOR
Truth Table:
A B C diff borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
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VHDL Code (Behavioural Modeling)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

Entity FS is
Port (a,b,c: in bit;
diff, bor: out bit);
end FS;

architecture FS_behof FS is
begin

P1: Process (a,b,c)

Begin
If (a=‘0’) then
if (b=c) then diff<=‘0’;
else diff<=‘1’;
end if;
else
if (b=c) then diff<=‘1’;
else diff<=‘0’;
end if;
end if;
end process p1;

P2: Process (a,b,c)

Begin
If (a=‘0’) then
if (b=‘0’ and c=‘0’) then bor<=‘0’;
else bor<=‘1’;
end if;
else
if (b=‘1’ and c=‘1’) then bor<=‘1’;
else bor<=‘0’;
end if;
end if;
end process P2;
End FS_beh;
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VHDL Code for 4x1 MUX (If-else Statement)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4_1 is
port (i : in std_logic_vector (0 to 3);
s : in std_logic_vector(0 to 1);
y: out std_logic);
end mux4_1;
architecture Behavioral of mux4_1 is
begin
process(s,i)
begin
If (s = "00") then y <= i(0);
elsif(s = "01") then y <= i(1);
elsif(s = "10") then y <= i(2);
else y <= i(3);
end if;
end process;
end Behavioral;
VHDL Code for 4x1 MUX (Case Statement)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4_1 is
port (i : in std_logic_vector (0 to 3);
s : in std_logic_vector(0 to 1);
y: out std_logic);
end mux4_1;
architecture Behavioral of mux4_1 is
begin
process(s,i)
begin
case s is
when "00" => y <= i(0);
when "01" => y <= i(1);
when "10" => y <= i(2);
when others => y <= i(3);
end case;
end process;
end Behavioral;
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VHDL Code for 4x1 MUX (Select Statement)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4_1 is
port (i : in std_logic_vector (0 to 3);
s : in std_logic_vector(0 to 1);
y: out std_logic);
end mux4_1;

architecture Behavioral of mux4_1 is

begin
with s select
y <= i(0) when "00",
i(1) when "01",
i(2) when "10",
i(3) when others;
end Behavioral;

VHDL Code for 4x1 MUX (When-else Statement)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4_1 is
port (i : in std_logic_vector (0 to 3);
s : in std_logic_vector(0 to 1);
y: out std_logic);
end mux4_1;

architecture Behavioral of mux4_1 is

begin
y <= i(0) when s = "00"
else i(1) when s = "01"
else i(2) when s = "10"
else i(3);
end Behavioral;
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Lecture-23

VHDL PROGRAMS FOR SEQUENTIAL CIRCUITS

Flip Flops
A flip-flop is a device which stores a single bit (binary digit) of data; It is a basic memory element in
digital systems (same as the bi-stable multivibrator) one of its two states represents a "one" and the other
represents a "zero". Such a circuit is described as sequential logic.
There are 4 types of flip flops:
1. SR Flip-flop
2. JK Flip-flop
3. D Flip-flop
4. T Flip-flop

D- Flip Flop
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VHDL Code for D Flip Flop

library ieee ;
use ieee.std_logic_1164.all;

entity dff is
port( D, clock,reset : in std_logic;
dout: out std_logic );
end dff;

architecture behv of dff is

begin
process(clock,reset)
begin
If (reset=‘1’) then
dout<=‘0’;
elsif (clock='1' and clock'event) then -- clock rising edge
data_out<= D;
end if;
end process;
end behv;
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S-R Flip-flop (Set-Reset)

In a memory device set and Reset is often required

for synchronization of the device in such case S-R
Flip-flop is need & this is refereed as clocked set-
reset.

VHDL Code for SR Flip Flop

library ieee ;
use ieee.std_logic_1164.all;
entity srff is
Port(reset,clock,s,r : in std_logic;
q: out std_logic );
end srff;
architecture behv of srff is
Signal FF: std_logic:=‘0’;
begin
process(clock,reset)
variable sr: std_logic_vector(0 to 1);
begin
If (reset=‘0’) then --negative logic
FF<=‘0’;
-- clock negative edge
elsif (clock=‘0' and clock'event) then
sr := s & r;
case sr is
when "01" => FF <= ’0’;
when "10" => FF <= ’1’;
when "11" => FF <= ’Z’;
when others => FF <= FF;
end case;
end if;
end process;
Q<= FF;
end behv;
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JK Flip-flop

The race conditions in S-R Flip-flop can be

eliminated by converting it in to J.K, the data
inputs J and K are ANDed with Q\ and Q to obtain
S & R inputs.
S=J.Q\
R=K.Q

VHDL Code for JK Flip Flop

library ieee ;
use ieee.std_logic_1164.all;

entity jkff is
Port(reset,clock,j,k : in std_logic;
q: out std_logic );
end jkff;
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Ramnagaria, Jagatpura, Jaipur-302017, INDIA
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Recognized by UGC under Section 2(f) of the UGC Act, 1956
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architecture behv of jkff is

Signal FF: std_logic;
begin
process(clock,reset)
variable jk: std_logic_vector(0 to 1);
begin
If (reset=‘0’) then --negative logic
FF<=‘0’;
-- clock negative edge
elsif (rising_edge(clock)) then
jk := j & k;
case jk is
when "01" => FF <= ’0’;
when "10" => FF <= ’1’;
when "11" => FF <= not FF;
when others => FF <= FF;
end case;
end if;
end process;
Q<= FF;
end behv;
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Ramnagaria, Jagatpura, Jaipur-302017, INDIA
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T-Flip-flop (Toggle)
On every change in clock pulse the output ‘Q’
changes its state (Toggle). A Flip-flop with one
data input which changes state for every clock
pulse.(J=K=’1’ in JK Flip-flop the resulting
output is ‘T’ Flip-flop).

VHDL Code for T Flip Flop

library ieee ;
use ieee.std_logic_1164.all;

entity tff is
Port(reset,clock,t : in std_logic;
q: out std_logic );
end tff;

architecture behv of tff is

begin
process(clock,reset)
Variable FF: std_logic;
begin
If (reset=‘0’) then
FF:=‘0’;
elsif (clock=‘0' and clock'event) then
if (t=‘1’) then
FF:= not FF;
end if;
end if;
Q<= FF;
end process;
end behv;
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
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Simulation Waveforms:
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Lecture-24
SHIFT REGISTERS
Flip flops can be used to store a single bit of binary data (1or 0). However, in order to store multiple bits
of data, we need multiple flip flops. N flip flops are to be connected in an order to store n bits of data.
A Register is a device which is used to store such information. It is a group of flip flops connected in
series used to store multiple bits of data.
The information stored within these registers can be transferred with the help of shift registers. Shift
Register is a group of flip flops used to store multiple bits of data. The bits stored in such registers can
be made to move within the registers and in/out of the registers by applying clock pulses. An n -bit shift
register can be formed by connecting n flip-flops where each flip flop stores a single bit of data.
The registers which will shift the bits to left are called “Shift left registers”.
The registers which will shift the bits to right are called “Shift right registers”.
Shift registers are basically of 4 types. These are:
1. Serial In Serial Out shift register
2. Serial In parallel Out shift register
3. Parallel In Serial Out shift register
4. Parallel In parallel Out shift register

Serial-In Serial-Out Shift Register (SISO) –

The shift register, which allows serial input (one bit after the other through a single data line) and
produces a serial output is known as Serial-In Serial-Out shift register. Since there is only one output,
the data leaves the shift register one bit at a time in a serial pattern, thus the name Serial-In Serial-Out
Shift Register.
The logic circuit given below shows a serial-in serial-out shift register. The circuit consists of four D
flip-flops which are connected in a serial manner. All these flip-flops are synchronous with each other
since the same clock signal is applied to each flip flop.

The above circuit is an example of shift right register, taking the serial data input from the left side of
the flip flop. The main use of a SISO is to act as a delayelement.
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Serial-In Parallel-Out shift Register (SIPO) –

The shift register, which allows serial input (one bit after the other through a single data line) and
produces a parallel output is known as Serial-In Parallel-Out shift register.
The logic circuit given below shows a serial-in-parallel-out shift register. The circuit consists of four D
flip-flops which are connected. The clear (CLR) signal is connected in addition to the clock signal to all
the 4 flip flops in order to RESET them. The output of the first flip flop is connected to the input of the
next flip flop and so on. All these flip-flops are synchronous with each other since the same clock signal
is applied to each flip flop.

The above circuit is an example of shift right register, taking the serial data input from the left side of
the flip flop and producing a parallel output. They are used in communication lines where
demultiplexing of a data line into several parallel lines is required because the main use of the SIPO
register is to convert serial data into parallel data.

Parallel-In Serial-Out Shift Register (PISO) –

The shift register, which allows parallel input (data is given separately to each flip flop and in a
simultaneous manner) and produces a serial output is known as Parallel-In Serial-Out shift register.
The logic circuit given below shows a parallel-in-serial-out shift register. The circuit consists of four D
flip-flops which are connected. The clock input is directly connected to all the flip flops but the input
data is connected individually to each flip flop through a multiplexer at the input of every flip flop. The
output of the previous flip flop and parallel data input are connected to the input of the MUX and the
output of MUX is connected to the next flip flop. All these flip-flops are synchronous with each other
since the same clock signal is applied to each flip flop.

A Parallel in Serial out (PISO) shift register us used to convert parallel data to serial data.
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Parallel-In Parallel-Out Shift Register (PIPO) –

The shift register, which allows parallel input (data is given separately to each flip flop and in a
simultaneous manner) and also produces a parallel output is known as Parallel-In parallel-Out shift
register.
The logic circuit given below shows a parallel-in-parallel-out shift register. The circuit consists of four
D flip-flops which are connected. The clear (CLR) signal and clock signals are connected to all the 4
flip flops. In this type of register, there are no interconnections between the individual flip-flops since
no serial shifting of the data is required. Data is given as input separately for each flip flop and in the
same way, output also collected individually from each flip flop.
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Bidirectional Shift Register –

If we shift a binary number to the left by one position, it is equivalent to multiplying the number by 2
and if we shift a binary number to the right by one position, it is equivalent to dividing the number by
2.To perform these operations we need a register which can shift the data in either direction.
Bidirectional shift registers are the registers which are capable of shifting the data either right or left
depending on the mode selected. If the mode selected is 1(high), the data will be shifted towards the
right direction and if the mode selected is 0(low), the data will be shifted towards the left direction.
The logic circuit given below shows a Bidirectional shift register. The circuit consists of four D flip -
flops which are connected. The input data is connected at two ends of the circuit and depending on the
mode selected only one and gate is in the active state.
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VHDL code for SISO Shift Register

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity siso is
port(sin,clk, rst : in std_logic;
sout: out std_logic );
end siso;

architecture struct of siso is

signal x:std_logic_vector (0 to 4);
component dff
port(D,clock,reset : in std_logic;
dout: out std_logic);
end component;
Begin
X(0)<= sin;
L1: For i in 0 to 3 generate
L2:dff port map (x(i),clk,rst,x(i+1));
End generate;
Sout<= x(4);
end struct;
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VHDL code for SIPO Shift Register

library ieee;
use ieee.std_logic_1164.all;
entity sipo is
port(sin,clk,rst : in std_logic;
Q: out std_logic_vector(3 downto 0) );
end sipo;
architecture arch of sipo is
signal x: std_logic_vector (3 downto 0);
begin
process (rst,clk)
begin
if rst = ‘1’ then
x <= "0000";
elsif (CLK'event and CLK='1') then
x <= sin & x(3 downto 1);
end if;
end process;
Q<= x;
end arch;

Universal Shift Register

VHDL Code for Universal Shift Register

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity univ_SHIFT_REGISTER is
Generic (N : integer := 4);
Port ( Din : in STD_LOGIC_VECTOR (N-1 downto 0);
Dout : out STD_LOGIC_VECTOR (N-1 downto 0);
ld_shift, l_r, rst, clk, Sin : in STD_LOGIC;
sout: out STD_LOGIC);
end univ_SHIFT_REGISTER;

architecture Behavioral of univ_SHIFT_REGISTER is

signal tmp: STD_LOGIC_VECTOR(N-1 downto 0);
begin
process (clk, rst)
begin
if rst='1' then
tmp<= "0000";
elsif (clk'event and clk = '1') then
if (ld_shift='1') then tmp<= Din;
elsif ( l_r='1' ) then tmp<= tmp(N-2 downto 0) & Sin;
else tmp<= sin &tmp(N-1 downto 1);
end if;
end if;
end process;
Sout<= tmp(N-1) when (l_r = '1') else tmp (0);
Dout<=tmp;
end Behavioral;
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Lecture-25
COUNTERS
A special type of sequential circuit used to count the pulse is known as a counter, or a collection of flip
flops where the clock signal is applied is known as counters.
The counter is one of the widest applications of the flip flop. Based on the clock pulse, the output of the
counter contains a predefined state. The number of the pulse can be counted using the output of the
counter.
Truth Table

There are the following types of counters:

o Asynchronous Counters
o Synchronous Counters

Asynchronous or ripple counters

The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle (T) flip-flop are being used.
But we can use the JK flip-flop also with J and K connected permanently to logic 1. External clock is
applied to the clock input of flip-flop A and QA output is applied to the clock input of the next flip-flop
i.e. FF-B.
Logical Diagram
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Operation
S.N. Condition Operation

1 Initially let both QBQA = 00 initially

the FFs be in the
reset state

2 After 1st As soon as the first negative clock edge is applied, FF-A will toggle and
negative clock QA will be equal to 1.
edge QA is connected to clock input of FF-B. Since QA has changed from 0 to
1, it is treated as the positive clock edge by FF-B. There is no change in
QB because FF-B is a negative edge triggered FF.
QBQA = 01 after the first clock pulse.

3 After 2nd On the arrival of second negative clock edge, FF-A toggles again and
negative clock QA = 0.
edge The change in QA acts as a negative clock edge for FF-B. So it will also
toggle, and QB will be 1.
QBQA = 10 after the second clock pulse.

4 After 3rd On the arrival of 3rd negative clock edge, FF-A toggles again and
negative clock QA become 1 from 0.
edge Since this is a positive going change, FF-B does not respond to it and
remains inactive. So QB does not change and continues to be equal to 1.
QBQA = 11 after the third clock pulse.

5 After 4th On the arrival of 4th negative clock edge, FF-A toggles again and
negative clock QA becomes 1 from 0.
edge This negative change in QA acts as clock pulse for FF-B. Hence it
toggles to change QB from 1 to 0.
QBQA = 00 after the fourth clock pulse.
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Synchronous counters
If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a counter is
called as synchronous counter.
2-bit Synchronous up counter
The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle flip-flop. The JB and
KB inputs are connected to QA.
Logical Diagram

Operation
S.N. Condition Operation

1 Initially let both QBQA = 00 initially.

the FFs be in the
reset state

2 After 1st negative As soon as the first negative clock edge is applied, FF-A will toggle
clock edge and QA will change from 0 to 1.
But at the instant of application of negative clock edge, QA , JB = KB =
0. Hence FF-B will not change its state. So QB will remain 0.
QBQA = 01 after the first clock pulse.

3 After 2nd negative On the arrival of second negative clock edge, FF-A toggles again and
clock edge QA changes from 1 to 0.
But at this instant QA was 1. So JB = KB= 1 and FF-B will toggle.
Hence QB changes from 0 to 1.
QBQA = 10 after the second clock pulse.

4 After 3rd negative On application of the third falling clock edge, FF-A will toggle from 0
clock edge to 1 but there is no change of state for FF-B.
QBQA = 11 after the third clock pulse.

5 After 4th negative On application of the next clock pulse, QA will change from 1 to 0 as
clock edge QB will also change from 1 to 0.
QBQA = 00 after the fourth clock pulse.
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Classification of counters
Depending on the way in which the counting progresses, the synchronous or asynchronous counters are
classified as follows −
 Up counters
 Down counters
 Up/Down counters

UP/DOWN Counter
Up counter and down counter is combined together to obtain an UP/DOWN counter. A mode control (M)
input is also provided to select either up or down mode. A combinational circuit is required to be
designed and used between each pair of flip-flop in order to achieve the up/down operation.
 Type of up/down counters
 UP/DOWN ripple counters
 UP/DOWN synchronous counter

UP/DOWN Ripple Counters

In the UP/DOWN ripple counter all the FFs operate in the toggle mode. So either T flip-flops or JK flip-
flops are to be used. The LSB flip-flop receives clock directly. But the clock to every other FF is
obtained from (Q = Q bar) output of the previous FF.
 UP counting mode (M=0) − The Q output of the preceding FF is connected to the clock of the
next stage if up counting is to be achieved. For this mode, the mode select input M is at logic 0
(M=0).
 DOWN counting mode (M=1) − If M = 1, then the Q bar output of the preceding FF is connected
to the next FF. This will operate the counter in the counting mode.

Example
3-bit binary up/down ripple counter.
 3-bit − hence three FFs are required.
 UP/DOWN − So a mode control input is essential.
 For a ripple up counter, the Q output of preceding FF is connected to the clock input of the next
one.
 For a ripple up counter, the Q output of preceding FF is connected to the clock input of the next
one.
 For a ripple down counter, the Q bar output of preceding FF is connected to the clock input of the
next one.
 Let the selection of Q and Q bar output of the preceding FF be controlled by the mode control
input M such that, If M = 0, UP counting. So connect Q to CLK. If M = 1, DOWN counting. So
connect Q bar to CLK.
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Lecture-26
UNIT-III
MOS INVERTERS
 The inverter is the most fundamental logic gate that performs a Boolean operation on a single input
variable.
 Using positive logic convention
-- Logic ‘1’ represents high voltage of VDD
--Logic ‘0’ represents low voltage of 0

Fig. Logic Symbol and Truth Table of the Inverter

Voltage Transfer Characteristics of Ideal Inverter

 Vth is called the inverter threshold voltage.
 For Ideal Inverter Vth =VDD/2
 The input voltage between 0 and Vth is interpreted as logic ‘0’ =>Vout= ‘1’
 The input voltage between Vth and VDD is interpreted as logic ‘1’=>Vout= ‘0’

Fig. Voltage Transfer Characteristic curve of ideal Inverter

Generalized circuit of nMOS inverter

• The driver transistor (nmos)
 Vin =VGS andVout= VDS
 The source and the substrate are ground, VSB=0
• The load device (represented as two terminal circuit element)
 terminal current is IL, and terminal voltage is VL
• The characteristics of the inverter circuit depends on load device.

Voltage Transfer Characteristic (VTC):

 The VTC describe Voutas a function of Vin under DC condition
 Applying KCL
ID (Vin,Vout) =IL(VL)
At very low input voltage level
 Vout= VOH
 Driver transistor (nMOS) is cut off
 no conducting current
 voltage drop across the load is very small

As Vin increases
 The driver transistor starts conducting
 The output voltage starts to decrease.
 two critical voltage points, where the slope of curve dVout/dVin=-1
 the smaller input voltage level is VIL
 The larger input voltage level is VIH
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 Further increase in input

 Output voltage continues to drop and reaches to the level of VOL, when input voltage level is equal
to VOH
 The inverter threshold Vth is considered as the transition voltage where Vin=Vout

Critical Voltage Levels

 VOH: Maximum output voltage when the output level is logic ‘1’
 VOL: Minimum output voltage when the output level is logic ‘0’
 VIL: Maximum input voltage which can be interpreted as logic ‘0’
 VIH: Minimum input voltage which can be interpreted as logic ‘1’

Noise Immunity and Noise Margin

Fig. Propagation of digital signals under the influence of noise

 Noise Margins are the measure of logic circuit’s noise tolerance.

 (by how much the input voltage can change without disturbing the present logic output state).
 Circuit consists of three identical inverters connected in cascade
 the input voltage of the first inverter is VOH, i.e., a logic ‘1’
 the output voltage of the first inverter will be equal to VOLcorresponding to a logic ‘0’ level
 output signal is transmitted to the next inverter input via an interconnect (metal or polysilicon line)
 on-chip interconnects are generally prone to signal noise
 the output signal of the first inverter will be perturbed during transmission
 If the input voltage of the second inverter is smaller than VOL, this signal will be interpreted correctly
as logic ‘0’
 if the input voltage becomes larger than VIL (as a result of noise), then it may not be interpreted
correctly.
 VILis the maximum allowable voltage at the input of the second inverter, which is low enough to
ensure a logic ‘1’ output.
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 Assume that the second inverter produces an output voltage level of VOH.
 this output signal will be perturbed because of noise interference, and the voltage level at the input of
the third inverter will be different from VOH
 If the input voltage of the third inverter is larger than VOH, this signal will be interpreted correctly as a
logic ‘1’
 If the voltage level drops below VIHdue to noise, the input voltage of third inverter cannot be
interpreted as a logic ‘1’
 VIHis the minimum allowable voltage at the input of the third inverter which is high enough to ensure a
logic ‘0’ output.

Noise Margins
 Noise margins are the noise tolerances for the digital circuits.
 The noise immunity of the circuit increases with NM
 Two noise margins are defined:
 the noise margin for low signal levels (NML)
 the noise margin for high signal levels (NMH).

NML = VIL - VOL

NMH =VOH -VIH
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Resistive-Load inverter

 Enhancement-type nMOS transistor acts as the

driver device.
 The load consists of a simple linear resistor, RL
 In DC steady-state operation, the drain current
IDof the driver MOSFET is equal to the load
current IR
 To simplify the calculations, channel-length
modulation effect will be neglected.
 the source and the substrate terminals of the
driver transistor are both connected to the
ground; hence, VSB = 0

Operation modes:

(i) Vin<VT0 cut off

No current, no voltage drop across the load resistor
V =V
out DD
(ii) VT0 ≤ Vin<Vout+VT0,  saturation
 Initially, (VDS =Vout) > Vin-VT0
Thus

 With increasing input voltage, the drain current of the driver also increases, and the output
voltage V0ut, starts to drop
(iii) Vin ≥ Vout+VT0  Linear
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Operating regions of the driver transistor in the resistive-load inverter

Fig.: Typical VTC of a resistive-load inverter

circuit.

Calculation of VOH
The output voltage Vout is given by Vout = VDD - RL . IR
When Vin< Vth  the driver transistor is cutoff
Thus IR = ID = 0  VOH = VDD

Calculation of VOL
Assume that the input voltage is equal to VOH
i.e. Vin = VOH = VDD
Since Vin –VT0>Voutdriver transistor operates in linear region

Using KCL for the output node, i.e. IR = ID

Calculation of VIL
By definition, VIL is the smaller of the two input voltage values at which the slope of the VTC becomes
equal to (-1), i.e., dVout/dVin = - 1
when the input is equal to VIL, the output voltage (Vout) is only slightly smaller than VOH.
Vout> Vin – VT0 the driver transistor operates in saturation.
Writing the KCL for the output node.

differentiate both sides of equation with respect to Vin,

Since the derivative of the output voltage with respect to the input voltage is equal to (-1) at VIL, we can
substitute dVout /dVin = -1

The value of the output voltage when the input is equal to VIL

Calculation of VIH
VIH is the larger of the two voltage points on VTC at which the slope is equal to (-1).
when the input voltage is equal to VIH, the output voltage Vout, is only slightly larger than the output low
voltage VOL.
Vout< Vin – VT0  driver transistor operates in linear region.
Applying KCL equation for the output node,

Differentiating both sides w.r.t. Vin, we get

substitute dVout /dVin = -1, since the slope of the VTC is equal to (-1) also at Vin = VIH

Substitute into the current equation

Positive solution of this equation gives the output voltage

Finally

Calculation of Vth
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VTC of the resistive-load inverter, for different of the parameter (knRL)

Lecture-27
NMOS Inverters with Active Load
Enhancement-Load nMOS Inverter
 The saturated enhancement-load inverter requires a single voltage supply and a relatively simple
fabrication process, yet the VOHlevel is limited to VDD – VT,Ioad.
 In linear enhancement load inverter, the VOHlevel is equal to VDD, resulting in higher noise margins
compared to saturated enhancement-load inverter.
 The most significant drawback of linear enhancement load inverter is the use of two separate power
supply voltages.
 both types of inverter suffer from relatively high stand-by (DC) power dissipation; hence,
enhancement-load nMOS inverters are not used in any large-scale digital applications.
Depletion-Load nMOS Inverter
Advantages:
i. sharp VTC transition and better noise
margins,
ii. single power supply, and
iii. smaller overall layout area.
 VT0, driver >0, and VT0, Load <0,
 VGS,load= 0 always
 the condition VGS,Load>VT,loadis
satisfied, and the load device always
has a conducting channel regardless of
the input and output voltage levels.

 the load device is subject to the substrate-bias effect, so that its threshold voltage is a function of its
source-to substrate voltage, VSB,load= Vout.

 When the output voltage is small, i.e.,

when Vout< VDD +VT,load, (VDS,load>VGS,load–VT,load)
 the load transistor is in saturation.
load current is given by
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 For larger output voltage levels, i.e., for (Vout> VDD + VT,load),the depletion-type load transistor
operates in the linear region.
The load current is

Figure: Typical VTC of a depletion-load

inverter circuit.

Calculation of Critical Voltage Levels

 The operating regions and the voltage levels of the driver and the load transistors at critical points are
as follows
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Calculation of VOH
When Vin< VT0,driver  the driver transistor is cutoff and load device is conducting in linear region
Thus ID,load = ID,driver = 0 , substituting VOH=Vout

The only valid solution in the linear region is VOH = VDD.

Calculation of VOL
Assume that the input voltage is equal to VOH
i.e. Vin = VOH = VDD
Since Vin –VT0>Voutdriver transistor operates in linear region, load operates in saturation region

The above equation can be solved by temporarily neglecting the dependence of VT,load on VOL as follows

Calculation of VIL
When Vin= VIL slope of VTC curve dVout/dVin = - 1
Vout> Vin – VT0the driver transistor operates in saturation region
load operates in linear region
Applying KCL for the output node

Differentiate both sides of equation with respect to Vin,

we can assume that the term (dVT,Ioad/dVin) is negligible with respect to the others.
Substituting VIL for Vin, and letting dVout/dVin = -1, we obtain
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Differentiating both sides w.r.t. Vin, we get

.
substitute dVout /dVin = -1, since the slope of the VTC is equal to (-1) and solve for Vin = VIH

the derivative of the load threshold voltage with respect to the output voltage cannot be neglected and is
given by

VTC of the depletion-load inverter, with different driver to load ratios

The driver to load ratio is given by

Lecture-28
CMOS INVERTER

Figure. (a)CMOS inverter circuit. (b)Simplified view of the CMOS inverter, consisting of two
complementary

 It consists of an enhancement-type nMOS transistor and an enhancement-type pMOS transistor,

operating in complementary mode
 both devices contribute equally to the circuit operation characteristics.
 for high input, the nMOS transistor drives (pulls down) the output node while the pMOS transistor
acts as the load, and for low input the pMOS transistor drives (pulls up) the output node while the
nMOS transistor acts as the load
 circuit topology is complementary push-pull
Advantages:
 the steady-state power dissipation is virtually negligible, except for small power dissipation due to
leakage currents.
 VTC exhibits a full output voltage swing between 0V and VDD (large Noise Margins) and very sharp
transition (resembles that of an ideal inverter)
Disadvantages:
 Fabrication process is more complex than the standard nMOS-only process.
 the close proximity of an nMOS and a pMOS transistor may cause latch-up condition. (In order to
prevent this undesirable effect, additional guard rings must be built around the nMOS and the pMOS
transistors as well)
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CMOS Operation
 Since VSB = 0 for both devices, thus no
substrate-bias effect
 From circuit diagram
VGS,n = Vin
VDS,n = Vout
and
VGS,p = - (VDD - Vin)
VDS,p = - (VDD - Vout)

 When Vin< VT0,n, nMOS cutoff, pMOSlinear region

ID,n = ID,p = 0
VDS,p = 0
Vout = VOH = VDD
 When Vin> (VDD+VT0,p), nMOSlinear region, pMOScutoff
ID,n = ID,p = 0
VDS,n = 0
Vout = VOL = 0
 nMOS transistor operates in saturation
if Vin> VT0,n and VDS,n≥ VGS,n- VTO,n=>Vout ≥ Vin - VTO,n
 The pMOS transistor operates in saturation
if Vin< VDD+VT0,p and VDS,p≤ VGS,p– VTO,p=>Vout ≤ Vin – VTO,p

VTC Curve with operating regions

Calculation of Critical Voltage Levels

 Five regions and the corresponding critical input and output voltage levels

 As ID =f (VGS, VDS) ID,n =f (Vin, Vout) and ID,p =f (Vin, Vout)

 According to KCL
ID,n = ID,p

Calculation of VIL
When Vin= VIL slope of VTC curve dVout/dVin = - 1
nMOS saturation region and pMOSlinear region
From ID,n= ID,p we obtain the following current equation:

The expression can be rewritten as

Differentiating both sides w.r.t. Vin, we get

Substituting Vin =VIL , and dVout/dVin = -1, we obtain

The critical voltage VIL can be found as a function of the output voltage as follows:

Calculation of VIH
When Vin =VIH
nMOS linear region, and pMOS saturation region
Applying KCL equation for the output node,

The expression can be rewritten as

Differentiating both sides w.r.t. Vin, we get

substituting dVout /dVin = -1, and Vin = VIH , we get

The critical voltage VIH can be found as a function of the output voltage as follows:

Where

Calculation of Vth
 The inverter threshold voltage is defined as Vth = Vin = Vout
set Vin = Vout = Vth = 0.5VDD
For pMOS transistor:
VGS,p=Vin-VDD=-0.5VDD, and VDS,p=Vout-VDD=-0.5VDD
VDS,p<VGS,p – VT,p saturation region

For nMOS transistor:

VGS,n=Vin = 0.5VDD, and VDS,n=Vout= 0.5VDD
VDS,n>VGS,n – VT0,n  saturation region

Applying KCL
ID,p= ID,n
=
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VTC of the CMOS inverter, with different nMOS to pMOS ratios

The driver to load ratio is given by

Pseudo nMOS Inverter

 Pseudo nMOS design style reduces dynamic power (by reducing capacitive loading) at the cost of
having non-zero static power by replacing the pull up network by a single pMOS transistor with its
gate terminal grounded.
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Pull-up to Pull-down Ratio (Zpu/Zpd)

Pull-up to pull-down ratio is defined as
Z= Zpu/Zpd
Where
Zpu (L/W)Load, and
Zpd (L/W)driver
Pull-up to Pull-down Ratio for nMOS Inverter
 For nMOS inverter with enhancement type nMOS driver transistor and depletion
type nMOS load transistor
For equal margins around the inverter threshold;
Set Vth = 0.5VDD , Vin = Vout = Vth
for load transistor:
VDS,load = VDD - Vout = VDD - 0.5VDD = 0.5VDD and VGS,load= 0
Thus VDS,load>VGS,load – VT0,load saturation region
for driver transistor:
VDS,driver = Vout = 0.5VDD and VGS,driver= Vin = 0.5VDD
Thus VDS,load>VGS,load – VT0,load saturation region
both the transistors are in saturation

As ID,load= ID,driver

=
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Lecture-29

Calculation and Analysis of Delays (Speed) for CMOS inverter

Cascade Connection of two CMOS Inverter

 To simplify the problem of voltage dependent capacitances, the capacitances of this circuit are
combined into an equivalent lumped linear capacitance, connected between the O/P node of the
inverter and the ground.
 This combined capacitance at the output node will be called the load capacitance (Cload)
 Cload= Cgd,n + Cgd,p + Cdb,n + Cdb,p + Cint + Cg

CMOS Inverter with single O/P Capacitance

 Problem of analysing the switching behaviour can be handled more easily using this single lumped
O/P capacitance.
 Question of inverter transient response is reduced to finding the charge-up and charge-down times of a
single capacitance which is charged and discharged through one transistor.
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Delay – Time Definitions

 Propagation delay times ГPHL andГPLHdetermine the I/P-to-O/P signal delay during the high-to-low
and low-to-high transitions of the O/P, respectively.
 ГPHL is the time delay between the V50%-transition of the rising input voltage and the V50%-transition
of the falling output voltage or time required for the output voltage to fall from VOH to the V50% level
or it is ГPHL = t1 - t0
 ГPLH is the time delay between the V50%-transition of the falling input voltage and the V50%-transition
of the rising output voltage or the time required for the output voltage to rise from VOL to the V50%
level or it is ГPLH = t3 - t2
 The voltage point V50% is defined as follows.
V50% = VOL + ½ (VOH - VOL) = ½ (VOL + VOH)

 Average Propagation Delay Гp of the inverter characterizes the average time required for the input
signal to propagate through the inverter.

 The voltage level V10% and V90% is defined as

V10% = VOL + 0.1 . (VOH - VOL)
V90% = VOL + 0.9 . (VOH - VOL)
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Rise time and Fall time of O/P Voltage

 Гrise = rise from the V10% level to V90% level or tD - tC.

 Гfall = fall from the V90% level to V10% level or tB - tA.

Calculation of Delay : Average Current Method

 Calculation of propagation delays is Based on estimating the average capacitance current during
charge down and charge up.
 The delay times are found as:-

Where, Iavg is the constant average current from capacitor during an output transition.
 Average current during high-to-low transition can be calculated by using the current values at starting
and end of transition :-
Iavg, HL = ½ [ic (Vin = VOH, Vout = VOH) + ic (Vin = VOH, Vout = V50%)]
 Similarly, Average current during low-to-high transition:-
Iavg, LH = ½ [ic (Vin = VOL, Vout = V50%) + ic (Vin = VOL, Vout = VOL)]
Limitations of Average current method
 While the average-current method is relatively simple and requires minimal calculation, it neglects the
variations of capacitance current between the beginning and end points of the transition.
 So, we do not expect the average-current method to provide a very accurate estimate of the delay
times.
 Still, this approach can provide rough, first-order estimates of the charge-up and charge-down delay
times.
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Calculation of Delay–Times: Differential Method

 The propagation delay times can be found more accurately by solving the state equation of the output
node in the time domain.
 The differential equation associated with the output node is given below.
 See the capacitance current is also a function of the O/P voltage and is given by :-

 First, we consider the rising-input case for a CMOS inverter. Initially the output voltage is assumed to
be equal to VOH.
 Now, VOL VOH, nMOS is turned on, and it discharges the load capacitance
o iD,p = 0, as pMOS is switched off
 The differential equation describing the discharge event is then

 The, input and output voltage waveforms

during this high-to-low transition.
 First, consider the nMOS transistor operating
in saturation.
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 As, Saturation current is independent of the output voltage so solution in this time interval (t0 to t1’) is.

 Evaluating this simple integral yields

 At t = t', the output voltage will be equal to (VDD - VTn) and the transistor will be at the saturation-
linear region boundary.
 Now, consider the nMOS transistor operating in the linear region.

 The solution of discharge event in the time interval between t1' and t1 can be found as

 Evaluating this simple integral yields

 Note that tdelaycorresponds to the propagation delay time ГPHLfor falling output.

 Finally, the propagation delay time for high-to-low output transition (ГPHL)can be found by combining
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 For VOH = VDD and VOL= 0, as is the case for the CMOS inverter,

 In a CMOS inverter, the charge-up event of the output load capacitance for falling input transition is
completely analogous to the charge-down event for rising input.
 When going from VOH to VOL; nMOS = cut off and the load capacitance is being charged up through
the pMOS transistor.
 Now, the propagation delay time ГPLH can be found as

 For VOH = VDD and VOL = 0, then

Conditions for balanced propagation delays

 Finally delay-time is given by:

 After, Comparing the delay expression, we can see that the sufficient conditions for balanced
propagation delays, i.e., for ГPHL= ГPLHin a CMOS inverter are:
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Delay time for non-ideal I/P pulse waveform

Example: Consider the CMOS inverter circuit shown below, with VDD = 3.3 V. The I-V characteristics of
the nMOS transistor are specified as follows: when VGS= 3.3 V, the drain current reaches its saturation
level Isat= 2 mA for VDS2.5 V. Assume that the I/P signal applied to the gate is a step pulse that switches
instantaneously from 0 V to 3.3 V. Using the data above, calculate the delay time necessary for the output
to fall from its initial value of 3.3 V to 1.65 V, assuming an output load capacitance of 300 fF.
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Solution:
• Assuming that the nMOS transistor operates in saturation from t = 0 to t = t1’= tsat, and that it will
operate in the linear region from t = t1’= tsat to t = t2= tdelay.
• The current equation for the saturation region can be written as:

• We can calculate the amount of time in which the nMOS transistor operates in saturation (t sat), by
integrating this equation

• The transconductance knof the nMOS transistor can be found as follows:

• Now, the current equation for the linear operating region is

• Integrating this differential equation between the two voltage boundary conditions yields the time in
which the nMOS transistor operates in the linear region during this transition.

• Thus, the total delay time is found to be tdelay = 120 + 133 = 253 ps
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Lecture-30

Power dissipation and its analysis for CMOS inverter

Applications of Power Dissipation
• In newer technologies power consumption is a primary design constraint
• In some applications low power consumption is more important than performance:
 Mobile communications
 Mobile computing
 Wireless Internet
 Medical implants
 Deep space applications

Need to estimate power dissipation

Power dissipation affects
• Performance
• Reliability
• Packaging
• Cost
• Portability
Where Does Power Go in CMOS?
 Static Power: Due to DC current drawn from power supply
 Dynamic Power Consumption:Charging and Discharging Capacitors
 Short Circuit Currents: Short Circuit Path between Supply Rails during Switching
 Leakage:Leaking diodes and transistorsStatic Power dissipation

Static Power dissipation

 Static power dissipation is defined for VLSI circuit in static condition i. e. for steady-state condition
when O/P is either in logic ‘1’ or ‘0’ state.
 It is also called as DC power dissipation.
 The DC power dissipation of an inverter circuit:-

 Now, DC current drawn by the inverter circuit may vary depending on the input and output voltage
levels.
 Assume input voltage level corresponds to logic "0“ during 0% of the operation time and to logic " 1
" during the other 50%, the overall DC power consumption of the circuit:-
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Static Power dissipation for Resistive load inverter

Static Power dissipation for CMOS Inverter

 Since the CMOS inverter does not draw any significant current from the power source in both of its
steady-state operating points (Vout = VOH and Vout = VOL), the DC (STATIC) power dissipation of this
circuit is almost negligible.
 The drain current that flows through the nMOS and the pMOS transistors in both cases is essentially
limited to reverse leakage current of source and drain and in short-channel MOSFETs, the relatively
small subthreshold and gate leakage currents.
 So, CMOS is preferred for low power consumption applications.

Dynamic (Switching) Power Consumption

 During switching events where the output load capacitance is alternatingly charged up and charged
down,, the CMOS inverter dissipates power, which is called as dynamic power consumption of the
CMOS inverter
 Consider the simple CMOS inverter circuit
Dynamic Power Dissipation of CMOS Inverter

Fig.: I/P and O/P voltage waveforms and the expected load capacitor current waveform of CMOS
Inverter
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 When I/P voltage switches from Low to High; pMOS= off and nMOS = ON; so O/P load capacitance
Cload is being discharged through the nMOS transistor. So, Capacitor current is equal to drain current
of nMOS transistor (i.e. Icap = ID, n).
 When I/P coltage switches from High to Low; nMOS= off and pMOS = ON; so output load
capacitance Cload is being charged-up through the pMOS transistor. So, Capacitor current is equal to
drain current of pMOS transistor (i.e. Icap = ID, p).
 Assuming periodic I/P & O/P waveforms, average dynamic power dissipated by any device over one
period is :-

 Since during switching, the nMOS transistor and the pMOS transistor in a CMOS inverter conduct
current for one-half period each, the average power dissipation of the CMOS inverter is equivalent to
the charge up and charge down of load capacitor.

 Evaluating the integrals

 Now, f= 1/T, this expression can also be written as:

 Here, we will see that average power dissipation of the CMOS inverter is proportional to the switching
frequency f, so the low-power advantage of CMOS circuits becomes less prominent in high-speed
operation.
 Average power dissipation is independent of all transistor characteristics and transistor sizes
 Also, the switching delay times have no relevance to the amount of power consumption during the
switching events. Because switching power is solely dissipated for charging and discharging the
output capacitance from VOL to VOH, and vice versa
 Because of this reason, the switching power expression derived for the CMOS inverter also applies to
all general CMOS circuits.
 The analysis of switching power dissipation presented above is based on the assumption that the
output node of a CMOS gate undergoes one power-consuming transition (0-to-VDD transition) in each
clock cycle, but this is not correct as node transition rate can be slower than the clock rate. So, we will
introduce αT (node transition factor), which is the effective number of CMOS Logic power-consuming
voltage transitions experienced per clock cycle.
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 The average Circuits switching power consumption becomes:-

Effect of Internal nodes on Dynamic Power

 During switching, internal circuit node also have voltage transitions. These internal nodes also
contribute to the overall power dissipation, due to the parasitic capacitances associated with each
internal node.
 The generalized expression for the average switching power dissipation is:-

where Ci, represents the parasitic capacitance associated with each node in the circuit (including the
output node) and αTi, represents the corresponding node transition factor associated with that node.

Reduction of Dyn. Power Consumption

 The generalized expression for the average switching power dissipation is:-

 Factors responsible for power reduction

1. Reduction of the power supply voltage VDD,
2. Reduction of the voltage swing in all nodes,
3. Reduction of the switching probability (transition factor) and
4. Reduction of the load capacitance.

Short-Circuit Power Dissipation

 The current component which passes through both the nMOS and the pMOS devices during switching
does not contribute to the charging of the capacitances in the circuit, and hence, it is called the short-
circuit current component.
 This component is especially prevalent if the output load capacitance is small, and/or if the input
signal rise and fall times are large
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Leakage Power Dissipation

• Four main leakage current components in a MOSFET:-
1. The reverse diode leakage occurs when the pn-junction between the drain and the bulk of the
transistor is reverse-biased.
2. Subthreshold current, which is due to carrier diffusion between the source and the drain regions of
the transistor in weak inversion.
3. Gate-induced drain leakage (GIDL), which occurs under gate and drain overlap area where the
doping density higher than 1*1019 cm-3.
4. Gate leakage, which occurs due to quantum-mechanical tunneling of electrons through thin gate
oxide.
Leakage Power Dissipation – pn Junction
• The reverse leakage current of a pn junction is expressed by

where Vbiasis the reverse bias voltage across the junction, Jsis the reverse saturation current density and
the A is the junction area.

Leakage Power Dissipation – subthreshold current

• The subthreshold leakage current can occur even when there is no switching activity in the circuit and
that this component must be carefully considered for estimating the total power dissipation in the
stand-by operation mode.

• To limit the subthreshold current component - Avoid very low Vth

• The total power dissipation in CMOS digital circuits can be expressed as the sum of four components,

where Ishort-circuitdenotes the average short-circuit current, Ileakagedenotes the reverse leakage and
subthreshold leakage currents, and Istaticdenotes the current component drawn from the power supply.

• The switching power dissipation, which is the first term is the dominating component in most CMOS
logic gates.
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Lecture-31
Combinational Logic, NAND Gate, NOR gate, XOR gate (complex logic circuits)

CMOS COMPOUND GATES

 These are formed by combining series and parallel structures of transistors.
 There are two important subsets of the general complex CMOS gate topology.
1. AND-OR-INVERT (AOI)
2. OR – AND-INVERT (OAI)

AND-OR-INVERT (AOI)
 It enables the sum-of-products realization of a Boolean function in one logic stage.
 The pull-down net of the AOI gate consists of parallel branches of series-connected nMOS driver
transistors and the corresponding p-type pull-up network can simply be found using the dual-graph
concept.

OR-AND-INVERT (OAI)
 It on the other hand, enables the product-of-sums realization of a Boolean function in one logic stage.
 The pull-down net of the OAI gate consists of series branches of parallel-connected nMOS driver
transistors.
 The corresponding p-type pull-up network can be found using the dual-graph concept.
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Example 1
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Example2

Circuit topology:
 N and P devices with sources and drains connected in parallel.
 Vg is the control signal for the N device;
 Vgc (complement of Vg) is the control signal for the P device.

Operation:
 When Vg is high (at Vdd) and Vgc is therefore low (at Gnd), the NFET and PFET are both ON. The
switch is therefore CLOSED and Vout will be the same logic level as Vin.
 When Vg is low (at Gnd) and Vgc is high (at Vdd), both devices are OFF. The switch is therefore
OPEN and Vout will be independent of Vin (high Z connection).
 General Combinational Logic Circuit
 Here, Inputs (V1,V2,..) are represented by node voltages.
 The Boolean (or logic) value of " 1 " = VDD,
 The Boolean (or logic) value of "0" = low voltage of 0.
 In output there is a capacitance CL, which represents the combined parasitic device capacitances in the
circuit and the interconnect capacitance components seen by the output node.
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Two-Input NOR Gate

CMOS NOR2 (Two-Input NOR) Gate

 At every point in time (except during the switching transients) each gate output is connected to either
VDD or VSS via a low-resistive path.
 The outputs of the gates assume at all times the value of the Boolean function, implemented by the
circuit (ignoring, once again, the transient effects during switching periods).
 This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on
the capacitance of high impedance circuit nodes.
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 Here, we see circuit consists of a parallel-connected n-net and a series-connected complementary p-

net.
 Input voltage VA and VB

 When either one or both inputs are high, i.e., when the n-net creates a conducting path between the
output node and the ground, the p-net is cut-off.
 On the other hand, if both input voltages are low, i.e., the n-net is cut-off, then the p-net creates a
conducting path between the output node and the supply voltage VDD.
 A DC current path between the VDD and ground is not established for any of the input combinations.

CMOS NAND2 (Two-Input NAND) Gate

 The operating principle of this circuit is the exact dual of the CMOS NOR2 operation
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CMOS XOR GATE

For Pull-Up network, we have to take inverse of whole expression. So,

For Pull-Down network, we will take the same expression.

Now, apply the same rules of designing and we will get CMOS XOR circuit
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Lecture-32
Compound Gates, 2 input CMOS Multiplexer using CMOS

Complex Logic Circuits

Inspection of the circuit topology reveals the simple design principle of the pull-down network:
* OR operations are performed by parallel-connected drivers.
* AND operations are performed by series-connected drivers.
* Inversion is provided by the nature of MOS circuit operation.

 Each input variable is assigned to only one driver.

 For the analysis and design of complex logic gates, we can employ the equivalent inverter approach : -

 if all input variables are logic-high, the equivalent-driver(W/L) ratio of the pull-down network
consisting of five nMOS transistors is

 For calculating the logic-low voltage level VOL we have to consider various cases, since the value of
VOL actually depends on the number and the configuration of the conducting nMOS transistors in
each case.
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To realize complex functions of multiple input variables, the basic circuit structures and design principles
developed for NOR and NAND can be extended to complex logic gates. The ability to realize complex logic
functions, using a small number of transistors is one of the most attractive features of nMOS and CMOS logic
circuits. Consider the following Boolean function as an example.
Z=[P(S+T)+QR]’
The nMOS depletion-load complex logic gate used to realize this function is shown in figure. In this figure, the left
nMOS driver branch of three driver transistors is used to perform the logic function P (S + T), while the right-hand
side branch performs the function QR. By connecting the two branches in parallel, and by placing the load
transistor between the output node and the supply voltage VDD, we obtain the given complex function. Each input
variable is assigned to only one driver.

Inspection of the circuit topology gives simple design principles of the pull-down network −

 OR operations are performed by parallel-connected drivers.

 AND operations are performed by series-connected drivers.
 Inversion is provided by the nature of MOS circuit operation.
If all input variables are logic-high in the circuit realizing the function, the equivalent driver (W/L) ratio of the pull-
down network consisting of five nMOS transistors is
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 Each driver transistor in the pull-down network is shown by ai and each node is shown by a vertex
in the pull-down graph. Next, a new vertex is created within each confined area in the pull graph,
and neighboring vertices are connected by edges which cross each edge in the pull-down graph
only once. This new graph shows the pull-up network.
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2 : 1 MUX using transmission gate:

 This gate selects either input A or B on the basis of the value of the control signal 'C'.When control
signal C is logic low the output is equal to the input A and when control signal C is logic high the
output is equal to the input B.
 The 2 : 1 MUX selects either A or B depending upon the control signal C. This is equivalent to
implementing the Boolean function.
 F = (A  C + B  C bar)
 When the control signal C is high then the upper transmission gate is ON and it passes A through it so
that output = A.

 When the control signal C is low then the upper transmission gate turns OFF and it will not allow A to
pass through it, at the same time the lower transmission gate is 'ON' and it allows B to pass through it
so the output = B.
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Lecture-33
Memory latches and registers using CMOS
Logic circuits are divided into two categories − (a) Combinational Circuits, and (b) Sequential
Circuits.
In Combinational circuits, the output depends only on the condition of the latest inputs.
In Sequential circuits, the output depends not only on the latest inputs, but also on the condition of
earlier inputs. Sequential circuits contain memory elements.

Sequential circuits are of three types −

Bistable − Bistable circuits have two stable operating points and will be in either of the states.
Example − Memory cells, latches, flip-flops and registers.
Monostable − Monostable circuits have only one stable operating point and even if they are
temporarily perturbed to the opposite state, they will return in time to their stable operating point.
Example: Timers, pulse generators.
Astable − circuits have no stable operating point and oscillate between several states. Example −
Ring oscillator.
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CMOS Logic Circuits

SR Latch based on NOR Gate

If the set input (S) is equal to logic "1" and the reset input is equal to logic "0." then the output Q
will be forced to logic "1". While Q¯ is forced to logic "0". This means the SR latch will be set,
irrespective of its previous state.
Similarly, if S is equal to "0" and R is equal to "1" then the output Q will be forced
to "0" while Q¯ is forced to "1". This means the latch is reset, regardless of its previously held state.
Finally, if both of the inputs S and R are equal to logic "1" then both output will be forced to
logic "0" which conflicts with the complementarity of Q and Q¯.
Therefore, this input combination is not allowed during normal operation. Truth table of NOR based
SR Latch is given in table.

S R Q Q¯ Operation

0 0 Q Q¯ Hold

1 0 1 0 Set

0 1 0 1 Reset

1 1 0 0 Not allowed
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CMOS SR latch based on NOR gate is shown in the figure given below.

If the S is equal to VOH and the R is equal to VOL, both of the parallel-connected transistors M1
and M2 will be ON. The voltage on node Q¯ will assume a logic-low level of VOL = 0.
At the same time, both M3 and M4 are turned off, which results in a logic-high voltage VOH at
node Q. If the R is equal to VOH and the S is equal to VOL, M1 and M2 turned off and M3 and M4
turned on.
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SR Latch based on NAND Gate

Block diagram and gate level schematic of NAND based SR latch is shown in the figure. The small
circles at the S and R input terminals represents that the circuit responds to active low input signals.

S R Q Q′

0 0 NC NC No change. Latch remained in present

state.

1 0 1 0 Latch SET.

0 1 0 1 Latch RESET.

1 1 0 0 Invalid condition.
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If S goes to 0 (while R = 1), Q goes high, pulling Q¯ low and the latch enters Set state
S = 0 then Q = 1 (if R = 1)
If R goes to 0 (while S = 1), Q goes high, pulling Q¯ low and the latch is Reset
R = 0 then Q = 1 (if S = 1)
Hold state requires both S and R to be high. If S = R = 0 then output is not allowed, as it would
result in an indeterminate state. CMOS SR Latch based on NAND Gate is shown in figure.

Depletion-load nMOS SR Latch based on NAND Gate is shown in figure. The operation is similar
to that of CMOS NAND SR latch. The CMOS circuit implementation has low static power
dissipation and high noise margin.
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Clocked SR Latch
The figure shows a NOR-based SR latch with a clock added. The latch is responsive to inputs S and
R only when CLK is high.

When CLK is low, the latch retains its current state. Observe that Q changes state −

 When S goes high during positive CLK.

 On leading CLK edge after changes in S & R during CLK low time.
 A positive glitch in S while CLK is high
 When R goes high during positive CLK.

 two parallel transistors in tree P are ON, thus retaining state in the memory cell.
 When clock is high, the circuit becomes simply a NOR based CMOS latch which will
respond to input S and R.
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Clocked SR Latch based on NAND Gate

Circuit is implemented with four NAND gates. If this circuit is implemented with CMOS then it
requires 16 transistors.

 The latch is responsive to S or R only if CLK is high.

 If both input signals and the CLK signals are active high: i.e., the latch output Q will be set
when CLK = "1" S = "1" and R = "0"
 Similarly, the latch will be reset when CLK = "1," S = "0," and
When CLK is low, the latch retains its present state.
CMOS D Latch Implementation

The D latch is normally, implemented with transmission gate (TG) switches as shown in the figure.
The input TG is activated with CLK while the latch feedback loop TG is activated with CLK. Input
D is accepted when CLK is high. When CLK goes low, the input is opencircuited and the latch is
set with the prior data D.
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Clocked JK Latch

The figure above shows a clocked JK latch, based on NAND gates. The disadvantage of an SR latch is that
when both S and R are high, its output state becomes indeterminant. The JK latch eliminates this problem by
using feedback from output to input, such that all input states of the truth table are allowable. If J = K = 0, the
latch will hold its present state.
If J = 1 and K = 0, the latch will set on the next positive-going clock edge, i.e. Q = 1, Q¯ = 0
If J = 0 and K = 1, the latch will reset on the next positive-going clock edge, i.e. Q = 1 and Q¯ = 0.
If J = K = 1, the latch will toggle on the next positive-going clock edge
The operation of the clocked JK latch is summarized in the truth table given in table.

J K Q Q¯ S R Q Q¯ Operation

0 1 1 1 0 1
0 0 Hold
1 0 1 1 1 0

0 1 1 1 0 1
0 1 Reset
1 0 1 0 0 1

0 1 0 1 1 0
1 0 Set
1 0 1 1 1 0

0 1 0 1 1 0
1 1 toggle
1 0 1 0 0 1
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Lecture-34
Transmission Gate (TG), estimation of gate delays, Transistor sizing
Transmission Gates
 Transmission Gate is designed by connecting PMOS and NMOS devices together in parallel.
 These gates are quite different from conventional CMOS logic gates as the transmission gate is
symmetrical, or bilateral, that is, the input and output are interchangeable.
Need for Transmission gates:
 NMOS device only passes a strong “0” but a weak “1”, while the PMOS device passes a strong “1”
but a weak “0” resulting in a requirement of a basic bilateral CMOS switch.
 By combining the characteristics of the NMOS and the PMOS devices, it is possible to transmit
both a strong logic “0” or a strong logic “1” value in either direction without any degradation
forming the basis of a Transmission Gate.
 This bilateral operation is shown in the transmission gate symbol below which shows two
superimposed triangles pointing in opposite directions to indicate the two signal direction

CMOS Transmission Gate

 Two MOS transistors are connected back-to-back in parallel with an inverter used between the gate
of the NMOS and PMOS to provide the two complementary control voltages.
 When the input control signal, VC is LOW, both the NMOS and PMOS transistors are cut-off and
the switch is open.
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 When VC is high, both devices are biased into conduction and the switch is closed.
 Transmission gate acts as a “closed” switch when VC = 1, while the gate acts as an “open” switch when
VC = 0 operating as a voltage-controlled switch.
 The bubble of the symbol indicating the gate of the PMOS FET.
 The operation of a transmission gate using both a truth table and boolean expression can be defined as
follows

 Above truth table shows that the output at B relies not only the logic level of the input A, but also on the
logic level present on the control input.
 Logic level value of B is defined as both A AND Control giving us the boolean expression for a
transmission gate of:
B= A. Control
 Boolean expression of a transmission gate incorporates the logical AND function so this operation is
implemented using a standard 2-input AND gate with one input being the data input while the other is the
control input as shown.
 AND Gate Implementation


 A single NMOS or a single PMOS on its own can be used as a CMOS switch.
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 Combination of the two transistors in parallel has some advantages.An FET channel is resistive so the
ON-resistances of both transistors are effectively connected in parallel.
 As a FETs ON-resistance is a function of the gate-to-source voltage, VGS, as one transistor becomes less
conducting due to the gate drive, the other transistor takes over and becomes more conducting.
 Combined value of the two ON-resistances (as low as 2 or 3Ω) stays more or less constant than would be
the case for a single switching transistor on its own.

 Connecting a P-channel FET (PMOS) with an N-channel FET (NMOS), a solid-state switch can be
created which is digitally controlled using logic level voltages and is commonly called a “transmission
gate”.
 The Transmission Gate, (TG) is a bilateral switch where either of its terminals can be the input or the
output.
 Along with the input and output terminals, the transmission gate has a third connection called the control,
where the control input determines the switching state of the gate as an open or closed (NO/NC) switch.
 This input is typically driven by a digital logic signal that toggles between ground (0V) and a set DC
voltage, usually VDD.
 When the control input is low (Control = 0), the switch is open, and when the control input is HIGH
(Control = 1) the switch is closed.
 Transmission gates act like voltage-controlled switches, and being switches, CMOS transmission gates
can be used for switching both analogue and digital signals passing the full range of voltages (from 0V
to VDD) in either direction, which as discussed is not possible with a single MOS device.
 The combination of an NMOS and a PMOS transistor together within a single gate means that the
NMOS transistor will transfer a good logic “0” but a poor logic “1”, while the PMOS transistor transfers
a good logic “1” but a poor logic “0”.
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 Connecting an NMOS transistor with a PMOS transistor in parallel provides a single bilateral switch
which offers efficient output drive capability for CMOS logic gates controlled by a single input logic
level.
 Transmission Gate Model

Logic 1 transfer:

with

Logic 0 transfer:

CMOS transmission gate

Ways to Improve Gate Delay

tp ≈ (tpHL tpLH) ≈ [CL ÷ (k’ W/L VDD)]

Reduce CL

• internal diffusion capacitance of the gate itself (keep the drain diffusion as small as possible)

• other terms: interconnect capacitance & fanout

Increase W/L ratio of the transistor

• the most powerful and effective performance optimization tool in the hands of the designer

• watch out for self-loading! – when the intrinsic capacitance dominates the extrinsic load Increase VDD

Increasing VDD

 can trade-off energy for performance

 increasing VDD above a certain level yields only very minimal improvements
 reliability concerns enforce a firm upper bound on VDD
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The sizing of the transistor can be done using RC delay approximation. The RC Delay Model helps in delay
estimation CMOS circuit. The RC delay model treats the non-linear transistor current-voltage I-V and
capacitor voltage C-V characteristics with their equivalent resistance and capacitance model. This RC delay
model approximates a transistor as a switch with a series of resistance or effective resistance R (Which is the
ratio of the average value of Vds to Ids). The size of a unit transistor is approximated as 4/2 lambda. The RC
circuit equivalent models for the PMOS and NMOS transistors are shown below.
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Here the k width of both PMOS and NMOS transistors is contacted to Source S and drain D. Since the holes
in PMOS have lower mobility compared to electrons in the NMOS transistors, the PMOS will have twice the
resistance of the NMOS. The n-well is usually tied with the High voltage because the capacitors of PMOS are
shown with the VDD as their second terminal in the figure shown above. Similarly in nMOS, the capacitors
are connected to ground because usually p-well will be connected to lower supply.

1. The NMOS transistor which is having k times of width will have the resistance of R/k.

2. Similarly, A unit PMOS transistor which is having the k times of width will have the resistance
of 2R/k.

This is because of PMOS transistor will have greater resistance compared to the NMOS transistor because its
mobility is less. The value of R will be typically on the order of 10kOhm for a single transistor. Let us
understand the concept of transistor sizing with an example.

Given the logic function Y = A ( B + C ) + D E and asked to size the PMOS and NMOS transistors.
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PMOS sizing:

For a unit PMOS transistor, the effective resistance with the width k is given by 2R/k.
By looking at the pull-up network in the above circuit, we should find out the worst-case or the longest path to
VDD. In the above network, the path E-C-B is the longest path. So we can write the
equation (2R/k)+(2R/k)+(2R/k) = R, where R is the effective resistance. The equation gives the value of k = 6.
Therefore the k value transistors E, C, and B will be 6.

One more path D-C-B also contributes to the worst-case or longest path, So the k value of the transistor D also
becomes 6. The transistor A is equivalent to two transistors B and C (by looking at the circuit). Therefore we can
write 2R/k = 2 * 2R/6 Since we know the k values of B and C transistors.
Therefore the k value of transistor A is 3.

NMOS sizing:

For a unit NMOS transistor, the effective resistance with the width k is given by R/k.
In the above network, the worst-case or the longest path can be seen is with two transistors. (The paths A-B, A-
C, and D-E). So we can write the relation 2 * R/k = R, So the value of k of all the NMOS transistors will be 2
since all are in the longest path.
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Lecture-35
Basic physical design of simple Gates and Layout issues, Layout issues for
CMOS inverter
Layout Designing Guidelines:
Run VDD and VSS in metal at the top and bottom of the cell
• Run a vertical poly line for each gate input
• Order the poly gate signals to allow the maximal connection between transistors via abutting source-drain
connection.
• Place n-gate segments close to VSS and p-gate segments close to VDD
• Connection to complete the logic gate should be made in poly, metal, or, where appropriate, in diffusion
Logic Gates Design Issues
• Hierarchical design

− Architecture level
− RTL/logic gate level
− Circuit level
− Layout level

• Critical paths – the path with the longest delay that require attention to timing details

• The number of Fanins and Fanouts affects the performance of the circuits

CMOS inverter
A complementary CMOS inverter is implemented as the series connection of a p-device and an n-device. The
source and the substrate (body) of the p -device is tied to the VDD rail, while the source and the substrate of
the n-device are connected to the ground bus. Thus, the devices do not suffer from anybody effect. To derive
the DC transfer characteristics for the CMOS inverter, which depicts the variation of the output
voltage (Vout) as a function of the input voltage (Vin)(Vin), one can identify five following regions of
operation for the n -transistor and p -transistor.
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Placement of one nMOS and one pMOS transistor.

Complete mask layout of the CMOS inverter.

Lecture-36
Layout for NAND, NOR and Complex Logic gates

LAYOUT DESIGNING

 Basic mask layout design guidelines for CMOS logic gates

 The design of physical layout linked to overall circuit performance (area, speed, power dissipation)
 Physical structure directly determines the transconductances of the transistors,
 The parasitic capacitances and resistances,
 The detailed mask layout of logic gates requires a very intensive and time-consuming design effort,
 Automated layout generation (e.g., standard cells + computer-aided placement and routing
 Mask layout drawings must strictly conform to a set of layout design rules
 The stick diagrams, to simplify the overall topology of layout in the early design phases.

All complex gates can be designed using a single row of N-transistors and a single row of P transistors,
Aligned at common gate connections
• Design procedure
− Draw two dual graphs to P transistor tree and N transistor tree
− Find all Euler paths that cover the graph
− Find a P and an N Euler path that have identical labeling
− If not found, break the gate in the minimum numbers of places to achieve design

NMOS Gate CONSTRUCTION

Layout of CMOS NAND and NOR

Steps required for generating the mask layout of a CMOS NAND2 gate.

Complex CMOS Logic Gates

The realization of complex Boolean functions requires a series-parallel network of nMOS transistors
which constitute the so-called pull-down net, and a corresponding dual network of pMOS transistors
which constitute the pull-up net. Once the network topology of the nMOS pull- down network is known,
the pull-up network of pMOS transistors can easily be constructed by using the dual-graph concept.

A complex CMOS logic gate realizing a Boolean function with 5 input variables.
Stick Diagram layout of the complex CMOS logic gate
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Lecture-37
Layout of TG, Layout optimization using Euler path
Euler-path method

Simply find a Euler path in the pull-down network graph and a Euler path in the pull-up network graph
with the identical ordering of input labels, i.e., find a common Euler path for both graphs. The Euler path
is defined as an uninterrupted path that traverses each edge (branch) of the graph exactly once. Figure 3.12
shows the construction of a common Euler path for both graphs in our example. Finding a common Euler
path in both graphs for the pull-down and pull-up net provides a gate ordering that minimizes the number
of active-area breaks. In both cases, the Euler path starts at (x) and ends at (y).

Optimized stick diagram layout of the complex CMOS logic gate.

It is seen that there is a common sequence (E-D-A-B-C) in both graphs. The polysilicon gate columns can
be arranged according to this sequence, which results in uninterrupted active areas for nMOS as well as
for pMOS transistors. The stick diagram of the new layout is shown in Fig. . In this case, the separation
between two neighboring poly columns must allow only for one metal-diffusion contact. The advantages
of this new layout are more compact (smaller) layout area, simple routing of signals, and correspondingly,
smaller parasitic capacitance.
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Circuit diagram of the CMOS one-bit full adder.

the circuit diagram of a CMOS one-bit full adder. The circuit has three inputs, and two outputs, sum and
carry_out. The corresponding mask layout of this circuit is given in Fig. 3.15. All input and output signals
have been arranged in vertical polysilicon columns. Notice that both the sum-circuit and the carry-circuit
have been realized using one uninterrupted active area each.

Mask layout of the CMOS full adder circuit..

Lecture-38
DRC rules for layout and issues of interconnects, Latch up problem

Layout Design Rules

The design rules primary address two issues:

1. The geometrical reproduction of features that can be reproduced by
the mask making and lithographical process ,and
2. The interaction between different layers.

There are primarily two approaches in describing the design rules.

1. Linear scaling is possible only over a limited range of dimensions.

2. Scalable design rules are conservative .This results in over dimensioned and less dense design.

1. Scalable Design Rules (e.g. SCMOS, λ-based design rules):

In this approach, all rules are defined in terms of a single parameter λ. The rules are so chosen that a
design can be easily ported over a cross section of industrial process ,making the layout portable
.Scaling can be easily done by simply changing the value of.
The key disadvantages of this approach are:

2. Absolute Design Rules (e.g. μ-based design rules ) :

In this approach, the design rules are expressed in absolute dimensions (e.g. 0.7 μm) and therefore can
exploit the features of a given process to a maximum degree. Here, scaling and porting is more
demanding, and has to be performed either manually or using CAD tools .Also, these rules tend to be
more complex especially for deep submicron.
The fundamental unity in the definition of a set of design rules is the minimum line width .It stands for
the minimum mask dimension that can be safely transferred to the semiconductor material .Even for the
same minimum dimension, design rules tend to differ from company to company, and from process to
process. Now, CAD tools allow designs to migrate between compatible processes.
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Layer Representations

With increase of complexity in the CMOS processes, the visualization of all the mask levels that are
used in the actual fabrication process becomes inhibited. The layer concept translates these masks to a
set of conceptual layout levels that are easier to visualize by the circuit designer. From the designer's
viewpoint, all CMOS designs have the following entities:

 Two different substrates and/or wells: which are p-type for NMOS and n-type for PMOS.
 Diffusion regions (p+ and n+): which defines the area where transistors can be formed. These regions
are also called active areas. Diffusion of an inverse type is needed to implement contacts to the well or
to substrate.These are called select regions.
 Transistor gate electrodes : Polysilicon layer
 Metal interconnect layers
 Interlayer contacts and via layers.

The layers for typical CMOS processes are represented in various figures in terms of:

 A color scheme (Mead-Conway colors).

 Other color schemes designed to differentiate CMOS structures.
 Varying stipple patterns
 Varying line styles

Mead Conway Color coding for layers.

layer representations for CMOS inverter using above design rules is shown below-

CMOS Inverter Layout Figure

Lecture-39

Dynamic CMOS circuits, PE (pre-charge and Evaluation) Logic

Dynamic logic circuits v/s Static logic circuits

Static logic circuits

 Static logic circuits may require a large number of transistors to implement a function and may cause a
considerable time delay while dynamic circuits provide more compact designs with faster switching
speeds and reduced power consumption.
 Static logic circuits may require a large number of transistors to implement a function and may cause a
considerable time delay while dynamic circuits provide more compact designs with faster switching
speeds and reduced power consumption.
 Switching speed of static circuits is limited by two factors:
 Current conduction level through a MOSFET
 Parasitic capacitances in the network.
 Instead of fighting the time constant limits induced by the RC parasitics, the presence of capacitances
is accepted.

Dynamic logic circuits

 The operation of dynamic logic gates depends on temporary storage of charge in parasitic node
capacitances.
 A dynamic CMOS circuit technique helps in reducing the number of transistors used to implement any
logic function.
 It works in two phases:
1. Precharge:
Output node capacitance is precharged.
2. Evaluate:
Output voltage level is evaluated according to the applied inputs.
 Both of these operations are scheduled by a single clock signal.
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Dynamic CMOS Circuits

During the precharge phase ( Clock = 0),

 output node of the dynamic CMOS stage is precharged to a high logic level,
 Out is precharged to VDD by Mp. Me is turned off, no dc current flows (regardless of input values)
 output of the CMOS inverter becomes low.
During the evaluate phase ( Clock = 1),
 output node of the dynamic CMOS stage is either discharged to a low level through the nMOS
circuitry (1 to 0 transition), or it remains high.
 Me is turned on, Mp is turned off. Output is pulled down to zero depending on the values on the
inputs. If not, precharged value remains on CL.
 inverter output voltage can also make at most one transition during the evaluation phase, from 0 to 1.

Regardless of the input voltages applied, it is not possible for the inverter output to make a 1 to 0 transition
during the evaluation phase.

When the clock signal is low (precharge phase),

pMOS precharge transistor MP conducts

nMOS evaluate transistor Me is off.
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 The parasitic output capacitance of the circuit is charged upto a logic-high level of Vout = VDD.
 The input voltages are also applied during this phase, but they have no influence yet upon the
output level since Me is turned off.

 When the clock signal becomes high (evaluate phase),

Precharge transistor Mp turns off
Evaluate transistor Me turns on.
 The output node voltage may now remain at the logic high level or drop to a logic low, depending
on the input voltage levels. The final discharged output level depends on the time span of the
evaluation phase.
 If the input signals create a conducting path between the output node and the ground, the output
capacitance will discharge to 0 V.
 Otherwise, Vout remains at VDD.
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Lecture-40

Clocked CMOS (C2MOS) logic

Clocked-CMOS (C2MOS) is a logic family that combines static logic design with the
synchronization achieved by using clock signals. ... In modern design, the technique is still useful in
certain applications, such as dynamic “NORA” circuits. Figure show the general structure of a
C2MOS logic gate.

Clocked-CMOS (C2MOS) is a logic family that combines static logic design with the
synchronization achieved by using clock signals. In the early days of CMOS, many SSI and MSI
chips were based on C2MOS In modern design, the technique is still useful in certain applications,
such as dynamic “NORA” circuits.
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Figure show the general structure of a C2MOS logic gate. The inputs A, B, and C are connected to
complementary nFET/pFET pairs as in ordinary static design where they act like open or closed
switches. The only modification is the insertion of two clocked FETs between the logic arrays and the
output. Mp is controlled by ϕ¯and separates the pFET logic block and Cout while Mn is controlled
by ϕ and serves the same function for the nFET logic block. The operation of the gate can be
understood by effects of the clock ϕ(t)ϕ(t).

When the clock is at a level of ϕ=1ϕ=1 as in Figure (a), both Mn and Mp are biased active. This
connects both logic arrays to the output node, and the gate degenerates to its static equivalent circuit;
the main difference are longer switching times due to the additional parasitics. After the transients
have decayed, the output capacitor Cout will be charged to a voltage Vout=0 orVout=VDD. Figure
(b) shows the circuit when ϕ=0and both Mn and Mp are in cutoff. This isolates the output node from
both logic arrays and the value of Vout=VResult is held on Cout. However, a moment's reflection
will verify that this is identical to the problem of maintaining charge on a capacitive node using an
OFF transmission gate, so that the value of Vout will change in time. The result is only valid for the
hold time tH, which is an important characteristic of this type of circuit.
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Since C2MOS is based on static logic, it is a simple matter to design an entire family of gates with the
same characteristics. Examples of these are the NAND2 gate in Figure (a) and the NOR2 gate in Figure
(b). In principle, any AOI or OAI logic circuit may be created using the formalism. However, since the
additional delay introduced by the clocking FETs cannot be eliminated, the logic family is automatically
limited to slower systems

A variation of C2MOSC2MOS latch is shown in Figure. This uses a static inverter between two clocked
circuits as the second stage to produce the output, which is not a tri-state node. This allows for the output
to be taken at any time. The third stage circuit (which is the second C2MOS inverter in the chain) is now
being used to provide clocked controlled feedback.

C2MOS logic provides a straightforward approach to synchronizing data flow while maintaining static
logic ideas.
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Lecture-41

Domino logic circuit

 Problem in cascading conventional dynamic CMOS stages occurs when one or more inputs of a
stage make a 1 to 0 transition during the evaluation phase.
 If we build a system by cascading domino CMOS logic gates, all input transistors in subsequent
logic blocks will be turned off during the precharge phase, since all inverter outputs are equal to
0.
 During the evaluation phase, each inverter output can make at most one transition (from 0 to 1),
and thus each input of all subsequent logic stages can also make at most one transition(0 to 1).
 In a cascade structure consisting of several such stages, the evaluation of each stage ripples the
next stage evaluation, similar to a chain of dominos falling one after the other.
 The structure is hence called domino CMOS logic.
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Lecture-42

NORA CMOS Logic (NP-Domino Logic)

In domino logic, an inverter is required to connect, while NORA logic consist of alternating nMOS and
pMOS stages, as shown in following figure-

 The precharge and evaluate timing of nMOS logic stage is accomplished by clock signal ‘Ф’
while pMOS logic stages are controlled by ϕ .
Operation
 When Ф=0, the output nodes of nMOS logic blocks are precharge to VDD through pMOS
precharge transistor, whereas the output nodes of pMOS logic blocks are pre-charged to 0V
through the nMOS discharge transistor, driven by Ф.
 When Ф=1, all cascaded nMOS and pMOS logic stages evaluate one after the other.

 Advantages of NORA CMOS logic:

1. No requirement of static CMOS inverter at the output of every dynamic logic stage.
2. Direct coupling of logic blocks is done by alternating nMOS and pMOS logic blocks.
3. It allows pipelined system architecture.
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NORA logic is also compatible with domino CMOS logic.

1. Outputs of NORA nMOS logic blocks can be inverted, and then applied to the input of a
domino CMOS block, which is also driven by the clock signal .
2. Buffered output of a domino CMOS stage can be applied directly to the input of a NORA
nMOS stage.
Consider an nMOS-pMOS logic sequence and a clocked CMOS (C2MOS) output buffer.
 When the clock is low
All stages of circuit perform the precharge- discharge operation.
 When the clock is high
All stages of circuit evaluate output levels
 This circuit is also called φ-section,meaning that evaluation occurs during active φ.
 In next circuit, signals φand φhave been interchanged.
When the clock is high:
All logic stages perform the precharge-discharge operation
When the clock is high:
All stages evaluate output levels when the clock is low.
This circuit is called φ section meaning that evaluation occurs during active φ .
 A pipelined system can be constructed by simply cascading alternating φ and inverse φ sections.
 All logic stages in one section are evaluated during the same clock cycle. When the clock is low,
φsections in the pipelined system undergo the precharge cycle, while the φ sections undergo
evaluation.
 When the clock signal changes from low to high, φsections start the evaluation cycle, while the
φ sections undergo precharge.
 Consecutive sets of input data can be processed in alternating sections of the pipelined system.
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NORA CMOS -section; evaluation occurs during φ = 0

• As in all dynamic CMOS structures, NORA CMOS logic gates also suffer from charge sharing
and leakage.
• To overcome the dynamic charge sharing and soft- node leakage problems in NORA CMOS
structures, a circuit technique called Zipper CMOS can be used.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

Lecture-43
Zipper CMOS logic

 Zipper logic is a scheme for improving charge leakage and charge sharing problems.
 Identical to NORA except the clock signals.
 It receives a slightly different clock signals for the pre-charge (discharge) transistors and for pull
down (pull up) transistors.
 Clock signals which drive pMOS precharge and nMOS discharge transistors, allow the transistors
to remain in weak conduction or in cutoff during evaluate phase, thus compensating for charge
sharing and charge leakage problems.
 pMOS pre-charge transistors gates are held at Vdd - |Vtp|
 nMOS pre-charge transistors gates are held at Vtn above GND.

Clock signals of the Zipper CMOS architecture

Lecture-44

Basic memory circuit

Memory is the best essential element of a computer because computer can’t perform simple tasks. The
performance of computer mainly based on memory and CPU. Memory is internal storage media of
computer that has several names such as majorly categorized into two types, Main memory and
Secondary memory.

1. Primary Memory / Volatile Memory.

2. Secondary Memory / Non Volatile Memory.

1. Primary Memory / Volatile Memory:

Primary Memory also called as volatile memory because the memory can’t store the data permanently.
Primary memory select any part of memory when user want to save the data in memory but that may not
be store permanently on that location. It also has another name i.e. RAM.

Random Access Memory (RAM):

The primary storage is referred to as random access memory (RAM) due to the random selection of
memory locations. It performs both read and write operations on memory. If power failures happened in
systems during memory access then you will lose your data permanently. So, RAM is volatile memory.
RAM categorized into following types.

 DRAM
 SRAM
 DRDRAM
2. Secondary Memory / Non Volatile Memory:

Secondary memory is external and permanent memory that is useful to store the external storage media
such as floppy disk, magnetic disks, magnetic tapes and etc cache devices. Secondary memory deals with
following types of components.

Read Only Memory (ROM) :

ROM is permanent memory locations that offer huge types of standards to save data. But it work with
read only operation. No data lose happen whenever power failure occur during the ROM memory work in
computers.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

ROM memory has several models such names are following.

1. PROM: Programmable Read Only Memory (PROM) maintains large storage media but can’t offer the
erase features in ROM. This type of RO maintains PROM chips to write data once and read many. The
programs or instructions designed in PROM can’t be erased by other programs.

2. EPROM : Erasable Programmable Read Only Memory designed for recover the problems of PROM
and ROM. Users can delete the data of EPROM thorough pass on ultraviolet light and it erases chip is
reprogrammed.

3. EEPROM: Electrically Erasable Programmable Read Only Memory similar to the EPROM but it uses
electrical beam for erase the data of ROM.

Cache Memory: Main memory less than the access time of CPU so, the performance will decrease
through less access time. Speed mismatch will decrease through maintain cache memory. Main memory
can store huge amount of data but the cache memory normally kept small and low expensive cost. All
types of external media like Magnetic disks, Magnetic drives and etc store in cache memory to provide
quick access tools to the users.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

Lecture-45

SRAM memory cell

An SRAM cell has three different states: standby (the circuit is idle), reading (the data has been
requested) or writing (updating the contents). SRAM operating in read mode and write modes should
have "readability" and "write stability", respectively.
If the word line is not asserted, the access transistors M5 and M6 disconnect the cell from the bit lines.
The two cross-coupled inverters formed by M1 – M4 will continue to reinforce each other as long as they
are connected to the supply.
Read Operation
In theory, reading only requires asserting the word line WL and reading the SRAM cell state by a single
access transistor and bit line, e.g. M6, BL. However, bit lines are relatively long and have large parasitic
capacitance. To speed up reading, a more complex process is used in practice: The read cycle is started by
precharging both bit lines BL and BL, to high (logic 1) voltage. Then asserting the word line WL enables
both the access transistors M5 and M6, which causes one bit line BL voltage to slightly drop. Then the
BL and BL lines will have a small voltage difference between them. A sense amplifier will sense which
line has the higher voltage and thus determine whether there was 1 or 0 stored. The higher the sensitivity
of the sense amplifier, the faster the read operation. As the NMOS is more powerful, the pull-down is
easier. Therefore, bit lines are traditionally precharged to high voltage.
Many researchers are also trying to precharge at a slightly low voltage to reduce the power consumption.

1T DRAM cell
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

Write Operation
The write cycle begins by applying the value to be written to the bit lines. If we wish to write a 0, we
would apply a 0 to the bit lines, i.e. setting BL to 1 and BL to 0. This is similar to applying a reset pulse
to an SR-latch, which causes the flip flop to change state. A 1 is written by inverting the values of the bit
lines. WL is then asserted and the value that is to be stored is latched in. This works because the bit line
input-drivers are designed to be much stronger than the relatively weak transistors in the cell itself so they
can easily override the previous state of the cross-coupled inverters. In practice, access NMOS transistors
M5 and M6 have to be stronger than either bottom NMOS (M1, M3) or top PMOS (M2, M4) transistors.
This is easily obtained as PMOS transistors are much weaker than NMOS when same sized.
Consequently, when one transistor pair (e.g. M3 and M4) is only slightly overridden by the write process,
the opposite transistors pair (M1 and M2) gate voltage is also changed. This means that the M1 and
M2 transistors can be easier overridden, and so on. Thus, cross-coupled inverters magnify the writing
process.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

Lecture-46

DRAM memory cell

1T DRAM cell

Write Operation of 1T DRAM cell

• The "data write" operation on the 1-T cell is quite straightforward.
• For the write "1“ operation, the bit line (D) is raised to logic " 1 " by the write circuitry, while the
selected word line is pulled high by the row address decoder.
• The access transistor Ml turns on, allowing the storage cap. C1 to charge up to a logic-1 level.
• For the write “0“ operation, the bit line (D) is pulled to logic “0" and the word line is pulled high
by the row address decoder.
• In this case, the storage capacitor C discharges through the access transistor, resulting in a stored
“0" bit.
Read Operation of 1T DRAM cell
• For reading of stored data from 1-T DRAM cell, a elaborative read-refresh circuit is required due
to the fact that the "data read" operation need a "destructive readout”. It means that the stored
data must be destroyed or lost during the read operation.
• Typically, the read operation starts with pre-charging the column capacitance C2.
• Then, the word line is pulled high in order to activate the access transistor Ml.
• Charge sharing between C1 and C2 occurs and, depending on the amount of stored charge on C1,
the column voltage either increases or decreases slightly. It destroys the stored charge on C1. SO,
we also have to refresh data every time for each "data read" operation.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in

3 T DRAM cell
 A 3T DRAM cell has a higher density than a SRAM cell; moreover in a 3T DRAM, there is no
constraint on device ratios and the read operation is non destructive.
 In this cell, the storage capacitance is the gate capacitance of the readout device, so making this
scheme attractive for embedded memory applications; however, a 3T DRAM shows still limited
performance and low retention time to severely limit its use in advanced integrated circuits. 3T
DRAM utilizes gate of the transistor and a capacitance to store the data value.
 When data is to be written, write signal is enabled and the data from the bit line is fed into the cell.
When data is to be read from the cell, read line is enabled and data is read through the bit line. 3T
DRAM cell occupies less area compared to the 4T DRAM cell.
Swami Keshvanand Institute of Technology, Management &Gramothan,
Ramnagaria, Jagatpura, Jaipur-302017, INDIA
Approved by AICTE, Ministry of HRD, Government of India
Recognized by UGC under Section 2(f) of the UGC Act, 1956
Tel.: +91-0141- 5160400Fax: +91-0141-2759555
E-mail: [email protected] Web: www.skit.ac.in


 The 3T1D cell in fig. shows the scheme of the basic cell. The basis of the storage system is the
charge placed in node S, written from BL write line when T1 is activated.
 Consequently, it has a DRAM cell nature, but it allows a non-destructive read process (a clear
advantage over 1T1C memories) and high performance read and writes operation, comparable to
6T.With T1 and T3 transistors as accessing devices, the whole cell is composed by four transistors
of similar size to the corresponding of 6T.
 This implies a more compact cell structure. In order to write the cell at the BL write line level it is
only required to activate T1 through the WL write line. Hence, the S node stores either a 0 or
a VDD−Vth voltage depending on the logic value.
 This voltage results in the accumulation of charge at the gate of devices D1 and T2. A key aspect
of the 3T1D memory cell is that the capacitance of the gated diode (D1) when VGS is
above VTH is significantly higher with respect to lower voltages, because there is a substantial
amount of charge stored in the inversion layer.
 In order to read the cell, the read bit line BL read has to be previously pre-charged at VDD level.
Then T3 is activated from WL read line. If a high (1) level is stored in S, transistor T2 turns on
and discharges the bit line. If a low (0) level is stored in S, transistor T2 does not reach enough
conduction level.
 The objective of the gated diode D1 is to improve Read Access Time. When a high (1) level is
stored in S, D1 connected to WL read line causes a boosting effect of the voltage level in node S.
The voltage level reached at node S is close to VDD voltage causing a fast discharge of the
parasitic capacitance in BL read. If allow (0) level is stored, transistor T2 keeps turned off.

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